1 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s 2 // RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s 3 // RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s 4 5 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp-simd -x c -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s 6 // RUN: %clang_cc1 -fopenmp-simd -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s 7 // RUN: %clang_cc1 -fopenmp-simd -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s 8 // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} 9 // expected-no-diagnostics 10 #ifndef HEADER 11 #define HEADER 12 13 _Bool bv, bx; 14 char cv, cx; 15 unsigned char ucv, ucx; 16 short sv, sx; 17 unsigned short usv, usx; 18 int iv, ix; 19 unsigned int uiv, uix; 20 long lv, lx; 21 unsigned long ulv, ulx; 22 long long llv, llx; 23 unsigned long long ullv, ullx; 24 float fv, fx; 25 double dv, dx; 26 long double ldv, ldx; 27 _Complex int civ, cix; 28 _Complex float cfv, cfx; 29 _Complex double cdv, cdx; 30 char *cpx; 31 32 typedef int int4 __attribute__((__vector_size__(16))); 33 int4 int4x; 34 35 struct BitFields { 36 int : 32; 37 int a : 31; 38 } bfx; 39 40 struct BitFields_packed { 41 int : 32; 42 int a : 31; 43 } __attribute__ ((__packed__)) bfx_packed; 44 45 struct BitFields2 { 46 int : 31; 47 int a : 1; 48 } bfx2; 49 50 struct BitFields2_packed { 51 int : 31; 52 int a : 1; 53 } __attribute__ ((__packed__)) bfx2_packed; 54 55 struct BitFields3 { 56 int : 11; 57 int a : 14; 58 } bfx3; 59 60 struct BitFields3_packed { 61 int : 11; 62 int a : 14; 63 } __attribute__ ((__packed__)) bfx3_packed; 64 65 struct BitFields4 { 66 short : 16; 67 int a: 1; 68 long b : 7; 69 } bfx4; 70 71 struct BitFields4_packed { 72 short : 16; 73 int a: 1; 74 long b : 7; 75 } __attribute__ ((__packed__)) bfx4_packed; 76 77 typedef float float2 __attribute__((ext_vector_type(2))); 78 float2 float2x; 79 80 // Register "0" is currently an invalid register for global register variables. 81 // Use "esp" instead of "0". 82 // register int rix __asm__("0"); 83 register int rix __asm__("esp"); 84 85 int main(void) { 86 // CHECK: atomicrmw fadd ptr @{{.+}}, double 1.000000e+00 monotonic, align 8 87 #pragma omp atomic 88 ++dv; 89 // CHECK: atomicrmw add ptr @{{.+}}, i8 1 monotonic, align 1 90 #pragma omp atomic 91 bx++; 92 // CHECK: atomicrmw add ptr @{{.+}}, i8 1 monotonic, align 1 93 #pragma omp atomic update 94 ++cx; 95 // CHECK: atomicrmw sub ptr @{{.+}}, i8 1 monotonic, align 1 96 #pragma omp atomic 97 ucx--; 98 // CHECK: atomicrmw sub ptr @{{.+}}, i16 1 monotonic, align 2 99 #pragma omp atomic update 100 --sx; 101 // CHECK: [[USV:%.+]] = load i16, ptr @{{.+}}, 102 // CHECK: [[EXPR:%.+]] = zext i16 [[USV]] to i32 103 // CHECK: [[X:%.+]] = load atomic i16, ptr [[X_ADDR:@.+]] monotonic, align 2 104 // CHECK: br label %[[CONT:.+]] 105 // CHECK: [[CONT]] 106 // CHECK: [[EXPECTED:%.+]] = phi i16 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ] 107 // CHECK: [[CONV:%.+]] = zext i16 [[EXPECTED]] to i32 108 // CHECK: [[ADD:%.+]] = add nsw i32 [[CONV]], [[EXPR]] 109 // CHECK: [[DESIRED:%.+]] = trunc i32 [[ADD]] to i16 110 // CHECK: store i16 [[DESIRED]], ptr [[TEMP:%.+]], 111 // CHECK: [[DESIRED:%.+]] = load i16, ptr [[TEMP]], 112 // CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i16 [[EXPECTED]], i16 [[DESIRED]] monotonic monotonic, align 2 113 // CHECK: [[OLD_X]] = extractvalue { i16, i1 } [[RES]], 0 114 // CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i16, i1 } [[RES]], 1 115 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 116 // CHECK: [[EXIT]] 117 #pragma omp atomic 118 usx += usv; 119 // CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}}, 120 // CHECK: [[X:%.+]] = load atomic i32, ptr [[X_ADDR:@.+]] monotonic, align 4 121 // CHECK: br label %[[CONT:.+]] 122 // CHECK: [[CONT]] 123 // CHECK: [[EXPECTED:%.+]] = phi i32 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ] 124 // CHECK: [[DESIRED:%.+]] = mul nsw i32 [[EXPECTED]], [[EXPR]] 125 // CHECK: store i32 [[DESIRED]], ptr [[TEMP:%.+]], 126 // CHECK: [[DESIRED:%.+]] = load i32, ptr [[TEMP]], 127 // CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i32 [[EXPECTED]], i32 [[DESIRED]] monotonic monotonic, align 4 128 // CHECK: [[OLD_X]] = extractvalue { i32, i1 } [[RES]], 0 129 // CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i32, i1 } [[RES]], 1 130 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 131 // CHECK: [[EXIT]] 132 #pragma omp atomic update 133 ix *= iv; 134 // CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}}, 135 // CHECK: atomicrmw sub ptr @{{.+}}, i32 [[EXPR]] monotonic, align 4 136 #pragma omp atomic 137 uix -= uiv; 138 // CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}}, 139 // CHECK: [[X:%.+]] = load atomic i32, ptr [[X_ADDR:@.+]] monotonic, align 4 140 // CHECK: br label %[[CONT:.+]] 141 // CHECK: [[CONT]] 142 // CHECK: [[EXPECTED:%.+]] = phi i32 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ] 143 // CHECK: [[DESIRED:%.+]] = shl i32 [[EXPECTED]], [[EXPR]] 144 // CHECK: store i32 [[DESIRED]], ptr [[TEMP:%.+]], 145 // CHECK: [[DESIRED:%.+]] = load i32, ptr [[TEMP]], 146 // CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i32 [[EXPECTED]], i32 [[DESIRED]] monotonic monotonic, align 4 147 // CHECK: [[OLD_X]] = extractvalue { i32, i1 } [[RES]], 0 148 // CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i32, i1 } [[RES]], 1 149 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 150 // CHECK: [[EXIT]] 151 #pragma omp atomic update 152 ix <<= iv; 153 // CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}}, 154 // CHECK: [[X:%.+]] = load atomic i32, ptr [[X_ADDR:@.+]] monotonic, align 4 155 // CHECK: br label %[[CONT:.+]] 156 // CHECK: [[CONT]] 157 // CHECK: [[EXPECTED:%.+]] = phi i32 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ] 158 // CHECK: [[DESIRED:%.+]] = lshr i32 [[EXPECTED]], [[EXPR]] 159 // CHECK: store i32 [[DESIRED]], ptr [[TEMP:%.+]], 160 // CHECK: [[DESIRED:%.+]] = load i32, ptr [[TEMP]], 161 // CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i32 [[EXPECTED]], i32 [[DESIRED]] monotonic monotonic, align 4 162 // CHECK: [[OLD_X]] = extractvalue { i32, i1 } [[RES]], 0 163 // CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i32, i1 } [[RES]], 1 164 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 165 // CHECK: [[EXIT]] 166 #pragma omp atomic 167 uix >>= uiv; 168 // CHECK: [[EXPR:%.+]] = load i64, ptr @{{.+}}, 169 // CHECK: [[X:%.+]] = load atomic i64, ptr [[X_ADDR:@.+]] monotonic, align 8 170 // CHECK: br label %[[CONT:.+]] 171 // CHECK: [[CONT]] 172 // CHECK: [[EXPECTED:%.+]] = phi i64 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ] 173 // CHECK: [[DESIRED:%.+]] = sdiv i64 [[EXPECTED]], [[EXPR]] 174 // CHECK: store i64 [[DESIRED]], ptr [[TEMP:%.+]], 175 // CHECK: [[DESIRED:%.+]] = load i64, ptr [[TEMP]], 176 // CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i64 [[EXPECTED]], i64 [[DESIRED]] monotonic monotonic, align 8 177 // CHECK: [[OLD_X]] = extractvalue { i64, i1 } [[RES]], 0 178 // CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i64, i1 } [[RES]], 1 179 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 180 // CHECK: [[EXIT]] 181 #pragma omp atomic update 182 lx /= lv; 183 // CHECK: [[EXPR:%.+]] = load i64, ptr @{{.+}}, 184 // CHECK: atomicrmw and ptr @{{.+}}, i64 [[EXPR]] monotonic, align 8 185 #pragma omp atomic 186 ulx &= ulv; 187 // CHECK: [[EXPR:%.+]] = load i64, ptr @{{.+}}, 188 // CHECK: atomicrmw xor ptr @{{.+}}, i64 [[EXPR]] monotonic, align 8 189 #pragma omp atomic update 190 llx ^= llv; 191 // CHECK: [[EXPR:%.+]] = load i64, ptr @{{.+}}, 192 // CHECK: atomicrmw or ptr @{{.+}}, i64 [[EXPR]] monotonic, align 8 193 #pragma omp atomic 194 ullx |= ullv; 195 // CHECK: [[EXPR:%.+]] = load float, ptr @{{.+}}, 196 // CHECK: atomicrmw fadd ptr @{{.+}}, float [[EXPR]] monotonic, align 4 197 #pragma omp atomic update 198 fx = fx + fv; 199 // CHECK: [[EXPR:%.+]] = load double, ptr @{{.+}}, 200 // CHECK: [[OLD:%.+]] = load atomic i64, ptr [[X_ADDR:@.+]] monotonic, align 8 201 // CHECK: br label %[[CONT:.+]] 202 // CHECK: [[CONT]] 203 // CHECK: [[EXPECTED:%.+]] = phi i64 [ [[OLD]], %{{.+}} ], [ [[PREV:%.+]], %[[CONT]] ] 204 // CHECK: [[OLD:%.+]] = bitcast i64 [[EXPECTED]] to double 205 // CHECK: [[SUB:%.+]] = fsub double [[EXPR]], [[OLD]] 206 // CHECK: store double [[SUB]], ptr [[TEMP:%.+]], 207 // CHECK: [[DESIRED:%.+]] = load i64, ptr [[TEMP]], 208 // CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i64 [[EXPECTED]], i64 [[DESIRED]] monotonic monotonic, align 8 209 // CHECK: [[PREV:%.+]] = extractvalue { i64, i1 } [[RES]], 0 210 // CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i64, i1 } [[RES]], 1 211 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 212 // CHECK: [[EXIT]] 213 #pragma omp atomic 214 dx = dv - dx; 215 // CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}, 216 // CHECK: [[OLD:%.+]] = load atomic i128, ptr [[X_ADDR:@.+]] monotonic, align 16 217 // CHECK: br label %[[CONT:.+]] 218 // CHECK: [[CONT]] 219 // CHECK: [[EXPECTED:%.+]] = phi i128 [ [[OLD]], %{{.+}} ], [ [[PREV:%.+]], %[[CONT]] ] 220 // CHECK: store i128 [[EXPECTED]], ptr [[TEMP:%.+]], 221 // CHECK: store i128 [[EXPECTED]], ptr [[TEMP1:%.+]], 222 // CHECK: [[OLD:%.+]] = load x86_fp80, ptr [[TEMP1]] 223 // CHECK: [[MUL:%.+]] = fmul x86_fp80 [[OLD]], [[EXPR]] 224 // CHECK: store x86_fp80 [[MUL]], ptr [[TEMP]] 225 // CHECK: [[DESIRED:%.+]] = load i128, ptr [[TEMP]] 226 // CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i128 [[EXPECTED]], i128 [[DESIRED]] monotonic monotonic, align 16 227 // CHECK: [[PREV:%.+]] = extractvalue { i128, i1 } [[RES]], 0 228 // CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i128, i1 } [[RES]], 1 229 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 230 // CHECK: [[EXIT]] 231 #pragma omp atomic update 232 ldx = ldx * ldv; 233 // CHECK: [[EXPR_RE:%.+]] = load i32, ptr @{{.+}} 234 // CHECK: [[EXPR_IM:%.+]] = load i32, ptr getelementptr inbounds nuw ({ i32, i32 }, ptr @{{.+}}, i32 0, i32 1) 235 // CHECK: call void @__atomic_load(i64 noundef 8, ptr noundef [[X_ADDR:@.+]], ptr noundef [[EXPECTED_ADDR:%.+]], i32 noundef 0) 236 // CHECK: br label %[[CONT:.+]] 237 // CHECK: [[CONT]] 238 // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 0 239 // CHECK: [[X_RE:%.+]] = load i32, ptr [[X_RE_ADDR]] 240 // CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 1 241 // CHECK: [[X_IM:%.+]] = load i32, ptr [[X_IM_ADDR]] 242 // <Skip checks for complex calculations> 243 // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR:%.+]], i32 0, i32 0 244 // CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR]], i32 0, i32 1 245 // CHECK: store i32 %{{.+}}, ptr [[X_RE_ADDR]] 246 // CHECK: store i32 %{{.+}}, ptr [[X_IM_ADDR]] 247 // CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, ptr noundef [[X_ADDR]], ptr noundef [[EXPECTED_ADDR]], ptr noundef [[DESIRED_ADDR]], i32 noundef 0, i32 noundef 0) 248 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 249 // CHECK: [[EXIT]] 250 #pragma omp atomic 251 cix = civ / cix; 252 // CHECK: [[EXPR_RE:%.+]] = load float, ptr @{{.+}} 253 // CHECK: [[EXPR_IM:%.+]] = load float, ptr getelementptr inbounds nuw ({ float, float }, ptr @{{.+}}, i32 0, i32 1) 254 // CHECK: call void @__atomic_load(i64 noundef 8, ptr noundef [[X_ADDR:@.+]], ptr noundef [[EXPECTED_ADDR:%.+]], i32 noundef 0) 255 // CHECK: br label %[[CONT:.+]] 256 // CHECK: [[CONT]] 257 // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { float, float }, ptr [[EXPECTED_ADDR]], i32 0, i32 0 258 // CHECK: [[X_RE:%.+]] = load float, ptr [[X_RE_ADDR]] 259 // CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { float, float }, ptr [[EXPECTED_ADDR]], i32 0, i32 1 260 // CHECK: [[X_IM:%.+]] = load float, ptr [[X_IM_ADDR]] 261 // <Skip checks for complex calculations> 262 // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { float, float }, ptr [[DESIRED_ADDR:%.+]], i32 0, i32 0 263 // CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { float, float }, ptr [[DESIRED_ADDR]], i32 0, i32 1 264 // CHECK: store float %{{.+}}, ptr [[X_RE_ADDR]] 265 // CHECK: store float %{{.+}}, ptr [[X_IM_ADDR]] 266 // CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, ptr noundef [[X_ADDR]], ptr noundef [[EXPECTED_ADDR]], ptr noundef [[DESIRED_ADDR]], i32 noundef 0, i32 noundef 0) 267 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 268 // CHECK: [[EXIT]] 269 #pragma omp atomic update 270 cfx = cfv + cfx; 271 // CHECK: [[EXPR_RE:%.+]] = load double, ptr @{{.+}} 272 // CHECK: [[EXPR_IM:%.+]] = load double, ptr getelementptr inbounds nuw ({ double, double }, ptr @{{.+}}, i32 0, i32 1) 273 // CHECK: call void @__atomic_load(i64 noundef 16, ptr noundef [[X_ADDR:@.+]], ptr noundef [[EXPECTED_ADDR:%.+]], i32 noundef 5) 274 // CHECK: br label %[[CONT:.+]] 275 // CHECK: [[CONT]] 276 // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { double, double }, ptr [[EXPECTED_ADDR]], i32 0, i32 0 277 // CHECK: [[X_RE:%.+]] = load double, ptr [[X_RE_ADDR]] 278 // CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { double, double }, ptr [[EXPECTED_ADDR]], i32 0, i32 1 279 // CHECK: [[X_IM:%.+]] = load double, ptr [[X_IM_ADDR]] 280 // <Skip checks for complex calculations> 281 // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { double, double }, ptr [[DESIRED_ADDR:%.+]], i32 0, i32 0 282 // CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { double, double }, ptr [[DESIRED_ADDR]], i32 0, i32 1 283 // CHECK: store double %{{.+}}, ptr [[X_RE_ADDR]] 284 // CHECK: store double %{{.+}}, ptr [[X_IM_ADDR]] 285 // CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 16, ptr noundef [[X_ADDR]], ptr noundef [[EXPECTED_ADDR]], ptr noundef [[DESIRED_ADDR]], i32 noundef 5, i32 noundef 5) 286 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 287 // CHECK: [[EXIT]] 288 // CHECK: call{{.*}} @__kmpc_flush( 289 #pragma omp atomic seq_cst 290 cdx = cdx - cdv; 291 // CHECK: [[BV:%.+]] = load i8, ptr @{{.+}} 292 // CHECK: [[BOOL:%.+]] = trunc i8 [[BV]] to i1 293 // CHECK: [[EXPR:%.+]] = zext i1 [[BOOL]] to i64 294 // CHECK: atomicrmw and ptr @{{.+}}, i64 [[EXPR]] monotonic, align 8 295 #pragma omp atomic update 296 ulx = ulx & bv; 297 // CHECK: [[CV:%.+]] = load i8, ptr @{{.+}}, align 1 298 // CHECK: [[EXPR:%.+]] = sext i8 [[CV]] to i32 299 // CHECK: [[BX:%.+]] = load atomic i8, ptr [[BX_ADDR:@.+]] monotonic, align 1 300 // CHECK: br label %[[CONT:.+]] 301 // CHECK: [[CONT]] 302 // CHECK: [[EXPECTED:%.+]] = phi i8 [ [[BX]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ] 303 // CHECK: [[OLD:%.+]] = trunc i8 [[EXPECTED]] to i1 304 // CHECK: [[X_RVAL:%.+]] = zext i1 [[OLD]] to i32 305 // CHECK: [[AND:%.+]] = and i32 [[EXPR]], [[X_RVAL]] 306 // CHECK: [[CAST:%.+]] = icmp ne i32 [[AND]], 0 307 // CHECK: [[DESIRED:%.+]] = zext i1 [[CAST]] to i8 308 // CHECK: store i8 [[DESIRED]], ptr [[TEMP:%.+]], 309 // CHECK: [[DESIRED:%.+]] = load i8, ptr [[TEMP]], 310 // CHECK: [[RES:%.+]] = cmpxchg ptr [[BX_ADDR]], i8 [[EXPECTED]], i8 [[DESIRED]] monotonic monotonic, align 1 311 // CHECK: [[OLD_X:%.+]] = extractvalue { i8, i1 } [[RES]], 0 312 // CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i8, i1 } [[RES]], 1 313 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 314 // CHECK: [[EXIT]] 315 #pragma omp atomic 316 bx = cv & bx; 317 // CHECK: [[UCV:%.+]] = load i8, ptr @{{.+}}, 318 // CHECK: [[EXPR:%.+]] = zext i8 [[UCV]] to i32 319 // CHECK: [[X:%.+]] = load atomic i8, ptr [[CX_ADDR:@.+]] seq_cst, align 1 320 // CHECK: br label %[[CONT:.+]] 321 // CHECK: [[CONT]] 322 // CHECK: [[EXPECTED:%.+]] = phi i8 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ] 323 // CHECK: [[X_RVAL:%.+]] = sext i8 [[EXPECTED]] to i32 324 // CHECK: [[ASHR:%.+]] = ashr i32 [[X_RVAL]], [[EXPR]] 325 // CHECK: [[DESIRED:%.+]] = trunc i32 [[ASHR]] to i8 326 // CHECK: store i8 [[DESIRED]], ptr [[TEMP:%.+]], 327 // CHECK: [[DESIRED:%.+]] = load i8, ptr [[TEMP]], 328 // CHECK: [[RES:%.+]] = cmpxchg ptr [[CX_ADDR]], i8 [[EXPECTED]], i8 [[DESIRED]] seq_cst seq_cst, align 1 329 // CHECK: [[OLD_X:%.+]] = extractvalue { i8, i1 } [[RES]], 0 330 // CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i8, i1 } [[RES]], 1 331 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 332 // CHECK: [[EXIT]] 333 // CHECK: call{{.*}} @__kmpc_flush( 334 #pragma omp atomic update, seq_cst 335 cx = cx >> ucv; 336 // CHECK: [[SV:%.+]] = load i16, ptr @{{.+}}, 337 // CHECK: [[EXPR:%.+]] = sext i16 [[SV]] to i32 338 // CHECK: [[X:%.+]] = load atomic i64, ptr [[ULX_ADDR:@.+]] monotonic, align 8 339 // CHECK: br label %[[CONT:.+]] 340 // CHECK: [[CONT]] 341 // CHECK: [[EXPECTED:%.+]] = phi i64 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ] 342 // CHECK: [[X_RVAL:%.+]] = trunc i64 [[EXPECTED]] to i32 343 // CHECK: [[SHL:%.+]] = shl i32 [[EXPR]], [[X_RVAL]] 344 // CHECK: [[DESIRED:%.+]] = sext i32 [[SHL]] to i64 345 // CHECK: store i64 [[DESIRED]], ptr [[TEMP:%.+]], 346 // CHECK: [[DESIRED:%.+]] = load i64, ptr [[TEMP]], 347 // CHECK: [[RES:%.+]] = cmpxchg ptr [[ULX_ADDR]], i64 [[EXPECTED]], i64 [[DESIRED]] monotonic monotonic, align 8 348 // CHECK: [[OLD_X:%.+]] = extractvalue { i64, i1 } [[RES]], 0 349 // CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i64, i1 } [[RES]], 1 350 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 351 // CHECK: [[EXIT]] 352 #pragma omp atomic update 353 ulx = sv << ulx; 354 // CHECK: [[USV:%.+]] = load i16, ptr @{{.+}}, 355 // CHECK: [[EXPR:%.+]] = zext i16 [[USV]] to i64 356 // CHECK: [[X:%.+]] = load atomic i64, ptr [[LX_ADDR:@.+]] monotonic, align 8 357 // CHECK: br label %[[CONT:.+]] 358 // CHECK: [[CONT]] 359 // CHECK: [[EXPECTED:%.+]] = phi i64 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ] 360 // CHECK: [[DESIRED:%.+]] = srem i64 [[EXPECTED]], [[EXPR]] 361 // CHECK: store i64 [[DESIRED]], ptr [[TEMP:%.+]], 362 // CHECK: [[DESIRED:%.+]] = load i64, ptr [[TEMP]], 363 // CHECK: [[RES:%.+]] = cmpxchg ptr [[LX_ADDR]], i64 [[EXPECTED]], i64 [[DESIRED]] monotonic monotonic, align 8 364 // CHECK: [[OLD_X:%.+]] = extractvalue { i64, i1 } [[RES]], 0 365 // CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i64, i1 } [[RES]], 1 366 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 367 // CHECK: [[EXIT]] 368 #pragma omp atomic 369 lx = lx % usv; 370 // CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}} 371 // CHECK: atomicrmw or ptr @{{.+}}, i32 [[EXPR]] seq_cst, align 4 372 // CHECK: call{{.*}} @__kmpc_flush( 373 #pragma omp atomic seq_cst, update 374 uix = iv | uix; 375 // CHECK: [[EXPR:%.+]] = load i32, ptr @{{.+}} 376 // CHECK: atomicrmw and ptr @{{.+}}, i32 [[EXPR]] monotonic, align 4 377 #pragma omp atomic 378 ix = ix & uiv; 379 // CHECK: [[EXPR:%.+]] = load i64, ptr @{{.+}}, 380 // CHECK: call void @__atomic_load(i64 noundef 8, ptr noundef [[X_ADDR:@.+]], ptr noundef [[EXPECTED_ADDR:%.+]], i32 noundef 0) 381 // CHECK: br label %[[CONT:.+]] 382 // CHECK: [[CONT]] 383 // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 0 384 // CHECK: [[X_RE:%.+]] = load i32, ptr [[X_RE_ADDR]] 385 // CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 1 386 // CHECK: [[X_IM:%.+]] = load i32, ptr [[X_IM_ADDR]] 387 // <Skip checks for complex calculations> 388 // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR:%.+]], i32 0, i32 0 389 // CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR]], i32 0, i32 1 390 // CHECK: store i32 %{{.+}}, ptr [[X_RE_ADDR]] 391 // CHECK: store i32 %{{.+}}, ptr [[X_IM_ADDR]] 392 // CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, ptr noundef [[X_ADDR]], ptr noundef [[EXPECTED_ADDR]], ptr noundef [[DESIRED_ADDR]], i32 noundef 0, i32 noundef 0) 393 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 394 // CHECK: [[EXIT]] 395 #pragma omp atomic update 396 cix = lv + cix; 397 // CHECK: [[ULV:%.+]] = load i64, ptr @{{.+}}, 398 // CHECK: [[EXPR:%.+]] = uitofp i64 [[ULV]] to float 399 // CHECK: [[OLD:%.+]] = load atomic i32, ptr [[X_ADDR:@.+]] monotonic, align 4 400 // CHECK: br label %[[CONT:.+]] 401 // CHECK: [[CONT]] 402 // CHECK: [[EXPECTED:%.+]] = phi i32 [ [[OLD]], %{{.+}} ], [ [[PREV:%.+]], %[[CONT]] ] 403 // CHECK: [[OLD:%.+]] = bitcast i32 [[EXPECTED]] to float 404 // CHECK: [[MUL:%.+]] = fmul float [[OLD]], [[EXPR]] 405 // CHECK: store float [[MUL]], ptr [[TEMP:%.+]], 406 // CHECK: [[DESIRED:%.+]] = load i32, ptr [[TEMP]], 407 // CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i32 [[EXPECTED]], i32 [[DESIRED]] monotonic monotonic, align 4 408 // CHECK: [[PREV:%.+]] = extractvalue { i32, i1 } [[RES]], 0 409 // CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i32, i1 } [[RES]], 1 410 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 411 // CHECK: [[EXIT]] 412 #pragma omp atomic 413 fx = fx * ulv; 414 // CHECK: [[LLV:%.+]] = load i64, ptr @{{.+}}, 415 // CHECK: [[EXPR:%.+]] = sitofp i64 [[LLV]] to double 416 // CHECK: [[OLD:%.+]] = load atomic i64, ptr [[X_ADDR:@.+]] monotonic, align 8 417 // CHECK: br label %[[CONT:.+]] 418 // CHECK: [[CONT]] 419 // CHECK: [[EXPECTED:%.+]] = phi i64 [ [[OLD]], %{{.+}} ], [ [[PREV:%.+]], %[[CONT]] ] 420 // CHECK: [[OLD:%.+]] = bitcast i64 [[EXPECTED]] to double 421 // CHECK: [[DIV:%.+]] = fdiv double [[OLD]], [[EXPR]] 422 // CHECK: store double [[DIV]], ptr [[TEMP:%.+]], 423 // CHECK: [[DESIRED:%.+]] = load i64, ptr [[TEMP]], 424 // CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i64 [[EXPECTED]], i64 [[DESIRED]] monotonic monotonic, align 8 425 // CHECK: [[PREV:%.+]] = extractvalue { i64, i1 } [[RES]], 0 426 // CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i64, i1 } [[RES]], 1 427 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 428 // CHECK: [[EXIT]] 429 #pragma omp atomic update 430 dx /= llv; 431 // CHECK: [[ULLV:%.+]] = load i64, ptr @{{.+}}, 432 // CHECK: [[EXPR:%.+]] = uitofp i64 [[ULLV]] to x86_fp80 433 // CHECK: [[OLD:%.+]] = load atomic i128, ptr [[X_ADDR:@.+]] monotonic, align 16 434 // CHECK: br label %[[CONT:.+]] 435 // CHECK: [[CONT]] 436 // CHECK: [[EXPECTED:%.+]] = phi i128 [ [[OLD]], %{{.+}} ], [ [[PREV:%.+]], %[[CONT]] ] 437 // CHECK: store i128 [[EXPECTED]], ptr [[TEMP1:%.+]] 438 // CHECK: [[OLD:%.+]] = load x86_fp80, ptr [[TEMP:%.+]] 439 // CHECK: [[SUB:%.+]] = fsub x86_fp80 [[OLD]], [[EXPR]] 440 // CHECK: store x86_fp80 [[SUB]], ptr [[TEMP1]] 441 // CHECK: [[DESIRED:%.+]] = load i128, ptr [[TEMP1]] 442 // CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i128 [[EXPECTED]], i128 [[DESIRED]] monotonic monotonic, align 16 443 // CHECK: [[PREV:%.+]] = extractvalue { i128, i1 } [[RES]], 0 444 // CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i128, i1 } [[RES]], 1 445 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 446 // CHECK: [[EXIT]] 447 #pragma omp atomic 448 ldx -= ullv; 449 // CHECK: [[EXPR:%.+]] = load float, ptr @{{.+}}, 450 // CHECK: call void @__atomic_load(i64 noundef 8, ptr noundef [[X_ADDR:@.+]], ptr noundef [[EXPECTED_ADDR:%.+]], i32 noundef 0) 451 // CHECK: br label %[[CONT:.+]] 452 // CHECK: [[CONT]] 453 // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 0 454 // CHECK: [[X_RE:%.+]] = load i32, ptr [[X_RE_ADDR]] 455 // CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[EXPECTED_ADDR]], i32 0, i32 1 456 // CHECK: [[X_IM:%.+]] = load i32, ptr [[X_IM_ADDR]] 457 // <Skip checks for complex calculations> 458 // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR:%.+]], i32 0, i32 0 459 // CHECK: [[X_IM_ADDR:%.+]] = getelementptr inbounds nuw { i32, i32 }, ptr [[DESIRED_ADDR]], i32 0, i32 1 460 // CHECK: store i32 %{{.+}}, ptr [[X_RE_ADDR]] 461 // CHECK: store i32 %{{.+}}, ptr [[X_IM_ADDR]] 462 // CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, ptr noundef [[X_ADDR]], ptr noundef [[EXPECTED_ADDR]], ptr noundef [[DESIRED_ADDR]], i32 noundef 0, i32 noundef 0) 463 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 464 // CHECK: [[EXIT]] 465 #pragma omp atomic update 466 cix = fv / cix; 467 // CHECK: [[EXPR:%.+]] = load double, ptr @{{.+}}, 468 // CHECK: [[X:%.+]] = load atomic i16, ptr [[X_ADDR:@.+]] monotonic, align 2 469 // CHECK: br label %[[CONT:.+]] 470 // CHECK: [[CONT]] 471 // CHECK: [[EXPECTED:%.+]] = phi i16 [ [[X]], %{{.+}} ], [ [[OLD_X:%.+]], %[[CONT]] ] 472 // CHECK: [[CONV:%.+]] = sext i16 [[EXPECTED]] to i32 473 // CHECK: [[X_RVAL:%.+]] = sitofp i32 [[CONV]] to double 474 // CHECK: [[ADD:%.+]] = fadd double [[X_RVAL]], [[EXPR]] 475 // CHECK: [[DESIRED:%.+]] = fptosi double [[ADD]] to i16 476 // CHECK: store i16 [[DESIRED]], ptr [[TEMP:%.+]] 477 // CHECK: [[DESIRED:%.+]] = load i16, ptr [[TEMP]] 478 // CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i16 [[EXPECTED]], i16 [[DESIRED]] monotonic monotonic, align 2 479 // CHECK: [[OLD_X]] = extractvalue { i16, i1 } [[RES]], 0 480 // CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i16, i1 } [[RES]], 1 481 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 482 // CHECK: [[EXIT]] 483 #pragma omp atomic 484 sx = sx + dv; 485 // CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}}, 486 // CHECK: [[XI8:%.+]] = load atomic i8, ptr [[X_ADDR:@.+]] monotonic, align 1 487 // CHECK: br label %[[CONT:.+]] 488 // CHECK: [[CONT]] 489 // CHECK: [[EXPECTED:%.+]] = phi i8 [ [[XI8]], %{{.+}} ], [ [[OLD_XI8:%.+]], %[[CONT]] ] 490 // CHECK: [[BOOL_EXPECTED:%.+]] = trunc i8 [[EXPECTED]] to i1 491 // CHECK: [[CONV:%.+]] = zext i1 [[BOOL_EXPECTED]] to i32 492 // CHECK: [[X_RVAL:%.+]] = sitofp i32 [[CONV]] to x86_fp80 493 // CHECK: [[MUL:%.+]] = fmul x86_fp80 [[EXPR]], [[X_RVAL]] 494 // CHECK: [[BOOL_DESIRED:%.+]] = fcmp une x86_fp80 [[MUL]], 0xK00000000000000000000 495 // CHECK: [[DESIRED:%.+]] = zext i1 [[BOOL_DESIRED]] to i8 496 // CHECK: store i8 [[DESIRED]], ptr [[TEMP:%.+]] 497 // CHECK: [[DESIRED:%.+]] = load i8, ptr [[TEMP]] 498 // CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i8 [[EXPECTED]], i8 [[DESIRED]] release monotonic, align 1 499 // CHECK: [[OLD_XI8:%.+]] = extractvalue { i8, i1 } [[RES]], 0 500 // CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i8, i1 } [[RES]], 1 501 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 502 // CHECK: [[EXIT]] 503 // CHECK: call{{.*}} @__kmpc_flush( 504 #pragma omp atomic update release 505 bx = ldv * bx; 506 // CHECK: [[EXPR_RE:%.+]] = load i32, ptr [[CIV_ADDR:@.+]], 507 // CHECK: [[EXPR_IM:%.+]] = load i32, ptr getelementptr inbounds nuw ({ i32, i32 }, ptr [[CIV_ADDR]], i32 0, i32 1), 508 // CHECK: [[XI8:%.+]] = load atomic i8, ptr [[X_ADDR:@.+]] monotonic, align 1 509 // CHECK: br label %[[CONT:.+]] 510 // CHECK: [[CONT]] 511 // CHECK: [[EXPECTED:%.+]] = phi i8 [ [[XI8]], %{{.+}} ], [ [[OLD_XI8:%.+]], %[[CONT]] ] 512 // CHECK: [[BOOL_EXPECTED:%.+]] = trunc i8 [[EXPECTED]] to i1 513 // CHECK: [[X_RVAL:%.+]] = zext i1 [[BOOL_EXPECTED]] to i32 514 // CHECK: [[SUB_RE:%.+]] = sub i32 [[EXPR_RE:%.+]], [[X_RVAL]] 515 // CHECK: [[SUB_IM:%.+]] = sub i32 [[EXPR_IM:%.+]], 0 516 // CHECK: icmp ne i32 [[SUB_RE]], 0 517 // CHECK: icmp ne i32 [[SUB_IM]], 0 518 // CHECK: [[BOOL_DESIRED:%.+]] = or i1 519 // CHECK: [[DESIRED:%.+]] = zext i1 [[BOOL_DESIRED]] to i8 520 // CHECK: store i8 [[DESIRED]], ptr [[TEMP:%.+]] 521 // CHECK: [[DESIRED:%.+]] = load i8, ptr [[TEMP]] 522 // CHECK: [[RES:%.+]] = cmpxchg ptr [[X_ADDR]], i8 [[EXPECTED]], i8 [[DESIRED]] monotonic monotonic, align 1 523 // CHECK: [[OLD_XI8:%.+]] = extractvalue { i8, i1 } [[RES]], 0 524 // CHECK: [[SUCCESS_FAIL:%.+]] = extractvalue { i8, i1 } [[RES]], 1 525 // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] 526 // CHECK: [[EXIT]] 527 #pragma omp atomic 528 bx = civ - bx; 529 // CHECK: [[IDX:%.+]] = load i16, ptr @{{.+}} 530 // CHECK: load i8, ptr 531 // CHECK: [[VEC_ITEM_VAL:%.+]] = zext i1 %{{.+}} to i32 532 // CHECK: [[I128VAL:%.+]] = load atomic i128, ptr [[DEST:@.+]] monotonic, align 16 533 // CHECK: br label %[[CONT:.+]] 534 // CHECK: [[CONT]] 535 // CHECK: [[OLD_I128:%.+]] = phi i128 [ [[I128VAL]], %{{.+}} ], [ [[FAILED_I128_OLD_VAL:%.+]], %[[CONT]] ] 536 // CHECK: store i128 [[OLD_I128]], ptr [[TEMP:%.+]], 537 // CHECK: [[OLD_VEC_VAL:%.+]] = bitcast i128 [[OLD_I128]] to <4 x i32> 538 // CHECK: store <4 x i32> [[OLD_VEC_VAL]], ptr [[LDTEMP:%.+]], 539 // CHECK: [[VEC_VAL:%.+]] = load <4 x i32>, ptr [[LDTEMP]] 540 // CHECK: [[ITEM:%.+]] = extractelement <4 x i32> [[VEC_VAL]], i16 [[IDX]] 541 // CHECK: [[OR:%.+]] = or i32 [[ITEM]], [[VEC_ITEM_VAL]] 542 // CHECK: [[VEC_VAL:%.+]] = load <4 x i32>, ptr [[TEMP]] 543 // CHECK: [[NEW_VEC_VAL:%.+]] = insertelement <4 x i32> [[VEC_VAL]], i32 [[OR]], i16 [[IDX]] 544 // CHECK: store <4 x i32> [[NEW_VEC_VAL]], ptr [[TEMP]] 545 // CHECK: [[NEW_I128:%.+]] = load i128, ptr [[TEMP]] 546 // CHECK: [[RES:%.+]] = cmpxchg ptr [[DEST]], i128 [[OLD_I128]], i128 [[NEW_I128]] monotonic monotonic, align 16 547 // CHECK: [[FAILED_I128_OLD_VAL:%.+]] = extractvalue { i128, i1 } [[RES]], 0 548 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i128, i1 } [[RES]], 1 549 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] 550 // CHECK: [[EXIT]] 551 #pragma omp atomic update 552 int4x[sv] |= bv; 553 // CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}} 554 // CHECK: [[PREV_VALUE:%.+]] = load atomic i32, ptr getelementptr (i8, ptr @{{.+}}, i64 4) monotonic, align 4 555 // CHECK: br label %[[CONT:.+]] 556 // CHECK: [[CONT]] 557 // CHECK: [[OLD_BF_VALUE:%.+]] = phi i32 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ] 558 // CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP1:%.+]], 559 // CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP:%.+]], 560 // CHECK: [[A_LD:%.+]] = load i32, ptr [[TEMP]], 561 // CHECK: [[A_SHL:%.+]] = shl i32 [[A_LD]], 1 562 // CHECK: [[A_ASHR:%.+]] = ashr i32 [[A_SHL]], 1 563 // CHECK: [[X_RVAL:%.+]] = sitofp i32 [[A_ASHR]] to x86_fp80 564 // CHECK: [[SUB:%.+]] = fsub x86_fp80 [[X_RVAL]], [[EXPR]] 565 // CHECK: [[CONV:%.+]] = fptosi x86_fp80 [[SUB]] to i32 566 // CHECK: [[NEW_VAL:%.+]] = load i32, ptr [[TEMP1]], 567 // CHECK: [[BF_VALUE:%.+]] = and i32 [[CONV]], 2147483647 568 // CHECK: [[BF_CLEAR:%.+]] = and i32 [[NEW_VAL]], -2147483648 569 // CHECK: or i32 [[BF_CLEAR]], [[BF_VALUE]] 570 // CHECK: store i32 %{{.+}}, ptr [[TEMP1]] 571 // CHECK: [[NEW_BF_VALUE:%.+]] = load i32, ptr [[TEMP1]] 572 // CHECK: [[RES:%.+]] = cmpxchg ptr getelementptr (i8, ptr @{{.+}}, i64 4), i32 [[OLD_BF_VALUE]], i32 [[NEW_BF_VALUE]] monotonic monotonic, align 4 573 // CHECK: [[FAILED_OLD_VAL]] = extractvalue { i32, i1 } [[RES]], 0 574 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i32, i1 } [[RES]], 1 575 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] 576 // CHECK: [[EXIT]] 577 #pragma omp atomic 578 bfx.a = bfx.a - ldv; 579 // CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}} 580 // CHECK: call void @__atomic_load(i64 noundef 4, ptr noundef getelementptr (i8, ptr @{{.+}}, i64 4), ptr noundef [[LDTEMP:%.+]], i32 noundef 0) 581 // CHECK: br label %[[CONT:.+]] 582 // CHECK: [[CONT]] 583 // CHECK: [[PREV_VALUE:%.+]] = load i32, ptr [[LDTEMP]] 584 // CHECK: store i32 [[PREV_VALUE]], ptr [[TEMP1:%.+]], 585 // CHECK: [[PREV_VALUE:%.+]] = load i32, ptr [[LDTEMP]] 586 // CHECK: store i32 [[PREV_VALUE]], ptr [[TEMP:%.+]], 587 // CHECK: [[A_LD:%.+]] = load i32, ptr [[TEMP]], 588 // CHECK: [[A_SHL:%.+]] = shl i32 [[A_LD]], 1 589 // CHECK: [[A_ASHR:%.+]] = ashr i32 [[A_SHL]], 1 590 // CHECK: [[X_RVAL:%.+]] = sitofp i32 [[A_ASHR]] to x86_fp80 591 // CHECK: [[MUL:%.+]] = fmul x86_fp80 [[X_RVAL]], [[EXPR]] 592 // CHECK: [[CONV:%.+]] = fptosi x86_fp80 [[MUL]] to i32 593 // CHECK: [[NEW_VAL:%.+]] = load i32, ptr [[TEMP1]], 594 // CHECK: [[BF_VALUE:%.+]] = and i32 [[CONV]], 2147483647 595 // CHECK: [[BF_CLEAR:%.+]] = and i32 [[NEW_VAL]], -2147483648 596 // CHECK: or i32 [[BF_CLEAR]], [[BF_VALUE]] 597 // CHECK: store i32 %{{.+}}, ptr [[TEMP1]] 598 // CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 4, ptr noundef getelementptr (i8, ptr @{{.+}}, i64 4), ptr noundef [[LDTEMP]], ptr noundef [[TEMP1]], i32 noundef 0, i32 noundef 0) 599 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] 600 // CHECK: [[EXIT]] 601 #pragma omp atomic update 602 bfx_packed.a *= ldv; 603 // CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}} 604 // CHECK: [[PREV_VALUE:%.+]] = load atomic i32, ptr @{{.+}} monotonic, align 4 605 // CHECK: br label %[[CONT:.+]] 606 // CHECK: [[CONT]] 607 // CHECK: [[OLD_BF_VALUE:%.+]] = phi i32 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ] 608 // CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP1:%.+]], 609 // CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP:%.+]], 610 // CHECK: [[A_LD:%.+]] = load i32, ptr [[TEMP]], 611 // CHECK: [[A_ASHR:%.+]] = ashr i32 [[A_LD]], 31 612 // CHECK: [[X_RVAL:%.+]] = sitofp i32 [[A_ASHR]] to x86_fp80 613 // CHECK: [[SUB:%.+]] = fsub x86_fp80 [[X_RVAL]], [[EXPR]] 614 // CHECK: [[CONV:%.+]] = fptosi x86_fp80 [[SUB]] to i32 615 // CHECK: [[NEW_VAL:%.+]] = load i32, ptr [[TEMP1]], 616 // CHECK: [[BF_AND:%.+]] = and i32 [[CONV]], 1 617 // CHECK: [[BF_VALUE:%.+]] = shl i32 [[BF_AND]], 31 618 // CHECK: [[BF_CLEAR:%.+]] = and i32 [[NEW_VAL]], 2147483647 619 // CHECK: or i32 [[BF_CLEAR]], [[BF_VALUE]] 620 // CHECK: store i32 %{{.+}}, ptr [[TEMP1]] 621 // CHECK: [[NEW_BF_VALUE:%.+]] = load i32, ptr [[TEMP1]] 622 // CHECK: [[RES:%.+]] = cmpxchg ptr @{{.+}}, i32 [[OLD_BF_VALUE]], i32 [[NEW_BF_VALUE]] monotonic monotonic, align 4 623 // CHECK: [[FAILED_OLD_VAL]] = extractvalue { i32, i1 } [[RES]], 0 624 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i32, i1 } [[RES]], 1 625 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] 626 // CHECK: [[EXIT]] 627 #pragma omp atomic 628 bfx2.a -= ldv; 629 // CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}} 630 // CHECK: [[PREV_VALUE:%.+]] = load atomic i8, ptr getelementptr (i8, ptr @{{.+}}, i64 3) monotonic, align 1 631 // CHECK: br label %[[CONT:.+]] 632 // CHECK: [[CONT]] 633 // CHECK: [[OLD_BF_VALUE:%.+]] = phi i8 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ] 634 // CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST1:%.+]], 635 // CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST:%.+]], 636 // CHECK: [[A_LD:%.+]] = load i8, ptr [[BITCAST]], 637 // CHECK: [[A_ASHR:%.+]] = ashr i8 [[A_LD]], 7 638 // CHECK: [[CAST:%.+]] = sext i8 [[A_ASHR]] to i32 639 // CHECK: [[X_RVAL:%.+]] = sitofp i32 [[CAST]] to x86_fp80 640 // CHECK: [[DIV:%.+]] = fdiv x86_fp80 [[EXPR]], [[X_RVAL]] 641 // CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 [[DIV]] to i32 642 // CHECK: [[TRUNC:%.+]] = trunc i32 [[NEW_VAL]] to i8 643 // CHECK: [[BF_LD:%.+]] = load i8, ptr [[BITCAST1]], 644 // CHECK: [[BF_AND:%.+]] = and i8 [[TRUNC]], 1 645 // CHECK: [[BF_VALUE:%.+]] = shl i8 [[BF_AND]], 7 646 // CHECK: [[BF_CLEAR:%.+]] = and i8 %{{.+}}, 127 647 // CHECK: or i8 [[BF_CLEAR]], [[BF_VALUE]] 648 // CHECK: store i8 %{{.+}}, ptr [[BITCAST1]] 649 // CHECK: [[NEW_BF_VALUE:%.+]] = load i8, ptr [[BITCAST1]] 650 // CHECK: [[RES:%.+]] = cmpxchg ptr getelementptr (i8, ptr @{{.+}}, i64 3), i8 [[OLD_BF_VALUE]], i8 [[NEW_BF_VALUE]] monotonic monotonic, align 1 651 // CHECK: [[FAILED_OLD_VAL]] = extractvalue { i8, i1 } [[RES]], 0 652 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i8, i1 } [[RES]], 1 653 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] 654 // CHECK: [[EXIT]] 655 #pragma omp atomic update 656 bfx2_packed.a = ldv / bfx2_packed.a; 657 // CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}} 658 // CHECK: [[PREV_VALUE:%.+]] = load atomic i32, ptr @{{.+}} monotonic, align 4 659 // CHECK: br label %[[CONT:.+]] 660 // CHECK: [[CONT]] 661 // CHECK: [[OLD_BF_VALUE:%.+]] = phi i32 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ] 662 // CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP1:%.+]], 663 // CHECK: store i32 [[OLD_BF_VALUE]], ptr [[TEMP:%.+]], 664 // CHECK: [[A_LD:%.+]] = load i32, ptr [[TEMP]], 665 // CHECK: [[A_SHL:%.+]] = shl i32 [[A_LD]], 7 666 // CHECK: [[A_ASHR:%.+]] = ashr i32 [[A_SHL]], 18 667 // CHECK: [[X_RVAL:%.+]] = sitofp i32 [[A_ASHR]] to x86_fp80 668 // CHECK: [[DIV:%.+]] = fdiv x86_fp80 [[X_RVAL]], [[EXPR]] 669 // CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 [[DIV]] to i32 670 // CHECK: [[BF_LD:%.+]] = load i32, ptr [[TEMP1]], 671 // CHECK: [[BF_AND:%.+]] = and i32 [[NEW_VAL]], 16383 672 // CHECK: [[BF_VALUE:%.+]] = shl i32 [[BF_AND]], 11 673 // CHECK: [[BF_CLEAR:%.+]] = and i32 %{{.+}}, -33552385 674 // CHECK: or i32 [[BF_CLEAR]], [[BF_VALUE]] 675 // CHECK: store i32 %{{.+}}, ptr [[TEMP1]] 676 // CHECK: [[NEW_BF_VALUE:%.+]] = load i32, ptr [[TEMP1]] 677 // CHECK: [[RES:%.+]] = cmpxchg ptr @{{.+}}, i32 [[OLD_BF_VALUE]], i32 [[NEW_BF_VALUE]] monotonic monotonic, align 4 678 // CHECK: [[FAILED_OLD_VAL]] = extractvalue { i32, i1 } [[RES]], 0 679 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i32, i1 } [[RES]], 1 680 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] 681 // CHECK: [[EXIT]] 682 #pragma omp atomic 683 bfx3.a /= ldv; 684 // CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}} 685 // CHECK: call void @__atomic_load(i64 noundef 3, ptr noundef getelementptr (i8, ptr @{{.+}}, i64 1), ptr noundef [[BITCAST:%.+]], i32 noundef 0) 686 // CHECK: br label %[[CONT:.+]] 687 // CHECK: [[CONT]] 688 // CHECK: [[PREV_VALUE:%.+]] = load i24, ptr [[LDTEMP:%.+]], 689 // CHECK: store i24 [[PREV_VALUE]], ptr [[TEMP1:%.+]], 690 // CHECK: [[PREV_VALUE:%.+]] = load i24, ptr [[LDTEMP]] 691 // CHECK: store i24 [[PREV_VALUE]], ptr [[TEMP:%.+]], 692 // CHECK: [[A_LD:%.+]] = load i24, ptr [[TEMP]], 693 // CHECK: [[A_SHL:%.+]] = shl i24 [[A_LD]], 7 694 // CHECK: [[A_ASHR:%.+]] = ashr i24 [[A_SHL]], 10 695 // CHECK: [[CAST:%.+]] = sext i24 [[A_ASHR]] to i32 696 // CHECK: [[X_RVAL:%.+]] = sitofp i32 [[CAST]] to x86_fp80 697 // CHECK: [[ADD:%.+]] = fadd x86_fp80 [[X_RVAL]], [[EXPR]] 698 // CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 [[ADD]] to i32 699 // CHECK: [[TRUNC:%.+]] = trunc i32 [[NEW_VAL]] to i24 700 // CHECK: [[BF_LD:%.+]] = load i24, ptr [[TEMP1]], 701 // CHECK: [[BF_AND:%.+]] = and i24 [[TRUNC]], 16383 702 // CHECK: [[BF_VALUE:%.+]] = shl i24 [[BF_AND]], 3 703 // CHECK: [[BF_CLEAR:%.+]] = and i24 [[BF_LD]], -131065 704 // CHECK: or i24 [[BF_CLEAR]], [[BF_VALUE]] 705 // CHECK: store i24 %{{.+}}, ptr [[TEMP1]] 706 // CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 3, ptr noundef getelementptr (i8, ptr @{{.+}}, i64 1), ptr noundef [[LDTEMP]], ptr noundef [[TEMP1]], i32 noundef 0, i32 noundef 0) 707 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] 708 // CHECK: [[EXIT]] 709 #pragma omp atomic update 710 bfx3_packed.a += ldv; 711 // CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}} 712 // CHECK: [[PREV_VALUE:%.+]] = load atomic i64, ptr @{{.+}} monotonic, align 8 713 // CHECK: br label %[[CONT:.+]] 714 // CHECK: [[CONT]] 715 // CHECK: [[OLD_BF_VALUE:%.+]] = phi i64 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ] 716 // CHECK: store i64 [[OLD_BF_VALUE]], ptr [[TEMP1:%.+]], 717 // CHECK: store i64 [[OLD_BF_VALUE]], ptr [[TEMP:%.+]], 718 // CHECK: [[A_LD:%.+]] = load i64, ptr [[TEMP]], 719 // CHECK: [[A_SHL:%.+]] = shl i64 [[A_LD]], 47 720 // CHECK: [[A_ASHR:%.+]] = ashr i64 [[A_SHL:%.+]], 63 721 // CHECK: [[A_CAST:%.+]] = trunc i64 [[A_ASHR:%.+]] to i32 722 // CHECK: [[X_RVAL:%.+]] = sitofp i32 [[CAST:%.+]] to x86_fp80 723 // CHECK: [[MUL:%.+]] = fmul x86_fp80 [[X_RVAL]], [[EXPR]] 724 // CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 [[MUL]] to i32 725 // CHECK: [[ZEXT:%.+]] = zext i32 [[NEW_VAL]] to i64 726 // CHECK: [[BF_LD:%.+]] = load i64, ptr [[TEMP1]], 727 // CHECK: [[BF_AND:%.+]] = and i64 [[ZEXT]], 1 728 // CHECK: [[BF_VALUE:%.+]] = shl i64 [[BF_AND]], 16 729 // CHECK: [[BF_CLEAR:%.+]] = and i64 [[BF_LD]], -65537 730 // CHECK: or i64 [[BF_CLEAR]], [[BF_VALUE]] 731 // CHECK: store i64 %{{.+}}, ptr [[TEMP1]] 732 // CHECK: [[NEW_BF_VALUE:%.+]] = load i64, ptr [[TEMP1]] 733 // CHECK: [[RES:%.+]] = cmpxchg ptr @{{.+}}, i64 [[OLD_BF_VALUE]], i64 [[NEW_BF_VALUE]] monotonic monotonic, align 8 734 // CHECK: [[FAILED_OLD_VAL]] = extractvalue { i64, i1 } [[RES]], 0 735 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i64, i1 } [[RES]], 1 736 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] 737 // CHECK: [[EXIT]] 738 #pragma omp atomic 739 bfx4.a = bfx4.a * ldv; 740 // CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}} 741 // CHECK: [[PREV_VALUE:%.+]] = load atomic i8, ptr getelementptr inbounds nuw (%struct.BitFields4_packed, ptr @{{.+}}, i32 0, i32 1) monotonic, align 1 742 // CHECK: br label %[[CONT:.+]] 743 // CHECK: [[CONT]] 744 // CHECK: [[OLD_BF_VALUE:%.+]] = phi i8 [ [[PREV_VALUE]], %{{.+}} ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ] 745 // CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST1:%.+]], 746 // CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST:%.+]], 747 // CHECK: [[A_LD:%.+]] = load i8, ptr [[BITCAST]], 748 // CHECK: [[A_SHL:%.+]] = shl i8 [[A_LD]], 7 749 // CHECK: [[A_ASHR:%.+]] = ashr i8 [[A_SHL:%.+]], 7 750 // CHECK: [[CAST:%.+]] = sext i8 [[A_ASHR:%.+]] to i32 751 // CHECK: [[CONV:%.+]] = sitofp i32 [[CAST]] to x86_fp80 752 // CHECK: [[SUB: %.+]] = fsub x86_fp80 [[CONV]], [[EXPR]] 753 // CHECK: [[CONV:%.+]] = fptosi x86_fp80 [[SUB:%.+]] to i32 754 // CHECK: [[NEW_VAL:%.+]] = trunc i32 [[CONV]] to i8 755 // CHECK: [[BF_LD:%.+]] = load i8, ptr [[BITCAST1]], 756 // CHECK: [[BF_VALUE:%.+]] = and i8 [[NEW_VAL]], 1 757 // CHECK: [[BF_CLEAR:%.+]] = and i8 [[BF_LD]], -2 758 // CHECK: or i8 [[BF_CLEAR]], [[BF_VALUE]] 759 // CHECK: store i8 %{{.+}}, ptr [[BITCAST1]] 760 // CHECK: [[NEW_BF_VALUE:%.+]] = load i8, ptr [[BITCAST1]] 761 // CHECK: [[RES:%.+]] = cmpxchg ptr getelementptr inbounds nuw (%struct.BitFields4_packed, ptr @{{.+}}, i32 0, i32 1), i8 [[OLD_BF_VALUE]], i8 [[NEW_BF_VALUE]] monotonic monotonic, align 1 762 // CHECK: [[FAILED_OLD_VAL]] = extractvalue { i8, i1 } [[RES]], 0 763 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i8, i1 } [[RES]], 1 764 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] 765 // CHECK: [[EXIT]] 766 #pragma omp atomic relaxed update 767 bfx4_packed.a -= ldv; 768 // CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}} 769 // CHECK: [[PREV_VALUE:%.+]] = load atomic i64, ptr @{{.+}} monotonic, align 8 770 // CHECK: br label %[[CONT:.+]] 771 // CHECK: [[CONT]] 772 // CHECK: [[OLD_BF_VALUE:%.+]] = phi i64 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ] 773 // CHECK: store i64 [[OLD_BF_VALUE]], ptr [[TEMP1:%.+]], 774 // CHECK: store i64 [[OLD_BF_VALUE]], ptr [[TEMP:%.+]], 775 // CHECK: [[A_LD:%.+]] = load i64, ptr [[TEMP]], 776 // CHECK: [[A_SHL:%.+]] = shl i64 [[A_LD]], 40 777 // CHECK: [[A_ASHR:%.+]] = ashr i64 [[A_SHL:%.+]], 57 778 // CHECK: [[CONV:%.+]] = sitofp i64 [[A_ASHR]] to x86_fp80 779 // CHECK: [[DIV:%.+]] = fdiv x86_fp80 [[CONV]], [[EXPR]] 780 // CHECK: [[CONV:%.+]] = fptosi x86_fp80 [[DIV]] to i64 781 // CHECK: [[BF_LD:%.+]] = load i64, ptr [[TEMP1]], 782 // CHECK: [[BF_AND:%.+]] = and i64 [[CONV]], 127 783 // CHECK: [[BF_VALUE:%.+]] = shl i64 [[BF_AND:%.+]], 17 784 // CHECK: [[BF_CLEAR:%.+]] = and i64 [[BF_LD]], -16646145 785 // CHECK: [[VAL:%.+]] = or i64 [[BF_CLEAR]], [[BF_VALUE]] 786 // CHECK: store i64 [[VAL]], ptr [[TEMP1]] 787 // CHECK: [[NEW_BF_VALUE:%.+]] = load i64, ptr [[TEMP1]] 788 // CHECK: [[RES:%.+]] = cmpxchg ptr @{{.+}}, i64 [[OLD_BF_VALUE]], i64 [[NEW_BF_VALUE]] monotonic monotonic, align 8 789 // CHECK: [[FAILED_OLD_VAL]] = extractvalue { i64, i1 } [[RES]], 0 790 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i64, i1 } [[RES]], 1 791 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] 792 // CHECK: [[EXIT]] 793 #pragma omp atomic 794 bfx4.b /= ldv; 795 // CHECK: [[EXPR:%.+]] = load x86_fp80, ptr @{{.+}} 796 // CHECK: [[PREV_VALUE:%.+]] = load atomic i8, ptr getelementptr inbounds nuw (%struct.BitFields4_packed, ptr @{{.+}}, i32 0, i32 1) monotonic, align 1 797 // CHECK: br label %[[CONT:.+]] 798 // CHECK: [[CONT]] 799 // CHECK: [[OLD_BF_VALUE:%.+]] = phi i8 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ] 800 // CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST1:%.+]], 801 // CHECK: store i8 [[OLD_BF_VALUE]], ptr [[BITCAST:%.+]], 802 // CHECK: [[A_LD:%.+]] = load i8, ptr [[BITCAST]], 803 // CHECK: [[A_ASHR:%.+]] = ashr i8 [[A_LD]], 1 804 // CHECK: [[CAST:%.+]] = sext i8 [[A_ASHR]] to i64 805 // CHECK: [[CONV:%.+]] = sitofp i64 [[CAST]] to x86_fp80 806 // CHECK: [[ADD:%.+]] = fadd x86_fp80 [[CONV]], [[EXPR]] 807 // CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 [[ADD]] to i64 808 // CHECK: [[TRUNC:%.+]] = trunc i64 [[NEW_VAL]] to i8 809 // CHECK: [[BF_LD:%.+]] = load i8, ptr [[BITCAST1]], 810 // CHECK: [[BF_AND:%.+]] = and i8 [[TRUNC]], 127 811 // CHECK: [[BF_VALUE:%.+]] = shl i8 [[BF_AND]], 1 812 // CHECK: [[BF_CLEAR:%.+]] = and i8 [[BF_LD]], 1 813 // CHECK: or i8 [[BF_CLEAR]], [[BF_VALUE]] 814 // CHECK: store i8 %{{.+}}, ptr [[BITCAST1]] 815 // CHECK: [[NEW_BF_VALUE:%.+]] = load i8, ptr [[BITCAST1]] 816 // CHECK: [[RES:%.+]] = cmpxchg ptr getelementptr inbounds nuw (%struct.BitFields4_packed, ptr @{{.+}}, i32 0, i32 1), i8 [[OLD_BF_VALUE]], i8 [[NEW_BF_VALUE]] monotonic monotonic, align 1 817 // CHECK: [[FAILED_OLD_VAL]] = extractvalue { i8, i1 } [[RES]], 0 818 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i8, i1 } [[RES]], 1 819 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] 820 // CHECK: [[EXIT]] 821 #pragma omp atomic update relaxed 822 bfx4_packed.b += ldv; 823 // CHECK: load i64, ptr 824 // CHECK: [[EXPR:%.+]] = uitofp i64 %{{.+}} to float 825 // CHECK: [[I64VAL:%.+]] = load atomic i64, ptr [[DEST:@.+]] monotonic, align 8 826 // CHECK: br label %[[CONT:.+]] 827 // CHECK: [[CONT]] 828 // CHECK: [[OLD_I64:%.+]] = phi i64 [ [[I64VAL]], %{{.+}} ], [ [[FAILED_I64_OLD_VAL:%.+]], %[[CONT]] ] 829 // CHECK: store i64 [[OLD_I64]], ptr [[TEMP:%.+]], 830 // CHECK: [[OLD_VEC_VAL:%.+]] = bitcast i64 [[OLD_I64]] to <2 x float> 831 // CHECK: store <2 x float> [[OLD_VEC_VAL]], ptr [[LDTEMP:%.+]], 832 // CHECK: [[VEC_VAL:%.+]] = load <2 x float>, ptr [[LDTEMP]] 833 // CHECK: [[X:%.+]] = extractelement <2 x float> [[VEC_VAL]], i64 0 834 // CHECK: [[VEC_ITEM_VAL:%.+]] = fsub float [[EXPR]], [[X]] 835 // CHECK: [[VEC_VAL:%.+]] = load <2 x float>, ptr [[TEMP]], 836 // CHECK: [[NEW_VEC_VAL:%.+]] = insertelement <2 x float> [[VEC_VAL]], float [[VEC_ITEM_VAL]], i64 0 837 // CHECK: store <2 x float> [[NEW_VEC_VAL]], ptr [[TEMP]] 838 // CHECK: [[NEW_I64:%.+]] = load i64, ptr [[TEMP]] 839 // CHECK: [[RES:%.+]] = cmpxchg ptr [[DEST]], i64 [[OLD_I64]], i64 [[NEW_I64]] monotonic monotonic, align 8 840 // CHECK: [[FAILED_I64_OLD_VAL:%.+]] = extractvalue { i64, i1 } [[RES]], 0 841 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i64, i1 } [[RES]], 1 842 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] 843 // CHECK: [[EXIT]] 844 #pragma omp atomic relaxed 845 float2x.x = ulv - float2x.x; 846 // CHECK: [[EXPR:%.+]] = load double, ptr @{{.+}}, 847 // CHECK: [[OLD_VAL:%.+]] = call i32 @llvm.read_register.i32([[REG:metadata ![0-9]+]]) 848 // CHECK: [[X_RVAL:%.+]] = sitofp i32 [[OLD_VAL]] to double 849 // CHECK: [[DIV:%.+]] = fdiv double [[EXPR]], [[X_RVAL]] 850 // CHECK: [[NEW_VAL:%.+]] = fptosi double [[DIV]] to i32 851 // CHECK: call void @llvm.write_register.i32([[REG]], i32 [[NEW_VAL]]) 852 // CHECK: call{{.*}} @__kmpc_flush( 853 #pragma omp atomic seq_cst 854 rix = dv / rix; 855 856 // CHECK: [[LD_CPX:%.+]] = load atomic ptr, ptr @cpx monotonic 857 // CHECK: br label %[[CONT:.+]] 858 // CHECK: [[CONT]] 859 // CHECK: [[PHI:%.+]] = phi ptr 860 // CHECK: [[RES:%.+]] = cmpxchg ptr @cpx, 861 // CHECK: br i1 %{{.+}}, label %[[EXIT:.+]], label %[[CONT]] 862 #pragma omp atomic update 863 cpx += 1; 864 865 return 0; 866 } 867 868 #endif 869