xref: /llvm-project/clang/test/OpenMP/atomic_compare_codegen.cpp (revision 49ee8b53ef39c158d40d76128828379dd34ea61f) 
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs
2 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s
3 // RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s
4 // RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s
5 
6 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp-simd -x c -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
7 // RUN: %clang_cc1 -fopenmp-simd -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s
8 // RUN: %clang_cc1 -fopenmp-simd -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
9 // expected-no-diagnostics
10 
11 #ifndef HEADER
12 #define HEADER
13 
foo(void)14 void foo(void) {
15   char cx, ce, cd;
16   unsigned char ucx, uce, ucd;
17   short sx, se, sd;
18   unsigned short usx, use, usd;
19   int ix, ie, id;
20   unsigned int uix, uie, uid;
21   long lx, le, ld;
22   unsigned long ulx, ule, uld;
23   long long llx, lle, lld;
24   unsigned long long ullx, ulle, ulld;
25   float fx, fe, fd;
26   double dx, de, dd;
27 
28 #pragma omp atomic compare
29   cx = cx > ce ? ce : cx;
30 #pragma omp atomic compare
31   cx = cx < ce ? ce : cx;
32 #pragma omp atomic compare
33   cx = ce > cx ? ce : cx;
34 #pragma omp atomic compare
35   cx = ce < cx ? ce : cx;
36 #pragma omp atomic compare
37   if (cx > ce)
38     cx = ce;
39 #pragma omp atomic compare
40   if (cx < ce)
41     cx = ce;
42 #pragma omp atomic compare
43   if (ce > cx)
44     cx = ce;
45 #pragma omp atomic compare
46   if (ce < cx)
47     cx = ce;
48 
49 #pragma omp atomic compare
50   cx = cx == ce ? cd : cx;
51 #pragma omp atomic compare
52   cx = ce == cx ? cd : cx;
53 #pragma omp atomic compare
54   if (cx == ce)
55     cx = cd;
56 #pragma omp atomic compare
57   if (ce == cx)
58     cx = cd;
59 
60 #pragma omp atomic compare
61   ucx = ucx > uce ? uce : ucx;
62 #pragma omp atomic compare
63   ucx = ucx < uce ? uce : ucx;
64 #pragma omp atomic compare
65   ucx = uce > ucx ? uce : ucx;
66 #pragma omp atomic compare
67   ucx = uce < ucx ? uce : ucx;
68 #pragma omp atomic compare
69   if (ucx > uce)
70     ucx = uce;
71 #pragma omp atomic compare
72   if (ucx < uce)
73     ucx = uce;
74 #pragma omp atomic compare
75   if (uce > ucx)
76     ucx = uce;
77 #pragma omp atomic compare
78   if (uce < ucx)
79     ucx = uce;
80 
81 #pragma omp atomic compare
82   ucx = ucx == uce ? ucd : ucx;
83 #pragma omp atomic compare
84   ucx = uce == ucx ? ucd : ucx;
85 #pragma omp atomic compare
86   if (ucx == uce)
87     ucx = ucd;
88 #pragma omp atomic compare
89   if (uce == ucx)
90     ucx = ucd;
91 
92 #pragma omp atomic compare acq_rel
93   cx = cx > ce ? ce : cx;
94 #pragma omp atomic compare acq_rel
95   cx = cx < ce ? ce : cx;
96 #pragma omp atomic compare acq_rel
97   cx = ce > cx ? ce : cx;
98 #pragma omp atomic compare acq_rel
99   cx = ce < cx ? ce : cx;
100 #pragma omp atomic compare acq_rel
101   if (cx > ce)
102     cx = ce;
103 #pragma omp atomic compare acq_rel
104   if (cx < ce)
105     cx = ce;
106 #pragma omp atomic compare acq_rel
107   if (ce > cx)
108     cx = ce;
109 #pragma omp atomic compare acq_rel
110   if (ce < cx)
111     cx = ce;
112 
113 #pragma omp atomic compare acq_rel
114   cx = cx == ce ? cd : cx;
115 #pragma omp atomic compare acq_rel
116   cx = ce == cx ? cd : cx;
117 #pragma omp atomic compare acq_rel
118   if (cx == ce)
119     cx = cd;
120 #pragma omp atomic compare acq_rel
121   if (ce == cx)
122     cx = cd;
123 
124 #pragma omp atomic compare acq_rel
125   ucx = ucx > uce ? uce : ucx;
126 #pragma omp atomic compare acq_rel
127   ucx = ucx < uce ? uce : ucx;
128 #pragma omp atomic compare acq_rel
129   ucx = uce > ucx ? uce : ucx;
130 #pragma omp atomic compare acq_rel
131   ucx = uce < ucx ? uce : ucx;
132 #pragma omp atomic compare acq_rel
133   if (ucx > uce)
134     ucx = uce;
135 #pragma omp atomic compare acq_rel
136   if (ucx < uce)
137     ucx = uce;
138 #pragma omp atomic compare acq_rel
139   if (uce > ucx)
140     ucx = uce;
141 #pragma omp atomic compare acq_rel
142   if (uce < ucx)
143     ucx = uce;
144 
145 #pragma omp atomic compare acq_rel
146   ucx = ucx == uce ? ucd : ucx;
147 #pragma omp atomic compare acq_rel
148   ucx = uce == ucx ? ucd : ucx;
149 #pragma omp atomic compare acq_rel
150   if (ucx == uce)
151     ucx = ucd;
152 #pragma omp atomic compare acq_rel
153   if (uce == ucx)
154     ucx = ucd;
155 
156 #pragma omp atomic compare acquire
157   cx = cx > ce ? ce : cx;
158 #pragma omp atomic compare acquire
159   cx = cx < ce ? ce : cx;
160 #pragma omp atomic compare acquire
161   cx = ce > cx ? ce : cx;
162 #pragma omp atomic compare acquire
163   cx = ce < cx ? ce : cx;
164 #pragma omp atomic compare acquire
165   if (cx > ce)
166     cx = ce;
167 #pragma omp atomic compare acquire
168   if (cx < ce)
169     cx = ce;
170 #pragma omp atomic compare acquire
171   if (ce > cx)
172     cx = ce;
173 #pragma omp atomic compare acquire
174   if (ce < cx)
175     cx = ce;
176 
177 #pragma omp atomic compare acquire
178   cx = cx == ce ? cd : cx;
179 #pragma omp atomic compare acquire
180   cx = ce == cx ? cd : cx;
181 #pragma omp atomic compare acquire
182   if (cx == ce)
183     cx = cd;
184 #pragma omp atomic compare acquire
185   if (ce == cx)
186     cx = cd;
187 
188 #pragma omp atomic compare acquire
189   ucx = ucx > uce ? uce : ucx;
190 #pragma omp atomic compare acquire
191   ucx = ucx < uce ? uce : ucx;
192 #pragma omp atomic compare acquire
193   ucx = uce > ucx ? uce : ucx;
194 #pragma omp atomic compare acquire
195   ucx = uce < ucx ? uce : ucx;
196 #pragma omp atomic compare acquire
197   if (ucx > uce)
198     ucx = uce;
199 #pragma omp atomic compare acquire
200   if (ucx < uce)
201     ucx = uce;
202 #pragma omp atomic compare acquire
203   if (uce > ucx)
204     ucx = uce;
205 #pragma omp atomic compare acquire
206   if (uce < ucx)
207     ucx = uce;
208 
209 #pragma omp atomic compare acquire
210   ucx = ucx == uce ? ucd : ucx;
211 #pragma omp atomic compare acquire
212   ucx = uce == ucx ? ucd : ucx;
213 #pragma omp atomic compare acquire
214   if (ucx == uce)
215     ucx = ucd;
216 #pragma omp atomic compare acquire
217   if (uce == ucx)
218     ucx = ucd;
219 
220 #pragma omp atomic compare relaxed
221   cx = cx > ce ? ce : cx;
222 #pragma omp atomic compare relaxed
223   cx = cx < ce ? ce : cx;
224 #pragma omp atomic compare relaxed
225   cx = ce > cx ? ce : cx;
226 #pragma omp atomic compare relaxed
227   cx = ce < cx ? ce : cx;
228 #pragma omp atomic compare relaxed
229   if (cx > ce)
230     cx = ce;
231 #pragma omp atomic compare relaxed
232   if (cx < ce)
233     cx = ce;
234 #pragma omp atomic compare relaxed
235   if (ce > cx)
236     cx = ce;
237 #pragma omp atomic compare relaxed
238   if (ce < cx)
239     cx = ce;
240 
241 #pragma omp atomic compare relaxed
242   cx = cx == ce ? cd : cx;
243 #pragma omp atomic compare relaxed
244   cx = ce == cx ? cd : cx;
245 #pragma omp atomic compare relaxed
246   if (cx == ce)
247     cx = cd;
248 #pragma omp atomic compare relaxed
249   if (ce == cx)
250     cx = cd;
251 
252 #pragma omp atomic compare relaxed
253   ucx = ucx > uce ? uce : ucx;
254 #pragma omp atomic compare relaxed
255   ucx = ucx < uce ? uce : ucx;
256 #pragma omp atomic compare relaxed
257   ucx = uce > ucx ? uce : ucx;
258 #pragma omp atomic compare relaxed
259   ucx = uce < ucx ? uce : ucx;
260 #pragma omp atomic compare relaxed
261   if (ucx > uce)
262     ucx = uce;
263 #pragma omp atomic compare relaxed
264   if (ucx < uce)
265     ucx = uce;
266 #pragma omp atomic compare relaxed
267   if (uce > ucx)
268     ucx = uce;
269 #pragma omp atomic compare relaxed
270   if (uce < ucx)
271     ucx = uce;
272 
273 #pragma omp atomic compare relaxed
274   ucx = ucx == uce ? ucd : ucx;
275 #pragma omp atomic compare relaxed
276   ucx = uce == ucx ? ucd : ucx;
277 #pragma omp atomic compare relaxed
278   if (ucx == uce)
279     ucx = ucd;
280 #pragma omp atomic compare relaxed
281   if (uce == ucx)
282     ucx = ucd;
283 
284 #pragma omp atomic compare release
285   cx = cx > ce ? ce : cx;
286 #pragma omp atomic compare release
287   cx = cx < ce ? ce : cx;
288 #pragma omp atomic compare release
289   cx = ce > cx ? ce : cx;
290 #pragma omp atomic compare release
291   cx = ce < cx ? ce : cx;
292 #pragma omp atomic compare release
293   if (cx > ce)
294     cx = ce;
295 #pragma omp atomic compare release
296   if (cx < ce)
297     cx = ce;
298 #pragma omp atomic compare release
299   if (ce > cx)
300     cx = ce;
301 #pragma omp atomic compare release
302   if (ce < cx)
303     cx = ce;
304 
305 #pragma omp atomic compare release
306   cx = cx == ce ? cd : cx;
307 #pragma omp atomic compare release
308   cx = ce == cx ? cd : cx;
309 #pragma omp atomic compare release
310   if (cx == ce)
311     cx = cd;
312 #pragma omp atomic compare release
313   if (ce == cx)
314     cx = cd;
315 
316 #pragma omp atomic compare release
317   ucx = ucx > uce ? uce : ucx;
318 #pragma omp atomic compare release
319   ucx = ucx < uce ? uce : ucx;
320 #pragma omp atomic compare release
321   ucx = uce > ucx ? uce : ucx;
322 #pragma omp atomic compare release
323   ucx = uce < ucx ? uce : ucx;
324 #pragma omp atomic compare release
325   if (ucx > uce)
326     ucx = uce;
327 #pragma omp atomic compare release
328   if (ucx < uce)
329     ucx = uce;
330 #pragma omp atomic compare release
331   if (uce > ucx)
332     ucx = uce;
333 #pragma omp atomic compare release
334   if (uce < ucx)
335     ucx = uce;
336 
337 #pragma omp atomic compare release
338   ucx = ucx == uce ? ucd : ucx;
339 #pragma omp atomic compare release
340   ucx = uce == ucx ? ucd : ucx;
341 #pragma omp atomic compare release
342   if (ucx == uce)
343     ucx = ucd;
344 #pragma omp atomic compare release
345   if (uce == ucx)
346     ucx = ucd;
347 
348 #pragma omp atomic compare seq_cst
349   cx = cx > ce ? ce : cx;
350 #pragma omp atomic compare seq_cst
351   cx = cx < ce ? ce : cx;
352 #pragma omp atomic compare seq_cst
353   cx = ce > cx ? ce : cx;
354 #pragma omp atomic compare seq_cst
355   cx = ce < cx ? ce : cx;
356 #pragma omp atomic compare seq_cst
357   if (cx > ce)
358     cx = ce;
359 #pragma omp atomic compare seq_cst
360   if (cx < ce)
361     cx = ce;
362 #pragma omp atomic compare seq_cst
363   if (ce > cx)
364     cx = ce;
365 #pragma omp atomic compare seq_cst
366   if (ce < cx)
367     cx = ce;
368 
369 #pragma omp atomic compare seq_cst
370   cx = cx == ce ? cd : cx;
371 #pragma omp atomic compare seq_cst
372   cx = ce == cx ? cd : cx;
373 #pragma omp atomic compare seq_cst
374   if (cx == ce)
375     cx = cd;
376 #pragma omp atomic compare seq_cst
377   if (ce == cx)
378     cx = cd;
379 
380 #pragma omp atomic compare seq_cst
381   ucx = ucx > uce ? uce : ucx;
382 #pragma omp atomic compare seq_cst
383   ucx = ucx < uce ? uce : ucx;
384 #pragma omp atomic compare seq_cst
385   ucx = uce > ucx ? uce : ucx;
386 #pragma omp atomic compare seq_cst
387   ucx = uce < ucx ? uce : ucx;
388 #pragma omp atomic compare seq_cst
389   if (ucx > uce)
390     ucx = uce;
391 #pragma omp atomic compare seq_cst
392   if (ucx < uce)
393     ucx = uce;
394 #pragma omp atomic compare seq_cst
395   if (uce > ucx)
396     ucx = uce;
397 #pragma omp atomic compare seq_cst
398   if (uce < ucx)
399     ucx = uce;
400 
401 #pragma omp atomic compare seq_cst
402   ucx = ucx == uce ? ucd : ucx;
403 #pragma omp atomic compare seq_cst
404   ucx = uce == ucx ? ucd : ucx;
405 #pragma omp atomic compare seq_cst
406   if (ucx == uce)
407     ucx = ucd;
408 #pragma omp atomic compare seq_cst
409   if (uce == ucx)
410     ucx = ucd;
411 
412 #pragma omp atomic compare
413   sx = sx > se ? se : sx;
414 #pragma omp atomic compare
415   sx = sx < se ? se : sx;
416 #pragma omp atomic compare
417   sx = se > sx ? se : sx;
418 #pragma omp atomic compare
419   sx = se < sx ? se : sx;
420 #pragma omp atomic compare
421   if (sx > se)
422     sx = se;
423 #pragma omp atomic compare
424   if (sx < se)
425     sx = se;
426 #pragma omp atomic compare
427   if (se > sx)
428     sx = se;
429 #pragma omp atomic compare
430   if (se < sx)
431     sx = se;
432 
433 #pragma omp atomic compare
434   sx = sx == se ? sd : sx;
435 #pragma omp atomic compare
436   sx = se == sx ? sd : sx;
437 #pragma omp atomic compare
438   if (sx == se)
439     sx = sd;
440 #pragma omp atomic compare
441   if (se == sx)
442     sx = sd;
443 
444 #pragma omp atomic compare
445   usx = usx > use ? use : usx;
446 #pragma omp atomic compare
447   usx = usx < use ? use : usx;
448 #pragma omp atomic compare
449   usx = use > usx ? use : usx;
450 #pragma omp atomic compare
451   usx = use < usx ? use : usx;
452 #pragma omp atomic compare
453   if (usx > use)
454     usx = use;
455 #pragma omp atomic compare
456   if (usx < use)
457     usx = use;
458 #pragma omp atomic compare
459   if (use > usx)
460     usx = use;
461 #pragma omp atomic compare
462   if (use < usx)
463     usx = use;
464 
465 #pragma omp atomic compare
466   usx = usx == use ? usd : usx;
467 #pragma omp atomic compare
468   usx = use == usx ? usd : usx;
469 #pragma omp atomic compare
470   if (usx == use)
471     usx = usd;
472 #pragma omp atomic compare
473   if (use == usx)
474     usx = usd;
475 
476 #pragma omp atomic compare acq_rel
477   sx = sx > se ? se : sx;
478 #pragma omp atomic compare acq_rel
479   sx = sx < se ? se : sx;
480 #pragma omp atomic compare acq_rel
481   sx = se > sx ? se : sx;
482 #pragma omp atomic compare acq_rel
483   sx = se < sx ? se : sx;
484 #pragma omp atomic compare acq_rel
485   if (sx > se)
486     sx = se;
487 #pragma omp atomic compare acq_rel
488   if (sx < se)
489     sx = se;
490 #pragma omp atomic compare acq_rel
491   if (se > sx)
492     sx = se;
493 #pragma omp atomic compare acq_rel
494   if (se < sx)
495     sx = se;
496 
497 #pragma omp atomic compare acq_rel
498   sx = sx == se ? sd : sx;
499 #pragma omp atomic compare acq_rel
500   sx = se == sx ? sd : sx;
501 #pragma omp atomic compare acq_rel
502   if (sx == se)
503     sx = sd;
504 #pragma omp atomic compare acq_rel
505   if (se == sx)
506     sx = sd;
507 
508 #pragma omp atomic compare acq_rel
509   usx = usx > use ? use : usx;
510 #pragma omp atomic compare acq_rel
511   usx = usx < use ? use : usx;
512 #pragma omp atomic compare acq_rel
513   usx = use > usx ? use : usx;
514 #pragma omp atomic compare acq_rel
515   usx = use < usx ? use : usx;
516 #pragma omp atomic compare acq_rel
517   if (usx > use)
518     usx = use;
519 #pragma omp atomic compare acq_rel
520   if (usx < use)
521     usx = use;
522 #pragma omp atomic compare acq_rel
523   if (use > usx)
524     usx = use;
525 #pragma omp atomic compare acq_rel
526   if (use < usx)
527     usx = use;
528 
529 #pragma omp atomic compare acq_rel
530   usx = usx == use ? usd : usx;
531 #pragma omp atomic compare acq_rel
532   usx = use == usx ? usd : usx;
533 #pragma omp atomic compare acq_rel
534   if (usx == use)
535     usx = usd;
536 #pragma omp atomic compare acq_rel
537   if (use == usx)
538     usx = usd;
539 
540 #pragma omp atomic compare acquire
541   sx = sx > se ? se : sx;
542 #pragma omp atomic compare acquire
543   sx = sx < se ? se : sx;
544 #pragma omp atomic compare acquire
545   sx = se > sx ? se : sx;
546 #pragma omp atomic compare acquire
547   sx = se < sx ? se : sx;
548 #pragma omp atomic compare acquire
549   if (sx > se)
550     sx = se;
551 #pragma omp atomic compare acquire
552   if (sx < se)
553     sx = se;
554 #pragma omp atomic compare acquire
555   if (se > sx)
556     sx = se;
557 #pragma omp atomic compare acquire
558   if (se < sx)
559     sx = se;
560 
561 #pragma omp atomic compare acquire
562   sx = sx == se ? sd : sx;
563 #pragma omp atomic compare acquire
564   sx = se == sx ? sd : sx;
565 #pragma omp atomic compare acquire
566   if (sx == se)
567     sx = sd;
568 #pragma omp atomic compare acquire
569   if (se == sx)
570     sx = sd;
571 
572 #pragma omp atomic compare acquire
573   usx = usx > use ? use : usx;
574 #pragma omp atomic compare acquire
575   usx = usx < use ? use : usx;
576 #pragma omp atomic compare acquire
577   usx = use > usx ? use : usx;
578 #pragma omp atomic compare acquire
579   usx = use < usx ? use : usx;
580 #pragma omp atomic compare acquire
581   if (usx > use)
582     usx = use;
583 #pragma omp atomic compare acquire
584   if (usx < use)
585     usx = use;
586 #pragma omp atomic compare acquire
587   if (use > usx)
588     usx = use;
589 #pragma omp atomic compare acquire
590   if (use < usx)
591     usx = use;
592 
593 #pragma omp atomic compare acquire
594   usx = usx == use ? usd : usx;
595 #pragma omp atomic compare acquire
596   usx = use == usx ? usd : usx;
597 #pragma omp atomic compare acquire
598   if (usx == use)
599     usx = usd;
600 #pragma omp atomic compare acquire
601   if (use == usx)
602     usx = usd;
603 
604 #pragma omp atomic compare relaxed
605   sx = sx > se ? se : sx;
606 #pragma omp atomic compare relaxed
607   sx = sx < se ? se : sx;
608 #pragma omp atomic compare relaxed
609   sx = se > sx ? se : sx;
610 #pragma omp atomic compare relaxed
611   sx = se < sx ? se : sx;
612 #pragma omp atomic compare relaxed
613   if (sx > se)
614     sx = se;
615 #pragma omp atomic compare relaxed
616   if (sx < se)
617     sx = se;
618 #pragma omp atomic compare relaxed
619   if (se > sx)
620     sx = se;
621 #pragma omp atomic compare relaxed
622   if (se < sx)
623     sx = se;
624 
625 #pragma omp atomic compare relaxed
626   sx = sx == se ? sd : sx;
627 #pragma omp atomic compare relaxed
628   sx = se == sx ? sd : sx;
629 #pragma omp atomic compare relaxed
630   if (sx == se)
631     sx = sd;
632 #pragma omp atomic compare relaxed
633   if (se == sx)
634     sx = sd;
635 
636 #pragma omp atomic compare relaxed
637   usx = usx > use ? use : usx;
638 #pragma omp atomic compare relaxed
639   usx = usx < use ? use : usx;
640 #pragma omp atomic compare relaxed
641   usx = use > usx ? use : usx;
642 #pragma omp atomic compare relaxed
643   usx = use < usx ? use : usx;
644 #pragma omp atomic compare relaxed
645   if (usx > use)
646     usx = use;
647 #pragma omp atomic compare relaxed
648   if (usx < use)
649     usx = use;
650 #pragma omp atomic compare relaxed
651   if (use > usx)
652     usx = use;
653 #pragma omp atomic compare relaxed
654   if (use < usx)
655     usx = use;
656 
657 #pragma omp atomic compare relaxed
658   usx = usx == use ? usd : usx;
659 #pragma omp atomic compare relaxed
660   usx = use == usx ? usd : usx;
661 #pragma omp atomic compare relaxed
662   if (usx == use)
663     usx = usd;
664 #pragma omp atomic compare relaxed
665   if (use == usx)
666     usx = usd;
667 
668 #pragma omp atomic compare release
669   sx = sx > se ? se : sx;
670 #pragma omp atomic compare release
671   sx = sx < se ? se : sx;
672 #pragma omp atomic compare release
673   sx = se > sx ? se : sx;
674 #pragma omp atomic compare release
675   sx = se < sx ? se : sx;
676 #pragma omp atomic compare release
677   if (sx > se)
678     sx = se;
679 #pragma omp atomic compare release
680   if (sx < se)
681     sx = se;
682 #pragma omp atomic compare release
683   if (se > sx)
684     sx = se;
685 #pragma omp atomic compare release
686   if (se < sx)
687     sx = se;
688 
689 #pragma omp atomic compare release
690   sx = sx == se ? sd : sx;
691 #pragma omp atomic compare release
692   sx = se == sx ? sd : sx;
693 #pragma omp atomic compare release
694   if (sx == se)
695     sx = sd;
696 #pragma omp atomic compare release
697   if (se == sx)
698     sx = sd;
699 
700 #pragma omp atomic compare release
701   usx = usx > use ? use : usx;
702 #pragma omp atomic compare release
703   usx = usx < use ? use : usx;
704 #pragma omp atomic compare release
705   usx = use > usx ? use : usx;
706 #pragma omp atomic compare release
707   usx = use < usx ? use : usx;
708 #pragma omp atomic compare release
709   if (usx > use)
710     usx = use;
711 #pragma omp atomic compare release
712   if (usx < use)
713     usx = use;
714 #pragma omp atomic compare release
715   if (use > usx)
716     usx = use;
717 #pragma omp atomic compare release
718   if (use < usx)
719     usx = use;
720 
721 #pragma omp atomic compare release
722   usx = usx == use ? usd : usx;
723 #pragma omp atomic compare release
724   usx = use == usx ? usd : usx;
725 #pragma omp atomic compare release
726   if (usx == use)
727     usx = usd;
728 #pragma omp atomic compare release
729   if (use == usx)
730     usx = usd;
731 
732 #pragma omp atomic compare seq_cst
733   sx = sx > se ? se : sx;
734 #pragma omp atomic compare seq_cst
735   sx = sx < se ? se : sx;
736 #pragma omp atomic compare seq_cst
737   sx = se > sx ? se : sx;
738 #pragma omp atomic compare seq_cst
739   sx = se < sx ? se : sx;
740 #pragma omp atomic compare seq_cst
741   if (sx > se)
742     sx = se;
743 #pragma omp atomic compare seq_cst
744   if (sx < se)
745     sx = se;
746 #pragma omp atomic compare seq_cst
747   if (se > sx)
748     sx = se;
749 #pragma omp atomic compare seq_cst
750   if (se < sx)
751     sx = se;
752 
753 #pragma omp atomic compare seq_cst
754   sx = sx == se ? sd : sx;
755 #pragma omp atomic compare seq_cst
756   sx = se == sx ? sd : sx;
757 #pragma omp atomic compare seq_cst
758   if (sx == se)
759     sx = sd;
760 #pragma omp atomic compare seq_cst
761   if (se == sx)
762     sx = sd;
763 
764 #pragma omp atomic compare seq_cst
765   usx = usx > use ? use : usx;
766 #pragma omp atomic compare seq_cst
767   usx = usx < use ? use : usx;
768 #pragma omp atomic compare seq_cst
769   usx = use > usx ? use : usx;
770 #pragma omp atomic compare seq_cst
771   usx = use < usx ? use : usx;
772 #pragma omp atomic compare seq_cst
773   if (usx > use)
774     usx = use;
775 #pragma omp atomic compare seq_cst
776   if (usx < use)
777     usx = use;
778 #pragma omp atomic compare seq_cst
779   if (use > usx)
780     usx = use;
781 #pragma omp atomic compare seq_cst
782   if (use < usx)
783     usx = use;
784 
785 #pragma omp atomic compare seq_cst
786   usx = usx == use ? usd : usx;
787 #pragma omp atomic compare seq_cst
788   usx = use == usx ? usd : usx;
789 #pragma omp atomic compare seq_cst
790   if (usx == use)
791     usx = usd;
792 #pragma omp atomic compare seq_cst
793   if (use == usx)
794     usx = usd;
795 
796 #pragma omp atomic compare
797   ix = ix > ie ? ie : ix;
798 #pragma omp atomic compare
799   ix = ix < ie ? ie : ix;
800 #pragma omp atomic compare
801   ix = ie > ix ? ie : ix;
802 #pragma omp atomic compare
803   ix = ie < ix ? ie : ix;
804 #pragma omp atomic compare
805   if (ix > ie)
806     ix = ie;
807 #pragma omp atomic compare
808   if (ix < ie)
809     ix = ie;
810 #pragma omp atomic compare
811   if (ie > ix)
812     ix = ie;
813 #pragma omp atomic compare
814   if (ie < ix)
815     ix = ie;
816 
817 #pragma omp atomic compare
818   ix = ix == ie ? id : ix;
819 #pragma omp atomic compare
820   ix = ie == ix ? id : ix;
821 #pragma omp atomic compare
822   if (ix == ie)
823     ix = id;
824 #pragma omp atomic compare
825   if (ie == ix)
826     ix = id;
827 
828 #pragma omp atomic compare
829   uix = uix > uie ? uie : uix;
830 #pragma omp atomic compare
831   uix = uix < uie ? uie : uix;
832 #pragma omp atomic compare
833   uix = uie > uix ? uie : uix;
834 #pragma omp atomic compare
835   uix = uie < uix ? uie : uix;
836 #pragma omp atomic compare
837   if (uix > uie)
838     uix = uie;
839 #pragma omp atomic compare
840   if (uix < uie)
841     uix = uie;
842 #pragma omp atomic compare
843   if (uie > uix)
844     uix = uie;
845 #pragma omp atomic compare
846   if (uie < uix)
847     uix = uie;
848 
849 #pragma omp atomic compare
850   uix = uix == uie ? uid : uix;
851 #pragma omp atomic compare
852   uix = uie == uix ? uid : uix;
853 #pragma omp atomic compare
854   if (uix == uie)
855     uix = uid;
856 #pragma omp atomic compare
857   if (uie == uix)
858     uix = uid;
859 
860 #pragma omp atomic compare acq_rel
861   ix = ix > ie ? ie : ix;
862 #pragma omp atomic compare acq_rel
863   ix = ix < ie ? ie : ix;
864 #pragma omp atomic compare acq_rel
865   ix = ie > ix ? ie : ix;
866 #pragma omp atomic compare acq_rel
867   ix = ie < ix ? ie : ix;
868 #pragma omp atomic compare acq_rel
869   if (ix > ie)
870     ix = ie;
871 #pragma omp atomic compare acq_rel
872   if (ix < ie)
873     ix = ie;
874 #pragma omp atomic compare acq_rel
875   if (ie > ix)
876     ix = ie;
877 #pragma omp atomic compare acq_rel
878   if (ie < ix)
879     ix = ie;
880 
881 #pragma omp atomic compare acq_rel
882   ix = ix == ie ? id : ix;
883 #pragma omp atomic compare acq_rel
884   ix = ie == ix ? id : ix;
885 #pragma omp atomic compare acq_rel
886   if (ix == ie)
887     ix = id;
888 #pragma omp atomic compare acq_rel
889   if (ie == ix)
890     ix = id;
891 
892 #pragma omp atomic compare acq_rel
893   uix = uix > uie ? uie : uix;
894 #pragma omp atomic compare acq_rel
895   uix = uix < uie ? uie : uix;
896 #pragma omp atomic compare acq_rel
897   uix = uie > uix ? uie : uix;
898 #pragma omp atomic compare acq_rel
899   uix = uie < uix ? uie : uix;
900 #pragma omp atomic compare acq_rel
901   if (uix > uie)
902     uix = uie;
903 #pragma omp atomic compare acq_rel
904   if (uix < uie)
905     uix = uie;
906 #pragma omp atomic compare acq_rel
907   if (uie > uix)
908     uix = uie;
909 #pragma omp atomic compare acq_rel
910   if (uie < uix)
911     uix = uie;
912 
913 #pragma omp atomic compare acq_rel
914   uix = uix == uie ? uid : uix;
915 #pragma omp atomic compare acq_rel
916   uix = uie == uix ? uid : uix;
917 #pragma omp atomic compare acq_rel
918   if (uix == uie)
919     uix = uid;
920 #pragma omp atomic compare acq_rel
921   if (uie == uix)
922     uix = uid;
923 
924 #pragma omp atomic compare acquire
925   ix = ix > ie ? ie : ix;
926 #pragma omp atomic compare acquire
927   ix = ix < ie ? ie : ix;
928 #pragma omp atomic compare acquire
929   ix = ie > ix ? ie : ix;
930 #pragma omp atomic compare acquire
931   ix = ie < ix ? ie : ix;
932 #pragma omp atomic compare acquire
933   if (ix > ie)
934     ix = ie;
935 #pragma omp atomic compare acquire
936   if (ix < ie)
937     ix = ie;
938 #pragma omp atomic compare acquire
939   if (ie > ix)
940     ix = ie;
941 #pragma omp atomic compare acquire
942   if (ie < ix)
943     ix = ie;
944 
945 #pragma omp atomic compare acquire
946   ix = ix == ie ? id : ix;
947 #pragma omp atomic compare acquire
948   ix = ie == ix ? id : ix;
949 #pragma omp atomic compare acquire
950   if (ix == ie)
951     ix = id;
952 #pragma omp atomic compare acquire
953   if (ie == ix)
954     ix = id;
955 
956 #pragma omp atomic compare acquire
957   uix = uix > uie ? uie : uix;
958 #pragma omp atomic compare acquire
959   uix = uix < uie ? uie : uix;
960 #pragma omp atomic compare acquire
961   uix = uie > uix ? uie : uix;
962 #pragma omp atomic compare acquire
963   uix = uie < uix ? uie : uix;
964 #pragma omp atomic compare acquire
965   if (uix > uie)
966     uix = uie;
967 #pragma omp atomic compare acquire
968   if (uix < uie)
969     uix = uie;
970 #pragma omp atomic compare acquire
971   if (uie > uix)
972     uix = uie;
973 #pragma omp atomic compare acquire
974   if (uie < uix)
975     uix = uie;
976 
977 #pragma omp atomic compare acquire
978   uix = uix == uie ? uid : uix;
979 #pragma omp atomic compare acquire
980   uix = uie == uix ? uid : uix;
981 #pragma omp atomic compare acquire
982   if (uix == uie)
983     uix = uid;
984 #pragma omp atomic compare acquire
985   if (uie == uix)
986     uix = uid;
987 
988 #pragma omp atomic compare relaxed
989   ix = ix > ie ? ie : ix;
990 #pragma omp atomic compare relaxed
991   ix = ix < ie ? ie : ix;
992 #pragma omp atomic compare relaxed
993   ix = ie > ix ? ie : ix;
994 #pragma omp atomic compare relaxed
995   ix = ie < ix ? ie : ix;
996 #pragma omp atomic compare relaxed
997   if (ix > ie)
998     ix = ie;
999 #pragma omp atomic compare relaxed
1000   if (ix < ie)
1001     ix = ie;
1002 #pragma omp atomic compare relaxed
1003   if (ie > ix)
1004     ix = ie;
1005 #pragma omp atomic compare relaxed
1006   if (ie < ix)
1007     ix = ie;
1008 
1009 #pragma omp atomic compare relaxed
1010   ix = ix == ie ? id : ix;
1011 #pragma omp atomic compare relaxed
1012   ix = ie == ix ? id : ix;
1013 #pragma omp atomic compare relaxed
1014   if (ix == ie)
1015     ix = id;
1016 #pragma omp atomic compare relaxed
1017   if (ie == ix)
1018     ix = id;
1019 
1020 #pragma omp atomic compare relaxed
1021   uix = uix > uie ? uie : uix;
1022 #pragma omp atomic compare relaxed
1023   uix = uix < uie ? uie : uix;
1024 #pragma omp atomic compare relaxed
1025   uix = uie > uix ? uie : uix;
1026 #pragma omp atomic compare relaxed
1027   uix = uie < uix ? uie : uix;
1028 #pragma omp atomic compare relaxed
1029   if (uix > uie)
1030     uix = uie;
1031 #pragma omp atomic compare relaxed
1032   if (uix < uie)
1033     uix = uie;
1034 #pragma omp atomic compare relaxed
1035   if (uie > uix)
1036     uix = uie;
1037 #pragma omp atomic compare relaxed
1038   if (uie < uix)
1039     uix = uie;
1040 
1041 #pragma omp atomic compare relaxed
1042   uix = uix == uie ? uid : uix;
1043 #pragma omp atomic compare relaxed
1044   uix = uie == uix ? uid : uix;
1045 #pragma omp atomic compare relaxed
1046   if (uix == uie)
1047     uix = uid;
1048 #pragma omp atomic compare relaxed
1049   if (uie == uix)
1050     uix = uid;
1051 
1052 #pragma omp atomic compare release
1053   ix = ix > ie ? ie : ix;
1054 #pragma omp atomic compare release
1055   ix = ix < ie ? ie : ix;
1056 #pragma omp atomic compare release
1057   ix = ie > ix ? ie : ix;
1058 #pragma omp atomic compare release
1059   ix = ie < ix ? ie : ix;
1060 #pragma omp atomic compare release
1061   if (ix > ie)
1062     ix = ie;
1063 #pragma omp atomic compare release
1064   if (ix < ie)
1065     ix = ie;
1066 #pragma omp atomic compare release
1067   if (ie > ix)
1068     ix = ie;
1069 #pragma omp atomic compare release
1070   if (ie < ix)
1071     ix = ie;
1072 
1073 #pragma omp atomic compare release
1074   ix = ix == ie ? id : ix;
1075 #pragma omp atomic compare release
1076   ix = ie == ix ? id : ix;
1077 #pragma omp atomic compare release
1078   if (ix == ie)
1079     ix = id;
1080 #pragma omp atomic compare release
1081   if (ie == ix)
1082     ix = id;
1083 
1084 #pragma omp atomic compare release
1085   uix = uix > uie ? uie : uix;
1086 #pragma omp atomic compare release
1087   uix = uix < uie ? uie : uix;
1088 #pragma omp atomic compare release
1089   uix = uie > uix ? uie : uix;
1090 #pragma omp atomic compare release
1091   uix = uie < uix ? uie : uix;
1092 #pragma omp atomic compare release
1093   if (uix > uie)
1094     uix = uie;
1095 #pragma omp atomic compare release
1096   if (uix < uie)
1097     uix = uie;
1098 #pragma omp atomic compare release
1099   if (uie > uix)
1100     uix = uie;
1101 #pragma omp atomic compare release
1102   if (uie < uix)
1103     uix = uie;
1104 
1105 #pragma omp atomic compare release
1106   uix = uix == uie ? uid : uix;
1107 #pragma omp atomic compare release
1108   uix = uie == uix ? uid : uix;
1109 #pragma omp atomic compare release
1110   if (uix == uie)
1111     uix = uid;
1112 #pragma omp atomic compare release
1113   if (uie == uix)
1114     uix = uid;
1115 
1116 #pragma omp atomic compare seq_cst
1117   ix = ix > ie ? ie : ix;
1118 #pragma omp atomic compare seq_cst
1119   ix = ix < ie ? ie : ix;
1120 #pragma omp atomic compare seq_cst
1121   ix = ie > ix ? ie : ix;
1122 #pragma omp atomic compare seq_cst
1123   ix = ie < ix ? ie : ix;
1124 #pragma omp atomic compare seq_cst
1125   if (ix > ie)
1126     ix = ie;
1127 #pragma omp atomic compare seq_cst
1128   if (ix < ie)
1129     ix = ie;
1130 #pragma omp atomic compare seq_cst
1131   if (ie > ix)
1132     ix = ie;
1133 #pragma omp atomic compare seq_cst
1134   if (ie < ix)
1135     ix = ie;
1136 
1137 #pragma omp atomic compare seq_cst
1138   ix = ix == ie ? id : ix;
1139 #pragma omp atomic compare seq_cst
1140   ix = ie == ix ? id : ix;
1141 #pragma omp atomic compare seq_cst
1142   if (ix == ie)
1143     ix = id;
1144 #pragma omp atomic compare seq_cst
1145   if (ie == ix)
1146     ix = id;
1147 
1148 #pragma omp atomic compare seq_cst
1149   uix = uix > uie ? uie : uix;
1150 #pragma omp atomic compare seq_cst
1151   uix = uix < uie ? uie : uix;
1152 #pragma omp atomic compare seq_cst
1153   uix = uie > uix ? uie : uix;
1154 #pragma omp atomic compare seq_cst
1155   uix = uie < uix ? uie : uix;
1156 #pragma omp atomic compare seq_cst
1157   if (uix > uie)
1158     uix = uie;
1159 #pragma omp atomic compare seq_cst
1160   if (uix < uie)
1161     uix = uie;
1162 #pragma omp atomic compare seq_cst
1163   if (uie > uix)
1164     uix = uie;
1165 #pragma omp atomic compare seq_cst
1166   if (uie < uix)
1167     uix = uie;
1168 
1169 #pragma omp atomic compare seq_cst
1170   uix = uix == uie ? uid : uix;
1171 #pragma omp atomic compare seq_cst
1172   uix = uie == uix ? uid : uix;
1173 #pragma omp atomic compare seq_cst
1174   if (uix == uie)
1175     uix = uid;
1176 #pragma omp atomic compare seq_cst
1177   if (uie == uix)
1178     uix = uid;
1179 
1180 #pragma omp atomic compare
1181   lx = lx > le ? le : lx;
1182 #pragma omp atomic compare
1183   lx = lx < le ? le : lx;
1184 #pragma omp atomic compare
1185   lx = le > lx ? le : lx;
1186 #pragma omp atomic compare
1187   lx = le < lx ? le : lx;
1188 #pragma omp atomic compare
1189   if (lx > le)
1190     lx = le;
1191 #pragma omp atomic compare
1192   if (lx < le)
1193     lx = le;
1194 #pragma omp atomic compare
1195   if (le > lx)
1196     lx = le;
1197 #pragma omp atomic compare
1198   if (le < lx)
1199     lx = le;
1200 
1201 #pragma omp atomic compare
1202   lx = lx == le ? ld : lx;
1203 #pragma omp atomic compare
1204   lx = le == lx ? ld : lx;
1205 #pragma omp atomic compare
1206   if (lx == le)
1207     lx = ld;
1208 #pragma omp atomic compare
1209   if (le == lx)
1210     lx = ld;
1211 
1212 #pragma omp atomic compare
1213   ulx = ulx > ule ? ule : ulx;
1214 #pragma omp atomic compare
1215   ulx = ulx < ule ? ule : ulx;
1216 #pragma omp atomic compare
1217   ulx = ule > ulx ? ule : ulx;
1218 #pragma omp atomic compare
1219   ulx = ule < ulx ? ule : ulx;
1220 #pragma omp atomic compare
1221   if (ulx > ule)
1222     ulx = ule;
1223 #pragma omp atomic compare
1224   if (ulx < ule)
1225     ulx = ule;
1226 #pragma omp atomic compare
1227   if (ule > ulx)
1228     ulx = ule;
1229 #pragma omp atomic compare
1230   if (ule < ulx)
1231     ulx = ule;
1232 
1233 #pragma omp atomic compare
1234   ulx = ulx == ule ? uld : ulx;
1235 #pragma omp atomic compare
1236   ulx = ule == ulx ? uld : ulx;
1237 #pragma omp atomic compare
1238   if (ulx == ule)
1239     ulx = uld;
1240 #pragma omp atomic compare
1241   if (ule == ulx)
1242     ulx = uld;
1243 
1244 #pragma omp atomic compare acq_rel
1245   lx = lx > le ? le : lx;
1246 #pragma omp atomic compare acq_rel
1247   lx = lx < le ? le : lx;
1248 #pragma omp atomic compare acq_rel
1249   lx = le > lx ? le : lx;
1250 #pragma omp atomic compare acq_rel
1251   lx = le < lx ? le : lx;
1252 #pragma omp atomic compare acq_rel
1253   if (lx > le)
1254     lx = le;
1255 #pragma omp atomic compare acq_rel
1256   if (lx < le)
1257     lx = le;
1258 #pragma omp atomic compare acq_rel
1259   if (le > lx)
1260     lx = le;
1261 #pragma omp atomic compare acq_rel
1262   if (le < lx)
1263     lx = le;
1264 
1265 #pragma omp atomic compare acq_rel
1266   lx = lx == le ? ld : lx;
1267 #pragma omp atomic compare acq_rel
1268   lx = le == lx ? ld : lx;
1269 #pragma omp atomic compare acq_rel
1270   if (lx == le)
1271     lx = ld;
1272 #pragma omp atomic compare acq_rel
1273   if (le == lx)
1274     lx = ld;
1275 
1276 #pragma omp atomic compare acq_rel
1277   ulx = ulx > ule ? ule : ulx;
1278 #pragma omp atomic compare acq_rel
1279   ulx = ulx < ule ? ule : ulx;
1280 #pragma omp atomic compare acq_rel
1281   ulx = ule > ulx ? ule : ulx;
1282 #pragma omp atomic compare acq_rel
1283   ulx = ule < ulx ? ule : ulx;
1284 #pragma omp atomic compare acq_rel
1285   if (ulx > ule)
1286     ulx = ule;
1287 #pragma omp atomic compare acq_rel
1288   if (ulx < ule)
1289     ulx = ule;
1290 #pragma omp atomic compare acq_rel
1291   if (ule > ulx)
1292     ulx = ule;
1293 #pragma omp atomic compare acq_rel
1294   if (ule < ulx)
1295     ulx = ule;
1296 
1297 #pragma omp atomic compare acq_rel
1298   ulx = ulx == ule ? uld : ulx;
1299 #pragma omp atomic compare acq_rel
1300   ulx = ule == ulx ? uld : ulx;
1301 #pragma omp atomic compare acq_rel
1302   if (ulx == ule)
1303     ulx = uld;
1304 #pragma omp atomic compare acq_rel
1305   if (ule == ulx)
1306     ulx = uld;
1307 
1308 #pragma omp atomic compare acquire
1309   lx = lx > le ? le : lx;
1310 #pragma omp atomic compare acquire
1311   lx = lx < le ? le : lx;
1312 #pragma omp atomic compare acquire
1313   lx = le > lx ? le : lx;
1314 #pragma omp atomic compare acquire
1315   lx = le < lx ? le : lx;
1316 #pragma omp atomic compare acquire
1317   if (lx > le)
1318     lx = le;
1319 #pragma omp atomic compare acquire
1320   if (lx < le)
1321     lx = le;
1322 #pragma omp atomic compare acquire
1323   if (le > lx)
1324     lx = le;
1325 #pragma omp atomic compare acquire
1326   if (le < lx)
1327     lx = le;
1328 
1329 #pragma omp atomic compare acquire
1330   lx = lx == le ? ld : lx;
1331 #pragma omp atomic compare acquire
1332   lx = le == lx ? ld : lx;
1333 #pragma omp atomic compare acquire
1334   if (lx == le)
1335     lx = ld;
1336 #pragma omp atomic compare acquire
1337   if (le == lx)
1338     lx = ld;
1339 
1340 #pragma omp atomic compare acquire
1341   ulx = ulx > ule ? ule : ulx;
1342 #pragma omp atomic compare acquire
1343   ulx = ulx < ule ? ule : ulx;
1344 #pragma omp atomic compare acquire
1345   ulx = ule > ulx ? ule : ulx;
1346 #pragma omp atomic compare acquire
1347   ulx = ule < ulx ? ule : ulx;
1348 #pragma omp atomic compare acquire
1349   if (ulx > ule)
1350     ulx = ule;
1351 #pragma omp atomic compare acquire
1352   if (ulx < ule)
1353     ulx = ule;
1354 #pragma omp atomic compare acquire
1355   if (ule > ulx)
1356     ulx = ule;
1357 #pragma omp atomic compare acquire
1358   if (ule < ulx)
1359     ulx = ule;
1360 
1361 #pragma omp atomic compare acquire
1362   ulx = ulx == ule ? uld : ulx;
1363 #pragma omp atomic compare acquire
1364   ulx = ule == ulx ? uld : ulx;
1365 #pragma omp atomic compare acquire
1366   if (ulx == ule)
1367     ulx = uld;
1368 #pragma omp atomic compare acquire
1369   if (ule == ulx)
1370     ulx = uld;
1371 
1372 #pragma omp atomic compare relaxed
1373   lx = lx > le ? le : lx;
1374 #pragma omp atomic compare relaxed
1375   lx = lx < le ? le : lx;
1376 #pragma omp atomic compare relaxed
1377   lx = le > lx ? le : lx;
1378 #pragma omp atomic compare relaxed
1379   lx = le < lx ? le : lx;
1380 #pragma omp atomic compare relaxed
1381   if (lx > le)
1382     lx = le;
1383 #pragma omp atomic compare relaxed
1384   if (lx < le)
1385     lx = le;
1386 #pragma omp atomic compare relaxed
1387   if (le > lx)
1388     lx = le;
1389 #pragma omp atomic compare relaxed
1390   if (le < lx)
1391     lx = le;
1392 
1393 #pragma omp atomic compare relaxed
1394   lx = lx == le ? ld : lx;
1395 #pragma omp atomic compare relaxed
1396   lx = le == lx ? ld : lx;
1397 #pragma omp atomic compare relaxed
1398   if (lx == le)
1399     lx = ld;
1400 #pragma omp atomic compare relaxed
1401   if (le == lx)
1402     lx = ld;
1403 
1404 #pragma omp atomic compare relaxed
1405   ulx = ulx > ule ? ule : ulx;
1406 #pragma omp atomic compare relaxed
1407   ulx = ulx < ule ? ule : ulx;
1408 #pragma omp atomic compare relaxed
1409   ulx = ule > ulx ? ule : ulx;
1410 #pragma omp atomic compare relaxed
1411   ulx = ule < ulx ? ule : ulx;
1412 #pragma omp atomic compare relaxed
1413   if (ulx > ule)
1414     ulx = ule;
1415 #pragma omp atomic compare relaxed
1416   if (ulx < ule)
1417     ulx = ule;
1418 #pragma omp atomic compare relaxed
1419   if (ule > ulx)
1420     ulx = ule;
1421 #pragma omp atomic compare relaxed
1422   if (ule < ulx)
1423     ulx = ule;
1424 
1425 #pragma omp atomic compare relaxed
1426   ulx = ulx == ule ? uld : ulx;
1427 #pragma omp atomic compare relaxed
1428   ulx = ule == ulx ? uld : ulx;
1429 #pragma omp atomic compare relaxed
1430   if (ulx == ule)
1431     ulx = uld;
1432 #pragma omp atomic compare relaxed
1433   if (ule == ulx)
1434     ulx = uld;
1435 
1436 #pragma omp atomic compare release
1437   lx = lx > le ? le : lx;
1438 #pragma omp atomic compare release
1439   lx = lx < le ? le : lx;
1440 #pragma omp atomic compare release
1441   lx = le > lx ? le : lx;
1442 #pragma omp atomic compare release
1443   lx = le < lx ? le : lx;
1444 #pragma omp atomic compare release
1445   if (lx > le)
1446     lx = le;
1447 #pragma omp atomic compare release
1448   if (lx < le)
1449     lx = le;
1450 #pragma omp atomic compare release
1451   if (le > lx)
1452     lx = le;
1453 #pragma omp atomic compare release
1454   if (le < lx)
1455     lx = le;
1456 
1457 #pragma omp atomic compare release
1458   lx = lx == le ? ld : lx;
1459 #pragma omp atomic compare release
1460   lx = le == lx ? ld : lx;
1461 #pragma omp atomic compare release
1462   if (lx == le)
1463     lx = ld;
1464 #pragma omp atomic compare release
1465   if (le == lx)
1466     lx = ld;
1467 
1468 #pragma omp atomic compare release
1469   ulx = ulx > ule ? ule : ulx;
1470 #pragma omp atomic compare release
1471   ulx = ulx < ule ? ule : ulx;
1472 #pragma omp atomic compare release
1473   ulx = ule > ulx ? ule : ulx;
1474 #pragma omp atomic compare release
1475   ulx = ule < ulx ? ule : ulx;
1476 #pragma omp atomic compare release
1477   if (ulx > ule)
1478     ulx = ule;
1479 #pragma omp atomic compare release
1480   if (ulx < ule)
1481     ulx = ule;
1482 #pragma omp atomic compare release
1483   if (ule > ulx)
1484     ulx = ule;
1485 #pragma omp atomic compare release
1486   if (ule < ulx)
1487     ulx = ule;
1488 
1489 #pragma omp atomic compare release
1490   ulx = ulx == ule ? uld : ulx;
1491 #pragma omp atomic compare release
1492   ulx = ule == ulx ? uld : ulx;
1493 #pragma omp atomic compare release
1494   if (ulx == ule)
1495     ulx = uld;
1496 #pragma omp atomic compare release
1497   if (ule == ulx)
1498     ulx = uld;
1499 
1500 #pragma omp atomic compare seq_cst
1501   lx = lx > le ? le : lx;
1502 #pragma omp atomic compare seq_cst
1503   lx = lx < le ? le : lx;
1504 #pragma omp atomic compare seq_cst
1505   lx = le > lx ? le : lx;
1506 #pragma omp atomic compare seq_cst
1507   lx = le < lx ? le : lx;
1508 #pragma omp atomic compare seq_cst
1509   if (lx > le)
1510     lx = le;
1511 #pragma omp atomic compare seq_cst
1512   if (lx < le)
1513     lx = le;
1514 #pragma omp atomic compare seq_cst
1515   if (le > lx)
1516     lx = le;
1517 #pragma omp atomic compare seq_cst
1518   if (le < lx)
1519     lx = le;
1520 
1521 #pragma omp atomic compare seq_cst
1522   lx = lx == le ? ld : lx;
1523 #pragma omp atomic compare seq_cst
1524   lx = le == lx ? ld : lx;
1525 #pragma omp atomic compare seq_cst
1526   if (lx == le)
1527     lx = ld;
1528 #pragma omp atomic compare seq_cst
1529   if (le == lx)
1530     lx = ld;
1531 
1532 #pragma omp atomic compare seq_cst
1533   ulx = ulx > ule ? ule : ulx;
1534 #pragma omp atomic compare seq_cst
1535   ulx = ulx < ule ? ule : ulx;
1536 #pragma omp atomic compare seq_cst
1537   ulx = ule > ulx ? ule : ulx;
1538 #pragma omp atomic compare seq_cst
1539   ulx = ule < ulx ? ule : ulx;
1540 #pragma omp atomic compare seq_cst
1541   if (ulx > ule)
1542     ulx = ule;
1543 #pragma omp atomic compare seq_cst
1544   if (ulx < ule)
1545     ulx = ule;
1546 #pragma omp atomic compare seq_cst
1547   if (ule > ulx)
1548     ulx = ule;
1549 #pragma omp atomic compare seq_cst
1550   if (ule < ulx)
1551     ulx = ule;
1552 
1553 #pragma omp atomic compare seq_cst
1554   ulx = ulx == ule ? uld : ulx;
1555 #pragma omp atomic compare seq_cst
1556   ulx = ule == ulx ? uld : ulx;
1557 #pragma omp atomic compare seq_cst
1558   if (ulx == ule)
1559     ulx = uld;
1560 #pragma omp atomic compare seq_cst
1561   if (ule == ulx)
1562     ulx = uld;
1563 
1564 #pragma omp atomic compare
1565   llx = llx > lle ? lle : llx;
1566 #pragma omp atomic compare
1567   llx = llx < lle ? lle : llx;
1568 #pragma omp atomic compare
1569   llx = lle > llx ? lle : llx;
1570 #pragma omp atomic compare
1571   llx = lle < llx ? lle : llx;
1572 #pragma omp atomic compare
1573   if (llx > lle)
1574     llx = lle;
1575 #pragma omp atomic compare
1576   if (llx < lle)
1577     llx = lle;
1578 #pragma omp atomic compare
1579   if (lle > llx)
1580     llx = lle;
1581 #pragma omp atomic compare
1582   if (lle < llx)
1583     llx = lle;
1584 
1585 #pragma omp atomic compare
1586   llx = llx == lle ? lld : llx;
1587 #pragma omp atomic compare
1588   llx = lle == llx ? lld : llx;
1589 #pragma omp atomic compare
1590   if (llx == lle)
1591     llx = lld;
1592 #pragma omp atomic compare
1593   if (lle == llx)
1594     llx = lld;
1595 
1596 #pragma omp atomic compare
1597   ullx = ullx > ulle ? ulle : ullx;
1598 #pragma omp atomic compare
1599   ullx = ullx < ulle ? ulle : ullx;
1600 #pragma omp atomic compare
1601   ullx = ulle > ullx ? ulle : ullx;
1602 #pragma omp atomic compare
1603   ullx = ulle < ullx ? ulle : ullx;
1604 #pragma omp atomic compare
1605   if (ullx > ulle)
1606     ullx = ulle;
1607 #pragma omp atomic compare
1608   if (ullx < ulle)
1609     ullx = ulle;
1610 #pragma omp atomic compare
1611   if (ulle > ullx)
1612     ullx = ulle;
1613 #pragma omp atomic compare
1614   if (ulle < ullx)
1615     ullx = ulle;
1616 
1617 #pragma omp atomic compare
1618   ullx = ullx == ulle ? ulld : ullx;
1619 #pragma omp atomic compare
1620   ullx = ulle == ullx ? ulld : ullx;
1621 #pragma omp atomic compare
1622   if (ullx == ulle)
1623     ullx = ulld;
1624 #pragma omp atomic compare
1625   if (ulle == ullx)
1626     ullx = ulld;
1627 
1628 #pragma omp atomic compare acq_rel
1629   llx = llx > lle ? lle : llx;
1630 #pragma omp atomic compare acq_rel
1631   llx = llx < lle ? lle : llx;
1632 #pragma omp atomic compare acq_rel
1633   llx = lle > llx ? lle : llx;
1634 #pragma omp atomic compare acq_rel
1635   llx = lle < llx ? lle : llx;
1636 #pragma omp atomic compare acq_rel
1637   if (llx > lle)
1638     llx = lle;
1639 #pragma omp atomic compare acq_rel
1640   if (llx < lle)
1641     llx = lle;
1642 #pragma omp atomic compare acq_rel
1643   if (lle > llx)
1644     llx = lle;
1645 #pragma omp atomic compare acq_rel
1646   if (lle < llx)
1647     llx = lle;
1648 
1649 #pragma omp atomic compare acq_rel
1650   llx = llx == lle ? lld : llx;
1651 #pragma omp atomic compare acq_rel
1652   llx = lle == llx ? lld : llx;
1653 #pragma omp atomic compare acq_rel
1654   if (llx == lle)
1655     llx = lld;
1656 #pragma omp atomic compare acq_rel
1657   if (lle == llx)
1658     llx = lld;
1659 
1660 #pragma omp atomic compare acq_rel
1661   ullx = ullx > ulle ? ulle : ullx;
1662 #pragma omp atomic compare acq_rel
1663   ullx = ullx < ulle ? ulle : ullx;
1664 #pragma omp atomic compare acq_rel
1665   ullx = ulle > ullx ? ulle : ullx;
1666 #pragma omp atomic compare acq_rel
1667   ullx = ulle < ullx ? ulle : ullx;
1668 #pragma omp atomic compare acq_rel
1669   if (ullx > ulle)
1670     ullx = ulle;
1671 #pragma omp atomic compare acq_rel
1672   if (ullx < ulle)
1673     ullx = ulle;
1674 #pragma omp atomic compare acq_rel
1675   if (ulle > ullx)
1676     ullx = ulle;
1677 #pragma omp atomic compare acq_rel
1678   if (ulle < ullx)
1679     ullx = ulle;
1680 
1681 #pragma omp atomic compare acq_rel
1682   ullx = ullx == ulle ? ulld : ullx;
1683 #pragma omp atomic compare acq_rel
1684   ullx = ulle == ullx ? ulld : ullx;
1685 #pragma omp atomic compare acq_rel
1686   if (ullx == ulle)
1687     ullx = ulld;
1688 #pragma omp atomic compare acq_rel
1689   if (ulle == ullx)
1690     ullx = ulld;
1691 
1692 #pragma omp atomic compare acquire
1693   llx = llx > lle ? lle : llx;
1694 #pragma omp atomic compare acquire
1695   llx = llx < lle ? lle : llx;
1696 #pragma omp atomic compare acquire
1697   llx = lle > llx ? lle : llx;
1698 #pragma omp atomic compare acquire
1699   llx = lle < llx ? lle : llx;
1700 #pragma omp atomic compare acquire
1701   if (llx > lle)
1702     llx = lle;
1703 #pragma omp atomic compare acquire
1704   if (llx < lle)
1705     llx = lle;
1706 #pragma omp atomic compare acquire
1707   if (lle > llx)
1708     llx = lle;
1709 #pragma omp atomic compare acquire
1710   if (lle < llx)
1711     llx = lle;
1712 
1713 #pragma omp atomic compare acquire
1714   llx = llx == lle ? lld : llx;
1715 #pragma omp atomic compare acquire
1716   llx = lle == llx ? lld : llx;
1717 #pragma omp atomic compare acquire
1718   if (llx == lle)
1719     llx = lld;
1720 #pragma omp atomic compare acquire
1721   if (lle == llx)
1722     llx = lld;
1723 
1724 #pragma omp atomic compare acquire
1725   ullx = ullx > ulle ? ulle : ullx;
1726 #pragma omp atomic compare acquire
1727   ullx = ullx < ulle ? ulle : ullx;
1728 #pragma omp atomic compare acquire
1729   ullx = ulle > ullx ? ulle : ullx;
1730 #pragma omp atomic compare acquire
1731   ullx = ulle < ullx ? ulle : ullx;
1732 #pragma omp atomic compare acquire
1733   if (ullx > ulle)
1734     ullx = ulle;
1735 #pragma omp atomic compare acquire
1736   if (ullx < ulle)
1737     ullx = ulle;
1738 #pragma omp atomic compare acquire
1739   if (ulle > ullx)
1740     ullx = ulle;
1741 #pragma omp atomic compare acquire
1742   if (ulle < ullx)
1743     ullx = ulle;
1744 
1745 #pragma omp atomic compare acquire
1746   ullx = ullx == ulle ? ulld : ullx;
1747 #pragma omp atomic compare acquire
1748   ullx = ulle == ullx ? ulld : ullx;
1749 #pragma omp atomic compare acquire
1750   if (ullx == ulle)
1751     ullx = ulld;
1752 #pragma omp atomic compare acquire
1753   if (ulle == ullx)
1754     ullx = ulld;
1755 
1756 #pragma omp atomic compare relaxed
1757   llx = llx > lle ? lle : llx;
1758 #pragma omp atomic compare relaxed
1759   llx = llx < lle ? lle : llx;
1760 #pragma omp atomic compare relaxed
1761   llx = lle > llx ? lle : llx;
1762 #pragma omp atomic compare relaxed
1763   llx = lle < llx ? lle : llx;
1764 #pragma omp atomic compare relaxed
1765   if (llx > lle)
1766     llx = lle;
1767 #pragma omp atomic compare relaxed
1768   if (llx < lle)
1769     llx = lle;
1770 #pragma omp atomic compare relaxed
1771   if (lle > llx)
1772     llx = lle;
1773 #pragma omp atomic compare relaxed
1774   if (lle < llx)
1775     llx = lle;
1776 
1777 #pragma omp atomic compare relaxed
1778   llx = llx == lle ? lld : llx;
1779 #pragma omp atomic compare relaxed
1780   llx = lle == llx ? lld : llx;
1781 #pragma omp atomic compare relaxed
1782   if (llx == lle)
1783     llx = lld;
1784 #pragma omp atomic compare relaxed
1785   if (lle == llx)
1786     llx = lld;
1787 
1788 #pragma omp atomic compare relaxed
1789   ullx = ullx > ulle ? ulle : ullx;
1790 #pragma omp atomic compare relaxed
1791   ullx = ullx < ulle ? ulle : ullx;
1792 #pragma omp atomic compare relaxed
1793   ullx = ulle > ullx ? ulle : ullx;
1794 #pragma omp atomic compare relaxed
1795   ullx = ulle < ullx ? ulle : ullx;
1796 #pragma omp atomic compare relaxed
1797   if (ullx > ulle)
1798     ullx = ulle;
1799 #pragma omp atomic compare relaxed
1800   if (ullx < ulle)
1801     ullx = ulle;
1802 #pragma omp atomic compare relaxed
1803   if (ulle > ullx)
1804     ullx = ulle;
1805 #pragma omp atomic compare relaxed
1806   if (ulle < ullx)
1807     ullx = ulle;
1808 
1809 #pragma omp atomic compare relaxed
1810   ullx = ullx == ulle ? ulld : ullx;
1811 #pragma omp atomic compare relaxed
1812   ullx = ulle == ullx ? ulld : ullx;
1813 #pragma omp atomic compare relaxed
1814   if (ullx == ulle)
1815     ullx = ulld;
1816 #pragma omp atomic compare relaxed
1817   if (ulle == ullx)
1818     ullx = ulld;
1819 
1820 #pragma omp atomic compare release
1821   llx = llx > lle ? lle : llx;
1822 #pragma omp atomic compare release
1823   llx = llx < lle ? lle : llx;
1824 #pragma omp atomic compare release
1825   llx = lle > llx ? lle : llx;
1826 #pragma omp atomic compare release
1827   llx = lle < llx ? lle : llx;
1828 #pragma omp atomic compare release
1829   if (llx > lle)
1830     llx = lle;
1831 #pragma omp atomic compare release
1832   if (llx < lle)
1833     llx = lle;
1834 #pragma omp atomic compare release
1835   if (lle > llx)
1836     llx = lle;
1837 #pragma omp atomic compare release
1838   if (lle < llx)
1839     llx = lle;
1840 
1841 #pragma omp atomic compare release
1842   llx = llx == lle ? lld : llx;
1843 #pragma omp atomic compare release
1844   llx = lle == llx ? lld : llx;
1845 #pragma omp atomic compare release
1846   if (llx == lle)
1847     llx = lld;
1848 #pragma omp atomic compare release
1849   if (lle == llx)
1850     llx = lld;
1851 
1852 #pragma omp atomic compare release
1853   ullx = ullx > ulle ? ulle : ullx;
1854 #pragma omp atomic compare release
1855   ullx = ullx < ulle ? ulle : ullx;
1856 #pragma omp atomic compare release
1857   ullx = ulle > ullx ? ulle : ullx;
1858 #pragma omp atomic compare release
1859   ullx = ulle < ullx ? ulle : ullx;
1860 #pragma omp atomic compare release
1861   if (ullx > ulle)
1862     ullx = ulle;
1863 #pragma omp atomic compare release
1864   if (ullx < ulle)
1865     ullx = ulle;
1866 #pragma omp atomic compare release
1867   if (ulle > ullx)
1868     ullx = ulle;
1869 #pragma omp atomic compare release
1870   if (ulle < ullx)
1871     ullx = ulle;
1872 
1873 #pragma omp atomic compare release
1874   ullx = ullx == ulle ? ulld : ullx;
1875 #pragma omp atomic compare release
1876   ullx = ulle == ullx ? ulld : ullx;
1877 #pragma omp atomic compare release
1878   if (ullx == ulle)
1879     ullx = ulld;
1880 #pragma omp atomic compare release
1881   if (ulle == ullx)
1882     ullx = ulld;
1883 
1884 #pragma omp atomic compare seq_cst
1885   llx = llx > lle ? lle : llx;
1886 #pragma omp atomic compare seq_cst
1887   llx = llx < lle ? lle : llx;
1888 #pragma omp atomic compare seq_cst
1889   llx = lle > llx ? lle : llx;
1890 #pragma omp atomic compare seq_cst
1891   llx = lle < llx ? lle : llx;
1892 #pragma omp atomic compare seq_cst
1893   if (llx > lle)
1894     llx = lle;
1895 #pragma omp atomic compare seq_cst
1896   if (llx < lle)
1897     llx = lle;
1898 #pragma omp atomic compare seq_cst
1899   if (lle > llx)
1900     llx = lle;
1901 #pragma omp atomic compare seq_cst
1902   if (lle < llx)
1903     llx = lle;
1904 
1905 #pragma omp atomic compare seq_cst
1906   llx = llx == lle ? lld : llx;
1907 #pragma omp atomic compare seq_cst
1908   llx = lle == llx ? lld : llx;
1909 #pragma omp atomic compare seq_cst
1910   if (llx == lle)
1911     llx = lld;
1912 #pragma omp atomic compare seq_cst
1913   if (lle == llx)
1914     llx = lld;
1915 
1916 #pragma omp atomic compare seq_cst
1917   ullx = ullx > ulle ? ulle : ullx;
1918 #pragma omp atomic compare seq_cst
1919   ullx = ullx < ulle ? ulle : ullx;
1920 #pragma omp atomic compare seq_cst
1921   ullx = ulle > ullx ? ulle : ullx;
1922 #pragma omp atomic compare seq_cst
1923   ullx = ulle < ullx ? ulle : ullx;
1924 #pragma omp atomic compare seq_cst
1925   if (ullx > ulle)
1926     ullx = ulle;
1927 #pragma omp atomic compare seq_cst
1928   if (ullx < ulle)
1929     ullx = ulle;
1930 #pragma omp atomic compare seq_cst
1931   if (ulle > ullx)
1932     ullx = ulle;
1933 #pragma omp atomic compare seq_cst
1934   if (ulle < ullx)
1935     ullx = ulle;
1936 
1937 #pragma omp atomic compare seq_cst
1938   ullx = ullx == ulle ? ulld : ullx;
1939 #pragma omp atomic compare seq_cst
1940   ullx = ulle == ullx ? ulld : ullx;
1941 #pragma omp atomic compare seq_cst
1942   if (ullx == ulle)
1943     ullx = ulld;
1944 #pragma omp atomic compare seq_cst
1945   if (ulle == ullx)
1946     ullx = ulld;
1947 
1948 #pragma omp atomic compare
1949   fx = fx > fe ? fe : fx;
1950 #pragma omp atomic compare
1951   fx = fx < fe ? fe : fx;
1952 #pragma omp atomic compare
1953   fx = fe > fx ? fe : fx;
1954 #pragma omp atomic compare
1955   fx = fe < fx ? fe : fx;
1956 #pragma omp atomic compare
1957   if (fx > fe)
1958     fx = fe;
1959 #pragma omp atomic compare
1960   if (fx < fe)
1961     fx = fe;
1962 #pragma omp atomic compare
1963   if (fe > fx)
1964     fx = fe;
1965 #pragma omp atomic compare
1966   if (fe < fx)
1967     fx = fe;
1968 
1969 #pragma omp atomic compare acq_rel
1970   fx = fx > fe ? fe : fx;
1971 #pragma omp atomic compare acq_rel
1972   fx = fx < fe ? fe : fx;
1973 #pragma omp atomic compare acq_rel
1974   fx = fe > fx ? fe : fx;
1975 #pragma omp atomic compare acq_rel
1976   fx = fe < fx ? fe : fx;
1977 #pragma omp atomic compare acq_rel
1978   if (fx > fe)
1979     fx = fe;
1980 #pragma omp atomic compare acq_rel
1981   if (fx < fe)
1982     fx = fe;
1983 #pragma omp atomic compare acq_rel
1984   if (fe > fx)
1985     fx = fe;
1986 #pragma omp atomic compare acq_rel
1987   if (fe < fx)
1988     fx = fe;
1989 
1990 #pragma omp atomic compare acquire
1991   fx = fx > fe ? fe : fx;
1992 #pragma omp atomic compare acquire
1993   fx = fx < fe ? fe : fx;
1994 #pragma omp atomic compare acquire
1995   fx = fe > fx ? fe : fx;
1996 #pragma omp atomic compare acquire
1997   fx = fe < fx ? fe : fx;
1998 #pragma omp atomic compare acquire
1999   if (fx > fe)
2000     fx = fe;
2001 #pragma omp atomic compare acquire
2002   if (fx < fe)
2003     fx = fe;
2004 #pragma omp atomic compare acquire
2005   if (fe > fx)
2006     fx = fe;
2007 #pragma omp atomic compare acquire
2008   if (fe < fx)
2009     fx = fe;
2010 
2011 #pragma omp atomic compare relaxed
2012   fx = fx > fe ? fe : fx;
2013 #pragma omp atomic compare relaxed
2014   fx = fx < fe ? fe : fx;
2015 #pragma omp atomic compare relaxed
2016   fx = fe > fx ? fe : fx;
2017 #pragma omp atomic compare relaxed
2018   fx = fe < fx ? fe : fx;
2019 #pragma omp atomic compare relaxed
2020   if (fx > fe)
2021     fx = fe;
2022 #pragma omp atomic compare relaxed
2023   if (fx < fe)
2024     fx = fe;
2025 #pragma omp atomic compare relaxed
2026   if (fe > fx)
2027     fx = fe;
2028 #pragma omp atomic compare relaxed
2029   if (fe < fx)
2030     fx = fe;
2031 
2032 #pragma omp atomic compare release
2033   fx = fx > fe ? fe : fx;
2034 #pragma omp atomic compare release
2035   fx = fx < fe ? fe : fx;
2036 #pragma omp atomic compare release
2037   fx = fe > fx ? fe : fx;
2038 #pragma omp atomic compare release
2039   fx = fe < fx ? fe : fx;
2040 #pragma omp atomic compare release
2041   if (fx > fe)
2042     fx = fe;
2043 #pragma omp atomic compare release
2044   if (fx < fe)
2045     fx = fe;
2046 #pragma omp atomic compare release
2047   if (fe > fx)
2048     fx = fe;
2049 #pragma omp atomic compare release
2050   if (fe < fx)
2051     fx = fe;
2052 
2053 #pragma omp atomic compare seq_cst
2054   fx = fx > fe ? fe : fx;
2055 #pragma omp atomic compare seq_cst
2056   fx = fx < fe ? fe : fx;
2057 #pragma omp atomic compare seq_cst
2058   fx = fe > fx ? fe : fx;
2059 #pragma omp atomic compare seq_cst
2060   fx = fe < fx ? fe : fx;
2061 #pragma omp atomic compare seq_cst
2062   if (fx > fe)
2063     fx = fe;
2064 #pragma omp atomic compare seq_cst
2065   if (fx < fe)
2066     fx = fe;
2067 #pragma omp atomic compare seq_cst
2068   if (fe > fx)
2069     fx = fe;
2070 #pragma omp atomic compare seq_cst
2071   if (fe < fx)
2072     fx = fe;
2073 
2074 #pragma omp atomic compare
2075   dx = dx > de ? de : dx;
2076 #pragma omp atomic compare
2077   dx = dx < de ? de : dx;
2078 #pragma omp atomic compare
2079   dx = de > dx ? de : dx;
2080 #pragma omp atomic compare
2081   dx = de < dx ? de : dx;
2082 #pragma omp atomic compare
2083   if (dx > de)
2084     dx = de;
2085 #pragma omp atomic compare
2086   if (dx < de)
2087     dx = de;
2088 #pragma omp atomic compare
2089   if (de > dx)
2090     dx = de;
2091 #pragma omp atomic compare
2092   if (de < dx)
2093     dx = de;
2094 
2095 #pragma omp atomic compare acq_rel
2096   dx = dx > de ? de : dx;
2097 #pragma omp atomic compare acq_rel
2098   dx = dx < de ? de : dx;
2099 #pragma omp atomic compare acq_rel
2100   dx = de > dx ? de : dx;
2101 #pragma omp atomic compare acq_rel
2102   dx = de < dx ? de : dx;
2103 #pragma omp atomic compare acq_rel
2104   if (dx > de)
2105     dx = de;
2106 #pragma omp atomic compare acq_rel
2107   if (dx < de)
2108     dx = de;
2109 #pragma omp atomic compare acq_rel
2110   if (de > dx)
2111     dx = de;
2112 #pragma omp atomic compare acq_rel
2113   if (de < dx)
2114     dx = de;
2115 
2116 #pragma omp atomic compare acquire
2117   dx = dx > de ? de : dx;
2118 #pragma omp atomic compare acquire
2119   dx = dx < de ? de : dx;
2120 #pragma omp atomic compare acquire
2121   dx = de > dx ? de : dx;
2122 #pragma omp atomic compare acquire
2123   dx = de < dx ? de : dx;
2124 #pragma omp atomic compare acquire
2125   if (dx > de)
2126     dx = de;
2127 #pragma omp atomic compare acquire
2128   if (dx < de)
2129     dx = de;
2130 #pragma omp atomic compare acquire
2131   if (de > dx)
2132     dx = de;
2133 #pragma omp atomic compare acquire
2134   if (de < dx)
2135     dx = de;
2136 
2137 #pragma omp atomic compare relaxed
2138   dx = dx > de ? de : dx;
2139 #pragma omp atomic compare relaxed
2140   dx = dx < de ? de : dx;
2141 #pragma omp atomic compare relaxed
2142   dx = de > dx ? de : dx;
2143 #pragma omp atomic compare relaxed
2144   dx = de < dx ? de : dx;
2145 #pragma omp atomic compare relaxed
2146   if (dx > de)
2147     dx = de;
2148 #pragma omp atomic compare relaxed
2149   if (dx < de)
2150     dx = de;
2151 #pragma omp atomic compare relaxed
2152   if (de > dx)
2153     dx = de;
2154 #pragma omp atomic compare relaxed
2155   if (de < dx)
2156     dx = de;
2157 
2158 #pragma omp atomic compare release
2159   dx = dx > de ? de : dx;
2160 #pragma omp atomic compare release
2161   dx = dx < de ? de : dx;
2162 #pragma omp atomic compare release
2163   dx = de > dx ? de : dx;
2164 #pragma omp atomic compare release
2165   dx = de < dx ? de : dx;
2166 #pragma omp atomic compare release
2167   if (dx > de)
2168     dx = de;
2169 #pragma omp atomic compare release
2170   if (dx < de)
2171     dx = de;
2172 #pragma omp atomic compare release
2173   if (de > dx)
2174     dx = de;
2175 #pragma omp atomic compare release
2176   if (de < dx)
2177     dx = de;
2178 
2179 #pragma omp atomic compare seq_cst
2180   dx = dx > de ? de : dx;
2181 #pragma omp atomic compare seq_cst
2182   dx = dx < de ? de : dx;
2183 #pragma omp atomic compare seq_cst
2184   dx = de > dx ? de : dx;
2185 #pragma omp atomic compare seq_cst
2186   dx = de < dx ? de : dx;
2187 #pragma omp atomic compare seq_cst
2188   if (dx > de)
2189     dx = de;
2190 #pragma omp atomic compare seq_cst
2191   if (dx < de)
2192     dx = de;
2193 #pragma omp atomic compare seq_cst
2194   if (de > dx)
2195     dx = de;
2196 #pragma omp atomic compare seq_cst
2197   if (de < dx)
2198     dx = de;
2199 }
2200 
bar()2201 void bar() {
2202   char cx, cv, cr, ce, cd;
2203   unsigned char ucx, ucv, ucr, uce, ucd;
2204   short sx, sv, sr, se, sd;
2205   unsigned short usx, usv, usr, use, usd;
2206   int ix, iv, ir, ie, id;
2207   unsigned int uix, uiv, uir, uie, uid;
2208   long lx, lv, lr, le, ld;
2209   unsigned long ulx, ulv, ulr, ule, uld;
2210   long long llx, llv, llr, lle, lld;
2211   unsigned long long ullx, ullv, ullr, ulle, ulld;
2212   float fx, fv, fe, fd;
2213   double dx, dv, de, dd;
2214 
2215 #pragma omp atomic compare capture
2216   {
2217     cv = cx;
2218     if (ce > cx) {
2219       cx = ce;
2220     }
2221   }
2222 #pragma omp atomic compare capture
2223   {
2224     cv = cx;
2225     if (cx > ce) {
2226       cx = ce;
2227     }
2228   }
2229 #pragma omp atomic compare capture
2230   {
2231     cv = cx;
2232     if (ce < cx) {
2233       cx = ce;
2234     }
2235   }
2236 #pragma omp atomic compare capture
2237   {
2238     cv = cx;
2239     if (cx < ce) {
2240       cx = ce;
2241     }
2242   }
2243 #pragma omp atomic compare capture
2244   {
2245     cv = cx;
2246     if (cx == ce) {
2247       cx = cd;
2248     }
2249   }
2250 #pragma omp atomic compare capture
2251   {
2252     cv = cx;
2253     if (ce == cx) {
2254       cx = cd;
2255     }
2256   }
2257 #pragma omp atomic compare capture
2258   {
2259     if (ce > cx) {
2260       cx = ce;
2261     }
2262     cv = cx;
2263   }
2264 #pragma omp atomic compare capture
2265   {
2266     if (cx > ce) {
2267       cx = ce;
2268     }
2269     cv = cx;
2270   }
2271 #pragma omp atomic compare capture
2272   {
2273     if (ce < cx) {
2274       cx = ce;
2275     }
2276     cv = cx;
2277   }
2278 #pragma omp atomic compare capture
2279   {
2280     if (cx < ce) {
2281       cx = ce;
2282     }
2283     cv = cx;
2284   }
2285 #pragma omp atomic compare capture
2286   {
2287     if (cx == ce) {
2288       cx = cd;
2289     }
2290     cv = cx;
2291   }
2292 #pragma omp atomic compare capture
2293   {
2294     if (ce == cx) {
2295       cx = cd;
2296     }
2297     cv = cx;
2298   }
2299 #pragma omp atomic compare capture
2300   if (cx == ce) {
2301     cx = cd;
2302   } else {
2303     cv = cx;
2304   }
2305 #pragma omp atomic compare capture
2306   if (ce == cx) {
2307     cx = cd;
2308   } else {
2309     cv = cx;
2310   }
2311 #pragma omp atomic compare capture
2312   {
2313     cr = cx == ce;
2314     if (cr) {
2315       cx = cd;
2316     }
2317   }
2318 #pragma omp atomic compare capture
2319   {
2320     cr = ce == cx;
2321     if (cr) {
2322       cx = cd;
2323     }
2324   }
2325 #pragma omp atomic compare capture
2326   {
2327     cr = cx == ce;
2328     if (cr) {
2329       cx = cd;
2330     } else {
2331       cv = cx;
2332     }
2333   }
2334 #pragma omp atomic compare capture
2335   {
2336     cr = ce == cx;
2337     if (cr) {
2338       cx = cd;
2339     } else {
2340       cv = cx;
2341     }
2342   }
2343 
2344 #pragma omp atomic compare capture acq_rel
2345   {
2346     cv = cx;
2347     if (ce > cx) {
2348       cx = ce;
2349     }
2350   }
2351 #pragma omp atomic compare capture acq_rel
2352   {
2353     cv = cx;
2354     if (cx > ce) {
2355       cx = ce;
2356     }
2357   }
2358 #pragma omp atomic compare capture acq_rel
2359   {
2360     cv = cx;
2361     if (ce < cx) {
2362       cx = ce;
2363     }
2364   }
2365 #pragma omp atomic compare capture acq_rel
2366   {
2367     cv = cx;
2368     if (cx < ce) {
2369       cx = ce;
2370     }
2371   }
2372 #pragma omp atomic compare capture acq_rel
2373   {
2374     cv = cx;
2375     if (cx == ce) {
2376       cx = cd;
2377     }
2378   }
2379 #pragma omp atomic compare capture acq_rel
2380   {
2381     cv = cx;
2382     if (ce == cx) {
2383       cx = cd;
2384     }
2385   }
2386 #pragma omp atomic compare capture acq_rel
2387   {
2388     if (ce > cx) {
2389       cx = ce;
2390     }
2391     cv = cx;
2392   }
2393 #pragma omp atomic compare capture acq_rel
2394   {
2395     if (cx > ce) {
2396       cx = ce;
2397     }
2398     cv = cx;
2399   }
2400 #pragma omp atomic compare capture acq_rel
2401   {
2402     if (ce < cx) {
2403       cx = ce;
2404     }
2405     cv = cx;
2406   }
2407 #pragma omp atomic compare capture acq_rel
2408   {
2409     if (cx < ce) {
2410       cx = ce;
2411     }
2412     cv = cx;
2413   }
2414 #pragma omp atomic compare capture acq_rel
2415   {
2416     if (cx == ce) {
2417       cx = cd;
2418     }
2419     cv = cx;
2420   }
2421 #pragma omp atomic compare capture acq_rel
2422   {
2423     if (ce == cx) {
2424       cx = cd;
2425     }
2426     cv = cx;
2427   }
2428 #pragma omp atomic compare capture acq_rel
2429   if (cx == ce) {
2430     cx = cd;
2431   } else {
2432     cv = cx;
2433   }
2434 #pragma omp atomic compare capture acq_rel
2435   if (ce == cx) {
2436     cx = cd;
2437   } else {
2438     cv = cx;
2439   }
2440 #pragma omp atomic compare capture acq_rel
2441   {
2442     cr = cx == ce;
2443     if (cr) {
2444       cx = cd;
2445     }
2446   }
2447 #pragma omp atomic compare capture acq_rel
2448   {
2449     cr = ce == cx;
2450     if (cr) {
2451       cx = cd;
2452     }
2453   }
2454 #pragma omp atomic compare capture acq_rel
2455   {
2456     cr = cx == ce;
2457     if (cr) {
2458       cx = cd;
2459     } else {
2460       cv = cx;
2461     }
2462   }
2463 #pragma omp atomic compare capture acq_rel
2464   {
2465     cr = ce == cx;
2466     if (cr) {
2467       cx = cd;
2468     } else {
2469       cv = cx;
2470     }
2471   }
2472 
2473 #pragma omp atomic compare capture acquire
2474   {
2475     cv = cx;
2476     if (ce > cx) {
2477       cx = ce;
2478     }
2479   }
2480 #pragma omp atomic compare capture acquire
2481   {
2482     cv = cx;
2483     if (cx > ce) {
2484       cx = ce;
2485     }
2486   }
2487 #pragma omp atomic compare capture acquire
2488   {
2489     cv = cx;
2490     if (ce < cx) {
2491       cx = ce;
2492     }
2493   }
2494 #pragma omp atomic compare capture acquire
2495   {
2496     cv = cx;
2497     if (cx < ce) {
2498       cx = ce;
2499     }
2500   }
2501 #pragma omp atomic compare capture acquire
2502   {
2503     cv = cx;
2504     if (cx == ce) {
2505       cx = cd;
2506     }
2507   }
2508 #pragma omp atomic compare capture acquire
2509   {
2510     cv = cx;
2511     if (ce == cx) {
2512       cx = cd;
2513     }
2514   }
2515 #pragma omp atomic compare capture acquire
2516   {
2517     if (ce > cx) {
2518       cx = ce;
2519     }
2520     cv = cx;
2521   }
2522 #pragma omp atomic compare capture acquire
2523   {
2524     if (cx > ce) {
2525       cx = ce;
2526     }
2527     cv = cx;
2528   }
2529 #pragma omp atomic compare capture acquire
2530   {
2531     if (ce < cx) {
2532       cx = ce;
2533     }
2534     cv = cx;
2535   }
2536 #pragma omp atomic compare capture acquire
2537   {
2538     if (cx < ce) {
2539       cx = ce;
2540     }
2541     cv = cx;
2542   }
2543 #pragma omp atomic compare capture acquire
2544   {
2545     if (cx == ce) {
2546       cx = cd;
2547     }
2548     cv = cx;
2549   }
2550 #pragma omp atomic compare capture acquire
2551   {
2552     if (ce == cx) {
2553       cx = cd;
2554     }
2555     cv = cx;
2556   }
2557 #pragma omp atomic compare capture acquire
2558   if (cx == ce) {
2559     cx = cd;
2560   } else {
2561     cv = cx;
2562   }
2563 #pragma omp atomic compare capture acquire
2564   if (ce == cx) {
2565     cx = cd;
2566   } else {
2567     cv = cx;
2568   }
2569 #pragma omp atomic compare capture acquire
2570   {
2571     cr = cx == ce;
2572     if (cr) {
2573       cx = cd;
2574     }
2575   }
2576 #pragma omp atomic compare capture acquire
2577   {
2578     cr = ce == cx;
2579     if (cr) {
2580       cx = cd;
2581     }
2582   }
2583 #pragma omp atomic compare capture acquire
2584   {
2585     cr = cx == ce;
2586     if (cr) {
2587       cx = cd;
2588     } else {
2589       cv = cx;
2590     }
2591   }
2592 #pragma omp atomic compare capture acquire
2593   {
2594     cr = ce == cx;
2595     if (cr) {
2596       cx = cd;
2597     } else {
2598       cv = cx;
2599     }
2600   }
2601 
2602 #pragma omp atomic compare capture relaxed
2603   {
2604     cv = cx;
2605     if (ce > cx) {
2606       cx = ce;
2607     }
2608   }
2609 #pragma omp atomic compare capture relaxed
2610   {
2611     cv = cx;
2612     if (cx > ce) {
2613       cx = ce;
2614     }
2615   }
2616 #pragma omp atomic compare capture relaxed
2617   {
2618     cv = cx;
2619     if (ce < cx) {
2620       cx = ce;
2621     }
2622   }
2623 #pragma omp atomic compare capture relaxed
2624   {
2625     cv = cx;
2626     if (cx < ce) {
2627       cx = ce;
2628     }
2629   }
2630 #pragma omp atomic compare capture relaxed
2631   {
2632     cv = cx;
2633     if (cx == ce) {
2634       cx = cd;
2635     }
2636   }
2637 #pragma omp atomic compare capture relaxed
2638   {
2639     cv = cx;
2640     if (ce == cx) {
2641       cx = cd;
2642     }
2643   }
2644 #pragma omp atomic compare capture relaxed
2645   {
2646     if (ce > cx) {
2647       cx = ce;
2648     }
2649     cv = cx;
2650   }
2651 #pragma omp atomic compare capture relaxed
2652   {
2653     if (cx > ce) {
2654       cx = ce;
2655     }
2656     cv = cx;
2657   }
2658 #pragma omp atomic compare capture relaxed
2659   {
2660     if (ce < cx) {
2661       cx = ce;
2662     }
2663     cv = cx;
2664   }
2665 #pragma omp atomic compare capture relaxed
2666   {
2667     if (cx < ce) {
2668       cx = ce;
2669     }
2670     cv = cx;
2671   }
2672 #pragma omp atomic compare capture relaxed
2673   {
2674     if (cx == ce) {
2675       cx = cd;
2676     }
2677     cv = cx;
2678   }
2679 #pragma omp atomic compare capture relaxed
2680   {
2681     if (ce == cx) {
2682       cx = cd;
2683     }
2684     cv = cx;
2685   }
2686 #pragma omp atomic compare capture relaxed
2687   if (cx == ce) {
2688     cx = cd;
2689   } else {
2690     cv = cx;
2691   }
2692 #pragma omp atomic compare capture relaxed
2693   if (ce == cx) {
2694     cx = cd;
2695   } else {
2696     cv = cx;
2697   }
2698 #pragma omp atomic compare capture relaxed
2699   {
2700     cr = cx == ce;
2701     if (cr) {
2702       cx = cd;
2703     }
2704   }
2705 #pragma omp atomic compare capture relaxed
2706   {
2707     cr = ce == cx;
2708     if (cr) {
2709       cx = cd;
2710     }
2711   }
2712 #pragma omp atomic compare capture relaxed
2713   {
2714     cr = cx == ce;
2715     if (cr) {
2716       cx = cd;
2717     } else {
2718       cv = cx;
2719     }
2720   }
2721 #pragma omp atomic compare capture relaxed
2722   {
2723     cr = ce == cx;
2724     if (cr) {
2725       cx = cd;
2726     } else {
2727       cv = cx;
2728     }
2729   }
2730 
2731 #pragma omp atomic compare capture release
2732   {
2733     cv = cx;
2734     if (ce > cx) {
2735       cx = ce;
2736     }
2737   }
2738 #pragma omp atomic compare capture release
2739   {
2740     cv = cx;
2741     if (cx > ce) {
2742       cx = ce;
2743     }
2744   }
2745 #pragma omp atomic compare capture release
2746   {
2747     cv = cx;
2748     if (ce < cx) {
2749       cx = ce;
2750     }
2751   }
2752 #pragma omp atomic compare capture release
2753   {
2754     cv = cx;
2755     if (cx < ce) {
2756       cx = ce;
2757     }
2758   }
2759 #pragma omp atomic compare capture release
2760   {
2761     cv = cx;
2762     if (cx == ce) {
2763       cx = cd;
2764     }
2765   }
2766 #pragma omp atomic compare capture release
2767   {
2768     cv = cx;
2769     if (ce == cx) {
2770       cx = cd;
2771     }
2772   }
2773 #pragma omp atomic compare capture release
2774   {
2775     if (ce > cx) {
2776       cx = ce;
2777     }
2778     cv = cx;
2779   }
2780 #pragma omp atomic compare capture release
2781   {
2782     if (cx > ce) {
2783       cx = ce;
2784     }
2785     cv = cx;
2786   }
2787 #pragma omp atomic compare capture release
2788   {
2789     if (ce < cx) {
2790       cx = ce;
2791     }
2792     cv = cx;
2793   }
2794 #pragma omp atomic compare capture release
2795   {
2796     if (cx < ce) {
2797       cx = ce;
2798     }
2799     cv = cx;
2800   }
2801 #pragma omp atomic compare capture release
2802   {
2803     if (cx == ce) {
2804       cx = cd;
2805     }
2806     cv = cx;
2807   }
2808 #pragma omp atomic compare capture release
2809   {
2810     if (ce == cx) {
2811       cx = cd;
2812     }
2813     cv = cx;
2814   }
2815 #pragma omp atomic compare capture release
2816   if (cx == ce) {
2817     cx = cd;
2818   } else {
2819     cv = cx;
2820   }
2821 #pragma omp atomic compare capture release
2822   if (ce == cx) {
2823     cx = cd;
2824   } else {
2825     cv = cx;
2826   }
2827 #pragma omp atomic compare capture release
2828   {
2829     cr = cx == ce;
2830     if (cr) {
2831       cx = cd;
2832     }
2833   }
2834 #pragma omp atomic compare capture release
2835   {
2836     cr = ce == cx;
2837     if (cr) {
2838       cx = cd;
2839     }
2840   }
2841 #pragma omp atomic compare capture release
2842   {
2843     cr = cx == ce;
2844     if (cr) {
2845       cx = cd;
2846     } else {
2847       cv = cx;
2848     }
2849   }
2850 #pragma omp atomic compare capture release
2851   {
2852     cr = ce == cx;
2853     if (cr) {
2854       cx = cd;
2855     } else {
2856       cv = cx;
2857     }
2858   }
2859 
2860 #pragma omp atomic compare capture seq_cst
2861   {
2862     cv = cx;
2863     if (ce > cx) {
2864       cx = ce;
2865     }
2866   }
2867 #pragma omp atomic compare capture seq_cst
2868   {
2869     cv = cx;
2870     if (cx > ce) {
2871       cx = ce;
2872     }
2873   }
2874 #pragma omp atomic compare capture seq_cst
2875   {
2876     cv = cx;
2877     if (ce < cx) {
2878       cx = ce;
2879     }
2880   }
2881 #pragma omp atomic compare capture seq_cst
2882   {
2883     cv = cx;
2884     if (cx < ce) {
2885       cx = ce;
2886     }
2887   }
2888 #pragma omp atomic compare capture seq_cst
2889   {
2890     cv = cx;
2891     if (cx == ce) {
2892       cx = cd;
2893     }
2894   }
2895 #pragma omp atomic compare capture seq_cst
2896   {
2897     cv = cx;
2898     if (ce == cx) {
2899       cx = cd;
2900     }
2901   }
2902 #pragma omp atomic compare capture seq_cst
2903   {
2904     if (ce > cx) {
2905       cx = ce;
2906     }
2907     cv = cx;
2908   }
2909 #pragma omp atomic compare capture seq_cst
2910   {
2911     if (cx > ce) {
2912       cx = ce;
2913     }
2914     cv = cx;
2915   }
2916 #pragma omp atomic compare capture seq_cst
2917   {
2918     if (ce < cx) {
2919       cx = ce;
2920     }
2921     cv = cx;
2922   }
2923 #pragma omp atomic compare capture seq_cst
2924   {
2925     if (cx < ce) {
2926       cx = ce;
2927     }
2928     cv = cx;
2929   }
2930 #pragma omp atomic compare capture seq_cst
2931   {
2932     if (cx == ce) {
2933       cx = cd;
2934     }
2935     cv = cx;
2936   }
2937 #pragma omp atomic compare capture seq_cst
2938   {
2939     if (ce == cx) {
2940       cx = cd;
2941     }
2942     cv = cx;
2943   }
2944 #pragma omp atomic compare capture seq_cst
2945   if (cx == ce) {
2946     cx = cd;
2947   } else {
2948     cv = cx;
2949   }
2950 #pragma omp atomic compare capture seq_cst
2951   if (ce == cx) {
2952     cx = cd;
2953   } else {
2954     cv = cx;
2955   }
2956 #pragma omp atomic compare capture seq_cst
2957   {
2958     cr = cx == ce;
2959     if (cr) {
2960       cx = cd;
2961     }
2962   }
2963 #pragma omp atomic compare capture seq_cst
2964   {
2965     cr = ce == cx;
2966     if (cr) {
2967       cx = cd;
2968     }
2969   }
2970 #pragma omp atomic compare capture seq_cst
2971   {
2972     cr = cx == ce;
2973     if (cr) {
2974       cx = cd;
2975     } else {
2976       cv = cx;
2977     }
2978   }
2979 #pragma omp atomic compare capture seq_cst
2980   {
2981     cr = ce == cx;
2982     if (cr) {
2983       cx = cd;
2984     } else {
2985       cv = cx;
2986     }
2987   }
2988 
2989 #pragma omp atomic compare capture
2990   {
2991     ucv = ucx;
2992     if (uce > ucx) {
2993       ucx = uce;
2994     }
2995   }
2996 #pragma omp atomic compare capture
2997   {
2998     ucv = ucx;
2999     if (ucx > uce) {
3000       ucx = uce;
3001     }
3002   }
3003 #pragma omp atomic compare capture
3004   {
3005     ucv = ucx;
3006     if (uce < ucx) {
3007       ucx = uce;
3008     }
3009   }
3010 #pragma omp atomic compare capture
3011   {
3012     ucv = ucx;
3013     if (ucx < uce) {
3014       ucx = uce;
3015     }
3016   }
3017 #pragma omp atomic compare capture
3018   {
3019     ucv = ucx;
3020     if (ucx == uce) {
3021       ucx = ucd;
3022     }
3023   }
3024 #pragma omp atomic compare capture
3025   {
3026     ucv = ucx;
3027     if (uce == ucx) {
3028       ucx = ucd;
3029     }
3030   }
3031 #pragma omp atomic compare capture
3032   {
3033     if (uce > ucx) {
3034       ucx = uce;
3035     }
3036     ucv = ucx;
3037   }
3038 #pragma omp atomic compare capture
3039   {
3040     if (ucx > uce) {
3041       ucx = uce;
3042     }
3043     ucv = ucx;
3044   }
3045 #pragma omp atomic compare capture
3046   {
3047     if (uce < ucx) {
3048       ucx = uce;
3049     }
3050     ucv = ucx;
3051   }
3052 #pragma omp atomic compare capture
3053   {
3054     if (ucx < uce) {
3055       ucx = uce;
3056     }
3057     ucv = ucx;
3058   }
3059 #pragma omp atomic compare capture
3060   {
3061     if (ucx == uce) {
3062       ucx = ucd;
3063     }
3064     ucv = ucx;
3065   }
3066 #pragma omp atomic compare capture
3067   {
3068     if (uce == ucx) {
3069       ucx = ucd;
3070     }
3071     ucv = ucx;
3072   }
3073 #pragma omp atomic compare capture
3074   if (ucx == uce) {
3075     ucx = ucd;
3076   } else {
3077     ucv = ucx;
3078   }
3079 #pragma omp atomic compare capture
3080   if (uce == ucx) {
3081     ucx = ucd;
3082   } else {
3083     ucv = ucx;
3084   }
3085 #pragma omp atomic compare capture
3086   {
3087     ucr = ucx == uce;
3088     if (ucr) {
3089       ucx = ucd;
3090     }
3091   }
3092 #pragma omp atomic compare capture
3093   {
3094     ucr = uce == ucx;
3095     if (ucr) {
3096       ucx = ucd;
3097     }
3098   }
3099 #pragma omp atomic compare capture
3100   {
3101     ucr = ucx == uce;
3102     if (ucr) {
3103       ucx = ucd;
3104     } else {
3105       ucv = ucx;
3106     }
3107   }
3108 #pragma omp atomic compare capture
3109   {
3110     ucr = uce == ucx;
3111     if (ucr) {
3112       ucx = ucd;
3113     } else {
3114       ucv = ucx;
3115     }
3116   }
3117 
3118 #pragma omp atomic compare capture acq_rel
3119   {
3120     ucv = ucx;
3121     if (uce > ucx) {
3122       ucx = uce;
3123     }
3124   }
3125 #pragma omp atomic compare capture acq_rel
3126   {
3127     ucv = ucx;
3128     if (ucx > uce) {
3129       ucx = uce;
3130     }
3131   }
3132 #pragma omp atomic compare capture acq_rel
3133   {
3134     ucv = ucx;
3135     if (uce < ucx) {
3136       ucx = uce;
3137     }
3138   }
3139 #pragma omp atomic compare capture acq_rel
3140   {
3141     ucv = ucx;
3142     if (ucx < uce) {
3143       ucx = uce;
3144     }
3145   }
3146 #pragma omp atomic compare capture acq_rel
3147   {
3148     ucv = ucx;
3149     if (ucx == uce) {
3150       ucx = ucd;
3151     }
3152   }
3153 #pragma omp atomic compare capture acq_rel
3154   {
3155     ucv = ucx;
3156     if (uce == ucx) {
3157       ucx = ucd;
3158     }
3159   }
3160 #pragma omp atomic compare capture acq_rel
3161   {
3162     if (uce > ucx) {
3163       ucx = uce;
3164     }
3165     ucv = ucx;
3166   }
3167 #pragma omp atomic compare capture acq_rel
3168   {
3169     if (ucx > uce) {
3170       ucx = uce;
3171     }
3172     ucv = ucx;
3173   }
3174 #pragma omp atomic compare capture acq_rel
3175   {
3176     if (uce < ucx) {
3177       ucx = uce;
3178     }
3179     ucv = ucx;
3180   }
3181 #pragma omp atomic compare capture acq_rel
3182   {
3183     if (ucx < uce) {
3184       ucx = uce;
3185     }
3186     ucv = ucx;
3187   }
3188 #pragma omp atomic compare capture acq_rel
3189   {
3190     if (ucx == uce) {
3191       ucx = ucd;
3192     }
3193     ucv = ucx;
3194   }
3195 #pragma omp atomic compare capture acq_rel
3196   {
3197     if (uce == ucx) {
3198       ucx = ucd;
3199     }
3200     ucv = ucx;
3201   }
3202 #pragma omp atomic compare capture acq_rel
3203   if (ucx == uce) {
3204     ucx = ucd;
3205   } else {
3206     ucv = ucx;
3207   }
3208 #pragma omp atomic compare capture acq_rel
3209   if (uce == ucx) {
3210     ucx = ucd;
3211   } else {
3212     ucv = ucx;
3213   }
3214 #pragma omp atomic compare capture acq_rel
3215   {
3216     ucr = ucx == uce;
3217     if (ucr) {
3218       ucx = ucd;
3219     }
3220   }
3221 #pragma omp atomic compare capture acq_rel
3222   {
3223     ucr = uce == ucx;
3224     if (ucr) {
3225       ucx = ucd;
3226     }
3227   }
3228 #pragma omp atomic compare capture acq_rel
3229   {
3230     ucr = ucx == uce;
3231     if (ucr) {
3232       ucx = ucd;
3233     } else {
3234       ucv = ucx;
3235     }
3236   }
3237 #pragma omp atomic compare capture acq_rel
3238   {
3239     ucr = uce == ucx;
3240     if (ucr) {
3241       ucx = ucd;
3242     } else {
3243       ucv = ucx;
3244     }
3245   }
3246 
3247 #pragma omp atomic compare capture acquire
3248   {
3249     ucv = ucx;
3250     if (uce > ucx) {
3251       ucx = uce;
3252     }
3253   }
3254 #pragma omp atomic compare capture acquire
3255   {
3256     ucv = ucx;
3257     if (ucx > uce) {
3258       ucx = uce;
3259     }
3260   }
3261 #pragma omp atomic compare capture acquire
3262   {
3263     ucv = ucx;
3264     if (uce < ucx) {
3265       ucx = uce;
3266     }
3267   }
3268 #pragma omp atomic compare capture acquire
3269   {
3270     ucv = ucx;
3271     if (ucx < uce) {
3272       ucx = uce;
3273     }
3274   }
3275 #pragma omp atomic compare capture acquire
3276   {
3277     ucv = ucx;
3278     if (ucx == uce) {
3279       ucx = ucd;
3280     }
3281   }
3282 #pragma omp atomic compare capture acquire
3283   {
3284     ucv = ucx;
3285     if (uce == ucx) {
3286       ucx = ucd;
3287     }
3288   }
3289 #pragma omp atomic compare capture acquire
3290   {
3291     if (uce > ucx) {
3292       ucx = uce;
3293     }
3294     ucv = ucx;
3295   }
3296 #pragma omp atomic compare capture acquire
3297   {
3298     if (ucx > uce) {
3299       ucx = uce;
3300     }
3301     ucv = ucx;
3302   }
3303 #pragma omp atomic compare capture acquire
3304   {
3305     if (uce < ucx) {
3306       ucx = uce;
3307     }
3308     ucv = ucx;
3309   }
3310 #pragma omp atomic compare capture acquire
3311   {
3312     if (ucx < uce) {
3313       ucx = uce;
3314     }
3315     ucv = ucx;
3316   }
3317 #pragma omp atomic compare capture acquire
3318   {
3319     if (ucx == uce) {
3320       ucx = ucd;
3321     }
3322     ucv = ucx;
3323   }
3324 #pragma omp atomic compare capture acquire
3325   {
3326     if (uce == ucx) {
3327       ucx = ucd;
3328     }
3329     ucv = ucx;
3330   }
3331 #pragma omp atomic compare capture acquire
3332   if (ucx == uce) {
3333     ucx = ucd;
3334   } else {
3335     ucv = ucx;
3336   }
3337 #pragma omp atomic compare capture acquire
3338   if (uce == ucx) {
3339     ucx = ucd;
3340   } else {
3341     ucv = ucx;
3342   }
3343 #pragma omp atomic compare capture acquire
3344   {
3345     ucr = ucx == uce;
3346     if (ucr) {
3347       ucx = ucd;
3348     }
3349   }
3350 #pragma omp atomic compare capture acquire
3351   {
3352     ucr = uce == ucx;
3353     if (ucr) {
3354       ucx = ucd;
3355     }
3356   }
3357 #pragma omp atomic compare capture acquire
3358   {
3359     ucr = ucx == uce;
3360     if (ucr) {
3361       ucx = ucd;
3362     } else {
3363       ucv = ucx;
3364     }
3365   }
3366 #pragma omp atomic compare capture acquire
3367   {
3368     ucr = uce == ucx;
3369     if (ucr) {
3370       ucx = ucd;
3371     } else {
3372       ucv = ucx;
3373     }
3374   }
3375 
3376 #pragma omp atomic compare capture relaxed
3377   {
3378     ucv = ucx;
3379     if (uce > ucx) {
3380       ucx = uce;
3381     }
3382   }
3383 #pragma omp atomic compare capture relaxed
3384   {
3385     ucv = ucx;
3386     if (ucx > uce) {
3387       ucx = uce;
3388     }
3389   }
3390 #pragma omp atomic compare capture relaxed
3391   {
3392     ucv = ucx;
3393     if (uce < ucx) {
3394       ucx = uce;
3395     }
3396   }
3397 #pragma omp atomic compare capture relaxed
3398   {
3399     ucv = ucx;
3400     if (ucx < uce) {
3401       ucx = uce;
3402     }
3403   }
3404 #pragma omp atomic compare capture relaxed
3405   {
3406     ucv = ucx;
3407     if (ucx == uce) {
3408       ucx = ucd;
3409     }
3410   }
3411 #pragma omp atomic compare capture relaxed
3412   {
3413     ucv = ucx;
3414     if (uce == ucx) {
3415       ucx = ucd;
3416     }
3417   }
3418 #pragma omp atomic compare capture relaxed
3419   {
3420     if (uce > ucx) {
3421       ucx = uce;
3422     }
3423     ucv = ucx;
3424   }
3425 #pragma omp atomic compare capture relaxed
3426   {
3427     if (ucx > uce) {
3428       ucx = uce;
3429     }
3430     ucv = ucx;
3431   }
3432 #pragma omp atomic compare capture relaxed
3433   {
3434     if (uce < ucx) {
3435       ucx = uce;
3436     }
3437     ucv = ucx;
3438   }
3439 #pragma omp atomic compare capture relaxed
3440   {
3441     if (ucx < uce) {
3442       ucx = uce;
3443     }
3444     ucv = ucx;
3445   }
3446 #pragma omp atomic compare capture relaxed
3447   {
3448     if (ucx == uce) {
3449       ucx = ucd;
3450     }
3451     ucv = ucx;
3452   }
3453 #pragma omp atomic compare capture relaxed
3454   {
3455     if (uce == ucx) {
3456       ucx = ucd;
3457     }
3458     ucv = ucx;
3459   }
3460 #pragma omp atomic compare capture relaxed
3461   if (ucx == uce) {
3462     ucx = ucd;
3463   } else {
3464     ucv = ucx;
3465   }
3466 #pragma omp atomic compare capture relaxed
3467   if (uce == ucx) {
3468     ucx = ucd;
3469   } else {
3470     ucv = ucx;
3471   }
3472 #pragma omp atomic compare capture relaxed
3473   {
3474     ucr = ucx == uce;
3475     if (ucr) {
3476       ucx = ucd;
3477     }
3478   }
3479 #pragma omp atomic compare capture relaxed
3480   {
3481     ucr = uce == ucx;
3482     if (ucr) {
3483       ucx = ucd;
3484     }
3485   }
3486 #pragma omp atomic compare capture relaxed
3487   {
3488     ucr = ucx == uce;
3489     if (ucr) {
3490       ucx = ucd;
3491     } else {
3492       ucv = ucx;
3493     }
3494   }
3495 #pragma omp atomic compare capture relaxed
3496   {
3497     ucr = uce == ucx;
3498     if (ucr) {
3499       ucx = ucd;
3500     } else {
3501       ucv = ucx;
3502     }
3503   }
3504 
3505 #pragma omp atomic compare capture release
3506   {
3507     ucv = ucx;
3508     if (uce > ucx) {
3509       ucx = uce;
3510     }
3511   }
3512 #pragma omp atomic compare capture release
3513   {
3514     ucv = ucx;
3515     if (ucx > uce) {
3516       ucx = uce;
3517     }
3518   }
3519 #pragma omp atomic compare capture release
3520   {
3521     ucv = ucx;
3522     if (uce < ucx) {
3523       ucx = uce;
3524     }
3525   }
3526 #pragma omp atomic compare capture release
3527   {
3528     ucv = ucx;
3529     if (ucx < uce) {
3530       ucx = uce;
3531     }
3532   }
3533 #pragma omp atomic compare capture release
3534   {
3535     ucv = ucx;
3536     if (ucx == uce) {
3537       ucx = ucd;
3538     }
3539   }
3540 #pragma omp atomic compare capture release
3541   {
3542     ucv = ucx;
3543     if (uce == ucx) {
3544       ucx = ucd;
3545     }
3546   }
3547 #pragma omp atomic compare capture release
3548   {
3549     if (uce > ucx) {
3550       ucx = uce;
3551     }
3552     ucv = ucx;
3553   }
3554 #pragma omp atomic compare capture release
3555   {
3556     if (ucx > uce) {
3557       ucx = uce;
3558     }
3559     ucv = ucx;
3560   }
3561 #pragma omp atomic compare capture release
3562   {
3563     if (uce < ucx) {
3564       ucx = uce;
3565     }
3566     ucv = ucx;
3567   }
3568 #pragma omp atomic compare capture release
3569   {
3570     if (ucx < uce) {
3571       ucx = uce;
3572     }
3573     ucv = ucx;
3574   }
3575 #pragma omp atomic compare capture release
3576   {
3577     if (ucx == uce) {
3578       ucx = ucd;
3579     }
3580     ucv = ucx;
3581   }
3582 #pragma omp atomic compare capture release
3583   {
3584     if (uce == ucx) {
3585       ucx = ucd;
3586     }
3587     ucv = ucx;
3588   }
3589 #pragma omp atomic compare capture release
3590   if (ucx == uce) {
3591     ucx = ucd;
3592   } else {
3593     ucv = ucx;
3594   }
3595 #pragma omp atomic compare capture release
3596   if (uce == ucx) {
3597     ucx = ucd;
3598   } else {
3599     ucv = ucx;
3600   }
3601 #pragma omp atomic compare capture release
3602   {
3603     ucr = ucx == uce;
3604     if (ucr) {
3605       ucx = ucd;
3606     }
3607   }
3608 #pragma omp atomic compare capture release
3609   {
3610     ucr = uce == ucx;
3611     if (ucr) {
3612       ucx = ucd;
3613     }
3614   }
3615 #pragma omp atomic compare capture release
3616   {
3617     ucr = ucx == uce;
3618     if (ucr) {
3619       ucx = ucd;
3620     } else {
3621       ucv = ucx;
3622     }
3623   }
3624 #pragma omp atomic compare capture release
3625   {
3626     ucr = uce == ucx;
3627     if (ucr) {
3628       ucx = ucd;
3629     } else {
3630       ucv = ucx;
3631     }
3632   }
3633 
3634 #pragma omp atomic compare capture seq_cst
3635   {
3636     ucv = ucx;
3637     if (uce > ucx) {
3638       ucx = uce;
3639     }
3640   }
3641 #pragma omp atomic compare capture seq_cst
3642   {
3643     ucv = ucx;
3644     if (ucx > uce) {
3645       ucx = uce;
3646     }
3647   }
3648 #pragma omp atomic compare capture seq_cst
3649   {
3650     ucv = ucx;
3651     if (uce < ucx) {
3652       ucx = uce;
3653     }
3654   }
3655 #pragma omp atomic compare capture seq_cst
3656   {
3657     ucv = ucx;
3658     if (ucx < uce) {
3659       ucx = uce;
3660     }
3661   }
3662 #pragma omp atomic compare capture seq_cst
3663   {
3664     ucv = ucx;
3665     if (ucx == uce) {
3666       ucx = ucd;
3667     }
3668   }
3669 #pragma omp atomic compare capture seq_cst
3670   {
3671     ucv = ucx;
3672     if (uce == ucx) {
3673       ucx = ucd;
3674     }
3675   }
3676 #pragma omp atomic compare capture seq_cst
3677   {
3678     if (uce > ucx) {
3679       ucx = uce;
3680     }
3681     ucv = ucx;
3682   }
3683 #pragma omp atomic compare capture seq_cst
3684   {
3685     if (ucx > uce) {
3686       ucx = uce;
3687     }
3688     ucv = ucx;
3689   }
3690 #pragma omp atomic compare capture seq_cst
3691   {
3692     if (uce < ucx) {
3693       ucx = uce;
3694     }
3695     ucv = ucx;
3696   }
3697 #pragma omp atomic compare capture seq_cst
3698   {
3699     if (ucx < uce) {
3700       ucx = uce;
3701     }
3702     ucv = ucx;
3703   }
3704 #pragma omp atomic compare capture seq_cst
3705   {
3706     if (ucx == uce) {
3707       ucx = ucd;
3708     }
3709     ucv = ucx;
3710   }
3711 #pragma omp atomic compare capture seq_cst
3712   {
3713     if (uce == ucx) {
3714       ucx = ucd;
3715     }
3716     ucv = ucx;
3717   }
3718 #pragma omp atomic compare capture seq_cst
3719   if (ucx == uce) {
3720     ucx = ucd;
3721   } else {
3722     ucv = ucx;
3723   }
3724 #pragma omp atomic compare capture seq_cst
3725   if (uce == ucx) {
3726     ucx = ucd;
3727   } else {
3728     ucv = ucx;
3729   }
3730 #pragma omp atomic compare capture seq_cst
3731   {
3732     ucr = ucx == uce;
3733     if (ucr) {
3734       ucx = ucd;
3735     }
3736   }
3737 #pragma omp atomic compare capture seq_cst
3738   {
3739     ucr = uce == ucx;
3740     if (ucr) {
3741       ucx = ucd;
3742     }
3743   }
3744 #pragma omp atomic compare capture seq_cst
3745   {
3746     ucr = ucx == uce;
3747     if (ucr) {
3748       ucx = ucd;
3749     } else {
3750       ucv = ucx;
3751     }
3752   }
3753 #pragma omp atomic compare capture seq_cst
3754   {
3755     ucr = uce == ucx;
3756     if (ucr) {
3757       ucx = ucd;
3758     } else {
3759       ucv = ucx;
3760     }
3761   }
3762 
3763 #pragma omp atomic compare capture
3764   {
3765     sv = sx;
3766     if (se > sx) {
3767       sx = se;
3768     }
3769   }
3770 #pragma omp atomic compare capture
3771   {
3772     sv = sx;
3773     if (sx > se) {
3774       sx = se;
3775     }
3776   }
3777 #pragma omp atomic compare capture
3778   {
3779     sv = sx;
3780     if (se < sx) {
3781       sx = se;
3782     }
3783   }
3784 #pragma omp atomic compare capture
3785   {
3786     sv = sx;
3787     if (sx < se) {
3788       sx = se;
3789     }
3790   }
3791 #pragma omp atomic compare capture
3792   {
3793     sv = sx;
3794     if (sx == se) {
3795       sx = sd;
3796     }
3797   }
3798 #pragma omp atomic compare capture
3799   {
3800     sv = sx;
3801     if (se == sx) {
3802       sx = sd;
3803     }
3804   }
3805 #pragma omp atomic compare capture
3806   {
3807     if (se > sx) {
3808       sx = se;
3809     }
3810     sv = sx;
3811   }
3812 #pragma omp atomic compare capture
3813   {
3814     if (sx > se) {
3815       sx = se;
3816     }
3817     sv = sx;
3818   }
3819 #pragma omp atomic compare capture
3820   {
3821     if (se < sx) {
3822       sx = se;
3823     }
3824     sv = sx;
3825   }
3826 #pragma omp atomic compare capture
3827   {
3828     if (sx < se) {
3829       sx = se;
3830     }
3831     sv = sx;
3832   }
3833 #pragma omp atomic compare capture
3834   {
3835     if (sx == se) {
3836       sx = sd;
3837     }
3838     sv = sx;
3839   }
3840 #pragma omp atomic compare capture
3841   {
3842     if (se == sx) {
3843       sx = sd;
3844     }
3845     sv = sx;
3846   }
3847 #pragma omp atomic compare capture
3848   if (sx == se) {
3849     sx = sd;
3850   } else {
3851     sv = sx;
3852   }
3853 #pragma omp atomic compare capture
3854   if (se == sx) {
3855     sx = sd;
3856   } else {
3857     sv = sx;
3858   }
3859 #pragma omp atomic compare capture
3860   {
3861     sr = sx == se;
3862     if (sr) {
3863       sx = sd;
3864     }
3865   }
3866 #pragma omp atomic compare capture
3867   {
3868     sr = se == sx;
3869     if (sr) {
3870       sx = sd;
3871     }
3872   }
3873 #pragma omp atomic compare capture
3874   {
3875     sr = sx == se;
3876     if (sr) {
3877       sx = sd;
3878     } else {
3879       sv = sx;
3880     }
3881   }
3882 #pragma omp atomic compare capture
3883   {
3884     sr = se == sx;
3885     if (sr) {
3886       sx = sd;
3887     } else {
3888       sv = sx;
3889     }
3890   }
3891 
3892 #pragma omp atomic compare capture acq_rel
3893   {
3894     sv = sx;
3895     if (se > sx) {
3896       sx = se;
3897     }
3898   }
3899 #pragma omp atomic compare capture acq_rel
3900   {
3901     sv = sx;
3902     if (sx > se) {
3903       sx = se;
3904     }
3905   }
3906 #pragma omp atomic compare capture acq_rel
3907   {
3908     sv = sx;
3909     if (se < sx) {
3910       sx = se;
3911     }
3912   }
3913 #pragma omp atomic compare capture acq_rel
3914   {
3915     sv = sx;
3916     if (sx < se) {
3917       sx = se;
3918     }
3919   }
3920 #pragma omp atomic compare capture acq_rel
3921   {
3922     sv = sx;
3923     if (sx == se) {
3924       sx = sd;
3925     }
3926   }
3927 #pragma omp atomic compare capture acq_rel
3928   {
3929     sv = sx;
3930     if (se == sx) {
3931       sx = sd;
3932     }
3933   }
3934 #pragma omp atomic compare capture acq_rel
3935   {
3936     if (se > sx) {
3937       sx = se;
3938     }
3939     sv = sx;
3940   }
3941 #pragma omp atomic compare capture acq_rel
3942   {
3943     if (sx > se) {
3944       sx = se;
3945     }
3946     sv = sx;
3947   }
3948 #pragma omp atomic compare capture acq_rel
3949   {
3950     if (se < sx) {
3951       sx = se;
3952     }
3953     sv = sx;
3954   }
3955 #pragma omp atomic compare capture acq_rel
3956   {
3957     if (sx < se) {
3958       sx = se;
3959     }
3960     sv = sx;
3961   }
3962 #pragma omp atomic compare capture acq_rel
3963   {
3964     if (sx == se) {
3965       sx = sd;
3966     }
3967     sv = sx;
3968   }
3969 #pragma omp atomic compare capture acq_rel
3970   {
3971     if (se == sx) {
3972       sx = sd;
3973     }
3974     sv = sx;
3975   }
3976 #pragma omp atomic compare capture acq_rel
3977   if (sx == se) {
3978     sx = sd;
3979   } else {
3980     sv = sx;
3981   }
3982 #pragma omp atomic compare capture acq_rel
3983   if (se == sx) {
3984     sx = sd;
3985   } else {
3986     sv = sx;
3987   }
3988 #pragma omp atomic compare capture acq_rel
3989   {
3990     sr = sx == se;
3991     if (sr) {
3992       sx = sd;
3993     }
3994   }
3995 #pragma omp atomic compare capture acq_rel
3996   {
3997     sr = se == sx;
3998     if (sr) {
3999       sx = sd;
4000     }
4001   }
4002 #pragma omp atomic compare capture acq_rel
4003   {
4004     sr = sx == se;
4005     if (sr) {
4006       sx = sd;
4007     } else {
4008       sv = sx;
4009     }
4010   }
4011 #pragma omp atomic compare capture acq_rel
4012   {
4013     sr = se == sx;
4014     if (sr) {
4015       sx = sd;
4016     } else {
4017       sv = sx;
4018     }
4019   }
4020 
4021 #pragma omp atomic compare capture acquire
4022   {
4023     sv = sx;
4024     if (se > sx) {
4025       sx = se;
4026     }
4027   }
4028 #pragma omp atomic compare capture acquire
4029   {
4030     sv = sx;
4031     if (sx > se) {
4032       sx = se;
4033     }
4034   }
4035 #pragma omp atomic compare capture acquire
4036   {
4037     sv = sx;
4038     if (se < sx) {
4039       sx = se;
4040     }
4041   }
4042 #pragma omp atomic compare capture acquire
4043   {
4044     sv = sx;
4045     if (sx < se) {
4046       sx = se;
4047     }
4048   }
4049 #pragma omp atomic compare capture acquire
4050   {
4051     sv = sx;
4052     if (sx == se) {
4053       sx = sd;
4054     }
4055   }
4056 #pragma omp atomic compare capture acquire
4057   {
4058     sv = sx;
4059     if (se == sx) {
4060       sx = sd;
4061     }
4062   }
4063 #pragma omp atomic compare capture acquire
4064   {
4065     if (se > sx) {
4066       sx = se;
4067     }
4068     sv = sx;
4069   }
4070 #pragma omp atomic compare capture acquire
4071   {
4072     if (sx > se) {
4073       sx = se;
4074     }
4075     sv = sx;
4076   }
4077 #pragma omp atomic compare capture acquire
4078   {
4079     if (se < sx) {
4080       sx = se;
4081     }
4082     sv = sx;
4083   }
4084 #pragma omp atomic compare capture acquire
4085   {
4086     if (sx < se) {
4087       sx = se;
4088     }
4089     sv = sx;
4090   }
4091 #pragma omp atomic compare capture acquire
4092   {
4093     if (sx == se) {
4094       sx = sd;
4095     }
4096     sv = sx;
4097   }
4098 #pragma omp atomic compare capture acquire
4099   {
4100     if (se == sx) {
4101       sx = sd;
4102     }
4103     sv = sx;
4104   }
4105 #pragma omp atomic compare capture acquire
4106   if (sx == se) {
4107     sx = sd;
4108   } else {
4109     sv = sx;
4110   }
4111 #pragma omp atomic compare capture acquire
4112   if (se == sx) {
4113     sx = sd;
4114   } else {
4115     sv = sx;
4116   }
4117 #pragma omp atomic compare capture acquire
4118   {
4119     sr = sx == se;
4120     if (sr) {
4121       sx = sd;
4122     }
4123   }
4124 #pragma omp atomic compare capture acquire
4125   {
4126     sr = se == sx;
4127     if (sr) {
4128       sx = sd;
4129     }
4130   }
4131 #pragma omp atomic compare capture acquire
4132   {
4133     sr = sx == se;
4134     if (sr) {
4135       sx = sd;
4136     } else {
4137       sv = sx;
4138     }
4139   }
4140 #pragma omp atomic compare capture acquire
4141   {
4142     sr = se == sx;
4143     if (sr) {
4144       sx = sd;
4145     } else {
4146       sv = sx;
4147     }
4148   }
4149 
4150 #pragma omp atomic compare capture relaxed
4151   {
4152     sv = sx;
4153     if (se > sx) {
4154       sx = se;
4155     }
4156   }
4157 #pragma omp atomic compare capture relaxed
4158   {
4159     sv = sx;
4160     if (sx > se) {
4161       sx = se;
4162     }
4163   }
4164 #pragma omp atomic compare capture relaxed
4165   {
4166     sv = sx;
4167     if (se < sx) {
4168       sx = se;
4169     }
4170   }
4171 #pragma omp atomic compare capture relaxed
4172   {
4173     sv = sx;
4174     if (sx < se) {
4175       sx = se;
4176     }
4177   }
4178 #pragma omp atomic compare capture relaxed
4179   {
4180     sv = sx;
4181     if (sx == se) {
4182       sx = sd;
4183     }
4184   }
4185 #pragma omp atomic compare capture relaxed
4186   {
4187     sv = sx;
4188     if (se == sx) {
4189       sx = sd;
4190     }
4191   }
4192 #pragma omp atomic compare capture relaxed
4193   {
4194     if (se > sx) {
4195       sx = se;
4196     }
4197     sv = sx;
4198   }
4199 #pragma omp atomic compare capture relaxed
4200   {
4201     if (sx > se) {
4202       sx = se;
4203     }
4204     sv = sx;
4205   }
4206 #pragma omp atomic compare capture relaxed
4207   {
4208     if (se < sx) {
4209       sx = se;
4210     }
4211     sv = sx;
4212   }
4213 #pragma omp atomic compare capture relaxed
4214   {
4215     if (sx < se) {
4216       sx = se;
4217     }
4218     sv = sx;
4219   }
4220 #pragma omp atomic compare capture relaxed
4221   {
4222     if (sx == se) {
4223       sx = sd;
4224     }
4225     sv = sx;
4226   }
4227 #pragma omp atomic compare capture relaxed
4228   {
4229     if (se == sx) {
4230       sx = sd;
4231     }
4232     sv = sx;
4233   }
4234 #pragma omp atomic compare capture relaxed
4235   if (sx == se) {
4236     sx = sd;
4237   } else {
4238     sv = sx;
4239   }
4240 #pragma omp atomic compare capture relaxed
4241   if (se == sx) {
4242     sx = sd;
4243   } else {
4244     sv = sx;
4245   }
4246 #pragma omp atomic compare capture relaxed
4247   {
4248     sr = sx == se;
4249     if (sr) {
4250       sx = sd;
4251     }
4252   }
4253 #pragma omp atomic compare capture relaxed
4254   {
4255     sr = se == sx;
4256     if (sr) {
4257       sx = sd;
4258     }
4259   }
4260 #pragma omp atomic compare capture relaxed
4261   {
4262     sr = sx == se;
4263     if (sr) {
4264       sx = sd;
4265     } else {
4266       sv = sx;
4267     }
4268   }
4269 #pragma omp atomic compare capture relaxed
4270   {
4271     sr = se == sx;
4272     if (sr) {
4273       sx = sd;
4274     } else {
4275       sv = sx;
4276     }
4277   }
4278 
4279 #pragma omp atomic compare capture release
4280   {
4281     sv = sx;
4282     if (se > sx) {
4283       sx = se;
4284     }
4285   }
4286 #pragma omp atomic compare capture release
4287   {
4288     sv = sx;
4289     if (sx > se) {
4290       sx = se;
4291     }
4292   }
4293 #pragma omp atomic compare capture release
4294   {
4295     sv = sx;
4296     if (se < sx) {
4297       sx = se;
4298     }
4299   }
4300 #pragma omp atomic compare capture release
4301   {
4302     sv = sx;
4303     if (sx < se) {
4304       sx = se;
4305     }
4306   }
4307 #pragma omp atomic compare capture release
4308   {
4309     sv = sx;
4310     if (sx == se) {
4311       sx = sd;
4312     }
4313   }
4314 #pragma omp atomic compare capture release
4315   {
4316     sv = sx;
4317     if (se == sx) {
4318       sx = sd;
4319     }
4320   }
4321 #pragma omp atomic compare capture release
4322   {
4323     if (se > sx) {
4324       sx = se;
4325     }
4326     sv = sx;
4327   }
4328 #pragma omp atomic compare capture release
4329   {
4330     if (sx > se) {
4331       sx = se;
4332     }
4333     sv = sx;
4334   }
4335 #pragma omp atomic compare capture release
4336   {
4337     if (se < sx) {
4338       sx = se;
4339     }
4340     sv = sx;
4341   }
4342 #pragma omp atomic compare capture release
4343   {
4344     if (sx < se) {
4345       sx = se;
4346     }
4347     sv = sx;
4348   }
4349 #pragma omp atomic compare capture release
4350   {
4351     if (sx == se) {
4352       sx = sd;
4353     }
4354     sv = sx;
4355   }
4356 #pragma omp atomic compare capture release
4357   {
4358     if (se == sx) {
4359       sx = sd;
4360     }
4361     sv = sx;
4362   }
4363 #pragma omp atomic compare capture release
4364   if (sx == se) {
4365     sx = sd;
4366   } else {
4367     sv = sx;
4368   }
4369 #pragma omp atomic compare capture release
4370   if (se == sx) {
4371     sx = sd;
4372   } else {
4373     sv = sx;
4374   }
4375 #pragma omp atomic compare capture release
4376   {
4377     sr = sx == se;
4378     if (sr) {
4379       sx = sd;
4380     }
4381   }
4382 #pragma omp atomic compare capture release
4383   {
4384     sr = se == sx;
4385     if (sr) {
4386       sx = sd;
4387     }
4388   }
4389 #pragma omp atomic compare capture release
4390   {
4391     sr = sx == se;
4392     if (sr) {
4393       sx = sd;
4394     } else {
4395       sv = sx;
4396     }
4397   }
4398 #pragma omp atomic compare capture release
4399   {
4400     sr = se == sx;
4401     if (sr) {
4402       sx = sd;
4403     } else {
4404       sv = sx;
4405     }
4406   }
4407 
4408 #pragma omp atomic compare capture seq_cst
4409   {
4410     sv = sx;
4411     if (se > sx) {
4412       sx = se;
4413     }
4414   }
4415 #pragma omp atomic compare capture seq_cst
4416   {
4417     sv = sx;
4418     if (sx > se) {
4419       sx = se;
4420     }
4421   }
4422 #pragma omp atomic compare capture seq_cst
4423   {
4424     sv = sx;
4425     if (se < sx) {
4426       sx = se;
4427     }
4428   }
4429 #pragma omp atomic compare capture seq_cst
4430   {
4431     sv = sx;
4432     if (sx < se) {
4433       sx = se;
4434     }
4435   }
4436 #pragma omp atomic compare capture seq_cst
4437   {
4438     sv = sx;
4439     if (sx == se) {
4440       sx = sd;
4441     }
4442   }
4443 #pragma omp atomic compare capture seq_cst
4444   {
4445     sv = sx;
4446     if (se == sx) {
4447       sx = sd;
4448     }
4449   }
4450 #pragma omp atomic compare capture seq_cst
4451   {
4452     if (se > sx) {
4453       sx = se;
4454     }
4455     sv = sx;
4456   }
4457 #pragma omp atomic compare capture seq_cst
4458   {
4459     if (sx > se) {
4460       sx = se;
4461     }
4462     sv = sx;
4463   }
4464 #pragma omp atomic compare capture seq_cst
4465   {
4466     if (se < sx) {
4467       sx = se;
4468     }
4469     sv = sx;
4470   }
4471 #pragma omp atomic compare capture seq_cst
4472   {
4473     if (sx < se) {
4474       sx = se;
4475     }
4476     sv = sx;
4477   }
4478 #pragma omp atomic compare capture seq_cst
4479   {
4480     if (sx == se) {
4481       sx = sd;
4482     }
4483     sv = sx;
4484   }
4485 #pragma omp atomic compare capture seq_cst
4486   {
4487     if (se == sx) {
4488       sx = sd;
4489     }
4490     sv = sx;
4491   }
4492 #pragma omp atomic compare capture seq_cst
4493   if (sx == se) {
4494     sx = sd;
4495   } else {
4496     sv = sx;
4497   }
4498 #pragma omp atomic compare capture seq_cst
4499   if (se == sx) {
4500     sx = sd;
4501   } else {
4502     sv = sx;
4503   }
4504 #pragma omp atomic compare capture seq_cst
4505   {
4506     sr = sx == se;
4507     if (sr) {
4508       sx = sd;
4509     }
4510   }
4511 #pragma omp atomic compare capture seq_cst
4512   {
4513     sr = se == sx;
4514     if (sr) {
4515       sx = sd;
4516     }
4517   }
4518 #pragma omp atomic compare capture seq_cst
4519   {
4520     sr = sx == se;
4521     if (sr) {
4522       sx = sd;
4523     } else {
4524       sv = sx;
4525     }
4526   }
4527 #pragma omp atomic compare capture seq_cst
4528   {
4529     sr = se == sx;
4530     if (sr) {
4531       sx = sd;
4532     } else {
4533       sv = sx;
4534     }
4535   }
4536 
4537 #pragma omp atomic compare capture
4538   {
4539     usv = usx;
4540     if (use > usx) {
4541       usx = use;
4542     }
4543   }
4544 #pragma omp atomic compare capture
4545   {
4546     usv = usx;
4547     if (usx > use) {
4548       usx = use;
4549     }
4550   }
4551 #pragma omp atomic compare capture
4552   {
4553     usv = usx;
4554     if (use < usx) {
4555       usx = use;
4556     }
4557   }
4558 #pragma omp atomic compare capture
4559   {
4560     usv = usx;
4561     if (usx < use) {
4562       usx = use;
4563     }
4564   }
4565 #pragma omp atomic compare capture
4566   {
4567     usv = usx;
4568     if (usx == use) {
4569       usx = usd;
4570     }
4571   }
4572 #pragma omp atomic compare capture
4573   {
4574     usv = usx;
4575     if (use == usx) {
4576       usx = usd;
4577     }
4578   }
4579 #pragma omp atomic compare capture
4580   {
4581     if (use > usx) {
4582       usx = use;
4583     }
4584     usv = usx;
4585   }
4586 #pragma omp atomic compare capture
4587   {
4588     if (usx > use) {
4589       usx = use;
4590     }
4591     usv = usx;
4592   }
4593 #pragma omp atomic compare capture
4594   {
4595     if (use < usx) {
4596       usx = use;
4597     }
4598     usv = usx;
4599   }
4600 #pragma omp atomic compare capture
4601   {
4602     if (usx < use) {
4603       usx = use;
4604     }
4605     usv = usx;
4606   }
4607 #pragma omp atomic compare capture
4608   {
4609     if (usx == use) {
4610       usx = usd;
4611     }
4612     usv = usx;
4613   }
4614 #pragma omp atomic compare capture
4615   {
4616     if (use == usx) {
4617       usx = usd;
4618     }
4619     usv = usx;
4620   }
4621 #pragma omp atomic compare capture
4622   if (usx == use) {
4623     usx = usd;
4624   } else {
4625     usv = usx;
4626   }
4627 #pragma omp atomic compare capture
4628   if (use == usx) {
4629     usx = usd;
4630   } else {
4631     usv = usx;
4632   }
4633 #pragma omp atomic compare capture
4634   {
4635     usr = usx == use;
4636     if (usr) {
4637       usx = usd;
4638     }
4639   }
4640 #pragma omp atomic compare capture
4641   {
4642     usr = use == usx;
4643     if (usr) {
4644       usx = usd;
4645     }
4646   }
4647 #pragma omp atomic compare capture
4648   {
4649     usr = usx == use;
4650     if (usr) {
4651       usx = usd;
4652     } else {
4653       usv = usx;
4654     }
4655   }
4656 #pragma omp atomic compare capture
4657   {
4658     usr = use == usx;
4659     if (usr) {
4660       usx = usd;
4661     } else {
4662       usv = usx;
4663     }
4664   }
4665 
4666 #pragma omp atomic compare capture acq_rel
4667   {
4668     usv = usx;
4669     if (use > usx) {
4670       usx = use;
4671     }
4672   }
4673 #pragma omp atomic compare capture acq_rel
4674   {
4675     usv = usx;
4676     if (usx > use) {
4677       usx = use;
4678     }
4679   }
4680 #pragma omp atomic compare capture acq_rel
4681   {
4682     usv = usx;
4683     if (use < usx) {
4684       usx = use;
4685     }
4686   }
4687 #pragma omp atomic compare capture acq_rel
4688   {
4689     usv = usx;
4690     if (usx < use) {
4691       usx = use;
4692     }
4693   }
4694 #pragma omp atomic compare capture acq_rel
4695   {
4696     usv = usx;
4697     if (usx == use) {
4698       usx = usd;
4699     }
4700   }
4701 #pragma omp atomic compare capture acq_rel
4702   {
4703     usv = usx;
4704     if (use == usx) {
4705       usx = usd;
4706     }
4707   }
4708 #pragma omp atomic compare capture acq_rel
4709   {
4710     if (use > usx) {
4711       usx = use;
4712     }
4713     usv = usx;
4714   }
4715 #pragma omp atomic compare capture acq_rel
4716   {
4717     if (usx > use) {
4718       usx = use;
4719     }
4720     usv = usx;
4721   }
4722 #pragma omp atomic compare capture acq_rel
4723   {
4724     if (use < usx) {
4725       usx = use;
4726     }
4727     usv = usx;
4728   }
4729 #pragma omp atomic compare capture acq_rel
4730   {
4731     if (usx < use) {
4732       usx = use;
4733     }
4734     usv = usx;
4735   }
4736 #pragma omp atomic compare capture acq_rel
4737   {
4738     if (usx == use) {
4739       usx = usd;
4740     }
4741     usv = usx;
4742   }
4743 #pragma omp atomic compare capture acq_rel
4744   {
4745     if (use == usx) {
4746       usx = usd;
4747     }
4748     usv = usx;
4749   }
4750 #pragma omp atomic compare capture acq_rel
4751   if (usx == use) {
4752     usx = usd;
4753   } else {
4754     usv = usx;
4755   }
4756 #pragma omp atomic compare capture acq_rel
4757   if (use == usx) {
4758     usx = usd;
4759   } else {
4760     usv = usx;
4761   }
4762 #pragma omp atomic compare capture acq_rel
4763   {
4764     usr = usx == use;
4765     if (usr) {
4766       usx = usd;
4767     }
4768   }
4769 #pragma omp atomic compare capture acq_rel
4770   {
4771     usr = use == usx;
4772     if (usr) {
4773       usx = usd;
4774     }
4775   }
4776 #pragma omp atomic compare capture acq_rel
4777   {
4778     usr = usx == use;
4779     if (usr) {
4780       usx = usd;
4781     } else {
4782       usv = usx;
4783     }
4784   }
4785 #pragma omp atomic compare capture acq_rel
4786   {
4787     usr = use == usx;
4788     if (usr) {
4789       usx = usd;
4790     } else {
4791       usv = usx;
4792     }
4793   }
4794 
4795 #pragma omp atomic compare capture acquire
4796   {
4797     usv = usx;
4798     if (use > usx) {
4799       usx = use;
4800     }
4801   }
4802 #pragma omp atomic compare capture acquire
4803   {
4804     usv = usx;
4805     if (usx > use) {
4806       usx = use;
4807     }
4808   }
4809 #pragma omp atomic compare capture acquire
4810   {
4811     usv = usx;
4812     if (use < usx) {
4813       usx = use;
4814     }
4815   }
4816 #pragma omp atomic compare capture acquire
4817   {
4818     usv = usx;
4819     if (usx < use) {
4820       usx = use;
4821     }
4822   }
4823 #pragma omp atomic compare capture acquire
4824   {
4825     usv = usx;
4826     if (usx == use) {
4827       usx = usd;
4828     }
4829   }
4830 #pragma omp atomic compare capture acquire
4831   {
4832     usv = usx;
4833     if (use == usx) {
4834       usx = usd;
4835     }
4836   }
4837 #pragma omp atomic compare capture acquire
4838   {
4839     if (use > usx) {
4840       usx = use;
4841     }
4842     usv = usx;
4843   }
4844 #pragma omp atomic compare capture acquire
4845   {
4846     if (usx > use) {
4847       usx = use;
4848     }
4849     usv = usx;
4850   }
4851 #pragma omp atomic compare capture acquire
4852   {
4853     if (use < usx) {
4854       usx = use;
4855     }
4856     usv = usx;
4857   }
4858 #pragma omp atomic compare capture acquire
4859   {
4860     if (usx < use) {
4861       usx = use;
4862     }
4863     usv = usx;
4864   }
4865 #pragma omp atomic compare capture acquire
4866   {
4867     if (usx == use) {
4868       usx = usd;
4869     }
4870     usv = usx;
4871   }
4872 #pragma omp atomic compare capture acquire
4873   {
4874     if (use == usx) {
4875       usx = usd;
4876     }
4877     usv = usx;
4878   }
4879 #pragma omp atomic compare capture acquire
4880   if (usx == use) {
4881     usx = usd;
4882   } else {
4883     usv = usx;
4884   }
4885 #pragma omp atomic compare capture acquire
4886   if (use == usx) {
4887     usx = usd;
4888   } else {
4889     usv = usx;
4890   }
4891 #pragma omp atomic compare capture acquire
4892   {
4893     usr = usx == use;
4894     if (usr) {
4895       usx = usd;
4896     }
4897   }
4898 #pragma omp atomic compare capture acquire
4899   {
4900     usr = use == usx;
4901     if (usr) {
4902       usx = usd;
4903     }
4904   }
4905 #pragma omp atomic compare capture acquire
4906   {
4907     usr = usx == use;
4908     if (usr) {
4909       usx = usd;
4910     } else {
4911       usv = usx;
4912     }
4913   }
4914 #pragma omp atomic compare capture acquire
4915   {
4916     usr = use == usx;
4917     if (usr) {
4918       usx = usd;
4919     } else {
4920       usv = usx;
4921     }
4922   }
4923 
4924 #pragma omp atomic compare capture relaxed
4925   {
4926     usv = usx;
4927     if (use > usx) {
4928       usx = use;
4929     }
4930   }
4931 #pragma omp atomic compare capture relaxed
4932   {
4933     usv = usx;
4934     if (usx > use) {
4935       usx = use;
4936     }
4937   }
4938 #pragma omp atomic compare capture relaxed
4939   {
4940     usv = usx;
4941     if (use < usx) {
4942       usx = use;
4943     }
4944   }
4945 #pragma omp atomic compare capture relaxed
4946   {
4947     usv = usx;
4948     if (usx < use) {
4949       usx = use;
4950     }
4951   }
4952 #pragma omp atomic compare capture relaxed
4953   {
4954     usv = usx;
4955     if (usx == use) {
4956       usx = usd;
4957     }
4958   }
4959 #pragma omp atomic compare capture relaxed
4960   {
4961     usv = usx;
4962     if (use == usx) {
4963       usx = usd;
4964     }
4965   }
4966 #pragma omp atomic compare capture relaxed
4967   {
4968     if (use > usx) {
4969       usx = use;
4970     }
4971     usv = usx;
4972   }
4973 #pragma omp atomic compare capture relaxed
4974   {
4975     if (usx > use) {
4976       usx = use;
4977     }
4978     usv = usx;
4979   }
4980 #pragma omp atomic compare capture relaxed
4981   {
4982     if (use < usx) {
4983       usx = use;
4984     }
4985     usv = usx;
4986   }
4987 #pragma omp atomic compare capture relaxed
4988   {
4989     if (usx < use) {
4990       usx = use;
4991     }
4992     usv = usx;
4993   }
4994 #pragma omp atomic compare capture relaxed
4995   {
4996     if (usx == use) {
4997       usx = usd;
4998     }
4999     usv = usx;
5000   }
5001 #pragma omp atomic compare capture relaxed
5002   {
5003     if (use == usx) {
5004       usx = usd;
5005     }
5006     usv = usx;
5007   }
5008 #pragma omp atomic compare capture relaxed
5009   if (usx == use) {
5010     usx = usd;
5011   } else {
5012     usv = usx;
5013   }
5014 #pragma omp atomic compare capture relaxed
5015   if (use == usx) {
5016     usx = usd;
5017   } else {
5018     usv = usx;
5019   }
5020 #pragma omp atomic compare capture relaxed
5021   {
5022     usr = usx == use;
5023     if (usr) {
5024       usx = usd;
5025     }
5026   }
5027 #pragma omp atomic compare capture relaxed
5028   {
5029     usr = use == usx;
5030     if (usr) {
5031       usx = usd;
5032     }
5033   }
5034 #pragma omp atomic compare capture relaxed
5035   {
5036     usr = usx == use;
5037     if (usr) {
5038       usx = usd;
5039     } else {
5040       usv = usx;
5041     }
5042   }
5043 #pragma omp atomic compare capture relaxed
5044   {
5045     usr = use == usx;
5046     if (usr) {
5047       usx = usd;
5048     } else {
5049       usv = usx;
5050     }
5051   }
5052 
5053 #pragma omp atomic compare capture release
5054   {
5055     usv = usx;
5056     if (use > usx) {
5057       usx = use;
5058     }
5059   }
5060 #pragma omp atomic compare capture release
5061   {
5062     usv = usx;
5063     if (usx > use) {
5064       usx = use;
5065     }
5066   }
5067 #pragma omp atomic compare capture release
5068   {
5069     usv = usx;
5070     if (use < usx) {
5071       usx = use;
5072     }
5073   }
5074 #pragma omp atomic compare capture release
5075   {
5076     usv = usx;
5077     if (usx < use) {
5078       usx = use;
5079     }
5080   }
5081 #pragma omp atomic compare capture release
5082   {
5083     usv = usx;
5084     if (usx == use) {
5085       usx = usd;
5086     }
5087   }
5088 #pragma omp atomic compare capture release
5089   {
5090     usv = usx;
5091     if (use == usx) {
5092       usx = usd;
5093     }
5094   }
5095 #pragma omp atomic compare capture release
5096   {
5097     if (use > usx) {
5098       usx = use;
5099     }
5100     usv = usx;
5101   }
5102 #pragma omp atomic compare capture release
5103   {
5104     if (usx > use) {
5105       usx = use;
5106     }
5107     usv = usx;
5108   }
5109 #pragma omp atomic compare capture release
5110   {
5111     if (use < usx) {
5112       usx = use;
5113     }
5114     usv = usx;
5115   }
5116 #pragma omp atomic compare capture release
5117   {
5118     if (usx < use) {
5119       usx = use;
5120     }
5121     usv = usx;
5122   }
5123 #pragma omp atomic compare capture release
5124   {
5125     if (usx == use) {
5126       usx = usd;
5127     }
5128     usv = usx;
5129   }
5130 #pragma omp atomic compare capture release
5131   {
5132     if (use == usx) {
5133       usx = usd;
5134     }
5135     usv = usx;
5136   }
5137 #pragma omp atomic compare capture release
5138   if (usx == use) {
5139     usx = usd;
5140   } else {
5141     usv = usx;
5142   }
5143 #pragma omp atomic compare capture release
5144   if (use == usx) {
5145     usx = usd;
5146   } else {
5147     usv = usx;
5148   }
5149 #pragma omp atomic compare capture release
5150   {
5151     usr = usx == use;
5152     if (usr) {
5153       usx = usd;
5154     }
5155   }
5156 #pragma omp atomic compare capture release
5157   {
5158     usr = use == usx;
5159     if (usr) {
5160       usx = usd;
5161     }
5162   }
5163 #pragma omp atomic compare capture release
5164   {
5165     usr = usx == use;
5166     if (usr) {
5167       usx = usd;
5168     } else {
5169       usv = usx;
5170     }
5171   }
5172 #pragma omp atomic compare capture release
5173   {
5174     usr = use == usx;
5175     if (usr) {
5176       usx = usd;
5177     } else {
5178       usv = usx;
5179     }
5180   }
5181 
5182 #pragma omp atomic compare capture seq_cst
5183   {
5184     usv = usx;
5185     if (use > usx) {
5186       usx = use;
5187     }
5188   }
5189 #pragma omp atomic compare capture seq_cst
5190   {
5191     usv = usx;
5192     if (usx > use) {
5193       usx = use;
5194     }
5195   }
5196 #pragma omp atomic compare capture seq_cst
5197   {
5198     usv = usx;
5199     if (use < usx) {
5200       usx = use;
5201     }
5202   }
5203 #pragma omp atomic compare capture seq_cst
5204   {
5205     usv = usx;
5206     if (usx < use) {
5207       usx = use;
5208     }
5209   }
5210 #pragma omp atomic compare capture seq_cst
5211   {
5212     usv = usx;
5213     if (usx == use) {
5214       usx = usd;
5215     }
5216   }
5217 #pragma omp atomic compare capture seq_cst
5218   {
5219     usv = usx;
5220     if (use == usx) {
5221       usx = usd;
5222     }
5223   }
5224 #pragma omp atomic compare capture seq_cst
5225   {
5226     if (use > usx) {
5227       usx = use;
5228     }
5229     usv = usx;
5230   }
5231 #pragma omp atomic compare capture seq_cst
5232   {
5233     if (usx > use) {
5234       usx = use;
5235     }
5236     usv = usx;
5237   }
5238 #pragma omp atomic compare capture seq_cst
5239   {
5240     if (use < usx) {
5241       usx = use;
5242     }
5243     usv = usx;
5244   }
5245 #pragma omp atomic compare capture seq_cst
5246   {
5247     if (usx < use) {
5248       usx = use;
5249     }
5250     usv = usx;
5251   }
5252 #pragma omp atomic compare capture seq_cst
5253   {
5254     if (usx == use) {
5255       usx = usd;
5256     }
5257     usv = usx;
5258   }
5259 #pragma omp atomic compare capture seq_cst
5260   {
5261     if (use == usx) {
5262       usx = usd;
5263     }
5264     usv = usx;
5265   }
5266 #pragma omp atomic compare capture seq_cst
5267   if (usx == use) {
5268     usx = usd;
5269   } else {
5270     usv = usx;
5271   }
5272 #pragma omp atomic compare capture seq_cst
5273   if (use == usx) {
5274     usx = usd;
5275   } else {
5276     usv = usx;
5277   }
5278 #pragma omp atomic compare capture seq_cst
5279   {
5280     usr = usx == use;
5281     if (usr) {
5282       usx = usd;
5283     }
5284   }
5285 #pragma omp atomic compare capture seq_cst
5286   {
5287     usr = use == usx;
5288     if (usr) {
5289       usx = usd;
5290     }
5291   }
5292 #pragma omp atomic compare capture seq_cst
5293   {
5294     usr = usx == use;
5295     if (usr) {
5296       usx = usd;
5297     } else {
5298       usv = usx;
5299     }
5300   }
5301 #pragma omp atomic compare capture seq_cst
5302   {
5303     usr = use == usx;
5304     if (usr) {
5305       usx = usd;
5306     } else {
5307       usv = usx;
5308     }
5309   }
5310 
5311 #pragma omp atomic compare capture
5312   {
5313     iv = ix;
5314     if (ie > ix) {
5315       ix = ie;
5316     }
5317   }
5318 #pragma omp atomic compare capture
5319   {
5320     iv = ix;
5321     if (ix > ie) {
5322       ix = ie;
5323     }
5324   }
5325 #pragma omp atomic compare capture
5326   {
5327     iv = ix;
5328     if (ie < ix) {
5329       ix = ie;
5330     }
5331   }
5332 #pragma omp atomic compare capture
5333   {
5334     iv = ix;
5335     if (ix < ie) {
5336       ix = ie;
5337     }
5338   }
5339 #pragma omp atomic compare capture
5340   {
5341     iv = ix;
5342     if (ix == ie) {
5343       ix = id;
5344     }
5345   }
5346 #pragma omp atomic compare capture
5347   {
5348     iv = ix;
5349     if (ie == ix) {
5350       ix = id;
5351     }
5352   }
5353 #pragma omp atomic compare capture
5354   {
5355     if (ie > ix) {
5356       ix = ie;
5357     }
5358     iv = ix;
5359   }
5360 #pragma omp atomic compare capture
5361   {
5362     if (ix > ie) {
5363       ix = ie;
5364     }
5365     iv = ix;
5366   }
5367 #pragma omp atomic compare capture
5368   {
5369     if (ie < ix) {
5370       ix = ie;
5371     }
5372     iv = ix;
5373   }
5374 #pragma omp atomic compare capture
5375   {
5376     if (ix < ie) {
5377       ix = ie;
5378     }
5379     iv = ix;
5380   }
5381 #pragma omp atomic compare capture
5382   {
5383     if (ix == ie) {
5384       ix = id;
5385     }
5386     iv = ix;
5387   }
5388 #pragma omp atomic compare capture
5389   {
5390     if (ie == ix) {
5391       ix = id;
5392     }
5393     iv = ix;
5394   }
5395 #pragma omp atomic compare capture
5396   if (ix == ie) {
5397     ix = id;
5398   } else {
5399     iv = ix;
5400   }
5401 #pragma omp atomic compare capture
5402   if (ie == ix) {
5403     ix = id;
5404   } else {
5405     iv = ix;
5406   }
5407 #pragma omp atomic compare capture
5408   {
5409     ir = ix == ie;
5410     if (ir) {
5411       ix = id;
5412     }
5413   }
5414 #pragma omp atomic compare capture
5415   {
5416     ir = ie == ix;
5417     if (ir) {
5418       ix = id;
5419     }
5420   }
5421 #pragma omp atomic compare capture
5422   {
5423     ir = ix == ie;
5424     if (ir) {
5425       ix = id;
5426     } else {
5427       iv = ix;
5428     }
5429   }
5430 #pragma omp atomic compare capture
5431   {
5432     ir = ie == ix;
5433     if (ir) {
5434       ix = id;
5435     } else {
5436       iv = ix;
5437     }
5438   }
5439 
5440 #pragma omp atomic compare capture acq_rel
5441   {
5442     iv = ix;
5443     if (ie > ix) {
5444       ix = ie;
5445     }
5446   }
5447 #pragma omp atomic compare capture acq_rel
5448   {
5449     iv = ix;
5450     if (ix > ie) {
5451       ix = ie;
5452     }
5453   }
5454 #pragma omp atomic compare capture acq_rel
5455   {
5456     iv = ix;
5457     if (ie < ix) {
5458       ix = ie;
5459     }
5460   }
5461 #pragma omp atomic compare capture acq_rel
5462   {
5463     iv = ix;
5464     if (ix < ie) {
5465       ix = ie;
5466     }
5467   }
5468 #pragma omp atomic compare capture acq_rel
5469   {
5470     iv = ix;
5471     if (ix == ie) {
5472       ix = id;
5473     }
5474   }
5475 #pragma omp atomic compare capture acq_rel
5476   {
5477     iv = ix;
5478     if (ie == ix) {
5479       ix = id;
5480     }
5481   }
5482 #pragma omp atomic compare capture acq_rel
5483   {
5484     if (ie > ix) {
5485       ix = ie;
5486     }
5487     iv = ix;
5488   }
5489 #pragma omp atomic compare capture acq_rel
5490   {
5491     if (ix > ie) {
5492       ix = ie;
5493     }
5494     iv = ix;
5495   }
5496 #pragma omp atomic compare capture acq_rel
5497   {
5498     if (ie < ix) {
5499       ix = ie;
5500     }
5501     iv = ix;
5502   }
5503 #pragma omp atomic compare capture acq_rel
5504   {
5505     if (ix < ie) {
5506       ix = ie;
5507     }
5508     iv = ix;
5509   }
5510 #pragma omp atomic compare capture acq_rel
5511   {
5512     if (ix == ie) {
5513       ix = id;
5514     }
5515     iv = ix;
5516   }
5517 #pragma omp atomic compare capture acq_rel
5518   {
5519     if (ie == ix) {
5520       ix = id;
5521     }
5522     iv = ix;
5523   }
5524 #pragma omp atomic compare capture acq_rel
5525   if (ix == ie) {
5526     ix = id;
5527   } else {
5528     iv = ix;
5529   }
5530 #pragma omp atomic compare capture acq_rel
5531   if (ie == ix) {
5532     ix = id;
5533   } else {
5534     iv = ix;
5535   }
5536 #pragma omp atomic compare capture acq_rel
5537   {
5538     ir = ix == ie;
5539     if (ir) {
5540       ix = id;
5541     }
5542   }
5543 #pragma omp atomic compare capture acq_rel
5544   {
5545     ir = ie == ix;
5546     if (ir) {
5547       ix = id;
5548     }
5549   }
5550 #pragma omp atomic compare capture acq_rel
5551   {
5552     ir = ix == ie;
5553     if (ir) {
5554       ix = id;
5555     } else {
5556       iv = ix;
5557     }
5558   }
5559 #pragma omp atomic compare capture acq_rel
5560   {
5561     ir = ie == ix;
5562     if (ir) {
5563       ix = id;
5564     } else {
5565       iv = ix;
5566     }
5567   }
5568 
5569 #pragma omp atomic compare capture acquire
5570   {
5571     iv = ix;
5572     if (ie > ix) {
5573       ix = ie;
5574     }
5575   }
5576 #pragma omp atomic compare capture acquire
5577   {
5578     iv = ix;
5579     if (ix > ie) {
5580       ix = ie;
5581     }
5582   }
5583 #pragma omp atomic compare capture acquire
5584   {
5585     iv = ix;
5586     if (ie < ix) {
5587       ix = ie;
5588     }
5589   }
5590 #pragma omp atomic compare capture acquire
5591   {
5592     iv = ix;
5593     if (ix < ie) {
5594       ix = ie;
5595     }
5596   }
5597 #pragma omp atomic compare capture acquire
5598   {
5599     iv = ix;
5600     if (ix == ie) {
5601       ix = id;
5602     }
5603   }
5604 #pragma omp atomic compare capture acquire
5605   {
5606     iv = ix;
5607     if (ie == ix) {
5608       ix = id;
5609     }
5610   }
5611 #pragma omp atomic compare capture acquire
5612   {
5613     if (ie > ix) {
5614       ix = ie;
5615     }
5616     iv = ix;
5617   }
5618 #pragma omp atomic compare capture acquire
5619   {
5620     if (ix > ie) {
5621       ix = ie;
5622     }
5623     iv = ix;
5624   }
5625 #pragma omp atomic compare capture acquire
5626   {
5627     if (ie < ix) {
5628       ix = ie;
5629     }
5630     iv = ix;
5631   }
5632 #pragma omp atomic compare capture acquire
5633   {
5634     if (ix < ie) {
5635       ix = ie;
5636     }
5637     iv = ix;
5638   }
5639 #pragma omp atomic compare capture acquire
5640   {
5641     if (ix == ie) {
5642       ix = id;
5643     }
5644     iv = ix;
5645   }
5646 #pragma omp atomic compare capture acquire
5647   {
5648     if (ie == ix) {
5649       ix = id;
5650     }
5651     iv = ix;
5652   }
5653 #pragma omp atomic compare capture acquire
5654   if (ix == ie) {
5655     ix = id;
5656   } else {
5657     iv = ix;
5658   }
5659 #pragma omp atomic compare capture acquire
5660   if (ie == ix) {
5661     ix = id;
5662   } else {
5663     iv = ix;
5664   }
5665 #pragma omp atomic compare capture acquire
5666   {
5667     ir = ix == ie;
5668     if (ir) {
5669       ix = id;
5670     }
5671   }
5672 #pragma omp atomic compare capture acquire
5673   {
5674     ir = ie == ix;
5675     if (ir) {
5676       ix = id;
5677     }
5678   }
5679 #pragma omp atomic compare capture acquire
5680   {
5681     ir = ix == ie;
5682     if (ir) {
5683       ix = id;
5684     } else {
5685       iv = ix;
5686     }
5687   }
5688 #pragma omp atomic compare capture acquire
5689   {
5690     ir = ie == ix;
5691     if (ir) {
5692       ix = id;
5693     } else {
5694       iv = ix;
5695     }
5696   }
5697 
5698 #pragma omp atomic compare capture relaxed
5699   {
5700     iv = ix;
5701     if (ie > ix) {
5702       ix = ie;
5703     }
5704   }
5705 #pragma omp atomic compare capture relaxed
5706   {
5707     iv = ix;
5708     if (ix > ie) {
5709       ix = ie;
5710     }
5711   }
5712 #pragma omp atomic compare capture relaxed
5713   {
5714     iv = ix;
5715     if (ie < ix) {
5716       ix = ie;
5717     }
5718   }
5719 #pragma omp atomic compare capture relaxed
5720   {
5721     iv = ix;
5722     if (ix < ie) {
5723       ix = ie;
5724     }
5725   }
5726 #pragma omp atomic compare capture relaxed
5727   {
5728     iv = ix;
5729     if (ix == ie) {
5730       ix = id;
5731     }
5732   }
5733 #pragma omp atomic compare capture relaxed
5734   {
5735     iv = ix;
5736     if (ie == ix) {
5737       ix = id;
5738     }
5739   }
5740 #pragma omp atomic compare capture relaxed
5741   {
5742     if (ie > ix) {
5743       ix = ie;
5744     }
5745     iv = ix;
5746   }
5747 #pragma omp atomic compare capture relaxed
5748   {
5749     if (ix > ie) {
5750       ix = ie;
5751     }
5752     iv = ix;
5753   }
5754 #pragma omp atomic compare capture relaxed
5755   {
5756     if (ie < ix) {
5757       ix = ie;
5758     }
5759     iv = ix;
5760   }
5761 #pragma omp atomic compare capture relaxed
5762   {
5763     if (ix < ie) {
5764       ix = ie;
5765     }
5766     iv = ix;
5767   }
5768 #pragma omp atomic compare capture relaxed
5769   {
5770     if (ix == ie) {
5771       ix = id;
5772     }
5773     iv = ix;
5774   }
5775 #pragma omp atomic compare capture relaxed
5776   {
5777     if (ie == ix) {
5778       ix = id;
5779     }
5780     iv = ix;
5781   }
5782 #pragma omp atomic compare capture relaxed
5783   if (ix == ie) {
5784     ix = id;
5785   } else {
5786     iv = ix;
5787   }
5788 #pragma omp atomic compare capture relaxed
5789   if (ie == ix) {
5790     ix = id;
5791   } else {
5792     iv = ix;
5793   }
5794 #pragma omp atomic compare capture relaxed
5795   {
5796     ir = ix == ie;
5797     if (ir) {
5798       ix = id;
5799     }
5800   }
5801 #pragma omp atomic compare capture relaxed
5802   {
5803     ir = ie == ix;
5804     if (ir) {
5805       ix = id;
5806     }
5807   }
5808 #pragma omp atomic compare capture relaxed
5809   {
5810     ir = ix == ie;
5811     if (ir) {
5812       ix = id;
5813     } else {
5814       iv = ix;
5815     }
5816   }
5817 #pragma omp atomic compare capture relaxed
5818   {
5819     ir = ie == ix;
5820     if (ir) {
5821       ix = id;
5822     } else {
5823       iv = ix;
5824     }
5825   }
5826 
5827 #pragma omp atomic compare capture release
5828   {
5829     iv = ix;
5830     if (ie > ix) {
5831       ix = ie;
5832     }
5833   }
5834 #pragma omp atomic compare capture release
5835   {
5836     iv = ix;
5837     if (ix > ie) {
5838       ix = ie;
5839     }
5840   }
5841 #pragma omp atomic compare capture release
5842   {
5843     iv = ix;
5844     if (ie < ix) {
5845       ix = ie;
5846     }
5847   }
5848 #pragma omp atomic compare capture release
5849   {
5850     iv = ix;
5851     if (ix < ie) {
5852       ix = ie;
5853     }
5854   }
5855 #pragma omp atomic compare capture release
5856   {
5857     iv = ix;
5858     if (ix == ie) {
5859       ix = id;
5860     }
5861   }
5862 #pragma omp atomic compare capture release
5863   {
5864     iv = ix;
5865     if (ie == ix) {
5866       ix = id;
5867     }
5868   }
5869 #pragma omp atomic compare capture release
5870   {
5871     if (ie > ix) {
5872       ix = ie;
5873     }
5874     iv = ix;
5875   }
5876 #pragma omp atomic compare capture release
5877   {
5878     if (ix > ie) {
5879       ix = ie;
5880     }
5881     iv = ix;
5882   }
5883 #pragma omp atomic compare capture release
5884   {
5885     if (ie < ix) {
5886       ix = ie;
5887     }
5888     iv = ix;
5889   }
5890 #pragma omp atomic compare capture release
5891   {
5892     if (ix < ie) {
5893       ix = ie;
5894     }
5895     iv = ix;
5896   }
5897 #pragma omp atomic compare capture release
5898   {
5899     if (ix == ie) {
5900       ix = id;
5901     }
5902     iv = ix;
5903   }
5904 #pragma omp atomic compare capture release
5905   {
5906     if (ie == ix) {
5907       ix = id;
5908     }
5909     iv = ix;
5910   }
5911 #pragma omp atomic compare capture release
5912   if (ix == ie) {
5913     ix = id;
5914   } else {
5915     iv = ix;
5916   }
5917 #pragma omp atomic compare capture release
5918   if (ie == ix) {
5919     ix = id;
5920   } else {
5921     iv = ix;
5922   }
5923 #pragma omp atomic compare capture release
5924   {
5925     ir = ix == ie;
5926     if (ir) {
5927       ix = id;
5928     }
5929   }
5930 #pragma omp atomic compare capture release
5931   {
5932     ir = ie == ix;
5933     if (ir) {
5934       ix = id;
5935     }
5936   }
5937 #pragma omp atomic compare capture release
5938   {
5939     ir = ix == ie;
5940     if (ir) {
5941       ix = id;
5942     } else {
5943       iv = ix;
5944     }
5945   }
5946 #pragma omp atomic compare capture release
5947   {
5948     ir = ie == ix;
5949     if (ir) {
5950       ix = id;
5951     } else {
5952       iv = ix;
5953     }
5954   }
5955 
5956 #pragma omp atomic compare capture seq_cst
5957   {
5958     iv = ix;
5959     if (ie > ix) {
5960       ix = ie;
5961     }
5962   }
5963 #pragma omp atomic compare capture seq_cst
5964   {
5965     iv = ix;
5966     if (ix > ie) {
5967       ix = ie;
5968     }
5969   }
5970 #pragma omp atomic compare capture seq_cst
5971   {
5972     iv = ix;
5973     if (ie < ix) {
5974       ix = ie;
5975     }
5976   }
5977 #pragma omp atomic compare capture seq_cst
5978   {
5979     iv = ix;
5980     if (ix < ie) {
5981       ix = ie;
5982     }
5983   }
5984 #pragma omp atomic compare capture seq_cst
5985   {
5986     iv = ix;
5987     if (ix == ie) {
5988       ix = id;
5989     }
5990   }
5991 #pragma omp atomic compare capture seq_cst
5992   {
5993     iv = ix;
5994     if (ie == ix) {
5995       ix = id;
5996     }
5997   }
5998 #pragma omp atomic compare capture seq_cst
5999   {
6000     if (ie > ix) {
6001       ix = ie;
6002     }
6003     iv = ix;
6004   }
6005 #pragma omp atomic compare capture seq_cst
6006   {
6007     if (ix > ie) {
6008       ix = ie;
6009     }
6010     iv = ix;
6011   }
6012 #pragma omp atomic compare capture seq_cst
6013   {
6014     if (ie < ix) {
6015       ix = ie;
6016     }
6017     iv = ix;
6018   }
6019 #pragma omp atomic compare capture seq_cst
6020   {
6021     if (ix < ie) {
6022       ix = ie;
6023     }
6024     iv = ix;
6025   }
6026 #pragma omp atomic compare capture seq_cst
6027   {
6028     if (ix == ie) {
6029       ix = id;
6030     }
6031     iv = ix;
6032   }
6033 #pragma omp atomic compare capture seq_cst
6034   {
6035     if (ie == ix) {
6036       ix = id;
6037     }
6038     iv = ix;
6039   }
6040 #pragma omp atomic compare capture seq_cst
6041   if (ix == ie) {
6042     ix = id;
6043   } else {
6044     iv = ix;
6045   }
6046 #pragma omp atomic compare capture seq_cst
6047   if (ie == ix) {
6048     ix = id;
6049   } else {
6050     iv = ix;
6051   }
6052 #pragma omp atomic compare capture seq_cst
6053   {
6054     ir = ix == ie;
6055     if (ir) {
6056       ix = id;
6057     }
6058   }
6059 #pragma omp atomic compare capture seq_cst
6060   {
6061     ir = ie == ix;
6062     if (ir) {
6063       ix = id;
6064     }
6065   }
6066 #pragma omp atomic compare capture seq_cst
6067   {
6068     ir = ix == ie;
6069     if (ir) {
6070       ix = id;
6071     } else {
6072       iv = ix;
6073     }
6074   }
6075 #pragma omp atomic compare capture seq_cst
6076   {
6077     ir = ie == ix;
6078     if (ir) {
6079       ix = id;
6080     } else {
6081       iv = ix;
6082     }
6083   }
6084 
6085 #pragma omp atomic compare capture
6086   {
6087     uiv = uix;
6088     if (uie > uix) {
6089       uix = uie;
6090     }
6091   }
6092 #pragma omp atomic compare capture
6093   {
6094     uiv = uix;
6095     if (uix > uie) {
6096       uix = uie;
6097     }
6098   }
6099 #pragma omp atomic compare capture
6100   {
6101     uiv = uix;
6102     if (uie < uix) {
6103       uix = uie;
6104     }
6105   }
6106 #pragma omp atomic compare capture
6107   {
6108     uiv = uix;
6109     if (uix < uie) {
6110       uix = uie;
6111     }
6112   }
6113 #pragma omp atomic compare capture
6114   {
6115     uiv = uix;
6116     if (uix == uie) {
6117       uix = uid;
6118     }
6119   }
6120 #pragma omp atomic compare capture
6121   {
6122     uiv = uix;
6123     if (uie == uix) {
6124       uix = uid;
6125     }
6126   }
6127 #pragma omp atomic compare capture
6128   {
6129     if (uie > uix) {
6130       uix = uie;
6131     }
6132     uiv = uix;
6133   }
6134 #pragma omp atomic compare capture
6135   {
6136     if (uix > uie) {
6137       uix = uie;
6138     }
6139     uiv = uix;
6140   }
6141 #pragma omp atomic compare capture
6142   {
6143     if (uie < uix) {
6144       uix = uie;
6145     }
6146     uiv = uix;
6147   }
6148 #pragma omp atomic compare capture
6149   {
6150     if (uix < uie) {
6151       uix = uie;
6152     }
6153     uiv = uix;
6154   }
6155 #pragma omp atomic compare capture
6156   {
6157     if (uix == uie) {
6158       uix = uid;
6159     }
6160     uiv = uix;
6161   }
6162 #pragma omp atomic compare capture
6163   {
6164     if (uie == uix) {
6165       uix = uid;
6166     }
6167     uiv = uix;
6168   }
6169 #pragma omp atomic compare capture
6170   if (uix == uie) {
6171     uix = uid;
6172   } else {
6173     uiv = uix;
6174   }
6175 #pragma omp atomic compare capture
6176   if (uie == uix) {
6177     uix = uid;
6178   } else {
6179     uiv = uix;
6180   }
6181 #pragma omp atomic compare capture
6182   {
6183     uir = uix == uie;
6184     if (uir) {
6185       uix = uid;
6186     }
6187   }
6188 #pragma omp atomic compare capture
6189   {
6190     uir = uie == uix;
6191     if (uir) {
6192       uix = uid;
6193     }
6194   }
6195 #pragma omp atomic compare capture
6196   {
6197     uir = uix == uie;
6198     if (uir) {
6199       uix = uid;
6200     } else {
6201       uiv = uix;
6202     }
6203   }
6204 #pragma omp atomic compare capture
6205   {
6206     uir = uie == uix;
6207     if (uir) {
6208       uix = uid;
6209     } else {
6210       uiv = uix;
6211     }
6212   }
6213 
6214 #pragma omp atomic compare capture acq_rel
6215   {
6216     uiv = uix;
6217     if (uie > uix) {
6218       uix = uie;
6219     }
6220   }
6221 #pragma omp atomic compare capture acq_rel
6222   {
6223     uiv = uix;
6224     if (uix > uie) {
6225       uix = uie;
6226     }
6227   }
6228 #pragma omp atomic compare capture acq_rel
6229   {
6230     uiv = uix;
6231     if (uie < uix) {
6232       uix = uie;
6233     }
6234   }
6235 #pragma omp atomic compare capture acq_rel
6236   {
6237     uiv = uix;
6238     if (uix < uie) {
6239       uix = uie;
6240     }
6241   }
6242 #pragma omp atomic compare capture acq_rel
6243   {
6244     uiv = uix;
6245     if (uix == uie) {
6246       uix = uid;
6247     }
6248   }
6249 #pragma omp atomic compare capture acq_rel
6250   {
6251     uiv = uix;
6252     if (uie == uix) {
6253       uix = uid;
6254     }
6255   }
6256 #pragma omp atomic compare capture acq_rel
6257   {
6258     if (uie > uix) {
6259       uix = uie;
6260     }
6261     uiv = uix;
6262   }
6263 #pragma omp atomic compare capture acq_rel
6264   {
6265     if (uix > uie) {
6266       uix = uie;
6267     }
6268     uiv = uix;
6269   }
6270 #pragma omp atomic compare capture acq_rel
6271   {
6272     if (uie < uix) {
6273       uix = uie;
6274     }
6275     uiv = uix;
6276   }
6277 #pragma omp atomic compare capture acq_rel
6278   {
6279     if (uix < uie) {
6280       uix = uie;
6281     }
6282     uiv = uix;
6283   }
6284 #pragma omp atomic compare capture acq_rel
6285   {
6286     if (uix == uie) {
6287       uix = uid;
6288     }
6289     uiv = uix;
6290   }
6291 #pragma omp atomic compare capture acq_rel
6292   {
6293     if (uie == uix) {
6294       uix = uid;
6295     }
6296     uiv = uix;
6297   }
6298 #pragma omp atomic compare capture acq_rel
6299   if (uix == uie) {
6300     uix = uid;
6301   } else {
6302     uiv = uix;
6303   }
6304 #pragma omp atomic compare capture acq_rel
6305   if (uie == uix) {
6306     uix = uid;
6307   } else {
6308     uiv = uix;
6309   }
6310 #pragma omp atomic compare capture acq_rel
6311   {
6312     uir = uix == uie;
6313     if (uir) {
6314       uix = uid;
6315     }
6316   }
6317 #pragma omp atomic compare capture acq_rel
6318   {
6319     uir = uie == uix;
6320     if (uir) {
6321       uix = uid;
6322     }
6323   }
6324 #pragma omp atomic compare capture acq_rel
6325   {
6326     uir = uix == uie;
6327     if (uir) {
6328       uix = uid;
6329     } else {
6330       uiv = uix;
6331     }
6332   }
6333 #pragma omp atomic compare capture acq_rel
6334   {
6335     uir = uie == uix;
6336     if (uir) {
6337       uix = uid;
6338     } else {
6339       uiv = uix;
6340     }
6341   }
6342 
6343 #pragma omp atomic compare capture acquire
6344   {
6345     uiv = uix;
6346     if (uie > uix) {
6347       uix = uie;
6348     }
6349   }
6350 #pragma omp atomic compare capture acquire
6351   {
6352     uiv = uix;
6353     if (uix > uie) {
6354       uix = uie;
6355     }
6356   }
6357 #pragma omp atomic compare capture acquire
6358   {
6359     uiv = uix;
6360     if (uie < uix) {
6361       uix = uie;
6362     }
6363   }
6364 #pragma omp atomic compare capture acquire
6365   {
6366     uiv = uix;
6367     if (uix < uie) {
6368       uix = uie;
6369     }
6370   }
6371 #pragma omp atomic compare capture acquire
6372   {
6373     uiv = uix;
6374     if (uix == uie) {
6375       uix = uid;
6376     }
6377   }
6378 #pragma omp atomic compare capture acquire
6379   {
6380     uiv = uix;
6381     if (uie == uix) {
6382       uix = uid;
6383     }
6384   }
6385 #pragma omp atomic compare capture acquire
6386   {
6387     if (uie > uix) {
6388       uix = uie;
6389     }
6390     uiv = uix;
6391   }
6392 #pragma omp atomic compare capture acquire
6393   {
6394     if (uix > uie) {
6395       uix = uie;
6396     }
6397     uiv = uix;
6398   }
6399 #pragma omp atomic compare capture acquire
6400   {
6401     if (uie < uix) {
6402       uix = uie;
6403     }
6404     uiv = uix;
6405   }
6406 #pragma omp atomic compare capture acquire
6407   {
6408     if (uix < uie) {
6409       uix = uie;
6410     }
6411     uiv = uix;
6412   }
6413 #pragma omp atomic compare capture acquire
6414   {
6415     if (uix == uie) {
6416       uix = uid;
6417     }
6418     uiv = uix;
6419   }
6420 #pragma omp atomic compare capture acquire
6421   {
6422     if (uie == uix) {
6423       uix = uid;
6424     }
6425     uiv = uix;
6426   }
6427 #pragma omp atomic compare capture acquire
6428   if (uix == uie) {
6429     uix = uid;
6430   } else {
6431     uiv = uix;
6432   }
6433 #pragma omp atomic compare capture acquire
6434   if (uie == uix) {
6435     uix = uid;
6436   } else {
6437     uiv = uix;
6438   }
6439 #pragma omp atomic compare capture acquire
6440   {
6441     uir = uix == uie;
6442     if (uir) {
6443       uix = uid;
6444     }
6445   }
6446 #pragma omp atomic compare capture acquire
6447   {
6448     uir = uie == uix;
6449     if (uir) {
6450       uix = uid;
6451     }
6452   }
6453 #pragma omp atomic compare capture acquire
6454   {
6455     uir = uix == uie;
6456     if (uir) {
6457       uix = uid;
6458     } else {
6459       uiv = uix;
6460     }
6461   }
6462 #pragma omp atomic compare capture acquire
6463   {
6464     uir = uie == uix;
6465     if (uir) {
6466       uix = uid;
6467     } else {
6468       uiv = uix;
6469     }
6470   }
6471 
6472 #pragma omp atomic compare capture relaxed
6473   {
6474     uiv = uix;
6475     if (uie > uix) {
6476       uix = uie;
6477     }
6478   }
6479 #pragma omp atomic compare capture relaxed
6480   {
6481     uiv = uix;
6482     if (uix > uie) {
6483       uix = uie;
6484     }
6485   }
6486 #pragma omp atomic compare capture relaxed
6487   {
6488     uiv = uix;
6489     if (uie < uix) {
6490       uix = uie;
6491     }
6492   }
6493 #pragma omp atomic compare capture relaxed
6494   {
6495     uiv = uix;
6496     if (uix < uie) {
6497       uix = uie;
6498     }
6499   }
6500 #pragma omp atomic compare capture relaxed
6501   {
6502     uiv = uix;
6503     if (uix == uie) {
6504       uix = uid;
6505     }
6506   }
6507 #pragma omp atomic compare capture relaxed
6508   {
6509     uiv = uix;
6510     if (uie == uix) {
6511       uix = uid;
6512     }
6513   }
6514 #pragma omp atomic compare capture relaxed
6515   {
6516     if (uie > uix) {
6517       uix = uie;
6518     }
6519     uiv = uix;
6520   }
6521 #pragma omp atomic compare capture relaxed
6522   {
6523     if (uix > uie) {
6524       uix = uie;
6525     }
6526     uiv = uix;
6527   }
6528 #pragma omp atomic compare capture relaxed
6529   {
6530     if (uie < uix) {
6531       uix = uie;
6532     }
6533     uiv = uix;
6534   }
6535 #pragma omp atomic compare capture relaxed
6536   {
6537     if (uix < uie) {
6538       uix = uie;
6539     }
6540     uiv = uix;
6541   }
6542 #pragma omp atomic compare capture relaxed
6543   {
6544     if (uix == uie) {
6545       uix = uid;
6546     }
6547     uiv = uix;
6548   }
6549 #pragma omp atomic compare capture relaxed
6550   {
6551     if (uie == uix) {
6552       uix = uid;
6553     }
6554     uiv = uix;
6555   }
6556 #pragma omp atomic compare capture relaxed
6557   if (uix == uie) {
6558     uix = uid;
6559   } else {
6560     uiv = uix;
6561   }
6562 #pragma omp atomic compare capture relaxed
6563   if (uie == uix) {
6564     uix = uid;
6565   } else {
6566     uiv = uix;
6567   }
6568 #pragma omp atomic compare capture relaxed
6569   {
6570     uir = uix == uie;
6571     if (uir) {
6572       uix = uid;
6573     }
6574   }
6575 #pragma omp atomic compare capture relaxed
6576   {
6577     uir = uie == uix;
6578     if (uir) {
6579       uix = uid;
6580     }
6581   }
6582 #pragma omp atomic compare capture relaxed
6583   {
6584     uir = uix == uie;
6585     if (uir) {
6586       uix = uid;
6587     } else {
6588       uiv = uix;
6589     }
6590   }
6591 #pragma omp atomic compare capture relaxed
6592   {
6593     uir = uie == uix;
6594     if (uir) {
6595       uix = uid;
6596     } else {
6597       uiv = uix;
6598     }
6599   }
6600 
6601 #pragma omp atomic compare capture release
6602   {
6603     uiv = uix;
6604     if (uie > uix) {
6605       uix = uie;
6606     }
6607   }
6608 #pragma omp atomic compare capture release
6609   {
6610     uiv = uix;
6611     if (uix > uie) {
6612       uix = uie;
6613     }
6614   }
6615 #pragma omp atomic compare capture release
6616   {
6617     uiv = uix;
6618     if (uie < uix) {
6619       uix = uie;
6620     }
6621   }
6622 #pragma omp atomic compare capture release
6623   {
6624     uiv = uix;
6625     if (uix < uie) {
6626       uix = uie;
6627     }
6628   }
6629 #pragma omp atomic compare capture release
6630   {
6631     uiv = uix;
6632     if (uix == uie) {
6633       uix = uid;
6634     }
6635   }
6636 #pragma omp atomic compare capture release
6637   {
6638     uiv = uix;
6639     if (uie == uix) {
6640       uix = uid;
6641     }
6642   }
6643 #pragma omp atomic compare capture release
6644   {
6645     if (uie > uix) {
6646       uix = uie;
6647     }
6648     uiv = uix;
6649   }
6650 #pragma omp atomic compare capture release
6651   {
6652     if (uix > uie) {
6653       uix = uie;
6654     }
6655     uiv = uix;
6656   }
6657 #pragma omp atomic compare capture release
6658   {
6659     if (uie < uix) {
6660       uix = uie;
6661     }
6662     uiv = uix;
6663   }
6664 #pragma omp atomic compare capture release
6665   {
6666     if (uix < uie) {
6667       uix = uie;
6668     }
6669     uiv = uix;
6670   }
6671 #pragma omp atomic compare capture release
6672   {
6673     if (uix == uie) {
6674       uix = uid;
6675     }
6676     uiv = uix;
6677   }
6678 #pragma omp atomic compare capture release
6679   {
6680     if (uie == uix) {
6681       uix = uid;
6682     }
6683     uiv = uix;
6684   }
6685 #pragma omp atomic compare capture release
6686   if (uix == uie) {
6687     uix = uid;
6688   } else {
6689     uiv = uix;
6690   }
6691 #pragma omp atomic compare capture release
6692   if (uie == uix) {
6693     uix = uid;
6694   } else {
6695     uiv = uix;
6696   }
6697 #pragma omp atomic compare capture release
6698   {
6699     uir = uix == uie;
6700     if (uir) {
6701       uix = uid;
6702     }
6703   }
6704 #pragma omp atomic compare capture release
6705   {
6706     uir = uie == uix;
6707     if (uir) {
6708       uix = uid;
6709     }
6710   }
6711 #pragma omp atomic compare capture release
6712   {
6713     uir = uix == uie;
6714     if (uir) {
6715       uix = uid;
6716     } else {
6717       uiv = uix;
6718     }
6719   }
6720 #pragma omp atomic compare capture release
6721   {
6722     uir = uie == uix;
6723     if (uir) {
6724       uix = uid;
6725     } else {
6726       uiv = uix;
6727     }
6728   }
6729 
6730 #pragma omp atomic compare capture seq_cst
6731   {
6732     uiv = uix;
6733     if (uie > uix) {
6734       uix = uie;
6735     }
6736   }
6737 #pragma omp atomic compare capture seq_cst
6738   {
6739     uiv = uix;
6740     if (uix > uie) {
6741       uix = uie;
6742     }
6743   }
6744 #pragma omp atomic compare capture seq_cst
6745   {
6746     uiv = uix;
6747     if (uie < uix) {
6748       uix = uie;
6749     }
6750   }
6751 #pragma omp atomic compare capture seq_cst
6752   {
6753     uiv = uix;
6754     if (uix < uie) {
6755       uix = uie;
6756     }
6757   }
6758 #pragma omp atomic compare capture seq_cst
6759   {
6760     uiv = uix;
6761     if (uix == uie) {
6762       uix = uid;
6763     }
6764   }
6765 #pragma omp atomic compare capture seq_cst
6766   {
6767     uiv = uix;
6768     if (uie == uix) {
6769       uix = uid;
6770     }
6771   }
6772 #pragma omp atomic compare capture seq_cst
6773   {
6774     if (uie > uix) {
6775       uix = uie;
6776     }
6777     uiv = uix;
6778   }
6779 #pragma omp atomic compare capture seq_cst
6780   {
6781     if (uix > uie) {
6782       uix = uie;
6783     }
6784     uiv = uix;
6785   }
6786 #pragma omp atomic compare capture seq_cst
6787   {
6788     if (uie < uix) {
6789       uix = uie;
6790     }
6791     uiv = uix;
6792   }
6793 #pragma omp atomic compare capture seq_cst
6794   {
6795     if (uix < uie) {
6796       uix = uie;
6797     }
6798     uiv = uix;
6799   }
6800 #pragma omp atomic compare capture seq_cst
6801   {
6802     if (uix == uie) {
6803       uix = uid;
6804     }
6805     uiv = uix;
6806   }
6807 #pragma omp atomic compare capture seq_cst
6808   {
6809     if (uie == uix) {
6810       uix = uid;
6811     }
6812     uiv = uix;
6813   }
6814 #pragma omp atomic compare capture seq_cst
6815   if (uix == uie) {
6816     uix = uid;
6817   } else {
6818     uiv = uix;
6819   }
6820 #pragma omp atomic compare capture seq_cst
6821   if (uie == uix) {
6822     uix = uid;
6823   } else {
6824     uiv = uix;
6825   }
6826 #pragma omp atomic compare capture seq_cst
6827   {
6828     uir = uix == uie;
6829     if (uir) {
6830       uix = uid;
6831     }
6832   }
6833 #pragma omp atomic compare capture seq_cst
6834   {
6835     uir = uie == uix;
6836     if (uir) {
6837       uix = uid;
6838     }
6839   }
6840 #pragma omp atomic compare capture seq_cst
6841   {
6842     uir = uix == uie;
6843     if (uir) {
6844       uix = uid;
6845     } else {
6846       uiv = uix;
6847     }
6848   }
6849 #pragma omp atomic compare capture seq_cst
6850   {
6851     uir = uie == uix;
6852     if (uir) {
6853       uix = uid;
6854     } else {
6855       uiv = uix;
6856     }
6857   }
6858 
6859 #pragma omp atomic compare capture
6860   {
6861     lv = lx;
6862     if (le > lx) {
6863       lx = le;
6864     }
6865   }
6866 #pragma omp atomic compare capture
6867   {
6868     lv = lx;
6869     if (lx > le) {
6870       lx = le;
6871     }
6872   }
6873 #pragma omp atomic compare capture
6874   {
6875     lv = lx;
6876     if (le < lx) {
6877       lx = le;
6878     }
6879   }
6880 #pragma omp atomic compare capture
6881   {
6882     lv = lx;
6883     if (lx < le) {
6884       lx = le;
6885     }
6886   }
6887 #pragma omp atomic compare capture
6888   {
6889     lv = lx;
6890     if (lx == le) {
6891       lx = ld;
6892     }
6893   }
6894 #pragma omp atomic compare capture
6895   {
6896     lv = lx;
6897     if (le == lx) {
6898       lx = ld;
6899     }
6900   }
6901 #pragma omp atomic compare capture
6902   {
6903     if (le > lx) {
6904       lx = le;
6905     }
6906     lv = lx;
6907   }
6908 #pragma omp atomic compare capture
6909   {
6910     if (lx > le) {
6911       lx = le;
6912     }
6913     lv = lx;
6914   }
6915 #pragma omp atomic compare capture
6916   {
6917     if (le < lx) {
6918       lx = le;
6919     }
6920     lv = lx;
6921   }
6922 #pragma omp atomic compare capture
6923   {
6924     if (lx < le) {
6925       lx = le;
6926     }
6927     lv = lx;
6928   }
6929 #pragma omp atomic compare capture
6930   {
6931     if (lx == le) {
6932       lx = ld;
6933     }
6934     lv = lx;
6935   }
6936 #pragma omp atomic compare capture
6937   {
6938     if (le == lx) {
6939       lx = ld;
6940     }
6941     lv = lx;
6942   }
6943 #pragma omp atomic compare capture
6944   if (lx == le) {
6945     lx = ld;
6946   } else {
6947     lv = lx;
6948   }
6949 #pragma omp atomic compare capture
6950   if (le == lx) {
6951     lx = ld;
6952   } else {
6953     lv = lx;
6954   }
6955 #pragma omp atomic compare capture
6956   {
6957     lr = lx == le;
6958     if (lr) {
6959       lx = ld;
6960     }
6961   }
6962 #pragma omp atomic compare capture
6963   {
6964     lr = le == lx;
6965     if (lr) {
6966       lx = ld;
6967     }
6968   }
6969 #pragma omp atomic compare capture
6970   {
6971     lr = lx == le;
6972     if (lr) {
6973       lx = ld;
6974     } else {
6975       lv = lx;
6976     }
6977   }
6978 #pragma omp atomic compare capture
6979   {
6980     lr = le == lx;
6981     if (lr) {
6982       lx = ld;
6983     } else {
6984       lv = lx;
6985     }
6986   }
6987 
6988 #pragma omp atomic compare capture acq_rel
6989   {
6990     lv = lx;
6991     if (le > lx) {
6992       lx = le;
6993     }
6994   }
6995 #pragma omp atomic compare capture acq_rel
6996   {
6997     lv = lx;
6998     if (lx > le) {
6999       lx = le;
7000     }
7001   }
7002 #pragma omp atomic compare capture acq_rel
7003   {
7004     lv = lx;
7005     if (le < lx) {
7006       lx = le;
7007     }
7008   }
7009 #pragma omp atomic compare capture acq_rel
7010   {
7011     lv = lx;
7012     if (lx < le) {
7013       lx = le;
7014     }
7015   }
7016 #pragma omp atomic compare capture acq_rel
7017   {
7018     lv = lx;
7019     if (lx == le) {
7020       lx = ld;
7021     }
7022   }
7023 #pragma omp atomic compare capture acq_rel
7024   {
7025     lv = lx;
7026     if (le == lx) {
7027       lx = ld;
7028     }
7029   }
7030 #pragma omp atomic compare capture acq_rel
7031   {
7032     if (le > lx) {
7033       lx = le;
7034     }
7035     lv = lx;
7036   }
7037 #pragma omp atomic compare capture acq_rel
7038   {
7039     if (lx > le) {
7040       lx = le;
7041     }
7042     lv = lx;
7043   }
7044 #pragma omp atomic compare capture acq_rel
7045   {
7046     if (le < lx) {
7047       lx = le;
7048     }
7049     lv = lx;
7050   }
7051 #pragma omp atomic compare capture acq_rel
7052   {
7053     if (lx < le) {
7054       lx = le;
7055     }
7056     lv = lx;
7057   }
7058 #pragma omp atomic compare capture acq_rel
7059   {
7060     if (lx == le) {
7061       lx = ld;
7062     }
7063     lv = lx;
7064   }
7065 #pragma omp atomic compare capture acq_rel
7066   {
7067     if (le == lx) {
7068       lx = ld;
7069     }
7070     lv = lx;
7071   }
7072 #pragma omp atomic compare capture acq_rel
7073   if (lx == le) {
7074     lx = ld;
7075   } else {
7076     lv = lx;
7077   }
7078 #pragma omp atomic compare capture acq_rel
7079   if (le == lx) {
7080     lx = ld;
7081   } else {
7082     lv = lx;
7083   }
7084 #pragma omp atomic compare capture acq_rel
7085   {
7086     lr = lx == le;
7087     if (lr) {
7088       lx = ld;
7089     }
7090   }
7091 #pragma omp atomic compare capture acq_rel
7092   {
7093     lr = le == lx;
7094     if (lr) {
7095       lx = ld;
7096     }
7097   }
7098 #pragma omp atomic compare capture acq_rel
7099   {
7100     lr = lx == le;
7101     if (lr) {
7102       lx = ld;
7103     } else {
7104       lv = lx;
7105     }
7106   }
7107 #pragma omp atomic compare capture acq_rel
7108   {
7109     lr = le == lx;
7110     if (lr) {
7111       lx = ld;
7112     } else {
7113       lv = lx;
7114     }
7115   }
7116 
7117 #pragma omp atomic compare capture acquire
7118   {
7119     lv = lx;
7120     if (le > lx) {
7121       lx = le;
7122     }
7123   }
7124 #pragma omp atomic compare capture acquire
7125   {
7126     lv = lx;
7127     if (lx > le) {
7128       lx = le;
7129     }
7130   }
7131 #pragma omp atomic compare capture acquire
7132   {
7133     lv = lx;
7134     if (le < lx) {
7135       lx = le;
7136     }
7137   }
7138 #pragma omp atomic compare capture acquire
7139   {
7140     lv = lx;
7141     if (lx < le) {
7142       lx = le;
7143     }
7144   }
7145 #pragma omp atomic compare capture acquire
7146   {
7147     lv = lx;
7148     if (lx == le) {
7149       lx = ld;
7150     }
7151   }
7152 #pragma omp atomic compare capture acquire
7153   {
7154     lv = lx;
7155     if (le == lx) {
7156       lx = ld;
7157     }
7158   }
7159 #pragma omp atomic compare capture acquire
7160   {
7161     if (le > lx) {
7162       lx = le;
7163     }
7164     lv = lx;
7165   }
7166 #pragma omp atomic compare capture acquire
7167   {
7168     if (lx > le) {
7169       lx = le;
7170     }
7171     lv = lx;
7172   }
7173 #pragma omp atomic compare capture acquire
7174   {
7175     if (le < lx) {
7176       lx = le;
7177     }
7178     lv = lx;
7179   }
7180 #pragma omp atomic compare capture acquire
7181   {
7182     if (lx < le) {
7183       lx = le;
7184     }
7185     lv = lx;
7186   }
7187 #pragma omp atomic compare capture acquire
7188   {
7189     if (lx == le) {
7190       lx = ld;
7191     }
7192     lv = lx;
7193   }
7194 #pragma omp atomic compare capture acquire
7195   {
7196     if (le == lx) {
7197       lx = ld;
7198     }
7199     lv = lx;
7200   }
7201 #pragma omp atomic compare capture acquire
7202   if (lx == le) {
7203     lx = ld;
7204   } else {
7205     lv = lx;
7206   }
7207 #pragma omp atomic compare capture acquire
7208   if (le == lx) {
7209     lx = ld;
7210   } else {
7211     lv = lx;
7212   }
7213 #pragma omp atomic compare capture acquire
7214   {
7215     lr = lx == le;
7216     if (lr) {
7217       lx = ld;
7218     }
7219   }
7220 #pragma omp atomic compare capture acquire
7221   {
7222     lr = le == lx;
7223     if (lr) {
7224       lx = ld;
7225     }
7226   }
7227 #pragma omp atomic compare capture acquire
7228   {
7229     lr = lx == le;
7230     if (lr) {
7231       lx = ld;
7232     } else {
7233       lv = lx;
7234     }
7235   }
7236 #pragma omp atomic compare capture acquire
7237   {
7238     lr = le == lx;
7239     if (lr) {
7240       lx = ld;
7241     } else {
7242       lv = lx;
7243     }
7244   }
7245 
7246 #pragma omp atomic compare capture relaxed
7247   {
7248     lv = lx;
7249     if (le > lx) {
7250       lx = le;
7251     }
7252   }
7253 #pragma omp atomic compare capture relaxed
7254   {
7255     lv = lx;
7256     if (lx > le) {
7257       lx = le;
7258     }
7259   }
7260 #pragma omp atomic compare capture relaxed
7261   {
7262     lv = lx;
7263     if (le < lx) {
7264       lx = le;
7265     }
7266   }
7267 #pragma omp atomic compare capture relaxed
7268   {
7269     lv = lx;
7270     if (lx < le) {
7271       lx = le;
7272     }
7273   }
7274 #pragma omp atomic compare capture relaxed
7275   {
7276     lv = lx;
7277     if (lx == le) {
7278       lx = ld;
7279     }
7280   }
7281 #pragma omp atomic compare capture relaxed
7282   {
7283     lv = lx;
7284     if (le == lx) {
7285       lx = ld;
7286     }
7287   }
7288 #pragma omp atomic compare capture relaxed
7289   {
7290     if (le > lx) {
7291       lx = le;
7292     }
7293     lv = lx;
7294   }
7295 #pragma omp atomic compare capture relaxed
7296   {
7297     if (lx > le) {
7298       lx = le;
7299     }
7300     lv = lx;
7301   }
7302 #pragma omp atomic compare capture relaxed
7303   {
7304     if (le < lx) {
7305       lx = le;
7306     }
7307     lv = lx;
7308   }
7309 #pragma omp atomic compare capture relaxed
7310   {
7311     if (lx < le) {
7312       lx = le;
7313     }
7314     lv = lx;
7315   }
7316 #pragma omp atomic compare capture relaxed
7317   {
7318     if (lx == le) {
7319       lx = ld;
7320     }
7321     lv = lx;
7322   }
7323 #pragma omp atomic compare capture relaxed
7324   {
7325     if (le == lx) {
7326       lx = ld;
7327     }
7328     lv = lx;
7329   }
7330 #pragma omp atomic compare capture relaxed
7331   if (lx == le) {
7332     lx = ld;
7333   } else {
7334     lv = lx;
7335   }
7336 #pragma omp atomic compare capture relaxed
7337   if (le == lx) {
7338     lx = ld;
7339   } else {
7340     lv = lx;
7341   }
7342 #pragma omp atomic compare capture relaxed
7343   {
7344     lr = lx == le;
7345     if (lr) {
7346       lx = ld;
7347     }
7348   }
7349 #pragma omp atomic compare capture relaxed
7350   {
7351     lr = le == lx;
7352     if (lr) {
7353       lx = ld;
7354     }
7355   }
7356 #pragma omp atomic compare capture relaxed
7357   {
7358     lr = lx == le;
7359     if (lr) {
7360       lx = ld;
7361     } else {
7362       lv = lx;
7363     }
7364   }
7365 #pragma omp atomic compare capture relaxed
7366   {
7367     lr = le == lx;
7368     if (lr) {
7369       lx = ld;
7370     } else {
7371       lv = lx;
7372     }
7373   }
7374 
7375 #pragma omp atomic compare capture release
7376   {
7377     lv = lx;
7378     if (le > lx) {
7379       lx = le;
7380     }
7381   }
7382 #pragma omp atomic compare capture release
7383   {
7384     lv = lx;
7385     if (lx > le) {
7386       lx = le;
7387     }
7388   }
7389 #pragma omp atomic compare capture release
7390   {
7391     lv = lx;
7392     if (le < lx) {
7393       lx = le;
7394     }
7395   }
7396 #pragma omp atomic compare capture release
7397   {
7398     lv = lx;
7399     if (lx < le) {
7400       lx = le;
7401     }
7402   }
7403 #pragma omp atomic compare capture release
7404   {
7405     lv = lx;
7406     if (lx == le) {
7407       lx = ld;
7408     }
7409   }
7410 #pragma omp atomic compare capture release
7411   {
7412     lv = lx;
7413     if (le == lx) {
7414       lx = ld;
7415     }
7416   }
7417 #pragma omp atomic compare capture release
7418   {
7419     if (le > lx) {
7420       lx = le;
7421     }
7422     lv = lx;
7423   }
7424 #pragma omp atomic compare capture release
7425   {
7426     if (lx > le) {
7427       lx = le;
7428     }
7429     lv = lx;
7430   }
7431 #pragma omp atomic compare capture release
7432   {
7433     if (le < lx) {
7434       lx = le;
7435     }
7436     lv = lx;
7437   }
7438 #pragma omp atomic compare capture release
7439   {
7440     if (lx < le) {
7441       lx = le;
7442     }
7443     lv = lx;
7444   }
7445 #pragma omp atomic compare capture release
7446   {
7447     if (lx == le) {
7448       lx = ld;
7449     }
7450     lv = lx;
7451   }
7452 #pragma omp atomic compare capture release
7453   {
7454     if (le == lx) {
7455       lx = ld;
7456     }
7457     lv = lx;
7458   }
7459 #pragma omp atomic compare capture release
7460   if (lx == le) {
7461     lx = ld;
7462   } else {
7463     lv = lx;
7464   }
7465 #pragma omp atomic compare capture release
7466   if (le == lx) {
7467     lx = ld;
7468   } else {
7469     lv = lx;
7470   }
7471 #pragma omp atomic compare capture release
7472   {
7473     lr = lx == le;
7474     if (lr) {
7475       lx = ld;
7476     }
7477   }
7478 #pragma omp atomic compare capture release
7479   {
7480     lr = le == lx;
7481     if (lr) {
7482       lx = ld;
7483     }
7484   }
7485 #pragma omp atomic compare capture release
7486   {
7487     lr = lx == le;
7488     if (lr) {
7489       lx = ld;
7490     } else {
7491       lv = lx;
7492     }
7493   }
7494 #pragma omp atomic compare capture release
7495   {
7496     lr = le == lx;
7497     if (lr) {
7498       lx = ld;
7499     } else {
7500       lv = lx;
7501     }
7502   }
7503 
7504 #pragma omp atomic compare capture seq_cst
7505   {
7506     lv = lx;
7507     if (le > lx) {
7508       lx = le;
7509     }
7510   }
7511 #pragma omp atomic compare capture seq_cst
7512   {
7513     lv = lx;
7514     if (lx > le) {
7515       lx = le;
7516     }
7517   }
7518 #pragma omp atomic compare capture seq_cst
7519   {
7520     lv = lx;
7521     if (le < lx) {
7522       lx = le;
7523     }
7524   }
7525 #pragma omp atomic compare capture seq_cst
7526   {
7527     lv = lx;
7528     if (lx < le) {
7529       lx = le;
7530     }
7531   }
7532 #pragma omp atomic compare capture seq_cst
7533   {
7534     lv = lx;
7535     if (lx == le) {
7536       lx = ld;
7537     }
7538   }
7539 #pragma omp atomic compare capture seq_cst
7540   {
7541     lv = lx;
7542     if (le == lx) {
7543       lx = ld;
7544     }
7545   }
7546 #pragma omp atomic compare capture seq_cst
7547   {
7548     if (le > lx) {
7549       lx = le;
7550     }
7551     lv = lx;
7552   }
7553 #pragma omp atomic compare capture seq_cst
7554   {
7555     if (lx > le) {
7556       lx = le;
7557     }
7558     lv = lx;
7559   }
7560 #pragma omp atomic compare capture seq_cst
7561   {
7562     if (le < lx) {
7563       lx = le;
7564     }
7565     lv = lx;
7566   }
7567 #pragma omp atomic compare capture seq_cst
7568   {
7569     if (lx < le) {
7570       lx = le;
7571     }
7572     lv = lx;
7573   }
7574 #pragma omp atomic compare capture seq_cst
7575   {
7576     if (lx == le) {
7577       lx = ld;
7578     }
7579     lv = lx;
7580   }
7581 #pragma omp atomic compare capture seq_cst
7582   {
7583     if (le == lx) {
7584       lx = ld;
7585     }
7586     lv = lx;
7587   }
7588 #pragma omp atomic compare capture seq_cst
7589   if (lx == le) {
7590     lx = ld;
7591   } else {
7592     lv = lx;
7593   }
7594 #pragma omp atomic compare capture seq_cst
7595   if (le == lx) {
7596     lx = ld;
7597   } else {
7598     lv = lx;
7599   }
7600 #pragma omp atomic compare capture seq_cst
7601   {
7602     lr = lx == le;
7603     if (lr) {
7604       lx = ld;
7605     }
7606   }
7607 #pragma omp atomic compare capture seq_cst
7608   {
7609     lr = le == lx;
7610     if (lr) {
7611       lx = ld;
7612     }
7613   }
7614 #pragma omp atomic compare capture seq_cst
7615   {
7616     lr = lx == le;
7617     if (lr) {
7618       lx = ld;
7619     } else {
7620       lv = lx;
7621     }
7622   }
7623 #pragma omp atomic compare capture seq_cst
7624   {
7625     lr = le == lx;
7626     if (lr) {
7627       lx = ld;
7628     } else {
7629       lv = lx;
7630     }
7631   }
7632 
7633 #pragma omp atomic compare capture
7634   {
7635     ulv = ulx;
7636     if (ule > ulx) {
7637       ulx = ule;
7638     }
7639   }
7640 #pragma omp atomic compare capture
7641   {
7642     ulv = ulx;
7643     if (ulx > ule) {
7644       ulx = ule;
7645     }
7646   }
7647 #pragma omp atomic compare capture
7648   {
7649     ulv = ulx;
7650     if (ule < ulx) {
7651       ulx = ule;
7652     }
7653   }
7654 #pragma omp atomic compare capture
7655   {
7656     ulv = ulx;
7657     if (ulx < ule) {
7658       ulx = ule;
7659     }
7660   }
7661 #pragma omp atomic compare capture
7662   {
7663     ulv = ulx;
7664     if (ulx == ule) {
7665       ulx = uld;
7666     }
7667   }
7668 #pragma omp atomic compare capture
7669   {
7670     ulv = ulx;
7671     if (ule == ulx) {
7672       ulx = uld;
7673     }
7674   }
7675 #pragma omp atomic compare capture
7676   {
7677     if (ule > ulx) {
7678       ulx = ule;
7679     }
7680     ulv = ulx;
7681   }
7682 #pragma omp atomic compare capture
7683   {
7684     if (ulx > ule) {
7685       ulx = ule;
7686     }
7687     ulv = ulx;
7688   }
7689 #pragma omp atomic compare capture
7690   {
7691     if (ule < ulx) {
7692       ulx = ule;
7693     }
7694     ulv = ulx;
7695   }
7696 #pragma omp atomic compare capture
7697   {
7698     if (ulx < ule) {
7699       ulx = ule;
7700     }
7701     ulv = ulx;
7702   }
7703 #pragma omp atomic compare capture
7704   {
7705     if (ulx == ule) {
7706       ulx = uld;
7707     }
7708     ulv = ulx;
7709   }
7710 #pragma omp atomic compare capture
7711   {
7712     if (ule == ulx) {
7713       ulx = uld;
7714     }
7715     ulv = ulx;
7716   }
7717 #pragma omp atomic compare capture
7718   if (ulx == ule) {
7719     ulx = uld;
7720   } else {
7721     ulv = ulx;
7722   }
7723 #pragma omp atomic compare capture
7724   if (ule == ulx) {
7725     ulx = uld;
7726   } else {
7727     ulv = ulx;
7728   }
7729 #pragma omp atomic compare capture
7730   {
7731     ulr = ulx == ule;
7732     if (ulr) {
7733       ulx = uld;
7734     }
7735   }
7736 #pragma omp atomic compare capture
7737   {
7738     ulr = ule == ulx;
7739     if (ulr) {
7740       ulx = uld;
7741     }
7742   }
7743 #pragma omp atomic compare capture
7744   {
7745     ulr = ulx == ule;
7746     if (ulr) {
7747       ulx = uld;
7748     } else {
7749       ulv = ulx;
7750     }
7751   }
7752 #pragma omp atomic compare capture
7753   {
7754     ulr = ule == ulx;
7755     if (ulr) {
7756       ulx = uld;
7757     } else {
7758       ulv = ulx;
7759     }
7760   }
7761 
7762 #pragma omp atomic compare capture acq_rel
7763   {
7764     ulv = ulx;
7765     if (ule > ulx) {
7766       ulx = ule;
7767     }
7768   }
7769 #pragma omp atomic compare capture acq_rel
7770   {
7771     ulv = ulx;
7772     if (ulx > ule) {
7773       ulx = ule;
7774     }
7775   }
7776 #pragma omp atomic compare capture acq_rel
7777   {
7778     ulv = ulx;
7779     if (ule < ulx) {
7780       ulx = ule;
7781     }
7782   }
7783 #pragma omp atomic compare capture acq_rel
7784   {
7785     ulv = ulx;
7786     if (ulx < ule) {
7787       ulx = ule;
7788     }
7789   }
7790 #pragma omp atomic compare capture acq_rel
7791   {
7792     ulv = ulx;
7793     if (ulx == ule) {
7794       ulx = uld;
7795     }
7796   }
7797 #pragma omp atomic compare capture acq_rel
7798   {
7799     ulv = ulx;
7800     if (ule == ulx) {
7801       ulx = uld;
7802     }
7803   }
7804 #pragma omp atomic compare capture acq_rel
7805   {
7806     if (ule > ulx) {
7807       ulx = ule;
7808     }
7809     ulv = ulx;
7810   }
7811 #pragma omp atomic compare capture acq_rel
7812   {
7813     if (ulx > ule) {
7814       ulx = ule;
7815     }
7816     ulv = ulx;
7817   }
7818 #pragma omp atomic compare capture acq_rel
7819   {
7820     if (ule < ulx) {
7821       ulx = ule;
7822     }
7823     ulv = ulx;
7824   }
7825 #pragma omp atomic compare capture acq_rel
7826   {
7827     if (ulx < ule) {
7828       ulx = ule;
7829     }
7830     ulv = ulx;
7831   }
7832 #pragma omp atomic compare capture acq_rel
7833   {
7834     if (ulx == ule) {
7835       ulx = uld;
7836     }
7837     ulv = ulx;
7838   }
7839 #pragma omp atomic compare capture acq_rel
7840   {
7841     if (ule == ulx) {
7842       ulx = uld;
7843     }
7844     ulv = ulx;
7845   }
7846 #pragma omp atomic compare capture acq_rel
7847   if (ulx == ule) {
7848     ulx = uld;
7849   } else {
7850     ulv = ulx;
7851   }
7852 #pragma omp atomic compare capture acq_rel
7853   if (ule == ulx) {
7854     ulx = uld;
7855   } else {
7856     ulv = ulx;
7857   }
7858 #pragma omp atomic compare capture acq_rel
7859   {
7860     ulr = ulx == ule;
7861     if (ulr) {
7862       ulx = uld;
7863     }
7864   }
7865 #pragma omp atomic compare capture acq_rel
7866   {
7867     ulr = ule == ulx;
7868     if (ulr) {
7869       ulx = uld;
7870     }
7871   }
7872 #pragma omp atomic compare capture acq_rel
7873   {
7874     ulr = ulx == ule;
7875     if (ulr) {
7876       ulx = uld;
7877     } else {
7878       ulv = ulx;
7879     }
7880   }
7881 #pragma omp atomic compare capture acq_rel
7882   {
7883     ulr = ule == ulx;
7884     if (ulr) {
7885       ulx = uld;
7886     } else {
7887       ulv = ulx;
7888     }
7889   }
7890 
7891 #pragma omp atomic compare capture acquire
7892   {
7893     ulv = ulx;
7894     if (ule > ulx) {
7895       ulx = ule;
7896     }
7897   }
7898 #pragma omp atomic compare capture acquire
7899   {
7900     ulv = ulx;
7901     if (ulx > ule) {
7902       ulx = ule;
7903     }
7904   }
7905 #pragma omp atomic compare capture acquire
7906   {
7907     ulv = ulx;
7908     if (ule < ulx) {
7909       ulx = ule;
7910     }
7911   }
7912 #pragma omp atomic compare capture acquire
7913   {
7914     ulv = ulx;
7915     if (ulx < ule) {
7916       ulx = ule;
7917     }
7918   }
7919 #pragma omp atomic compare capture acquire
7920   {
7921     ulv = ulx;
7922     if (ulx == ule) {
7923       ulx = uld;
7924     }
7925   }
7926 #pragma omp atomic compare capture acquire
7927   {
7928     ulv = ulx;
7929     if (ule == ulx) {
7930       ulx = uld;
7931     }
7932   }
7933 #pragma omp atomic compare capture acquire
7934   {
7935     if (ule > ulx) {
7936       ulx = ule;
7937     }
7938     ulv = ulx;
7939   }
7940 #pragma omp atomic compare capture acquire
7941   {
7942     if (ulx > ule) {
7943       ulx = ule;
7944     }
7945     ulv = ulx;
7946   }
7947 #pragma omp atomic compare capture acquire
7948   {
7949     if (ule < ulx) {
7950       ulx = ule;
7951     }
7952     ulv = ulx;
7953   }
7954 #pragma omp atomic compare capture acquire
7955   {
7956     if (ulx < ule) {
7957       ulx = ule;
7958     }
7959     ulv = ulx;
7960   }
7961 #pragma omp atomic compare capture acquire
7962   {
7963     if (ulx == ule) {
7964       ulx = uld;
7965     }
7966     ulv = ulx;
7967   }
7968 #pragma omp atomic compare capture acquire
7969   {
7970     if (ule == ulx) {
7971       ulx = uld;
7972     }
7973     ulv = ulx;
7974   }
7975 #pragma omp atomic compare capture acquire
7976   if (ulx == ule) {
7977     ulx = uld;
7978   } else {
7979     ulv = ulx;
7980   }
7981 #pragma omp atomic compare capture acquire
7982   if (ule == ulx) {
7983     ulx = uld;
7984   } else {
7985     ulv = ulx;
7986   }
7987 #pragma omp atomic compare capture acquire
7988   {
7989     ulr = ulx == ule;
7990     if (ulr) {
7991       ulx = uld;
7992     }
7993   }
7994 #pragma omp atomic compare capture acquire
7995   {
7996     ulr = ule == ulx;
7997     if (ulr) {
7998       ulx = uld;
7999     }
8000   }
8001 #pragma omp atomic compare capture acquire
8002   {
8003     ulr = ulx == ule;
8004     if (ulr) {
8005       ulx = uld;
8006     } else {
8007       ulv = ulx;
8008     }
8009   }
8010 #pragma omp atomic compare capture acquire
8011   {
8012     ulr = ule == ulx;
8013     if (ulr) {
8014       ulx = uld;
8015     } else {
8016       ulv = ulx;
8017     }
8018   }
8019 
8020 #pragma omp atomic compare capture relaxed
8021   {
8022     ulv = ulx;
8023     if (ule > ulx) {
8024       ulx = ule;
8025     }
8026   }
8027 #pragma omp atomic compare capture relaxed
8028   {
8029     ulv = ulx;
8030     if (ulx > ule) {
8031       ulx = ule;
8032     }
8033   }
8034 #pragma omp atomic compare capture relaxed
8035   {
8036     ulv = ulx;
8037     if (ule < ulx) {
8038       ulx = ule;
8039     }
8040   }
8041 #pragma omp atomic compare capture relaxed
8042   {
8043     ulv = ulx;
8044     if (ulx < ule) {
8045       ulx = ule;
8046     }
8047   }
8048 #pragma omp atomic compare capture relaxed
8049   {
8050     ulv = ulx;
8051     if (ulx == ule) {
8052       ulx = uld;
8053     }
8054   }
8055 #pragma omp atomic compare capture relaxed
8056   {
8057     ulv = ulx;
8058     if (ule == ulx) {
8059       ulx = uld;
8060     }
8061   }
8062 #pragma omp atomic compare capture relaxed
8063   {
8064     if (ule > ulx) {
8065       ulx = ule;
8066     }
8067     ulv = ulx;
8068   }
8069 #pragma omp atomic compare capture relaxed
8070   {
8071     if (ulx > ule) {
8072       ulx = ule;
8073     }
8074     ulv = ulx;
8075   }
8076 #pragma omp atomic compare capture relaxed
8077   {
8078     if (ule < ulx) {
8079       ulx = ule;
8080     }
8081     ulv = ulx;
8082   }
8083 #pragma omp atomic compare capture relaxed
8084   {
8085     if (ulx < ule) {
8086       ulx = ule;
8087     }
8088     ulv = ulx;
8089   }
8090 #pragma omp atomic compare capture relaxed
8091   {
8092     if (ulx == ule) {
8093       ulx = uld;
8094     }
8095     ulv = ulx;
8096   }
8097 #pragma omp atomic compare capture relaxed
8098   {
8099     if (ule == ulx) {
8100       ulx = uld;
8101     }
8102     ulv = ulx;
8103   }
8104 #pragma omp atomic compare capture relaxed
8105   if (ulx == ule) {
8106     ulx = uld;
8107   } else {
8108     ulv = ulx;
8109   }
8110 #pragma omp atomic compare capture relaxed
8111   if (ule == ulx) {
8112     ulx = uld;
8113   } else {
8114     ulv = ulx;
8115   }
8116 #pragma omp atomic compare capture relaxed
8117   {
8118     ulr = ulx == ule;
8119     if (ulr) {
8120       ulx = uld;
8121     }
8122   }
8123 #pragma omp atomic compare capture relaxed
8124   {
8125     ulr = ule == ulx;
8126     if (ulr) {
8127       ulx = uld;
8128     }
8129   }
8130 #pragma omp atomic compare capture relaxed
8131   {
8132     ulr = ulx == ule;
8133     if (ulr) {
8134       ulx = uld;
8135     } else {
8136       ulv = ulx;
8137     }
8138   }
8139 #pragma omp atomic compare capture relaxed
8140   {
8141     ulr = ule == ulx;
8142     if (ulr) {
8143       ulx = uld;
8144     } else {
8145       ulv = ulx;
8146     }
8147   }
8148 
8149 #pragma omp atomic compare capture release
8150   {
8151     ulv = ulx;
8152     if (ule > ulx) {
8153       ulx = ule;
8154     }
8155   }
8156 #pragma omp atomic compare capture release
8157   {
8158     ulv = ulx;
8159     if (ulx > ule) {
8160       ulx = ule;
8161     }
8162   }
8163 #pragma omp atomic compare capture release
8164   {
8165     ulv = ulx;
8166     if (ule < ulx) {
8167       ulx = ule;
8168     }
8169   }
8170 #pragma omp atomic compare capture release
8171   {
8172     ulv = ulx;
8173     if (ulx < ule) {
8174       ulx = ule;
8175     }
8176   }
8177 #pragma omp atomic compare capture release
8178   {
8179     ulv = ulx;
8180     if (ulx == ule) {
8181       ulx = uld;
8182     }
8183   }
8184 #pragma omp atomic compare capture release
8185   {
8186     ulv = ulx;
8187     if (ule == ulx) {
8188       ulx = uld;
8189     }
8190   }
8191 #pragma omp atomic compare capture release
8192   {
8193     if (ule > ulx) {
8194       ulx = ule;
8195     }
8196     ulv = ulx;
8197   }
8198 #pragma omp atomic compare capture release
8199   {
8200     if (ulx > ule) {
8201       ulx = ule;
8202     }
8203     ulv = ulx;
8204   }
8205 #pragma omp atomic compare capture release
8206   {
8207     if (ule < ulx) {
8208       ulx = ule;
8209     }
8210     ulv = ulx;
8211   }
8212 #pragma omp atomic compare capture release
8213   {
8214     if (ulx < ule) {
8215       ulx = ule;
8216     }
8217     ulv = ulx;
8218   }
8219 #pragma omp atomic compare capture release
8220   {
8221     if (ulx == ule) {
8222       ulx = uld;
8223     }
8224     ulv = ulx;
8225   }
8226 #pragma omp atomic compare capture release
8227   {
8228     if (ule == ulx) {
8229       ulx = uld;
8230     }
8231     ulv = ulx;
8232   }
8233 #pragma omp atomic compare capture release
8234   if (ulx == ule) {
8235     ulx = uld;
8236   } else {
8237     ulv = ulx;
8238   }
8239 #pragma omp atomic compare capture release
8240   if (ule == ulx) {
8241     ulx = uld;
8242   } else {
8243     ulv = ulx;
8244   }
8245 #pragma omp atomic compare capture release
8246   {
8247     ulr = ulx == ule;
8248     if (ulr) {
8249       ulx = uld;
8250     }
8251   }
8252 #pragma omp atomic compare capture release
8253   {
8254     ulr = ule == ulx;
8255     if (ulr) {
8256       ulx = uld;
8257     }
8258   }
8259 #pragma omp atomic compare capture release
8260   {
8261     ulr = ulx == ule;
8262     if (ulr) {
8263       ulx = uld;
8264     } else {
8265       ulv = ulx;
8266     }
8267   }
8268 #pragma omp atomic compare capture release
8269   {
8270     ulr = ule == ulx;
8271     if (ulr) {
8272       ulx = uld;
8273     } else {
8274       ulv = ulx;
8275     }
8276   }
8277 
8278 #pragma omp atomic compare capture seq_cst
8279   {
8280     ulv = ulx;
8281     if (ule > ulx) {
8282       ulx = ule;
8283     }
8284   }
8285 #pragma omp atomic compare capture seq_cst
8286   {
8287     ulv = ulx;
8288     if (ulx > ule) {
8289       ulx = ule;
8290     }
8291   }
8292 #pragma omp atomic compare capture seq_cst
8293   {
8294     ulv = ulx;
8295     if (ule < ulx) {
8296       ulx = ule;
8297     }
8298   }
8299 #pragma omp atomic compare capture seq_cst
8300   {
8301     ulv = ulx;
8302     if (ulx < ule) {
8303       ulx = ule;
8304     }
8305   }
8306 #pragma omp atomic compare capture seq_cst
8307   {
8308     ulv = ulx;
8309     if (ulx == ule) {
8310       ulx = uld;
8311     }
8312   }
8313 #pragma omp atomic compare capture seq_cst
8314   {
8315     ulv = ulx;
8316     if (ule == ulx) {
8317       ulx = uld;
8318     }
8319   }
8320 #pragma omp atomic compare capture seq_cst
8321   {
8322     if (ule > ulx) {
8323       ulx = ule;
8324     }
8325     ulv = ulx;
8326   }
8327 #pragma omp atomic compare capture seq_cst
8328   {
8329     if (ulx > ule) {
8330       ulx = ule;
8331     }
8332     ulv = ulx;
8333   }
8334 #pragma omp atomic compare capture seq_cst
8335   {
8336     if (ule < ulx) {
8337       ulx = ule;
8338     }
8339     ulv = ulx;
8340   }
8341 #pragma omp atomic compare capture seq_cst
8342   {
8343     if (ulx < ule) {
8344       ulx = ule;
8345     }
8346     ulv = ulx;
8347   }
8348 #pragma omp atomic compare capture seq_cst
8349   {
8350     if (ulx == ule) {
8351       ulx = uld;
8352     }
8353     ulv = ulx;
8354   }
8355 #pragma omp atomic compare capture seq_cst
8356   {
8357     if (ule == ulx) {
8358       ulx = uld;
8359     }
8360     ulv = ulx;
8361   }
8362 #pragma omp atomic compare capture seq_cst
8363   if (ulx == ule) {
8364     ulx = uld;
8365   } else {
8366     ulv = ulx;
8367   }
8368 #pragma omp atomic compare capture seq_cst
8369   if (ule == ulx) {
8370     ulx = uld;
8371   } else {
8372     ulv = ulx;
8373   }
8374 #pragma omp atomic compare capture seq_cst
8375   {
8376     ulr = ulx == ule;
8377     if (ulr) {
8378       ulx = uld;
8379     }
8380   }
8381 #pragma omp atomic compare capture seq_cst
8382   {
8383     ulr = ule == ulx;
8384     if (ulr) {
8385       ulx = uld;
8386     }
8387   }
8388 #pragma omp atomic compare capture seq_cst
8389   {
8390     ulr = ulx == ule;
8391     if (ulr) {
8392       ulx = uld;
8393     } else {
8394       ulv = ulx;
8395     }
8396   }
8397 #pragma omp atomic compare capture seq_cst
8398   {
8399     ulr = ule == ulx;
8400     if (ulr) {
8401       ulx = uld;
8402     } else {
8403       ulv = ulx;
8404     }
8405   }
8406 
8407 #pragma omp atomic compare capture
8408   {
8409     llv = llx;
8410     if (lle > llx) {
8411       llx = lle;
8412     }
8413   }
8414 #pragma omp atomic compare capture
8415   {
8416     llv = llx;
8417     if (llx > lle) {
8418       llx = lle;
8419     }
8420   }
8421 #pragma omp atomic compare capture
8422   {
8423     llv = llx;
8424     if (lle < llx) {
8425       llx = lle;
8426     }
8427   }
8428 #pragma omp atomic compare capture
8429   {
8430     llv = llx;
8431     if (llx < lle) {
8432       llx = lle;
8433     }
8434   }
8435 #pragma omp atomic compare capture
8436   {
8437     llv = llx;
8438     if (llx == lle) {
8439       llx = lld;
8440     }
8441   }
8442 #pragma omp atomic compare capture
8443   {
8444     llv = llx;
8445     if (lle == llx) {
8446       llx = lld;
8447     }
8448   }
8449 #pragma omp atomic compare capture
8450   {
8451     if (lle > llx) {
8452       llx = lle;
8453     }
8454     llv = llx;
8455   }
8456 #pragma omp atomic compare capture
8457   {
8458     if (llx > lle) {
8459       llx = lle;
8460     }
8461     llv = llx;
8462   }
8463 #pragma omp atomic compare capture
8464   {
8465     if (lle < llx) {
8466       llx = lle;
8467     }
8468     llv = llx;
8469   }
8470 #pragma omp atomic compare capture
8471   {
8472     if (llx < lle) {
8473       llx = lle;
8474     }
8475     llv = llx;
8476   }
8477 #pragma omp atomic compare capture
8478   {
8479     if (llx == lle) {
8480       llx = lld;
8481     }
8482     llv = llx;
8483   }
8484 #pragma omp atomic compare capture
8485   {
8486     if (lle == llx) {
8487       llx = lld;
8488     }
8489     llv = llx;
8490   }
8491 #pragma omp atomic compare capture
8492   if (llx == lle) {
8493     llx = lld;
8494   } else {
8495     llv = llx;
8496   }
8497 #pragma omp atomic compare capture
8498   if (lle == llx) {
8499     llx = lld;
8500   } else {
8501     llv = llx;
8502   }
8503 #pragma omp atomic compare capture
8504   {
8505     llr = llx == lle;
8506     if (llr) {
8507       llx = lld;
8508     }
8509   }
8510 #pragma omp atomic compare capture
8511   {
8512     llr = lle == llx;
8513     if (llr) {
8514       llx = lld;
8515     }
8516   }
8517 #pragma omp atomic compare capture
8518   {
8519     llr = llx == lle;
8520     if (llr) {
8521       llx = lld;
8522     } else {
8523       llv = llx;
8524     }
8525   }
8526 #pragma omp atomic compare capture
8527   {
8528     llr = lle == llx;
8529     if (llr) {
8530       llx = lld;
8531     } else {
8532       llv = llx;
8533     }
8534   }
8535 
8536 #pragma omp atomic compare capture acq_rel
8537   {
8538     llv = llx;
8539     if (lle > llx) {
8540       llx = lle;
8541     }
8542   }
8543 #pragma omp atomic compare capture acq_rel
8544   {
8545     llv = llx;
8546     if (llx > lle) {
8547       llx = lle;
8548     }
8549   }
8550 #pragma omp atomic compare capture acq_rel
8551   {
8552     llv = llx;
8553     if (lle < llx) {
8554       llx = lle;
8555     }
8556   }
8557 #pragma omp atomic compare capture acq_rel
8558   {
8559     llv = llx;
8560     if (llx < lle) {
8561       llx = lle;
8562     }
8563   }
8564 #pragma omp atomic compare capture acq_rel
8565   {
8566     llv = llx;
8567     if (llx == lle) {
8568       llx = lld;
8569     }
8570   }
8571 #pragma omp atomic compare capture acq_rel
8572   {
8573     llv = llx;
8574     if (lle == llx) {
8575       llx = lld;
8576     }
8577   }
8578 #pragma omp atomic compare capture acq_rel
8579   {
8580     if (lle > llx) {
8581       llx = lle;
8582     }
8583     llv = llx;
8584   }
8585 #pragma omp atomic compare capture acq_rel
8586   {
8587     if (llx > lle) {
8588       llx = lle;
8589     }
8590     llv = llx;
8591   }
8592 #pragma omp atomic compare capture acq_rel
8593   {
8594     if (lle < llx) {
8595       llx = lle;
8596     }
8597     llv = llx;
8598   }
8599 #pragma omp atomic compare capture acq_rel
8600   {
8601     if (llx < lle) {
8602       llx = lle;
8603     }
8604     llv = llx;
8605   }
8606 #pragma omp atomic compare capture acq_rel
8607   {
8608     if (llx == lle) {
8609       llx = lld;
8610     }
8611     llv = llx;
8612   }
8613 #pragma omp atomic compare capture acq_rel
8614   {
8615     if (lle == llx) {
8616       llx = lld;
8617     }
8618     llv = llx;
8619   }
8620 #pragma omp atomic compare capture acq_rel
8621   if (llx == lle) {
8622     llx = lld;
8623   } else {
8624     llv = llx;
8625   }
8626 #pragma omp atomic compare capture acq_rel
8627   if (lle == llx) {
8628     llx = lld;
8629   } else {
8630     llv = llx;
8631   }
8632 #pragma omp atomic compare capture acq_rel
8633   {
8634     llr = llx == lle;
8635     if (llr) {
8636       llx = lld;
8637     }
8638   }
8639 #pragma omp atomic compare capture acq_rel
8640   {
8641     llr = lle == llx;
8642     if (llr) {
8643       llx = lld;
8644     }
8645   }
8646 #pragma omp atomic compare capture acq_rel
8647   {
8648     llr = llx == lle;
8649     if (llr) {
8650       llx = lld;
8651     } else {
8652       llv = llx;
8653     }
8654   }
8655 #pragma omp atomic compare capture acq_rel
8656   {
8657     llr = lle == llx;
8658     if (llr) {
8659       llx = lld;
8660     } else {
8661       llv = llx;
8662     }
8663   }
8664 
8665 #pragma omp atomic compare capture acquire
8666   {
8667     llv = llx;
8668     if (lle > llx) {
8669       llx = lle;
8670     }
8671   }
8672 #pragma omp atomic compare capture acquire
8673   {
8674     llv = llx;
8675     if (llx > lle) {
8676       llx = lle;
8677     }
8678   }
8679 #pragma omp atomic compare capture acquire
8680   {
8681     llv = llx;
8682     if (lle < llx) {
8683       llx = lle;
8684     }
8685   }
8686 #pragma omp atomic compare capture acquire
8687   {
8688     llv = llx;
8689     if (llx < lle) {
8690       llx = lle;
8691     }
8692   }
8693 #pragma omp atomic compare capture acquire
8694   {
8695     llv = llx;
8696     if (llx == lle) {
8697       llx = lld;
8698     }
8699   }
8700 #pragma omp atomic compare capture acquire
8701   {
8702     llv = llx;
8703     if (lle == llx) {
8704       llx = lld;
8705     }
8706   }
8707 #pragma omp atomic compare capture acquire
8708   {
8709     if (lle > llx) {
8710       llx = lle;
8711     }
8712     llv = llx;
8713   }
8714 #pragma omp atomic compare capture acquire
8715   {
8716     if (llx > lle) {
8717       llx = lle;
8718     }
8719     llv = llx;
8720   }
8721 #pragma omp atomic compare capture acquire
8722   {
8723     if (lle < llx) {
8724       llx = lle;
8725     }
8726     llv = llx;
8727   }
8728 #pragma omp atomic compare capture acquire
8729   {
8730     if (llx < lle) {
8731       llx = lle;
8732     }
8733     llv = llx;
8734   }
8735 #pragma omp atomic compare capture acquire
8736   {
8737     if (llx == lle) {
8738       llx = lld;
8739     }
8740     llv = llx;
8741   }
8742 #pragma omp atomic compare capture acquire
8743   {
8744     if (lle == llx) {
8745       llx = lld;
8746     }
8747     llv = llx;
8748   }
8749 #pragma omp atomic compare capture acquire
8750   if (llx == lle) {
8751     llx = lld;
8752   } else {
8753     llv = llx;
8754   }
8755 #pragma omp atomic compare capture acquire
8756   if (lle == llx) {
8757     llx = lld;
8758   } else {
8759     llv = llx;
8760   }
8761 #pragma omp atomic compare capture acquire
8762   {
8763     llr = llx == lle;
8764     if (llr) {
8765       llx = lld;
8766     }
8767   }
8768 #pragma omp atomic compare capture acquire
8769   {
8770     llr = lle == llx;
8771     if (llr) {
8772       llx = lld;
8773     }
8774   }
8775 #pragma omp atomic compare capture acquire
8776   {
8777     llr = llx == lle;
8778     if (llr) {
8779       llx = lld;
8780     } else {
8781       llv = llx;
8782     }
8783   }
8784 #pragma omp atomic compare capture acquire
8785   {
8786     llr = lle == llx;
8787     if (llr) {
8788       llx = lld;
8789     } else {
8790       llv = llx;
8791     }
8792   }
8793 
8794 #pragma omp atomic compare capture relaxed
8795   {
8796     llv = llx;
8797     if (lle > llx) {
8798       llx = lle;
8799     }
8800   }
8801 #pragma omp atomic compare capture relaxed
8802   {
8803     llv = llx;
8804     if (llx > lle) {
8805       llx = lle;
8806     }
8807   }
8808 #pragma omp atomic compare capture relaxed
8809   {
8810     llv = llx;
8811     if (lle < llx) {
8812       llx = lle;
8813     }
8814   }
8815 #pragma omp atomic compare capture relaxed
8816   {
8817     llv = llx;
8818     if (llx < lle) {
8819       llx = lle;
8820     }
8821   }
8822 #pragma omp atomic compare capture relaxed
8823   {
8824     llv = llx;
8825     if (llx == lle) {
8826       llx = lld;
8827     }
8828   }
8829 #pragma omp atomic compare capture relaxed
8830   {
8831     llv = llx;
8832     if (lle == llx) {
8833       llx = lld;
8834     }
8835   }
8836 #pragma omp atomic compare capture relaxed
8837   {
8838     if (lle > llx) {
8839       llx = lle;
8840     }
8841     llv = llx;
8842   }
8843 #pragma omp atomic compare capture relaxed
8844   {
8845     if (llx > lle) {
8846       llx = lle;
8847     }
8848     llv = llx;
8849   }
8850 #pragma omp atomic compare capture relaxed
8851   {
8852     if (lle < llx) {
8853       llx = lle;
8854     }
8855     llv = llx;
8856   }
8857 #pragma omp atomic compare capture relaxed
8858   {
8859     if (llx < lle) {
8860       llx = lle;
8861     }
8862     llv = llx;
8863   }
8864 #pragma omp atomic compare capture relaxed
8865   {
8866     if (llx == lle) {
8867       llx = lld;
8868     }
8869     llv = llx;
8870   }
8871 #pragma omp atomic compare capture relaxed
8872   {
8873     if (lle == llx) {
8874       llx = lld;
8875     }
8876     llv = llx;
8877   }
8878 #pragma omp atomic compare capture relaxed
8879   if (llx == lle) {
8880     llx = lld;
8881   } else {
8882     llv = llx;
8883   }
8884 #pragma omp atomic compare capture relaxed
8885   if (lle == llx) {
8886     llx = lld;
8887   } else {
8888     llv = llx;
8889   }
8890 #pragma omp atomic compare capture relaxed
8891   {
8892     llr = llx == lle;
8893     if (llr) {
8894       llx = lld;
8895     }
8896   }
8897 #pragma omp atomic compare capture relaxed
8898   {
8899     llr = lle == llx;
8900     if (llr) {
8901       llx = lld;
8902     }
8903   }
8904 #pragma omp atomic compare capture relaxed
8905   {
8906     llr = llx == lle;
8907     if (llr) {
8908       llx = lld;
8909     } else {
8910       llv = llx;
8911     }
8912   }
8913 #pragma omp atomic compare capture relaxed
8914   {
8915     llr = lle == llx;
8916     if (llr) {
8917       llx = lld;
8918     } else {
8919       llv = llx;
8920     }
8921   }
8922 
8923 #pragma omp atomic compare capture release
8924   {
8925     llv = llx;
8926     if (lle > llx) {
8927       llx = lle;
8928     }
8929   }
8930 #pragma omp atomic compare capture release
8931   {
8932     llv = llx;
8933     if (llx > lle) {
8934       llx = lle;
8935     }
8936   }
8937 #pragma omp atomic compare capture release
8938   {
8939     llv = llx;
8940     if (lle < llx) {
8941       llx = lle;
8942     }
8943   }
8944 #pragma omp atomic compare capture release
8945   {
8946     llv = llx;
8947     if (llx < lle) {
8948       llx = lle;
8949     }
8950   }
8951 #pragma omp atomic compare capture release
8952   {
8953     llv = llx;
8954     if (llx == lle) {
8955       llx = lld;
8956     }
8957   }
8958 #pragma omp atomic compare capture release
8959   {
8960     llv = llx;
8961     if (lle == llx) {
8962       llx = lld;
8963     }
8964   }
8965 #pragma omp atomic compare capture release
8966   {
8967     if (lle > llx) {
8968       llx = lle;
8969     }
8970     llv = llx;
8971   }
8972 #pragma omp atomic compare capture release
8973   {
8974     if (llx > lle) {
8975       llx = lle;
8976     }
8977     llv = llx;
8978   }
8979 #pragma omp atomic compare capture release
8980   {
8981     if (lle < llx) {
8982       llx = lle;
8983     }
8984     llv = llx;
8985   }
8986 #pragma omp atomic compare capture release
8987   {
8988     if (llx < lle) {
8989       llx = lle;
8990     }
8991     llv = llx;
8992   }
8993 #pragma omp atomic compare capture release
8994   {
8995     if (llx == lle) {
8996       llx = lld;
8997     }
8998     llv = llx;
8999   }
9000 #pragma omp atomic compare capture release
9001   {
9002     if (lle == llx) {
9003       llx = lld;
9004     }
9005     llv = llx;
9006   }
9007 #pragma omp atomic compare capture release
9008   if (llx == lle) {
9009     llx = lld;
9010   } else {
9011     llv = llx;
9012   }
9013 #pragma omp atomic compare capture release
9014   if (lle == llx) {
9015     llx = lld;
9016   } else {
9017     llv = llx;
9018   }
9019 #pragma omp atomic compare capture release
9020   {
9021     llr = llx == lle;
9022     if (llr) {
9023       llx = lld;
9024     }
9025   }
9026 #pragma omp atomic compare capture release
9027   {
9028     llr = lle == llx;
9029     if (llr) {
9030       llx = lld;
9031     }
9032   }
9033 #pragma omp atomic compare capture release
9034   {
9035     llr = llx == lle;
9036     if (llr) {
9037       llx = lld;
9038     } else {
9039       llv = llx;
9040     }
9041   }
9042 #pragma omp atomic compare capture release
9043   {
9044     llr = lle == llx;
9045     if (llr) {
9046       llx = lld;
9047     } else {
9048       llv = llx;
9049     }
9050   }
9051 
9052 #pragma omp atomic compare capture seq_cst
9053   {
9054     llv = llx;
9055     if (lle > llx) {
9056       llx = lle;
9057     }
9058   }
9059 #pragma omp atomic compare capture seq_cst
9060   {
9061     llv = llx;
9062     if (llx > lle) {
9063       llx = lle;
9064     }
9065   }
9066 #pragma omp atomic compare capture seq_cst
9067   {
9068     llv = llx;
9069     if (lle < llx) {
9070       llx = lle;
9071     }
9072   }
9073 #pragma omp atomic compare capture seq_cst
9074   {
9075     llv = llx;
9076     if (llx < lle) {
9077       llx = lle;
9078     }
9079   }
9080 #pragma omp atomic compare capture seq_cst
9081   {
9082     llv = llx;
9083     if (llx == lle) {
9084       llx = lld;
9085     }
9086   }
9087 #pragma omp atomic compare capture seq_cst
9088   {
9089     llv = llx;
9090     if (lle == llx) {
9091       llx = lld;
9092     }
9093   }
9094 #pragma omp atomic compare capture seq_cst
9095   {
9096     if (lle > llx) {
9097       llx = lle;
9098     }
9099     llv = llx;
9100   }
9101 #pragma omp atomic compare capture seq_cst
9102   {
9103     if (llx > lle) {
9104       llx = lle;
9105     }
9106     llv = llx;
9107   }
9108 #pragma omp atomic compare capture seq_cst
9109   {
9110     if (lle < llx) {
9111       llx = lle;
9112     }
9113     llv = llx;
9114   }
9115 #pragma omp atomic compare capture seq_cst
9116   {
9117     if (llx < lle) {
9118       llx = lle;
9119     }
9120     llv = llx;
9121   }
9122 #pragma omp atomic compare capture seq_cst
9123   {
9124     if (llx == lle) {
9125       llx = lld;
9126     }
9127     llv = llx;
9128   }
9129 #pragma omp atomic compare capture seq_cst
9130   {
9131     if (lle == llx) {
9132       llx = lld;
9133     }
9134     llv = llx;
9135   }
9136 #pragma omp atomic compare capture seq_cst
9137   if (llx == lle) {
9138     llx = lld;
9139   } else {
9140     llv = llx;
9141   }
9142 #pragma omp atomic compare capture seq_cst
9143   if (lle == llx) {
9144     llx = lld;
9145   } else {
9146     llv = llx;
9147   }
9148 #pragma omp atomic compare capture seq_cst
9149   {
9150     llr = llx == lle;
9151     if (llr) {
9152       llx = lld;
9153     }
9154   }
9155 #pragma omp atomic compare capture seq_cst
9156   {
9157     llr = lle == llx;
9158     if (llr) {
9159       llx = lld;
9160     }
9161   }
9162 #pragma omp atomic compare capture seq_cst
9163   {
9164     llr = llx == lle;
9165     if (llr) {
9166       llx = lld;
9167     } else {
9168       llv = llx;
9169     }
9170   }
9171 #pragma omp atomic compare capture seq_cst
9172   {
9173     llr = lle == llx;
9174     if (llr) {
9175       llx = lld;
9176     } else {
9177       llv = llx;
9178     }
9179   }
9180 
9181 #pragma omp atomic compare capture
9182   {
9183     ullv = ullx;
9184     if (ulle > ullx) {
9185       ullx = ulle;
9186     }
9187   }
9188 #pragma omp atomic compare capture
9189   {
9190     ullv = ullx;
9191     if (ullx > ulle) {
9192       ullx = ulle;
9193     }
9194   }
9195 #pragma omp atomic compare capture
9196   {
9197     ullv = ullx;
9198     if (ulle < ullx) {
9199       ullx = ulle;
9200     }
9201   }
9202 #pragma omp atomic compare capture
9203   {
9204     ullv = ullx;
9205     if (ullx < ulle) {
9206       ullx = ulle;
9207     }
9208   }
9209 #pragma omp atomic compare capture
9210   {
9211     ullv = ullx;
9212     if (ullx == ulle) {
9213       ullx = ulld;
9214     }
9215   }
9216 #pragma omp atomic compare capture
9217   {
9218     ullv = ullx;
9219     if (ulle == ullx) {
9220       ullx = ulld;
9221     }
9222   }
9223 #pragma omp atomic compare capture
9224   {
9225     if (ulle > ullx) {
9226       ullx = ulle;
9227     }
9228     ullv = ullx;
9229   }
9230 #pragma omp atomic compare capture
9231   {
9232     if (ullx > ulle) {
9233       ullx = ulle;
9234     }
9235     ullv = ullx;
9236   }
9237 #pragma omp atomic compare capture
9238   {
9239     if (ulle < ullx) {
9240       ullx = ulle;
9241     }
9242     ullv = ullx;
9243   }
9244 #pragma omp atomic compare capture
9245   {
9246     if (ullx < ulle) {
9247       ullx = ulle;
9248     }
9249     ullv = ullx;
9250   }
9251 #pragma omp atomic compare capture
9252   {
9253     if (ullx == ulle) {
9254       ullx = ulld;
9255     }
9256     ullv = ullx;
9257   }
9258 #pragma omp atomic compare capture
9259   {
9260     if (ulle == ullx) {
9261       ullx = ulld;
9262     }
9263     ullv = ullx;
9264   }
9265 #pragma omp atomic compare capture
9266   if (ullx == ulle) {
9267     ullx = ulld;
9268   } else {
9269     ullv = ullx;
9270   }
9271 #pragma omp atomic compare capture
9272   if (ulle == ullx) {
9273     ullx = ulld;
9274   } else {
9275     ullv = ullx;
9276   }
9277 #pragma omp atomic compare capture
9278   {
9279     ullr = ullx == ulle;
9280     if (ullr) {
9281       ullx = ulld;
9282     }
9283   }
9284 #pragma omp atomic compare capture
9285   {
9286     ullr = ulle == ullx;
9287     if (ullr) {
9288       ullx = ulld;
9289     }
9290   }
9291 #pragma omp atomic compare capture
9292   {
9293     ullr = ullx == ulle;
9294     if (ullr) {
9295       ullx = ulld;
9296     } else {
9297       ullv = ullx;
9298     }
9299   }
9300 #pragma omp atomic compare capture
9301   {
9302     ullr = ulle == ullx;
9303     if (ullr) {
9304       ullx = ulld;
9305     } else {
9306       ullv = ullx;
9307     }
9308   }
9309 
9310 #pragma omp atomic compare capture acq_rel
9311   {
9312     ullv = ullx;
9313     if (ulle > ullx) {
9314       ullx = ulle;
9315     }
9316   }
9317 #pragma omp atomic compare capture acq_rel
9318   {
9319     ullv = ullx;
9320     if (ullx > ulle) {
9321       ullx = ulle;
9322     }
9323   }
9324 #pragma omp atomic compare capture acq_rel
9325   {
9326     ullv = ullx;
9327     if (ulle < ullx) {
9328       ullx = ulle;
9329     }
9330   }
9331 #pragma omp atomic compare capture acq_rel
9332   {
9333     ullv = ullx;
9334     if (ullx < ulle) {
9335       ullx = ulle;
9336     }
9337   }
9338 #pragma omp atomic compare capture acq_rel
9339   {
9340     ullv = ullx;
9341     if (ullx == ulle) {
9342       ullx = ulld;
9343     }
9344   }
9345 #pragma omp atomic compare capture acq_rel
9346   {
9347     ullv = ullx;
9348     if (ulle == ullx) {
9349       ullx = ulld;
9350     }
9351   }
9352 #pragma omp atomic compare capture acq_rel
9353   {
9354     if (ulle > ullx) {
9355       ullx = ulle;
9356     }
9357     ullv = ullx;
9358   }
9359 #pragma omp atomic compare capture acq_rel
9360   {
9361     if (ullx > ulle) {
9362       ullx = ulle;
9363     }
9364     ullv = ullx;
9365   }
9366 #pragma omp atomic compare capture acq_rel
9367   {
9368     if (ulle < ullx) {
9369       ullx = ulle;
9370     }
9371     ullv = ullx;
9372   }
9373 #pragma omp atomic compare capture acq_rel
9374   {
9375     if (ullx < ulle) {
9376       ullx = ulle;
9377     }
9378     ullv = ullx;
9379   }
9380 #pragma omp atomic compare capture acq_rel
9381   {
9382     if (ullx == ulle) {
9383       ullx = ulld;
9384     }
9385     ullv = ullx;
9386   }
9387 #pragma omp atomic compare capture acq_rel
9388   {
9389     if (ulle == ullx) {
9390       ullx = ulld;
9391     }
9392     ullv = ullx;
9393   }
9394 #pragma omp atomic compare capture acq_rel
9395   if (ullx == ulle) {
9396     ullx = ulld;
9397   } else {
9398     ullv = ullx;
9399   }
9400 #pragma omp atomic compare capture acq_rel
9401   if (ulle == ullx) {
9402     ullx = ulld;
9403   } else {
9404     ullv = ullx;
9405   }
9406 #pragma omp atomic compare capture acq_rel
9407   {
9408     ullr = ullx == ulle;
9409     if (ullr) {
9410       ullx = ulld;
9411     }
9412   }
9413 #pragma omp atomic compare capture acq_rel
9414   {
9415     ullr = ulle == ullx;
9416     if (ullr) {
9417       ullx = ulld;
9418     }
9419   }
9420 #pragma omp atomic compare capture acq_rel
9421   {
9422     ullr = ullx == ulle;
9423     if (ullr) {
9424       ullx = ulld;
9425     } else {
9426       ullv = ullx;
9427     }
9428   }
9429 #pragma omp atomic compare capture acq_rel
9430   {
9431     ullr = ulle == ullx;
9432     if (ullr) {
9433       ullx = ulld;
9434     } else {
9435       ullv = ullx;
9436     }
9437   }
9438 
9439 #pragma omp atomic compare capture acquire
9440   {
9441     ullv = ullx;
9442     if (ulle > ullx) {
9443       ullx = ulle;
9444     }
9445   }
9446 #pragma omp atomic compare capture acquire
9447   {
9448     ullv = ullx;
9449     if (ullx > ulle) {
9450       ullx = ulle;
9451     }
9452   }
9453 #pragma omp atomic compare capture acquire
9454   {
9455     ullv = ullx;
9456     if (ulle < ullx) {
9457       ullx = ulle;
9458     }
9459   }
9460 #pragma omp atomic compare capture acquire
9461   {
9462     ullv = ullx;
9463     if (ullx < ulle) {
9464       ullx = ulle;
9465     }
9466   }
9467 #pragma omp atomic compare capture acquire
9468   {
9469     ullv = ullx;
9470     if (ullx == ulle) {
9471       ullx = ulld;
9472     }
9473   }
9474 #pragma omp atomic compare capture acquire
9475   {
9476     ullv = ullx;
9477     if (ulle == ullx) {
9478       ullx = ulld;
9479     }
9480   }
9481 #pragma omp atomic compare capture acquire
9482   {
9483     if (ulle > ullx) {
9484       ullx = ulle;
9485     }
9486     ullv = ullx;
9487   }
9488 #pragma omp atomic compare capture acquire
9489   {
9490     if (ullx > ulle) {
9491       ullx = ulle;
9492     }
9493     ullv = ullx;
9494   }
9495 #pragma omp atomic compare capture acquire
9496   {
9497     if (ulle < ullx) {
9498       ullx = ulle;
9499     }
9500     ullv = ullx;
9501   }
9502 #pragma omp atomic compare capture acquire
9503   {
9504     if (ullx < ulle) {
9505       ullx = ulle;
9506     }
9507     ullv = ullx;
9508   }
9509 #pragma omp atomic compare capture acquire
9510   {
9511     if (ullx == ulle) {
9512       ullx = ulld;
9513     }
9514     ullv = ullx;
9515   }
9516 #pragma omp atomic compare capture acquire
9517   {
9518     if (ulle == ullx) {
9519       ullx = ulld;
9520     }
9521     ullv = ullx;
9522   }
9523 #pragma omp atomic compare capture acquire
9524   if (ullx == ulle) {
9525     ullx = ulld;
9526   } else {
9527     ullv = ullx;
9528   }
9529 #pragma omp atomic compare capture acquire
9530   if (ulle == ullx) {
9531     ullx = ulld;
9532   } else {
9533     ullv = ullx;
9534   }
9535 #pragma omp atomic compare capture acquire
9536   {
9537     ullr = ullx == ulle;
9538     if (ullr) {
9539       ullx = ulld;
9540     }
9541   }
9542 #pragma omp atomic compare capture acquire
9543   {
9544     ullr = ulle == ullx;
9545     if (ullr) {
9546       ullx = ulld;
9547     }
9548   }
9549 #pragma omp atomic compare capture acquire
9550   {
9551     ullr = ullx == ulle;
9552     if (ullr) {
9553       ullx = ulld;
9554     } else {
9555       ullv = ullx;
9556     }
9557   }
9558 #pragma omp atomic compare capture acquire
9559   {
9560     ullr = ulle == ullx;
9561     if (ullr) {
9562       ullx = ulld;
9563     } else {
9564       ullv = ullx;
9565     }
9566   }
9567 
9568 #pragma omp atomic compare capture relaxed
9569   {
9570     ullv = ullx;
9571     if (ulle > ullx) {
9572       ullx = ulle;
9573     }
9574   }
9575 #pragma omp atomic compare capture relaxed
9576   {
9577     ullv = ullx;
9578     if (ullx > ulle) {
9579       ullx = ulle;
9580     }
9581   }
9582 #pragma omp atomic compare capture relaxed
9583   {
9584     ullv = ullx;
9585     if (ulle < ullx) {
9586       ullx = ulle;
9587     }
9588   }
9589 #pragma omp atomic compare capture relaxed
9590   {
9591     ullv = ullx;
9592     if (ullx < ulle) {
9593       ullx = ulle;
9594     }
9595   }
9596 #pragma omp atomic compare capture relaxed
9597   {
9598     ullv = ullx;
9599     if (ullx == ulle) {
9600       ullx = ulld;
9601     }
9602   }
9603 #pragma omp atomic compare capture relaxed
9604   {
9605     ullv = ullx;
9606     if (ulle == ullx) {
9607       ullx = ulld;
9608     }
9609   }
9610 #pragma omp atomic compare capture relaxed
9611   {
9612     if (ulle > ullx) {
9613       ullx = ulle;
9614     }
9615     ullv = ullx;
9616   }
9617 #pragma omp atomic compare capture relaxed
9618   {
9619     if (ullx > ulle) {
9620       ullx = ulle;
9621     }
9622     ullv = ullx;
9623   }
9624 #pragma omp atomic compare capture relaxed
9625   {
9626     if (ulle < ullx) {
9627       ullx = ulle;
9628     }
9629     ullv = ullx;
9630   }
9631 #pragma omp atomic compare capture relaxed
9632   {
9633     if (ullx < ulle) {
9634       ullx = ulle;
9635     }
9636     ullv = ullx;
9637   }
9638 #pragma omp atomic compare capture relaxed
9639   {
9640     if (ullx == ulle) {
9641       ullx = ulld;
9642     }
9643     ullv = ullx;
9644   }
9645 #pragma omp atomic compare capture relaxed
9646   {
9647     if (ulle == ullx) {
9648       ullx = ulld;
9649     }
9650     ullv = ullx;
9651   }
9652 #pragma omp atomic compare capture relaxed
9653   if (ullx == ulle) {
9654     ullx = ulld;
9655   } else {
9656     ullv = ullx;
9657   }
9658 #pragma omp atomic compare capture relaxed
9659   if (ulle == ullx) {
9660     ullx = ulld;
9661   } else {
9662     ullv = ullx;
9663   }
9664 #pragma omp atomic compare capture relaxed
9665   {
9666     ullr = ullx == ulle;
9667     if (ullr) {
9668       ullx = ulld;
9669     }
9670   }
9671 #pragma omp atomic compare capture relaxed
9672   {
9673     ullr = ulle == ullx;
9674     if (ullr) {
9675       ullx = ulld;
9676     }
9677   }
9678 #pragma omp atomic compare capture relaxed
9679   {
9680     ullr = ullx == ulle;
9681     if (ullr) {
9682       ullx = ulld;
9683     } else {
9684       ullv = ullx;
9685     }
9686   }
9687 #pragma omp atomic compare capture relaxed
9688   {
9689     ullr = ulle == ullx;
9690     if (ullr) {
9691       ullx = ulld;
9692     } else {
9693       ullv = ullx;
9694     }
9695   }
9696 
9697 #pragma omp atomic compare capture release
9698   {
9699     ullv = ullx;
9700     if (ulle > ullx) {
9701       ullx = ulle;
9702     }
9703   }
9704 #pragma omp atomic compare capture release
9705   {
9706     ullv = ullx;
9707     if (ullx > ulle) {
9708       ullx = ulle;
9709     }
9710   }
9711 #pragma omp atomic compare capture release
9712   {
9713     ullv = ullx;
9714     if (ulle < ullx) {
9715       ullx = ulle;
9716     }
9717   }
9718 #pragma omp atomic compare capture release
9719   {
9720     ullv = ullx;
9721     if (ullx < ulle) {
9722       ullx = ulle;
9723     }
9724   }
9725 #pragma omp atomic compare capture release
9726   {
9727     ullv = ullx;
9728     if (ullx == ulle) {
9729       ullx = ulld;
9730     }
9731   }
9732 #pragma omp atomic compare capture release
9733   {
9734     ullv = ullx;
9735     if (ulle == ullx) {
9736       ullx = ulld;
9737     }
9738   }
9739 #pragma omp atomic compare capture release
9740   {
9741     if (ulle > ullx) {
9742       ullx = ulle;
9743     }
9744     ullv = ullx;
9745   }
9746 #pragma omp atomic compare capture release
9747   {
9748     if (ullx > ulle) {
9749       ullx = ulle;
9750     }
9751     ullv = ullx;
9752   }
9753 #pragma omp atomic compare capture release
9754   {
9755     if (ulle < ullx) {
9756       ullx = ulle;
9757     }
9758     ullv = ullx;
9759   }
9760 #pragma omp atomic compare capture release
9761   {
9762     if (ullx < ulle) {
9763       ullx = ulle;
9764     }
9765     ullv = ullx;
9766   }
9767 #pragma omp atomic compare capture release
9768   {
9769     if (ullx == ulle) {
9770       ullx = ulld;
9771     }
9772     ullv = ullx;
9773   }
9774 #pragma omp atomic compare capture release
9775   {
9776     if (ulle == ullx) {
9777       ullx = ulld;
9778     }
9779     ullv = ullx;
9780   }
9781 #pragma omp atomic compare capture release
9782   if (ullx == ulle) {
9783     ullx = ulld;
9784   } else {
9785     ullv = ullx;
9786   }
9787 #pragma omp atomic compare capture release
9788   if (ulle == ullx) {
9789     ullx = ulld;
9790   } else {
9791     ullv = ullx;
9792   }
9793 #pragma omp atomic compare capture release
9794   {
9795     ullr = ullx == ulle;
9796     if (ullr) {
9797       ullx = ulld;
9798     }
9799   }
9800 #pragma omp atomic compare capture release
9801   {
9802     ullr = ulle == ullx;
9803     if (ullr) {
9804       ullx = ulld;
9805     }
9806   }
9807 #pragma omp atomic compare capture release
9808   {
9809     ullr = ullx == ulle;
9810     if (ullr) {
9811       ullx = ulld;
9812     } else {
9813       ullv = ullx;
9814     }
9815   }
9816 #pragma omp atomic compare capture release
9817   {
9818     ullr = ulle == ullx;
9819     if (ullr) {
9820       ullx = ulld;
9821     } else {
9822       ullv = ullx;
9823     }
9824   }
9825 
9826 #pragma omp atomic compare capture seq_cst
9827   {
9828     ullv = ullx;
9829     if (ulle > ullx) {
9830       ullx = ulle;
9831     }
9832   }
9833 #pragma omp atomic compare capture seq_cst
9834   {
9835     ullv = ullx;
9836     if (ullx > ulle) {
9837       ullx = ulle;
9838     }
9839   }
9840 #pragma omp atomic compare capture seq_cst
9841   {
9842     ullv = ullx;
9843     if (ulle < ullx) {
9844       ullx = ulle;
9845     }
9846   }
9847 #pragma omp atomic compare capture seq_cst
9848   {
9849     ullv = ullx;
9850     if (ullx < ulle) {
9851       ullx = ulle;
9852     }
9853   }
9854 #pragma omp atomic compare capture seq_cst
9855   {
9856     ullv = ullx;
9857     if (ullx == ulle) {
9858       ullx = ulld;
9859     }
9860   }
9861 #pragma omp atomic compare capture seq_cst
9862   {
9863     ullv = ullx;
9864     if (ulle == ullx) {
9865       ullx = ulld;
9866     }
9867   }
9868 #pragma omp atomic compare capture seq_cst
9869   {
9870     if (ulle > ullx) {
9871       ullx = ulle;
9872     }
9873     ullv = ullx;
9874   }
9875 #pragma omp atomic compare capture seq_cst
9876   {
9877     if (ullx > ulle) {
9878       ullx = ulle;
9879     }
9880     ullv = ullx;
9881   }
9882 #pragma omp atomic compare capture seq_cst
9883   {
9884     if (ulle < ullx) {
9885       ullx = ulle;
9886     }
9887     ullv = ullx;
9888   }
9889 #pragma omp atomic compare capture seq_cst
9890   {
9891     if (ullx < ulle) {
9892       ullx = ulle;
9893     }
9894     ullv = ullx;
9895   }
9896 #pragma omp atomic compare capture seq_cst
9897   {
9898     if (ullx == ulle) {
9899       ullx = ulld;
9900     }
9901     ullv = ullx;
9902   }
9903 #pragma omp atomic compare capture seq_cst
9904   {
9905     if (ulle == ullx) {
9906       ullx = ulld;
9907     }
9908     ullv = ullx;
9909   }
9910 #pragma omp atomic compare capture seq_cst
9911   if (ullx == ulle) {
9912     ullx = ulld;
9913   } else {
9914     ullv = ullx;
9915   }
9916 #pragma omp atomic compare capture seq_cst
9917   if (ulle == ullx) {
9918     ullx = ulld;
9919   } else {
9920     ullv = ullx;
9921   }
9922 #pragma omp atomic compare capture seq_cst
9923   {
9924     ullr = ullx == ulle;
9925     if (ullr) {
9926       ullx = ulld;
9927     }
9928   }
9929 #pragma omp atomic compare capture seq_cst
9930   {
9931     ullr = ulle == ullx;
9932     if (ullr) {
9933       ullx = ulld;
9934     }
9935   }
9936 #pragma omp atomic compare capture seq_cst
9937   {
9938     ullr = ullx == ulle;
9939     if (ullr) {
9940       ullx = ulld;
9941     } else {
9942       ullv = ullx;
9943     }
9944   }
9945 #pragma omp atomic compare capture seq_cst
9946   {
9947     ullr = ulle == ullx;
9948     if (ullr) {
9949       ullx = ulld;
9950     } else {
9951       ullv = ullx;
9952     }
9953   }
9954 
9955 #pragma omp atomic compare capture
9956   {
9957     fv = fx;
9958     if (fe > fx) {
9959       fx = fe;
9960     }
9961   }
9962 #pragma omp atomic compare capture
9963   {
9964     fv = fx;
9965     if (fx > fe) {
9966       fx = fe;
9967     }
9968   }
9969 #pragma omp atomic compare capture
9970   {
9971     fv = fx;
9972     if (fe < fx) {
9973       fx = fe;
9974     }
9975   }
9976 #pragma omp atomic compare capture
9977   {
9978     fv = fx;
9979     if (fx < fe) {
9980       fx = fe;
9981     }
9982   }
9983 #pragma omp atomic compare capture
9984   {
9985     fv = fx;
9986     if (fx == fe) {
9987       fx = fd;
9988     }
9989   }
9990 #pragma omp atomic compare capture
9991   {
9992     fv = fx;
9993     if (fe == fx) {
9994       fx = fd;
9995     }
9996   }
9997 #pragma omp atomic compare capture
9998   {
9999     if (fe > fx) {
10000       fx = fe;
10001     }
10002     fv = fx;
10003   }
10004 #pragma omp atomic compare capture
10005   {
10006     if (fx > fe) {
10007       fx = fe;
10008     }
10009     fv = fx;
10010   }
10011 #pragma omp atomic compare capture
10012   {
10013     if (fe < fx) {
10014       fx = fe;
10015     }
10016     fv = fx;
10017   }
10018 #pragma omp atomic compare capture
10019   {
10020     if (fx < fe) {
10021       fx = fe;
10022     }
10023     fv = fx;
10024   }
10025 #pragma omp atomic compare capture
10026   {
10027     if (fx == fe) {
10028       fx = fd;
10029     }
10030     fv = fx;
10031   }
10032 #pragma omp atomic compare capture
10033   {
10034     if (fe == fx) {
10035       fx = fd;
10036     }
10037     fv = fx;
10038   }
10039 #pragma omp atomic compare capture
10040   if (fx == fe) {
10041     fx = fd;
10042   } else {
10043     fv = fx;
10044   }
10045 #pragma omp atomic compare capture
10046   if (fe == fx) {
10047     fx = fd;
10048   } else {
10049     fv = fx;
10050   }
10051 #pragma omp atomic compare capture
10052   {
10053     ir = fx == fe;
10054     if (ir) {
10055       fx = fd;
10056     }
10057   }
10058 #pragma omp atomic compare capture
10059   {
10060     ir = fe == fx;
10061     if (ir) {
10062       fx = fd;
10063     }
10064   }
10065 #pragma omp atomic compare capture
10066   {
10067     ir = fx == fe;
10068     if (ir) {
10069       fx = fd;
10070     } else {
10071       fv = fx;
10072     }
10073   }
10074 #pragma omp atomic compare capture
10075   {
10076     ir = fe == fx;
10077     if (ir) {
10078       fx = fd;
10079     } else {
10080       fv = fx;
10081     }
10082   }
10083 
10084 #pragma omp atomic compare capture acq_rel
10085   {
10086     fv = fx;
10087     if (fe > fx) {
10088       fx = fe;
10089     }
10090   }
10091 #pragma omp atomic compare capture acq_rel
10092   {
10093     fv = fx;
10094     if (fx > fe) {
10095       fx = fe;
10096     }
10097   }
10098 #pragma omp atomic compare capture acq_rel
10099   {
10100     fv = fx;
10101     if (fe < fx) {
10102       fx = fe;
10103     }
10104   }
10105 #pragma omp atomic compare capture acq_rel
10106   {
10107     fv = fx;
10108     if (fx < fe) {
10109       fx = fe;
10110     }
10111   }
10112 #pragma omp atomic compare capture acq_rel
10113   {
10114     fv = fx;
10115     if (fx == fe) {
10116       fx = fd;
10117     }
10118   }
10119 #pragma omp atomic compare capture acq_rel
10120   {
10121     fv = fx;
10122     if (fe == fx) {
10123       fx = fd;
10124     }
10125   }
10126 #pragma omp atomic compare capture acq_rel
10127   {
10128     if (fe > fx) {
10129       fx = fe;
10130     }
10131     fv = fx;
10132   }
10133 #pragma omp atomic compare capture acq_rel
10134   {
10135     if (fx > fe) {
10136       fx = fe;
10137     }
10138     fv = fx;
10139   }
10140 #pragma omp atomic compare capture acq_rel
10141   {
10142     if (fe < fx) {
10143       fx = fe;
10144     }
10145     fv = fx;
10146   }
10147 #pragma omp atomic compare capture acq_rel
10148   {
10149     if (fx < fe) {
10150       fx = fe;
10151     }
10152     fv = fx;
10153   }
10154 #pragma omp atomic compare capture acq_rel
10155   {
10156     if (fx == fe) {
10157       fx = fd;
10158     }
10159     fv = fx;
10160   }
10161 #pragma omp atomic compare capture acq_rel
10162   {
10163     if (fe == fx) {
10164       fx = fd;
10165     }
10166     fv = fx;
10167   }
10168 #pragma omp atomic compare capture acq_rel
10169   if (fx == fe) {
10170     fx = fd;
10171   } else {
10172     fv = fx;
10173   }
10174 #pragma omp atomic compare capture acq_rel
10175   if (fe == fx) {
10176     fx = fd;
10177   } else {
10178     fv = fx;
10179   }
10180 #pragma omp atomic compare capture acq_rel
10181   {
10182     ir = fx == fe;
10183     if (ir) {
10184       fx = fd;
10185     }
10186   }
10187 #pragma omp atomic compare capture acq_rel
10188   {
10189     ir = fe == fx;
10190     if (ir) {
10191       fx = fd;
10192     }
10193   }
10194 #pragma omp atomic compare capture acq_rel
10195   {
10196     ir = fx == fe;
10197     if (ir) {
10198       fx = fd;
10199     } else {
10200       fv = fx;
10201     }
10202   }
10203 #pragma omp atomic compare capture acq_rel
10204   {
10205     ir = fe == fx;
10206     if (ir) {
10207       fx = fd;
10208     } else {
10209       fv = fx;
10210     }
10211   }
10212 
10213 #pragma omp atomic compare capture acquire
10214   {
10215     fv = fx;
10216     if (fe > fx) {
10217       fx = fe;
10218     }
10219   }
10220 #pragma omp atomic compare capture acquire
10221   {
10222     fv = fx;
10223     if (fx > fe) {
10224       fx = fe;
10225     }
10226   }
10227 #pragma omp atomic compare capture acquire
10228   {
10229     fv = fx;
10230     if (fe < fx) {
10231       fx = fe;
10232     }
10233   }
10234 #pragma omp atomic compare capture acquire
10235   {
10236     fv = fx;
10237     if (fx < fe) {
10238       fx = fe;
10239     }
10240   }
10241 #pragma omp atomic compare capture acquire
10242   {
10243     fv = fx;
10244     if (fx == fe) {
10245       fx = fd;
10246     }
10247   }
10248 #pragma omp atomic compare capture acquire
10249   {
10250     fv = fx;
10251     if (fe == fx) {
10252       fx = fd;
10253     }
10254   }
10255 #pragma omp atomic compare capture acquire
10256   {
10257     if (fe > fx) {
10258       fx = fe;
10259     }
10260     fv = fx;
10261   }
10262 #pragma omp atomic compare capture acquire
10263   {
10264     if (fx > fe) {
10265       fx = fe;
10266     }
10267     fv = fx;
10268   }
10269 #pragma omp atomic compare capture acquire
10270   {
10271     if (fe < fx) {
10272       fx = fe;
10273     }
10274     fv = fx;
10275   }
10276 #pragma omp atomic compare capture acquire
10277   {
10278     if (fx < fe) {
10279       fx = fe;
10280     }
10281     fv = fx;
10282   }
10283 #pragma omp atomic compare capture acquire
10284   {
10285     if (fx == fe) {
10286       fx = fd;
10287     }
10288     fv = fx;
10289   }
10290 #pragma omp atomic compare capture acquire
10291   {
10292     if (fe == fx) {
10293       fx = fd;
10294     }
10295     fv = fx;
10296   }
10297 #pragma omp atomic compare capture acquire
10298   if (fx == fe) {
10299     fx = fd;
10300   } else {
10301     fv = fx;
10302   }
10303 #pragma omp atomic compare capture acquire
10304   if (fe == fx) {
10305     fx = fd;
10306   } else {
10307     fv = fx;
10308   }
10309 #pragma omp atomic compare capture acquire
10310   {
10311     ir = fx == fe;
10312     if (ir) {
10313       fx = fd;
10314     }
10315   }
10316 #pragma omp atomic compare capture acquire
10317   {
10318     ir = fe == fx;
10319     if (ir) {
10320       fx = fd;
10321     }
10322   }
10323 #pragma omp atomic compare capture acquire
10324   {
10325     ir = fx == fe;
10326     if (ir) {
10327       fx = fd;
10328     } else {
10329       fv = fx;
10330     }
10331   }
10332 #pragma omp atomic compare capture acquire
10333   {
10334     ir = fe == fx;
10335     if (ir) {
10336       fx = fd;
10337     } else {
10338       fv = fx;
10339     }
10340   }
10341 
10342 #pragma omp atomic compare capture relaxed
10343   {
10344     fv = fx;
10345     if (fe > fx) {
10346       fx = fe;
10347     }
10348   }
10349 #pragma omp atomic compare capture relaxed
10350   {
10351     fv = fx;
10352     if (fx > fe) {
10353       fx = fe;
10354     }
10355   }
10356 #pragma omp atomic compare capture relaxed
10357   {
10358     fv = fx;
10359     if (fe < fx) {
10360       fx = fe;
10361     }
10362   }
10363 #pragma omp atomic compare capture relaxed
10364   {
10365     fv = fx;
10366     if (fx < fe) {
10367       fx = fe;
10368     }
10369   }
10370 #pragma omp atomic compare capture relaxed
10371   {
10372     fv = fx;
10373     if (fx == fe) {
10374       fx = fd;
10375     }
10376   }
10377 #pragma omp atomic compare capture relaxed
10378   {
10379     fv = fx;
10380     if (fe == fx) {
10381       fx = fd;
10382     }
10383   }
10384 #pragma omp atomic compare capture relaxed
10385   {
10386     if (fe > fx) {
10387       fx = fe;
10388     }
10389     fv = fx;
10390   }
10391 #pragma omp atomic compare capture relaxed
10392   {
10393     if (fx > fe) {
10394       fx = fe;
10395     }
10396     fv = fx;
10397   }
10398 #pragma omp atomic compare capture relaxed
10399   {
10400     if (fe < fx) {
10401       fx = fe;
10402     }
10403     fv = fx;
10404   }
10405 #pragma omp atomic compare capture relaxed
10406   {
10407     if (fx < fe) {
10408       fx = fe;
10409     }
10410     fv = fx;
10411   }
10412 #pragma omp atomic compare capture relaxed
10413   {
10414     if (fx == fe) {
10415       fx = fd;
10416     }
10417     fv = fx;
10418   }
10419 #pragma omp atomic compare capture relaxed
10420   {
10421     if (fe == fx) {
10422       fx = fd;
10423     }
10424     fv = fx;
10425   }
10426 #pragma omp atomic compare capture relaxed
10427   if (fx == fe) {
10428     fx = fd;
10429   } else {
10430     fv = fx;
10431   }
10432 #pragma omp atomic compare capture relaxed
10433   if (fe == fx) {
10434     fx = fd;
10435   } else {
10436     fv = fx;
10437   }
10438 #pragma omp atomic compare capture relaxed
10439   {
10440     ir = fx == fe;
10441     if (ir) {
10442       fx = fd;
10443     }
10444   }
10445 #pragma omp atomic compare capture relaxed
10446   {
10447     ir = fe == fx;
10448     if (ir) {
10449       fx = fd;
10450     }
10451   }
10452 #pragma omp atomic compare capture relaxed
10453   {
10454     ir = fx == fe;
10455     if (ir) {
10456       fx = fd;
10457     } else {
10458       fv = fx;
10459     }
10460   }
10461 #pragma omp atomic compare capture relaxed
10462   {
10463     ir = fe == fx;
10464     if (ir) {
10465       fx = fd;
10466     } else {
10467       fv = fx;
10468     }
10469   }
10470 
10471 #pragma omp atomic compare capture release
10472   {
10473     fv = fx;
10474     if (fe > fx) {
10475       fx = fe;
10476     }
10477   }
10478 #pragma omp atomic compare capture release
10479   {
10480     fv = fx;
10481     if (fx > fe) {
10482       fx = fe;
10483     }
10484   }
10485 #pragma omp atomic compare capture release
10486   {
10487     fv = fx;
10488     if (fe < fx) {
10489       fx = fe;
10490     }
10491   }
10492 #pragma omp atomic compare capture release
10493   {
10494     fv = fx;
10495     if (fx < fe) {
10496       fx = fe;
10497     }
10498   }
10499 #pragma omp atomic compare capture release
10500   {
10501     fv = fx;
10502     if (fx == fe) {
10503       fx = fd;
10504     }
10505   }
10506 #pragma omp atomic compare capture release
10507   {
10508     fv = fx;
10509     if (fe == fx) {
10510       fx = fd;
10511     }
10512   }
10513 #pragma omp atomic compare capture release
10514   {
10515     if (fe > fx) {
10516       fx = fe;
10517     }
10518     fv = fx;
10519   }
10520 #pragma omp atomic compare capture release
10521   {
10522     if (fx > fe) {
10523       fx = fe;
10524     }
10525     fv = fx;
10526   }
10527 #pragma omp atomic compare capture release
10528   {
10529     if (fe < fx) {
10530       fx = fe;
10531     }
10532     fv = fx;
10533   }
10534 #pragma omp atomic compare capture release
10535   {
10536     if (fx < fe) {
10537       fx = fe;
10538     }
10539     fv = fx;
10540   }
10541 #pragma omp atomic compare capture release
10542   {
10543     if (fx == fe) {
10544       fx = fd;
10545     }
10546     fv = fx;
10547   }
10548 #pragma omp atomic compare capture release
10549   {
10550     if (fe == fx) {
10551       fx = fd;
10552     }
10553     fv = fx;
10554   }
10555 #pragma omp atomic compare capture release
10556   if (fx == fe) {
10557     fx = fd;
10558   } else {
10559     fv = fx;
10560   }
10561 #pragma omp atomic compare capture release
10562   if (fe == fx) {
10563     fx = fd;
10564   } else {
10565     fv = fx;
10566   }
10567 #pragma omp atomic compare capture release
10568   {
10569     ir = fx == fe;
10570     if (ir) {
10571       fx = fd;
10572     }
10573   }
10574 #pragma omp atomic compare capture release
10575   {
10576     ir = fe == fx;
10577     if (ir) {
10578       fx = fd;
10579     }
10580   }
10581 #pragma omp atomic compare capture release
10582   {
10583     ir = fx == fe;
10584     if (ir) {
10585       fx = fd;
10586     } else {
10587       fv = fx;
10588     }
10589   }
10590 #pragma omp atomic compare capture release
10591   {
10592     ir = fe == fx;
10593     if (ir) {
10594       fx = fd;
10595     } else {
10596       fv = fx;
10597     }
10598   }
10599 
10600 #pragma omp atomic compare capture seq_cst
10601   {
10602     fv = fx;
10603     if (fe > fx) {
10604       fx = fe;
10605     }
10606   }
10607 #pragma omp atomic compare capture seq_cst
10608   {
10609     fv = fx;
10610     if (fx > fe) {
10611       fx = fe;
10612     }
10613   }
10614 #pragma omp atomic compare capture seq_cst
10615   {
10616     fv = fx;
10617     if (fe < fx) {
10618       fx = fe;
10619     }
10620   }
10621 #pragma omp atomic compare capture seq_cst
10622   {
10623     fv = fx;
10624     if (fx < fe) {
10625       fx = fe;
10626     }
10627   }
10628 #pragma omp atomic compare capture seq_cst
10629   {
10630     fv = fx;
10631     if (fx == fe) {
10632       fx = fd;
10633     }
10634   }
10635 #pragma omp atomic compare capture seq_cst
10636   {
10637     fv = fx;
10638     if (fe == fx) {
10639       fx = fd;
10640     }
10641   }
10642 #pragma omp atomic compare capture seq_cst
10643   {
10644     if (fe > fx) {
10645       fx = fe;
10646     }
10647     fv = fx;
10648   }
10649 #pragma omp atomic compare capture seq_cst
10650   {
10651     if (fx > fe) {
10652       fx = fe;
10653     }
10654     fv = fx;
10655   }
10656 #pragma omp atomic compare capture seq_cst
10657   {
10658     if (fe < fx) {
10659       fx = fe;
10660     }
10661     fv = fx;
10662   }
10663 #pragma omp atomic compare capture seq_cst
10664   {
10665     if (fx < fe) {
10666       fx = fe;
10667     }
10668     fv = fx;
10669   }
10670 #pragma omp atomic compare capture seq_cst
10671   {
10672     if (fx == fe) {
10673       fx = fd;
10674     }
10675     fv = fx;
10676   }
10677 #pragma omp atomic compare capture seq_cst
10678   {
10679     if (fe == fx) {
10680       fx = fd;
10681     }
10682     fv = fx;
10683   }
10684 #pragma omp atomic compare capture seq_cst
10685   if (fx == fe) {
10686     fx = fd;
10687   } else {
10688     fv = fx;
10689   }
10690 #pragma omp atomic compare capture seq_cst
10691   if (fe == fx) {
10692     fx = fd;
10693   } else {
10694     fv = fx;
10695   }
10696 #pragma omp atomic compare capture seq_cst
10697   {
10698     ir = fx == fe;
10699     if (ir) {
10700       fx = fd;
10701     }
10702   }
10703 #pragma omp atomic compare capture seq_cst
10704   {
10705     ir = fe == fx;
10706     if (ir) {
10707       fx = fd;
10708     }
10709   }
10710 #pragma omp atomic compare capture seq_cst
10711   {
10712     ir = fx == fe;
10713     if (ir) {
10714       fx = fd;
10715     } else {
10716       fv = fx;
10717     }
10718   }
10719 #pragma omp atomic compare capture seq_cst
10720   {
10721     ir = fe == fx;
10722     if (ir) {
10723       fx = fd;
10724     } else {
10725       fv = fx;
10726     }
10727   }
10728 
10729 #pragma omp atomic compare capture
10730   {
10731     dv = dx;
10732     if (de > dx) {
10733       dx = de;
10734     }
10735   }
10736 #pragma omp atomic compare capture
10737   {
10738     dv = dx;
10739     if (dx > de) {
10740       dx = de;
10741     }
10742   }
10743 #pragma omp atomic compare capture
10744   {
10745     dv = dx;
10746     if (de < dx) {
10747       dx = de;
10748     }
10749   }
10750 #pragma omp atomic compare capture
10751   {
10752     dv = dx;
10753     if (dx < de) {
10754       dx = de;
10755     }
10756   }
10757 #pragma omp atomic compare capture
10758   {
10759     dv = dx;
10760     if (dx == de) {
10761       dx = dd;
10762     }
10763   }
10764 #pragma omp atomic compare capture
10765   {
10766     dv = dx;
10767     if (de == dx) {
10768       dx = dd;
10769     }
10770   }
10771 #pragma omp atomic compare capture
10772   {
10773     if (de > dx) {
10774       dx = de;
10775     }
10776     dv = dx;
10777   }
10778 #pragma omp atomic compare capture
10779   {
10780     if (dx > de) {
10781       dx = de;
10782     }
10783     dv = dx;
10784   }
10785 #pragma omp atomic compare capture
10786   {
10787     if (de < dx) {
10788       dx = de;
10789     }
10790     dv = dx;
10791   }
10792 #pragma omp atomic compare capture
10793   {
10794     if (dx < de) {
10795       dx = de;
10796     }
10797     dv = dx;
10798   }
10799 #pragma omp atomic compare capture
10800   {
10801     if (dx == de) {
10802       dx = dd;
10803     }
10804     dv = dx;
10805   }
10806 #pragma omp atomic compare capture
10807   {
10808     if (de == dx) {
10809       dx = dd;
10810     }
10811     dv = dx;
10812   }
10813 #pragma omp atomic compare capture
10814   if (dx == de) {
10815     dx = dd;
10816   } else {
10817     dv = dx;
10818   }
10819 #pragma omp atomic compare capture
10820   if (de == dx) {
10821     dx = dd;
10822   } else {
10823     dv = dx;
10824   }
10825 #pragma omp atomic compare capture
10826   {
10827     ir = dx == de;
10828     if (ir) {
10829       dx = dd;
10830     }
10831   }
10832 #pragma omp atomic compare capture
10833   {
10834     ir = de == dx;
10835     if (ir) {
10836       dx = dd;
10837     }
10838   }
10839 #pragma omp atomic compare capture
10840   {
10841     ir = dx == de;
10842     if (ir) {
10843       dx = dd;
10844     } else {
10845       dv = dx;
10846     }
10847   }
10848 #pragma omp atomic compare capture
10849   {
10850     ir = de == dx;
10851     if (ir) {
10852       dx = dd;
10853     } else {
10854       dv = dx;
10855     }
10856   }
10857 
10858 #pragma omp atomic compare capture acq_rel
10859   {
10860     dv = dx;
10861     if (de > dx) {
10862       dx = de;
10863     }
10864   }
10865 #pragma omp atomic compare capture acq_rel
10866   {
10867     dv = dx;
10868     if (dx > de) {
10869       dx = de;
10870     }
10871   }
10872 #pragma omp atomic compare capture acq_rel
10873   {
10874     dv = dx;
10875     if (de < dx) {
10876       dx = de;
10877     }
10878   }
10879 #pragma omp atomic compare capture acq_rel
10880   {
10881     dv = dx;
10882     if (dx < de) {
10883       dx = de;
10884     }
10885   }
10886 #pragma omp atomic compare capture acq_rel
10887   {
10888     dv = dx;
10889     if (dx == de) {
10890       dx = dd;
10891     }
10892   }
10893 #pragma omp atomic compare capture acq_rel
10894   {
10895     dv = dx;
10896     if (de == dx) {
10897       dx = dd;
10898     }
10899   }
10900 #pragma omp atomic compare capture acq_rel
10901   {
10902     if (de > dx) {
10903       dx = de;
10904     }
10905     dv = dx;
10906   }
10907 #pragma omp atomic compare capture acq_rel
10908   {
10909     if (dx > de) {
10910       dx = de;
10911     }
10912     dv = dx;
10913   }
10914 #pragma omp atomic compare capture acq_rel
10915   {
10916     if (de < dx) {
10917       dx = de;
10918     }
10919     dv = dx;
10920   }
10921 #pragma omp atomic compare capture acq_rel
10922   {
10923     if (dx < de) {
10924       dx = de;
10925     }
10926     dv = dx;
10927   }
10928 #pragma omp atomic compare capture acq_rel
10929   {
10930     if (dx == de) {
10931       dx = dd;
10932     }
10933     dv = dx;
10934   }
10935 #pragma omp atomic compare capture acq_rel
10936   {
10937     if (de == dx) {
10938       dx = dd;
10939     }
10940     dv = dx;
10941   }
10942 #pragma omp atomic compare capture acq_rel
10943   if (dx == de) {
10944     dx = dd;
10945   } else {
10946     dv = dx;
10947   }
10948 #pragma omp atomic compare capture acq_rel
10949   if (de == dx) {
10950     dx = dd;
10951   } else {
10952     dv = dx;
10953   }
10954 #pragma omp atomic compare capture acq_rel
10955   {
10956     ir = dx == de;
10957     if (ir) {
10958       dx = dd;
10959     }
10960   }
10961 #pragma omp atomic compare capture acq_rel
10962   {
10963     ir = de == dx;
10964     if (ir) {
10965       dx = dd;
10966     }
10967   }
10968 #pragma omp atomic compare capture acq_rel
10969   {
10970     ir = dx == de;
10971     if (ir) {
10972       dx = dd;
10973     } else {
10974       dv = dx;
10975     }
10976   }
10977 #pragma omp atomic compare capture acq_rel
10978   {
10979     ir = de == dx;
10980     if (ir) {
10981       dx = dd;
10982     } else {
10983       dv = dx;
10984     }
10985   }
10986 
10987 #pragma omp atomic compare capture acquire
10988   {
10989     dv = dx;
10990     if (de > dx) {
10991       dx = de;
10992     }
10993   }
10994 #pragma omp atomic compare capture acquire
10995   {
10996     dv = dx;
10997     if (dx > de) {
10998       dx = de;
10999     }
11000   }
11001 #pragma omp atomic compare capture acquire
11002   {
11003     dv = dx;
11004     if (de < dx) {
11005       dx = de;
11006     }
11007   }
11008 #pragma omp atomic compare capture acquire
11009   {
11010     dv = dx;
11011     if (dx < de) {
11012       dx = de;
11013     }
11014   }
11015 #pragma omp atomic compare capture acquire
11016   {
11017     dv = dx;
11018     if (dx == de) {
11019       dx = dd;
11020     }
11021   }
11022 #pragma omp atomic compare capture acquire
11023   {
11024     dv = dx;
11025     if (de == dx) {
11026       dx = dd;
11027     }
11028   }
11029 #pragma omp atomic compare capture acquire
11030   {
11031     if (de > dx) {
11032       dx = de;
11033     }
11034     dv = dx;
11035   }
11036 #pragma omp atomic compare capture acquire
11037   {
11038     if (dx > de) {
11039       dx = de;
11040     }
11041     dv = dx;
11042   }
11043 #pragma omp atomic compare capture acquire
11044   {
11045     if (de < dx) {
11046       dx = de;
11047     }
11048     dv = dx;
11049   }
11050 #pragma omp atomic compare capture acquire
11051   {
11052     if (dx < de) {
11053       dx = de;
11054     }
11055     dv = dx;
11056   }
11057 #pragma omp atomic compare capture acquire
11058   {
11059     if (dx == de) {
11060       dx = dd;
11061     }
11062     dv = dx;
11063   }
11064 #pragma omp atomic compare capture acquire
11065   {
11066     if (de == dx) {
11067       dx = dd;
11068     }
11069     dv = dx;
11070   }
11071 #pragma omp atomic compare capture acquire
11072   if (dx == de) {
11073     dx = dd;
11074   } else {
11075     dv = dx;
11076   }
11077 #pragma omp atomic compare capture acquire
11078   if (de == dx) {
11079     dx = dd;
11080   } else {
11081     dv = dx;
11082   }
11083 #pragma omp atomic compare capture acquire
11084   {
11085     ir = dx == de;
11086     if (ir) {
11087       dx = dd;
11088     }
11089   }
11090 #pragma omp atomic compare capture acquire
11091   {
11092     ir = de == dx;
11093     if (ir) {
11094       dx = dd;
11095     }
11096   }
11097 #pragma omp atomic compare capture acquire
11098   {
11099     ir = dx == de;
11100     if (ir) {
11101       dx = dd;
11102     } else {
11103       dv = dx;
11104     }
11105   }
11106 #pragma omp atomic compare capture acquire
11107   {
11108     ir = de == dx;
11109     if (ir) {
11110       dx = dd;
11111     } else {
11112       dv = dx;
11113     }
11114   }
11115 
11116 #pragma omp atomic compare capture relaxed
11117   {
11118     dv = dx;
11119     if (de > dx) {
11120       dx = de;
11121     }
11122   }
11123 #pragma omp atomic compare capture relaxed
11124   {
11125     dv = dx;
11126     if (dx > de) {
11127       dx = de;
11128     }
11129   }
11130 #pragma omp atomic compare capture relaxed
11131   {
11132     dv = dx;
11133     if (de < dx) {
11134       dx = de;
11135     }
11136   }
11137 #pragma omp atomic compare capture relaxed
11138   {
11139     dv = dx;
11140     if (dx < de) {
11141       dx = de;
11142     }
11143   }
11144 #pragma omp atomic compare capture relaxed
11145   {
11146     dv = dx;
11147     if (dx == de) {
11148       dx = dd;
11149     }
11150   }
11151 #pragma omp atomic compare capture relaxed
11152   {
11153     dv = dx;
11154     if (de == dx) {
11155       dx = dd;
11156     }
11157   }
11158 #pragma omp atomic compare capture relaxed
11159   {
11160     if (de > dx) {
11161       dx = de;
11162     }
11163     dv = dx;
11164   }
11165 #pragma omp atomic compare capture relaxed
11166   {
11167     if (dx > de) {
11168       dx = de;
11169     }
11170     dv = dx;
11171   }
11172 #pragma omp atomic compare capture relaxed
11173   {
11174     if (de < dx) {
11175       dx = de;
11176     }
11177     dv = dx;
11178   }
11179 #pragma omp atomic compare capture relaxed
11180   {
11181     if (dx < de) {
11182       dx = de;
11183     }
11184     dv = dx;
11185   }
11186 #pragma omp atomic compare capture relaxed
11187   {
11188     if (dx == de) {
11189       dx = dd;
11190     }
11191     dv = dx;
11192   }
11193 #pragma omp atomic compare capture relaxed
11194   {
11195     if (de == dx) {
11196       dx = dd;
11197     }
11198     dv = dx;
11199   }
11200 #pragma omp atomic compare capture relaxed
11201   if (dx == de) {
11202     dx = dd;
11203   } else {
11204     dv = dx;
11205   }
11206 #pragma omp atomic compare capture relaxed
11207   if (de == dx) {
11208     dx = dd;
11209   } else {
11210     dv = dx;
11211   }
11212 #pragma omp atomic compare capture relaxed
11213   {
11214     ir = dx == de;
11215     if (ir) {
11216       dx = dd;
11217     }
11218   }
11219 #pragma omp atomic compare capture relaxed
11220   {
11221     ir = de == dx;
11222     if (ir) {
11223       dx = dd;
11224     }
11225   }
11226 #pragma omp atomic compare capture relaxed
11227   {
11228     ir = dx == de;
11229     if (ir) {
11230       dx = dd;
11231     } else {
11232       dv = dx;
11233     }
11234   }
11235 #pragma omp atomic compare capture relaxed
11236   {
11237     ir = de == dx;
11238     if (ir) {
11239       dx = dd;
11240     } else {
11241       dv = dx;
11242     }
11243   }
11244 
11245 #pragma omp atomic compare capture release
11246   {
11247     dv = dx;
11248     if (de > dx) {
11249       dx = de;
11250     }
11251   }
11252 #pragma omp atomic compare capture release
11253   {
11254     dv = dx;
11255     if (dx > de) {
11256       dx = de;
11257     }
11258   }
11259 #pragma omp atomic compare capture release
11260   {
11261     dv = dx;
11262     if (de < dx) {
11263       dx = de;
11264     }
11265   }
11266 #pragma omp atomic compare capture release
11267   {
11268     dv = dx;
11269     if (dx < de) {
11270       dx = de;
11271     }
11272   }
11273 #pragma omp atomic compare capture release
11274   {
11275     dv = dx;
11276     if (dx == de) {
11277       dx = dd;
11278     }
11279   }
11280 #pragma omp atomic compare capture release
11281   {
11282     dv = dx;
11283     if (de == dx) {
11284       dx = dd;
11285     }
11286   }
11287 #pragma omp atomic compare capture release
11288   {
11289     if (de > dx) {
11290       dx = de;
11291     }
11292     dv = dx;
11293   }
11294 #pragma omp atomic compare capture release
11295   {
11296     if (dx > de) {
11297       dx = de;
11298     }
11299     dv = dx;
11300   }
11301 #pragma omp atomic compare capture release
11302   {
11303     if (de < dx) {
11304       dx = de;
11305     }
11306     dv = dx;
11307   }
11308 #pragma omp atomic compare capture release
11309   {
11310     if (dx < de) {
11311       dx = de;
11312     }
11313     dv = dx;
11314   }
11315 #pragma omp atomic compare capture release
11316   {
11317     if (dx == de) {
11318       dx = dd;
11319     }
11320     dv = dx;
11321   }
11322 #pragma omp atomic compare capture release
11323   {
11324     if (de == dx) {
11325       dx = dd;
11326     }
11327     dv = dx;
11328   }
11329 #pragma omp atomic compare capture release
11330   if (dx == de) {
11331     dx = dd;
11332   } else {
11333     dv = dx;
11334   }
11335 #pragma omp atomic compare capture release
11336   if (de == dx) {
11337     dx = dd;
11338   } else {
11339     dv = dx;
11340   }
11341 #pragma omp atomic compare capture release
11342   {
11343     ir = dx == de;
11344     if (ir) {
11345       dx = dd;
11346     }
11347   }
11348 #pragma omp atomic compare capture release
11349   {
11350     ir = de == dx;
11351     if (ir) {
11352       dx = dd;
11353     }
11354   }
11355 #pragma omp atomic compare capture release
11356   {
11357     ir = dx == de;
11358     if (ir) {
11359       dx = dd;
11360     } else {
11361       dv = dx;
11362     }
11363   }
11364 #pragma omp atomic compare capture release
11365   {
11366     ir = de == dx;
11367     if (ir) {
11368       dx = dd;
11369     } else {
11370       dv = dx;
11371     }
11372   }
11373 
11374 #pragma omp atomic compare capture seq_cst
11375   {
11376     dv = dx;
11377     if (de > dx) {
11378       dx = de;
11379     }
11380   }
11381 #pragma omp atomic compare capture seq_cst
11382   {
11383     dv = dx;
11384     if (dx > de) {
11385       dx = de;
11386     }
11387   }
11388 #pragma omp atomic compare capture seq_cst
11389   {
11390     dv = dx;
11391     if (de < dx) {
11392       dx = de;
11393     }
11394   }
11395 #pragma omp atomic compare capture seq_cst
11396   {
11397     dv = dx;
11398     if (dx < de) {
11399       dx = de;
11400     }
11401   }
11402 #pragma omp atomic compare capture seq_cst
11403   {
11404     dv = dx;
11405     if (dx == de) {
11406       dx = dd;
11407     }
11408   }
11409 #pragma omp atomic compare capture seq_cst
11410   {
11411     dv = dx;
11412     if (de == dx) {
11413       dx = dd;
11414     }
11415   }
11416 #pragma omp atomic compare capture seq_cst
11417   {
11418     if (de > dx) {
11419       dx = de;
11420     }
11421     dv = dx;
11422   }
11423 #pragma omp atomic compare capture seq_cst
11424   {
11425     if (dx > de) {
11426       dx = de;
11427     }
11428     dv = dx;
11429   }
11430 #pragma omp atomic compare capture seq_cst
11431   {
11432     if (de < dx) {
11433       dx = de;
11434     }
11435     dv = dx;
11436   }
11437 #pragma omp atomic compare capture seq_cst
11438   {
11439     if (dx < de) {
11440       dx = de;
11441     }
11442     dv = dx;
11443   }
11444 #pragma omp atomic compare capture seq_cst
11445   {
11446     if (dx == de) {
11447       dx = dd;
11448     }
11449     dv = dx;
11450   }
11451 #pragma omp atomic compare capture seq_cst
11452   {
11453     if (de == dx) {
11454       dx = dd;
11455     }
11456     dv = dx;
11457   }
11458 #pragma omp atomic compare capture seq_cst
11459   if (dx == de) {
11460     dx = dd;
11461   } else {
11462     dv = dx;
11463   }
11464 #pragma omp atomic compare capture seq_cst
11465   if (de == dx) {
11466     dx = dd;
11467   } else {
11468     dv = dx;
11469   }
11470 #pragma omp atomic compare capture seq_cst
11471   {
11472     ir = dx == de;
11473     if (ir) {
11474       dx = dd;
11475     }
11476   }
11477 #pragma omp atomic compare capture seq_cst
11478   {
11479     ir = de == dx;
11480     if (ir) {
11481       dx = dd;
11482     }
11483   }
11484 #pragma omp atomic compare capture seq_cst
11485   {
11486     ir = dx == de;
11487     if (ir) {
11488       dx = dd;
11489     } else {
11490       dv = dx;
11491     }
11492   }
11493 #pragma omp atomic compare capture seq_cst
11494   {
11495     ir = de == dx;
11496     if (ir) {
11497       dx = dd;
11498     } else {
11499       dv = dx;
11500     }
11501   }
11502 }
11503 
11504 
cxevd()11505 char cxevd() {
11506   char cx, cv, ce, cd;
11507 
11508 #pragma omp atomic compare capture
11509   {
11510     cv = cx;
11511     cx = cx > ce ? ce : cx;
11512   }
11513 #pragma omp atomic compare capture
11514   {
11515     cv = cx;
11516     cx = cx < ce ? ce : cx;
11517   }
11518 #pragma omp atomic compare capture
11519   {
11520     cv = cx;
11521     cx = cx == ce ? cd : cx;
11522   }
11523 #pragma omp atomic compare capture
11524   {
11525     cx = cx > ce ? ce : cx;
11526     cv = cx;
11527   }
11528 #pragma omp atomic compare capture
11529   {
11530     cx = cx < ce ? ce : cx;
11531     cv = cx;
11532   }
11533 #pragma omp atomic compare capture
11534   {
11535     cx = cx == ce ? cd : cx;
11536     cv = cx;
11537   }
11538 
11539 #pragma omp atomic compare capture acq_rel
11540   {
11541     cv = cx;
11542     cx = cx > ce ? ce : cx;
11543   }
11544 #pragma omp atomic compare capture acq_rel
11545   {
11546     cv = cx;
11547     cx = cx < ce ? ce : cx;
11548   }
11549 #pragma omp atomic compare capture acq_rel
11550   {
11551     cv = cx;
11552     cx = cx == ce ? cd : cx;
11553   }
11554 #pragma omp atomic compare capture acq_rel
11555   {
11556     cx = cx > ce ? ce : cx;
11557     cv = cx;
11558   }
11559 #pragma omp atomic compare capture acq_rel
11560   {
11561     cx = cx < ce ? ce : cx;
11562     cv = cx;
11563   }
11564 #pragma omp atomic compare capture acq_rel
11565   {
11566     cx = cx == ce ? cd : cx;
11567     cv = cx;
11568   }
11569 
11570 #pragma omp atomic compare capture acquire
11571   {
11572     cv = cx;
11573     cx = cx > ce ? ce : cx;
11574   }
11575 #pragma omp atomic compare capture acquire
11576   {
11577     cv = cx;
11578     cx = cx < ce ? ce : cx;
11579   }
11580 #pragma omp atomic compare capture acquire
11581   {
11582     cv = cx;
11583     cx = cx == ce ? cd : cx;
11584   }
11585 #pragma omp atomic compare capture acquire
11586   {
11587     cx = cx > ce ? ce : cx;
11588     cv = cx;
11589   }
11590 #pragma omp atomic compare capture acquire
11591   {
11592     cx = cx < ce ? ce : cx;
11593     cv = cx;
11594   }
11595 #pragma omp atomic compare capture acquire
11596   {
11597     cx = cx == ce ? cd : cx;
11598     cv = cx;
11599   }
11600 
11601 #pragma omp atomic compare capture relaxed
11602   {
11603     cv = cx;
11604     cx = cx > ce ? ce : cx;
11605   }
11606 #pragma omp atomic compare capture relaxed
11607   {
11608     cv = cx;
11609     cx = cx < ce ? ce : cx;
11610   }
11611 #pragma omp atomic compare capture relaxed
11612   {
11613     cv = cx;
11614     cx = cx == ce ? cd : cx;
11615   }
11616 #pragma omp atomic compare capture relaxed
11617   {
11618     cx = cx > ce ? ce : cx;
11619     cv = cx;
11620   }
11621 #pragma omp atomic compare capture relaxed
11622   {
11623     cx = cx < ce ? ce : cx;
11624     cv = cx;
11625   }
11626 #pragma omp atomic compare capture relaxed
11627   {
11628     cx = cx == ce ? cd : cx;
11629     cv = cx;
11630   }
11631 
11632 #pragma omp atomic compare capture release
11633   {
11634     cv = cx;
11635     cx = cx > ce ? ce : cx;
11636   }
11637 #pragma omp atomic compare capture release
11638   {
11639     cv = cx;
11640     cx = cx < ce ? ce : cx;
11641   }
11642 #pragma omp atomic compare capture release
11643   {
11644     cv = cx;
11645     cx = cx == ce ? cd : cx;
11646   }
11647 #pragma omp atomic compare capture release
11648   {
11649     cx = cx > ce ? ce : cx;
11650     cv = cx;
11651   }
11652 #pragma omp atomic compare capture release
11653   {
11654     cx = cx < ce ? ce : cx;
11655     cv = cx;
11656   }
11657 #pragma omp atomic compare capture release
11658   {
11659     cx = cx == ce ? cd : cx;
11660     cv = cx;
11661   }
11662 
11663 #pragma omp atomic compare capture seq_cst
11664   {
11665     cv = cx;
11666     cx = cx > ce ? ce : cx;
11667   }
11668 #pragma omp atomic compare capture seq_cst
11669   {
11670     cv = cx;
11671     cx = cx < ce ? ce : cx;
11672   }
11673 #pragma omp atomic compare capture seq_cst
11674   {
11675     cv = cx;
11676     cx = cx == ce ? cd : cx;
11677   }
11678 #pragma omp atomic compare capture seq_cst
11679   {
11680     cx = cx > ce ? ce : cx;
11681     cv = cx;
11682   }
11683 #pragma omp atomic compare capture seq_cst
11684   {
11685     cx = cx < ce ? ce : cx;
11686     cv = cx;
11687   }
11688 #pragma omp atomic compare capture seq_cst
11689   {
11690     cx = cx == ce ? cd : cx;
11691     cv = cx;
11692   }
11693 
11694   return cv;
11695 }
11696 
ucxevd()11697 unsigned char ucxevd() {
11698   unsigned char ucx, ucv, uce, ucd;
11699 
11700 #pragma omp atomic compare capture
11701   {
11702     ucv = ucx;
11703     ucx = ucx > uce ? uce : ucx;
11704   }
11705 #pragma omp atomic compare capture
11706   {
11707     ucv = ucx;
11708     ucx = ucx < uce ? uce : ucx;
11709   }
11710 #pragma omp atomic compare capture
11711   {
11712     ucv = ucx;
11713     ucx = ucx == uce ? ucd : ucx;
11714   }
11715 #pragma omp atomic compare capture
11716   {
11717     ucx = ucx > uce ? uce : ucx;
11718     ucv = ucx;
11719   }
11720 #pragma omp atomic compare capture
11721   {
11722     ucx = ucx < uce ? uce : ucx;
11723     ucv = ucx;
11724   }
11725 #pragma omp atomic compare capture
11726   {
11727     ucx = ucx == uce ? ucd : ucx;
11728     ucv = ucx;
11729   }
11730 
11731 #pragma omp atomic compare capture acq_rel
11732   {
11733     ucv = ucx;
11734     ucx = ucx > uce ? uce : ucx;
11735   }
11736 #pragma omp atomic compare capture acq_rel
11737   {
11738     ucv = ucx;
11739     ucx = ucx < uce ? uce : ucx;
11740   }
11741 #pragma omp atomic compare capture acq_rel
11742   {
11743     ucv = ucx;
11744     ucx = ucx == uce ? ucd : ucx;
11745   }
11746 #pragma omp atomic compare capture acq_rel
11747   {
11748     ucx = ucx > uce ? uce : ucx;
11749     ucv = ucx;
11750   }
11751 #pragma omp atomic compare capture acq_rel
11752   {
11753     ucx = ucx < uce ? uce : ucx;
11754     ucv = ucx;
11755   }
11756 #pragma omp atomic compare capture acq_rel
11757   {
11758     ucx = ucx == uce ? ucd : ucx;
11759     ucv = ucx;
11760   }
11761 
11762 #pragma omp atomic compare capture acquire
11763   {
11764     ucv = ucx;
11765     ucx = ucx > uce ? uce : ucx;
11766   }
11767 #pragma omp atomic compare capture acquire
11768   {
11769     ucv = ucx;
11770     ucx = ucx < uce ? uce : ucx;
11771   }
11772 #pragma omp atomic compare capture acquire
11773   {
11774     ucv = ucx;
11775     ucx = ucx == uce ? ucd : ucx;
11776   }
11777 #pragma omp atomic compare capture acquire
11778   {
11779     ucx = ucx > uce ? uce : ucx;
11780     ucv = ucx;
11781   }
11782 #pragma omp atomic compare capture acquire
11783   {
11784     ucx = ucx < uce ? uce : ucx;
11785     ucv = ucx;
11786   }
11787 #pragma omp atomic compare capture acquire
11788   {
11789     ucx = ucx == uce ? ucd : ucx;
11790     ucv = ucx;
11791   }
11792 
11793 #pragma omp atomic compare capture relaxed
11794   {
11795     ucv = ucx;
11796     ucx = ucx > uce ? uce : ucx;
11797   }
11798 #pragma omp atomic compare capture relaxed
11799   {
11800     ucv = ucx;
11801     ucx = ucx < uce ? uce : ucx;
11802   }
11803 #pragma omp atomic compare capture relaxed
11804   {
11805     ucv = ucx;
11806     ucx = ucx == uce ? ucd : ucx;
11807   }
11808 #pragma omp atomic compare capture relaxed
11809   {
11810     ucx = ucx > uce ? uce : ucx;
11811     ucv = ucx;
11812   }
11813 #pragma omp atomic compare capture relaxed
11814   {
11815     ucx = ucx < uce ? uce : ucx;
11816     ucv = ucx;
11817   }
11818 #pragma omp atomic compare capture relaxed
11819   {
11820     ucx = ucx == uce ? ucd : ucx;
11821     ucv = ucx;
11822   }
11823 
11824 #pragma omp atomic compare capture release
11825   {
11826     ucv = ucx;
11827     ucx = ucx > uce ? uce : ucx;
11828   }
11829 #pragma omp atomic compare capture release
11830   {
11831     ucv = ucx;
11832     ucx = ucx < uce ? uce : ucx;
11833   }
11834 #pragma omp atomic compare capture release
11835   {
11836     ucv = ucx;
11837     ucx = ucx == uce ? ucd : ucx;
11838   }
11839 #pragma omp atomic compare capture release
11840   {
11841     ucx = ucx > uce ? uce : ucx;
11842     ucv = ucx;
11843   }
11844 #pragma omp atomic compare capture release
11845   {
11846     ucx = ucx < uce ? uce : ucx;
11847     ucv = ucx;
11848   }
11849 #pragma omp atomic compare capture release
11850   {
11851     ucx = ucx == uce ? ucd : ucx;
11852     ucv = ucx;
11853   }
11854 
11855 #pragma omp atomic compare capture seq_cst
11856   {
11857     ucv = ucx;
11858     ucx = ucx > uce ? uce : ucx;
11859   }
11860 #pragma omp atomic compare capture seq_cst
11861   {
11862     ucv = ucx;
11863     ucx = ucx < uce ? uce : ucx;
11864   }
11865 #pragma omp atomic compare capture seq_cst
11866   {
11867     ucv = ucx;
11868     ucx = ucx == uce ? ucd : ucx;
11869   }
11870 #pragma omp atomic compare capture seq_cst
11871   {
11872     ucx = ucx > uce ? uce : ucx;
11873     ucv = ucx;
11874   }
11875 #pragma omp atomic compare capture seq_cst
11876   {
11877     ucx = ucx < uce ? uce : ucx;
11878     ucv = ucx;
11879   }
11880 #pragma omp atomic compare capture seq_cst
11881   {
11882     ucx = ucx == uce ? ucd : ucx;
11883     ucv = ucx;
11884   }
11885 
11886   return ucv;
11887 }
11888 
sxevd()11889 short sxevd() {
11890   short sx, sv, se, sd;
11891 
11892 #pragma omp atomic compare capture
11893   {
11894     sv = sx;
11895     sx = sx > se ? se : sx;
11896   }
11897 #pragma omp atomic compare capture
11898   {
11899     sv = sx;
11900     sx = sx < se ? se : sx;
11901   }
11902 #pragma omp atomic compare capture
11903   {
11904     sv = sx;
11905     sx = sx == se ? sd : sx;
11906   }
11907 #pragma omp atomic compare capture
11908   {
11909     sx = sx > se ? se : sx;
11910     sv = sx;
11911   }
11912 #pragma omp atomic compare capture
11913   {
11914     sx = sx < se ? se : sx;
11915     sv = sx;
11916   }
11917 #pragma omp atomic compare capture
11918   {
11919     sx = sx == se ? sd : sx;
11920     sv = sx;
11921   }
11922 
11923 #pragma omp atomic compare capture acq_rel
11924   {
11925     sv = sx;
11926     sx = sx > se ? se : sx;
11927   }
11928 #pragma omp atomic compare capture acq_rel
11929   {
11930     sv = sx;
11931     sx = sx < se ? se : sx;
11932   }
11933 #pragma omp atomic compare capture acq_rel
11934   {
11935     sv = sx;
11936     sx = sx == se ? sd : sx;
11937   }
11938 #pragma omp atomic compare capture acq_rel
11939   {
11940     sx = sx > se ? se : sx;
11941     sv = sx;
11942   }
11943 #pragma omp atomic compare capture acq_rel
11944   {
11945     sx = sx < se ? se : sx;
11946     sv = sx;
11947   }
11948 #pragma omp atomic compare capture acq_rel
11949   {
11950     sx = sx == se ? sd : sx;
11951     sv = sx;
11952   }
11953 
11954 #pragma omp atomic compare capture acquire
11955   {
11956     sv = sx;
11957     sx = sx > se ? se : sx;
11958   }
11959 #pragma omp atomic compare capture acquire
11960   {
11961     sv = sx;
11962     sx = sx < se ? se : sx;
11963   }
11964 #pragma omp atomic compare capture acquire
11965   {
11966     sv = sx;
11967     sx = sx == se ? sd : sx;
11968   }
11969 #pragma omp atomic compare capture acquire
11970   {
11971     sx = sx > se ? se : sx;
11972     sv = sx;
11973   }
11974 #pragma omp atomic compare capture acquire
11975   {
11976     sx = sx < se ? se : sx;
11977     sv = sx;
11978   }
11979 #pragma omp atomic compare capture acquire
11980   {
11981     sx = sx == se ? sd : sx;
11982     sv = sx;
11983   }
11984 
11985 #pragma omp atomic compare capture relaxed
11986   {
11987     sv = sx;
11988     sx = sx > se ? se : sx;
11989   }
11990 #pragma omp atomic compare capture relaxed
11991   {
11992     sv = sx;
11993     sx = sx < se ? se : sx;
11994   }
11995 #pragma omp atomic compare capture relaxed
11996   {
11997     sv = sx;
11998     sx = sx == se ? sd : sx;
11999   }
12000 #pragma omp atomic compare capture relaxed
12001   {
12002     sx = sx > se ? se : sx;
12003     sv = sx;
12004   }
12005 #pragma omp atomic compare capture relaxed
12006   {
12007     sx = sx < se ? se : sx;
12008     sv = sx;
12009   }
12010 #pragma omp atomic compare capture relaxed
12011   {
12012     sx = sx == se ? sd : sx;
12013     sv = sx;
12014   }
12015 
12016 #pragma omp atomic compare capture release
12017   {
12018     sv = sx;
12019     sx = sx > se ? se : sx;
12020   }
12021 #pragma omp atomic compare capture release
12022   {
12023     sv = sx;
12024     sx = sx < se ? se : sx;
12025   }
12026 #pragma omp atomic compare capture release
12027   {
12028     sv = sx;
12029     sx = sx == se ? sd : sx;
12030   }
12031 #pragma omp atomic compare capture release
12032   {
12033     sx = sx > se ? se : sx;
12034     sv = sx;
12035   }
12036 #pragma omp atomic compare capture release
12037   {
12038     sx = sx < se ? se : sx;
12039     sv = sx;
12040   }
12041 #pragma omp atomic compare capture release
12042   {
12043     sx = sx == se ? sd : sx;
12044     sv = sx;
12045   }
12046 
12047 #pragma omp atomic compare capture seq_cst
12048   {
12049     sv = sx;
12050     sx = sx > se ? se : sx;
12051   }
12052 #pragma omp atomic compare capture seq_cst
12053   {
12054     sv = sx;
12055     sx = sx < se ? se : sx;
12056   }
12057 #pragma omp atomic compare capture seq_cst
12058   {
12059     sv = sx;
12060     sx = sx == se ? sd : sx;
12061   }
12062 #pragma omp atomic compare capture seq_cst
12063   {
12064     sx = sx > se ? se : sx;
12065     sv = sx;
12066   }
12067 #pragma omp atomic compare capture seq_cst
12068   {
12069     sx = sx < se ? se : sx;
12070     sv = sx;
12071   }
12072 #pragma omp atomic compare capture seq_cst
12073   {
12074     sx = sx == se ? sd : sx;
12075     sv = sx;
12076   }
12077 
12078   return sv;
12079 }
12080 
usxevd()12081 unsigned short usxevd() {
12082   unsigned short usx, usv, use, usd;
12083 
12084 #pragma omp atomic compare capture
12085   {
12086     usv = usx;
12087     usx = usx > use ? use : usx;
12088   }
12089 #pragma omp atomic compare capture
12090   {
12091     usv = usx;
12092     usx = usx < use ? use : usx;
12093   }
12094 #pragma omp atomic compare capture
12095   {
12096     usv = usx;
12097     usx = usx == use ? usd : usx;
12098   }
12099 #pragma omp atomic compare capture
12100   {
12101     usx = usx > use ? use : usx;
12102     usv = usx;
12103   }
12104 #pragma omp atomic compare capture
12105   {
12106     usx = usx < use ? use : usx;
12107     usv = usx;
12108   }
12109 #pragma omp atomic compare capture
12110   {
12111     usx = usx == use ? usd : usx;
12112     usv = usx;
12113   }
12114 
12115 #pragma omp atomic compare capture acq_rel
12116   {
12117     usv = usx;
12118     usx = usx > use ? use : usx;
12119   }
12120 #pragma omp atomic compare capture acq_rel
12121   {
12122     usv = usx;
12123     usx = usx < use ? use : usx;
12124   }
12125 #pragma omp atomic compare capture acq_rel
12126   {
12127     usv = usx;
12128     usx = usx == use ? usd : usx;
12129   }
12130 #pragma omp atomic compare capture acq_rel
12131   {
12132     usx = usx > use ? use : usx;
12133     usv = usx;
12134   }
12135 #pragma omp atomic compare capture acq_rel
12136   {
12137     usx = usx < use ? use : usx;
12138     usv = usx;
12139   }
12140 #pragma omp atomic compare capture acq_rel
12141   {
12142     usx = usx == use ? usd : usx;
12143     usv = usx;
12144   }
12145 
12146 #pragma omp atomic compare capture acquire
12147   {
12148     usv = usx;
12149     usx = usx > use ? use : usx;
12150   }
12151 #pragma omp atomic compare capture acquire
12152   {
12153     usv = usx;
12154     usx = usx < use ? use : usx;
12155   }
12156 #pragma omp atomic compare capture acquire
12157   {
12158     usv = usx;
12159     usx = usx == use ? usd : usx;
12160   }
12161 #pragma omp atomic compare capture acquire
12162   {
12163     usx = usx > use ? use : usx;
12164     usv = usx;
12165   }
12166 #pragma omp atomic compare capture acquire
12167   {
12168     usx = usx < use ? use : usx;
12169     usv = usx;
12170   }
12171 #pragma omp atomic compare capture acquire
12172   {
12173     usx = usx == use ? usd : usx;
12174     usv = usx;
12175   }
12176 
12177 #pragma omp atomic compare capture relaxed
12178   {
12179     usv = usx;
12180     usx = usx > use ? use : usx;
12181   }
12182 #pragma omp atomic compare capture relaxed
12183   {
12184     usv = usx;
12185     usx = usx < use ? use : usx;
12186   }
12187 #pragma omp atomic compare capture relaxed
12188   {
12189     usv = usx;
12190     usx = usx == use ? usd : usx;
12191   }
12192 #pragma omp atomic compare capture relaxed
12193   {
12194     usx = usx > use ? use : usx;
12195     usv = usx;
12196   }
12197 #pragma omp atomic compare capture relaxed
12198   {
12199     usx = usx < use ? use : usx;
12200     usv = usx;
12201   }
12202 #pragma omp atomic compare capture relaxed
12203   {
12204     usx = usx == use ? usd : usx;
12205     usv = usx;
12206   }
12207 
12208 #pragma omp atomic compare capture release
12209   {
12210     usv = usx;
12211     usx = usx > use ? use : usx;
12212   }
12213 #pragma omp atomic compare capture release
12214   {
12215     usv = usx;
12216     usx = usx < use ? use : usx;
12217   }
12218 #pragma omp atomic compare capture release
12219   {
12220     usv = usx;
12221     usx = usx == use ? usd : usx;
12222   }
12223 #pragma omp atomic compare capture release
12224   {
12225     usx = usx > use ? use : usx;
12226     usv = usx;
12227   }
12228 #pragma omp atomic compare capture release
12229   {
12230     usx = usx < use ? use : usx;
12231     usv = usx;
12232   }
12233 #pragma omp atomic compare capture release
12234   {
12235     usx = usx == use ? usd : usx;
12236     usv = usx;
12237   }
12238 
12239 #pragma omp atomic compare capture seq_cst
12240   {
12241     usv = usx;
12242     usx = usx > use ? use : usx;
12243   }
12244 #pragma omp atomic compare capture seq_cst
12245   {
12246     usv = usx;
12247     usx = usx < use ? use : usx;
12248   }
12249 #pragma omp atomic compare capture seq_cst
12250   {
12251     usv = usx;
12252     usx = usx == use ? usd : usx;
12253   }
12254 #pragma omp atomic compare capture seq_cst
12255   {
12256     usx = usx > use ? use : usx;
12257     usv = usx;
12258   }
12259 #pragma omp atomic compare capture seq_cst
12260   {
12261     usx = usx < use ? use : usx;
12262     usv = usx;
12263   }
12264 #pragma omp atomic compare capture seq_cst
12265   {
12266     usx = usx == use ? usd : usx;
12267     usv = usx;
12268   }
12269 
12270   return usv;
12271 }
12272 
ixevd()12273 int ixevd() {
12274   int ix, iv, ie, id;
12275 
12276 #pragma omp atomic compare capture
12277   {
12278     iv = ix;
12279     ix = ix > ie ? ie : ix;
12280   }
12281 #pragma omp atomic compare capture
12282   {
12283     iv = ix;
12284     ix = ix < ie ? ie : ix;
12285   }
12286 #pragma omp atomic compare capture
12287   {
12288     iv = ix;
12289     ix = ix == ie ? id : ix;
12290   }
12291 #pragma omp atomic compare capture
12292   {
12293     ix = ix > ie ? ie : ix;
12294     iv = ix;
12295   }
12296 #pragma omp atomic compare capture
12297   {
12298     ix = ix < ie ? ie : ix;
12299     iv = ix;
12300   }
12301 #pragma omp atomic compare capture
12302   {
12303     ix = ix == ie ? id : ix;
12304     iv = ix;
12305   }
12306 
12307 #pragma omp atomic compare capture acq_rel
12308   {
12309     iv = ix;
12310     ix = ix > ie ? ie : ix;
12311   }
12312 #pragma omp atomic compare capture acq_rel
12313   {
12314     iv = ix;
12315     ix = ix < ie ? ie : ix;
12316   }
12317 #pragma omp atomic compare capture acq_rel
12318   {
12319     iv = ix;
12320     ix = ix == ie ? id : ix;
12321   }
12322 #pragma omp atomic compare capture acq_rel
12323   {
12324     ix = ix > ie ? ie : ix;
12325     iv = ix;
12326   }
12327 #pragma omp atomic compare capture acq_rel
12328   {
12329     ix = ix < ie ? ie : ix;
12330     iv = ix;
12331   }
12332 #pragma omp atomic compare capture acq_rel
12333   {
12334     ix = ix == ie ? id : ix;
12335     iv = ix;
12336   }
12337 
12338 #pragma omp atomic compare capture acquire
12339   {
12340     iv = ix;
12341     ix = ix > ie ? ie : ix;
12342   }
12343 #pragma omp atomic compare capture acquire
12344   {
12345     iv = ix;
12346     ix = ix < ie ? ie : ix;
12347   }
12348 #pragma omp atomic compare capture acquire
12349   {
12350     iv = ix;
12351     ix = ix == ie ? id : ix;
12352   }
12353 #pragma omp atomic compare capture acquire
12354   {
12355     ix = ix > ie ? ie : ix;
12356     iv = ix;
12357   }
12358 #pragma omp atomic compare capture acquire
12359   {
12360     ix = ix < ie ? ie : ix;
12361     iv = ix;
12362   }
12363 #pragma omp atomic compare capture acquire
12364   {
12365     ix = ix == ie ? id : ix;
12366     iv = ix;
12367   }
12368 
12369 #pragma omp atomic compare capture relaxed
12370   {
12371     iv = ix;
12372     ix = ix > ie ? ie : ix;
12373   }
12374 #pragma omp atomic compare capture relaxed
12375   {
12376     iv = ix;
12377     ix = ix < ie ? ie : ix;
12378   }
12379 #pragma omp atomic compare capture relaxed
12380   {
12381     iv = ix;
12382     ix = ix == ie ? id : ix;
12383   }
12384 #pragma omp atomic compare capture relaxed
12385   {
12386     ix = ix > ie ? ie : ix;
12387     iv = ix;
12388   }
12389 #pragma omp atomic compare capture relaxed
12390   {
12391     ix = ix < ie ? ie : ix;
12392     iv = ix;
12393   }
12394 #pragma omp atomic compare capture relaxed
12395   {
12396     ix = ix == ie ? id : ix;
12397     iv = ix;
12398   }
12399 
12400 #pragma omp atomic compare capture release
12401   {
12402     iv = ix;
12403     ix = ix > ie ? ie : ix;
12404   }
12405 #pragma omp atomic compare capture release
12406   {
12407     iv = ix;
12408     ix = ix < ie ? ie : ix;
12409   }
12410 #pragma omp atomic compare capture release
12411   {
12412     iv = ix;
12413     ix = ix == ie ? id : ix;
12414   }
12415 #pragma omp atomic compare capture release
12416   {
12417     ix = ix > ie ? ie : ix;
12418     iv = ix;
12419   }
12420 #pragma omp atomic compare capture release
12421   {
12422     ix = ix < ie ? ie : ix;
12423     iv = ix;
12424   }
12425 #pragma omp atomic compare capture release
12426   {
12427     ix = ix == ie ? id : ix;
12428     iv = ix;
12429   }
12430 
12431 #pragma omp atomic compare capture seq_cst
12432   {
12433     iv = ix;
12434     ix = ix > ie ? ie : ix;
12435   }
12436 #pragma omp atomic compare capture seq_cst
12437   {
12438     iv = ix;
12439     ix = ix < ie ? ie : ix;
12440   }
12441 #pragma omp atomic compare capture seq_cst
12442   {
12443     iv = ix;
12444     ix = ix == ie ? id : ix;
12445   }
12446 #pragma omp atomic compare capture seq_cst
12447   {
12448     ix = ix > ie ? ie : ix;
12449     iv = ix;
12450   }
12451 #pragma omp atomic compare capture seq_cst
12452   {
12453     ix = ix < ie ? ie : ix;
12454     iv = ix;
12455   }
12456 #pragma omp atomic compare capture seq_cst
12457   {
12458     ix = ix == ie ? id : ix;
12459     iv = ix;
12460   }
12461 
12462   return iv;
12463 }
12464 
uixevd()12465 unsigned int uixevd() {
12466   unsigned int uix, uiv, uie, uid;
12467 
12468 #pragma omp atomic compare capture
12469   {
12470     uiv = uix;
12471     uix = uix > uie ? uie : uix;
12472   }
12473 #pragma omp atomic compare capture
12474   {
12475     uiv = uix;
12476     uix = uix < uie ? uie : uix;
12477   }
12478 #pragma omp atomic compare capture
12479   {
12480     uiv = uix;
12481     uix = uix == uie ? uid : uix;
12482   }
12483 #pragma omp atomic compare capture
12484   {
12485     uix = uix > uie ? uie : uix;
12486     uiv = uix;
12487   }
12488 #pragma omp atomic compare capture
12489   {
12490     uix = uix < uie ? uie : uix;
12491     uiv = uix;
12492   }
12493 #pragma omp atomic compare capture
12494   {
12495     uix = uix == uie ? uid : uix;
12496     uiv = uix;
12497   }
12498 
12499 #pragma omp atomic compare capture acq_rel
12500   {
12501     uiv = uix;
12502     uix = uix > uie ? uie : uix;
12503   }
12504 #pragma omp atomic compare capture acq_rel
12505   {
12506     uiv = uix;
12507     uix = uix < uie ? uie : uix;
12508   }
12509 #pragma omp atomic compare capture acq_rel
12510   {
12511     uiv = uix;
12512     uix = uix == uie ? uid : uix;
12513   }
12514 #pragma omp atomic compare capture acq_rel
12515   {
12516     uix = uix > uie ? uie : uix;
12517     uiv = uix;
12518   }
12519 #pragma omp atomic compare capture acq_rel
12520   {
12521     uix = uix < uie ? uie : uix;
12522     uiv = uix;
12523   }
12524 #pragma omp atomic compare capture acq_rel
12525   {
12526     uix = uix == uie ? uid : uix;
12527     uiv = uix;
12528   }
12529 
12530 #pragma omp atomic compare capture acquire
12531   {
12532     uiv = uix;
12533     uix = uix > uie ? uie : uix;
12534   }
12535 #pragma omp atomic compare capture acquire
12536   {
12537     uiv = uix;
12538     uix = uix < uie ? uie : uix;
12539   }
12540 #pragma omp atomic compare capture acquire
12541   {
12542     uiv = uix;
12543     uix = uix == uie ? uid : uix;
12544   }
12545 #pragma omp atomic compare capture acquire
12546   {
12547     uix = uix > uie ? uie : uix;
12548     uiv = uix;
12549   }
12550 #pragma omp atomic compare capture acquire
12551   {
12552     uix = uix < uie ? uie : uix;
12553     uiv = uix;
12554   }
12555 #pragma omp atomic compare capture acquire
12556   {
12557     uix = uix == uie ? uid : uix;
12558     uiv = uix;
12559   }
12560 
12561 #pragma omp atomic compare capture relaxed
12562   {
12563     uiv = uix;
12564     uix = uix > uie ? uie : uix;
12565   }
12566 #pragma omp atomic compare capture relaxed
12567   {
12568     uiv = uix;
12569     uix = uix < uie ? uie : uix;
12570   }
12571 #pragma omp atomic compare capture relaxed
12572   {
12573     uiv = uix;
12574     uix = uix == uie ? uid : uix;
12575   }
12576 #pragma omp atomic compare capture relaxed
12577   {
12578     uix = uix > uie ? uie : uix;
12579     uiv = uix;
12580   }
12581 #pragma omp atomic compare capture relaxed
12582   {
12583     uix = uix < uie ? uie : uix;
12584     uiv = uix;
12585   }
12586 #pragma omp atomic compare capture relaxed
12587   {
12588     uix = uix == uie ? uid : uix;
12589     uiv = uix;
12590   }
12591 
12592 #pragma omp atomic compare capture release
12593   {
12594     uiv = uix;
12595     uix = uix > uie ? uie : uix;
12596   }
12597 #pragma omp atomic compare capture release
12598   {
12599     uiv = uix;
12600     uix = uix < uie ? uie : uix;
12601   }
12602 #pragma omp atomic compare capture release
12603   {
12604     uiv = uix;
12605     uix = uix == uie ? uid : uix;
12606   }
12607 #pragma omp atomic compare capture release
12608   {
12609     uix = uix > uie ? uie : uix;
12610     uiv = uix;
12611   }
12612 #pragma omp atomic compare capture release
12613   {
12614     uix = uix < uie ? uie : uix;
12615     uiv = uix;
12616   }
12617 #pragma omp atomic compare capture release
12618   {
12619     uix = uix == uie ? uid : uix;
12620     uiv = uix;
12621   }
12622 
12623 #pragma omp atomic compare capture seq_cst
12624   {
12625     uiv = uix;
12626     uix = uix > uie ? uie : uix;
12627   }
12628 #pragma omp atomic compare capture seq_cst
12629   {
12630     uiv = uix;
12631     uix = uix < uie ? uie : uix;
12632   }
12633 #pragma omp atomic compare capture seq_cst
12634   {
12635     uiv = uix;
12636     uix = uix == uie ? uid : uix;
12637   }
12638 #pragma omp atomic compare capture seq_cst
12639   {
12640     uix = uix > uie ? uie : uix;
12641     uiv = uix;
12642   }
12643 #pragma omp atomic compare capture seq_cst
12644   {
12645     uix = uix < uie ? uie : uix;
12646     uiv = uix;
12647   }
12648 #pragma omp atomic compare capture seq_cst
12649   {
12650     uix = uix == uie ? uid : uix;
12651     uiv = uix;
12652   }
12653 
12654   return uiv;
12655 }
12656 
lxevd()12657 long lxevd() {
12658   long lx, lv, le, ld;
12659 
12660 #pragma omp atomic compare capture
12661   {
12662     lv = lx;
12663     lx = lx > le ? le : lx;
12664   }
12665 #pragma omp atomic compare capture
12666   {
12667     lv = lx;
12668     lx = lx < le ? le : lx;
12669   }
12670 #pragma omp atomic compare capture
12671   {
12672     lv = lx;
12673     lx = lx == le ? ld : lx;
12674   }
12675 #pragma omp atomic compare capture
12676   {
12677     lx = lx > le ? le : lx;
12678     lv = lx;
12679   }
12680 #pragma omp atomic compare capture
12681   {
12682     lx = lx < le ? le : lx;
12683     lv = lx;
12684   }
12685 #pragma omp atomic compare capture
12686   {
12687     lx = lx == le ? ld : lx;
12688     lv = lx;
12689   }
12690 
12691 #pragma omp atomic compare capture acq_rel
12692   {
12693     lv = lx;
12694     lx = lx > le ? le : lx;
12695   }
12696 #pragma omp atomic compare capture acq_rel
12697   {
12698     lv = lx;
12699     lx = lx < le ? le : lx;
12700   }
12701 #pragma omp atomic compare capture acq_rel
12702   {
12703     lv = lx;
12704     lx = lx == le ? ld : lx;
12705   }
12706 #pragma omp atomic compare capture acq_rel
12707   {
12708     lx = lx > le ? le : lx;
12709     lv = lx;
12710   }
12711 #pragma omp atomic compare capture acq_rel
12712   {
12713     lx = lx < le ? le : lx;
12714     lv = lx;
12715   }
12716 #pragma omp atomic compare capture acq_rel
12717   {
12718     lx = lx == le ? ld : lx;
12719     lv = lx;
12720   }
12721 
12722 #pragma omp atomic compare capture acquire
12723   {
12724     lv = lx;
12725     lx = lx > le ? le : lx;
12726   }
12727 #pragma omp atomic compare capture acquire
12728   {
12729     lv = lx;
12730     lx = lx < le ? le : lx;
12731   }
12732 #pragma omp atomic compare capture acquire
12733   {
12734     lv = lx;
12735     lx = lx == le ? ld : lx;
12736   }
12737 #pragma omp atomic compare capture acquire
12738   {
12739     lx = lx > le ? le : lx;
12740     lv = lx;
12741   }
12742 #pragma omp atomic compare capture acquire
12743   {
12744     lx = lx < le ? le : lx;
12745     lv = lx;
12746   }
12747 #pragma omp atomic compare capture acquire
12748   {
12749     lx = lx == le ? ld : lx;
12750     lv = lx;
12751   }
12752 
12753 #pragma omp atomic compare capture relaxed
12754   {
12755     lv = lx;
12756     lx = lx > le ? le : lx;
12757   }
12758 #pragma omp atomic compare capture relaxed
12759   {
12760     lv = lx;
12761     lx = lx < le ? le : lx;
12762   }
12763 #pragma omp atomic compare capture relaxed
12764   {
12765     lv = lx;
12766     lx = lx == le ? ld : lx;
12767   }
12768 #pragma omp atomic compare capture relaxed
12769   {
12770     lx = lx > le ? le : lx;
12771     lv = lx;
12772   }
12773 #pragma omp atomic compare capture relaxed
12774   {
12775     lx = lx < le ? le : lx;
12776     lv = lx;
12777   }
12778 #pragma omp atomic compare capture relaxed
12779   {
12780     lx = lx == le ? ld : lx;
12781     lv = lx;
12782   }
12783 
12784 #pragma omp atomic compare capture release
12785   {
12786     lv = lx;
12787     lx = lx > le ? le : lx;
12788   }
12789 #pragma omp atomic compare capture release
12790   {
12791     lv = lx;
12792     lx = lx < le ? le : lx;
12793   }
12794 #pragma omp atomic compare capture release
12795   {
12796     lv = lx;
12797     lx = lx == le ? ld : lx;
12798   }
12799 #pragma omp atomic compare capture release
12800   {
12801     lx = lx > le ? le : lx;
12802     lv = lx;
12803   }
12804 #pragma omp atomic compare capture release
12805   {
12806     lx = lx < le ? le : lx;
12807     lv = lx;
12808   }
12809 #pragma omp atomic compare capture release
12810   {
12811     lx = lx == le ? ld : lx;
12812     lv = lx;
12813   }
12814 
12815 #pragma omp atomic compare capture seq_cst
12816   {
12817     lv = lx;
12818     lx = lx > le ? le : lx;
12819   }
12820 #pragma omp atomic compare capture seq_cst
12821   {
12822     lv = lx;
12823     lx = lx < le ? le : lx;
12824   }
12825 #pragma omp atomic compare capture seq_cst
12826   {
12827     lv = lx;
12828     lx = lx == le ? ld : lx;
12829   }
12830 #pragma omp atomic compare capture seq_cst
12831   {
12832     lx = lx > le ? le : lx;
12833     lv = lx;
12834   }
12835 #pragma omp atomic compare capture seq_cst
12836   {
12837     lx = lx < le ? le : lx;
12838     lv = lx;
12839   }
12840 #pragma omp atomic compare capture seq_cst
12841   {
12842     lx = lx == le ? ld : lx;
12843     lv = lx;
12844   }
12845 
12846   return lv;
12847 }
12848 
ulxevd()12849 unsigned long ulxevd() {
12850   unsigned long ulx, ulv, ule, uld;
12851 
12852 #pragma omp atomic compare capture
12853   {
12854     ulv = ulx;
12855     ulx = ulx > ule ? ule : ulx;
12856   }
12857 #pragma omp atomic compare capture
12858   {
12859     ulv = ulx;
12860     ulx = ulx < ule ? ule : ulx;
12861   }
12862 #pragma omp atomic compare capture
12863   {
12864     ulv = ulx;
12865     ulx = ulx == ule ? uld : ulx;
12866   }
12867 #pragma omp atomic compare capture
12868   {
12869     ulx = ulx > ule ? ule : ulx;
12870     ulv = ulx;
12871   }
12872 #pragma omp atomic compare capture
12873   {
12874     ulx = ulx < ule ? ule : ulx;
12875     ulv = ulx;
12876   }
12877 #pragma omp atomic compare capture
12878   {
12879     ulx = ulx == ule ? uld : ulx;
12880     ulv = ulx;
12881   }
12882 
12883 #pragma omp atomic compare capture acq_rel
12884   {
12885     ulv = ulx;
12886     ulx = ulx > ule ? ule : ulx;
12887   }
12888 #pragma omp atomic compare capture acq_rel
12889   {
12890     ulv = ulx;
12891     ulx = ulx < ule ? ule : ulx;
12892   }
12893 #pragma omp atomic compare capture acq_rel
12894   {
12895     ulv = ulx;
12896     ulx = ulx == ule ? uld : ulx;
12897   }
12898 #pragma omp atomic compare capture acq_rel
12899   {
12900     ulx = ulx > ule ? ule : ulx;
12901     ulv = ulx;
12902   }
12903 #pragma omp atomic compare capture acq_rel
12904   {
12905     ulx = ulx < ule ? ule : ulx;
12906     ulv = ulx;
12907   }
12908 #pragma omp atomic compare capture acq_rel
12909   {
12910     ulx = ulx == ule ? uld : ulx;
12911     ulv = ulx;
12912   }
12913 
12914 #pragma omp atomic compare capture acquire
12915   {
12916     ulv = ulx;
12917     ulx = ulx > ule ? ule : ulx;
12918   }
12919 #pragma omp atomic compare capture acquire
12920   {
12921     ulv = ulx;
12922     ulx = ulx < ule ? ule : ulx;
12923   }
12924 #pragma omp atomic compare capture acquire
12925   {
12926     ulv = ulx;
12927     ulx = ulx == ule ? uld : ulx;
12928   }
12929 #pragma omp atomic compare capture acquire
12930   {
12931     ulx = ulx > ule ? ule : ulx;
12932     ulv = ulx;
12933   }
12934 #pragma omp atomic compare capture acquire
12935   {
12936     ulx = ulx < ule ? ule : ulx;
12937     ulv = ulx;
12938   }
12939 #pragma omp atomic compare capture acquire
12940   {
12941     ulx = ulx == ule ? uld : ulx;
12942     ulv = ulx;
12943   }
12944 
12945 #pragma omp atomic compare capture relaxed
12946   {
12947     ulv = ulx;
12948     ulx = ulx > ule ? ule : ulx;
12949   }
12950 #pragma omp atomic compare capture relaxed
12951   {
12952     ulv = ulx;
12953     ulx = ulx < ule ? ule : ulx;
12954   }
12955 #pragma omp atomic compare capture relaxed
12956   {
12957     ulv = ulx;
12958     ulx = ulx == ule ? uld : ulx;
12959   }
12960 #pragma omp atomic compare capture relaxed
12961   {
12962     ulx = ulx > ule ? ule : ulx;
12963     ulv = ulx;
12964   }
12965 #pragma omp atomic compare capture relaxed
12966   {
12967     ulx = ulx < ule ? ule : ulx;
12968     ulv = ulx;
12969   }
12970 #pragma omp atomic compare capture relaxed
12971   {
12972     ulx = ulx == ule ? uld : ulx;
12973     ulv = ulx;
12974   }
12975 
12976 #pragma omp atomic compare capture release
12977   {
12978     ulv = ulx;
12979     ulx = ulx > ule ? ule : ulx;
12980   }
12981 #pragma omp atomic compare capture release
12982   {
12983     ulv = ulx;
12984     ulx = ulx < ule ? ule : ulx;
12985   }
12986 #pragma omp atomic compare capture release
12987   {
12988     ulv = ulx;
12989     ulx = ulx == ule ? uld : ulx;
12990   }
12991 #pragma omp atomic compare capture release
12992   {
12993     ulx = ulx > ule ? ule : ulx;
12994     ulv = ulx;
12995   }
12996 #pragma omp atomic compare capture release
12997   {
12998     ulx = ulx < ule ? ule : ulx;
12999     ulv = ulx;
13000   }
13001 #pragma omp atomic compare capture release
13002   {
13003     ulx = ulx == ule ? uld : ulx;
13004     ulv = ulx;
13005   }
13006 
13007 #pragma omp atomic compare capture seq_cst
13008   {
13009     ulv = ulx;
13010     ulx = ulx > ule ? ule : ulx;
13011   }
13012 #pragma omp atomic compare capture seq_cst
13013   {
13014     ulv = ulx;
13015     ulx = ulx < ule ? ule : ulx;
13016   }
13017 #pragma omp atomic compare capture seq_cst
13018   {
13019     ulv = ulx;
13020     ulx = ulx == ule ? uld : ulx;
13021   }
13022 #pragma omp atomic compare capture seq_cst
13023   {
13024     ulx = ulx > ule ? ule : ulx;
13025     ulv = ulx;
13026   }
13027 #pragma omp atomic compare capture seq_cst
13028   {
13029     ulx = ulx < ule ? ule : ulx;
13030     ulv = ulx;
13031   }
13032 #pragma omp atomic compare capture seq_cst
13033   {
13034     ulx = ulx == ule ? uld : ulx;
13035     ulv = ulx;
13036   }
13037 
13038   return ulv;
13039 }
13040 
llxevd()13041 long long llxevd() {
13042   long long llx, llv, lle, lld;
13043 
13044 #pragma omp atomic compare capture
13045   {
13046     llv = llx;
13047     llx = llx > lle ? lle : llx;
13048   }
13049 #pragma omp atomic compare capture
13050   {
13051     llv = llx;
13052     llx = llx < lle ? lle : llx;
13053   }
13054 #pragma omp atomic compare capture
13055   {
13056     llv = llx;
13057     llx = llx == lle ? lld : llx;
13058   }
13059 #pragma omp atomic compare capture
13060   {
13061     llx = llx > lle ? lle : llx;
13062     llv = llx;
13063   }
13064 #pragma omp atomic compare capture
13065   {
13066     llx = llx < lle ? lle : llx;
13067     llv = llx;
13068   }
13069 #pragma omp atomic compare capture
13070   {
13071     llx = llx == lle ? lld : llx;
13072     llv = llx;
13073   }
13074 
13075 #pragma omp atomic compare capture acq_rel
13076   {
13077     llv = llx;
13078     llx = llx > lle ? lle : llx;
13079   }
13080 #pragma omp atomic compare capture acq_rel
13081   {
13082     llv = llx;
13083     llx = llx < lle ? lle : llx;
13084   }
13085 #pragma omp atomic compare capture acq_rel
13086   {
13087     llv = llx;
13088     llx = llx == lle ? lld : llx;
13089   }
13090 #pragma omp atomic compare capture acq_rel
13091   {
13092     llx = llx > lle ? lle : llx;
13093     llv = llx;
13094   }
13095 #pragma omp atomic compare capture acq_rel
13096   {
13097     llx = llx < lle ? lle : llx;
13098     llv = llx;
13099   }
13100 #pragma omp atomic compare capture acq_rel
13101   {
13102     llx = llx == lle ? lld : llx;
13103     llv = llx;
13104   }
13105 
13106 #pragma omp atomic compare capture acquire
13107   {
13108     llv = llx;
13109     llx = llx > lle ? lle : llx;
13110   }
13111 #pragma omp atomic compare capture acquire
13112   {
13113     llv = llx;
13114     llx = llx < lle ? lle : llx;
13115   }
13116 #pragma omp atomic compare capture acquire
13117   {
13118     llv = llx;
13119     llx = llx == lle ? lld : llx;
13120   }
13121 #pragma omp atomic compare capture acquire
13122   {
13123     llx = llx > lle ? lle : llx;
13124     llv = llx;
13125   }
13126 #pragma omp atomic compare capture acquire
13127   {
13128     llx = llx < lle ? lle : llx;
13129     llv = llx;
13130   }
13131 #pragma omp atomic compare capture acquire
13132   {
13133     llx = llx == lle ? lld : llx;
13134     llv = llx;
13135   }
13136 
13137 #pragma omp atomic compare capture relaxed
13138   {
13139     llv = llx;
13140     llx = llx > lle ? lle : llx;
13141   }
13142 #pragma omp atomic compare capture relaxed
13143   {
13144     llv = llx;
13145     llx = llx < lle ? lle : llx;
13146   }
13147 #pragma omp atomic compare capture relaxed
13148   {
13149     llv = llx;
13150     llx = llx == lle ? lld : llx;
13151   }
13152 #pragma omp atomic compare capture relaxed
13153   {
13154     llx = llx > lle ? lle : llx;
13155     llv = llx;
13156   }
13157 #pragma omp atomic compare capture relaxed
13158   {
13159     llx = llx < lle ? lle : llx;
13160     llv = llx;
13161   }
13162 #pragma omp atomic compare capture relaxed
13163   {
13164     llx = llx == lle ? lld : llx;
13165     llv = llx;
13166   }
13167 
13168 #pragma omp atomic compare capture release
13169   {
13170     llv = llx;
13171     llx = llx > lle ? lle : llx;
13172   }
13173 #pragma omp atomic compare capture release
13174   {
13175     llv = llx;
13176     llx = llx < lle ? lle : llx;
13177   }
13178 #pragma omp atomic compare capture release
13179   {
13180     llv = llx;
13181     llx = llx == lle ? lld : llx;
13182   }
13183 #pragma omp atomic compare capture release
13184   {
13185     llx = llx > lle ? lle : llx;
13186     llv = llx;
13187   }
13188 #pragma omp atomic compare capture release
13189   {
13190     llx = llx < lle ? lle : llx;
13191     llv = llx;
13192   }
13193 #pragma omp atomic compare capture release
13194   {
13195     llx = llx == lle ? lld : llx;
13196     llv = llx;
13197   }
13198 
13199 #pragma omp atomic compare capture seq_cst
13200   {
13201     llv = llx;
13202     llx = llx > lle ? lle : llx;
13203   }
13204 #pragma omp atomic compare capture seq_cst
13205   {
13206     llv = llx;
13207     llx = llx < lle ? lle : llx;
13208   }
13209 #pragma omp atomic compare capture seq_cst
13210   {
13211     llv = llx;
13212     llx = llx == lle ? lld : llx;
13213   }
13214 #pragma omp atomic compare capture seq_cst
13215   {
13216     llx = llx > lle ? lle : llx;
13217     llv = llx;
13218   }
13219 #pragma omp atomic compare capture seq_cst
13220   {
13221     llx = llx < lle ? lle : llx;
13222     llv = llx;
13223   }
13224 #pragma omp atomic compare capture seq_cst
13225   {
13226     llx = llx == lle ? lld : llx;
13227     llv = llx;
13228   }
13229 
13230   return llv;
13231 }
13232 
ullxevd()13233 unsigned long long ullxevd() {
13234   unsigned long long ullx, ullv, ulle, ulld;
13235 
13236 #pragma omp atomic compare capture
13237   {
13238     ullv = ullx;
13239     ullx = ullx > ulle ? ulle : ullx;
13240   }
13241 #pragma omp atomic compare capture
13242   {
13243     ullv = ullx;
13244     ullx = ullx < ulle ? ulle : ullx;
13245   }
13246 #pragma omp atomic compare capture
13247   {
13248     ullv = ullx;
13249     ullx = ullx == ulle ? ulld : ullx;
13250   }
13251 #pragma omp atomic compare capture
13252   {
13253     ullx = ullx > ulle ? ulle : ullx;
13254     ullv = ullx;
13255   }
13256 #pragma omp atomic compare capture
13257   {
13258     ullx = ullx < ulle ? ulle : ullx;
13259     ullv = ullx;
13260   }
13261 #pragma omp atomic compare capture
13262   {
13263     ullx = ullx == ulle ? ulld : ullx;
13264     ullv = ullx;
13265   }
13266 
13267 #pragma omp atomic compare capture acq_rel
13268   {
13269     ullv = ullx;
13270     ullx = ullx > ulle ? ulle : ullx;
13271   }
13272 #pragma omp atomic compare capture acq_rel
13273   {
13274     ullv = ullx;
13275     ullx = ullx < ulle ? ulle : ullx;
13276   }
13277 #pragma omp atomic compare capture acq_rel
13278   {
13279     ullv = ullx;
13280     ullx = ullx == ulle ? ulld : ullx;
13281   }
13282 #pragma omp atomic compare capture acq_rel
13283   {
13284     ullx = ullx > ulle ? ulle : ullx;
13285     ullv = ullx;
13286   }
13287 #pragma omp atomic compare capture acq_rel
13288   {
13289     ullx = ullx < ulle ? ulle : ullx;
13290     ullv = ullx;
13291   }
13292 #pragma omp atomic compare capture acq_rel
13293   {
13294     ullx = ullx == ulle ? ulld : ullx;
13295     ullv = ullx;
13296   }
13297 
13298 #pragma omp atomic compare capture acquire
13299   {
13300     ullv = ullx;
13301     ullx = ullx > ulle ? ulle : ullx;
13302   }
13303 #pragma omp atomic compare capture acquire
13304   {
13305     ullv = ullx;
13306     ullx = ullx < ulle ? ulle : ullx;
13307   }
13308 #pragma omp atomic compare capture acquire
13309   {
13310     ullv = ullx;
13311     ullx = ullx == ulle ? ulld : ullx;
13312   }
13313 #pragma omp atomic compare capture acquire
13314   {
13315     ullx = ullx > ulle ? ulle : ullx;
13316     ullv = ullx;
13317   }
13318 #pragma omp atomic compare capture acquire
13319   {
13320     ullx = ullx < ulle ? ulle : ullx;
13321     ullv = ullx;
13322   }
13323 #pragma omp atomic compare capture acquire
13324   {
13325     ullx = ullx == ulle ? ulld : ullx;
13326     ullv = ullx;
13327   }
13328 
13329 #pragma omp atomic compare capture relaxed
13330   {
13331     ullv = ullx;
13332     ullx = ullx > ulle ? ulle : ullx;
13333   }
13334 #pragma omp atomic compare capture relaxed
13335   {
13336     ullv = ullx;
13337     ullx = ullx < ulle ? ulle : ullx;
13338   }
13339 #pragma omp atomic compare capture relaxed
13340   {
13341     ullv = ullx;
13342     ullx = ullx == ulle ? ulld : ullx;
13343   }
13344 #pragma omp atomic compare capture relaxed
13345   {
13346     ullx = ullx > ulle ? ulle : ullx;
13347     ullv = ullx;
13348   }
13349 #pragma omp atomic compare capture relaxed
13350   {
13351     ullx = ullx < ulle ? ulle : ullx;
13352     ullv = ullx;
13353   }
13354 #pragma omp atomic compare capture relaxed
13355   {
13356     ullx = ullx == ulle ? ulld : ullx;
13357     ullv = ullx;
13358   }
13359 
13360 #pragma omp atomic compare capture release
13361   {
13362     ullv = ullx;
13363     ullx = ullx > ulle ? ulle : ullx;
13364   }
13365 #pragma omp atomic compare capture release
13366   {
13367     ullv = ullx;
13368     ullx = ullx < ulle ? ulle : ullx;
13369   }
13370 #pragma omp atomic compare capture release
13371   {
13372     ullv = ullx;
13373     ullx = ullx == ulle ? ulld : ullx;
13374   }
13375 #pragma omp atomic compare capture release
13376   {
13377     ullx = ullx > ulle ? ulle : ullx;
13378     ullv = ullx;
13379   }
13380 #pragma omp atomic compare capture release
13381   {
13382     ullx = ullx < ulle ? ulle : ullx;
13383     ullv = ullx;
13384   }
13385 #pragma omp atomic compare capture release
13386   {
13387     ullx = ullx == ulle ? ulld : ullx;
13388     ullv = ullx;
13389   }
13390 
13391 #pragma omp atomic compare capture seq_cst
13392   {
13393     ullv = ullx;
13394     ullx = ullx > ulle ? ulle : ullx;
13395   }
13396 #pragma omp atomic compare capture seq_cst
13397   {
13398     ullv = ullx;
13399     ullx = ullx < ulle ? ulle : ullx;
13400   }
13401 #pragma omp atomic compare capture seq_cst
13402   {
13403     ullv = ullx;
13404     ullx = ullx == ulle ? ulld : ullx;
13405   }
13406 #pragma omp atomic compare capture seq_cst
13407   {
13408     ullx = ullx > ulle ? ulle : ullx;
13409     ullv = ullx;
13410   }
13411 #pragma omp atomic compare capture seq_cst
13412   {
13413     ullx = ullx < ulle ? ulle : ullx;
13414     ullv = ullx;
13415   }
13416 #pragma omp atomic compare capture seq_cst
13417   {
13418     ullx = ullx == ulle ? ulld : ullx;
13419     ullv = ullx;
13420   }
13421 
13422   return ullv;
13423 }
13424 
fxevd()13425 float fxevd() {
13426   float fx, fv, fe, fd;
13427 
13428 #pragma omp atomic compare capture
13429   {
13430     fv = fx;
13431     fx = fx > fe ? fe : fx;
13432   }
13433 #pragma omp atomic compare capture
13434   {
13435     fv = fx;
13436     fx = fx < fe ? fe : fx;
13437   }
13438 #pragma omp atomic compare capture
13439   {
13440     fv = fx;
13441     fx = fx == fe ? fd : fx;
13442   }
13443 #pragma omp atomic compare capture
13444   {
13445     fx = fx > fe ? fe : fx;
13446     fv = fx;
13447   }
13448 #pragma omp atomic compare capture
13449   {
13450     fx = fx < fe ? fe : fx;
13451     fv = fx;
13452   }
13453 #pragma omp atomic compare capture
13454   {
13455     fx = fx == fe ? fd : fx;
13456     fv = fx;
13457   }
13458 
13459 #pragma omp atomic compare capture acq_rel
13460   {
13461     fv = fx;
13462     fx = fx > fe ? fe : fx;
13463   }
13464 #pragma omp atomic compare capture acq_rel
13465   {
13466     fv = fx;
13467     fx = fx < fe ? fe : fx;
13468   }
13469 #pragma omp atomic compare capture acq_rel
13470   {
13471     fv = fx;
13472     fx = fx == fe ? fd : fx;
13473   }
13474 #pragma omp atomic compare capture acq_rel
13475   {
13476     fx = fx > fe ? fe : fx;
13477     fv = fx;
13478   }
13479 #pragma omp atomic compare capture acq_rel
13480   {
13481     fx = fx < fe ? fe : fx;
13482     fv = fx;
13483   }
13484 #pragma omp atomic compare capture acq_rel
13485   {
13486     fx = fx == fe ? fd : fx;
13487     fv = fx;
13488   }
13489 
13490 #pragma omp atomic compare capture acquire
13491   {
13492     fv = fx;
13493     fx = fx > fe ? fe : fx;
13494   }
13495 #pragma omp atomic compare capture acquire
13496   {
13497     fv = fx;
13498     fx = fx < fe ? fe : fx;
13499   }
13500 #pragma omp atomic compare capture acquire
13501   {
13502     fv = fx;
13503     fx = fx == fe ? fd : fx;
13504   }
13505 #pragma omp atomic compare capture acquire
13506   {
13507     fx = fx > fe ? fe : fx;
13508     fv = fx;
13509   }
13510 #pragma omp atomic compare capture acquire
13511   {
13512     fx = fx < fe ? fe : fx;
13513     fv = fx;
13514   }
13515 #pragma omp atomic compare capture acquire
13516   {
13517     fx = fx == fe ? fd : fx;
13518     fv = fx;
13519   }
13520 
13521 #pragma omp atomic compare capture relaxed
13522   {
13523     fv = fx;
13524     fx = fx > fe ? fe : fx;
13525   }
13526 #pragma omp atomic compare capture relaxed
13527   {
13528     fv = fx;
13529     fx = fx < fe ? fe : fx;
13530   }
13531 #pragma omp atomic compare capture relaxed
13532   {
13533     fv = fx;
13534     fx = fx == fe ? fd : fx;
13535   }
13536 #pragma omp atomic compare capture relaxed
13537   {
13538     fx = fx > fe ? fe : fx;
13539     fv = fx;
13540   }
13541 #pragma omp atomic compare capture relaxed
13542   {
13543     fx = fx < fe ? fe : fx;
13544     fv = fx;
13545   }
13546 #pragma omp atomic compare capture relaxed
13547   {
13548     fx = fx == fe ? fd : fx;
13549     fv = fx;
13550   }
13551 
13552 #pragma omp atomic compare capture release
13553   {
13554     fv = fx;
13555     fx = fx > fe ? fe : fx;
13556   }
13557 #pragma omp atomic compare capture release
13558   {
13559     fv = fx;
13560     fx = fx < fe ? fe : fx;
13561   }
13562 #pragma omp atomic compare capture release
13563   {
13564     fv = fx;
13565     fx = fx == fe ? fd : fx;
13566   }
13567 #pragma omp atomic compare capture release
13568   {
13569     fx = fx > fe ? fe : fx;
13570     fv = fx;
13571   }
13572 #pragma omp atomic compare capture release
13573   {
13574     fx = fx < fe ? fe : fx;
13575     fv = fx;
13576   }
13577 #pragma omp atomic compare capture release
13578   {
13579     fx = fx == fe ? fd : fx;
13580     fv = fx;
13581   }
13582 
13583 #pragma omp atomic compare capture seq_cst
13584   {
13585     fv = fx;
13586     fx = fx > fe ? fe : fx;
13587   }
13588 #pragma omp atomic compare capture seq_cst
13589   {
13590     fv = fx;
13591     fx = fx < fe ? fe : fx;
13592   }
13593 #pragma omp atomic compare capture seq_cst
13594   {
13595     fv = fx;
13596     fx = fx == fe ? fd : fx;
13597   }
13598 #pragma omp atomic compare capture seq_cst
13599   {
13600     fx = fx > fe ? fe : fx;
13601     fv = fx;
13602   }
13603 #pragma omp atomic compare capture seq_cst
13604   {
13605     fx = fx < fe ? fe : fx;
13606     fv = fx;
13607   }
13608 #pragma omp atomic compare capture seq_cst
13609   {
13610     fx = fx == fe ? fd : fx;
13611     fv = fx;
13612   }
13613 
13614   return fv;
13615 }
13616 
dxevd()13617 double dxevd() {
13618   double dx, dv, de, dd;
13619 
13620 #pragma omp atomic compare capture
13621   {
13622     dv = dx;
13623     dx = dx > de ? de : dx;
13624   }
13625 #pragma omp atomic compare capture
13626   {
13627     dv = dx;
13628     dx = dx < de ? de : dx;
13629   }
13630 #pragma omp atomic compare capture
13631   {
13632     dv = dx;
13633     dx = dx == de ? dd : dx;
13634   }
13635 #pragma omp atomic compare capture
13636   {
13637     dx = dx > de ? de : dx;
13638     dv = dx;
13639   }
13640 #pragma omp atomic compare capture
13641   {
13642     dx = dx < de ? de : dx;
13643     dv = dx;
13644   }
13645 #pragma omp atomic compare capture
13646   {
13647     dx = dx == de ? dd : dx;
13648     dv = dx;
13649   }
13650 
13651 #pragma omp atomic compare capture acq_rel
13652   {
13653     dv = dx;
13654     dx = dx > de ? de : dx;
13655   }
13656 #pragma omp atomic compare capture acq_rel
13657   {
13658     dv = dx;
13659     dx = dx < de ? de : dx;
13660   }
13661 #pragma omp atomic compare capture acq_rel
13662   {
13663     dv = dx;
13664     dx = dx == de ? dd : dx;
13665   }
13666 #pragma omp atomic compare capture acq_rel
13667   {
13668     dx = dx > de ? de : dx;
13669     dv = dx;
13670   }
13671 #pragma omp atomic compare capture acq_rel
13672   {
13673     dx = dx < de ? de : dx;
13674     dv = dx;
13675   }
13676 #pragma omp atomic compare capture acq_rel
13677   {
13678     dx = dx == de ? dd : dx;
13679     dv = dx;
13680   }
13681 
13682 #pragma omp atomic compare capture acquire
13683   {
13684     dv = dx;
13685     dx = dx > de ? de : dx;
13686   }
13687 #pragma omp atomic compare capture acquire
13688   {
13689     dv = dx;
13690     dx = dx < de ? de : dx;
13691   }
13692 #pragma omp atomic compare capture acquire
13693   {
13694     dv = dx;
13695     dx = dx == de ? dd : dx;
13696   }
13697 #pragma omp atomic compare capture acquire
13698   {
13699     dx = dx > de ? de : dx;
13700     dv = dx;
13701   }
13702 #pragma omp atomic compare capture acquire
13703   {
13704     dx = dx < de ? de : dx;
13705     dv = dx;
13706   }
13707 #pragma omp atomic compare capture acquire
13708   {
13709     dx = dx == de ? dd : dx;
13710     dv = dx;
13711   }
13712 
13713 #pragma omp atomic compare capture relaxed
13714   {
13715     dv = dx;
13716     dx = dx > de ? de : dx;
13717   }
13718 #pragma omp atomic compare capture relaxed
13719   {
13720     dv = dx;
13721     dx = dx < de ? de : dx;
13722   }
13723 #pragma omp atomic compare capture relaxed
13724   {
13725     dv = dx;
13726     dx = dx == de ? dd : dx;
13727   }
13728 #pragma omp atomic compare capture relaxed
13729   {
13730     dx = dx > de ? de : dx;
13731     dv = dx;
13732   }
13733 #pragma omp atomic compare capture relaxed
13734   {
13735     dx = dx < de ? de : dx;
13736     dv = dx;
13737   }
13738 #pragma omp atomic compare capture relaxed
13739   {
13740     dx = dx == de ? dd : dx;
13741     dv = dx;
13742   }
13743 
13744 #pragma omp atomic compare capture release
13745   {
13746     dv = dx;
13747     dx = dx > de ? de : dx;
13748   }
13749 #pragma omp atomic compare capture release
13750   {
13751     dv = dx;
13752     dx = dx < de ? de : dx;
13753   }
13754 #pragma omp atomic compare capture release
13755   {
13756     dv = dx;
13757     dx = dx == de ? dd : dx;
13758   }
13759 #pragma omp atomic compare capture release
13760   {
13761     dx = dx > de ? de : dx;
13762     dv = dx;
13763   }
13764 #pragma omp atomic compare capture release
13765   {
13766     dx = dx < de ? de : dx;
13767     dv = dx;
13768   }
13769 #pragma omp atomic compare capture release
13770   {
13771     dx = dx == de ? dd : dx;
13772     dv = dx;
13773   }
13774 
13775 #pragma omp atomic compare capture seq_cst
13776   {
13777     dv = dx;
13778     dx = dx > de ? de : dx;
13779   }
13780 #pragma omp atomic compare capture seq_cst
13781   {
13782     dv = dx;
13783     dx = dx < de ? de : dx;
13784   }
13785 #pragma omp atomic compare capture seq_cst
13786   {
13787     dv = dx;
13788     dx = dx == de ? dd : dx;
13789   }
13790 #pragma omp atomic compare capture seq_cst
13791   {
13792     dx = dx > de ? de : dx;
13793     dv = dx;
13794   }
13795 #pragma omp atomic compare capture seq_cst
13796   {
13797     dx = dx < de ? de : dx;
13798     dv = dx;
13799   }
13800 #pragma omp atomic compare capture seq_cst
13801   {
13802     dx = dx == de ? dd : dx;
13803     dv = dx;
13804   }
13805 
13806   return dv;
13807 }
13808 
13809 
fail_dxevd()13810 double fail_dxevd() {
13811   double dx, dv, de, dd;
13812 
13813 #pragma omp atomic compare capture relaxed fail(relaxed)
13814   {if(dx == de) { dx = dv; } else { dd = dx; }}
13815 
13816 #pragma omp atomic compare capture acquire fail(relaxed)
13817   {if(dx == de) { dx = dv; } else { dd = dx; }}
13818 
13819 #pragma omp atomic compare capture release fail(relaxed)
13820   {if(dx == de) { dx = dv; } else { dd = dx; }}
13821 
13822 #pragma omp atomic compare capture acq_rel fail(relaxed)
13823   {if(dx == de) { dx = dv; } else { dd = dx; }}
13824 
13825 #pragma omp atomic compare capture seq_cst fail(relaxed)
13826   {if(dx == de) { dx = dv; } else { dd = dx; }}
13827 
13828 #pragma omp atomic compare capture relaxed fail(acquire)
13829   {if(dx == de) { dx = dv; } else { dd = dx; }}
13830 
13831 #pragma omp atomic compare capture acquire fail(acquire)
13832   {if(dx == de) { dx = dv; } else { dd = dx; }}
13833 
13834 #pragma omp atomic compare capture release fail(acquire)
13835   {if(dx == de) { dx = dv; } else { dd = dx; }}
13836 
13837 #pragma omp atomic compare capture acq_rel fail(acquire)
13838   {if(dx == de) { dx = dv; } else { dd = dx; }}
13839 
13840 #pragma omp atomic compare capture seq_cst fail(acquire)
13841   {if(dx == de) { dx = dv; } else { dd = dx; }}
13842 
13843 #pragma omp atomic compare capture relaxed fail(seq_cst)
13844   {if(dx == de) { dx = dv; } else { dd = dx; }}
13845 
13846 #pragma omp atomic compare capture acquire fail(seq_cst)
13847   {if(dx == de) { dx = dv; } else { dd = dx; }}
13848 
13849 #pragma omp atomic compare capture release fail(seq_cst)
13850   {if(dx == de) { dx = dv; } else { dd = dx; }}
13851 
13852 #pragma omp atomic compare capture acq_rel fail(seq_cst)
13853   {if(dx == de) { dx = dv; } else { dd = dx; }}
13854 
13855 #pragma omp atomic compare capture seq_cst fail(seq_cst)
13856   {if(dx == de) { dx = dv; } else { dd = dx; }}
13857 
13858 #pragma omp atomic compare seq_cst fail(acquire)
13859   dx = dx < de ? de : dx;
13860 
13861 #pragma omp atomic compare relaxed fail(seq_cst)
13862   dx = dx > de ? de : dx;
13863 
13864   return dx;
13865 }
13866 
13867 #endif
13868 // CHECK-LABEL: @foo(
13869 // CHECK-NEXT:  entry:
13870 // CHECK-NEXT:    [[CX:%.*]] = alloca i8, align 1
13871 // CHECK-NEXT:    [[CE:%.*]] = alloca i8, align 1
13872 // CHECK-NEXT:    [[CD:%.*]] = alloca i8, align 1
13873 // CHECK-NEXT:    [[UCX:%.*]] = alloca i8, align 1
13874 // CHECK-NEXT:    [[UCE:%.*]] = alloca i8, align 1
13875 // CHECK-NEXT:    [[UCD:%.*]] = alloca i8, align 1
13876 // CHECK-NEXT:    [[SX:%.*]] = alloca i16, align 2
13877 // CHECK-NEXT:    [[SE:%.*]] = alloca i16, align 2
13878 // CHECK-NEXT:    [[SD:%.*]] = alloca i16, align 2
13879 // CHECK-NEXT:    [[USX:%.*]] = alloca i16, align 2
13880 // CHECK-NEXT:    [[USE:%.*]] = alloca i16, align 2
13881 // CHECK-NEXT:    [[USD:%.*]] = alloca i16, align 2
13882 // CHECK-NEXT:    [[IX:%.*]] = alloca i32, align 4
13883 // CHECK-NEXT:    [[IE:%.*]] = alloca i32, align 4
13884 // CHECK-NEXT:    [[ID:%.*]] = alloca i32, align 4
13885 // CHECK-NEXT:    [[UIX:%.*]] = alloca i32, align 4
13886 // CHECK-NEXT:    [[UIE:%.*]] = alloca i32, align 4
13887 // CHECK-NEXT:    [[UID:%.*]] = alloca i32, align 4
13888 // CHECK-NEXT:    [[LX:%.*]] = alloca i64, align 8
13889 // CHECK-NEXT:    [[LE:%.*]] = alloca i64, align 8
13890 // CHECK-NEXT:    [[LD:%.*]] = alloca i64, align 8
13891 // CHECK-NEXT:    [[ULX:%.*]] = alloca i64, align 8
13892 // CHECK-NEXT:    [[ULE:%.*]] = alloca i64, align 8
13893 // CHECK-NEXT:    [[ULD:%.*]] = alloca i64, align 8
13894 // CHECK-NEXT:    [[LLX:%.*]] = alloca i64, align 8
13895 // CHECK-NEXT:    [[LLE:%.*]] = alloca i64, align 8
13896 // CHECK-NEXT:    [[LLD:%.*]] = alloca i64, align 8
13897 // CHECK-NEXT:    [[ULLX:%.*]] = alloca i64, align 8
13898 // CHECK-NEXT:    [[ULLE:%.*]] = alloca i64, align 8
13899 // CHECK-NEXT:    [[ULLD:%.*]] = alloca i64, align 8
13900 // CHECK-NEXT:    [[FX:%.*]] = alloca float, align 4
13901 // CHECK-NEXT:    [[FE:%.*]] = alloca float, align 4
13902 // CHECK-NEXT:    [[FD:%.*]] = alloca float, align 4
13903 // CHECK-NEXT:    [[DX:%.*]] = alloca double, align 8
13904 // CHECK-NEXT:    [[DE:%.*]] = alloca double, align 8
13905 // CHECK-NEXT:    [[DD:%.*]] = alloca double, align 8
13906 // CHECK-NEXT:    [[TMP0:%.*]] = load i8, ptr [[CE]], align 1
13907 // CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP0]] monotonic, align 1
13908 // CHECK-NEXT:    [[TMP2:%.*]] = load i8, ptr [[CE]], align 1
13909 // CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP2]] monotonic, align 1
13910 // CHECK-NEXT:    [[TMP4:%.*]] = load i8, ptr [[CE]], align 1
13911 // CHECK-NEXT:    [[TMP5:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP4]] monotonic, align 1
13912 // CHECK-NEXT:    [[TMP6:%.*]] = load i8, ptr [[CE]], align 1
13913 // CHECK-NEXT:    [[TMP7:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP6]] monotonic, align 1
13914 // CHECK-NEXT:    [[TMP8:%.*]] = load i8, ptr [[CE]], align 1
13915 // CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP8]] monotonic, align 1
13916 // CHECK-NEXT:    [[TMP10:%.*]] = load i8, ptr [[CE]], align 1
13917 // CHECK-NEXT:    [[TMP11:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP10]] monotonic, align 1
13918 // CHECK-NEXT:    [[TMP12:%.*]] = load i8, ptr [[CE]], align 1
13919 // CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP12]] monotonic, align 1
13920 // CHECK-NEXT:    [[TMP14:%.*]] = load i8, ptr [[CE]], align 1
13921 // CHECK-NEXT:    [[TMP15:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP14]] monotonic, align 1
13922 // CHECK-NEXT:    [[TMP16:%.*]] = load i8, ptr [[CE]], align 1
13923 // CHECK-NEXT:    [[TMP17:%.*]] = load i8, ptr [[CD]], align 1
13924 // CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP16]], i8 [[TMP17]] monotonic monotonic, align 1
13925 // CHECK-NEXT:    [[TMP19:%.*]] = load i8, ptr [[CE]], align 1
13926 // CHECK-NEXT:    [[TMP20:%.*]] = load i8, ptr [[CD]], align 1
13927 // CHECK-NEXT:    [[TMP21:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP19]], i8 [[TMP20]] monotonic monotonic, align 1
13928 // CHECK-NEXT:    [[TMP22:%.*]] = load i8, ptr [[CE]], align 1
13929 // CHECK-NEXT:    [[TMP23:%.*]] = load i8, ptr [[CD]], align 1
13930 // CHECK-NEXT:    [[TMP24:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP22]], i8 [[TMP23]] monotonic monotonic, align 1
13931 // CHECK-NEXT:    [[TMP25:%.*]] = load i8, ptr [[CE]], align 1
13932 // CHECK-NEXT:    [[TMP26:%.*]] = load i8, ptr [[CD]], align 1
13933 // CHECK-NEXT:    [[TMP27:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP25]], i8 [[TMP26]] monotonic monotonic, align 1
13934 // CHECK-NEXT:    [[TMP28:%.*]] = load i8, ptr [[UCE]], align 1
13935 // CHECK-NEXT:    [[TMP29:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP28]] monotonic, align 1
13936 // CHECK-NEXT:    [[TMP30:%.*]] = load i8, ptr [[UCE]], align 1
13937 // CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP30]] monotonic, align 1
13938 // CHECK-NEXT:    [[TMP32:%.*]] = load i8, ptr [[UCE]], align 1
13939 // CHECK-NEXT:    [[TMP33:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP32]] monotonic, align 1
13940 // CHECK-NEXT:    [[TMP34:%.*]] = load i8, ptr [[UCE]], align 1
13941 // CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP34]] monotonic, align 1
13942 // CHECK-NEXT:    [[TMP36:%.*]] = load i8, ptr [[UCE]], align 1
13943 // CHECK-NEXT:    [[TMP37:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP36]] monotonic, align 1
13944 // CHECK-NEXT:    [[TMP38:%.*]] = load i8, ptr [[UCE]], align 1
13945 // CHECK-NEXT:    [[TMP39:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP38]] monotonic, align 1
13946 // CHECK-NEXT:    [[TMP40:%.*]] = load i8, ptr [[UCE]], align 1
13947 // CHECK-NEXT:    [[TMP41:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP40]] monotonic, align 1
13948 // CHECK-NEXT:    [[TMP42:%.*]] = load i8, ptr [[UCE]], align 1
13949 // CHECK-NEXT:    [[TMP43:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP42]] monotonic, align 1
13950 // CHECK-NEXT:    [[TMP44:%.*]] = load i8, ptr [[UCE]], align 1
13951 // CHECK-NEXT:    [[TMP45:%.*]] = load i8, ptr [[UCD]], align 1
13952 // CHECK-NEXT:    [[TMP46:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP44]], i8 [[TMP45]] monotonic monotonic, align 1
13953 // CHECK-NEXT:    [[TMP47:%.*]] = load i8, ptr [[UCE]], align 1
13954 // CHECK-NEXT:    [[TMP48:%.*]] = load i8, ptr [[UCD]], align 1
13955 // CHECK-NEXT:    [[TMP49:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP47]], i8 [[TMP48]] monotonic monotonic, align 1
13956 // CHECK-NEXT:    [[TMP50:%.*]] = load i8, ptr [[UCE]], align 1
13957 // CHECK-NEXT:    [[TMP51:%.*]] = load i8, ptr [[UCD]], align 1
13958 // CHECK-NEXT:    [[TMP52:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP50]], i8 [[TMP51]] monotonic monotonic, align 1
13959 // CHECK-NEXT:    [[TMP53:%.*]] = load i8, ptr [[UCE]], align 1
13960 // CHECK-NEXT:    [[TMP54:%.*]] = load i8, ptr [[UCD]], align 1
13961 // CHECK-NEXT:    [[TMP55:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP53]], i8 [[TMP54]] monotonic monotonic, align 1
13962 // CHECK-NEXT:    [[TMP56:%.*]] = load i8, ptr [[CE]], align 1
13963 // CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP56]] acq_rel, align 1
13964 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1:[0-9]+]])
13965 // CHECK-NEXT:    [[TMP58:%.*]] = load i8, ptr [[CE]], align 1
13966 // CHECK-NEXT:    [[TMP59:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP58]] acq_rel, align 1
13967 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
13968 // CHECK-NEXT:    [[TMP60:%.*]] = load i8, ptr [[CE]], align 1
13969 // CHECK-NEXT:    [[TMP61:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP60]] acq_rel, align 1
13970 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
13971 // CHECK-NEXT:    [[TMP62:%.*]] = load i8, ptr [[CE]], align 1
13972 // CHECK-NEXT:    [[TMP63:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP62]] acq_rel, align 1
13973 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
13974 // CHECK-NEXT:    [[TMP64:%.*]] = load i8, ptr [[CE]], align 1
13975 // CHECK-NEXT:    [[TMP65:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP64]] acq_rel, align 1
13976 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
13977 // CHECK-NEXT:    [[TMP66:%.*]] = load i8, ptr [[CE]], align 1
13978 // CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP66]] acq_rel, align 1
13979 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
13980 // CHECK-NEXT:    [[TMP68:%.*]] = load i8, ptr [[CE]], align 1
13981 // CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP68]] acq_rel, align 1
13982 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
13983 // CHECK-NEXT:    [[TMP70:%.*]] = load i8, ptr [[CE]], align 1
13984 // CHECK-NEXT:    [[TMP71:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP70]] acq_rel, align 1
13985 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
13986 // CHECK-NEXT:    [[TMP72:%.*]] = load i8, ptr [[CE]], align 1
13987 // CHECK-NEXT:    [[TMP73:%.*]] = load i8, ptr [[CD]], align 1
13988 // CHECK-NEXT:    [[TMP74:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP72]], i8 [[TMP73]] acq_rel acquire, align 1
13989 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
13990 // CHECK-NEXT:    [[TMP75:%.*]] = load i8, ptr [[CE]], align 1
13991 // CHECK-NEXT:    [[TMP76:%.*]] = load i8, ptr [[CD]], align 1
13992 // CHECK-NEXT:    [[TMP77:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP75]], i8 [[TMP76]] acq_rel acquire, align 1
13993 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
13994 // CHECK-NEXT:    [[TMP78:%.*]] = load i8, ptr [[CE]], align 1
13995 // CHECK-NEXT:    [[TMP79:%.*]] = load i8, ptr [[CD]], align 1
13996 // CHECK-NEXT:    [[TMP80:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP78]], i8 [[TMP79]] acq_rel acquire, align 1
13997 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
13998 // CHECK-NEXT:    [[TMP81:%.*]] = load i8, ptr [[CE]], align 1
13999 // CHECK-NEXT:    [[TMP82:%.*]] = load i8, ptr [[CD]], align 1
14000 // CHECK-NEXT:    [[TMP83:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP81]], i8 [[TMP82]] acq_rel acquire, align 1
14001 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14002 // CHECK-NEXT:    [[TMP84:%.*]] = load i8, ptr [[UCE]], align 1
14003 // CHECK-NEXT:    [[TMP85:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP84]] acq_rel, align 1
14004 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14005 // CHECK-NEXT:    [[TMP86:%.*]] = load i8, ptr [[UCE]], align 1
14006 // CHECK-NEXT:    [[TMP87:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP86]] acq_rel, align 1
14007 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14008 // CHECK-NEXT:    [[TMP88:%.*]] = load i8, ptr [[UCE]], align 1
14009 // CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP88]] acq_rel, align 1
14010 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14011 // CHECK-NEXT:    [[TMP90:%.*]] = load i8, ptr [[UCE]], align 1
14012 // CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP90]] acq_rel, align 1
14013 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14014 // CHECK-NEXT:    [[TMP92:%.*]] = load i8, ptr [[UCE]], align 1
14015 // CHECK-NEXT:    [[TMP93:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP92]] acq_rel, align 1
14016 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14017 // CHECK-NEXT:    [[TMP94:%.*]] = load i8, ptr [[UCE]], align 1
14018 // CHECK-NEXT:    [[TMP95:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP94]] acq_rel, align 1
14019 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14020 // CHECK-NEXT:    [[TMP96:%.*]] = load i8, ptr [[UCE]], align 1
14021 // CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP96]] acq_rel, align 1
14022 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14023 // CHECK-NEXT:    [[TMP98:%.*]] = load i8, ptr [[UCE]], align 1
14024 // CHECK-NEXT:    [[TMP99:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP98]] acq_rel, align 1
14025 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14026 // CHECK-NEXT:    [[TMP100:%.*]] = load i8, ptr [[UCE]], align 1
14027 // CHECK-NEXT:    [[TMP101:%.*]] = load i8, ptr [[UCD]], align 1
14028 // CHECK-NEXT:    [[TMP102:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP100]], i8 [[TMP101]] acq_rel acquire, align 1
14029 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14030 // CHECK-NEXT:    [[TMP103:%.*]] = load i8, ptr [[UCE]], align 1
14031 // CHECK-NEXT:    [[TMP104:%.*]] = load i8, ptr [[UCD]], align 1
14032 // CHECK-NEXT:    [[TMP105:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP103]], i8 [[TMP104]] acq_rel acquire, align 1
14033 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14034 // CHECK-NEXT:    [[TMP106:%.*]] = load i8, ptr [[UCE]], align 1
14035 // CHECK-NEXT:    [[TMP107:%.*]] = load i8, ptr [[UCD]], align 1
14036 // CHECK-NEXT:    [[TMP108:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP106]], i8 [[TMP107]] acq_rel acquire, align 1
14037 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14038 // CHECK-NEXT:    [[TMP109:%.*]] = load i8, ptr [[UCE]], align 1
14039 // CHECK-NEXT:    [[TMP110:%.*]] = load i8, ptr [[UCD]], align 1
14040 // CHECK-NEXT:    [[TMP111:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP109]], i8 [[TMP110]] acq_rel acquire, align 1
14041 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14042 // CHECK-NEXT:    [[TMP112:%.*]] = load i8, ptr [[CE]], align 1
14043 // CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP112]] acquire, align 1
14044 // CHECK-NEXT:    [[TMP114:%.*]] = load i8, ptr [[CE]], align 1
14045 // CHECK-NEXT:    [[TMP115:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP114]] acquire, align 1
14046 // CHECK-NEXT:    [[TMP116:%.*]] = load i8, ptr [[CE]], align 1
14047 // CHECK-NEXT:    [[TMP117:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP116]] acquire, align 1
14048 // CHECK-NEXT:    [[TMP118:%.*]] = load i8, ptr [[CE]], align 1
14049 // CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP118]] acquire, align 1
14050 // CHECK-NEXT:    [[TMP120:%.*]] = load i8, ptr [[CE]], align 1
14051 // CHECK-NEXT:    [[TMP121:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP120]] acquire, align 1
14052 // CHECK-NEXT:    [[TMP122:%.*]] = load i8, ptr [[CE]], align 1
14053 // CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP122]] acquire, align 1
14054 // CHECK-NEXT:    [[TMP124:%.*]] = load i8, ptr [[CE]], align 1
14055 // CHECK-NEXT:    [[TMP125:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP124]] acquire, align 1
14056 // CHECK-NEXT:    [[TMP126:%.*]] = load i8, ptr [[CE]], align 1
14057 // CHECK-NEXT:    [[TMP127:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP126]] acquire, align 1
14058 // CHECK-NEXT:    [[TMP128:%.*]] = load i8, ptr [[CE]], align 1
14059 // CHECK-NEXT:    [[TMP129:%.*]] = load i8, ptr [[CD]], align 1
14060 // CHECK-NEXT:    [[TMP130:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP128]], i8 [[TMP129]] acquire acquire, align 1
14061 // CHECK-NEXT:    [[TMP131:%.*]] = load i8, ptr [[CE]], align 1
14062 // CHECK-NEXT:    [[TMP132:%.*]] = load i8, ptr [[CD]], align 1
14063 // CHECK-NEXT:    [[TMP133:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP131]], i8 [[TMP132]] acquire acquire, align 1
14064 // CHECK-NEXT:    [[TMP134:%.*]] = load i8, ptr [[CE]], align 1
14065 // CHECK-NEXT:    [[TMP135:%.*]] = load i8, ptr [[CD]], align 1
14066 // CHECK-NEXT:    [[TMP136:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP134]], i8 [[TMP135]] acquire acquire, align 1
14067 // CHECK-NEXT:    [[TMP137:%.*]] = load i8, ptr [[CE]], align 1
14068 // CHECK-NEXT:    [[TMP138:%.*]] = load i8, ptr [[CD]], align 1
14069 // CHECK-NEXT:    [[TMP139:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP137]], i8 [[TMP138]] acquire acquire, align 1
14070 // CHECK-NEXT:    [[TMP140:%.*]] = load i8, ptr [[UCE]], align 1
14071 // CHECK-NEXT:    [[TMP141:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP140]] acquire, align 1
14072 // CHECK-NEXT:    [[TMP142:%.*]] = load i8, ptr [[UCE]], align 1
14073 // CHECK-NEXT:    [[TMP143:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP142]] acquire, align 1
14074 // CHECK-NEXT:    [[TMP144:%.*]] = load i8, ptr [[UCE]], align 1
14075 // CHECK-NEXT:    [[TMP145:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP144]] acquire, align 1
14076 // CHECK-NEXT:    [[TMP146:%.*]] = load i8, ptr [[UCE]], align 1
14077 // CHECK-NEXT:    [[TMP147:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP146]] acquire, align 1
14078 // CHECK-NEXT:    [[TMP148:%.*]] = load i8, ptr [[UCE]], align 1
14079 // CHECK-NEXT:    [[TMP149:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP148]] acquire, align 1
14080 // CHECK-NEXT:    [[TMP150:%.*]] = load i8, ptr [[UCE]], align 1
14081 // CHECK-NEXT:    [[TMP151:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP150]] acquire, align 1
14082 // CHECK-NEXT:    [[TMP152:%.*]] = load i8, ptr [[UCE]], align 1
14083 // CHECK-NEXT:    [[TMP153:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP152]] acquire, align 1
14084 // CHECK-NEXT:    [[TMP154:%.*]] = load i8, ptr [[UCE]], align 1
14085 // CHECK-NEXT:    [[TMP155:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP154]] acquire, align 1
14086 // CHECK-NEXT:    [[TMP156:%.*]] = load i8, ptr [[UCE]], align 1
14087 // CHECK-NEXT:    [[TMP157:%.*]] = load i8, ptr [[UCD]], align 1
14088 // CHECK-NEXT:    [[TMP158:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP156]], i8 [[TMP157]] acquire acquire, align 1
14089 // CHECK-NEXT:    [[TMP159:%.*]] = load i8, ptr [[UCE]], align 1
14090 // CHECK-NEXT:    [[TMP160:%.*]] = load i8, ptr [[UCD]], align 1
14091 // CHECK-NEXT:    [[TMP161:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP159]], i8 [[TMP160]] acquire acquire, align 1
14092 // CHECK-NEXT:    [[TMP162:%.*]] = load i8, ptr [[UCE]], align 1
14093 // CHECK-NEXT:    [[TMP163:%.*]] = load i8, ptr [[UCD]], align 1
14094 // CHECK-NEXT:    [[TMP164:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP162]], i8 [[TMP163]] acquire acquire, align 1
14095 // CHECK-NEXT:    [[TMP165:%.*]] = load i8, ptr [[UCE]], align 1
14096 // CHECK-NEXT:    [[TMP166:%.*]] = load i8, ptr [[UCD]], align 1
14097 // CHECK-NEXT:    [[TMP167:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP165]], i8 [[TMP166]] acquire acquire, align 1
14098 // CHECK-NEXT:    [[TMP168:%.*]] = load i8, ptr [[CE]], align 1
14099 // CHECK-NEXT:    [[TMP169:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP168]] monotonic, align 1
14100 // CHECK-NEXT:    [[TMP170:%.*]] = load i8, ptr [[CE]], align 1
14101 // CHECK-NEXT:    [[TMP171:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP170]] monotonic, align 1
14102 // CHECK-NEXT:    [[TMP172:%.*]] = load i8, ptr [[CE]], align 1
14103 // CHECK-NEXT:    [[TMP173:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP172]] monotonic, align 1
14104 // CHECK-NEXT:    [[TMP174:%.*]] = load i8, ptr [[CE]], align 1
14105 // CHECK-NEXT:    [[TMP175:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP174]] monotonic, align 1
14106 // CHECK-NEXT:    [[TMP176:%.*]] = load i8, ptr [[CE]], align 1
14107 // CHECK-NEXT:    [[TMP177:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP176]] monotonic, align 1
14108 // CHECK-NEXT:    [[TMP178:%.*]] = load i8, ptr [[CE]], align 1
14109 // CHECK-NEXT:    [[TMP179:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP178]] monotonic, align 1
14110 // CHECK-NEXT:    [[TMP180:%.*]] = load i8, ptr [[CE]], align 1
14111 // CHECK-NEXT:    [[TMP181:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP180]] monotonic, align 1
14112 // CHECK-NEXT:    [[TMP182:%.*]] = load i8, ptr [[CE]], align 1
14113 // CHECK-NEXT:    [[TMP183:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP182]] monotonic, align 1
14114 // CHECK-NEXT:    [[TMP184:%.*]] = load i8, ptr [[CE]], align 1
14115 // CHECK-NEXT:    [[TMP185:%.*]] = load i8, ptr [[CD]], align 1
14116 // CHECK-NEXT:    [[TMP186:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP184]], i8 [[TMP185]] monotonic monotonic, align 1
14117 // CHECK-NEXT:    [[TMP187:%.*]] = load i8, ptr [[CE]], align 1
14118 // CHECK-NEXT:    [[TMP188:%.*]] = load i8, ptr [[CD]], align 1
14119 // CHECK-NEXT:    [[TMP189:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP187]], i8 [[TMP188]] monotonic monotonic, align 1
14120 // CHECK-NEXT:    [[TMP190:%.*]] = load i8, ptr [[CE]], align 1
14121 // CHECK-NEXT:    [[TMP191:%.*]] = load i8, ptr [[CD]], align 1
14122 // CHECK-NEXT:    [[TMP192:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP190]], i8 [[TMP191]] monotonic monotonic, align 1
14123 // CHECK-NEXT:    [[TMP193:%.*]] = load i8, ptr [[CE]], align 1
14124 // CHECK-NEXT:    [[TMP194:%.*]] = load i8, ptr [[CD]], align 1
14125 // CHECK-NEXT:    [[TMP195:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP193]], i8 [[TMP194]] monotonic monotonic, align 1
14126 // CHECK-NEXT:    [[TMP196:%.*]] = load i8, ptr [[UCE]], align 1
14127 // CHECK-NEXT:    [[TMP197:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP196]] monotonic, align 1
14128 // CHECK-NEXT:    [[TMP198:%.*]] = load i8, ptr [[UCE]], align 1
14129 // CHECK-NEXT:    [[TMP199:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP198]] monotonic, align 1
14130 // CHECK-NEXT:    [[TMP200:%.*]] = load i8, ptr [[UCE]], align 1
14131 // CHECK-NEXT:    [[TMP201:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP200]] monotonic, align 1
14132 // CHECK-NEXT:    [[TMP202:%.*]] = load i8, ptr [[UCE]], align 1
14133 // CHECK-NEXT:    [[TMP203:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP202]] monotonic, align 1
14134 // CHECK-NEXT:    [[TMP204:%.*]] = load i8, ptr [[UCE]], align 1
14135 // CHECK-NEXT:    [[TMP205:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP204]] monotonic, align 1
14136 // CHECK-NEXT:    [[TMP206:%.*]] = load i8, ptr [[UCE]], align 1
14137 // CHECK-NEXT:    [[TMP207:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP206]] monotonic, align 1
14138 // CHECK-NEXT:    [[TMP208:%.*]] = load i8, ptr [[UCE]], align 1
14139 // CHECK-NEXT:    [[TMP209:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP208]] monotonic, align 1
14140 // CHECK-NEXT:    [[TMP210:%.*]] = load i8, ptr [[UCE]], align 1
14141 // CHECK-NEXT:    [[TMP211:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP210]] monotonic, align 1
14142 // CHECK-NEXT:    [[TMP212:%.*]] = load i8, ptr [[UCE]], align 1
14143 // CHECK-NEXT:    [[TMP213:%.*]] = load i8, ptr [[UCD]], align 1
14144 // CHECK-NEXT:    [[TMP214:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP212]], i8 [[TMP213]] monotonic monotonic, align 1
14145 // CHECK-NEXT:    [[TMP215:%.*]] = load i8, ptr [[UCE]], align 1
14146 // CHECK-NEXT:    [[TMP216:%.*]] = load i8, ptr [[UCD]], align 1
14147 // CHECK-NEXT:    [[TMP217:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP215]], i8 [[TMP216]] monotonic monotonic, align 1
14148 // CHECK-NEXT:    [[TMP218:%.*]] = load i8, ptr [[UCE]], align 1
14149 // CHECK-NEXT:    [[TMP219:%.*]] = load i8, ptr [[UCD]], align 1
14150 // CHECK-NEXT:    [[TMP220:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP218]], i8 [[TMP219]] monotonic monotonic, align 1
14151 // CHECK-NEXT:    [[TMP221:%.*]] = load i8, ptr [[UCE]], align 1
14152 // CHECK-NEXT:    [[TMP222:%.*]] = load i8, ptr [[UCD]], align 1
14153 // CHECK-NEXT:    [[TMP223:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP221]], i8 [[TMP222]] monotonic monotonic, align 1
14154 // CHECK-NEXT:    [[TMP224:%.*]] = load i8, ptr [[CE]], align 1
14155 // CHECK-NEXT:    [[TMP225:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP224]] release, align 1
14156 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14157 // CHECK-NEXT:    [[TMP226:%.*]] = load i8, ptr [[CE]], align 1
14158 // CHECK-NEXT:    [[TMP227:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP226]] release, align 1
14159 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14160 // CHECK-NEXT:    [[TMP228:%.*]] = load i8, ptr [[CE]], align 1
14161 // CHECK-NEXT:    [[TMP229:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP228]] release, align 1
14162 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14163 // CHECK-NEXT:    [[TMP230:%.*]] = load i8, ptr [[CE]], align 1
14164 // CHECK-NEXT:    [[TMP231:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP230]] release, align 1
14165 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14166 // CHECK-NEXT:    [[TMP232:%.*]] = load i8, ptr [[CE]], align 1
14167 // CHECK-NEXT:    [[TMP233:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP232]] release, align 1
14168 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14169 // CHECK-NEXT:    [[TMP234:%.*]] = load i8, ptr [[CE]], align 1
14170 // CHECK-NEXT:    [[TMP235:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP234]] release, align 1
14171 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14172 // CHECK-NEXT:    [[TMP236:%.*]] = load i8, ptr [[CE]], align 1
14173 // CHECK-NEXT:    [[TMP237:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP236]] release, align 1
14174 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14175 // CHECK-NEXT:    [[TMP238:%.*]] = load i8, ptr [[CE]], align 1
14176 // CHECK-NEXT:    [[TMP239:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP238]] release, align 1
14177 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14178 // CHECK-NEXT:    [[TMP240:%.*]] = load i8, ptr [[CE]], align 1
14179 // CHECK-NEXT:    [[TMP241:%.*]] = load i8, ptr [[CD]], align 1
14180 // CHECK-NEXT:    [[TMP242:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP240]], i8 [[TMP241]] release monotonic, align 1
14181 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14182 // CHECK-NEXT:    [[TMP243:%.*]] = load i8, ptr [[CE]], align 1
14183 // CHECK-NEXT:    [[TMP244:%.*]] = load i8, ptr [[CD]], align 1
14184 // CHECK-NEXT:    [[TMP245:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP243]], i8 [[TMP244]] release monotonic, align 1
14185 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14186 // CHECK-NEXT:    [[TMP246:%.*]] = load i8, ptr [[CE]], align 1
14187 // CHECK-NEXT:    [[TMP247:%.*]] = load i8, ptr [[CD]], align 1
14188 // CHECK-NEXT:    [[TMP248:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP246]], i8 [[TMP247]] release monotonic, align 1
14189 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14190 // CHECK-NEXT:    [[TMP249:%.*]] = load i8, ptr [[CE]], align 1
14191 // CHECK-NEXT:    [[TMP250:%.*]] = load i8, ptr [[CD]], align 1
14192 // CHECK-NEXT:    [[TMP251:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP249]], i8 [[TMP250]] release monotonic, align 1
14193 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14194 // CHECK-NEXT:    [[TMP252:%.*]] = load i8, ptr [[UCE]], align 1
14195 // CHECK-NEXT:    [[TMP253:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP252]] release, align 1
14196 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14197 // CHECK-NEXT:    [[TMP254:%.*]] = load i8, ptr [[UCE]], align 1
14198 // CHECK-NEXT:    [[TMP255:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP254]] release, align 1
14199 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14200 // CHECK-NEXT:    [[TMP256:%.*]] = load i8, ptr [[UCE]], align 1
14201 // CHECK-NEXT:    [[TMP257:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP256]] release, align 1
14202 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14203 // CHECK-NEXT:    [[TMP258:%.*]] = load i8, ptr [[UCE]], align 1
14204 // CHECK-NEXT:    [[TMP259:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP258]] release, align 1
14205 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14206 // CHECK-NEXT:    [[TMP260:%.*]] = load i8, ptr [[UCE]], align 1
14207 // CHECK-NEXT:    [[TMP261:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP260]] release, align 1
14208 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14209 // CHECK-NEXT:    [[TMP262:%.*]] = load i8, ptr [[UCE]], align 1
14210 // CHECK-NEXT:    [[TMP263:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP262]] release, align 1
14211 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14212 // CHECK-NEXT:    [[TMP264:%.*]] = load i8, ptr [[UCE]], align 1
14213 // CHECK-NEXT:    [[TMP265:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP264]] release, align 1
14214 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14215 // CHECK-NEXT:    [[TMP266:%.*]] = load i8, ptr [[UCE]], align 1
14216 // CHECK-NEXT:    [[TMP267:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP266]] release, align 1
14217 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14218 // CHECK-NEXT:    [[TMP268:%.*]] = load i8, ptr [[UCE]], align 1
14219 // CHECK-NEXT:    [[TMP269:%.*]] = load i8, ptr [[UCD]], align 1
14220 // CHECK-NEXT:    [[TMP270:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP268]], i8 [[TMP269]] release monotonic, align 1
14221 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14222 // CHECK-NEXT:    [[TMP271:%.*]] = load i8, ptr [[UCE]], align 1
14223 // CHECK-NEXT:    [[TMP272:%.*]] = load i8, ptr [[UCD]], align 1
14224 // CHECK-NEXT:    [[TMP273:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP271]], i8 [[TMP272]] release monotonic, align 1
14225 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14226 // CHECK-NEXT:    [[TMP274:%.*]] = load i8, ptr [[UCE]], align 1
14227 // CHECK-NEXT:    [[TMP275:%.*]] = load i8, ptr [[UCD]], align 1
14228 // CHECK-NEXT:    [[TMP276:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP274]], i8 [[TMP275]] release monotonic, align 1
14229 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14230 // CHECK-NEXT:    [[TMP277:%.*]] = load i8, ptr [[UCE]], align 1
14231 // CHECK-NEXT:    [[TMP278:%.*]] = load i8, ptr [[UCD]], align 1
14232 // CHECK-NEXT:    [[TMP279:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP277]], i8 [[TMP278]] release monotonic, align 1
14233 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14234 // CHECK-NEXT:    [[TMP280:%.*]] = load i8, ptr [[CE]], align 1
14235 // CHECK-NEXT:    [[TMP281:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP280]] seq_cst, align 1
14236 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14237 // CHECK-NEXT:    [[TMP282:%.*]] = load i8, ptr [[CE]], align 1
14238 // CHECK-NEXT:    [[TMP283:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP282]] seq_cst, align 1
14239 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14240 // CHECK-NEXT:    [[TMP284:%.*]] = load i8, ptr [[CE]], align 1
14241 // CHECK-NEXT:    [[TMP285:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP284]] seq_cst, align 1
14242 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14243 // CHECK-NEXT:    [[TMP286:%.*]] = load i8, ptr [[CE]], align 1
14244 // CHECK-NEXT:    [[TMP287:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP286]] seq_cst, align 1
14245 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14246 // CHECK-NEXT:    [[TMP288:%.*]] = load i8, ptr [[CE]], align 1
14247 // CHECK-NEXT:    [[TMP289:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP288]] seq_cst, align 1
14248 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14249 // CHECK-NEXT:    [[TMP290:%.*]] = load i8, ptr [[CE]], align 1
14250 // CHECK-NEXT:    [[TMP291:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP290]] seq_cst, align 1
14251 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14252 // CHECK-NEXT:    [[TMP292:%.*]] = load i8, ptr [[CE]], align 1
14253 // CHECK-NEXT:    [[TMP293:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP292]] seq_cst, align 1
14254 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14255 // CHECK-NEXT:    [[TMP294:%.*]] = load i8, ptr [[CE]], align 1
14256 // CHECK-NEXT:    [[TMP295:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP294]] seq_cst, align 1
14257 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14258 // CHECK-NEXT:    [[TMP296:%.*]] = load i8, ptr [[CE]], align 1
14259 // CHECK-NEXT:    [[TMP297:%.*]] = load i8, ptr [[CD]], align 1
14260 // CHECK-NEXT:    [[TMP298:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP296]], i8 [[TMP297]] seq_cst seq_cst, align 1
14261 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14262 // CHECK-NEXT:    [[TMP299:%.*]] = load i8, ptr [[CE]], align 1
14263 // CHECK-NEXT:    [[TMP300:%.*]] = load i8, ptr [[CD]], align 1
14264 // CHECK-NEXT:    [[TMP301:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP299]], i8 [[TMP300]] seq_cst seq_cst, align 1
14265 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14266 // CHECK-NEXT:    [[TMP302:%.*]] = load i8, ptr [[CE]], align 1
14267 // CHECK-NEXT:    [[TMP303:%.*]] = load i8, ptr [[CD]], align 1
14268 // CHECK-NEXT:    [[TMP304:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP302]], i8 [[TMP303]] seq_cst seq_cst, align 1
14269 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14270 // CHECK-NEXT:    [[TMP305:%.*]] = load i8, ptr [[CE]], align 1
14271 // CHECK-NEXT:    [[TMP306:%.*]] = load i8, ptr [[CD]], align 1
14272 // CHECK-NEXT:    [[TMP307:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP305]], i8 [[TMP306]] seq_cst seq_cst, align 1
14273 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14274 // CHECK-NEXT:    [[TMP308:%.*]] = load i8, ptr [[UCE]], align 1
14275 // CHECK-NEXT:    [[TMP309:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP308]] seq_cst, align 1
14276 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14277 // CHECK-NEXT:    [[TMP310:%.*]] = load i8, ptr [[UCE]], align 1
14278 // CHECK-NEXT:    [[TMP311:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP310]] seq_cst, align 1
14279 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14280 // CHECK-NEXT:    [[TMP312:%.*]] = load i8, ptr [[UCE]], align 1
14281 // CHECK-NEXT:    [[TMP313:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP312]] seq_cst, align 1
14282 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14283 // CHECK-NEXT:    [[TMP314:%.*]] = load i8, ptr [[UCE]], align 1
14284 // CHECK-NEXT:    [[TMP315:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP314]] seq_cst, align 1
14285 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14286 // CHECK-NEXT:    [[TMP316:%.*]] = load i8, ptr [[UCE]], align 1
14287 // CHECK-NEXT:    [[TMP317:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP316]] seq_cst, align 1
14288 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14289 // CHECK-NEXT:    [[TMP318:%.*]] = load i8, ptr [[UCE]], align 1
14290 // CHECK-NEXT:    [[TMP319:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP318]] seq_cst, align 1
14291 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14292 // CHECK-NEXT:    [[TMP320:%.*]] = load i8, ptr [[UCE]], align 1
14293 // CHECK-NEXT:    [[TMP321:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP320]] seq_cst, align 1
14294 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14295 // CHECK-NEXT:    [[TMP322:%.*]] = load i8, ptr [[UCE]], align 1
14296 // CHECK-NEXT:    [[TMP323:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP322]] seq_cst, align 1
14297 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14298 // CHECK-NEXT:    [[TMP324:%.*]] = load i8, ptr [[UCE]], align 1
14299 // CHECK-NEXT:    [[TMP325:%.*]] = load i8, ptr [[UCD]], align 1
14300 // CHECK-NEXT:    [[TMP326:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP324]], i8 [[TMP325]] seq_cst seq_cst, align 1
14301 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14302 // CHECK-NEXT:    [[TMP327:%.*]] = load i8, ptr [[UCE]], align 1
14303 // CHECK-NEXT:    [[TMP328:%.*]] = load i8, ptr [[UCD]], align 1
14304 // CHECK-NEXT:    [[TMP329:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP327]], i8 [[TMP328]] seq_cst seq_cst, align 1
14305 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14306 // CHECK-NEXT:    [[TMP330:%.*]] = load i8, ptr [[UCE]], align 1
14307 // CHECK-NEXT:    [[TMP331:%.*]] = load i8, ptr [[UCD]], align 1
14308 // CHECK-NEXT:    [[TMP332:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP330]], i8 [[TMP331]] seq_cst seq_cst, align 1
14309 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14310 // CHECK-NEXT:    [[TMP333:%.*]] = load i8, ptr [[UCE]], align 1
14311 // CHECK-NEXT:    [[TMP334:%.*]] = load i8, ptr [[UCD]], align 1
14312 // CHECK-NEXT:    [[TMP335:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP333]], i8 [[TMP334]] seq_cst seq_cst, align 1
14313 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14314 // CHECK-NEXT:    [[TMP336:%.*]] = load i16, ptr [[SE]], align 2
14315 // CHECK-NEXT:    [[TMP337:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP336]] monotonic, align 2
14316 // CHECK-NEXT:    [[TMP338:%.*]] = load i16, ptr [[SE]], align 2
14317 // CHECK-NEXT:    [[TMP339:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP338]] monotonic, align 2
14318 // CHECK-NEXT:    [[TMP340:%.*]] = load i16, ptr [[SE]], align 2
14319 // CHECK-NEXT:    [[TMP341:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP340]] monotonic, align 2
14320 // CHECK-NEXT:    [[TMP342:%.*]] = load i16, ptr [[SE]], align 2
14321 // CHECK-NEXT:    [[TMP343:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP342]] monotonic, align 2
14322 // CHECK-NEXT:    [[TMP344:%.*]] = load i16, ptr [[SE]], align 2
14323 // CHECK-NEXT:    [[TMP345:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP344]] monotonic, align 2
14324 // CHECK-NEXT:    [[TMP346:%.*]] = load i16, ptr [[SE]], align 2
14325 // CHECK-NEXT:    [[TMP347:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP346]] monotonic, align 2
14326 // CHECK-NEXT:    [[TMP348:%.*]] = load i16, ptr [[SE]], align 2
14327 // CHECK-NEXT:    [[TMP349:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP348]] monotonic, align 2
14328 // CHECK-NEXT:    [[TMP350:%.*]] = load i16, ptr [[SE]], align 2
14329 // CHECK-NEXT:    [[TMP351:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP350]] monotonic, align 2
14330 // CHECK-NEXT:    [[TMP352:%.*]] = load i16, ptr [[SE]], align 2
14331 // CHECK-NEXT:    [[TMP353:%.*]] = load i16, ptr [[SD]], align 2
14332 // CHECK-NEXT:    [[TMP354:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP352]], i16 [[TMP353]] monotonic monotonic, align 2
14333 // CHECK-NEXT:    [[TMP355:%.*]] = load i16, ptr [[SE]], align 2
14334 // CHECK-NEXT:    [[TMP356:%.*]] = load i16, ptr [[SD]], align 2
14335 // CHECK-NEXT:    [[TMP357:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP355]], i16 [[TMP356]] monotonic monotonic, align 2
14336 // CHECK-NEXT:    [[TMP358:%.*]] = load i16, ptr [[SE]], align 2
14337 // CHECK-NEXT:    [[TMP359:%.*]] = load i16, ptr [[SD]], align 2
14338 // CHECK-NEXT:    [[TMP360:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP358]], i16 [[TMP359]] monotonic monotonic, align 2
14339 // CHECK-NEXT:    [[TMP361:%.*]] = load i16, ptr [[SE]], align 2
14340 // CHECK-NEXT:    [[TMP362:%.*]] = load i16, ptr [[SD]], align 2
14341 // CHECK-NEXT:    [[TMP363:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP361]], i16 [[TMP362]] monotonic monotonic, align 2
14342 // CHECK-NEXT:    [[TMP364:%.*]] = load i16, ptr [[USE]], align 2
14343 // CHECK-NEXT:    [[TMP365:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP364]] monotonic, align 2
14344 // CHECK-NEXT:    [[TMP366:%.*]] = load i16, ptr [[USE]], align 2
14345 // CHECK-NEXT:    [[TMP367:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP366]] monotonic, align 2
14346 // CHECK-NEXT:    [[TMP368:%.*]] = load i16, ptr [[USE]], align 2
14347 // CHECK-NEXT:    [[TMP369:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP368]] monotonic, align 2
14348 // CHECK-NEXT:    [[TMP370:%.*]] = load i16, ptr [[USE]], align 2
14349 // CHECK-NEXT:    [[TMP371:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP370]] monotonic, align 2
14350 // CHECK-NEXT:    [[TMP372:%.*]] = load i16, ptr [[USE]], align 2
14351 // CHECK-NEXT:    [[TMP373:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP372]] monotonic, align 2
14352 // CHECK-NEXT:    [[TMP374:%.*]] = load i16, ptr [[USE]], align 2
14353 // CHECK-NEXT:    [[TMP375:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP374]] monotonic, align 2
14354 // CHECK-NEXT:    [[TMP376:%.*]] = load i16, ptr [[USE]], align 2
14355 // CHECK-NEXT:    [[TMP377:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP376]] monotonic, align 2
14356 // CHECK-NEXT:    [[TMP378:%.*]] = load i16, ptr [[USE]], align 2
14357 // CHECK-NEXT:    [[TMP379:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP378]] monotonic, align 2
14358 // CHECK-NEXT:    [[TMP380:%.*]] = load i16, ptr [[USE]], align 2
14359 // CHECK-NEXT:    [[TMP381:%.*]] = load i16, ptr [[USD]], align 2
14360 // CHECK-NEXT:    [[TMP382:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP380]], i16 [[TMP381]] monotonic monotonic, align 2
14361 // CHECK-NEXT:    [[TMP383:%.*]] = load i16, ptr [[USE]], align 2
14362 // CHECK-NEXT:    [[TMP384:%.*]] = load i16, ptr [[USD]], align 2
14363 // CHECK-NEXT:    [[TMP385:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP383]], i16 [[TMP384]] monotonic monotonic, align 2
14364 // CHECK-NEXT:    [[TMP386:%.*]] = load i16, ptr [[USE]], align 2
14365 // CHECK-NEXT:    [[TMP387:%.*]] = load i16, ptr [[USD]], align 2
14366 // CHECK-NEXT:    [[TMP388:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP386]], i16 [[TMP387]] monotonic monotonic, align 2
14367 // CHECK-NEXT:    [[TMP389:%.*]] = load i16, ptr [[USE]], align 2
14368 // CHECK-NEXT:    [[TMP390:%.*]] = load i16, ptr [[USD]], align 2
14369 // CHECK-NEXT:    [[TMP391:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP389]], i16 [[TMP390]] monotonic monotonic, align 2
14370 // CHECK-NEXT:    [[TMP392:%.*]] = load i16, ptr [[SE]], align 2
14371 // CHECK-NEXT:    [[TMP393:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP392]] acq_rel, align 2
14372 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14373 // CHECK-NEXT:    [[TMP394:%.*]] = load i16, ptr [[SE]], align 2
14374 // CHECK-NEXT:    [[TMP395:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP394]] acq_rel, align 2
14375 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14376 // CHECK-NEXT:    [[TMP396:%.*]] = load i16, ptr [[SE]], align 2
14377 // CHECK-NEXT:    [[TMP397:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP396]] acq_rel, align 2
14378 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14379 // CHECK-NEXT:    [[TMP398:%.*]] = load i16, ptr [[SE]], align 2
14380 // CHECK-NEXT:    [[TMP399:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP398]] acq_rel, align 2
14381 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14382 // CHECK-NEXT:    [[TMP400:%.*]] = load i16, ptr [[SE]], align 2
14383 // CHECK-NEXT:    [[TMP401:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP400]] acq_rel, align 2
14384 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14385 // CHECK-NEXT:    [[TMP402:%.*]] = load i16, ptr [[SE]], align 2
14386 // CHECK-NEXT:    [[TMP403:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP402]] acq_rel, align 2
14387 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14388 // CHECK-NEXT:    [[TMP404:%.*]] = load i16, ptr [[SE]], align 2
14389 // CHECK-NEXT:    [[TMP405:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP404]] acq_rel, align 2
14390 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14391 // CHECK-NEXT:    [[TMP406:%.*]] = load i16, ptr [[SE]], align 2
14392 // CHECK-NEXT:    [[TMP407:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP406]] acq_rel, align 2
14393 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14394 // CHECK-NEXT:    [[TMP408:%.*]] = load i16, ptr [[SE]], align 2
14395 // CHECK-NEXT:    [[TMP409:%.*]] = load i16, ptr [[SD]], align 2
14396 // CHECK-NEXT:    [[TMP410:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP408]], i16 [[TMP409]] acq_rel acquire, align 2
14397 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14398 // CHECK-NEXT:    [[TMP411:%.*]] = load i16, ptr [[SE]], align 2
14399 // CHECK-NEXT:    [[TMP412:%.*]] = load i16, ptr [[SD]], align 2
14400 // CHECK-NEXT:    [[TMP413:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP411]], i16 [[TMP412]] acq_rel acquire, align 2
14401 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14402 // CHECK-NEXT:    [[TMP414:%.*]] = load i16, ptr [[SE]], align 2
14403 // CHECK-NEXT:    [[TMP415:%.*]] = load i16, ptr [[SD]], align 2
14404 // CHECK-NEXT:    [[TMP416:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP414]], i16 [[TMP415]] acq_rel acquire, align 2
14405 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14406 // CHECK-NEXT:    [[TMP417:%.*]] = load i16, ptr [[SE]], align 2
14407 // CHECK-NEXT:    [[TMP418:%.*]] = load i16, ptr [[SD]], align 2
14408 // CHECK-NEXT:    [[TMP419:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP417]], i16 [[TMP418]] acq_rel acquire, align 2
14409 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14410 // CHECK-NEXT:    [[TMP420:%.*]] = load i16, ptr [[USE]], align 2
14411 // CHECK-NEXT:    [[TMP421:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP420]] acq_rel, align 2
14412 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14413 // CHECK-NEXT:    [[TMP422:%.*]] = load i16, ptr [[USE]], align 2
14414 // CHECK-NEXT:    [[TMP423:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP422]] acq_rel, align 2
14415 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14416 // CHECK-NEXT:    [[TMP424:%.*]] = load i16, ptr [[USE]], align 2
14417 // CHECK-NEXT:    [[TMP425:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP424]] acq_rel, align 2
14418 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14419 // CHECK-NEXT:    [[TMP426:%.*]] = load i16, ptr [[USE]], align 2
14420 // CHECK-NEXT:    [[TMP427:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP426]] acq_rel, align 2
14421 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14422 // CHECK-NEXT:    [[TMP428:%.*]] = load i16, ptr [[USE]], align 2
14423 // CHECK-NEXT:    [[TMP429:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP428]] acq_rel, align 2
14424 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14425 // CHECK-NEXT:    [[TMP430:%.*]] = load i16, ptr [[USE]], align 2
14426 // CHECK-NEXT:    [[TMP431:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP430]] acq_rel, align 2
14427 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14428 // CHECK-NEXT:    [[TMP432:%.*]] = load i16, ptr [[USE]], align 2
14429 // CHECK-NEXT:    [[TMP433:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP432]] acq_rel, align 2
14430 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14431 // CHECK-NEXT:    [[TMP434:%.*]] = load i16, ptr [[USE]], align 2
14432 // CHECK-NEXT:    [[TMP435:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP434]] acq_rel, align 2
14433 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14434 // CHECK-NEXT:    [[TMP436:%.*]] = load i16, ptr [[USE]], align 2
14435 // CHECK-NEXT:    [[TMP437:%.*]] = load i16, ptr [[USD]], align 2
14436 // CHECK-NEXT:    [[TMP438:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP436]], i16 [[TMP437]] acq_rel acquire, align 2
14437 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14438 // CHECK-NEXT:    [[TMP439:%.*]] = load i16, ptr [[USE]], align 2
14439 // CHECK-NEXT:    [[TMP440:%.*]] = load i16, ptr [[USD]], align 2
14440 // CHECK-NEXT:    [[TMP441:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP439]], i16 [[TMP440]] acq_rel acquire, align 2
14441 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14442 // CHECK-NEXT:    [[TMP442:%.*]] = load i16, ptr [[USE]], align 2
14443 // CHECK-NEXT:    [[TMP443:%.*]] = load i16, ptr [[USD]], align 2
14444 // CHECK-NEXT:    [[TMP444:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP442]], i16 [[TMP443]] acq_rel acquire, align 2
14445 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14446 // CHECK-NEXT:    [[TMP445:%.*]] = load i16, ptr [[USE]], align 2
14447 // CHECK-NEXT:    [[TMP446:%.*]] = load i16, ptr [[USD]], align 2
14448 // CHECK-NEXT:    [[TMP447:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP445]], i16 [[TMP446]] acq_rel acquire, align 2
14449 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14450 // CHECK-NEXT:    [[TMP448:%.*]] = load i16, ptr [[SE]], align 2
14451 // CHECK-NEXT:    [[TMP449:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP448]] acquire, align 2
14452 // CHECK-NEXT:    [[TMP450:%.*]] = load i16, ptr [[SE]], align 2
14453 // CHECK-NEXT:    [[TMP451:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP450]] acquire, align 2
14454 // CHECK-NEXT:    [[TMP452:%.*]] = load i16, ptr [[SE]], align 2
14455 // CHECK-NEXT:    [[TMP453:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP452]] acquire, align 2
14456 // CHECK-NEXT:    [[TMP454:%.*]] = load i16, ptr [[SE]], align 2
14457 // CHECK-NEXT:    [[TMP455:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP454]] acquire, align 2
14458 // CHECK-NEXT:    [[TMP456:%.*]] = load i16, ptr [[SE]], align 2
14459 // CHECK-NEXT:    [[TMP457:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP456]] acquire, align 2
14460 // CHECK-NEXT:    [[TMP458:%.*]] = load i16, ptr [[SE]], align 2
14461 // CHECK-NEXT:    [[TMP459:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP458]] acquire, align 2
14462 // CHECK-NEXT:    [[TMP460:%.*]] = load i16, ptr [[SE]], align 2
14463 // CHECK-NEXT:    [[TMP461:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP460]] acquire, align 2
14464 // CHECK-NEXT:    [[TMP462:%.*]] = load i16, ptr [[SE]], align 2
14465 // CHECK-NEXT:    [[TMP463:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP462]] acquire, align 2
14466 // CHECK-NEXT:    [[TMP464:%.*]] = load i16, ptr [[SE]], align 2
14467 // CHECK-NEXT:    [[TMP465:%.*]] = load i16, ptr [[SD]], align 2
14468 // CHECK-NEXT:    [[TMP466:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP464]], i16 [[TMP465]] acquire acquire, align 2
14469 // CHECK-NEXT:    [[TMP467:%.*]] = load i16, ptr [[SE]], align 2
14470 // CHECK-NEXT:    [[TMP468:%.*]] = load i16, ptr [[SD]], align 2
14471 // CHECK-NEXT:    [[TMP469:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP467]], i16 [[TMP468]] acquire acquire, align 2
14472 // CHECK-NEXT:    [[TMP470:%.*]] = load i16, ptr [[SE]], align 2
14473 // CHECK-NEXT:    [[TMP471:%.*]] = load i16, ptr [[SD]], align 2
14474 // CHECK-NEXT:    [[TMP472:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP470]], i16 [[TMP471]] acquire acquire, align 2
14475 // CHECK-NEXT:    [[TMP473:%.*]] = load i16, ptr [[SE]], align 2
14476 // CHECK-NEXT:    [[TMP474:%.*]] = load i16, ptr [[SD]], align 2
14477 // CHECK-NEXT:    [[TMP475:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP473]], i16 [[TMP474]] acquire acquire, align 2
14478 // CHECK-NEXT:    [[TMP476:%.*]] = load i16, ptr [[USE]], align 2
14479 // CHECK-NEXT:    [[TMP477:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP476]] acquire, align 2
14480 // CHECK-NEXT:    [[TMP478:%.*]] = load i16, ptr [[USE]], align 2
14481 // CHECK-NEXT:    [[TMP479:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP478]] acquire, align 2
14482 // CHECK-NEXT:    [[TMP480:%.*]] = load i16, ptr [[USE]], align 2
14483 // CHECK-NEXT:    [[TMP481:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP480]] acquire, align 2
14484 // CHECK-NEXT:    [[TMP482:%.*]] = load i16, ptr [[USE]], align 2
14485 // CHECK-NEXT:    [[TMP483:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP482]] acquire, align 2
14486 // CHECK-NEXT:    [[TMP484:%.*]] = load i16, ptr [[USE]], align 2
14487 // CHECK-NEXT:    [[TMP485:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP484]] acquire, align 2
14488 // CHECK-NEXT:    [[TMP486:%.*]] = load i16, ptr [[USE]], align 2
14489 // CHECK-NEXT:    [[TMP487:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP486]] acquire, align 2
14490 // CHECK-NEXT:    [[TMP488:%.*]] = load i16, ptr [[USE]], align 2
14491 // CHECK-NEXT:    [[TMP489:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP488]] acquire, align 2
14492 // CHECK-NEXT:    [[TMP490:%.*]] = load i16, ptr [[USE]], align 2
14493 // CHECK-NEXT:    [[TMP491:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP490]] acquire, align 2
14494 // CHECK-NEXT:    [[TMP492:%.*]] = load i16, ptr [[USE]], align 2
14495 // CHECK-NEXT:    [[TMP493:%.*]] = load i16, ptr [[USD]], align 2
14496 // CHECK-NEXT:    [[TMP494:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP492]], i16 [[TMP493]] acquire acquire, align 2
14497 // CHECK-NEXT:    [[TMP495:%.*]] = load i16, ptr [[USE]], align 2
14498 // CHECK-NEXT:    [[TMP496:%.*]] = load i16, ptr [[USD]], align 2
14499 // CHECK-NEXT:    [[TMP497:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP495]], i16 [[TMP496]] acquire acquire, align 2
14500 // CHECK-NEXT:    [[TMP498:%.*]] = load i16, ptr [[USE]], align 2
14501 // CHECK-NEXT:    [[TMP499:%.*]] = load i16, ptr [[USD]], align 2
14502 // CHECK-NEXT:    [[TMP500:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP498]], i16 [[TMP499]] acquire acquire, align 2
14503 // CHECK-NEXT:    [[TMP501:%.*]] = load i16, ptr [[USE]], align 2
14504 // CHECK-NEXT:    [[TMP502:%.*]] = load i16, ptr [[USD]], align 2
14505 // CHECK-NEXT:    [[TMP503:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP501]], i16 [[TMP502]] acquire acquire, align 2
14506 // CHECK-NEXT:    [[TMP504:%.*]] = load i16, ptr [[SE]], align 2
14507 // CHECK-NEXT:    [[TMP505:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP504]] monotonic, align 2
14508 // CHECK-NEXT:    [[TMP506:%.*]] = load i16, ptr [[SE]], align 2
14509 // CHECK-NEXT:    [[TMP507:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP506]] monotonic, align 2
14510 // CHECK-NEXT:    [[TMP508:%.*]] = load i16, ptr [[SE]], align 2
14511 // CHECK-NEXT:    [[TMP509:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP508]] monotonic, align 2
14512 // CHECK-NEXT:    [[TMP510:%.*]] = load i16, ptr [[SE]], align 2
14513 // CHECK-NEXT:    [[TMP511:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP510]] monotonic, align 2
14514 // CHECK-NEXT:    [[TMP512:%.*]] = load i16, ptr [[SE]], align 2
14515 // CHECK-NEXT:    [[TMP513:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP512]] monotonic, align 2
14516 // CHECK-NEXT:    [[TMP514:%.*]] = load i16, ptr [[SE]], align 2
14517 // CHECK-NEXT:    [[TMP515:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP514]] monotonic, align 2
14518 // CHECK-NEXT:    [[TMP516:%.*]] = load i16, ptr [[SE]], align 2
14519 // CHECK-NEXT:    [[TMP517:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP516]] monotonic, align 2
14520 // CHECK-NEXT:    [[TMP518:%.*]] = load i16, ptr [[SE]], align 2
14521 // CHECK-NEXT:    [[TMP519:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP518]] monotonic, align 2
14522 // CHECK-NEXT:    [[TMP520:%.*]] = load i16, ptr [[SE]], align 2
14523 // CHECK-NEXT:    [[TMP521:%.*]] = load i16, ptr [[SD]], align 2
14524 // CHECK-NEXT:    [[TMP522:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP520]], i16 [[TMP521]] monotonic monotonic, align 2
14525 // CHECK-NEXT:    [[TMP523:%.*]] = load i16, ptr [[SE]], align 2
14526 // CHECK-NEXT:    [[TMP524:%.*]] = load i16, ptr [[SD]], align 2
14527 // CHECK-NEXT:    [[TMP525:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP523]], i16 [[TMP524]] monotonic monotonic, align 2
14528 // CHECK-NEXT:    [[TMP526:%.*]] = load i16, ptr [[SE]], align 2
14529 // CHECK-NEXT:    [[TMP527:%.*]] = load i16, ptr [[SD]], align 2
14530 // CHECK-NEXT:    [[TMP528:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP526]], i16 [[TMP527]] monotonic monotonic, align 2
14531 // CHECK-NEXT:    [[TMP529:%.*]] = load i16, ptr [[SE]], align 2
14532 // CHECK-NEXT:    [[TMP530:%.*]] = load i16, ptr [[SD]], align 2
14533 // CHECK-NEXT:    [[TMP531:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP529]], i16 [[TMP530]] monotonic monotonic, align 2
14534 // CHECK-NEXT:    [[TMP532:%.*]] = load i16, ptr [[USE]], align 2
14535 // CHECK-NEXT:    [[TMP533:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP532]] monotonic, align 2
14536 // CHECK-NEXT:    [[TMP534:%.*]] = load i16, ptr [[USE]], align 2
14537 // CHECK-NEXT:    [[TMP535:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP534]] monotonic, align 2
14538 // CHECK-NEXT:    [[TMP536:%.*]] = load i16, ptr [[USE]], align 2
14539 // CHECK-NEXT:    [[TMP537:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP536]] monotonic, align 2
14540 // CHECK-NEXT:    [[TMP538:%.*]] = load i16, ptr [[USE]], align 2
14541 // CHECK-NEXT:    [[TMP539:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP538]] monotonic, align 2
14542 // CHECK-NEXT:    [[TMP540:%.*]] = load i16, ptr [[USE]], align 2
14543 // CHECK-NEXT:    [[TMP541:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP540]] monotonic, align 2
14544 // CHECK-NEXT:    [[TMP542:%.*]] = load i16, ptr [[USE]], align 2
14545 // CHECK-NEXT:    [[TMP543:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP542]] monotonic, align 2
14546 // CHECK-NEXT:    [[TMP544:%.*]] = load i16, ptr [[USE]], align 2
14547 // CHECK-NEXT:    [[TMP545:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP544]] monotonic, align 2
14548 // CHECK-NEXT:    [[TMP546:%.*]] = load i16, ptr [[USE]], align 2
14549 // CHECK-NEXT:    [[TMP547:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP546]] monotonic, align 2
14550 // CHECK-NEXT:    [[TMP548:%.*]] = load i16, ptr [[USE]], align 2
14551 // CHECK-NEXT:    [[TMP549:%.*]] = load i16, ptr [[USD]], align 2
14552 // CHECK-NEXT:    [[TMP550:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP548]], i16 [[TMP549]] monotonic monotonic, align 2
14553 // CHECK-NEXT:    [[TMP551:%.*]] = load i16, ptr [[USE]], align 2
14554 // CHECK-NEXT:    [[TMP552:%.*]] = load i16, ptr [[USD]], align 2
14555 // CHECK-NEXT:    [[TMP553:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP551]], i16 [[TMP552]] monotonic monotonic, align 2
14556 // CHECK-NEXT:    [[TMP554:%.*]] = load i16, ptr [[USE]], align 2
14557 // CHECK-NEXT:    [[TMP555:%.*]] = load i16, ptr [[USD]], align 2
14558 // CHECK-NEXT:    [[TMP556:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP554]], i16 [[TMP555]] monotonic monotonic, align 2
14559 // CHECK-NEXT:    [[TMP557:%.*]] = load i16, ptr [[USE]], align 2
14560 // CHECK-NEXT:    [[TMP558:%.*]] = load i16, ptr [[USD]], align 2
14561 // CHECK-NEXT:    [[TMP559:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP557]], i16 [[TMP558]] monotonic monotonic, align 2
14562 // CHECK-NEXT:    [[TMP560:%.*]] = load i16, ptr [[SE]], align 2
14563 // CHECK-NEXT:    [[TMP561:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP560]] release, align 2
14564 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14565 // CHECK-NEXT:    [[TMP562:%.*]] = load i16, ptr [[SE]], align 2
14566 // CHECK-NEXT:    [[TMP563:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP562]] release, align 2
14567 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14568 // CHECK-NEXT:    [[TMP564:%.*]] = load i16, ptr [[SE]], align 2
14569 // CHECK-NEXT:    [[TMP565:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP564]] release, align 2
14570 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14571 // CHECK-NEXT:    [[TMP566:%.*]] = load i16, ptr [[SE]], align 2
14572 // CHECK-NEXT:    [[TMP567:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP566]] release, align 2
14573 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14574 // CHECK-NEXT:    [[TMP568:%.*]] = load i16, ptr [[SE]], align 2
14575 // CHECK-NEXT:    [[TMP569:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP568]] release, align 2
14576 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14577 // CHECK-NEXT:    [[TMP570:%.*]] = load i16, ptr [[SE]], align 2
14578 // CHECK-NEXT:    [[TMP571:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP570]] release, align 2
14579 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14580 // CHECK-NEXT:    [[TMP572:%.*]] = load i16, ptr [[SE]], align 2
14581 // CHECK-NEXT:    [[TMP573:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP572]] release, align 2
14582 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14583 // CHECK-NEXT:    [[TMP574:%.*]] = load i16, ptr [[SE]], align 2
14584 // CHECK-NEXT:    [[TMP575:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP574]] release, align 2
14585 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14586 // CHECK-NEXT:    [[TMP576:%.*]] = load i16, ptr [[SE]], align 2
14587 // CHECK-NEXT:    [[TMP577:%.*]] = load i16, ptr [[SD]], align 2
14588 // CHECK-NEXT:    [[TMP578:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP576]], i16 [[TMP577]] release monotonic, align 2
14589 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14590 // CHECK-NEXT:    [[TMP579:%.*]] = load i16, ptr [[SE]], align 2
14591 // CHECK-NEXT:    [[TMP580:%.*]] = load i16, ptr [[SD]], align 2
14592 // CHECK-NEXT:    [[TMP581:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP579]], i16 [[TMP580]] release monotonic, align 2
14593 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14594 // CHECK-NEXT:    [[TMP582:%.*]] = load i16, ptr [[SE]], align 2
14595 // CHECK-NEXT:    [[TMP583:%.*]] = load i16, ptr [[SD]], align 2
14596 // CHECK-NEXT:    [[TMP584:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP582]], i16 [[TMP583]] release monotonic, align 2
14597 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14598 // CHECK-NEXT:    [[TMP585:%.*]] = load i16, ptr [[SE]], align 2
14599 // CHECK-NEXT:    [[TMP586:%.*]] = load i16, ptr [[SD]], align 2
14600 // CHECK-NEXT:    [[TMP587:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP585]], i16 [[TMP586]] release monotonic, align 2
14601 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14602 // CHECK-NEXT:    [[TMP588:%.*]] = load i16, ptr [[USE]], align 2
14603 // CHECK-NEXT:    [[TMP589:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP588]] release, align 2
14604 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14605 // CHECK-NEXT:    [[TMP590:%.*]] = load i16, ptr [[USE]], align 2
14606 // CHECK-NEXT:    [[TMP591:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP590]] release, align 2
14607 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14608 // CHECK-NEXT:    [[TMP592:%.*]] = load i16, ptr [[USE]], align 2
14609 // CHECK-NEXT:    [[TMP593:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP592]] release, align 2
14610 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14611 // CHECK-NEXT:    [[TMP594:%.*]] = load i16, ptr [[USE]], align 2
14612 // CHECK-NEXT:    [[TMP595:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP594]] release, align 2
14613 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14614 // CHECK-NEXT:    [[TMP596:%.*]] = load i16, ptr [[USE]], align 2
14615 // CHECK-NEXT:    [[TMP597:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP596]] release, align 2
14616 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14617 // CHECK-NEXT:    [[TMP598:%.*]] = load i16, ptr [[USE]], align 2
14618 // CHECK-NEXT:    [[TMP599:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP598]] release, align 2
14619 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14620 // CHECK-NEXT:    [[TMP600:%.*]] = load i16, ptr [[USE]], align 2
14621 // CHECK-NEXT:    [[TMP601:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP600]] release, align 2
14622 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14623 // CHECK-NEXT:    [[TMP602:%.*]] = load i16, ptr [[USE]], align 2
14624 // CHECK-NEXT:    [[TMP603:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP602]] release, align 2
14625 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14626 // CHECK-NEXT:    [[TMP604:%.*]] = load i16, ptr [[USE]], align 2
14627 // CHECK-NEXT:    [[TMP605:%.*]] = load i16, ptr [[USD]], align 2
14628 // CHECK-NEXT:    [[TMP606:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP604]], i16 [[TMP605]] release monotonic, align 2
14629 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14630 // CHECK-NEXT:    [[TMP607:%.*]] = load i16, ptr [[USE]], align 2
14631 // CHECK-NEXT:    [[TMP608:%.*]] = load i16, ptr [[USD]], align 2
14632 // CHECK-NEXT:    [[TMP609:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP607]], i16 [[TMP608]] release monotonic, align 2
14633 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14634 // CHECK-NEXT:    [[TMP610:%.*]] = load i16, ptr [[USE]], align 2
14635 // CHECK-NEXT:    [[TMP611:%.*]] = load i16, ptr [[USD]], align 2
14636 // CHECK-NEXT:    [[TMP612:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP610]], i16 [[TMP611]] release monotonic, align 2
14637 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14638 // CHECK-NEXT:    [[TMP613:%.*]] = load i16, ptr [[USE]], align 2
14639 // CHECK-NEXT:    [[TMP614:%.*]] = load i16, ptr [[USD]], align 2
14640 // CHECK-NEXT:    [[TMP615:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP613]], i16 [[TMP614]] release monotonic, align 2
14641 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14642 // CHECK-NEXT:    [[TMP616:%.*]] = load i16, ptr [[SE]], align 2
14643 // CHECK-NEXT:    [[TMP617:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP616]] seq_cst, align 2
14644 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14645 // CHECK-NEXT:    [[TMP618:%.*]] = load i16, ptr [[SE]], align 2
14646 // CHECK-NEXT:    [[TMP619:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP618]] seq_cst, align 2
14647 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14648 // CHECK-NEXT:    [[TMP620:%.*]] = load i16, ptr [[SE]], align 2
14649 // CHECK-NEXT:    [[TMP621:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP620]] seq_cst, align 2
14650 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14651 // CHECK-NEXT:    [[TMP622:%.*]] = load i16, ptr [[SE]], align 2
14652 // CHECK-NEXT:    [[TMP623:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP622]] seq_cst, align 2
14653 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14654 // CHECK-NEXT:    [[TMP624:%.*]] = load i16, ptr [[SE]], align 2
14655 // CHECK-NEXT:    [[TMP625:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP624]] seq_cst, align 2
14656 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14657 // CHECK-NEXT:    [[TMP626:%.*]] = load i16, ptr [[SE]], align 2
14658 // CHECK-NEXT:    [[TMP627:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP626]] seq_cst, align 2
14659 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14660 // CHECK-NEXT:    [[TMP628:%.*]] = load i16, ptr [[SE]], align 2
14661 // CHECK-NEXT:    [[TMP629:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP628]] seq_cst, align 2
14662 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14663 // CHECK-NEXT:    [[TMP630:%.*]] = load i16, ptr [[SE]], align 2
14664 // CHECK-NEXT:    [[TMP631:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP630]] seq_cst, align 2
14665 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14666 // CHECK-NEXT:    [[TMP632:%.*]] = load i16, ptr [[SE]], align 2
14667 // CHECK-NEXT:    [[TMP633:%.*]] = load i16, ptr [[SD]], align 2
14668 // CHECK-NEXT:    [[TMP634:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP632]], i16 [[TMP633]] seq_cst seq_cst, align 2
14669 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14670 // CHECK-NEXT:    [[TMP635:%.*]] = load i16, ptr [[SE]], align 2
14671 // CHECK-NEXT:    [[TMP636:%.*]] = load i16, ptr [[SD]], align 2
14672 // CHECK-NEXT:    [[TMP637:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP635]], i16 [[TMP636]] seq_cst seq_cst, align 2
14673 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14674 // CHECK-NEXT:    [[TMP638:%.*]] = load i16, ptr [[SE]], align 2
14675 // CHECK-NEXT:    [[TMP639:%.*]] = load i16, ptr [[SD]], align 2
14676 // CHECK-NEXT:    [[TMP640:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP638]], i16 [[TMP639]] seq_cst seq_cst, align 2
14677 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14678 // CHECK-NEXT:    [[TMP641:%.*]] = load i16, ptr [[SE]], align 2
14679 // CHECK-NEXT:    [[TMP642:%.*]] = load i16, ptr [[SD]], align 2
14680 // CHECK-NEXT:    [[TMP643:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP641]], i16 [[TMP642]] seq_cst seq_cst, align 2
14681 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14682 // CHECK-NEXT:    [[TMP644:%.*]] = load i16, ptr [[USE]], align 2
14683 // CHECK-NEXT:    [[TMP645:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP644]] seq_cst, align 2
14684 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14685 // CHECK-NEXT:    [[TMP646:%.*]] = load i16, ptr [[USE]], align 2
14686 // CHECK-NEXT:    [[TMP647:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP646]] seq_cst, align 2
14687 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14688 // CHECK-NEXT:    [[TMP648:%.*]] = load i16, ptr [[USE]], align 2
14689 // CHECK-NEXT:    [[TMP649:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP648]] seq_cst, align 2
14690 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14691 // CHECK-NEXT:    [[TMP650:%.*]] = load i16, ptr [[USE]], align 2
14692 // CHECK-NEXT:    [[TMP651:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP650]] seq_cst, align 2
14693 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14694 // CHECK-NEXT:    [[TMP652:%.*]] = load i16, ptr [[USE]], align 2
14695 // CHECK-NEXT:    [[TMP653:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP652]] seq_cst, align 2
14696 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14697 // CHECK-NEXT:    [[TMP654:%.*]] = load i16, ptr [[USE]], align 2
14698 // CHECK-NEXT:    [[TMP655:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP654]] seq_cst, align 2
14699 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14700 // CHECK-NEXT:    [[TMP656:%.*]] = load i16, ptr [[USE]], align 2
14701 // CHECK-NEXT:    [[TMP657:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP656]] seq_cst, align 2
14702 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14703 // CHECK-NEXT:    [[TMP658:%.*]] = load i16, ptr [[USE]], align 2
14704 // CHECK-NEXT:    [[TMP659:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP658]] seq_cst, align 2
14705 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14706 // CHECK-NEXT:    [[TMP660:%.*]] = load i16, ptr [[USE]], align 2
14707 // CHECK-NEXT:    [[TMP661:%.*]] = load i16, ptr [[USD]], align 2
14708 // CHECK-NEXT:    [[TMP662:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP660]], i16 [[TMP661]] seq_cst seq_cst, align 2
14709 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14710 // CHECK-NEXT:    [[TMP663:%.*]] = load i16, ptr [[USE]], align 2
14711 // CHECK-NEXT:    [[TMP664:%.*]] = load i16, ptr [[USD]], align 2
14712 // CHECK-NEXT:    [[TMP665:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP663]], i16 [[TMP664]] seq_cst seq_cst, align 2
14713 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14714 // CHECK-NEXT:    [[TMP666:%.*]] = load i16, ptr [[USE]], align 2
14715 // CHECK-NEXT:    [[TMP667:%.*]] = load i16, ptr [[USD]], align 2
14716 // CHECK-NEXT:    [[TMP668:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP666]], i16 [[TMP667]] seq_cst seq_cst, align 2
14717 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14718 // CHECK-NEXT:    [[TMP669:%.*]] = load i16, ptr [[USE]], align 2
14719 // CHECK-NEXT:    [[TMP670:%.*]] = load i16, ptr [[USD]], align 2
14720 // CHECK-NEXT:    [[TMP671:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP669]], i16 [[TMP670]] seq_cst seq_cst, align 2
14721 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14722 // CHECK-NEXT:    [[TMP672:%.*]] = load i32, ptr [[IE]], align 4
14723 // CHECK-NEXT:    [[TMP673:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP672]] monotonic, align 4
14724 // CHECK-NEXT:    [[TMP674:%.*]] = load i32, ptr [[IE]], align 4
14725 // CHECK-NEXT:    [[TMP675:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP674]] monotonic, align 4
14726 // CHECK-NEXT:    [[TMP676:%.*]] = load i32, ptr [[IE]], align 4
14727 // CHECK-NEXT:    [[TMP677:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP676]] monotonic, align 4
14728 // CHECK-NEXT:    [[TMP678:%.*]] = load i32, ptr [[IE]], align 4
14729 // CHECK-NEXT:    [[TMP679:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP678]] monotonic, align 4
14730 // CHECK-NEXT:    [[TMP680:%.*]] = load i32, ptr [[IE]], align 4
14731 // CHECK-NEXT:    [[TMP681:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP680]] monotonic, align 4
14732 // CHECK-NEXT:    [[TMP682:%.*]] = load i32, ptr [[IE]], align 4
14733 // CHECK-NEXT:    [[TMP683:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP682]] monotonic, align 4
14734 // CHECK-NEXT:    [[TMP684:%.*]] = load i32, ptr [[IE]], align 4
14735 // CHECK-NEXT:    [[TMP685:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP684]] monotonic, align 4
14736 // CHECK-NEXT:    [[TMP686:%.*]] = load i32, ptr [[IE]], align 4
14737 // CHECK-NEXT:    [[TMP687:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP686]] monotonic, align 4
14738 // CHECK-NEXT:    [[TMP688:%.*]] = load i32, ptr [[IE]], align 4
14739 // CHECK-NEXT:    [[TMP689:%.*]] = load i32, ptr [[ID]], align 4
14740 // CHECK-NEXT:    [[TMP690:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP688]], i32 [[TMP689]] monotonic monotonic, align 4
14741 // CHECK-NEXT:    [[TMP691:%.*]] = load i32, ptr [[IE]], align 4
14742 // CHECK-NEXT:    [[TMP692:%.*]] = load i32, ptr [[ID]], align 4
14743 // CHECK-NEXT:    [[TMP693:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP691]], i32 [[TMP692]] monotonic monotonic, align 4
14744 // CHECK-NEXT:    [[TMP694:%.*]] = load i32, ptr [[IE]], align 4
14745 // CHECK-NEXT:    [[TMP695:%.*]] = load i32, ptr [[ID]], align 4
14746 // CHECK-NEXT:    [[TMP696:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP694]], i32 [[TMP695]] monotonic monotonic, align 4
14747 // CHECK-NEXT:    [[TMP697:%.*]] = load i32, ptr [[IE]], align 4
14748 // CHECK-NEXT:    [[TMP698:%.*]] = load i32, ptr [[ID]], align 4
14749 // CHECK-NEXT:    [[TMP699:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP697]], i32 [[TMP698]] monotonic monotonic, align 4
14750 // CHECK-NEXT:    [[TMP700:%.*]] = load i32, ptr [[UIE]], align 4
14751 // CHECK-NEXT:    [[TMP701:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP700]] monotonic, align 4
14752 // CHECK-NEXT:    [[TMP702:%.*]] = load i32, ptr [[UIE]], align 4
14753 // CHECK-NEXT:    [[TMP703:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP702]] monotonic, align 4
14754 // CHECK-NEXT:    [[TMP704:%.*]] = load i32, ptr [[UIE]], align 4
14755 // CHECK-NEXT:    [[TMP705:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP704]] monotonic, align 4
14756 // CHECK-NEXT:    [[TMP706:%.*]] = load i32, ptr [[UIE]], align 4
14757 // CHECK-NEXT:    [[TMP707:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP706]] monotonic, align 4
14758 // CHECK-NEXT:    [[TMP708:%.*]] = load i32, ptr [[UIE]], align 4
14759 // CHECK-NEXT:    [[TMP709:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP708]] monotonic, align 4
14760 // CHECK-NEXT:    [[TMP710:%.*]] = load i32, ptr [[UIE]], align 4
14761 // CHECK-NEXT:    [[TMP711:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP710]] monotonic, align 4
14762 // CHECK-NEXT:    [[TMP712:%.*]] = load i32, ptr [[UIE]], align 4
14763 // CHECK-NEXT:    [[TMP713:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP712]] monotonic, align 4
14764 // CHECK-NEXT:    [[TMP714:%.*]] = load i32, ptr [[UIE]], align 4
14765 // CHECK-NEXT:    [[TMP715:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP714]] monotonic, align 4
14766 // CHECK-NEXT:    [[TMP716:%.*]] = load i32, ptr [[UIE]], align 4
14767 // CHECK-NEXT:    [[TMP717:%.*]] = load i32, ptr [[UID]], align 4
14768 // CHECK-NEXT:    [[TMP718:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP716]], i32 [[TMP717]] monotonic monotonic, align 4
14769 // CHECK-NEXT:    [[TMP719:%.*]] = load i32, ptr [[UIE]], align 4
14770 // CHECK-NEXT:    [[TMP720:%.*]] = load i32, ptr [[UID]], align 4
14771 // CHECK-NEXT:    [[TMP721:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP719]], i32 [[TMP720]] monotonic monotonic, align 4
14772 // CHECK-NEXT:    [[TMP722:%.*]] = load i32, ptr [[UIE]], align 4
14773 // CHECK-NEXT:    [[TMP723:%.*]] = load i32, ptr [[UID]], align 4
14774 // CHECK-NEXT:    [[TMP724:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP722]], i32 [[TMP723]] monotonic monotonic, align 4
14775 // CHECK-NEXT:    [[TMP725:%.*]] = load i32, ptr [[UIE]], align 4
14776 // CHECK-NEXT:    [[TMP726:%.*]] = load i32, ptr [[UID]], align 4
14777 // CHECK-NEXT:    [[TMP727:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP725]], i32 [[TMP726]] monotonic monotonic, align 4
14778 // CHECK-NEXT:    [[TMP728:%.*]] = load i32, ptr [[IE]], align 4
14779 // CHECK-NEXT:    [[TMP729:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP728]] acq_rel, align 4
14780 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14781 // CHECK-NEXT:    [[TMP730:%.*]] = load i32, ptr [[IE]], align 4
14782 // CHECK-NEXT:    [[TMP731:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP730]] acq_rel, align 4
14783 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14784 // CHECK-NEXT:    [[TMP732:%.*]] = load i32, ptr [[IE]], align 4
14785 // CHECK-NEXT:    [[TMP733:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP732]] acq_rel, align 4
14786 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14787 // CHECK-NEXT:    [[TMP734:%.*]] = load i32, ptr [[IE]], align 4
14788 // CHECK-NEXT:    [[TMP735:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP734]] acq_rel, align 4
14789 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14790 // CHECK-NEXT:    [[TMP736:%.*]] = load i32, ptr [[IE]], align 4
14791 // CHECK-NEXT:    [[TMP737:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP736]] acq_rel, align 4
14792 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14793 // CHECK-NEXT:    [[TMP738:%.*]] = load i32, ptr [[IE]], align 4
14794 // CHECK-NEXT:    [[TMP739:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP738]] acq_rel, align 4
14795 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14796 // CHECK-NEXT:    [[TMP740:%.*]] = load i32, ptr [[IE]], align 4
14797 // CHECK-NEXT:    [[TMP741:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP740]] acq_rel, align 4
14798 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14799 // CHECK-NEXT:    [[TMP742:%.*]] = load i32, ptr [[IE]], align 4
14800 // CHECK-NEXT:    [[TMP743:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP742]] acq_rel, align 4
14801 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14802 // CHECK-NEXT:    [[TMP744:%.*]] = load i32, ptr [[IE]], align 4
14803 // CHECK-NEXT:    [[TMP745:%.*]] = load i32, ptr [[ID]], align 4
14804 // CHECK-NEXT:    [[TMP746:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP744]], i32 [[TMP745]] acq_rel acquire, align 4
14805 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14806 // CHECK-NEXT:    [[TMP747:%.*]] = load i32, ptr [[IE]], align 4
14807 // CHECK-NEXT:    [[TMP748:%.*]] = load i32, ptr [[ID]], align 4
14808 // CHECK-NEXT:    [[TMP749:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP747]], i32 [[TMP748]] acq_rel acquire, align 4
14809 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14810 // CHECK-NEXT:    [[TMP750:%.*]] = load i32, ptr [[IE]], align 4
14811 // CHECK-NEXT:    [[TMP751:%.*]] = load i32, ptr [[ID]], align 4
14812 // CHECK-NEXT:    [[TMP752:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP750]], i32 [[TMP751]] acq_rel acquire, align 4
14813 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14814 // CHECK-NEXT:    [[TMP753:%.*]] = load i32, ptr [[IE]], align 4
14815 // CHECK-NEXT:    [[TMP754:%.*]] = load i32, ptr [[ID]], align 4
14816 // CHECK-NEXT:    [[TMP755:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP753]], i32 [[TMP754]] acq_rel acquire, align 4
14817 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14818 // CHECK-NEXT:    [[TMP756:%.*]] = load i32, ptr [[UIE]], align 4
14819 // CHECK-NEXT:    [[TMP757:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP756]] acq_rel, align 4
14820 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14821 // CHECK-NEXT:    [[TMP758:%.*]] = load i32, ptr [[UIE]], align 4
14822 // CHECK-NEXT:    [[TMP759:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP758]] acq_rel, align 4
14823 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14824 // CHECK-NEXT:    [[TMP760:%.*]] = load i32, ptr [[UIE]], align 4
14825 // CHECK-NEXT:    [[TMP761:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP760]] acq_rel, align 4
14826 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14827 // CHECK-NEXT:    [[TMP762:%.*]] = load i32, ptr [[UIE]], align 4
14828 // CHECK-NEXT:    [[TMP763:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP762]] acq_rel, align 4
14829 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14830 // CHECK-NEXT:    [[TMP764:%.*]] = load i32, ptr [[UIE]], align 4
14831 // CHECK-NEXT:    [[TMP765:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP764]] acq_rel, align 4
14832 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14833 // CHECK-NEXT:    [[TMP766:%.*]] = load i32, ptr [[UIE]], align 4
14834 // CHECK-NEXT:    [[TMP767:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP766]] acq_rel, align 4
14835 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14836 // CHECK-NEXT:    [[TMP768:%.*]] = load i32, ptr [[UIE]], align 4
14837 // CHECK-NEXT:    [[TMP769:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP768]] acq_rel, align 4
14838 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14839 // CHECK-NEXT:    [[TMP770:%.*]] = load i32, ptr [[UIE]], align 4
14840 // CHECK-NEXT:    [[TMP771:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP770]] acq_rel, align 4
14841 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14842 // CHECK-NEXT:    [[TMP772:%.*]] = load i32, ptr [[UIE]], align 4
14843 // CHECK-NEXT:    [[TMP773:%.*]] = load i32, ptr [[UID]], align 4
14844 // CHECK-NEXT:    [[TMP774:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP772]], i32 [[TMP773]] acq_rel acquire, align 4
14845 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14846 // CHECK-NEXT:    [[TMP775:%.*]] = load i32, ptr [[UIE]], align 4
14847 // CHECK-NEXT:    [[TMP776:%.*]] = load i32, ptr [[UID]], align 4
14848 // CHECK-NEXT:    [[TMP777:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP775]], i32 [[TMP776]] acq_rel acquire, align 4
14849 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14850 // CHECK-NEXT:    [[TMP778:%.*]] = load i32, ptr [[UIE]], align 4
14851 // CHECK-NEXT:    [[TMP779:%.*]] = load i32, ptr [[UID]], align 4
14852 // CHECK-NEXT:    [[TMP780:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP778]], i32 [[TMP779]] acq_rel acquire, align 4
14853 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14854 // CHECK-NEXT:    [[TMP781:%.*]] = load i32, ptr [[UIE]], align 4
14855 // CHECK-NEXT:    [[TMP782:%.*]] = load i32, ptr [[UID]], align 4
14856 // CHECK-NEXT:    [[TMP783:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP781]], i32 [[TMP782]] acq_rel acquire, align 4
14857 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14858 // CHECK-NEXT:    [[TMP784:%.*]] = load i32, ptr [[IE]], align 4
14859 // CHECK-NEXT:    [[TMP785:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP784]] acquire, align 4
14860 // CHECK-NEXT:    [[TMP786:%.*]] = load i32, ptr [[IE]], align 4
14861 // CHECK-NEXT:    [[TMP787:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP786]] acquire, align 4
14862 // CHECK-NEXT:    [[TMP788:%.*]] = load i32, ptr [[IE]], align 4
14863 // CHECK-NEXT:    [[TMP789:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP788]] acquire, align 4
14864 // CHECK-NEXT:    [[TMP790:%.*]] = load i32, ptr [[IE]], align 4
14865 // CHECK-NEXT:    [[TMP791:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP790]] acquire, align 4
14866 // CHECK-NEXT:    [[TMP792:%.*]] = load i32, ptr [[IE]], align 4
14867 // CHECK-NEXT:    [[TMP793:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP792]] acquire, align 4
14868 // CHECK-NEXT:    [[TMP794:%.*]] = load i32, ptr [[IE]], align 4
14869 // CHECK-NEXT:    [[TMP795:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP794]] acquire, align 4
14870 // CHECK-NEXT:    [[TMP796:%.*]] = load i32, ptr [[IE]], align 4
14871 // CHECK-NEXT:    [[TMP797:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP796]] acquire, align 4
14872 // CHECK-NEXT:    [[TMP798:%.*]] = load i32, ptr [[IE]], align 4
14873 // CHECK-NEXT:    [[TMP799:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP798]] acquire, align 4
14874 // CHECK-NEXT:    [[TMP800:%.*]] = load i32, ptr [[IE]], align 4
14875 // CHECK-NEXT:    [[TMP801:%.*]] = load i32, ptr [[ID]], align 4
14876 // CHECK-NEXT:    [[TMP802:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP800]], i32 [[TMP801]] acquire acquire, align 4
14877 // CHECK-NEXT:    [[TMP803:%.*]] = load i32, ptr [[IE]], align 4
14878 // CHECK-NEXT:    [[TMP804:%.*]] = load i32, ptr [[ID]], align 4
14879 // CHECK-NEXT:    [[TMP805:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP803]], i32 [[TMP804]] acquire acquire, align 4
14880 // CHECK-NEXT:    [[TMP806:%.*]] = load i32, ptr [[IE]], align 4
14881 // CHECK-NEXT:    [[TMP807:%.*]] = load i32, ptr [[ID]], align 4
14882 // CHECK-NEXT:    [[TMP808:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP806]], i32 [[TMP807]] acquire acquire, align 4
14883 // CHECK-NEXT:    [[TMP809:%.*]] = load i32, ptr [[IE]], align 4
14884 // CHECK-NEXT:    [[TMP810:%.*]] = load i32, ptr [[ID]], align 4
14885 // CHECK-NEXT:    [[TMP811:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP809]], i32 [[TMP810]] acquire acquire, align 4
14886 // CHECK-NEXT:    [[TMP812:%.*]] = load i32, ptr [[UIE]], align 4
14887 // CHECK-NEXT:    [[TMP813:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP812]] acquire, align 4
14888 // CHECK-NEXT:    [[TMP814:%.*]] = load i32, ptr [[UIE]], align 4
14889 // CHECK-NEXT:    [[TMP815:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP814]] acquire, align 4
14890 // CHECK-NEXT:    [[TMP816:%.*]] = load i32, ptr [[UIE]], align 4
14891 // CHECK-NEXT:    [[TMP817:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP816]] acquire, align 4
14892 // CHECK-NEXT:    [[TMP818:%.*]] = load i32, ptr [[UIE]], align 4
14893 // CHECK-NEXT:    [[TMP819:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP818]] acquire, align 4
14894 // CHECK-NEXT:    [[TMP820:%.*]] = load i32, ptr [[UIE]], align 4
14895 // CHECK-NEXT:    [[TMP821:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP820]] acquire, align 4
14896 // CHECK-NEXT:    [[TMP822:%.*]] = load i32, ptr [[UIE]], align 4
14897 // CHECK-NEXT:    [[TMP823:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP822]] acquire, align 4
14898 // CHECK-NEXT:    [[TMP824:%.*]] = load i32, ptr [[UIE]], align 4
14899 // CHECK-NEXT:    [[TMP825:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP824]] acquire, align 4
14900 // CHECK-NEXT:    [[TMP826:%.*]] = load i32, ptr [[UIE]], align 4
14901 // CHECK-NEXT:    [[TMP827:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP826]] acquire, align 4
14902 // CHECK-NEXT:    [[TMP828:%.*]] = load i32, ptr [[UIE]], align 4
14903 // CHECK-NEXT:    [[TMP829:%.*]] = load i32, ptr [[UID]], align 4
14904 // CHECK-NEXT:    [[TMP830:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP828]], i32 [[TMP829]] acquire acquire, align 4
14905 // CHECK-NEXT:    [[TMP831:%.*]] = load i32, ptr [[UIE]], align 4
14906 // CHECK-NEXT:    [[TMP832:%.*]] = load i32, ptr [[UID]], align 4
14907 // CHECK-NEXT:    [[TMP833:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP831]], i32 [[TMP832]] acquire acquire, align 4
14908 // CHECK-NEXT:    [[TMP834:%.*]] = load i32, ptr [[UIE]], align 4
14909 // CHECK-NEXT:    [[TMP835:%.*]] = load i32, ptr [[UID]], align 4
14910 // CHECK-NEXT:    [[TMP836:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP834]], i32 [[TMP835]] acquire acquire, align 4
14911 // CHECK-NEXT:    [[TMP837:%.*]] = load i32, ptr [[UIE]], align 4
14912 // CHECK-NEXT:    [[TMP838:%.*]] = load i32, ptr [[UID]], align 4
14913 // CHECK-NEXT:    [[TMP839:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP837]], i32 [[TMP838]] acquire acquire, align 4
14914 // CHECK-NEXT:    [[TMP840:%.*]] = load i32, ptr [[IE]], align 4
14915 // CHECK-NEXT:    [[TMP841:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP840]] monotonic, align 4
14916 // CHECK-NEXT:    [[TMP842:%.*]] = load i32, ptr [[IE]], align 4
14917 // CHECK-NEXT:    [[TMP843:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP842]] monotonic, align 4
14918 // CHECK-NEXT:    [[TMP844:%.*]] = load i32, ptr [[IE]], align 4
14919 // CHECK-NEXT:    [[TMP845:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP844]] monotonic, align 4
14920 // CHECK-NEXT:    [[TMP846:%.*]] = load i32, ptr [[IE]], align 4
14921 // CHECK-NEXT:    [[TMP847:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP846]] monotonic, align 4
14922 // CHECK-NEXT:    [[TMP848:%.*]] = load i32, ptr [[IE]], align 4
14923 // CHECK-NEXT:    [[TMP849:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP848]] monotonic, align 4
14924 // CHECK-NEXT:    [[TMP850:%.*]] = load i32, ptr [[IE]], align 4
14925 // CHECK-NEXT:    [[TMP851:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP850]] monotonic, align 4
14926 // CHECK-NEXT:    [[TMP852:%.*]] = load i32, ptr [[IE]], align 4
14927 // CHECK-NEXT:    [[TMP853:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP852]] monotonic, align 4
14928 // CHECK-NEXT:    [[TMP854:%.*]] = load i32, ptr [[IE]], align 4
14929 // CHECK-NEXT:    [[TMP855:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP854]] monotonic, align 4
14930 // CHECK-NEXT:    [[TMP856:%.*]] = load i32, ptr [[IE]], align 4
14931 // CHECK-NEXT:    [[TMP857:%.*]] = load i32, ptr [[ID]], align 4
14932 // CHECK-NEXT:    [[TMP858:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP856]], i32 [[TMP857]] monotonic monotonic, align 4
14933 // CHECK-NEXT:    [[TMP859:%.*]] = load i32, ptr [[IE]], align 4
14934 // CHECK-NEXT:    [[TMP860:%.*]] = load i32, ptr [[ID]], align 4
14935 // CHECK-NEXT:    [[TMP861:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP859]], i32 [[TMP860]] monotonic monotonic, align 4
14936 // CHECK-NEXT:    [[TMP862:%.*]] = load i32, ptr [[IE]], align 4
14937 // CHECK-NEXT:    [[TMP863:%.*]] = load i32, ptr [[ID]], align 4
14938 // CHECK-NEXT:    [[TMP864:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP862]], i32 [[TMP863]] monotonic monotonic, align 4
14939 // CHECK-NEXT:    [[TMP865:%.*]] = load i32, ptr [[IE]], align 4
14940 // CHECK-NEXT:    [[TMP866:%.*]] = load i32, ptr [[ID]], align 4
14941 // CHECK-NEXT:    [[TMP867:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP865]], i32 [[TMP866]] monotonic monotonic, align 4
14942 // CHECK-NEXT:    [[TMP868:%.*]] = load i32, ptr [[UIE]], align 4
14943 // CHECK-NEXT:    [[TMP869:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP868]] monotonic, align 4
14944 // CHECK-NEXT:    [[TMP870:%.*]] = load i32, ptr [[UIE]], align 4
14945 // CHECK-NEXT:    [[TMP871:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP870]] monotonic, align 4
14946 // CHECK-NEXT:    [[TMP872:%.*]] = load i32, ptr [[UIE]], align 4
14947 // CHECK-NEXT:    [[TMP873:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP872]] monotonic, align 4
14948 // CHECK-NEXT:    [[TMP874:%.*]] = load i32, ptr [[UIE]], align 4
14949 // CHECK-NEXT:    [[TMP875:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP874]] monotonic, align 4
14950 // CHECK-NEXT:    [[TMP876:%.*]] = load i32, ptr [[UIE]], align 4
14951 // CHECK-NEXT:    [[TMP877:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP876]] monotonic, align 4
14952 // CHECK-NEXT:    [[TMP878:%.*]] = load i32, ptr [[UIE]], align 4
14953 // CHECK-NEXT:    [[TMP879:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP878]] monotonic, align 4
14954 // CHECK-NEXT:    [[TMP880:%.*]] = load i32, ptr [[UIE]], align 4
14955 // CHECK-NEXT:    [[TMP881:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP880]] monotonic, align 4
14956 // CHECK-NEXT:    [[TMP882:%.*]] = load i32, ptr [[UIE]], align 4
14957 // CHECK-NEXT:    [[TMP883:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP882]] monotonic, align 4
14958 // CHECK-NEXT:    [[TMP884:%.*]] = load i32, ptr [[UIE]], align 4
14959 // CHECK-NEXT:    [[TMP885:%.*]] = load i32, ptr [[UID]], align 4
14960 // CHECK-NEXT:    [[TMP886:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP884]], i32 [[TMP885]] monotonic monotonic, align 4
14961 // CHECK-NEXT:    [[TMP887:%.*]] = load i32, ptr [[UIE]], align 4
14962 // CHECK-NEXT:    [[TMP888:%.*]] = load i32, ptr [[UID]], align 4
14963 // CHECK-NEXT:    [[TMP889:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP887]], i32 [[TMP888]] monotonic monotonic, align 4
14964 // CHECK-NEXT:    [[TMP890:%.*]] = load i32, ptr [[UIE]], align 4
14965 // CHECK-NEXT:    [[TMP891:%.*]] = load i32, ptr [[UID]], align 4
14966 // CHECK-NEXT:    [[TMP892:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP890]], i32 [[TMP891]] monotonic monotonic, align 4
14967 // CHECK-NEXT:    [[TMP893:%.*]] = load i32, ptr [[UIE]], align 4
14968 // CHECK-NEXT:    [[TMP894:%.*]] = load i32, ptr [[UID]], align 4
14969 // CHECK-NEXT:    [[TMP895:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP893]], i32 [[TMP894]] monotonic monotonic, align 4
14970 // CHECK-NEXT:    [[TMP896:%.*]] = load i32, ptr [[IE]], align 4
14971 // CHECK-NEXT:    [[TMP897:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP896]] release, align 4
14972 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14973 // CHECK-NEXT:    [[TMP898:%.*]] = load i32, ptr [[IE]], align 4
14974 // CHECK-NEXT:    [[TMP899:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP898]] release, align 4
14975 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14976 // CHECK-NEXT:    [[TMP900:%.*]] = load i32, ptr [[IE]], align 4
14977 // CHECK-NEXT:    [[TMP901:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP900]] release, align 4
14978 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14979 // CHECK-NEXT:    [[TMP902:%.*]] = load i32, ptr [[IE]], align 4
14980 // CHECK-NEXT:    [[TMP903:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP902]] release, align 4
14981 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14982 // CHECK-NEXT:    [[TMP904:%.*]] = load i32, ptr [[IE]], align 4
14983 // CHECK-NEXT:    [[TMP905:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP904]] release, align 4
14984 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14985 // CHECK-NEXT:    [[TMP906:%.*]] = load i32, ptr [[IE]], align 4
14986 // CHECK-NEXT:    [[TMP907:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP906]] release, align 4
14987 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14988 // CHECK-NEXT:    [[TMP908:%.*]] = load i32, ptr [[IE]], align 4
14989 // CHECK-NEXT:    [[TMP909:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP908]] release, align 4
14990 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14991 // CHECK-NEXT:    [[TMP910:%.*]] = load i32, ptr [[IE]], align 4
14992 // CHECK-NEXT:    [[TMP911:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP910]] release, align 4
14993 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14994 // CHECK-NEXT:    [[TMP912:%.*]] = load i32, ptr [[IE]], align 4
14995 // CHECK-NEXT:    [[TMP913:%.*]] = load i32, ptr [[ID]], align 4
14996 // CHECK-NEXT:    [[TMP914:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP912]], i32 [[TMP913]] release monotonic, align 4
14997 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
14998 // CHECK-NEXT:    [[TMP915:%.*]] = load i32, ptr [[IE]], align 4
14999 // CHECK-NEXT:    [[TMP916:%.*]] = load i32, ptr [[ID]], align 4
15000 // CHECK-NEXT:    [[TMP917:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP915]], i32 [[TMP916]] release monotonic, align 4
15001 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15002 // CHECK-NEXT:    [[TMP918:%.*]] = load i32, ptr [[IE]], align 4
15003 // CHECK-NEXT:    [[TMP919:%.*]] = load i32, ptr [[ID]], align 4
15004 // CHECK-NEXT:    [[TMP920:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP918]], i32 [[TMP919]] release monotonic, align 4
15005 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15006 // CHECK-NEXT:    [[TMP921:%.*]] = load i32, ptr [[IE]], align 4
15007 // CHECK-NEXT:    [[TMP922:%.*]] = load i32, ptr [[ID]], align 4
15008 // CHECK-NEXT:    [[TMP923:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP921]], i32 [[TMP922]] release monotonic, align 4
15009 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15010 // CHECK-NEXT:    [[TMP924:%.*]] = load i32, ptr [[UIE]], align 4
15011 // CHECK-NEXT:    [[TMP925:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP924]] release, align 4
15012 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15013 // CHECK-NEXT:    [[TMP926:%.*]] = load i32, ptr [[UIE]], align 4
15014 // CHECK-NEXT:    [[TMP927:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP926]] release, align 4
15015 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15016 // CHECK-NEXT:    [[TMP928:%.*]] = load i32, ptr [[UIE]], align 4
15017 // CHECK-NEXT:    [[TMP929:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP928]] release, align 4
15018 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15019 // CHECK-NEXT:    [[TMP930:%.*]] = load i32, ptr [[UIE]], align 4
15020 // CHECK-NEXT:    [[TMP931:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP930]] release, align 4
15021 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15022 // CHECK-NEXT:    [[TMP932:%.*]] = load i32, ptr [[UIE]], align 4
15023 // CHECK-NEXT:    [[TMP933:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP932]] release, align 4
15024 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15025 // CHECK-NEXT:    [[TMP934:%.*]] = load i32, ptr [[UIE]], align 4
15026 // CHECK-NEXT:    [[TMP935:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP934]] release, align 4
15027 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15028 // CHECK-NEXT:    [[TMP936:%.*]] = load i32, ptr [[UIE]], align 4
15029 // CHECK-NEXT:    [[TMP937:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP936]] release, align 4
15030 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15031 // CHECK-NEXT:    [[TMP938:%.*]] = load i32, ptr [[UIE]], align 4
15032 // CHECK-NEXT:    [[TMP939:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP938]] release, align 4
15033 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15034 // CHECK-NEXT:    [[TMP940:%.*]] = load i32, ptr [[UIE]], align 4
15035 // CHECK-NEXT:    [[TMP941:%.*]] = load i32, ptr [[UID]], align 4
15036 // CHECK-NEXT:    [[TMP942:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP940]], i32 [[TMP941]] release monotonic, align 4
15037 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15038 // CHECK-NEXT:    [[TMP943:%.*]] = load i32, ptr [[UIE]], align 4
15039 // CHECK-NEXT:    [[TMP944:%.*]] = load i32, ptr [[UID]], align 4
15040 // CHECK-NEXT:    [[TMP945:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP943]], i32 [[TMP944]] release monotonic, align 4
15041 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15042 // CHECK-NEXT:    [[TMP946:%.*]] = load i32, ptr [[UIE]], align 4
15043 // CHECK-NEXT:    [[TMP947:%.*]] = load i32, ptr [[UID]], align 4
15044 // CHECK-NEXT:    [[TMP948:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP946]], i32 [[TMP947]] release monotonic, align 4
15045 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15046 // CHECK-NEXT:    [[TMP949:%.*]] = load i32, ptr [[UIE]], align 4
15047 // CHECK-NEXT:    [[TMP950:%.*]] = load i32, ptr [[UID]], align 4
15048 // CHECK-NEXT:    [[TMP951:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP949]], i32 [[TMP950]] release monotonic, align 4
15049 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15050 // CHECK-NEXT:    [[TMP952:%.*]] = load i32, ptr [[IE]], align 4
15051 // CHECK-NEXT:    [[TMP953:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP952]] seq_cst, align 4
15052 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15053 // CHECK-NEXT:    [[TMP954:%.*]] = load i32, ptr [[IE]], align 4
15054 // CHECK-NEXT:    [[TMP955:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP954]] seq_cst, align 4
15055 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15056 // CHECK-NEXT:    [[TMP956:%.*]] = load i32, ptr [[IE]], align 4
15057 // CHECK-NEXT:    [[TMP957:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP956]] seq_cst, align 4
15058 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15059 // CHECK-NEXT:    [[TMP958:%.*]] = load i32, ptr [[IE]], align 4
15060 // CHECK-NEXT:    [[TMP959:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP958]] seq_cst, align 4
15061 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15062 // CHECK-NEXT:    [[TMP960:%.*]] = load i32, ptr [[IE]], align 4
15063 // CHECK-NEXT:    [[TMP961:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP960]] seq_cst, align 4
15064 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15065 // CHECK-NEXT:    [[TMP962:%.*]] = load i32, ptr [[IE]], align 4
15066 // CHECK-NEXT:    [[TMP963:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP962]] seq_cst, align 4
15067 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15068 // CHECK-NEXT:    [[TMP964:%.*]] = load i32, ptr [[IE]], align 4
15069 // CHECK-NEXT:    [[TMP965:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP964]] seq_cst, align 4
15070 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15071 // CHECK-NEXT:    [[TMP966:%.*]] = load i32, ptr [[IE]], align 4
15072 // CHECK-NEXT:    [[TMP967:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP966]] seq_cst, align 4
15073 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15074 // CHECK-NEXT:    [[TMP968:%.*]] = load i32, ptr [[IE]], align 4
15075 // CHECK-NEXT:    [[TMP969:%.*]] = load i32, ptr [[ID]], align 4
15076 // CHECK-NEXT:    [[TMP970:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP968]], i32 [[TMP969]] seq_cst seq_cst, align 4
15077 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15078 // CHECK-NEXT:    [[TMP971:%.*]] = load i32, ptr [[IE]], align 4
15079 // CHECK-NEXT:    [[TMP972:%.*]] = load i32, ptr [[ID]], align 4
15080 // CHECK-NEXT:    [[TMP973:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP971]], i32 [[TMP972]] seq_cst seq_cst, align 4
15081 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15082 // CHECK-NEXT:    [[TMP974:%.*]] = load i32, ptr [[IE]], align 4
15083 // CHECK-NEXT:    [[TMP975:%.*]] = load i32, ptr [[ID]], align 4
15084 // CHECK-NEXT:    [[TMP976:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP974]], i32 [[TMP975]] seq_cst seq_cst, align 4
15085 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15086 // CHECK-NEXT:    [[TMP977:%.*]] = load i32, ptr [[IE]], align 4
15087 // CHECK-NEXT:    [[TMP978:%.*]] = load i32, ptr [[ID]], align 4
15088 // CHECK-NEXT:    [[TMP979:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP977]], i32 [[TMP978]] seq_cst seq_cst, align 4
15089 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15090 // CHECK-NEXT:    [[TMP980:%.*]] = load i32, ptr [[UIE]], align 4
15091 // CHECK-NEXT:    [[TMP981:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP980]] seq_cst, align 4
15092 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15093 // CHECK-NEXT:    [[TMP982:%.*]] = load i32, ptr [[UIE]], align 4
15094 // CHECK-NEXT:    [[TMP983:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP982]] seq_cst, align 4
15095 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15096 // CHECK-NEXT:    [[TMP984:%.*]] = load i32, ptr [[UIE]], align 4
15097 // CHECK-NEXT:    [[TMP985:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP984]] seq_cst, align 4
15098 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15099 // CHECK-NEXT:    [[TMP986:%.*]] = load i32, ptr [[UIE]], align 4
15100 // CHECK-NEXT:    [[TMP987:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP986]] seq_cst, align 4
15101 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15102 // CHECK-NEXT:    [[TMP988:%.*]] = load i32, ptr [[UIE]], align 4
15103 // CHECK-NEXT:    [[TMP989:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP988]] seq_cst, align 4
15104 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15105 // CHECK-NEXT:    [[TMP990:%.*]] = load i32, ptr [[UIE]], align 4
15106 // CHECK-NEXT:    [[TMP991:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP990]] seq_cst, align 4
15107 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15108 // CHECK-NEXT:    [[TMP992:%.*]] = load i32, ptr [[UIE]], align 4
15109 // CHECK-NEXT:    [[TMP993:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP992]] seq_cst, align 4
15110 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15111 // CHECK-NEXT:    [[TMP994:%.*]] = load i32, ptr [[UIE]], align 4
15112 // CHECK-NEXT:    [[TMP995:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP994]] seq_cst, align 4
15113 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15114 // CHECK-NEXT:    [[TMP996:%.*]] = load i32, ptr [[UIE]], align 4
15115 // CHECK-NEXT:    [[TMP997:%.*]] = load i32, ptr [[UID]], align 4
15116 // CHECK-NEXT:    [[TMP998:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP996]], i32 [[TMP997]] seq_cst seq_cst, align 4
15117 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15118 // CHECK-NEXT:    [[TMP999:%.*]] = load i32, ptr [[UIE]], align 4
15119 // CHECK-NEXT:    [[TMP1000:%.*]] = load i32, ptr [[UID]], align 4
15120 // CHECK-NEXT:    [[TMP1001:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP999]], i32 [[TMP1000]] seq_cst seq_cst, align 4
15121 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15122 // CHECK-NEXT:    [[TMP1002:%.*]] = load i32, ptr [[UIE]], align 4
15123 // CHECK-NEXT:    [[TMP1003:%.*]] = load i32, ptr [[UID]], align 4
15124 // CHECK-NEXT:    [[TMP1004:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP1002]], i32 [[TMP1003]] seq_cst seq_cst, align 4
15125 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15126 // CHECK-NEXT:    [[TMP1005:%.*]] = load i32, ptr [[UIE]], align 4
15127 // CHECK-NEXT:    [[TMP1006:%.*]] = load i32, ptr [[UID]], align 4
15128 // CHECK-NEXT:    [[TMP1007:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP1005]], i32 [[TMP1006]] seq_cst seq_cst, align 4
15129 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15130 // CHECK-NEXT:    [[TMP1008:%.*]] = load i64, ptr [[LE]], align 8
15131 // CHECK-NEXT:    [[TMP1009:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1008]] monotonic, align 8
15132 // CHECK-NEXT:    [[TMP1010:%.*]] = load i64, ptr [[LE]], align 8
15133 // CHECK-NEXT:    [[TMP1011:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1010]] monotonic, align 8
15134 // CHECK-NEXT:    [[TMP1012:%.*]] = load i64, ptr [[LE]], align 8
15135 // CHECK-NEXT:    [[TMP1013:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1012]] monotonic, align 8
15136 // CHECK-NEXT:    [[TMP1014:%.*]] = load i64, ptr [[LE]], align 8
15137 // CHECK-NEXT:    [[TMP1015:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1014]] monotonic, align 8
15138 // CHECK-NEXT:    [[TMP1016:%.*]] = load i64, ptr [[LE]], align 8
15139 // CHECK-NEXT:    [[TMP1017:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1016]] monotonic, align 8
15140 // CHECK-NEXT:    [[TMP1018:%.*]] = load i64, ptr [[LE]], align 8
15141 // CHECK-NEXT:    [[TMP1019:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1018]] monotonic, align 8
15142 // CHECK-NEXT:    [[TMP1020:%.*]] = load i64, ptr [[LE]], align 8
15143 // CHECK-NEXT:    [[TMP1021:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1020]] monotonic, align 8
15144 // CHECK-NEXT:    [[TMP1022:%.*]] = load i64, ptr [[LE]], align 8
15145 // CHECK-NEXT:    [[TMP1023:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1022]] monotonic, align 8
15146 // CHECK-NEXT:    [[TMP1024:%.*]] = load i64, ptr [[LE]], align 8
15147 // CHECK-NEXT:    [[TMP1025:%.*]] = load i64, ptr [[LD]], align 8
15148 // CHECK-NEXT:    [[TMP1026:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1024]], i64 [[TMP1025]] monotonic monotonic, align 8
15149 // CHECK-NEXT:    [[TMP1027:%.*]] = load i64, ptr [[LE]], align 8
15150 // CHECK-NEXT:    [[TMP1028:%.*]] = load i64, ptr [[LD]], align 8
15151 // CHECK-NEXT:    [[TMP1029:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1027]], i64 [[TMP1028]] monotonic monotonic, align 8
15152 // CHECK-NEXT:    [[TMP1030:%.*]] = load i64, ptr [[LE]], align 8
15153 // CHECK-NEXT:    [[TMP1031:%.*]] = load i64, ptr [[LD]], align 8
15154 // CHECK-NEXT:    [[TMP1032:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1030]], i64 [[TMP1031]] monotonic monotonic, align 8
15155 // CHECK-NEXT:    [[TMP1033:%.*]] = load i64, ptr [[LE]], align 8
15156 // CHECK-NEXT:    [[TMP1034:%.*]] = load i64, ptr [[LD]], align 8
15157 // CHECK-NEXT:    [[TMP1035:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1033]], i64 [[TMP1034]] monotonic monotonic, align 8
15158 // CHECK-NEXT:    [[TMP1036:%.*]] = load i64, ptr [[ULE]], align 8
15159 // CHECK-NEXT:    [[TMP1037:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1036]] monotonic, align 8
15160 // CHECK-NEXT:    [[TMP1038:%.*]] = load i64, ptr [[ULE]], align 8
15161 // CHECK-NEXT:    [[TMP1039:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1038]] monotonic, align 8
15162 // CHECK-NEXT:    [[TMP1040:%.*]] = load i64, ptr [[ULE]], align 8
15163 // CHECK-NEXT:    [[TMP1041:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1040]] monotonic, align 8
15164 // CHECK-NEXT:    [[TMP1042:%.*]] = load i64, ptr [[ULE]], align 8
15165 // CHECK-NEXT:    [[TMP1043:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1042]] monotonic, align 8
15166 // CHECK-NEXT:    [[TMP1044:%.*]] = load i64, ptr [[ULE]], align 8
15167 // CHECK-NEXT:    [[TMP1045:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1044]] monotonic, align 8
15168 // CHECK-NEXT:    [[TMP1046:%.*]] = load i64, ptr [[ULE]], align 8
15169 // CHECK-NEXT:    [[TMP1047:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1046]] monotonic, align 8
15170 // CHECK-NEXT:    [[TMP1048:%.*]] = load i64, ptr [[ULE]], align 8
15171 // CHECK-NEXT:    [[TMP1049:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1048]] monotonic, align 8
15172 // CHECK-NEXT:    [[TMP1050:%.*]] = load i64, ptr [[ULE]], align 8
15173 // CHECK-NEXT:    [[TMP1051:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1050]] monotonic, align 8
15174 // CHECK-NEXT:    [[TMP1052:%.*]] = load i64, ptr [[ULE]], align 8
15175 // CHECK-NEXT:    [[TMP1053:%.*]] = load i64, ptr [[ULD]], align 8
15176 // CHECK-NEXT:    [[TMP1054:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1052]], i64 [[TMP1053]] monotonic monotonic, align 8
15177 // CHECK-NEXT:    [[TMP1055:%.*]] = load i64, ptr [[ULE]], align 8
15178 // CHECK-NEXT:    [[TMP1056:%.*]] = load i64, ptr [[ULD]], align 8
15179 // CHECK-NEXT:    [[TMP1057:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1055]], i64 [[TMP1056]] monotonic monotonic, align 8
15180 // CHECK-NEXT:    [[TMP1058:%.*]] = load i64, ptr [[ULE]], align 8
15181 // CHECK-NEXT:    [[TMP1059:%.*]] = load i64, ptr [[ULD]], align 8
15182 // CHECK-NEXT:    [[TMP1060:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1058]], i64 [[TMP1059]] monotonic monotonic, align 8
15183 // CHECK-NEXT:    [[TMP1061:%.*]] = load i64, ptr [[ULE]], align 8
15184 // CHECK-NEXT:    [[TMP1062:%.*]] = load i64, ptr [[ULD]], align 8
15185 // CHECK-NEXT:    [[TMP1063:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1061]], i64 [[TMP1062]] monotonic monotonic, align 8
15186 // CHECK-NEXT:    [[TMP1064:%.*]] = load i64, ptr [[LE]], align 8
15187 // CHECK-NEXT:    [[TMP1065:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1064]] acq_rel, align 8
15188 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15189 // CHECK-NEXT:    [[TMP1066:%.*]] = load i64, ptr [[LE]], align 8
15190 // CHECK-NEXT:    [[TMP1067:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1066]] acq_rel, align 8
15191 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15192 // CHECK-NEXT:    [[TMP1068:%.*]] = load i64, ptr [[LE]], align 8
15193 // CHECK-NEXT:    [[TMP1069:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1068]] acq_rel, align 8
15194 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15195 // CHECK-NEXT:    [[TMP1070:%.*]] = load i64, ptr [[LE]], align 8
15196 // CHECK-NEXT:    [[TMP1071:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1070]] acq_rel, align 8
15197 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15198 // CHECK-NEXT:    [[TMP1072:%.*]] = load i64, ptr [[LE]], align 8
15199 // CHECK-NEXT:    [[TMP1073:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1072]] acq_rel, align 8
15200 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15201 // CHECK-NEXT:    [[TMP1074:%.*]] = load i64, ptr [[LE]], align 8
15202 // CHECK-NEXT:    [[TMP1075:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1074]] acq_rel, align 8
15203 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15204 // CHECK-NEXT:    [[TMP1076:%.*]] = load i64, ptr [[LE]], align 8
15205 // CHECK-NEXT:    [[TMP1077:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1076]] acq_rel, align 8
15206 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15207 // CHECK-NEXT:    [[TMP1078:%.*]] = load i64, ptr [[LE]], align 8
15208 // CHECK-NEXT:    [[TMP1079:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1078]] acq_rel, align 8
15209 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15210 // CHECK-NEXT:    [[TMP1080:%.*]] = load i64, ptr [[LE]], align 8
15211 // CHECK-NEXT:    [[TMP1081:%.*]] = load i64, ptr [[LD]], align 8
15212 // CHECK-NEXT:    [[TMP1082:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1080]], i64 [[TMP1081]] acq_rel acquire, align 8
15213 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15214 // CHECK-NEXT:    [[TMP1083:%.*]] = load i64, ptr [[LE]], align 8
15215 // CHECK-NEXT:    [[TMP1084:%.*]] = load i64, ptr [[LD]], align 8
15216 // CHECK-NEXT:    [[TMP1085:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1083]], i64 [[TMP1084]] acq_rel acquire, align 8
15217 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15218 // CHECK-NEXT:    [[TMP1086:%.*]] = load i64, ptr [[LE]], align 8
15219 // CHECK-NEXT:    [[TMP1087:%.*]] = load i64, ptr [[LD]], align 8
15220 // CHECK-NEXT:    [[TMP1088:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1086]], i64 [[TMP1087]] acq_rel acquire, align 8
15221 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15222 // CHECK-NEXT:    [[TMP1089:%.*]] = load i64, ptr [[LE]], align 8
15223 // CHECK-NEXT:    [[TMP1090:%.*]] = load i64, ptr [[LD]], align 8
15224 // CHECK-NEXT:    [[TMP1091:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1089]], i64 [[TMP1090]] acq_rel acquire, align 8
15225 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15226 // CHECK-NEXT:    [[TMP1092:%.*]] = load i64, ptr [[ULE]], align 8
15227 // CHECK-NEXT:    [[TMP1093:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1092]] acq_rel, align 8
15228 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15229 // CHECK-NEXT:    [[TMP1094:%.*]] = load i64, ptr [[ULE]], align 8
15230 // CHECK-NEXT:    [[TMP1095:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1094]] acq_rel, align 8
15231 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15232 // CHECK-NEXT:    [[TMP1096:%.*]] = load i64, ptr [[ULE]], align 8
15233 // CHECK-NEXT:    [[TMP1097:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1096]] acq_rel, align 8
15234 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15235 // CHECK-NEXT:    [[TMP1098:%.*]] = load i64, ptr [[ULE]], align 8
15236 // CHECK-NEXT:    [[TMP1099:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1098]] acq_rel, align 8
15237 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15238 // CHECK-NEXT:    [[TMP1100:%.*]] = load i64, ptr [[ULE]], align 8
15239 // CHECK-NEXT:    [[TMP1101:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1100]] acq_rel, align 8
15240 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15241 // CHECK-NEXT:    [[TMP1102:%.*]] = load i64, ptr [[ULE]], align 8
15242 // CHECK-NEXT:    [[TMP1103:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1102]] acq_rel, align 8
15243 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15244 // CHECK-NEXT:    [[TMP1104:%.*]] = load i64, ptr [[ULE]], align 8
15245 // CHECK-NEXT:    [[TMP1105:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1104]] acq_rel, align 8
15246 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15247 // CHECK-NEXT:    [[TMP1106:%.*]] = load i64, ptr [[ULE]], align 8
15248 // CHECK-NEXT:    [[TMP1107:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1106]] acq_rel, align 8
15249 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15250 // CHECK-NEXT:    [[TMP1108:%.*]] = load i64, ptr [[ULE]], align 8
15251 // CHECK-NEXT:    [[TMP1109:%.*]] = load i64, ptr [[ULD]], align 8
15252 // CHECK-NEXT:    [[TMP1110:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1108]], i64 [[TMP1109]] acq_rel acquire, align 8
15253 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15254 // CHECK-NEXT:    [[TMP1111:%.*]] = load i64, ptr [[ULE]], align 8
15255 // CHECK-NEXT:    [[TMP1112:%.*]] = load i64, ptr [[ULD]], align 8
15256 // CHECK-NEXT:    [[TMP1113:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1111]], i64 [[TMP1112]] acq_rel acquire, align 8
15257 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15258 // CHECK-NEXT:    [[TMP1114:%.*]] = load i64, ptr [[ULE]], align 8
15259 // CHECK-NEXT:    [[TMP1115:%.*]] = load i64, ptr [[ULD]], align 8
15260 // CHECK-NEXT:    [[TMP1116:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1114]], i64 [[TMP1115]] acq_rel acquire, align 8
15261 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15262 // CHECK-NEXT:    [[TMP1117:%.*]] = load i64, ptr [[ULE]], align 8
15263 // CHECK-NEXT:    [[TMP1118:%.*]] = load i64, ptr [[ULD]], align 8
15264 // CHECK-NEXT:    [[TMP1119:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1117]], i64 [[TMP1118]] acq_rel acquire, align 8
15265 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15266 // CHECK-NEXT:    [[TMP1120:%.*]] = load i64, ptr [[LE]], align 8
15267 // CHECK-NEXT:    [[TMP1121:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1120]] acquire, align 8
15268 // CHECK-NEXT:    [[TMP1122:%.*]] = load i64, ptr [[LE]], align 8
15269 // CHECK-NEXT:    [[TMP1123:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1122]] acquire, align 8
15270 // CHECK-NEXT:    [[TMP1124:%.*]] = load i64, ptr [[LE]], align 8
15271 // CHECK-NEXT:    [[TMP1125:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1124]] acquire, align 8
15272 // CHECK-NEXT:    [[TMP1126:%.*]] = load i64, ptr [[LE]], align 8
15273 // CHECK-NEXT:    [[TMP1127:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1126]] acquire, align 8
15274 // CHECK-NEXT:    [[TMP1128:%.*]] = load i64, ptr [[LE]], align 8
15275 // CHECK-NEXT:    [[TMP1129:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1128]] acquire, align 8
15276 // CHECK-NEXT:    [[TMP1130:%.*]] = load i64, ptr [[LE]], align 8
15277 // CHECK-NEXT:    [[TMP1131:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1130]] acquire, align 8
15278 // CHECK-NEXT:    [[TMP1132:%.*]] = load i64, ptr [[LE]], align 8
15279 // CHECK-NEXT:    [[TMP1133:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1132]] acquire, align 8
15280 // CHECK-NEXT:    [[TMP1134:%.*]] = load i64, ptr [[LE]], align 8
15281 // CHECK-NEXT:    [[TMP1135:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1134]] acquire, align 8
15282 // CHECK-NEXT:    [[TMP1136:%.*]] = load i64, ptr [[LE]], align 8
15283 // CHECK-NEXT:    [[TMP1137:%.*]] = load i64, ptr [[LD]], align 8
15284 // CHECK-NEXT:    [[TMP1138:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1136]], i64 [[TMP1137]] acquire acquire, align 8
15285 // CHECK-NEXT:    [[TMP1139:%.*]] = load i64, ptr [[LE]], align 8
15286 // CHECK-NEXT:    [[TMP1140:%.*]] = load i64, ptr [[LD]], align 8
15287 // CHECK-NEXT:    [[TMP1141:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1139]], i64 [[TMP1140]] acquire acquire, align 8
15288 // CHECK-NEXT:    [[TMP1142:%.*]] = load i64, ptr [[LE]], align 8
15289 // CHECK-NEXT:    [[TMP1143:%.*]] = load i64, ptr [[LD]], align 8
15290 // CHECK-NEXT:    [[TMP1144:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1142]], i64 [[TMP1143]] acquire acquire, align 8
15291 // CHECK-NEXT:    [[TMP1145:%.*]] = load i64, ptr [[LE]], align 8
15292 // CHECK-NEXT:    [[TMP1146:%.*]] = load i64, ptr [[LD]], align 8
15293 // CHECK-NEXT:    [[TMP1147:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1145]], i64 [[TMP1146]] acquire acquire, align 8
15294 // CHECK-NEXT:    [[TMP1148:%.*]] = load i64, ptr [[ULE]], align 8
15295 // CHECK-NEXT:    [[TMP1149:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1148]] acquire, align 8
15296 // CHECK-NEXT:    [[TMP1150:%.*]] = load i64, ptr [[ULE]], align 8
15297 // CHECK-NEXT:    [[TMP1151:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1150]] acquire, align 8
15298 // CHECK-NEXT:    [[TMP1152:%.*]] = load i64, ptr [[ULE]], align 8
15299 // CHECK-NEXT:    [[TMP1153:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1152]] acquire, align 8
15300 // CHECK-NEXT:    [[TMP1154:%.*]] = load i64, ptr [[ULE]], align 8
15301 // CHECK-NEXT:    [[TMP1155:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1154]] acquire, align 8
15302 // CHECK-NEXT:    [[TMP1156:%.*]] = load i64, ptr [[ULE]], align 8
15303 // CHECK-NEXT:    [[TMP1157:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1156]] acquire, align 8
15304 // CHECK-NEXT:    [[TMP1158:%.*]] = load i64, ptr [[ULE]], align 8
15305 // CHECK-NEXT:    [[TMP1159:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1158]] acquire, align 8
15306 // CHECK-NEXT:    [[TMP1160:%.*]] = load i64, ptr [[ULE]], align 8
15307 // CHECK-NEXT:    [[TMP1161:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1160]] acquire, align 8
15308 // CHECK-NEXT:    [[TMP1162:%.*]] = load i64, ptr [[ULE]], align 8
15309 // CHECK-NEXT:    [[TMP1163:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1162]] acquire, align 8
15310 // CHECK-NEXT:    [[TMP1164:%.*]] = load i64, ptr [[ULE]], align 8
15311 // CHECK-NEXT:    [[TMP1165:%.*]] = load i64, ptr [[ULD]], align 8
15312 // CHECK-NEXT:    [[TMP1166:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1164]], i64 [[TMP1165]] acquire acquire, align 8
15313 // CHECK-NEXT:    [[TMP1167:%.*]] = load i64, ptr [[ULE]], align 8
15314 // CHECK-NEXT:    [[TMP1168:%.*]] = load i64, ptr [[ULD]], align 8
15315 // CHECK-NEXT:    [[TMP1169:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1167]], i64 [[TMP1168]] acquire acquire, align 8
15316 // CHECK-NEXT:    [[TMP1170:%.*]] = load i64, ptr [[ULE]], align 8
15317 // CHECK-NEXT:    [[TMP1171:%.*]] = load i64, ptr [[ULD]], align 8
15318 // CHECK-NEXT:    [[TMP1172:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1170]], i64 [[TMP1171]] acquire acquire, align 8
15319 // CHECK-NEXT:    [[TMP1173:%.*]] = load i64, ptr [[ULE]], align 8
15320 // CHECK-NEXT:    [[TMP1174:%.*]] = load i64, ptr [[ULD]], align 8
15321 // CHECK-NEXT:    [[TMP1175:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1173]], i64 [[TMP1174]] acquire acquire, align 8
15322 // CHECK-NEXT:    [[TMP1176:%.*]] = load i64, ptr [[LE]], align 8
15323 // CHECK-NEXT:    [[TMP1177:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1176]] monotonic, align 8
15324 // CHECK-NEXT:    [[TMP1178:%.*]] = load i64, ptr [[LE]], align 8
15325 // CHECK-NEXT:    [[TMP1179:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1178]] monotonic, align 8
15326 // CHECK-NEXT:    [[TMP1180:%.*]] = load i64, ptr [[LE]], align 8
15327 // CHECK-NEXT:    [[TMP1181:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1180]] monotonic, align 8
15328 // CHECK-NEXT:    [[TMP1182:%.*]] = load i64, ptr [[LE]], align 8
15329 // CHECK-NEXT:    [[TMP1183:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1182]] monotonic, align 8
15330 // CHECK-NEXT:    [[TMP1184:%.*]] = load i64, ptr [[LE]], align 8
15331 // CHECK-NEXT:    [[TMP1185:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1184]] monotonic, align 8
15332 // CHECK-NEXT:    [[TMP1186:%.*]] = load i64, ptr [[LE]], align 8
15333 // CHECK-NEXT:    [[TMP1187:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1186]] monotonic, align 8
15334 // CHECK-NEXT:    [[TMP1188:%.*]] = load i64, ptr [[LE]], align 8
15335 // CHECK-NEXT:    [[TMP1189:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1188]] monotonic, align 8
15336 // CHECK-NEXT:    [[TMP1190:%.*]] = load i64, ptr [[LE]], align 8
15337 // CHECK-NEXT:    [[TMP1191:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1190]] monotonic, align 8
15338 // CHECK-NEXT:    [[TMP1192:%.*]] = load i64, ptr [[LE]], align 8
15339 // CHECK-NEXT:    [[TMP1193:%.*]] = load i64, ptr [[LD]], align 8
15340 // CHECK-NEXT:    [[TMP1194:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1192]], i64 [[TMP1193]] monotonic monotonic, align 8
15341 // CHECK-NEXT:    [[TMP1195:%.*]] = load i64, ptr [[LE]], align 8
15342 // CHECK-NEXT:    [[TMP1196:%.*]] = load i64, ptr [[LD]], align 8
15343 // CHECK-NEXT:    [[TMP1197:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1195]], i64 [[TMP1196]] monotonic monotonic, align 8
15344 // CHECK-NEXT:    [[TMP1198:%.*]] = load i64, ptr [[LE]], align 8
15345 // CHECK-NEXT:    [[TMP1199:%.*]] = load i64, ptr [[LD]], align 8
15346 // CHECK-NEXT:    [[TMP1200:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1198]], i64 [[TMP1199]] monotonic monotonic, align 8
15347 // CHECK-NEXT:    [[TMP1201:%.*]] = load i64, ptr [[LE]], align 8
15348 // CHECK-NEXT:    [[TMP1202:%.*]] = load i64, ptr [[LD]], align 8
15349 // CHECK-NEXT:    [[TMP1203:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1201]], i64 [[TMP1202]] monotonic monotonic, align 8
15350 // CHECK-NEXT:    [[TMP1204:%.*]] = load i64, ptr [[ULE]], align 8
15351 // CHECK-NEXT:    [[TMP1205:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1204]] monotonic, align 8
15352 // CHECK-NEXT:    [[TMP1206:%.*]] = load i64, ptr [[ULE]], align 8
15353 // CHECK-NEXT:    [[TMP1207:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1206]] monotonic, align 8
15354 // CHECK-NEXT:    [[TMP1208:%.*]] = load i64, ptr [[ULE]], align 8
15355 // CHECK-NEXT:    [[TMP1209:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1208]] monotonic, align 8
15356 // CHECK-NEXT:    [[TMP1210:%.*]] = load i64, ptr [[ULE]], align 8
15357 // CHECK-NEXT:    [[TMP1211:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1210]] monotonic, align 8
15358 // CHECK-NEXT:    [[TMP1212:%.*]] = load i64, ptr [[ULE]], align 8
15359 // CHECK-NEXT:    [[TMP1213:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1212]] monotonic, align 8
15360 // CHECK-NEXT:    [[TMP1214:%.*]] = load i64, ptr [[ULE]], align 8
15361 // CHECK-NEXT:    [[TMP1215:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1214]] monotonic, align 8
15362 // CHECK-NEXT:    [[TMP1216:%.*]] = load i64, ptr [[ULE]], align 8
15363 // CHECK-NEXT:    [[TMP1217:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1216]] monotonic, align 8
15364 // CHECK-NEXT:    [[TMP1218:%.*]] = load i64, ptr [[ULE]], align 8
15365 // CHECK-NEXT:    [[TMP1219:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1218]] monotonic, align 8
15366 // CHECK-NEXT:    [[TMP1220:%.*]] = load i64, ptr [[ULE]], align 8
15367 // CHECK-NEXT:    [[TMP1221:%.*]] = load i64, ptr [[ULD]], align 8
15368 // CHECK-NEXT:    [[TMP1222:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1220]], i64 [[TMP1221]] monotonic monotonic, align 8
15369 // CHECK-NEXT:    [[TMP1223:%.*]] = load i64, ptr [[ULE]], align 8
15370 // CHECK-NEXT:    [[TMP1224:%.*]] = load i64, ptr [[ULD]], align 8
15371 // CHECK-NEXT:    [[TMP1225:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1223]], i64 [[TMP1224]] monotonic monotonic, align 8
15372 // CHECK-NEXT:    [[TMP1226:%.*]] = load i64, ptr [[ULE]], align 8
15373 // CHECK-NEXT:    [[TMP1227:%.*]] = load i64, ptr [[ULD]], align 8
15374 // CHECK-NEXT:    [[TMP1228:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1226]], i64 [[TMP1227]] monotonic monotonic, align 8
15375 // CHECK-NEXT:    [[TMP1229:%.*]] = load i64, ptr [[ULE]], align 8
15376 // CHECK-NEXT:    [[TMP1230:%.*]] = load i64, ptr [[ULD]], align 8
15377 // CHECK-NEXT:    [[TMP1231:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1229]], i64 [[TMP1230]] monotonic monotonic, align 8
15378 // CHECK-NEXT:    [[TMP1232:%.*]] = load i64, ptr [[LE]], align 8
15379 // CHECK-NEXT:    [[TMP1233:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1232]] release, align 8
15380 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15381 // CHECK-NEXT:    [[TMP1234:%.*]] = load i64, ptr [[LE]], align 8
15382 // CHECK-NEXT:    [[TMP1235:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1234]] release, align 8
15383 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15384 // CHECK-NEXT:    [[TMP1236:%.*]] = load i64, ptr [[LE]], align 8
15385 // CHECK-NEXT:    [[TMP1237:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1236]] release, align 8
15386 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15387 // CHECK-NEXT:    [[TMP1238:%.*]] = load i64, ptr [[LE]], align 8
15388 // CHECK-NEXT:    [[TMP1239:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1238]] release, align 8
15389 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15390 // CHECK-NEXT:    [[TMP1240:%.*]] = load i64, ptr [[LE]], align 8
15391 // CHECK-NEXT:    [[TMP1241:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1240]] release, align 8
15392 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15393 // CHECK-NEXT:    [[TMP1242:%.*]] = load i64, ptr [[LE]], align 8
15394 // CHECK-NEXT:    [[TMP1243:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1242]] release, align 8
15395 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15396 // CHECK-NEXT:    [[TMP1244:%.*]] = load i64, ptr [[LE]], align 8
15397 // CHECK-NEXT:    [[TMP1245:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1244]] release, align 8
15398 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15399 // CHECK-NEXT:    [[TMP1246:%.*]] = load i64, ptr [[LE]], align 8
15400 // CHECK-NEXT:    [[TMP1247:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1246]] release, align 8
15401 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15402 // CHECK-NEXT:    [[TMP1248:%.*]] = load i64, ptr [[LE]], align 8
15403 // CHECK-NEXT:    [[TMP1249:%.*]] = load i64, ptr [[LD]], align 8
15404 // CHECK-NEXT:    [[TMP1250:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1248]], i64 [[TMP1249]] release monotonic, align 8
15405 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15406 // CHECK-NEXT:    [[TMP1251:%.*]] = load i64, ptr [[LE]], align 8
15407 // CHECK-NEXT:    [[TMP1252:%.*]] = load i64, ptr [[LD]], align 8
15408 // CHECK-NEXT:    [[TMP1253:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1251]], i64 [[TMP1252]] release monotonic, align 8
15409 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15410 // CHECK-NEXT:    [[TMP1254:%.*]] = load i64, ptr [[LE]], align 8
15411 // CHECK-NEXT:    [[TMP1255:%.*]] = load i64, ptr [[LD]], align 8
15412 // CHECK-NEXT:    [[TMP1256:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1254]], i64 [[TMP1255]] release monotonic, align 8
15413 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15414 // CHECK-NEXT:    [[TMP1257:%.*]] = load i64, ptr [[LE]], align 8
15415 // CHECK-NEXT:    [[TMP1258:%.*]] = load i64, ptr [[LD]], align 8
15416 // CHECK-NEXT:    [[TMP1259:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1257]], i64 [[TMP1258]] release monotonic, align 8
15417 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15418 // CHECK-NEXT:    [[TMP1260:%.*]] = load i64, ptr [[ULE]], align 8
15419 // CHECK-NEXT:    [[TMP1261:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1260]] release, align 8
15420 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15421 // CHECK-NEXT:    [[TMP1262:%.*]] = load i64, ptr [[ULE]], align 8
15422 // CHECK-NEXT:    [[TMP1263:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1262]] release, align 8
15423 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15424 // CHECK-NEXT:    [[TMP1264:%.*]] = load i64, ptr [[ULE]], align 8
15425 // CHECK-NEXT:    [[TMP1265:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1264]] release, align 8
15426 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15427 // CHECK-NEXT:    [[TMP1266:%.*]] = load i64, ptr [[ULE]], align 8
15428 // CHECK-NEXT:    [[TMP1267:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1266]] release, align 8
15429 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15430 // CHECK-NEXT:    [[TMP1268:%.*]] = load i64, ptr [[ULE]], align 8
15431 // CHECK-NEXT:    [[TMP1269:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1268]] release, align 8
15432 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15433 // CHECK-NEXT:    [[TMP1270:%.*]] = load i64, ptr [[ULE]], align 8
15434 // CHECK-NEXT:    [[TMP1271:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1270]] release, align 8
15435 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15436 // CHECK-NEXT:    [[TMP1272:%.*]] = load i64, ptr [[ULE]], align 8
15437 // CHECK-NEXT:    [[TMP1273:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1272]] release, align 8
15438 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15439 // CHECK-NEXT:    [[TMP1274:%.*]] = load i64, ptr [[ULE]], align 8
15440 // CHECK-NEXT:    [[TMP1275:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1274]] release, align 8
15441 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15442 // CHECK-NEXT:    [[TMP1276:%.*]] = load i64, ptr [[ULE]], align 8
15443 // CHECK-NEXT:    [[TMP1277:%.*]] = load i64, ptr [[ULD]], align 8
15444 // CHECK-NEXT:    [[TMP1278:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1276]], i64 [[TMP1277]] release monotonic, align 8
15445 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15446 // CHECK-NEXT:    [[TMP1279:%.*]] = load i64, ptr [[ULE]], align 8
15447 // CHECK-NEXT:    [[TMP1280:%.*]] = load i64, ptr [[ULD]], align 8
15448 // CHECK-NEXT:    [[TMP1281:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1279]], i64 [[TMP1280]] release monotonic, align 8
15449 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15450 // CHECK-NEXT:    [[TMP1282:%.*]] = load i64, ptr [[ULE]], align 8
15451 // CHECK-NEXT:    [[TMP1283:%.*]] = load i64, ptr [[ULD]], align 8
15452 // CHECK-NEXT:    [[TMP1284:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1282]], i64 [[TMP1283]] release monotonic, align 8
15453 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15454 // CHECK-NEXT:    [[TMP1285:%.*]] = load i64, ptr [[ULE]], align 8
15455 // CHECK-NEXT:    [[TMP1286:%.*]] = load i64, ptr [[ULD]], align 8
15456 // CHECK-NEXT:    [[TMP1287:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1285]], i64 [[TMP1286]] release monotonic, align 8
15457 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15458 // CHECK-NEXT:    [[TMP1288:%.*]] = load i64, ptr [[LE]], align 8
15459 // CHECK-NEXT:    [[TMP1289:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1288]] seq_cst, align 8
15460 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15461 // CHECK-NEXT:    [[TMP1290:%.*]] = load i64, ptr [[LE]], align 8
15462 // CHECK-NEXT:    [[TMP1291:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1290]] seq_cst, align 8
15463 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15464 // CHECK-NEXT:    [[TMP1292:%.*]] = load i64, ptr [[LE]], align 8
15465 // CHECK-NEXT:    [[TMP1293:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1292]] seq_cst, align 8
15466 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15467 // CHECK-NEXT:    [[TMP1294:%.*]] = load i64, ptr [[LE]], align 8
15468 // CHECK-NEXT:    [[TMP1295:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1294]] seq_cst, align 8
15469 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15470 // CHECK-NEXT:    [[TMP1296:%.*]] = load i64, ptr [[LE]], align 8
15471 // CHECK-NEXT:    [[TMP1297:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1296]] seq_cst, align 8
15472 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15473 // CHECK-NEXT:    [[TMP1298:%.*]] = load i64, ptr [[LE]], align 8
15474 // CHECK-NEXT:    [[TMP1299:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1298]] seq_cst, align 8
15475 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15476 // CHECK-NEXT:    [[TMP1300:%.*]] = load i64, ptr [[LE]], align 8
15477 // CHECK-NEXT:    [[TMP1301:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1300]] seq_cst, align 8
15478 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15479 // CHECK-NEXT:    [[TMP1302:%.*]] = load i64, ptr [[LE]], align 8
15480 // CHECK-NEXT:    [[TMP1303:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1302]] seq_cst, align 8
15481 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15482 // CHECK-NEXT:    [[TMP1304:%.*]] = load i64, ptr [[LE]], align 8
15483 // CHECK-NEXT:    [[TMP1305:%.*]] = load i64, ptr [[LD]], align 8
15484 // CHECK-NEXT:    [[TMP1306:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1304]], i64 [[TMP1305]] seq_cst seq_cst, align 8
15485 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15486 // CHECK-NEXT:    [[TMP1307:%.*]] = load i64, ptr [[LE]], align 8
15487 // CHECK-NEXT:    [[TMP1308:%.*]] = load i64, ptr [[LD]], align 8
15488 // CHECK-NEXT:    [[TMP1309:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1307]], i64 [[TMP1308]] seq_cst seq_cst, align 8
15489 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15490 // CHECK-NEXT:    [[TMP1310:%.*]] = load i64, ptr [[LE]], align 8
15491 // CHECK-NEXT:    [[TMP1311:%.*]] = load i64, ptr [[LD]], align 8
15492 // CHECK-NEXT:    [[TMP1312:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1310]], i64 [[TMP1311]] seq_cst seq_cst, align 8
15493 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15494 // CHECK-NEXT:    [[TMP1313:%.*]] = load i64, ptr [[LE]], align 8
15495 // CHECK-NEXT:    [[TMP1314:%.*]] = load i64, ptr [[LD]], align 8
15496 // CHECK-NEXT:    [[TMP1315:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1313]], i64 [[TMP1314]] seq_cst seq_cst, align 8
15497 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15498 // CHECK-NEXT:    [[TMP1316:%.*]] = load i64, ptr [[ULE]], align 8
15499 // CHECK-NEXT:    [[TMP1317:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1316]] seq_cst, align 8
15500 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15501 // CHECK-NEXT:    [[TMP1318:%.*]] = load i64, ptr [[ULE]], align 8
15502 // CHECK-NEXT:    [[TMP1319:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1318]] seq_cst, align 8
15503 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15504 // CHECK-NEXT:    [[TMP1320:%.*]] = load i64, ptr [[ULE]], align 8
15505 // CHECK-NEXT:    [[TMP1321:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1320]] seq_cst, align 8
15506 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15507 // CHECK-NEXT:    [[TMP1322:%.*]] = load i64, ptr [[ULE]], align 8
15508 // CHECK-NEXT:    [[TMP1323:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1322]] seq_cst, align 8
15509 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15510 // CHECK-NEXT:    [[TMP1324:%.*]] = load i64, ptr [[ULE]], align 8
15511 // CHECK-NEXT:    [[TMP1325:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1324]] seq_cst, align 8
15512 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15513 // CHECK-NEXT:    [[TMP1326:%.*]] = load i64, ptr [[ULE]], align 8
15514 // CHECK-NEXT:    [[TMP1327:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1326]] seq_cst, align 8
15515 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15516 // CHECK-NEXT:    [[TMP1328:%.*]] = load i64, ptr [[ULE]], align 8
15517 // CHECK-NEXT:    [[TMP1329:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1328]] seq_cst, align 8
15518 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15519 // CHECK-NEXT:    [[TMP1330:%.*]] = load i64, ptr [[ULE]], align 8
15520 // CHECK-NEXT:    [[TMP1331:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1330]] seq_cst, align 8
15521 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15522 // CHECK-NEXT:    [[TMP1332:%.*]] = load i64, ptr [[ULE]], align 8
15523 // CHECK-NEXT:    [[TMP1333:%.*]] = load i64, ptr [[ULD]], align 8
15524 // CHECK-NEXT:    [[TMP1334:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1332]], i64 [[TMP1333]] seq_cst seq_cst, align 8
15525 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15526 // CHECK-NEXT:    [[TMP1335:%.*]] = load i64, ptr [[ULE]], align 8
15527 // CHECK-NEXT:    [[TMP1336:%.*]] = load i64, ptr [[ULD]], align 8
15528 // CHECK-NEXT:    [[TMP1337:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1335]], i64 [[TMP1336]] seq_cst seq_cst, align 8
15529 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15530 // CHECK-NEXT:    [[TMP1338:%.*]] = load i64, ptr [[ULE]], align 8
15531 // CHECK-NEXT:    [[TMP1339:%.*]] = load i64, ptr [[ULD]], align 8
15532 // CHECK-NEXT:    [[TMP1340:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1338]], i64 [[TMP1339]] seq_cst seq_cst, align 8
15533 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15534 // CHECK-NEXT:    [[TMP1341:%.*]] = load i64, ptr [[ULE]], align 8
15535 // CHECK-NEXT:    [[TMP1342:%.*]] = load i64, ptr [[ULD]], align 8
15536 // CHECK-NEXT:    [[TMP1343:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1341]], i64 [[TMP1342]] seq_cst seq_cst, align 8
15537 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15538 // CHECK-NEXT:    [[TMP1344:%.*]] = load i64, ptr [[LLE]], align 8
15539 // CHECK-NEXT:    [[TMP1345:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1344]] monotonic, align 8
15540 // CHECK-NEXT:    [[TMP1346:%.*]] = load i64, ptr [[LLE]], align 8
15541 // CHECK-NEXT:    [[TMP1347:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1346]] monotonic, align 8
15542 // CHECK-NEXT:    [[TMP1348:%.*]] = load i64, ptr [[LLE]], align 8
15543 // CHECK-NEXT:    [[TMP1349:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1348]] monotonic, align 8
15544 // CHECK-NEXT:    [[TMP1350:%.*]] = load i64, ptr [[LLE]], align 8
15545 // CHECK-NEXT:    [[TMP1351:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1350]] monotonic, align 8
15546 // CHECK-NEXT:    [[TMP1352:%.*]] = load i64, ptr [[LLE]], align 8
15547 // CHECK-NEXT:    [[TMP1353:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1352]] monotonic, align 8
15548 // CHECK-NEXT:    [[TMP1354:%.*]] = load i64, ptr [[LLE]], align 8
15549 // CHECK-NEXT:    [[TMP1355:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1354]] monotonic, align 8
15550 // CHECK-NEXT:    [[TMP1356:%.*]] = load i64, ptr [[LLE]], align 8
15551 // CHECK-NEXT:    [[TMP1357:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1356]] monotonic, align 8
15552 // CHECK-NEXT:    [[TMP1358:%.*]] = load i64, ptr [[LLE]], align 8
15553 // CHECK-NEXT:    [[TMP1359:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1358]] monotonic, align 8
15554 // CHECK-NEXT:    [[TMP1360:%.*]] = load i64, ptr [[LLE]], align 8
15555 // CHECK-NEXT:    [[TMP1361:%.*]] = load i64, ptr [[LLD]], align 8
15556 // CHECK-NEXT:    [[TMP1362:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1360]], i64 [[TMP1361]] monotonic monotonic, align 8
15557 // CHECK-NEXT:    [[TMP1363:%.*]] = load i64, ptr [[LLE]], align 8
15558 // CHECK-NEXT:    [[TMP1364:%.*]] = load i64, ptr [[LLD]], align 8
15559 // CHECK-NEXT:    [[TMP1365:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1363]], i64 [[TMP1364]] monotonic monotonic, align 8
15560 // CHECK-NEXT:    [[TMP1366:%.*]] = load i64, ptr [[LLE]], align 8
15561 // CHECK-NEXT:    [[TMP1367:%.*]] = load i64, ptr [[LLD]], align 8
15562 // CHECK-NEXT:    [[TMP1368:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1366]], i64 [[TMP1367]] monotonic monotonic, align 8
15563 // CHECK-NEXT:    [[TMP1369:%.*]] = load i64, ptr [[LLE]], align 8
15564 // CHECK-NEXT:    [[TMP1370:%.*]] = load i64, ptr [[LLD]], align 8
15565 // CHECK-NEXT:    [[TMP1371:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1369]], i64 [[TMP1370]] monotonic monotonic, align 8
15566 // CHECK-NEXT:    [[TMP1372:%.*]] = load i64, ptr [[ULLE]], align 8
15567 // CHECK-NEXT:    [[TMP1373:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1372]] monotonic, align 8
15568 // CHECK-NEXT:    [[TMP1374:%.*]] = load i64, ptr [[ULLE]], align 8
15569 // CHECK-NEXT:    [[TMP1375:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1374]] monotonic, align 8
15570 // CHECK-NEXT:    [[TMP1376:%.*]] = load i64, ptr [[ULLE]], align 8
15571 // CHECK-NEXT:    [[TMP1377:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1376]] monotonic, align 8
15572 // CHECK-NEXT:    [[TMP1378:%.*]] = load i64, ptr [[ULLE]], align 8
15573 // CHECK-NEXT:    [[TMP1379:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1378]] monotonic, align 8
15574 // CHECK-NEXT:    [[TMP1380:%.*]] = load i64, ptr [[ULLE]], align 8
15575 // CHECK-NEXT:    [[TMP1381:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1380]] monotonic, align 8
15576 // CHECK-NEXT:    [[TMP1382:%.*]] = load i64, ptr [[ULLE]], align 8
15577 // CHECK-NEXT:    [[TMP1383:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1382]] monotonic, align 8
15578 // CHECK-NEXT:    [[TMP1384:%.*]] = load i64, ptr [[ULLE]], align 8
15579 // CHECK-NEXT:    [[TMP1385:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1384]] monotonic, align 8
15580 // CHECK-NEXT:    [[TMP1386:%.*]] = load i64, ptr [[ULLE]], align 8
15581 // CHECK-NEXT:    [[TMP1387:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1386]] monotonic, align 8
15582 // CHECK-NEXT:    [[TMP1388:%.*]] = load i64, ptr [[ULLE]], align 8
15583 // CHECK-NEXT:    [[TMP1389:%.*]] = load i64, ptr [[ULLD]], align 8
15584 // CHECK-NEXT:    [[TMP1390:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1388]], i64 [[TMP1389]] monotonic monotonic, align 8
15585 // CHECK-NEXT:    [[TMP1391:%.*]] = load i64, ptr [[ULLE]], align 8
15586 // CHECK-NEXT:    [[TMP1392:%.*]] = load i64, ptr [[ULLD]], align 8
15587 // CHECK-NEXT:    [[TMP1393:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1391]], i64 [[TMP1392]] monotonic monotonic, align 8
15588 // CHECK-NEXT:    [[TMP1394:%.*]] = load i64, ptr [[ULLE]], align 8
15589 // CHECK-NEXT:    [[TMP1395:%.*]] = load i64, ptr [[ULLD]], align 8
15590 // CHECK-NEXT:    [[TMP1396:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1394]], i64 [[TMP1395]] monotonic monotonic, align 8
15591 // CHECK-NEXT:    [[TMP1397:%.*]] = load i64, ptr [[ULLE]], align 8
15592 // CHECK-NEXT:    [[TMP1398:%.*]] = load i64, ptr [[ULLD]], align 8
15593 // CHECK-NEXT:    [[TMP1399:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1397]], i64 [[TMP1398]] monotonic monotonic, align 8
15594 // CHECK-NEXT:    [[TMP1400:%.*]] = load i64, ptr [[LLE]], align 8
15595 // CHECK-NEXT:    [[TMP1401:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1400]] acq_rel, align 8
15596 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15597 // CHECK-NEXT:    [[TMP1402:%.*]] = load i64, ptr [[LLE]], align 8
15598 // CHECK-NEXT:    [[TMP1403:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1402]] acq_rel, align 8
15599 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15600 // CHECK-NEXT:    [[TMP1404:%.*]] = load i64, ptr [[LLE]], align 8
15601 // CHECK-NEXT:    [[TMP1405:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1404]] acq_rel, align 8
15602 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15603 // CHECK-NEXT:    [[TMP1406:%.*]] = load i64, ptr [[LLE]], align 8
15604 // CHECK-NEXT:    [[TMP1407:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1406]] acq_rel, align 8
15605 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15606 // CHECK-NEXT:    [[TMP1408:%.*]] = load i64, ptr [[LLE]], align 8
15607 // CHECK-NEXT:    [[TMP1409:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1408]] acq_rel, align 8
15608 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15609 // CHECK-NEXT:    [[TMP1410:%.*]] = load i64, ptr [[LLE]], align 8
15610 // CHECK-NEXT:    [[TMP1411:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1410]] acq_rel, align 8
15611 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15612 // CHECK-NEXT:    [[TMP1412:%.*]] = load i64, ptr [[LLE]], align 8
15613 // CHECK-NEXT:    [[TMP1413:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1412]] acq_rel, align 8
15614 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15615 // CHECK-NEXT:    [[TMP1414:%.*]] = load i64, ptr [[LLE]], align 8
15616 // CHECK-NEXT:    [[TMP1415:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1414]] acq_rel, align 8
15617 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15618 // CHECK-NEXT:    [[TMP1416:%.*]] = load i64, ptr [[LLE]], align 8
15619 // CHECK-NEXT:    [[TMP1417:%.*]] = load i64, ptr [[LLD]], align 8
15620 // CHECK-NEXT:    [[TMP1418:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1416]], i64 [[TMP1417]] acq_rel acquire, align 8
15621 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15622 // CHECK-NEXT:    [[TMP1419:%.*]] = load i64, ptr [[LLE]], align 8
15623 // CHECK-NEXT:    [[TMP1420:%.*]] = load i64, ptr [[LLD]], align 8
15624 // CHECK-NEXT:    [[TMP1421:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1419]], i64 [[TMP1420]] acq_rel acquire, align 8
15625 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15626 // CHECK-NEXT:    [[TMP1422:%.*]] = load i64, ptr [[LLE]], align 8
15627 // CHECK-NEXT:    [[TMP1423:%.*]] = load i64, ptr [[LLD]], align 8
15628 // CHECK-NEXT:    [[TMP1424:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1422]], i64 [[TMP1423]] acq_rel acquire, align 8
15629 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15630 // CHECK-NEXT:    [[TMP1425:%.*]] = load i64, ptr [[LLE]], align 8
15631 // CHECK-NEXT:    [[TMP1426:%.*]] = load i64, ptr [[LLD]], align 8
15632 // CHECK-NEXT:    [[TMP1427:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1425]], i64 [[TMP1426]] acq_rel acquire, align 8
15633 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15634 // CHECK-NEXT:    [[TMP1428:%.*]] = load i64, ptr [[ULLE]], align 8
15635 // CHECK-NEXT:    [[TMP1429:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1428]] acq_rel, align 8
15636 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15637 // CHECK-NEXT:    [[TMP1430:%.*]] = load i64, ptr [[ULLE]], align 8
15638 // CHECK-NEXT:    [[TMP1431:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1430]] acq_rel, align 8
15639 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15640 // CHECK-NEXT:    [[TMP1432:%.*]] = load i64, ptr [[ULLE]], align 8
15641 // CHECK-NEXT:    [[TMP1433:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1432]] acq_rel, align 8
15642 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15643 // CHECK-NEXT:    [[TMP1434:%.*]] = load i64, ptr [[ULLE]], align 8
15644 // CHECK-NEXT:    [[TMP1435:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1434]] acq_rel, align 8
15645 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15646 // CHECK-NEXT:    [[TMP1436:%.*]] = load i64, ptr [[ULLE]], align 8
15647 // CHECK-NEXT:    [[TMP1437:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1436]] acq_rel, align 8
15648 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15649 // CHECK-NEXT:    [[TMP1438:%.*]] = load i64, ptr [[ULLE]], align 8
15650 // CHECK-NEXT:    [[TMP1439:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1438]] acq_rel, align 8
15651 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15652 // CHECK-NEXT:    [[TMP1440:%.*]] = load i64, ptr [[ULLE]], align 8
15653 // CHECK-NEXT:    [[TMP1441:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1440]] acq_rel, align 8
15654 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15655 // CHECK-NEXT:    [[TMP1442:%.*]] = load i64, ptr [[ULLE]], align 8
15656 // CHECK-NEXT:    [[TMP1443:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1442]] acq_rel, align 8
15657 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15658 // CHECK-NEXT:    [[TMP1444:%.*]] = load i64, ptr [[ULLE]], align 8
15659 // CHECK-NEXT:    [[TMP1445:%.*]] = load i64, ptr [[ULLD]], align 8
15660 // CHECK-NEXT:    [[TMP1446:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1444]], i64 [[TMP1445]] acq_rel acquire, align 8
15661 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15662 // CHECK-NEXT:    [[TMP1447:%.*]] = load i64, ptr [[ULLE]], align 8
15663 // CHECK-NEXT:    [[TMP1448:%.*]] = load i64, ptr [[ULLD]], align 8
15664 // CHECK-NEXT:    [[TMP1449:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1447]], i64 [[TMP1448]] acq_rel acquire, align 8
15665 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15666 // CHECK-NEXT:    [[TMP1450:%.*]] = load i64, ptr [[ULLE]], align 8
15667 // CHECK-NEXT:    [[TMP1451:%.*]] = load i64, ptr [[ULLD]], align 8
15668 // CHECK-NEXT:    [[TMP1452:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1450]], i64 [[TMP1451]] acq_rel acquire, align 8
15669 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15670 // CHECK-NEXT:    [[TMP1453:%.*]] = load i64, ptr [[ULLE]], align 8
15671 // CHECK-NEXT:    [[TMP1454:%.*]] = load i64, ptr [[ULLD]], align 8
15672 // CHECK-NEXT:    [[TMP1455:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1453]], i64 [[TMP1454]] acq_rel acquire, align 8
15673 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15674 // CHECK-NEXT:    [[TMP1456:%.*]] = load i64, ptr [[LLE]], align 8
15675 // CHECK-NEXT:    [[TMP1457:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1456]] acquire, align 8
15676 // CHECK-NEXT:    [[TMP1458:%.*]] = load i64, ptr [[LLE]], align 8
15677 // CHECK-NEXT:    [[TMP1459:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1458]] acquire, align 8
15678 // CHECK-NEXT:    [[TMP1460:%.*]] = load i64, ptr [[LLE]], align 8
15679 // CHECK-NEXT:    [[TMP1461:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1460]] acquire, align 8
15680 // CHECK-NEXT:    [[TMP1462:%.*]] = load i64, ptr [[LLE]], align 8
15681 // CHECK-NEXT:    [[TMP1463:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1462]] acquire, align 8
15682 // CHECK-NEXT:    [[TMP1464:%.*]] = load i64, ptr [[LLE]], align 8
15683 // CHECK-NEXT:    [[TMP1465:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1464]] acquire, align 8
15684 // CHECK-NEXT:    [[TMP1466:%.*]] = load i64, ptr [[LLE]], align 8
15685 // CHECK-NEXT:    [[TMP1467:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1466]] acquire, align 8
15686 // CHECK-NEXT:    [[TMP1468:%.*]] = load i64, ptr [[LLE]], align 8
15687 // CHECK-NEXT:    [[TMP1469:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1468]] acquire, align 8
15688 // CHECK-NEXT:    [[TMP1470:%.*]] = load i64, ptr [[LLE]], align 8
15689 // CHECK-NEXT:    [[TMP1471:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1470]] acquire, align 8
15690 // CHECK-NEXT:    [[TMP1472:%.*]] = load i64, ptr [[LLE]], align 8
15691 // CHECK-NEXT:    [[TMP1473:%.*]] = load i64, ptr [[LLD]], align 8
15692 // CHECK-NEXT:    [[TMP1474:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1472]], i64 [[TMP1473]] acquire acquire, align 8
15693 // CHECK-NEXT:    [[TMP1475:%.*]] = load i64, ptr [[LLE]], align 8
15694 // CHECK-NEXT:    [[TMP1476:%.*]] = load i64, ptr [[LLD]], align 8
15695 // CHECK-NEXT:    [[TMP1477:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1475]], i64 [[TMP1476]] acquire acquire, align 8
15696 // CHECK-NEXT:    [[TMP1478:%.*]] = load i64, ptr [[LLE]], align 8
15697 // CHECK-NEXT:    [[TMP1479:%.*]] = load i64, ptr [[LLD]], align 8
15698 // CHECK-NEXT:    [[TMP1480:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1478]], i64 [[TMP1479]] acquire acquire, align 8
15699 // CHECK-NEXT:    [[TMP1481:%.*]] = load i64, ptr [[LLE]], align 8
15700 // CHECK-NEXT:    [[TMP1482:%.*]] = load i64, ptr [[LLD]], align 8
15701 // CHECK-NEXT:    [[TMP1483:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1481]], i64 [[TMP1482]] acquire acquire, align 8
15702 // CHECK-NEXT:    [[TMP1484:%.*]] = load i64, ptr [[ULLE]], align 8
15703 // CHECK-NEXT:    [[TMP1485:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1484]] acquire, align 8
15704 // CHECK-NEXT:    [[TMP1486:%.*]] = load i64, ptr [[ULLE]], align 8
15705 // CHECK-NEXT:    [[TMP1487:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1486]] acquire, align 8
15706 // CHECK-NEXT:    [[TMP1488:%.*]] = load i64, ptr [[ULLE]], align 8
15707 // CHECK-NEXT:    [[TMP1489:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1488]] acquire, align 8
15708 // CHECK-NEXT:    [[TMP1490:%.*]] = load i64, ptr [[ULLE]], align 8
15709 // CHECK-NEXT:    [[TMP1491:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1490]] acquire, align 8
15710 // CHECK-NEXT:    [[TMP1492:%.*]] = load i64, ptr [[ULLE]], align 8
15711 // CHECK-NEXT:    [[TMP1493:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1492]] acquire, align 8
15712 // CHECK-NEXT:    [[TMP1494:%.*]] = load i64, ptr [[ULLE]], align 8
15713 // CHECK-NEXT:    [[TMP1495:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1494]] acquire, align 8
15714 // CHECK-NEXT:    [[TMP1496:%.*]] = load i64, ptr [[ULLE]], align 8
15715 // CHECK-NEXT:    [[TMP1497:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1496]] acquire, align 8
15716 // CHECK-NEXT:    [[TMP1498:%.*]] = load i64, ptr [[ULLE]], align 8
15717 // CHECK-NEXT:    [[TMP1499:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1498]] acquire, align 8
15718 // CHECK-NEXT:    [[TMP1500:%.*]] = load i64, ptr [[ULLE]], align 8
15719 // CHECK-NEXT:    [[TMP1501:%.*]] = load i64, ptr [[ULLD]], align 8
15720 // CHECK-NEXT:    [[TMP1502:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1500]], i64 [[TMP1501]] acquire acquire, align 8
15721 // CHECK-NEXT:    [[TMP1503:%.*]] = load i64, ptr [[ULLE]], align 8
15722 // CHECK-NEXT:    [[TMP1504:%.*]] = load i64, ptr [[ULLD]], align 8
15723 // CHECK-NEXT:    [[TMP1505:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1503]], i64 [[TMP1504]] acquire acquire, align 8
15724 // CHECK-NEXT:    [[TMP1506:%.*]] = load i64, ptr [[ULLE]], align 8
15725 // CHECK-NEXT:    [[TMP1507:%.*]] = load i64, ptr [[ULLD]], align 8
15726 // CHECK-NEXT:    [[TMP1508:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1506]], i64 [[TMP1507]] acquire acquire, align 8
15727 // CHECK-NEXT:    [[TMP1509:%.*]] = load i64, ptr [[ULLE]], align 8
15728 // CHECK-NEXT:    [[TMP1510:%.*]] = load i64, ptr [[ULLD]], align 8
15729 // CHECK-NEXT:    [[TMP1511:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1509]], i64 [[TMP1510]] acquire acquire, align 8
15730 // CHECK-NEXT:    [[TMP1512:%.*]] = load i64, ptr [[LLE]], align 8
15731 // CHECK-NEXT:    [[TMP1513:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1512]] monotonic, align 8
15732 // CHECK-NEXT:    [[TMP1514:%.*]] = load i64, ptr [[LLE]], align 8
15733 // CHECK-NEXT:    [[TMP1515:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1514]] monotonic, align 8
15734 // CHECK-NEXT:    [[TMP1516:%.*]] = load i64, ptr [[LLE]], align 8
15735 // CHECK-NEXT:    [[TMP1517:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1516]] monotonic, align 8
15736 // CHECK-NEXT:    [[TMP1518:%.*]] = load i64, ptr [[LLE]], align 8
15737 // CHECK-NEXT:    [[TMP1519:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1518]] monotonic, align 8
15738 // CHECK-NEXT:    [[TMP1520:%.*]] = load i64, ptr [[LLE]], align 8
15739 // CHECK-NEXT:    [[TMP1521:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1520]] monotonic, align 8
15740 // CHECK-NEXT:    [[TMP1522:%.*]] = load i64, ptr [[LLE]], align 8
15741 // CHECK-NEXT:    [[TMP1523:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1522]] monotonic, align 8
15742 // CHECK-NEXT:    [[TMP1524:%.*]] = load i64, ptr [[LLE]], align 8
15743 // CHECK-NEXT:    [[TMP1525:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1524]] monotonic, align 8
15744 // CHECK-NEXT:    [[TMP1526:%.*]] = load i64, ptr [[LLE]], align 8
15745 // CHECK-NEXT:    [[TMP1527:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1526]] monotonic, align 8
15746 // CHECK-NEXT:    [[TMP1528:%.*]] = load i64, ptr [[LLE]], align 8
15747 // CHECK-NEXT:    [[TMP1529:%.*]] = load i64, ptr [[LLD]], align 8
15748 // CHECK-NEXT:    [[TMP1530:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1528]], i64 [[TMP1529]] monotonic monotonic, align 8
15749 // CHECK-NEXT:    [[TMP1531:%.*]] = load i64, ptr [[LLE]], align 8
15750 // CHECK-NEXT:    [[TMP1532:%.*]] = load i64, ptr [[LLD]], align 8
15751 // CHECK-NEXT:    [[TMP1533:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1531]], i64 [[TMP1532]] monotonic monotonic, align 8
15752 // CHECK-NEXT:    [[TMP1534:%.*]] = load i64, ptr [[LLE]], align 8
15753 // CHECK-NEXT:    [[TMP1535:%.*]] = load i64, ptr [[LLD]], align 8
15754 // CHECK-NEXT:    [[TMP1536:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1534]], i64 [[TMP1535]] monotonic monotonic, align 8
15755 // CHECK-NEXT:    [[TMP1537:%.*]] = load i64, ptr [[LLE]], align 8
15756 // CHECK-NEXT:    [[TMP1538:%.*]] = load i64, ptr [[LLD]], align 8
15757 // CHECK-NEXT:    [[TMP1539:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1537]], i64 [[TMP1538]] monotonic monotonic, align 8
15758 // CHECK-NEXT:    [[TMP1540:%.*]] = load i64, ptr [[ULLE]], align 8
15759 // CHECK-NEXT:    [[TMP1541:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1540]] monotonic, align 8
15760 // CHECK-NEXT:    [[TMP1542:%.*]] = load i64, ptr [[ULLE]], align 8
15761 // CHECK-NEXT:    [[TMP1543:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1542]] monotonic, align 8
15762 // CHECK-NEXT:    [[TMP1544:%.*]] = load i64, ptr [[ULLE]], align 8
15763 // CHECK-NEXT:    [[TMP1545:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1544]] monotonic, align 8
15764 // CHECK-NEXT:    [[TMP1546:%.*]] = load i64, ptr [[ULLE]], align 8
15765 // CHECK-NEXT:    [[TMP1547:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1546]] monotonic, align 8
15766 // CHECK-NEXT:    [[TMP1548:%.*]] = load i64, ptr [[ULLE]], align 8
15767 // CHECK-NEXT:    [[TMP1549:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1548]] monotonic, align 8
15768 // CHECK-NEXT:    [[TMP1550:%.*]] = load i64, ptr [[ULLE]], align 8
15769 // CHECK-NEXT:    [[TMP1551:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1550]] monotonic, align 8
15770 // CHECK-NEXT:    [[TMP1552:%.*]] = load i64, ptr [[ULLE]], align 8
15771 // CHECK-NEXT:    [[TMP1553:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1552]] monotonic, align 8
15772 // CHECK-NEXT:    [[TMP1554:%.*]] = load i64, ptr [[ULLE]], align 8
15773 // CHECK-NEXT:    [[TMP1555:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1554]] monotonic, align 8
15774 // CHECK-NEXT:    [[TMP1556:%.*]] = load i64, ptr [[ULLE]], align 8
15775 // CHECK-NEXT:    [[TMP1557:%.*]] = load i64, ptr [[ULLD]], align 8
15776 // CHECK-NEXT:    [[TMP1558:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1556]], i64 [[TMP1557]] monotonic monotonic, align 8
15777 // CHECK-NEXT:    [[TMP1559:%.*]] = load i64, ptr [[ULLE]], align 8
15778 // CHECK-NEXT:    [[TMP1560:%.*]] = load i64, ptr [[ULLD]], align 8
15779 // CHECK-NEXT:    [[TMP1561:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1559]], i64 [[TMP1560]] monotonic monotonic, align 8
15780 // CHECK-NEXT:    [[TMP1562:%.*]] = load i64, ptr [[ULLE]], align 8
15781 // CHECK-NEXT:    [[TMP1563:%.*]] = load i64, ptr [[ULLD]], align 8
15782 // CHECK-NEXT:    [[TMP1564:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1562]], i64 [[TMP1563]] monotonic monotonic, align 8
15783 // CHECK-NEXT:    [[TMP1565:%.*]] = load i64, ptr [[ULLE]], align 8
15784 // CHECK-NEXT:    [[TMP1566:%.*]] = load i64, ptr [[ULLD]], align 8
15785 // CHECK-NEXT:    [[TMP1567:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1565]], i64 [[TMP1566]] monotonic monotonic, align 8
15786 // CHECK-NEXT:    [[TMP1568:%.*]] = load i64, ptr [[LLE]], align 8
15787 // CHECK-NEXT:    [[TMP1569:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1568]] release, align 8
15788 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15789 // CHECK-NEXT:    [[TMP1570:%.*]] = load i64, ptr [[LLE]], align 8
15790 // CHECK-NEXT:    [[TMP1571:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1570]] release, align 8
15791 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15792 // CHECK-NEXT:    [[TMP1572:%.*]] = load i64, ptr [[LLE]], align 8
15793 // CHECK-NEXT:    [[TMP1573:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1572]] release, align 8
15794 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15795 // CHECK-NEXT:    [[TMP1574:%.*]] = load i64, ptr [[LLE]], align 8
15796 // CHECK-NEXT:    [[TMP1575:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1574]] release, align 8
15797 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15798 // CHECK-NEXT:    [[TMP1576:%.*]] = load i64, ptr [[LLE]], align 8
15799 // CHECK-NEXT:    [[TMP1577:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1576]] release, align 8
15800 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15801 // CHECK-NEXT:    [[TMP1578:%.*]] = load i64, ptr [[LLE]], align 8
15802 // CHECK-NEXT:    [[TMP1579:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1578]] release, align 8
15803 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15804 // CHECK-NEXT:    [[TMP1580:%.*]] = load i64, ptr [[LLE]], align 8
15805 // CHECK-NEXT:    [[TMP1581:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1580]] release, align 8
15806 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15807 // CHECK-NEXT:    [[TMP1582:%.*]] = load i64, ptr [[LLE]], align 8
15808 // CHECK-NEXT:    [[TMP1583:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1582]] release, align 8
15809 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15810 // CHECK-NEXT:    [[TMP1584:%.*]] = load i64, ptr [[LLE]], align 8
15811 // CHECK-NEXT:    [[TMP1585:%.*]] = load i64, ptr [[LLD]], align 8
15812 // CHECK-NEXT:    [[TMP1586:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1584]], i64 [[TMP1585]] release monotonic, align 8
15813 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15814 // CHECK-NEXT:    [[TMP1587:%.*]] = load i64, ptr [[LLE]], align 8
15815 // CHECK-NEXT:    [[TMP1588:%.*]] = load i64, ptr [[LLD]], align 8
15816 // CHECK-NEXT:    [[TMP1589:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1587]], i64 [[TMP1588]] release monotonic, align 8
15817 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15818 // CHECK-NEXT:    [[TMP1590:%.*]] = load i64, ptr [[LLE]], align 8
15819 // CHECK-NEXT:    [[TMP1591:%.*]] = load i64, ptr [[LLD]], align 8
15820 // CHECK-NEXT:    [[TMP1592:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1590]], i64 [[TMP1591]] release monotonic, align 8
15821 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15822 // CHECK-NEXT:    [[TMP1593:%.*]] = load i64, ptr [[LLE]], align 8
15823 // CHECK-NEXT:    [[TMP1594:%.*]] = load i64, ptr [[LLD]], align 8
15824 // CHECK-NEXT:    [[TMP1595:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1593]], i64 [[TMP1594]] release monotonic, align 8
15825 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15826 // CHECK-NEXT:    [[TMP1596:%.*]] = load i64, ptr [[ULLE]], align 8
15827 // CHECK-NEXT:    [[TMP1597:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1596]] release, align 8
15828 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15829 // CHECK-NEXT:    [[TMP1598:%.*]] = load i64, ptr [[ULLE]], align 8
15830 // CHECK-NEXT:    [[TMP1599:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1598]] release, align 8
15831 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15832 // CHECK-NEXT:    [[TMP1600:%.*]] = load i64, ptr [[ULLE]], align 8
15833 // CHECK-NEXT:    [[TMP1601:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1600]] release, align 8
15834 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15835 // CHECK-NEXT:    [[TMP1602:%.*]] = load i64, ptr [[ULLE]], align 8
15836 // CHECK-NEXT:    [[TMP1603:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1602]] release, align 8
15837 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15838 // CHECK-NEXT:    [[TMP1604:%.*]] = load i64, ptr [[ULLE]], align 8
15839 // CHECK-NEXT:    [[TMP1605:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1604]] release, align 8
15840 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15841 // CHECK-NEXT:    [[TMP1606:%.*]] = load i64, ptr [[ULLE]], align 8
15842 // CHECK-NEXT:    [[TMP1607:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1606]] release, align 8
15843 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15844 // CHECK-NEXT:    [[TMP1608:%.*]] = load i64, ptr [[ULLE]], align 8
15845 // CHECK-NEXT:    [[TMP1609:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1608]] release, align 8
15846 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15847 // CHECK-NEXT:    [[TMP1610:%.*]] = load i64, ptr [[ULLE]], align 8
15848 // CHECK-NEXT:    [[TMP1611:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1610]] release, align 8
15849 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15850 // CHECK-NEXT:    [[TMP1612:%.*]] = load i64, ptr [[ULLE]], align 8
15851 // CHECK-NEXT:    [[TMP1613:%.*]] = load i64, ptr [[ULLD]], align 8
15852 // CHECK-NEXT:    [[TMP1614:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1612]], i64 [[TMP1613]] release monotonic, align 8
15853 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15854 // CHECK-NEXT:    [[TMP1615:%.*]] = load i64, ptr [[ULLE]], align 8
15855 // CHECK-NEXT:    [[TMP1616:%.*]] = load i64, ptr [[ULLD]], align 8
15856 // CHECK-NEXT:    [[TMP1617:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1615]], i64 [[TMP1616]] release monotonic, align 8
15857 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15858 // CHECK-NEXT:    [[TMP1618:%.*]] = load i64, ptr [[ULLE]], align 8
15859 // CHECK-NEXT:    [[TMP1619:%.*]] = load i64, ptr [[ULLD]], align 8
15860 // CHECK-NEXT:    [[TMP1620:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1618]], i64 [[TMP1619]] release monotonic, align 8
15861 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15862 // CHECK-NEXT:    [[TMP1621:%.*]] = load i64, ptr [[ULLE]], align 8
15863 // CHECK-NEXT:    [[TMP1622:%.*]] = load i64, ptr [[ULLD]], align 8
15864 // CHECK-NEXT:    [[TMP1623:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1621]], i64 [[TMP1622]] release monotonic, align 8
15865 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15866 // CHECK-NEXT:    [[TMP1624:%.*]] = load i64, ptr [[LLE]], align 8
15867 // CHECK-NEXT:    [[TMP1625:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1624]] seq_cst, align 8
15868 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15869 // CHECK-NEXT:    [[TMP1626:%.*]] = load i64, ptr [[LLE]], align 8
15870 // CHECK-NEXT:    [[TMP1627:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1626]] seq_cst, align 8
15871 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15872 // CHECK-NEXT:    [[TMP1628:%.*]] = load i64, ptr [[LLE]], align 8
15873 // CHECK-NEXT:    [[TMP1629:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1628]] seq_cst, align 8
15874 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15875 // CHECK-NEXT:    [[TMP1630:%.*]] = load i64, ptr [[LLE]], align 8
15876 // CHECK-NEXT:    [[TMP1631:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1630]] seq_cst, align 8
15877 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15878 // CHECK-NEXT:    [[TMP1632:%.*]] = load i64, ptr [[LLE]], align 8
15879 // CHECK-NEXT:    [[TMP1633:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1632]] seq_cst, align 8
15880 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15881 // CHECK-NEXT:    [[TMP1634:%.*]] = load i64, ptr [[LLE]], align 8
15882 // CHECK-NEXT:    [[TMP1635:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1634]] seq_cst, align 8
15883 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15884 // CHECK-NEXT:    [[TMP1636:%.*]] = load i64, ptr [[LLE]], align 8
15885 // CHECK-NEXT:    [[TMP1637:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1636]] seq_cst, align 8
15886 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15887 // CHECK-NEXT:    [[TMP1638:%.*]] = load i64, ptr [[LLE]], align 8
15888 // CHECK-NEXT:    [[TMP1639:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1638]] seq_cst, align 8
15889 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15890 // CHECK-NEXT:    [[TMP1640:%.*]] = load i64, ptr [[LLE]], align 8
15891 // CHECK-NEXT:    [[TMP1641:%.*]] = load i64, ptr [[LLD]], align 8
15892 // CHECK-NEXT:    [[TMP1642:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1640]], i64 [[TMP1641]] seq_cst seq_cst, align 8
15893 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15894 // CHECK-NEXT:    [[TMP1643:%.*]] = load i64, ptr [[LLE]], align 8
15895 // CHECK-NEXT:    [[TMP1644:%.*]] = load i64, ptr [[LLD]], align 8
15896 // CHECK-NEXT:    [[TMP1645:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1643]], i64 [[TMP1644]] seq_cst seq_cst, align 8
15897 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15898 // CHECK-NEXT:    [[TMP1646:%.*]] = load i64, ptr [[LLE]], align 8
15899 // CHECK-NEXT:    [[TMP1647:%.*]] = load i64, ptr [[LLD]], align 8
15900 // CHECK-NEXT:    [[TMP1648:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1646]], i64 [[TMP1647]] seq_cst seq_cst, align 8
15901 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15902 // CHECK-NEXT:    [[TMP1649:%.*]] = load i64, ptr [[LLE]], align 8
15903 // CHECK-NEXT:    [[TMP1650:%.*]] = load i64, ptr [[LLD]], align 8
15904 // CHECK-NEXT:    [[TMP1651:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1649]], i64 [[TMP1650]] seq_cst seq_cst, align 8
15905 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15906 // CHECK-NEXT:    [[TMP1652:%.*]] = load i64, ptr [[ULLE]], align 8
15907 // CHECK-NEXT:    [[TMP1653:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1652]] seq_cst, align 8
15908 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15909 // CHECK-NEXT:    [[TMP1654:%.*]] = load i64, ptr [[ULLE]], align 8
15910 // CHECK-NEXT:    [[TMP1655:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1654]] seq_cst, align 8
15911 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15912 // CHECK-NEXT:    [[TMP1656:%.*]] = load i64, ptr [[ULLE]], align 8
15913 // CHECK-NEXT:    [[TMP1657:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1656]] seq_cst, align 8
15914 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15915 // CHECK-NEXT:    [[TMP1658:%.*]] = load i64, ptr [[ULLE]], align 8
15916 // CHECK-NEXT:    [[TMP1659:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1658]] seq_cst, align 8
15917 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15918 // CHECK-NEXT:    [[TMP1660:%.*]] = load i64, ptr [[ULLE]], align 8
15919 // CHECK-NEXT:    [[TMP1661:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1660]] seq_cst, align 8
15920 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15921 // CHECK-NEXT:    [[TMP1662:%.*]] = load i64, ptr [[ULLE]], align 8
15922 // CHECK-NEXT:    [[TMP1663:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1662]] seq_cst, align 8
15923 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15924 // CHECK-NEXT:    [[TMP1664:%.*]] = load i64, ptr [[ULLE]], align 8
15925 // CHECK-NEXT:    [[TMP1665:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1664]] seq_cst, align 8
15926 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15927 // CHECK-NEXT:    [[TMP1666:%.*]] = load i64, ptr [[ULLE]], align 8
15928 // CHECK-NEXT:    [[TMP1667:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1666]] seq_cst, align 8
15929 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15930 // CHECK-NEXT:    [[TMP1668:%.*]] = load i64, ptr [[ULLE]], align 8
15931 // CHECK-NEXT:    [[TMP1669:%.*]] = load i64, ptr [[ULLD]], align 8
15932 // CHECK-NEXT:    [[TMP1670:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1668]], i64 [[TMP1669]] seq_cst seq_cst, align 8
15933 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15934 // CHECK-NEXT:    [[TMP1671:%.*]] = load i64, ptr [[ULLE]], align 8
15935 // CHECK-NEXT:    [[TMP1672:%.*]] = load i64, ptr [[ULLD]], align 8
15936 // CHECK-NEXT:    [[TMP1673:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1671]], i64 [[TMP1672]] seq_cst seq_cst, align 8
15937 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15938 // CHECK-NEXT:    [[TMP1674:%.*]] = load i64, ptr [[ULLE]], align 8
15939 // CHECK-NEXT:    [[TMP1675:%.*]] = load i64, ptr [[ULLD]], align 8
15940 // CHECK-NEXT:    [[TMP1676:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1674]], i64 [[TMP1675]] seq_cst seq_cst, align 8
15941 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15942 // CHECK-NEXT:    [[TMP1677:%.*]] = load i64, ptr [[ULLE]], align 8
15943 // CHECK-NEXT:    [[TMP1678:%.*]] = load i64, ptr [[ULLD]], align 8
15944 // CHECK-NEXT:    [[TMP1679:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1677]], i64 [[TMP1678]] seq_cst seq_cst, align 8
15945 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15946 // CHECK-NEXT:    [[TMP1680:%.*]] = load float, ptr [[FE]], align 4
15947 // CHECK-NEXT:    [[TMP1681:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1680]] monotonic, align 4
15948 // CHECK-NEXT:    [[TMP1682:%.*]] = load float, ptr [[FE]], align 4
15949 // CHECK-NEXT:    [[TMP1683:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1682]] monotonic, align 4
15950 // CHECK-NEXT:    [[TMP1684:%.*]] = load float, ptr [[FE]], align 4
15951 // CHECK-NEXT:    [[TMP1685:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1684]] monotonic, align 4
15952 // CHECK-NEXT:    [[TMP1686:%.*]] = load float, ptr [[FE]], align 4
15953 // CHECK-NEXT:    [[TMP1687:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1686]] monotonic, align 4
15954 // CHECK-NEXT:    [[TMP1688:%.*]] = load float, ptr [[FE]], align 4
15955 // CHECK-NEXT:    [[TMP1689:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1688]] monotonic, align 4
15956 // CHECK-NEXT:    [[TMP1690:%.*]] = load float, ptr [[FE]], align 4
15957 // CHECK-NEXT:    [[TMP1691:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1690]] monotonic, align 4
15958 // CHECK-NEXT:    [[TMP1692:%.*]] = load float, ptr [[FE]], align 4
15959 // CHECK-NEXT:    [[TMP1693:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1692]] monotonic, align 4
15960 // CHECK-NEXT:    [[TMP1694:%.*]] = load float, ptr [[FE]], align 4
15961 // CHECK-NEXT:    [[TMP1695:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1694]] monotonic, align 4
15962 // CHECK-NEXT:    [[TMP1696:%.*]] = load float, ptr [[FE]], align 4
15963 // CHECK-NEXT:    [[TMP1697:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1696]] acq_rel, align 4
15964 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15965 // CHECK-NEXT:    [[TMP1698:%.*]] = load float, ptr [[FE]], align 4
15966 // CHECK-NEXT:    [[TMP1699:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1698]] acq_rel, align 4
15967 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15968 // CHECK-NEXT:    [[TMP1700:%.*]] = load float, ptr [[FE]], align 4
15969 // CHECK-NEXT:    [[TMP1701:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1700]] acq_rel, align 4
15970 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15971 // CHECK-NEXT:    [[TMP1702:%.*]] = load float, ptr [[FE]], align 4
15972 // CHECK-NEXT:    [[TMP1703:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1702]] acq_rel, align 4
15973 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15974 // CHECK-NEXT:    [[TMP1704:%.*]] = load float, ptr [[FE]], align 4
15975 // CHECK-NEXT:    [[TMP1705:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1704]] acq_rel, align 4
15976 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15977 // CHECK-NEXT:    [[TMP1706:%.*]] = load float, ptr [[FE]], align 4
15978 // CHECK-NEXT:    [[TMP1707:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1706]] acq_rel, align 4
15979 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15980 // CHECK-NEXT:    [[TMP1708:%.*]] = load float, ptr [[FE]], align 4
15981 // CHECK-NEXT:    [[TMP1709:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1708]] acq_rel, align 4
15982 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15983 // CHECK-NEXT:    [[TMP1710:%.*]] = load float, ptr [[FE]], align 4
15984 // CHECK-NEXT:    [[TMP1711:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1710]] acq_rel, align 4
15985 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
15986 // CHECK-NEXT:    [[TMP1712:%.*]] = load float, ptr [[FE]], align 4
15987 // CHECK-NEXT:    [[TMP1713:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1712]] acquire, align 4
15988 // CHECK-NEXT:    [[TMP1714:%.*]] = load float, ptr [[FE]], align 4
15989 // CHECK-NEXT:    [[TMP1715:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1714]] acquire, align 4
15990 // CHECK-NEXT:    [[TMP1716:%.*]] = load float, ptr [[FE]], align 4
15991 // CHECK-NEXT:    [[TMP1717:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1716]] acquire, align 4
15992 // CHECK-NEXT:    [[TMP1718:%.*]] = load float, ptr [[FE]], align 4
15993 // CHECK-NEXT:    [[TMP1719:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1718]] acquire, align 4
15994 // CHECK-NEXT:    [[TMP1720:%.*]] = load float, ptr [[FE]], align 4
15995 // CHECK-NEXT:    [[TMP1721:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1720]] acquire, align 4
15996 // CHECK-NEXT:    [[TMP1722:%.*]] = load float, ptr [[FE]], align 4
15997 // CHECK-NEXT:    [[TMP1723:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1722]] acquire, align 4
15998 // CHECK-NEXT:    [[TMP1724:%.*]] = load float, ptr [[FE]], align 4
15999 // CHECK-NEXT:    [[TMP1725:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1724]] acquire, align 4
16000 // CHECK-NEXT:    [[TMP1726:%.*]] = load float, ptr [[FE]], align 4
16001 // CHECK-NEXT:    [[TMP1727:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1726]] acquire, align 4
16002 // CHECK-NEXT:    [[TMP1728:%.*]] = load float, ptr [[FE]], align 4
16003 // CHECK-NEXT:    [[TMP1729:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1728]] monotonic, align 4
16004 // CHECK-NEXT:    [[TMP1730:%.*]] = load float, ptr [[FE]], align 4
16005 // CHECK-NEXT:    [[TMP1731:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1730]] monotonic, align 4
16006 // CHECK-NEXT:    [[TMP1732:%.*]] = load float, ptr [[FE]], align 4
16007 // CHECK-NEXT:    [[TMP1733:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1732]] monotonic, align 4
16008 // CHECK-NEXT:    [[TMP1734:%.*]] = load float, ptr [[FE]], align 4
16009 // CHECK-NEXT:    [[TMP1735:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1734]] monotonic, align 4
16010 // CHECK-NEXT:    [[TMP1736:%.*]] = load float, ptr [[FE]], align 4
16011 // CHECK-NEXT:    [[TMP1737:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1736]] monotonic, align 4
16012 // CHECK-NEXT:    [[TMP1738:%.*]] = load float, ptr [[FE]], align 4
16013 // CHECK-NEXT:    [[TMP1739:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1738]] monotonic, align 4
16014 // CHECK-NEXT:    [[TMP1740:%.*]] = load float, ptr [[FE]], align 4
16015 // CHECK-NEXT:    [[TMP1741:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1740]] monotonic, align 4
16016 // CHECK-NEXT:    [[TMP1742:%.*]] = load float, ptr [[FE]], align 4
16017 // CHECK-NEXT:    [[TMP1743:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1742]] monotonic, align 4
16018 // CHECK-NEXT:    [[TMP1744:%.*]] = load float, ptr [[FE]], align 4
16019 // CHECK-NEXT:    [[TMP1745:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1744]] release, align 4
16020 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16021 // CHECK-NEXT:    [[TMP1746:%.*]] = load float, ptr [[FE]], align 4
16022 // CHECK-NEXT:    [[TMP1747:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1746]] release, align 4
16023 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16024 // CHECK-NEXT:    [[TMP1748:%.*]] = load float, ptr [[FE]], align 4
16025 // CHECK-NEXT:    [[TMP1749:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1748]] release, align 4
16026 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16027 // CHECK-NEXT:    [[TMP1750:%.*]] = load float, ptr [[FE]], align 4
16028 // CHECK-NEXT:    [[TMP1751:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1750]] release, align 4
16029 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16030 // CHECK-NEXT:    [[TMP1752:%.*]] = load float, ptr [[FE]], align 4
16031 // CHECK-NEXT:    [[TMP1753:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1752]] release, align 4
16032 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16033 // CHECK-NEXT:    [[TMP1754:%.*]] = load float, ptr [[FE]], align 4
16034 // CHECK-NEXT:    [[TMP1755:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1754]] release, align 4
16035 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16036 // CHECK-NEXT:    [[TMP1756:%.*]] = load float, ptr [[FE]], align 4
16037 // CHECK-NEXT:    [[TMP1757:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1756]] release, align 4
16038 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16039 // CHECK-NEXT:    [[TMP1758:%.*]] = load float, ptr [[FE]], align 4
16040 // CHECK-NEXT:    [[TMP1759:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1758]] release, align 4
16041 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16042 // CHECK-NEXT:    [[TMP1760:%.*]] = load float, ptr [[FE]], align 4
16043 // CHECK-NEXT:    [[TMP1761:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1760]] seq_cst, align 4
16044 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16045 // CHECK-NEXT:    [[TMP1762:%.*]] = load float, ptr [[FE]], align 4
16046 // CHECK-NEXT:    [[TMP1763:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1762]] seq_cst, align 4
16047 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16048 // CHECK-NEXT:    [[TMP1764:%.*]] = load float, ptr [[FE]], align 4
16049 // CHECK-NEXT:    [[TMP1765:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1764]] seq_cst, align 4
16050 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16051 // CHECK-NEXT:    [[TMP1766:%.*]] = load float, ptr [[FE]], align 4
16052 // CHECK-NEXT:    [[TMP1767:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1766]] seq_cst, align 4
16053 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16054 // CHECK-NEXT:    [[TMP1768:%.*]] = load float, ptr [[FE]], align 4
16055 // CHECK-NEXT:    [[TMP1769:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1768]] seq_cst, align 4
16056 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16057 // CHECK-NEXT:    [[TMP1770:%.*]] = load float, ptr [[FE]], align 4
16058 // CHECK-NEXT:    [[TMP1771:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1770]] seq_cst, align 4
16059 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16060 // CHECK-NEXT:    [[TMP1772:%.*]] = load float, ptr [[FE]], align 4
16061 // CHECK-NEXT:    [[TMP1773:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1772]] seq_cst, align 4
16062 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16063 // CHECK-NEXT:    [[TMP1774:%.*]] = load float, ptr [[FE]], align 4
16064 // CHECK-NEXT:    [[TMP1775:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1774]] seq_cst, align 4
16065 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16066 // CHECK-NEXT:    [[TMP1776:%.*]] = load double, ptr [[DE]], align 8
16067 // CHECK-NEXT:    [[TMP1777:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1776]] monotonic, align 8
16068 // CHECK-NEXT:    [[TMP1778:%.*]] = load double, ptr [[DE]], align 8
16069 // CHECK-NEXT:    [[TMP1779:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1778]] monotonic, align 8
16070 // CHECK-NEXT:    [[TMP1780:%.*]] = load double, ptr [[DE]], align 8
16071 // CHECK-NEXT:    [[TMP1781:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1780]] monotonic, align 8
16072 // CHECK-NEXT:    [[TMP1782:%.*]] = load double, ptr [[DE]], align 8
16073 // CHECK-NEXT:    [[TMP1783:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1782]] monotonic, align 8
16074 // CHECK-NEXT:    [[TMP1784:%.*]] = load double, ptr [[DE]], align 8
16075 // CHECK-NEXT:    [[TMP1785:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1784]] monotonic, align 8
16076 // CHECK-NEXT:    [[TMP1786:%.*]] = load double, ptr [[DE]], align 8
16077 // CHECK-NEXT:    [[TMP1787:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1786]] monotonic, align 8
16078 // CHECK-NEXT:    [[TMP1788:%.*]] = load double, ptr [[DE]], align 8
16079 // CHECK-NEXT:    [[TMP1789:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1788]] monotonic, align 8
16080 // CHECK-NEXT:    [[TMP1790:%.*]] = load double, ptr [[DE]], align 8
16081 // CHECK-NEXT:    [[TMP1791:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1790]] monotonic, align 8
16082 // CHECK-NEXT:    [[TMP1792:%.*]] = load double, ptr [[DE]], align 8
16083 // CHECK-NEXT:    [[TMP1793:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1792]] acq_rel, align 8
16084 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16085 // CHECK-NEXT:    [[TMP1794:%.*]] = load double, ptr [[DE]], align 8
16086 // CHECK-NEXT:    [[TMP1795:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1794]] acq_rel, align 8
16087 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16088 // CHECK-NEXT:    [[TMP1796:%.*]] = load double, ptr [[DE]], align 8
16089 // CHECK-NEXT:    [[TMP1797:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1796]] acq_rel, align 8
16090 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16091 // CHECK-NEXT:    [[TMP1798:%.*]] = load double, ptr [[DE]], align 8
16092 // CHECK-NEXT:    [[TMP1799:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1798]] acq_rel, align 8
16093 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16094 // CHECK-NEXT:    [[TMP1800:%.*]] = load double, ptr [[DE]], align 8
16095 // CHECK-NEXT:    [[TMP1801:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1800]] acq_rel, align 8
16096 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16097 // CHECK-NEXT:    [[TMP1802:%.*]] = load double, ptr [[DE]], align 8
16098 // CHECK-NEXT:    [[TMP1803:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1802]] acq_rel, align 8
16099 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16100 // CHECK-NEXT:    [[TMP1804:%.*]] = load double, ptr [[DE]], align 8
16101 // CHECK-NEXT:    [[TMP1805:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1804]] acq_rel, align 8
16102 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16103 // CHECK-NEXT:    [[TMP1806:%.*]] = load double, ptr [[DE]], align 8
16104 // CHECK-NEXT:    [[TMP1807:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1806]] acq_rel, align 8
16105 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16106 // CHECK-NEXT:    [[TMP1808:%.*]] = load double, ptr [[DE]], align 8
16107 // CHECK-NEXT:    [[TMP1809:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1808]] acquire, align 8
16108 // CHECK-NEXT:    [[TMP1810:%.*]] = load double, ptr [[DE]], align 8
16109 // CHECK-NEXT:    [[TMP1811:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1810]] acquire, align 8
16110 // CHECK-NEXT:    [[TMP1812:%.*]] = load double, ptr [[DE]], align 8
16111 // CHECK-NEXT:    [[TMP1813:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1812]] acquire, align 8
16112 // CHECK-NEXT:    [[TMP1814:%.*]] = load double, ptr [[DE]], align 8
16113 // CHECK-NEXT:    [[TMP1815:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1814]] acquire, align 8
16114 // CHECK-NEXT:    [[TMP1816:%.*]] = load double, ptr [[DE]], align 8
16115 // CHECK-NEXT:    [[TMP1817:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1816]] acquire, align 8
16116 // CHECK-NEXT:    [[TMP1818:%.*]] = load double, ptr [[DE]], align 8
16117 // CHECK-NEXT:    [[TMP1819:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1818]] acquire, align 8
16118 // CHECK-NEXT:    [[TMP1820:%.*]] = load double, ptr [[DE]], align 8
16119 // CHECK-NEXT:    [[TMP1821:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1820]] acquire, align 8
16120 // CHECK-NEXT:    [[TMP1822:%.*]] = load double, ptr [[DE]], align 8
16121 // CHECK-NEXT:    [[TMP1823:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1822]] acquire, align 8
16122 // CHECK-NEXT:    [[TMP1824:%.*]] = load double, ptr [[DE]], align 8
16123 // CHECK-NEXT:    [[TMP1825:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1824]] monotonic, align 8
16124 // CHECK-NEXT:    [[TMP1826:%.*]] = load double, ptr [[DE]], align 8
16125 // CHECK-NEXT:    [[TMP1827:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1826]] monotonic, align 8
16126 // CHECK-NEXT:    [[TMP1828:%.*]] = load double, ptr [[DE]], align 8
16127 // CHECK-NEXT:    [[TMP1829:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1828]] monotonic, align 8
16128 // CHECK-NEXT:    [[TMP1830:%.*]] = load double, ptr [[DE]], align 8
16129 // CHECK-NEXT:    [[TMP1831:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1830]] monotonic, align 8
16130 // CHECK-NEXT:    [[TMP1832:%.*]] = load double, ptr [[DE]], align 8
16131 // CHECK-NEXT:    [[TMP1833:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1832]] monotonic, align 8
16132 // CHECK-NEXT:    [[TMP1834:%.*]] = load double, ptr [[DE]], align 8
16133 // CHECK-NEXT:    [[TMP1835:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1834]] monotonic, align 8
16134 // CHECK-NEXT:    [[TMP1836:%.*]] = load double, ptr [[DE]], align 8
16135 // CHECK-NEXT:    [[TMP1837:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1836]] monotonic, align 8
16136 // CHECK-NEXT:    [[TMP1838:%.*]] = load double, ptr [[DE]], align 8
16137 // CHECK-NEXT:    [[TMP1839:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1838]] monotonic, align 8
16138 // CHECK-NEXT:    [[TMP1840:%.*]] = load double, ptr [[DE]], align 8
16139 // CHECK-NEXT:    [[TMP1841:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1840]] release, align 8
16140 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16141 // CHECK-NEXT:    [[TMP1842:%.*]] = load double, ptr [[DE]], align 8
16142 // CHECK-NEXT:    [[TMP1843:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1842]] release, align 8
16143 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16144 // CHECK-NEXT:    [[TMP1844:%.*]] = load double, ptr [[DE]], align 8
16145 // CHECK-NEXT:    [[TMP1845:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1844]] release, align 8
16146 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16147 // CHECK-NEXT:    [[TMP1846:%.*]] = load double, ptr [[DE]], align 8
16148 // CHECK-NEXT:    [[TMP1847:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1846]] release, align 8
16149 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16150 // CHECK-NEXT:    [[TMP1848:%.*]] = load double, ptr [[DE]], align 8
16151 // CHECK-NEXT:    [[TMP1849:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1848]] release, align 8
16152 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16153 // CHECK-NEXT:    [[TMP1850:%.*]] = load double, ptr [[DE]], align 8
16154 // CHECK-NEXT:    [[TMP1851:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1850]] release, align 8
16155 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16156 // CHECK-NEXT:    [[TMP1852:%.*]] = load double, ptr [[DE]], align 8
16157 // CHECK-NEXT:    [[TMP1853:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1852]] release, align 8
16158 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16159 // CHECK-NEXT:    [[TMP1854:%.*]] = load double, ptr [[DE]], align 8
16160 // CHECK-NEXT:    [[TMP1855:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1854]] release, align 8
16161 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16162 // CHECK-NEXT:    [[TMP1856:%.*]] = load double, ptr [[DE]], align 8
16163 // CHECK-NEXT:    [[TMP1857:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1856]] seq_cst, align 8
16164 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16165 // CHECK-NEXT:    [[TMP1858:%.*]] = load double, ptr [[DE]], align 8
16166 // CHECK-NEXT:    [[TMP1859:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1858]] seq_cst, align 8
16167 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16168 // CHECK-NEXT:    [[TMP1860:%.*]] = load double, ptr [[DE]], align 8
16169 // CHECK-NEXT:    [[TMP1861:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1860]] seq_cst, align 8
16170 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16171 // CHECK-NEXT:    [[TMP1862:%.*]] = load double, ptr [[DE]], align 8
16172 // CHECK-NEXT:    [[TMP1863:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1862]] seq_cst, align 8
16173 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16174 // CHECK-NEXT:    [[TMP1864:%.*]] = load double, ptr [[DE]], align 8
16175 // CHECK-NEXT:    [[TMP1865:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1864]] seq_cst, align 8
16176 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16177 // CHECK-NEXT:    [[TMP1866:%.*]] = load double, ptr [[DE]], align 8
16178 // CHECK-NEXT:    [[TMP1867:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1866]] seq_cst, align 8
16179 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16180 // CHECK-NEXT:    [[TMP1868:%.*]] = load double, ptr [[DE]], align 8
16181 // CHECK-NEXT:    [[TMP1869:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1868]] seq_cst, align 8
16182 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16183 // CHECK-NEXT:    [[TMP1870:%.*]] = load double, ptr [[DE]], align 8
16184 // CHECK-NEXT:    [[TMP1871:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1870]] seq_cst, align 8
16185 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16186 // CHECK-NEXT:    ret void
16187 //
16188 //
16189 // CHECK-LABEL: @bar(
16190 // CHECK-NEXT:  entry:
16191 // CHECK-NEXT:    [[CX:%.*]] = alloca i8, align 1
16192 // CHECK-NEXT:    [[CV:%.*]] = alloca i8, align 1
16193 // CHECK-NEXT:    [[CR:%.*]] = alloca i8, align 1
16194 // CHECK-NEXT:    [[CE:%.*]] = alloca i8, align 1
16195 // CHECK-NEXT:    [[CD:%.*]] = alloca i8, align 1
16196 // CHECK-NEXT:    [[UCX:%.*]] = alloca i8, align 1
16197 // CHECK-NEXT:    [[UCV:%.*]] = alloca i8, align 1
16198 // CHECK-NEXT:    [[UCR:%.*]] = alloca i8, align 1
16199 // CHECK-NEXT:    [[UCE:%.*]] = alloca i8, align 1
16200 // CHECK-NEXT:    [[UCD:%.*]] = alloca i8, align 1
16201 // CHECK-NEXT:    [[SX:%.*]] = alloca i16, align 2
16202 // CHECK-NEXT:    [[SV:%.*]] = alloca i16, align 2
16203 // CHECK-NEXT:    [[SR:%.*]] = alloca i16, align 2
16204 // CHECK-NEXT:    [[SE:%.*]] = alloca i16, align 2
16205 // CHECK-NEXT:    [[SD:%.*]] = alloca i16, align 2
16206 // CHECK-NEXT:    [[USX:%.*]] = alloca i16, align 2
16207 // CHECK-NEXT:    [[USV:%.*]] = alloca i16, align 2
16208 // CHECK-NEXT:    [[USR:%.*]] = alloca i16, align 2
16209 // CHECK-NEXT:    [[USE:%.*]] = alloca i16, align 2
16210 // CHECK-NEXT:    [[USD:%.*]] = alloca i16, align 2
16211 // CHECK-NEXT:    [[IX:%.*]] = alloca i32, align 4
16212 // CHECK-NEXT:    [[IV:%.*]] = alloca i32, align 4
16213 // CHECK-NEXT:    [[IR:%.*]] = alloca i32, align 4
16214 // CHECK-NEXT:    [[IE:%.*]] = alloca i32, align 4
16215 // CHECK-NEXT:    [[ID:%.*]] = alloca i32, align 4
16216 // CHECK-NEXT:    [[UIX:%.*]] = alloca i32, align 4
16217 // CHECK-NEXT:    [[UIV:%.*]] = alloca i32, align 4
16218 // CHECK-NEXT:    [[UIR:%.*]] = alloca i32, align 4
16219 // CHECK-NEXT:    [[UIE:%.*]] = alloca i32, align 4
16220 // CHECK-NEXT:    [[UID:%.*]] = alloca i32, align 4
16221 // CHECK-NEXT:    [[LX:%.*]] = alloca i64, align 8
16222 // CHECK-NEXT:    [[LV:%.*]] = alloca i64, align 8
16223 // CHECK-NEXT:    [[LR:%.*]] = alloca i64, align 8
16224 // CHECK-NEXT:    [[LE:%.*]] = alloca i64, align 8
16225 // CHECK-NEXT:    [[LD:%.*]] = alloca i64, align 8
16226 // CHECK-NEXT:    [[ULX:%.*]] = alloca i64, align 8
16227 // CHECK-NEXT:    [[ULV:%.*]] = alloca i64, align 8
16228 // CHECK-NEXT:    [[ULR:%.*]] = alloca i64, align 8
16229 // CHECK-NEXT:    [[ULE:%.*]] = alloca i64, align 8
16230 // CHECK-NEXT:    [[ULD:%.*]] = alloca i64, align 8
16231 // CHECK-NEXT:    [[LLX:%.*]] = alloca i64, align 8
16232 // CHECK-NEXT:    [[LLV:%.*]] = alloca i64, align 8
16233 // CHECK-NEXT:    [[LLR:%.*]] = alloca i64, align 8
16234 // CHECK-NEXT:    [[LLE:%.*]] = alloca i64, align 8
16235 // CHECK-NEXT:    [[LLD:%.*]] = alloca i64, align 8
16236 // CHECK-NEXT:    [[ULLX:%.*]] = alloca i64, align 8
16237 // CHECK-NEXT:    [[ULLV:%.*]] = alloca i64, align 8
16238 // CHECK-NEXT:    [[ULLR:%.*]] = alloca i64, align 8
16239 // CHECK-NEXT:    [[ULLE:%.*]] = alloca i64, align 8
16240 // CHECK-NEXT:    [[ULLD:%.*]] = alloca i64, align 8
16241 // CHECK-NEXT:    [[FX:%.*]] = alloca float, align 4
16242 // CHECK-NEXT:    [[FV:%.*]] = alloca float, align 4
16243 // CHECK-NEXT:    [[FE:%.*]] = alloca float, align 4
16244 // CHECK-NEXT:    [[FD:%.*]] = alloca float, align 4
16245 // CHECK-NEXT:    [[DX:%.*]] = alloca double, align 8
16246 // CHECK-NEXT:    [[DV:%.*]] = alloca double, align 8
16247 // CHECK-NEXT:    [[DE:%.*]] = alloca double, align 8
16248 // CHECK-NEXT:    [[DD:%.*]] = alloca double, align 8
16249 // CHECK-NEXT:    [[TMP0:%.*]] = load i8, ptr [[CE]], align 1
16250 // CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP0]] monotonic, align 1
16251 // CHECK-NEXT:    store i8 [[TMP1]], ptr [[CV]], align 1
16252 // CHECK-NEXT:    [[TMP2:%.*]] = load i8, ptr [[CE]], align 1
16253 // CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP2]] monotonic, align 1
16254 // CHECK-NEXT:    store i8 [[TMP3]], ptr [[CV]], align 1
16255 // CHECK-NEXT:    [[TMP4:%.*]] = load i8, ptr [[CE]], align 1
16256 // CHECK-NEXT:    [[TMP5:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP4]] monotonic, align 1
16257 // CHECK-NEXT:    store i8 [[TMP5]], ptr [[CV]], align 1
16258 // CHECK-NEXT:    [[TMP6:%.*]] = load i8, ptr [[CE]], align 1
16259 // CHECK-NEXT:    [[TMP7:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP6]] monotonic, align 1
16260 // CHECK-NEXT:    store i8 [[TMP7]], ptr [[CV]], align 1
16261 // CHECK-NEXT:    [[TMP8:%.*]] = load i8, ptr [[CE]], align 1
16262 // CHECK-NEXT:    [[TMP9:%.*]] = load i8, ptr [[CD]], align 1
16263 // CHECK-NEXT:    [[TMP10:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP8]], i8 [[TMP9]] monotonic monotonic, align 1
16264 // CHECK-NEXT:    [[TMP11:%.*]] = extractvalue { i8, i1 } [[TMP10]], 0
16265 // CHECK-NEXT:    store i8 [[TMP11]], ptr [[CV]], align 1
16266 // CHECK-NEXT:    [[TMP12:%.*]] = load i8, ptr [[CE]], align 1
16267 // CHECK-NEXT:    [[TMP13:%.*]] = load i8, ptr [[CD]], align 1
16268 // CHECK-NEXT:    [[TMP14:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP12]], i8 [[TMP13]] monotonic monotonic, align 1
16269 // CHECK-NEXT:    [[TMP15:%.*]] = extractvalue { i8, i1 } [[TMP14]], 0
16270 // CHECK-NEXT:    store i8 [[TMP15]], ptr [[CV]], align 1
16271 // CHECK-NEXT:    [[TMP16:%.*]] = load i8, ptr [[CE]], align 1
16272 // CHECK-NEXT:    [[TMP17:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP16]] monotonic, align 1
16273 // CHECK-NEXT:    [[TMP18:%.*]] = icmp sgt i8 [[TMP17]], [[TMP16]]
16274 // CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i8 [[TMP16]], i8 [[TMP17]]
16275 // CHECK-NEXT:    store i8 [[TMP19]], ptr [[CV]], align 1
16276 // CHECK-NEXT:    [[TMP20:%.*]] = load i8, ptr [[CE]], align 1
16277 // CHECK-NEXT:    [[TMP21:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP20]] monotonic, align 1
16278 // CHECK-NEXT:    [[TMP22:%.*]] = icmp slt i8 [[TMP21]], [[TMP20]]
16279 // CHECK-NEXT:    [[TMP23:%.*]] = select i1 [[TMP22]], i8 [[TMP20]], i8 [[TMP21]]
16280 // CHECK-NEXT:    store i8 [[TMP23]], ptr [[CV]], align 1
16281 // CHECK-NEXT:    [[TMP24:%.*]] = load i8, ptr [[CE]], align 1
16282 // CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP24]] monotonic, align 1
16283 // CHECK-NEXT:    [[TMP26:%.*]] = icmp slt i8 [[TMP25]], [[TMP24]]
16284 // CHECK-NEXT:    [[TMP27:%.*]] = select i1 [[TMP26]], i8 [[TMP24]], i8 [[TMP25]]
16285 // CHECK-NEXT:    store i8 [[TMP27]], ptr [[CV]], align 1
16286 // CHECK-NEXT:    [[TMP28:%.*]] = load i8, ptr [[CE]], align 1
16287 // CHECK-NEXT:    [[TMP29:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP28]] monotonic, align 1
16288 // CHECK-NEXT:    [[TMP30:%.*]] = icmp sgt i8 [[TMP29]], [[TMP28]]
16289 // CHECK-NEXT:    [[TMP31:%.*]] = select i1 [[TMP30]], i8 [[TMP28]], i8 [[TMP29]]
16290 // CHECK-NEXT:    store i8 [[TMP31]], ptr [[CV]], align 1
16291 // CHECK-NEXT:    [[TMP32:%.*]] = load i8, ptr [[CE]], align 1
16292 // CHECK-NEXT:    [[TMP33:%.*]] = load i8, ptr [[CD]], align 1
16293 // CHECK-NEXT:    [[TMP34:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP32]], i8 [[TMP33]] monotonic monotonic, align 1
16294 // CHECK-NEXT:    [[TMP35:%.*]] = extractvalue { i8, i1 } [[TMP34]], 0
16295 // CHECK-NEXT:    [[TMP36:%.*]] = extractvalue { i8, i1 } [[TMP34]], 1
16296 // CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i8 [[TMP32]], i8 [[TMP35]]
16297 // CHECK-NEXT:    store i8 [[TMP37]], ptr [[CV]], align 1
16298 // CHECK-NEXT:    [[TMP38:%.*]] = load i8, ptr [[CE]], align 1
16299 // CHECK-NEXT:    [[TMP39:%.*]] = load i8, ptr [[CD]], align 1
16300 // CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP38]], i8 [[TMP39]] monotonic monotonic, align 1
16301 // CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i8, i1 } [[TMP40]], 0
16302 // CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i8, i1 } [[TMP40]], 1
16303 // CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i8 [[TMP38]], i8 [[TMP41]]
16304 // CHECK-NEXT:    store i8 [[TMP43]], ptr [[CV]], align 1
16305 // CHECK-NEXT:    [[TMP44:%.*]] = load i8, ptr [[CE]], align 1
16306 // CHECK-NEXT:    [[TMP45:%.*]] = load i8, ptr [[CD]], align 1
16307 // CHECK-NEXT:    [[TMP46:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP44]], i8 [[TMP45]] monotonic monotonic, align 1
16308 // CHECK-NEXT:    [[TMP47:%.*]] = extractvalue { i8, i1 } [[TMP46]], 0
16309 // CHECK-NEXT:    [[TMP48:%.*]] = extractvalue { i8, i1 } [[TMP46]], 1
16310 // CHECK-NEXT:    br i1 [[TMP48]], label [[CX_ATOMIC_EXIT:%.*]], label [[CX_ATOMIC_CONT:%.*]]
16311 // CHECK:       cx.atomic.cont:
16312 // CHECK-NEXT:    store i8 [[TMP47]], ptr [[CV]], align 1
16313 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT]]
16314 // CHECK:       cx.atomic.exit:
16315 // CHECK-NEXT:    [[TMP49:%.*]] = load i8, ptr [[CE]], align 1
16316 // CHECK-NEXT:    [[TMP50:%.*]] = load i8, ptr [[CD]], align 1
16317 // CHECK-NEXT:    [[TMP51:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP49]], i8 [[TMP50]] monotonic monotonic, align 1
16318 // CHECK-NEXT:    [[TMP52:%.*]] = extractvalue { i8, i1 } [[TMP51]], 0
16319 // CHECK-NEXT:    [[TMP53:%.*]] = extractvalue { i8, i1 } [[TMP51]], 1
16320 // CHECK-NEXT:    br i1 [[TMP53]], label [[CX_ATOMIC_EXIT1:%.*]], label [[CX_ATOMIC_CONT2:%.*]]
16321 // CHECK:       cx.atomic.cont2:
16322 // CHECK-NEXT:    store i8 [[TMP52]], ptr [[CV]], align 1
16323 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT1]]
16324 // CHECK:       cx.atomic.exit1:
16325 // CHECK-NEXT:    [[TMP54:%.*]] = load i8, ptr [[CE]], align 1
16326 // CHECK-NEXT:    [[TMP55:%.*]] = load i8, ptr [[CD]], align 1
16327 // CHECK-NEXT:    [[TMP56:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP54]], i8 [[TMP55]] monotonic monotonic, align 1
16328 // CHECK-NEXT:    [[TMP57:%.*]] = extractvalue { i8, i1 } [[TMP56]], 1
16329 // CHECK-NEXT:    [[TMP58:%.*]] = sext i1 [[TMP57]] to i8
16330 // CHECK-NEXT:    store i8 [[TMP58]], ptr [[CR]], align 1
16331 // CHECK-NEXT:    [[TMP59:%.*]] = load i8, ptr [[CE]], align 1
16332 // CHECK-NEXT:    [[TMP60:%.*]] = load i8, ptr [[CD]], align 1
16333 // CHECK-NEXT:    [[TMP61:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP59]], i8 [[TMP60]] monotonic monotonic, align 1
16334 // CHECK-NEXT:    [[TMP62:%.*]] = extractvalue { i8, i1 } [[TMP61]], 1
16335 // CHECK-NEXT:    [[TMP63:%.*]] = sext i1 [[TMP62]] to i8
16336 // CHECK-NEXT:    store i8 [[TMP63]], ptr [[CR]], align 1
16337 // CHECK-NEXT:    [[TMP64:%.*]] = load i8, ptr [[CE]], align 1
16338 // CHECK-NEXT:    [[TMP65:%.*]] = load i8, ptr [[CD]], align 1
16339 // CHECK-NEXT:    [[TMP66:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP64]], i8 [[TMP65]] monotonic monotonic, align 1
16340 // CHECK-NEXT:    [[TMP67:%.*]] = extractvalue { i8, i1 } [[TMP66]], 0
16341 // CHECK-NEXT:    [[TMP68:%.*]] = extractvalue { i8, i1 } [[TMP66]], 1
16342 // CHECK-NEXT:    br i1 [[TMP68]], label [[CX_ATOMIC_EXIT3:%.*]], label [[CX_ATOMIC_CONT4:%.*]]
16343 // CHECK:       cx.atomic.cont4:
16344 // CHECK-NEXT:    store i8 [[TMP67]], ptr [[CV]], align 1
16345 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT3]]
16346 // CHECK:       cx.atomic.exit3:
16347 // CHECK-NEXT:    [[TMP69:%.*]] = extractvalue { i8, i1 } [[TMP66]], 1
16348 // CHECK-NEXT:    [[TMP70:%.*]] = sext i1 [[TMP69]] to i8
16349 // CHECK-NEXT:    store i8 [[TMP70]], ptr [[CR]], align 1
16350 // CHECK-NEXT:    [[TMP71:%.*]] = load i8, ptr [[CE]], align 1
16351 // CHECK-NEXT:    [[TMP72:%.*]] = load i8, ptr [[CD]], align 1
16352 // CHECK-NEXT:    [[TMP73:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP71]], i8 [[TMP72]] monotonic monotonic, align 1
16353 // CHECK-NEXT:    [[TMP74:%.*]] = extractvalue { i8, i1 } [[TMP73]], 0
16354 // CHECK-NEXT:    [[TMP75:%.*]] = extractvalue { i8, i1 } [[TMP73]], 1
16355 // CHECK-NEXT:    br i1 [[TMP75]], label [[CX_ATOMIC_EXIT5:%.*]], label [[CX_ATOMIC_CONT6:%.*]]
16356 // CHECK:       cx.atomic.cont6:
16357 // CHECK-NEXT:    store i8 [[TMP74]], ptr [[CV]], align 1
16358 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT5]]
16359 // CHECK:       cx.atomic.exit5:
16360 // CHECK-NEXT:    [[TMP76:%.*]] = extractvalue { i8, i1 } [[TMP73]], 1
16361 // CHECK-NEXT:    [[TMP77:%.*]] = sext i1 [[TMP76]] to i8
16362 // CHECK-NEXT:    store i8 [[TMP77]], ptr [[CR]], align 1
16363 // CHECK-NEXT:    [[TMP78:%.*]] = load i8, ptr [[CE]], align 1
16364 // CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP78]] acq_rel, align 1
16365 // CHECK-NEXT:    store i8 [[TMP79]], ptr [[CV]], align 1
16366 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16367 // CHECK-NEXT:    [[TMP80:%.*]] = load i8, ptr [[CE]], align 1
16368 // CHECK-NEXT:    [[TMP81:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP80]] acq_rel, align 1
16369 // CHECK-NEXT:    store i8 [[TMP81]], ptr [[CV]], align 1
16370 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16371 // CHECK-NEXT:    [[TMP82:%.*]] = load i8, ptr [[CE]], align 1
16372 // CHECK-NEXT:    [[TMP83:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP82]] acq_rel, align 1
16373 // CHECK-NEXT:    store i8 [[TMP83]], ptr [[CV]], align 1
16374 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16375 // CHECK-NEXT:    [[TMP84:%.*]] = load i8, ptr [[CE]], align 1
16376 // CHECK-NEXT:    [[TMP85:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP84]] acq_rel, align 1
16377 // CHECK-NEXT:    store i8 [[TMP85]], ptr [[CV]], align 1
16378 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16379 // CHECK-NEXT:    [[TMP86:%.*]] = load i8, ptr [[CE]], align 1
16380 // CHECK-NEXT:    [[TMP87:%.*]] = load i8, ptr [[CD]], align 1
16381 // CHECK-NEXT:    [[TMP88:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP86]], i8 [[TMP87]] acq_rel acquire, align 1
16382 // CHECK-NEXT:    [[TMP89:%.*]] = extractvalue { i8, i1 } [[TMP88]], 0
16383 // CHECK-NEXT:    store i8 [[TMP89]], ptr [[CV]], align 1
16384 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16385 // CHECK-NEXT:    [[TMP90:%.*]] = load i8, ptr [[CE]], align 1
16386 // CHECK-NEXT:    [[TMP91:%.*]] = load i8, ptr [[CD]], align 1
16387 // CHECK-NEXT:    [[TMP92:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP90]], i8 [[TMP91]] acq_rel acquire, align 1
16388 // CHECK-NEXT:    [[TMP93:%.*]] = extractvalue { i8, i1 } [[TMP92]], 0
16389 // CHECK-NEXT:    store i8 [[TMP93]], ptr [[CV]], align 1
16390 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16391 // CHECK-NEXT:    [[TMP94:%.*]] = load i8, ptr [[CE]], align 1
16392 // CHECK-NEXT:    [[TMP95:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP94]] acq_rel, align 1
16393 // CHECK-NEXT:    [[TMP96:%.*]] = icmp sgt i8 [[TMP95]], [[TMP94]]
16394 // CHECK-NEXT:    [[TMP97:%.*]] = select i1 [[TMP96]], i8 [[TMP94]], i8 [[TMP95]]
16395 // CHECK-NEXT:    store i8 [[TMP97]], ptr [[CV]], align 1
16396 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16397 // CHECK-NEXT:    [[TMP98:%.*]] = load i8, ptr [[CE]], align 1
16398 // CHECK-NEXT:    [[TMP99:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP98]] acq_rel, align 1
16399 // CHECK-NEXT:    [[TMP100:%.*]] = icmp slt i8 [[TMP99]], [[TMP98]]
16400 // CHECK-NEXT:    [[TMP101:%.*]] = select i1 [[TMP100]], i8 [[TMP98]], i8 [[TMP99]]
16401 // CHECK-NEXT:    store i8 [[TMP101]], ptr [[CV]], align 1
16402 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16403 // CHECK-NEXT:    [[TMP102:%.*]] = load i8, ptr [[CE]], align 1
16404 // CHECK-NEXT:    [[TMP103:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP102]] acq_rel, align 1
16405 // CHECK-NEXT:    [[TMP104:%.*]] = icmp slt i8 [[TMP103]], [[TMP102]]
16406 // CHECK-NEXT:    [[TMP105:%.*]] = select i1 [[TMP104]], i8 [[TMP102]], i8 [[TMP103]]
16407 // CHECK-NEXT:    store i8 [[TMP105]], ptr [[CV]], align 1
16408 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16409 // CHECK-NEXT:    [[TMP106:%.*]] = load i8, ptr [[CE]], align 1
16410 // CHECK-NEXT:    [[TMP107:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP106]] acq_rel, align 1
16411 // CHECK-NEXT:    [[TMP108:%.*]] = icmp sgt i8 [[TMP107]], [[TMP106]]
16412 // CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i8 [[TMP106]], i8 [[TMP107]]
16413 // CHECK-NEXT:    store i8 [[TMP109]], ptr [[CV]], align 1
16414 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16415 // CHECK-NEXT:    [[TMP110:%.*]] = load i8, ptr [[CE]], align 1
16416 // CHECK-NEXT:    [[TMP111:%.*]] = load i8, ptr [[CD]], align 1
16417 // CHECK-NEXT:    [[TMP112:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP110]], i8 [[TMP111]] acq_rel acquire, align 1
16418 // CHECK-NEXT:    [[TMP113:%.*]] = extractvalue { i8, i1 } [[TMP112]], 0
16419 // CHECK-NEXT:    [[TMP114:%.*]] = extractvalue { i8, i1 } [[TMP112]], 1
16420 // CHECK-NEXT:    [[TMP115:%.*]] = select i1 [[TMP114]], i8 [[TMP110]], i8 [[TMP113]]
16421 // CHECK-NEXT:    store i8 [[TMP115]], ptr [[CV]], align 1
16422 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16423 // CHECK-NEXT:    [[TMP116:%.*]] = load i8, ptr [[CE]], align 1
16424 // CHECK-NEXT:    [[TMP117:%.*]] = load i8, ptr [[CD]], align 1
16425 // CHECK-NEXT:    [[TMP118:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP116]], i8 [[TMP117]] acq_rel acquire, align 1
16426 // CHECK-NEXT:    [[TMP119:%.*]] = extractvalue { i8, i1 } [[TMP118]], 0
16427 // CHECK-NEXT:    [[TMP120:%.*]] = extractvalue { i8, i1 } [[TMP118]], 1
16428 // CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i8 [[TMP116]], i8 [[TMP119]]
16429 // CHECK-NEXT:    store i8 [[TMP121]], ptr [[CV]], align 1
16430 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16431 // CHECK-NEXT:    [[TMP122:%.*]] = load i8, ptr [[CE]], align 1
16432 // CHECK-NEXT:    [[TMP123:%.*]] = load i8, ptr [[CD]], align 1
16433 // CHECK-NEXT:    [[TMP124:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP122]], i8 [[TMP123]] acq_rel acquire, align 1
16434 // CHECK-NEXT:    [[TMP125:%.*]] = extractvalue { i8, i1 } [[TMP124]], 0
16435 // CHECK-NEXT:    [[TMP126:%.*]] = extractvalue { i8, i1 } [[TMP124]], 1
16436 // CHECK-NEXT:    br i1 [[TMP126]], label [[CX_ATOMIC_EXIT7:%.*]], label [[CX_ATOMIC_CONT8:%.*]]
16437 // CHECK:       cx.atomic.cont8:
16438 // CHECK-NEXT:    store i8 [[TMP125]], ptr [[CV]], align 1
16439 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT7]]
16440 // CHECK:       cx.atomic.exit7:
16441 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16442 // CHECK-NEXT:    [[TMP127:%.*]] = load i8, ptr [[CE]], align 1
16443 // CHECK-NEXT:    [[TMP128:%.*]] = load i8, ptr [[CD]], align 1
16444 // CHECK-NEXT:    [[TMP129:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP127]], i8 [[TMP128]] acq_rel acquire, align 1
16445 // CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i8, i1 } [[TMP129]], 0
16446 // CHECK-NEXT:    [[TMP131:%.*]] = extractvalue { i8, i1 } [[TMP129]], 1
16447 // CHECK-NEXT:    br i1 [[TMP131]], label [[CX_ATOMIC_EXIT9:%.*]], label [[CX_ATOMIC_CONT10:%.*]]
16448 // CHECK:       cx.atomic.cont10:
16449 // CHECK-NEXT:    store i8 [[TMP130]], ptr [[CV]], align 1
16450 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT9]]
16451 // CHECK:       cx.atomic.exit9:
16452 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16453 // CHECK-NEXT:    [[TMP132:%.*]] = load i8, ptr [[CE]], align 1
16454 // CHECK-NEXT:    [[TMP133:%.*]] = load i8, ptr [[CD]], align 1
16455 // CHECK-NEXT:    [[TMP134:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP132]], i8 [[TMP133]] acq_rel acquire, align 1
16456 // CHECK-NEXT:    [[TMP135:%.*]] = extractvalue { i8, i1 } [[TMP134]], 1
16457 // CHECK-NEXT:    [[TMP136:%.*]] = sext i1 [[TMP135]] to i8
16458 // CHECK-NEXT:    store i8 [[TMP136]], ptr [[CR]], align 1
16459 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16460 // CHECK-NEXT:    [[TMP137:%.*]] = load i8, ptr [[CE]], align 1
16461 // CHECK-NEXT:    [[TMP138:%.*]] = load i8, ptr [[CD]], align 1
16462 // CHECK-NEXT:    [[TMP139:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP137]], i8 [[TMP138]] acq_rel acquire, align 1
16463 // CHECK-NEXT:    [[TMP140:%.*]] = extractvalue { i8, i1 } [[TMP139]], 1
16464 // CHECK-NEXT:    [[TMP141:%.*]] = sext i1 [[TMP140]] to i8
16465 // CHECK-NEXT:    store i8 [[TMP141]], ptr [[CR]], align 1
16466 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16467 // CHECK-NEXT:    [[TMP142:%.*]] = load i8, ptr [[CE]], align 1
16468 // CHECK-NEXT:    [[TMP143:%.*]] = load i8, ptr [[CD]], align 1
16469 // CHECK-NEXT:    [[TMP144:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP142]], i8 [[TMP143]] acq_rel acquire, align 1
16470 // CHECK-NEXT:    [[TMP145:%.*]] = extractvalue { i8, i1 } [[TMP144]], 0
16471 // CHECK-NEXT:    [[TMP146:%.*]] = extractvalue { i8, i1 } [[TMP144]], 1
16472 // CHECK-NEXT:    br i1 [[TMP146]], label [[CX_ATOMIC_EXIT11:%.*]], label [[CX_ATOMIC_CONT12:%.*]]
16473 // CHECK:       cx.atomic.cont12:
16474 // CHECK-NEXT:    store i8 [[TMP145]], ptr [[CV]], align 1
16475 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT11]]
16476 // CHECK:       cx.atomic.exit11:
16477 // CHECK-NEXT:    [[TMP147:%.*]] = extractvalue { i8, i1 } [[TMP144]], 1
16478 // CHECK-NEXT:    [[TMP148:%.*]] = sext i1 [[TMP147]] to i8
16479 // CHECK-NEXT:    store i8 [[TMP148]], ptr [[CR]], align 1
16480 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16481 // CHECK-NEXT:    [[TMP149:%.*]] = load i8, ptr [[CE]], align 1
16482 // CHECK-NEXT:    [[TMP150:%.*]] = load i8, ptr [[CD]], align 1
16483 // CHECK-NEXT:    [[TMP151:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP149]], i8 [[TMP150]] acq_rel acquire, align 1
16484 // CHECK-NEXT:    [[TMP152:%.*]] = extractvalue { i8, i1 } [[TMP151]], 0
16485 // CHECK-NEXT:    [[TMP153:%.*]] = extractvalue { i8, i1 } [[TMP151]], 1
16486 // CHECK-NEXT:    br i1 [[TMP153]], label [[CX_ATOMIC_EXIT13:%.*]], label [[CX_ATOMIC_CONT14:%.*]]
16487 // CHECK:       cx.atomic.cont14:
16488 // CHECK-NEXT:    store i8 [[TMP152]], ptr [[CV]], align 1
16489 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT13]]
16490 // CHECK:       cx.atomic.exit13:
16491 // CHECK-NEXT:    [[TMP154:%.*]] = extractvalue { i8, i1 } [[TMP151]], 1
16492 // CHECK-NEXT:    [[TMP155:%.*]] = sext i1 [[TMP154]] to i8
16493 // CHECK-NEXT:    store i8 [[TMP155]], ptr [[CR]], align 1
16494 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16495 // CHECK-NEXT:    [[TMP156:%.*]] = load i8, ptr [[CE]], align 1
16496 // CHECK-NEXT:    [[TMP157:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP156]] acquire, align 1
16497 // CHECK-NEXT:    store i8 [[TMP157]], ptr [[CV]], align 1
16498 // CHECK-NEXT:    [[TMP158:%.*]] = load i8, ptr [[CE]], align 1
16499 // CHECK-NEXT:    [[TMP159:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP158]] acquire, align 1
16500 // CHECK-NEXT:    store i8 [[TMP159]], ptr [[CV]], align 1
16501 // CHECK-NEXT:    [[TMP160:%.*]] = load i8, ptr [[CE]], align 1
16502 // CHECK-NEXT:    [[TMP161:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP160]] acquire, align 1
16503 // CHECK-NEXT:    store i8 [[TMP161]], ptr [[CV]], align 1
16504 // CHECK-NEXT:    [[TMP162:%.*]] = load i8, ptr [[CE]], align 1
16505 // CHECK-NEXT:    [[TMP163:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP162]] acquire, align 1
16506 // CHECK-NEXT:    store i8 [[TMP163]], ptr [[CV]], align 1
16507 // CHECK-NEXT:    [[TMP164:%.*]] = load i8, ptr [[CE]], align 1
16508 // CHECK-NEXT:    [[TMP165:%.*]] = load i8, ptr [[CD]], align 1
16509 // CHECK-NEXT:    [[TMP166:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP164]], i8 [[TMP165]] acquire acquire, align 1
16510 // CHECK-NEXT:    [[TMP167:%.*]] = extractvalue { i8, i1 } [[TMP166]], 0
16511 // CHECK-NEXT:    store i8 [[TMP167]], ptr [[CV]], align 1
16512 // CHECK-NEXT:    [[TMP168:%.*]] = load i8, ptr [[CE]], align 1
16513 // CHECK-NEXT:    [[TMP169:%.*]] = load i8, ptr [[CD]], align 1
16514 // CHECK-NEXT:    [[TMP170:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP168]], i8 [[TMP169]] acquire acquire, align 1
16515 // CHECK-NEXT:    [[TMP171:%.*]] = extractvalue { i8, i1 } [[TMP170]], 0
16516 // CHECK-NEXT:    store i8 [[TMP171]], ptr [[CV]], align 1
16517 // CHECK-NEXT:    [[TMP172:%.*]] = load i8, ptr [[CE]], align 1
16518 // CHECK-NEXT:    [[TMP173:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP172]] acquire, align 1
16519 // CHECK-NEXT:    [[TMP174:%.*]] = icmp sgt i8 [[TMP173]], [[TMP172]]
16520 // CHECK-NEXT:    [[TMP175:%.*]] = select i1 [[TMP174]], i8 [[TMP172]], i8 [[TMP173]]
16521 // CHECK-NEXT:    store i8 [[TMP175]], ptr [[CV]], align 1
16522 // CHECK-NEXT:    [[TMP176:%.*]] = load i8, ptr [[CE]], align 1
16523 // CHECK-NEXT:    [[TMP177:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP176]] acquire, align 1
16524 // CHECK-NEXT:    [[TMP178:%.*]] = icmp slt i8 [[TMP177]], [[TMP176]]
16525 // CHECK-NEXT:    [[TMP179:%.*]] = select i1 [[TMP178]], i8 [[TMP176]], i8 [[TMP177]]
16526 // CHECK-NEXT:    store i8 [[TMP179]], ptr [[CV]], align 1
16527 // CHECK-NEXT:    [[TMP180:%.*]] = load i8, ptr [[CE]], align 1
16528 // CHECK-NEXT:    [[TMP181:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP180]] acquire, align 1
16529 // CHECK-NEXT:    [[TMP182:%.*]] = icmp slt i8 [[TMP181]], [[TMP180]]
16530 // CHECK-NEXT:    [[TMP183:%.*]] = select i1 [[TMP182]], i8 [[TMP180]], i8 [[TMP181]]
16531 // CHECK-NEXT:    store i8 [[TMP183]], ptr [[CV]], align 1
16532 // CHECK-NEXT:    [[TMP184:%.*]] = load i8, ptr [[CE]], align 1
16533 // CHECK-NEXT:    [[TMP185:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP184]] acquire, align 1
16534 // CHECK-NEXT:    [[TMP186:%.*]] = icmp sgt i8 [[TMP185]], [[TMP184]]
16535 // CHECK-NEXT:    [[TMP187:%.*]] = select i1 [[TMP186]], i8 [[TMP184]], i8 [[TMP185]]
16536 // CHECK-NEXT:    store i8 [[TMP187]], ptr [[CV]], align 1
16537 // CHECK-NEXT:    [[TMP188:%.*]] = load i8, ptr [[CE]], align 1
16538 // CHECK-NEXT:    [[TMP189:%.*]] = load i8, ptr [[CD]], align 1
16539 // CHECK-NEXT:    [[TMP190:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP188]], i8 [[TMP189]] acquire acquire, align 1
16540 // CHECK-NEXT:    [[TMP191:%.*]] = extractvalue { i8, i1 } [[TMP190]], 0
16541 // CHECK-NEXT:    [[TMP192:%.*]] = extractvalue { i8, i1 } [[TMP190]], 1
16542 // CHECK-NEXT:    [[TMP193:%.*]] = select i1 [[TMP192]], i8 [[TMP188]], i8 [[TMP191]]
16543 // CHECK-NEXT:    store i8 [[TMP193]], ptr [[CV]], align 1
16544 // CHECK-NEXT:    [[TMP194:%.*]] = load i8, ptr [[CE]], align 1
16545 // CHECK-NEXT:    [[TMP195:%.*]] = load i8, ptr [[CD]], align 1
16546 // CHECK-NEXT:    [[TMP196:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP194]], i8 [[TMP195]] acquire acquire, align 1
16547 // CHECK-NEXT:    [[TMP197:%.*]] = extractvalue { i8, i1 } [[TMP196]], 0
16548 // CHECK-NEXT:    [[TMP198:%.*]] = extractvalue { i8, i1 } [[TMP196]], 1
16549 // CHECK-NEXT:    [[TMP199:%.*]] = select i1 [[TMP198]], i8 [[TMP194]], i8 [[TMP197]]
16550 // CHECK-NEXT:    store i8 [[TMP199]], ptr [[CV]], align 1
16551 // CHECK-NEXT:    [[TMP200:%.*]] = load i8, ptr [[CE]], align 1
16552 // CHECK-NEXT:    [[TMP201:%.*]] = load i8, ptr [[CD]], align 1
16553 // CHECK-NEXT:    [[TMP202:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP200]], i8 [[TMP201]] acquire acquire, align 1
16554 // CHECK-NEXT:    [[TMP203:%.*]] = extractvalue { i8, i1 } [[TMP202]], 0
16555 // CHECK-NEXT:    [[TMP204:%.*]] = extractvalue { i8, i1 } [[TMP202]], 1
16556 // CHECK-NEXT:    br i1 [[TMP204]], label [[CX_ATOMIC_EXIT15:%.*]], label [[CX_ATOMIC_CONT16:%.*]]
16557 // CHECK:       cx.atomic.cont16:
16558 // CHECK-NEXT:    store i8 [[TMP203]], ptr [[CV]], align 1
16559 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT15]]
16560 // CHECK:       cx.atomic.exit15:
16561 // CHECK-NEXT:    [[TMP205:%.*]] = load i8, ptr [[CE]], align 1
16562 // CHECK-NEXT:    [[TMP206:%.*]] = load i8, ptr [[CD]], align 1
16563 // CHECK-NEXT:    [[TMP207:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP205]], i8 [[TMP206]] acquire acquire, align 1
16564 // CHECK-NEXT:    [[TMP208:%.*]] = extractvalue { i8, i1 } [[TMP207]], 0
16565 // CHECK-NEXT:    [[TMP209:%.*]] = extractvalue { i8, i1 } [[TMP207]], 1
16566 // CHECK-NEXT:    br i1 [[TMP209]], label [[CX_ATOMIC_EXIT17:%.*]], label [[CX_ATOMIC_CONT18:%.*]]
16567 // CHECK:       cx.atomic.cont18:
16568 // CHECK-NEXT:    store i8 [[TMP208]], ptr [[CV]], align 1
16569 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT17]]
16570 // CHECK:       cx.atomic.exit17:
16571 // CHECK-NEXT:    [[TMP210:%.*]] = load i8, ptr [[CE]], align 1
16572 // CHECK-NEXT:    [[TMP211:%.*]] = load i8, ptr [[CD]], align 1
16573 // CHECK-NEXT:    [[TMP212:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP210]], i8 [[TMP211]] acquire acquire, align 1
16574 // CHECK-NEXT:    [[TMP213:%.*]] = extractvalue { i8, i1 } [[TMP212]], 1
16575 // CHECK-NEXT:    [[TMP214:%.*]] = sext i1 [[TMP213]] to i8
16576 // CHECK-NEXT:    store i8 [[TMP214]], ptr [[CR]], align 1
16577 // CHECK-NEXT:    [[TMP215:%.*]] = load i8, ptr [[CE]], align 1
16578 // CHECK-NEXT:    [[TMP216:%.*]] = load i8, ptr [[CD]], align 1
16579 // CHECK-NEXT:    [[TMP217:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP215]], i8 [[TMP216]] acquire acquire, align 1
16580 // CHECK-NEXT:    [[TMP218:%.*]] = extractvalue { i8, i1 } [[TMP217]], 1
16581 // CHECK-NEXT:    [[TMP219:%.*]] = sext i1 [[TMP218]] to i8
16582 // CHECK-NEXT:    store i8 [[TMP219]], ptr [[CR]], align 1
16583 // CHECK-NEXT:    [[TMP220:%.*]] = load i8, ptr [[CE]], align 1
16584 // CHECK-NEXT:    [[TMP221:%.*]] = load i8, ptr [[CD]], align 1
16585 // CHECK-NEXT:    [[TMP222:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP220]], i8 [[TMP221]] acquire acquire, align 1
16586 // CHECK-NEXT:    [[TMP223:%.*]] = extractvalue { i8, i1 } [[TMP222]], 0
16587 // CHECK-NEXT:    [[TMP224:%.*]] = extractvalue { i8, i1 } [[TMP222]], 1
16588 // CHECK-NEXT:    br i1 [[TMP224]], label [[CX_ATOMIC_EXIT19:%.*]], label [[CX_ATOMIC_CONT20:%.*]]
16589 // CHECK:       cx.atomic.cont20:
16590 // CHECK-NEXT:    store i8 [[TMP223]], ptr [[CV]], align 1
16591 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT19]]
16592 // CHECK:       cx.atomic.exit19:
16593 // CHECK-NEXT:    [[TMP225:%.*]] = extractvalue { i8, i1 } [[TMP222]], 1
16594 // CHECK-NEXT:    [[TMP226:%.*]] = sext i1 [[TMP225]] to i8
16595 // CHECK-NEXT:    store i8 [[TMP226]], ptr [[CR]], align 1
16596 // CHECK-NEXT:    [[TMP227:%.*]] = load i8, ptr [[CE]], align 1
16597 // CHECK-NEXT:    [[TMP228:%.*]] = load i8, ptr [[CD]], align 1
16598 // CHECK-NEXT:    [[TMP229:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP227]], i8 [[TMP228]] acquire acquire, align 1
16599 // CHECK-NEXT:    [[TMP230:%.*]] = extractvalue { i8, i1 } [[TMP229]], 0
16600 // CHECK-NEXT:    [[TMP231:%.*]] = extractvalue { i8, i1 } [[TMP229]], 1
16601 // CHECK-NEXT:    br i1 [[TMP231]], label [[CX_ATOMIC_EXIT21:%.*]], label [[CX_ATOMIC_CONT22:%.*]]
16602 // CHECK:       cx.atomic.cont22:
16603 // CHECK-NEXT:    store i8 [[TMP230]], ptr [[CV]], align 1
16604 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT21]]
16605 // CHECK:       cx.atomic.exit21:
16606 // CHECK-NEXT:    [[TMP232:%.*]] = extractvalue { i8, i1 } [[TMP229]], 1
16607 // CHECK-NEXT:    [[TMP233:%.*]] = sext i1 [[TMP232]] to i8
16608 // CHECK-NEXT:    store i8 [[TMP233]], ptr [[CR]], align 1
16609 // CHECK-NEXT:    [[TMP234:%.*]] = load i8, ptr [[CE]], align 1
16610 // CHECK-NEXT:    [[TMP235:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP234]] monotonic, align 1
16611 // CHECK-NEXT:    store i8 [[TMP235]], ptr [[CV]], align 1
16612 // CHECK-NEXT:    [[TMP236:%.*]] = load i8, ptr [[CE]], align 1
16613 // CHECK-NEXT:    [[TMP237:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP236]] monotonic, align 1
16614 // CHECK-NEXT:    store i8 [[TMP237]], ptr [[CV]], align 1
16615 // CHECK-NEXT:    [[TMP238:%.*]] = load i8, ptr [[CE]], align 1
16616 // CHECK-NEXT:    [[TMP239:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP238]] monotonic, align 1
16617 // CHECK-NEXT:    store i8 [[TMP239]], ptr [[CV]], align 1
16618 // CHECK-NEXT:    [[TMP240:%.*]] = load i8, ptr [[CE]], align 1
16619 // CHECK-NEXT:    [[TMP241:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP240]] monotonic, align 1
16620 // CHECK-NEXT:    store i8 [[TMP241]], ptr [[CV]], align 1
16621 // CHECK-NEXT:    [[TMP242:%.*]] = load i8, ptr [[CE]], align 1
16622 // CHECK-NEXT:    [[TMP243:%.*]] = load i8, ptr [[CD]], align 1
16623 // CHECK-NEXT:    [[TMP244:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP242]], i8 [[TMP243]] monotonic monotonic, align 1
16624 // CHECK-NEXT:    [[TMP245:%.*]] = extractvalue { i8, i1 } [[TMP244]], 0
16625 // CHECK-NEXT:    store i8 [[TMP245]], ptr [[CV]], align 1
16626 // CHECK-NEXT:    [[TMP246:%.*]] = load i8, ptr [[CE]], align 1
16627 // CHECK-NEXT:    [[TMP247:%.*]] = load i8, ptr [[CD]], align 1
16628 // CHECK-NEXT:    [[TMP248:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP246]], i8 [[TMP247]] monotonic monotonic, align 1
16629 // CHECK-NEXT:    [[TMP249:%.*]] = extractvalue { i8, i1 } [[TMP248]], 0
16630 // CHECK-NEXT:    store i8 [[TMP249]], ptr [[CV]], align 1
16631 // CHECK-NEXT:    [[TMP250:%.*]] = load i8, ptr [[CE]], align 1
16632 // CHECK-NEXT:    [[TMP251:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP250]] monotonic, align 1
16633 // CHECK-NEXT:    [[TMP252:%.*]] = icmp sgt i8 [[TMP251]], [[TMP250]]
16634 // CHECK-NEXT:    [[TMP253:%.*]] = select i1 [[TMP252]], i8 [[TMP250]], i8 [[TMP251]]
16635 // CHECK-NEXT:    store i8 [[TMP253]], ptr [[CV]], align 1
16636 // CHECK-NEXT:    [[TMP254:%.*]] = load i8, ptr [[CE]], align 1
16637 // CHECK-NEXT:    [[TMP255:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP254]] monotonic, align 1
16638 // CHECK-NEXT:    [[TMP256:%.*]] = icmp slt i8 [[TMP255]], [[TMP254]]
16639 // CHECK-NEXT:    [[TMP257:%.*]] = select i1 [[TMP256]], i8 [[TMP254]], i8 [[TMP255]]
16640 // CHECK-NEXT:    store i8 [[TMP257]], ptr [[CV]], align 1
16641 // CHECK-NEXT:    [[TMP258:%.*]] = load i8, ptr [[CE]], align 1
16642 // CHECK-NEXT:    [[TMP259:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP258]] monotonic, align 1
16643 // CHECK-NEXT:    [[TMP260:%.*]] = icmp slt i8 [[TMP259]], [[TMP258]]
16644 // CHECK-NEXT:    [[TMP261:%.*]] = select i1 [[TMP260]], i8 [[TMP258]], i8 [[TMP259]]
16645 // CHECK-NEXT:    store i8 [[TMP261]], ptr [[CV]], align 1
16646 // CHECK-NEXT:    [[TMP262:%.*]] = load i8, ptr [[CE]], align 1
16647 // CHECK-NEXT:    [[TMP263:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP262]] monotonic, align 1
16648 // CHECK-NEXT:    [[TMP264:%.*]] = icmp sgt i8 [[TMP263]], [[TMP262]]
16649 // CHECK-NEXT:    [[TMP265:%.*]] = select i1 [[TMP264]], i8 [[TMP262]], i8 [[TMP263]]
16650 // CHECK-NEXT:    store i8 [[TMP265]], ptr [[CV]], align 1
16651 // CHECK-NEXT:    [[TMP266:%.*]] = load i8, ptr [[CE]], align 1
16652 // CHECK-NEXT:    [[TMP267:%.*]] = load i8, ptr [[CD]], align 1
16653 // CHECK-NEXT:    [[TMP268:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP266]], i8 [[TMP267]] monotonic monotonic, align 1
16654 // CHECK-NEXT:    [[TMP269:%.*]] = extractvalue { i8, i1 } [[TMP268]], 0
16655 // CHECK-NEXT:    [[TMP270:%.*]] = extractvalue { i8, i1 } [[TMP268]], 1
16656 // CHECK-NEXT:    [[TMP271:%.*]] = select i1 [[TMP270]], i8 [[TMP266]], i8 [[TMP269]]
16657 // CHECK-NEXT:    store i8 [[TMP271]], ptr [[CV]], align 1
16658 // CHECK-NEXT:    [[TMP272:%.*]] = load i8, ptr [[CE]], align 1
16659 // CHECK-NEXT:    [[TMP273:%.*]] = load i8, ptr [[CD]], align 1
16660 // CHECK-NEXT:    [[TMP274:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP272]], i8 [[TMP273]] monotonic monotonic, align 1
16661 // CHECK-NEXT:    [[TMP275:%.*]] = extractvalue { i8, i1 } [[TMP274]], 0
16662 // CHECK-NEXT:    [[TMP276:%.*]] = extractvalue { i8, i1 } [[TMP274]], 1
16663 // CHECK-NEXT:    [[TMP277:%.*]] = select i1 [[TMP276]], i8 [[TMP272]], i8 [[TMP275]]
16664 // CHECK-NEXT:    store i8 [[TMP277]], ptr [[CV]], align 1
16665 // CHECK-NEXT:    [[TMP278:%.*]] = load i8, ptr [[CE]], align 1
16666 // CHECK-NEXT:    [[TMP279:%.*]] = load i8, ptr [[CD]], align 1
16667 // CHECK-NEXT:    [[TMP280:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP278]], i8 [[TMP279]] monotonic monotonic, align 1
16668 // CHECK-NEXT:    [[TMP281:%.*]] = extractvalue { i8, i1 } [[TMP280]], 0
16669 // CHECK-NEXT:    [[TMP282:%.*]] = extractvalue { i8, i1 } [[TMP280]], 1
16670 // CHECK-NEXT:    br i1 [[TMP282]], label [[CX_ATOMIC_EXIT23:%.*]], label [[CX_ATOMIC_CONT24:%.*]]
16671 // CHECK:       cx.atomic.cont24:
16672 // CHECK-NEXT:    store i8 [[TMP281]], ptr [[CV]], align 1
16673 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT23]]
16674 // CHECK:       cx.atomic.exit23:
16675 // CHECK-NEXT:    [[TMP283:%.*]] = load i8, ptr [[CE]], align 1
16676 // CHECK-NEXT:    [[TMP284:%.*]] = load i8, ptr [[CD]], align 1
16677 // CHECK-NEXT:    [[TMP285:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP283]], i8 [[TMP284]] monotonic monotonic, align 1
16678 // CHECK-NEXT:    [[TMP286:%.*]] = extractvalue { i8, i1 } [[TMP285]], 0
16679 // CHECK-NEXT:    [[TMP287:%.*]] = extractvalue { i8, i1 } [[TMP285]], 1
16680 // CHECK-NEXT:    br i1 [[TMP287]], label [[CX_ATOMIC_EXIT25:%.*]], label [[CX_ATOMIC_CONT26:%.*]]
16681 // CHECK:       cx.atomic.cont26:
16682 // CHECK-NEXT:    store i8 [[TMP286]], ptr [[CV]], align 1
16683 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT25]]
16684 // CHECK:       cx.atomic.exit25:
16685 // CHECK-NEXT:    [[TMP288:%.*]] = load i8, ptr [[CE]], align 1
16686 // CHECK-NEXT:    [[TMP289:%.*]] = load i8, ptr [[CD]], align 1
16687 // CHECK-NEXT:    [[TMP290:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP288]], i8 [[TMP289]] monotonic monotonic, align 1
16688 // CHECK-NEXT:    [[TMP291:%.*]] = extractvalue { i8, i1 } [[TMP290]], 1
16689 // CHECK-NEXT:    [[TMP292:%.*]] = sext i1 [[TMP291]] to i8
16690 // CHECK-NEXT:    store i8 [[TMP292]], ptr [[CR]], align 1
16691 // CHECK-NEXT:    [[TMP293:%.*]] = load i8, ptr [[CE]], align 1
16692 // CHECK-NEXT:    [[TMP294:%.*]] = load i8, ptr [[CD]], align 1
16693 // CHECK-NEXT:    [[TMP295:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP293]], i8 [[TMP294]] monotonic monotonic, align 1
16694 // CHECK-NEXT:    [[TMP296:%.*]] = extractvalue { i8, i1 } [[TMP295]], 1
16695 // CHECK-NEXT:    [[TMP297:%.*]] = sext i1 [[TMP296]] to i8
16696 // CHECK-NEXT:    store i8 [[TMP297]], ptr [[CR]], align 1
16697 // CHECK-NEXT:    [[TMP298:%.*]] = load i8, ptr [[CE]], align 1
16698 // CHECK-NEXT:    [[TMP299:%.*]] = load i8, ptr [[CD]], align 1
16699 // CHECK-NEXT:    [[TMP300:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP298]], i8 [[TMP299]] monotonic monotonic, align 1
16700 // CHECK-NEXT:    [[TMP301:%.*]] = extractvalue { i8, i1 } [[TMP300]], 0
16701 // CHECK-NEXT:    [[TMP302:%.*]] = extractvalue { i8, i1 } [[TMP300]], 1
16702 // CHECK-NEXT:    br i1 [[TMP302]], label [[CX_ATOMIC_EXIT27:%.*]], label [[CX_ATOMIC_CONT28:%.*]]
16703 // CHECK:       cx.atomic.cont28:
16704 // CHECK-NEXT:    store i8 [[TMP301]], ptr [[CV]], align 1
16705 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT27]]
16706 // CHECK:       cx.atomic.exit27:
16707 // CHECK-NEXT:    [[TMP303:%.*]] = extractvalue { i8, i1 } [[TMP300]], 1
16708 // CHECK-NEXT:    [[TMP304:%.*]] = sext i1 [[TMP303]] to i8
16709 // CHECK-NEXT:    store i8 [[TMP304]], ptr [[CR]], align 1
16710 // CHECK-NEXT:    [[TMP305:%.*]] = load i8, ptr [[CE]], align 1
16711 // CHECK-NEXT:    [[TMP306:%.*]] = load i8, ptr [[CD]], align 1
16712 // CHECK-NEXT:    [[TMP307:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP305]], i8 [[TMP306]] monotonic monotonic, align 1
16713 // CHECK-NEXT:    [[TMP308:%.*]] = extractvalue { i8, i1 } [[TMP307]], 0
16714 // CHECK-NEXT:    [[TMP309:%.*]] = extractvalue { i8, i1 } [[TMP307]], 1
16715 // CHECK-NEXT:    br i1 [[TMP309]], label [[CX_ATOMIC_EXIT29:%.*]], label [[CX_ATOMIC_CONT30:%.*]]
16716 // CHECK:       cx.atomic.cont30:
16717 // CHECK-NEXT:    store i8 [[TMP308]], ptr [[CV]], align 1
16718 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT29]]
16719 // CHECK:       cx.atomic.exit29:
16720 // CHECK-NEXT:    [[TMP310:%.*]] = extractvalue { i8, i1 } [[TMP307]], 1
16721 // CHECK-NEXT:    [[TMP311:%.*]] = sext i1 [[TMP310]] to i8
16722 // CHECK-NEXT:    store i8 [[TMP311]], ptr [[CR]], align 1
16723 // CHECK-NEXT:    [[TMP312:%.*]] = load i8, ptr [[CE]], align 1
16724 // CHECK-NEXT:    [[TMP313:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP312]] release, align 1
16725 // CHECK-NEXT:    store i8 [[TMP313]], ptr [[CV]], align 1
16726 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16727 // CHECK-NEXT:    [[TMP314:%.*]] = load i8, ptr [[CE]], align 1
16728 // CHECK-NEXT:    [[TMP315:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP314]] release, align 1
16729 // CHECK-NEXT:    store i8 [[TMP315]], ptr [[CV]], align 1
16730 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16731 // CHECK-NEXT:    [[TMP316:%.*]] = load i8, ptr [[CE]], align 1
16732 // CHECK-NEXT:    [[TMP317:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP316]] release, align 1
16733 // CHECK-NEXT:    store i8 [[TMP317]], ptr [[CV]], align 1
16734 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16735 // CHECK-NEXT:    [[TMP318:%.*]] = load i8, ptr [[CE]], align 1
16736 // CHECK-NEXT:    [[TMP319:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP318]] release, align 1
16737 // CHECK-NEXT:    store i8 [[TMP319]], ptr [[CV]], align 1
16738 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16739 // CHECK-NEXT:    [[TMP320:%.*]] = load i8, ptr [[CE]], align 1
16740 // CHECK-NEXT:    [[TMP321:%.*]] = load i8, ptr [[CD]], align 1
16741 // CHECK-NEXT:    [[TMP322:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP320]], i8 [[TMP321]] release monotonic, align 1
16742 // CHECK-NEXT:    [[TMP323:%.*]] = extractvalue { i8, i1 } [[TMP322]], 0
16743 // CHECK-NEXT:    store i8 [[TMP323]], ptr [[CV]], align 1
16744 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16745 // CHECK-NEXT:    [[TMP324:%.*]] = load i8, ptr [[CE]], align 1
16746 // CHECK-NEXT:    [[TMP325:%.*]] = load i8, ptr [[CD]], align 1
16747 // CHECK-NEXT:    [[TMP326:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP324]], i8 [[TMP325]] release monotonic, align 1
16748 // CHECK-NEXT:    [[TMP327:%.*]] = extractvalue { i8, i1 } [[TMP326]], 0
16749 // CHECK-NEXT:    store i8 [[TMP327]], ptr [[CV]], align 1
16750 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16751 // CHECK-NEXT:    [[TMP328:%.*]] = load i8, ptr [[CE]], align 1
16752 // CHECK-NEXT:    [[TMP329:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP328]] release, align 1
16753 // CHECK-NEXT:    [[TMP330:%.*]] = icmp sgt i8 [[TMP329]], [[TMP328]]
16754 // CHECK-NEXT:    [[TMP331:%.*]] = select i1 [[TMP330]], i8 [[TMP328]], i8 [[TMP329]]
16755 // CHECK-NEXT:    store i8 [[TMP331]], ptr [[CV]], align 1
16756 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16757 // CHECK-NEXT:    [[TMP332:%.*]] = load i8, ptr [[CE]], align 1
16758 // CHECK-NEXT:    [[TMP333:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP332]] release, align 1
16759 // CHECK-NEXT:    [[TMP334:%.*]] = icmp slt i8 [[TMP333]], [[TMP332]]
16760 // CHECK-NEXT:    [[TMP335:%.*]] = select i1 [[TMP334]], i8 [[TMP332]], i8 [[TMP333]]
16761 // CHECK-NEXT:    store i8 [[TMP335]], ptr [[CV]], align 1
16762 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16763 // CHECK-NEXT:    [[TMP336:%.*]] = load i8, ptr [[CE]], align 1
16764 // CHECK-NEXT:    [[TMP337:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP336]] release, align 1
16765 // CHECK-NEXT:    [[TMP338:%.*]] = icmp slt i8 [[TMP337]], [[TMP336]]
16766 // CHECK-NEXT:    [[TMP339:%.*]] = select i1 [[TMP338]], i8 [[TMP336]], i8 [[TMP337]]
16767 // CHECK-NEXT:    store i8 [[TMP339]], ptr [[CV]], align 1
16768 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16769 // CHECK-NEXT:    [[TMP340:%.*]] = load i8, ptr [[CE]], align 1
16770 // CHECK-NEXT:    [[TMP341:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP340]] release, align 1
16771 // CHECK-NEXT:    [[TMP342:%.*]] = icmp sgt i8 [[TMP341]], [[TMP340]]
16772 // CHECK-NEXT:    [[TMP343:%.*]] = select i1 [[TMP342]], i8 [[TMP340]], i8 [[TMP341]]
16773 // CHECK-NEXT:    store i8 [[TMP343]], ptr [[CV]], align 1
16774 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16775 // CHECK-NEXT:    [[TMP344:%.*]] = load i8, ptr [[CE]], align 1
16776 // CHECK-NEXT:    [[TMP345:%.*]] = load i8, ptr [[CD]], align 1
16777 // CHECK-NEXT:    [[TMP346:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP344]], i8 [[TMP345]] release monotonic, align 1
16778 // CHECK-NEXT:    [[TMP347:%.*]] = extractvalue { i8, i1 } [[TMP346]], 0
16779 // CHECK-NEXT:    [[TMP348:%.*]] = extractvalue { i8, i1 } [[TMP346]], 1
16780 // CHECK-NEXT:    [[TMP349:%.*]] = select i1 [[TMP348]], i8 [[TMP344]], i8 [[TMP347]]
16781 // CHECK-NEXT:    store i8 [[TMP349]], ptr [[CV]], align 1
16782 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16783 // CHECK-NEXT:    [[TMP350:%.*]] = load i8, ptr [[CE]], align 1
16784 // CHECK-NEXT:    [[TMP351:%.*]] = load i8, ptr [[CD]], align 1
16785 // CHECK-NEXT:    [[TMP352:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP350]], i8 [[TMP351]] release monotonic, align 1
16786 // CHECK-NEXT:    [[TMP353:%.*]] = extractvalue { i8, i1 } [[TMP352]], 0
16787 // CHECK-NEXT:    [[TMP354:%.*]] = extractvalue { i8, i1 } [[TMP352]], 1
16788 // CHECK-NEXT:    [[TMP355:%.*]] = select i1 [[TMP354]], i8 [[TMP350]], i8 [[TMP353]]
16789 // CHECK-NEXT:    store i8 [[TMP355]], ptr [[CV]], align 1
16790 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16791 // CHECK-NEXT:    [[TMP356:%.*]] = load i8, ptr [[CE]], align 1
16792 // CHECK-NEXT:    [[TMP357:%.*]] = load i8, ptr [[CD]], align 1
16793 // CHECK-NEXT:    [[TMP358:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP356]], i8 [[TMP357]] release monotonic, align 1
16794 // CHECK-NEXT:    [[TMP359:%.*]] = extractvalue { i8, i1 } [[TMP358]], 0
16795 // CHECK-NEXT:    [[TMP360:%.*]] = extractvalue { i8, i1 } [[TMP358]], 1
16796 // CHECK-NEXT:    br i1 [[TMP360]], label [[CX_ATOMIC_EXIT31:%.*]], label [[CX_ATOMIC_CONT32:%.*]]
16797 // CHECK:       cx.atomic.cont32:
16798 // CHECK-NEXT:    store i8 [[TMP359]], ptr [[CV]], align 1
16799 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT31]]
16800 // CHECK:       cx.atomic.exit31:
16801 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16802 // CHECK-NEXT:    [[TMP361:%.*]] = load i8, ptr [[CE]], align 1
16803 // CHECK-NEXT:    [[TMP362:%.*]] = load i8, ptr [[CD]], align 1
16804 // CHECK-NEXT:    [[TMP363:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP361]], i8 [[TMP362]] release monotonic, align 1
16805 // CHECK-NEXT:    [[TMP364:%.*]] = extractvalue { i8, i1 } [[TMP363]], 0
16806 // CHECK-NEXT:    [[TMP365:%.*]] = extractvalue { i8, i1 } [[TMP363]], 1
16807 // CHECK-NEXT:    br i1 [[TMP365]], label [[CX_ATOMIC_EXIT33:%.*]], label [[CX_ATOMIC_CONT34:%.*]]
16808 // CHECK:       cx.atomic.cont34:
16809 // CHECK-NEXT:    store i8 [[TMP364]], ptr [[CV]], align 1
16810 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT33]]
16811 // CHECK:       cx.atomic.exit33:
16812 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16813 // CHECK-NEXT:    [[TMP366:%.*]] = load i8, ptr [[CE]], align 1
16814 // CHECK-NEXT:    [[TMP367:%.*]] = load i8, ptr [[CD]], align 1
16815 // CHECK-NEXT:    [[TMP368:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP366]], i8 [[TMP367]] release monotonic, align 1
16816 // CHECK-NEXT:    [[TMP369:%.*]] = extractvalue { i8, i1 } [[TMP368]], 1
16817 // CHECK-NEXT:    [[TMP370:%.*]] = sext i1 [[TMP369]] to i8
16818 // CHECK-NEXT:    store i8 [[TMP370]], ptr [[CR]], align 1
16819 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16820 // CHECK-NEXT:    [[TMP371:%.*]] = load i8, ptr [[CE]], align 1
16821 // CHECK-NEXT:    [[TMP372:%.*]] = load i8, ptr [[CD]], align 1
16822 // CHECK-NEXT:    [[TMP373:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP371]], i8 [[TMP372]] release monotonic, align 1
16823 // CHECK-NEXT:    [[TMP374:%.*]] = extractvalue { i8, i1 } [[TMP373]], 1
16824 // CHECK-NEXT:    [[TMP375:%.*]] = sext i1 [[TMP374]] to i8
16825 // CHECK-NEXT:    store i8 [[TMP375]], ptr [[CR]], align 1
16826 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16827 // CHECK-NEXT:    [[TMP376:%.*]] = load i8, ptr [[CE]], align 1
16828 // CHECK-NEXT:    [[TMP377:%.*]] = load i8, ptr [[CD]], align 1
16829 // CHECK-NEXT:    [[TMP378:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP376]], i8 [[TMP377]] release monotonic, align 1
16830 // CHECK-NEXT:    [[TMP379:%.*]] = extractvalue { i8, i1 } [[TMP378]], 0
16831 // CHECK-NEXT:    [[TMP380:%.*]] = extractvalue { i8, i1 } [[TMP378]], 1
16832 // CHECK-NEXT:    br i1 [[TMP380]], label [[CX_ATOMIC_EXIT35:%.*]], label [[CX_ATOMIC_CONT36:%.*]]
16833 // CHECK:       cx.atomic.cont36:
16834 // CHECK-NEXT:    store i8 [[TMP379]], ptr [[CV]], align 1
16835 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT35]]
16836 // CHECK:       cx.atomic.exit35:
16837 // CHECK-NEXT:    [[TMP381:%.*]] = extractvalue { i8, i1 } [[TMP378]], 1
16838 // CHECK-NEXT:    [[TMP382:%.*]] = sext i1 [[TMP381]] to i8
16839 // CHECK-NEXT:    store i8 [[TMP382]], ptr [[CR]], align 1
16840 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16841 // CHECK-NEXT:    [[TMP383:%.*]] = load i8, ptr [[CE]], align 1
16842 // CHECK-NEXT:    [[TMP384:%.*]] = load i8, ptr [[CD]], align 1
16843 // CHECK-NEXT:    [[TMP385:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP383]], i8 [[TMP384]] release monotonic, align 1
16844 // CHECK-NEXT:    [[TMP386:%.*]] = extractvalue { i8, i1 } [[TMP385]], 0
16845 // CHECK-NEXT:    [[TMP387:%.*]] = extractvalue { i8, i1 } [[TMP385]], 1
16846 // CHECK-NEXT:    br i1 [[TMP387]], label [[CX_ATOMIC_EXIT37:%.*]], label [[CX_ATOMIC_CONT38:%.*]]
16847 // CHECK:       cx.atomic.cont38:
16848 // CHECK-NEXT:    store i8 [[TMP386]], ptr [[CV]], align 1
16849 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT37]]
16850 // CHECK:       cx.atomic.exit37:
16851 // CHECK-NEXT:    [[TMP388:%.*]] = extractvalue { i8, i1 } [[TMP385]], 1
16852 // CHECK-NEXT:    [[TMP389:%.*]] = sext i1 [[TMP388]] to i8
16853 // CHECK-NEXT:    store i8 [[TMP389]], ptr [[CR]], align 1
16854 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16855 // CHECK-NEXT:    [[TMP390:%.*]] = load i8, ptr [[CE]], align 1
16856 // CHECK-NEXT:    [[TMP391:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP390]] seq_cst, align 1
16857 // CHECK-NEXT:    store i8 [[TMP391]], ptr [[CV]], align 1
16858 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16859 // CHECK-NEXT:    [[TMP392:%.*]] = load i8, ptr [[CE]], align 1
16860 // CHECK-NEXT:    [[TMP393:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP392]] seq_cst, align 1
16861 // CHECK-NEXT:    store i8 [[TMP393]], ptr [[CV]], align 1
16862 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16863 // CHECK-NEXT:    [[TMP394:%.*]] = load i8, ptr [[CE]], align 1
16864 // CHECK-NEXT:    [[TMP395:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP394]] seq_cst, align 1
16865 // CHECK-NEXT:    store i8 [[TMP395]], ptr [[CV]], align 1
16866 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16867 // CHECK-NEXT:    [[TMP396:%.*]] = load i8, ptr [[CE]], align 1
16868 // CHECK-NEXT:    [[TMP397:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP396]] seq_cst, align 1
16869 // CHECK-NEXT:    store i8 [[TMP397]], ptr [[CV]], align 1
16870 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16871 // CHECK-NEXT:    [[TMP398:%.*]] = load i8, ptr [[CE]], align 1
16872 // CHECK-NEXT:    [[TMP399:%.*]] = load i8, ptr [[CD]], align 1
16873 // CHECK-NEXT:    [[TMP400:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP398]], i8 [[TMP399]] seq_cst seq_cst, align 1
16874 // CHECK-NEXT:    [[TMP401:%.*]] = extractvalue { i8, i1 } [[TMP400]], 0
16875 // CHECK-NEXT:    store i8 [[TMP401]], ptr [[CV]], align 1
16876 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16877 // CHECK-NEXT:    [[TMP402:%.*]] = load i8, ptr [[CE]], align 1
16878 // CHECK-NEXT:    [[TMP403:%.*]] = load i8, ptr [[CD]], align 1
16879 // CHECK-NEXT:    [[TMP404:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP402]], i8 [[TMP403]] seq_cst seq_cst, align 1
16880 // CHECK-NEXT:    [[TMP405:%.*]] = extractvalue { i8, i1 } [[TMP404]], 0
16881 // CHECK-NEXT:    store i8 [[TMP405]], ptr [[CV]], align 1
16882 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16883 // CHECK-NEXT:    [[TMP406:%.*]] = load i8, ptr [[CE]], align 1
16884 // CHECK-NEXT:    [[TMP407:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP406]] seq_cst, align 1
16885 // CHECK-NEXT:    [[TMP408:%.*]] = icmp sgt i8 [[TMP407]], [[TMP406]]
16886 // CHECK-NEXT:    [[TMP409:%.*]] = select i1 [[TMP408]], i8 [[TMP406]], i8 [[TMP407]]
16887 // CHECK-NEXT:    store i8 [[TMP409]], ptr [[CV]], align 1
16888 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16889 // CHECK-NEXT:    [[TMP410:%.*]] = load i8, ptr [[CE]], align 1
16890 // CHECK-NEXT:    [[TMP411:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP410]] seq_cst, align 1
16891 // CHECK-NEXT:    [[TMP412:%.*]] = icmp slt i8 [[TMP411]], [[TMP410]]
16892 // CHECK-NEXT:    [[TMP413:%.*]] = select i1 [[TMP412]], i8 [[TMP410]], i8 [[TMP411]]
16893 // CHECK-NEXT:    store i8 [[TMP413]], ptr [[CV]], align 1
16894 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16895 // CHECK-NEXT:    [[TMP414:%.*]] = load i8, ptr [[CE]], align 1
16896 // CHECK-NEXT:    [[TMP415:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP414]] seq_cst, align 1
16897 // CHECK-NEXT:    [[TMP416:%.*]] = icmp slt i8 [[TMP415]], [[TMP414]]
16898 // CHECK-NEXT:    [[TMP417:%.*]] = select i1 [[TMP416]], i8 [[TMP414]], i8 [[TMP415]]
16899 // CHECK-NEXT:    store i8 [[TMP417]], ptr [[CV]], align 1
16900 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16901 // CHECK-NEXT:    [[TMP418:%.*]] = load i8, ptr [[CE]], align 1
16902 // CHECK-NEXT:    [[TMP419:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP418]] seq_cst, align 1
16903 // CHECK-NEXT:    [[TMP420:%.*]] = icmp sgt i8 [[TMP419]], [[TMP418]]
16904 // CHECK-NEXT:    [[TMP421:%.*]] = select i1 [[TMP420]], i8 [[TMP418]], i8 [[TMP419]]
16905 // CHECK-NEXT:    store i8 [[TMP421]], ptr [[CV]], align 1
16906 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16907 // CHECK-NEXT:    [[TMP422:%.*]] = load i8, ptr [[CE]], align 1
16908 // CHECK-NEXT:    [[TMP423:%.*]] = load i8, ptr [[CD]], align 1
16909 // CHECK-NEXT:    [[TMP424:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP422]], i8 [[TMP423]] seq_cst seq_cst, align 1
16910 // CHECK-NEXT:    [[TMP425:%.*]] = extractvalue { i8, i1 } [[TMP424]], 0
16911 // CHECK-NEXT:    [[TMP426:%.*]] = extractvalue { i8, i1 } [[TMP424]], 1
16912 // CHECK-NEXT:    [[TMP427:%.*]] = select i1 [[TMP426]], i8 [[TMP422]], i8 [[TMP425]]
16913 // CHECK-NEXT:    store i8 [[TMP427]], ptr [[CV]], align 1
16914 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16915 // CHECK-NEXT:    [[TMP428:%.*]] = load i8, ptr [[CE]], align 1
16916 // CHECK-NEXT:    [[TMP429:%.*]] = load i8, ptr [[CD]], align 1
16917 // CHECK-NEXT:    [[TMP430:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP428]], i8 [[TMP429]] seq_cst seq_cst, align 1
16918 // CHECK-NEXT:    [[TMP431:%.*]] = extractvalue { i8, i1 } [[TMP430]], 0
16919 // CHECK-NEXT:    [[TMP432:%.*]] = extractvalue { i8, i1 } [[TMP430]], 1
16920 // CHECK-NEXT:    [[TMP433:%.*]] = select i1 [[TMP432]], i8 [[TMP428]], i8 [[TMP431]]
16921 // CHECK-NEXT:    store i8 [[TMP433]], ptr [[CV]], align 1
16922 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16923 // CHECK-NEXT:    [[TMP434:%.*]] = load i8, ptr [[CE]], align 1
16924 // CHECK-NEXT:    [[TMP435:%.*]] = load i8, ptr [[CD]], align 1
16925 // CHECK-NEXT:    [[TMP436:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP434]], i8 [[TMP435]] seq_cst seq_cst, align 1
16926 // CHECK-NEXT:    [[TMP437:%.*]] = extractvalue { i8, i1 } [[TMP436]], 0
16927 // CHECK-NEXT:    [[TMP438:%.*]] = extractvalue { i8, i1 } [[TMP436]], 1
16928 // CHECK-NEXT:    br i1 [[TMP438]], label [[CX_ATOMIC_EXIT39:%.*]], label [[CX_ATOMIC_CONT40:%.*]]
16929 // CHECK:       cx.atomic.cont40:
16930 // CHECK-NEXT:    store i8 [[TMP437]], ptr [[CV]], align 1
16931 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT39]]
16932 // CHECK:       cx.atomic.exit39:
16933 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16934 // CHECK-NEXT:    [[TMP439:%.*]] = load i8, ptr [[CE]], align 1
16935 // CHECK-NEXT:    [[TMP440:%.*]] = load i8, ptr [[CD]], align 1
16936 // CHECK-NEXT:    [[TMP441:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP439]], i8 [[TMP440]] seq_cst seq_cst, align 1
16937 // CHECK-NEXT:    [[TMP442:%.*]] = extractvalue { i8, i1 } [[TMP441]], 0
16938 // CHECK-NEXT:    [[TMP443:%.*]] = extractvalue { i8, i1 } [[TMP441]], 1
16939 // CHECK-NEXT:    br i1 [[TMP443]], label [[CX_ATOMIC_EXIT41:%.*]], label [[CX_ATOMIC_CONT42:%.*]]
16940 // CHECK:       cx.atomic.cont42:
16941 // CHECK-NEXT:    store i8 [[TMP442]], ptr [[CV]], align 1
16942 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT41]]
16943 // CHECK:       cx.atomic.exit41:
16944 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16945 // CHECK-NEXT:    [[TMP444:%.*]] = load i8, ptr [[CE]], align 1
16946 // CHECK-NEXT:    [[TMP445:%.*]] = load i8, ptr [[CD]], align 1
16947 // CHECK-NEXT:    [[TMP446:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP444]], i8 [[TMP445]] seq_cst seq_cst, align 1
16948 // CHECK-NEXT:    [[TMP447:%.*]] = extractvalue { i8, i1 } [[TMP446]], 1
16949 // CHECK-NEXT:    [[TMP448:%.*]] = sext i1 [[TMP447]] to i8
16950 // CHECK-NEXT:    store i8 [[TMP448]], ptr [[CR]], align 1
16951 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16952 // CHECK-NEXT:    [[TMP449:%.*]] = load i8, ptr [[CE]], align 1
16953 // CHECK-NEXT:    [[TMP450:%.*]] = load i8, ptr [[CD]], align 1
16954 // CHECK-NEXT:    [[TMP451:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP449]], i8 [[TMP450]] seq_cst seq_cst, align 1
16955 // CHECK-NEXT:    [[TMP452:%.*]] = extractvalue { i8, i1 } [[TMP451]], 1
16956 // CHECK-NEXT:    [[TMP453:%.*]] = sext i1 [[TMP452]] to i8
16957 // CHECK-NEXT:    store i8 [[TMP453]], ptr [[CR]], align 1
16958 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16959 // CHECK-NEXT:    [[TMP454:%.*]] = load i8, ptr [[CE]], align 1
16960 // CHECK-NEXT:    [[TMP455:%.*]] = load i8, ptr [[CD]], align 1
16961 // CHECK-NEXT:    [[TMP456:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP454]], i8 [[TMP455]] seq_cst seq_cst, align 1
16962 // CHECK-NEXT:    [[TMP457:%.*]] = extractvalue { i8, i1 } [[TMP456]], 0
16963 // CHECK-NEXT:    [[TMP458:%.*]] = extractvalue { i8, i1 } [[TMP456]], 1
16964 // CHECK-NEXT:    br i1 [[TMP458]], label [[CX_ATOMIC_EXIT43:%.*]], label [[CX_ATOMIC_CONT44:%.*]]
16965 // CHECK:       cx.atomic.cont44:
16966 // CHECK-NEXT:    store i8 [[TMP457]], ptr [[CV]], align 1
16967 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT43]]
16968 // CHECK:       cx.atomic.exit43:
16969 // CHECK-NEXT:    [[TMP459:%.*]] = extractvalue { i8, i1 } [[TMP456]], 1
16970 // CHECK-NEXT:    [[TMP460:%.*]] = sext i1 [[TMP459]] to i8
16971 // CHECK-NEXT:    store i8 [[TMP460]], ptr [[CR]], align 1
16972 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16973 // CHECK-NEXT:    [[TMP461:%.*]] = load i8, ptr [[CE]], align 1
16974 // CHECK-NEXT:    [[TMP462:%.*]] = load i8, ptr [[CD]], align 1
16975 // CHECK-NEXT:    [[TMP463:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP461]], i8 [[TMP462]] seq_cst seq_cst, align 1
16976 // CHECK-NEXT:    [[TMP464:%.*]] = extractvalue { i8, i1 } [[TMP463]], 0
16977 // CHECK-NEXT:    [[TMP465:%.*]] = extractvalue { i8, i1 } [[TMP463]], 1
16978 // CHECK-NEXT:    br i1 [[TMP465]], label [[CX_ATOMIC_EXIT45:%.*]], label [[CX_ATOMIC_CONT46:%.*]]
16979 // CHECK:       cx.atomic.cont46:
16980 // CHECK-NEXT:    store i8 [[TMP464]], ptr [[CV]], align 1
16981 // CHECK-NEXT:    br label [[CX_ATOMIC_EXIT45]]
16982 // CHECK:       cx.atomic.exit45:
16983 // CHECK-NEXT:    [[TMP466:%.*]] = extractvalue { i8, i1 } [[TMP463]], 1
16984 // CHECK-NEXT:    [[TMP467:%.*]] = sext i1 [[TMP466]] to i8
16985 // CHECK-NEXT:    store i8 [[TMP467]], ptr [[CR]], align 1
16986 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
16987 // CHECK-NEXT:    [[TMP468:%.*]] = load i8, ptr [[UCE]], align 1
16988 // CHECK-NEXT:    [[TMP469:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP468]] monotonic, align 1
16989 // CHECK-NEXT:    store i8 [[TMP469]], ptr [[UCV]], align 1
16990 // CHECK-NEXT:    [[TMP470:%.*]] = load i8, ptr [[UCE]], align 1
16991 // CHECK-NEXT:    [[TMP471:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP470]] monotonic, align 1
16992 // CHECK-NEXT:    store i8 [[TMP471]], ptr [[UCV]], align 1
16993 // CHECK-NEXT:    [[TMP472:%.*]] = load i8, ptr [[UCE]], align 1
16994 // CHECK-NEXT:    [[TMP473:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP472]] monotonic, align 1
16995 // CHECK-NEXT:    store i8 [[TMP473]], ptr [[UCV]], align 1
16996 // CHECK-NEXT:    [[TMP474:%.*]] = load i8, ptr [[UCE]], align 1
16997 // CHECK-NEXT:    [[TMP475:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP474]] monotonic, align 1
16998 // CHECK-NEXT:    store i8 [[TMP475]], ptr [[UCV]], align 1
16999 // CHECK-NEXT:    [[TMP476:%.*]] = load i8, ptr [[UCE]], align 1
17000 // CHECK-NEXT:    [[TMP477:%.*]] = load i8, ptr [[UCD]], align 1
17001 // CHECK-NEXT:    [[TMP478:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP476]], i8 [[TMP477]] monotonic monotonic, align 1
17002 // CHECK-NEXT:    [[TMP479:%.*]] = extractvalue { i8, i1 } [[TMP478]], 0
17003 // CHECK-NEXT:    store i8 [[TMP479]], ptr [[UCV]], align 1
17004 // CHECK-NEXT:    [[TMP480:%.*]] = load i8, ptr [[UCE]], align 1
17005 // CHECK-NEXT:    [[TMP481:%.*]] = load i8, ptr [[UCD]], align 1
17006 // CHECK-NEXT:    [[TMP482:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP480]], i8 [[TMP481]] monotonic monotonic, align 1
17007 // CHECK-NEXT:    [[TMP483:%.*]] = extractvalue { i8, i1 } [[TMP482]], 0
17008 // CHECK-NEXT:    store i8 [[TMP483]], ptr [[UCV]], align 1
17009 // CHECK-NEXT:    [[TMP484:%.*]] = load i8, ptr [[UCE]], align 1
17010 // CHECK-NEXT:    [[TMP485:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP484]] monotonic, align 1
17011 // CHECK-NEXT:    [[TMP486:%.*]] = icmp ugt i8 [[TMP485]], [[TMP484]]
17012 // CHECK-NEXT:    [[TMP487:%.*]] = select i1 [[TMP486]], i8 [[TMP484]], i8 [[TMP485]]
17013 // CHECK-NEXT:    store i8 [[TMP487]], ptr [[UCV]], align 1
17014 // CHECK-NEXT:    [[TMP488:%.*]] = load i8, ptr [[UCE]], align 1
17015 // CHECK-NEXT:    [[TMP489:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP488]] monotonic, align 1
17016 // CHECK-NEXT:    [[TMP490:%.*]] = icmp ult i8 [[TMP489]], [[TMP488]]
17017 // CHECK-NEXT:    [[TMP491:%.*]] = select i1 [[TMP490]], i8 [[TMP488]], i8 [[TMP489]]
17018 // CHECK-NEXT:    store i8 [[TMP491]], ptr [[UCV]], align 1
17019 // CHECK-NEXT:    [[TMP492:%.*]] = load i8, ptr [[UCE]], align 1
17020 // CHECK-NEXT:    [[TMP493:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP492]] monotonic, align 1
17021 // CHECK-NEXT:    [[TMP494:%.*]] = icmp ult i8 [[TMP493]], [[TMP492]]
17022 // CHECK-NEXT:    [[TMP495:%.*]] = select i1 [[TMP494]], i8 [[TMP492]], i8 [[TMP493]]
17023 // CHECK-NEXT:    store i8 [[TMP495]], ptr [[UCV]], align 1
17024 // CHECK-NEXT:    [[TMP496:%.*]] = load i8, ptr [[UCE]], align 1
17025 // CHECK-NEXT:    [[TMP497:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP496]] monotonic, align 1
17026 // CHECK-NEXT:    [[TMP498:%.*]] = icmp ugt i8 [[TMP497]], [[TMP496]]
17027 // CHECK-NEXT:    [[TMP499:%.*]] = select i1 [[TMP498]], i8 [[TMP496]], i8 [[TMP497]]
17028 // CHECK-NEXT:    store i8 [[TMP499]], ptr [[UCV]], align 1
17029 // CHECK-NEXT:    [[TMP500:%.*]] = load i8, ptr [[UCE]], align 1
17030 // CHECK-NEXT:    [[TMP501:%.*]] = load i8, ptr [[UCD]], align 1
17031 // CHECK-NEXT:    [[TMP502:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP500]], i8 [[TMP501]] monotonic monotonic, align 1
17032 // CHECK-NEXT:    [[TMP503:%.*]] = extractvalue { i8, i1 } [[TMP502]], 0
17033 // CHECK-NEXT:    [[TMP504:%.*]] = extractvalue { i8, i1 } [[TMP502]], 1
17034 // CHECK-NEXT:    [[TMP505:%.*]] = select i1 [[TMP504]], i8 [[TMP500]], i8 [[TMP503]]
17035 // CHECK-NEXT:    store i8 [[TMP505]], ptr [[UCV]], align 1
17036 // CHECK-NEXT:    [[TMP506:%.*]] = load i8, ptr [[UCE]], align 1
17037 // CHECK-NEXT:    [[TMP507:%.*]] = load i8, ptr [[UCD]], align 1
17038 // CHECK-NEXT:    [[TMP508:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP506]], i8 [[TMP507]] monotonic monotonic, align 1
17039 // CHECK-NEXT:    [[TMP509:%.*]] = extractvalue { i8, i1 } [[TMP508]], 0
17040 // CHECK-NEXT:    [[TMP510:%.*]] = extractvalue { i8, i1 } [[TMP508]], 1
17041 // CHECK-NEXT:    [[TMP511:%.*]] = select i1 [[TMP510]], i8 [[TMP506]], i8 [[TMP509]]
17042 // CHECK-NEXT:    store i8 [[TMP511]], ptr [[UCV]], align 1
17043 // CHECK-NEXT:    [[TMP512:%.*]] = load i8, ptr [[UCE]], align 1
17044 // CHECK-NEXT:    [[TMP513:%.*]] = load i8, ptr [[UCD]], align 1
17045 // CHECK-NEXT:    [[TMP514:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP512]], i8 [[TMP513]] monotonic monotonic, align 1
17046 // CHECK-NEXT:    [[TMP515:%.*]] = extractvalue { i8, i1 } [[TMP514]], 0
17047 // CHECK-NEXT:    [[TMP516:%.*]] = extractvalue { i8, i1 } [[TMP514]], 1
17048 // CHECK-NEXT:    br i1 [[TMP516]], label [[UCX_ATOMIC_EXIT:%.*]], label [[UCX_ATOMIC_CONT:%.*]]
17049 // CHECK:       ucx.atomic.cont:
17050 // CHECK-NEXT:    store i8 [[TMP515]], ptr [[UCV]], align 1
17051 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT]]
17052 // CHECK:       ucx.atomic.exit:
17053 // CHECK-NEXT:    [[TMP517:%.*]] = load i8, ptr [[UCE]], align 1
17054 // CHECK-NEXT:    [[TMP518:%.*]] = load i8, ptr [[UCD]], align 1
17055 // CHECK-NEXT:    [[TMP519:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP517]], i8 [[TMP518]] monotonic monotonic, align 1
17056 // CHECK-NEXT:    [[TMP520:%.*]] = extractvalue { i8, i1 } [[TMP519]], 0
17057 // CHECK-NEXT:    [[TMP521:%.*]] = extractvalue { i8, i1 } [[TMP519]], 1
17058 // CHECK-NEXT:    br i1 [[TMP521]], label [[UCX_ATOMIC_EXIT47:%.*]], label [[UCX_ATOMIC_CONT48:%.*]]
17059 // CHECK:       ucx.atomic.cont48:
17060 // CHECK-NEXT:    store i8 [[TMP520]], ptr [[UCV]], align 1
17061 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT47]]
17062 // CHECK:       ucx.atomic.exit47:
17063 // CHECK-NEXT:    [[TMP522:%.*]] = load i8, ptr [[UCE]], align 1
17064 // CHECK-NEXT:    [[TMP523:%.*]] = load i8, ptr [[UCD]], align 1
17065 // CHECK-NEXT:    [[TMP524:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP522]], i8 [[TMP523]] monotonic monotonic, align 1
17066 // CHECK-NEXT:    [[TMP525:%.*]] = extractvalue { i8, i1 } [[TMP524]], 1
17067 // CHECK-NEXT:    [[TMP526:%.*]] = zext i1 [[TMP525]] to i8
17068 // CHECK-NEXT:    store i8 [[TMP526]], ptr [[UCR]], align 1
17069 // CHECK-NEXT:    [[TMP527:%.*]] = load i8, ptr [[UCE]], align 1
17070 // CHECK-NEXT:    [[TMP528:%.*]] = load i8, ptr [[UCD]], align 1
17071 // CHECK-NEXT:    [[TMP529:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP527]], i8 [[TMP528]] monotonic monotonic, align 1
17072 // CHECK-NEXT:    [[TMP530:%.*]] = extractvalue { i8, i1 } [[TMP529]], 1
17073 // CHECK-NEXT:    [[TMP531:%.*]] = zext i1 [[TMP530]] to i8
17074 // CHECK-NEXT:    store i8 [[TMP531]], ptr [[UCR]], align 1
17075 // CHECK-NEXT:    [[TMP532:%.*]] = load i8, ptr [[UCE]], align 1
17076 // CHECK-NEXT:    [[TMP533:%.*]] = load i8, ptr [[UCD]], align 1
17077 // CHECK-NEXT:    [[TMP534:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP532]], i8 [[TMP533]] monotonic monotonic, align 1
17078 // CHECK-NEXT:    [[TMP535:%.*]] = extractvalue { i8, i1 } [[TMP534]], 0
17079 // CHECK-NEXT:    [[TMP536:%.*]] = extractvalue { i8, i1 } [[TMP534]], 1
17080 // CHECK-NEXT:    br i1 [[TMP536]], label [[UCX_ATOMIC_EXIT49:%.*]], label [[UCX_ATOMIC_CONT50:%.*]]
17081 // CHECK:       ucx.atomic.cont50:
17082 // CHECK-NEXT:    store i8 [[TMP535]], ptr [[UCV]], align 1
17083 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT49]]
17084 // CHECK:       ucx.atomic.exit49:
17085 // CHECK-NEXT:    [[TMP537:%.*]] = extractvalue { i8, i1 } [[TMP534]], 1
17086 // CHECK-NEXT:    [[TMP538:%.*]] = zext i1 [[TMP537]] to i8
17087 // CHECK-NEXT:    store i8 [[TMP538]], ptr [[UCR]], align 1
17088 // CHECK-NEXT:    [[TMP539:%.*]] = load i8, ptr [[UCE]], align 1
17089 // CHECK-NEXT:    [[TMP540:%.*]] = load i8, ptr [[UCD]], align 1
17090 // CHECK-NEXT:    [[TMP541:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP539]], i8 [[TMP540]] monotonic monotonic, align 1
17091 // CHECK-NEXT:    [[TMP542:%.*]] = extractvalue { i8, i1 } [[TMP541]], 0
17092 // CHECK-NEXT:    [[TMP543:%.*]] = extractvalue { i8, i1 } [[TMP541]], 1
17093 // CHECK-NEXT:    br i1 [[TMP543]], label [[UCX_ATOMIC_EXIT51:%.*]], label [[UCX_ATOMIC_CONT52:%.*]]
17094 // CHECK:       ucx.atomic.cont52:
17095 // CHECK-NEXT:    store i8 [[TMP542]], ptr [[UCV]], align 1
17096 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT51]]
17097 // CHECK:       ucx.atomic.exit51:
17098 // CHECK-NEXT:    [[TMP544:%.*]] = extractvalue { i8, i1 } [[TMP541]], 1
17099 // CHECK-NEXT:    [[TMP545:%.*]] = zext i1 [[TMP544]] to i8
17100 // CHECK-NEXT:    store i8 [[TMP545]], ptr [[UCR]], align 1
17101 // CHECK-NEXT:    [[TMP546:%.*]] = load i8, ptr [[UCE]], align 1
17102 // CHECK-NEXT:    [[TMP547:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP546]] acq_rel, align 1
17103 // CHECK-NEXT:    store i8 [[TMP547]], ptr [[UCV]], align 1
17104 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17105 // CHECK-NEXT:    [[TMP548:%.*]] = load i8, ptr [[UCE]], align 1
17106 // CHECK-NEXT:    [[TMP549:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP548]] acq_rel, align 1
17107 // CHECK-NEXT:    store i8 [[TMP549]], ptr [[UCV]], align 1
17108 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17109 // CHECK-NEXT:    [[TMP550:%.*]] = load i8, ptr [[UCE]], align 1
17110 // CHECK-NEXT:    [[TMP551:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP550]] acq_rel, align 1
17111 // CHECK-NEXT:    store i8 [[TMP551]], ptr [[UCV]], align 1
17112 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17113 // CHECK-NEXT:    [[TMP552:%.*]] = load i8, ptr [[UCE]], align 1
17114 // CHECK-NEXT:    [[TMP553:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP552]] acq_rel, align 1
17115 // CHECK-NEXT:    store i8 [[TMP553]], ptr [[UCV]], align 1
17116 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17117 // CHECK-NEXT:    [[TMP554:%.*]] = load i8, ptr [[UCE]], align 1
17118 // CHECK-NEXT:    [[TMP555:%.*]] = load i8, ptr [[UCD]], align 1
17119 // CHECK-NEXT:    [[TMP556:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP554]], i8 [[TMP555]] acq_rel acquire, align 1
17120 // CHECK-NEXT:    [[TMP557:%.*]] = extractvalue { i8, i1 } [[TMP556]], 0
17121 // CHECK-NEXT:    store i8 [[TMP557]], ptr [[UCV]], align 1
17122 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17123 // CHECK-NEXT:    [[TMP558:%.*]] = load i8, ptr [[UCE]], align 1
17124 // CHECK-NEXT:    [[TMP559:%.*]] = load i8, ptr [[UCD]], align 1
17125 // CHECK-NEXT:    [[TMP560:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP558]], i8 [[TMP559]] acq_rel acquire, align 1
17126 // CHECK-NEXT:    [[TMP561:%.*]] = extractvalue { i8, i1 } [[TMP560]], 0
17127 // CHECK-NEXT:    store i8 [[TMP561]], ptr [[UCV]], align 1
17128 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17129 // CHECK-NEXT:    [[TMP562:%.*]] = load i8, ptr [[UCE]], align 1
17130 // CHECK-NEXT:    [[TMP563:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP562]] acq_rel, align 1
17131 // CHECK-NEXT:    [[TMP564:%.*]] = icmp ugt i8 [[TMP563]], [[TMP562]]
17132 // CHECK-NEXT:    [[TMP565:%.*]] = select i1 [[TMP564]], i8 [[TMP562]], i8 [[TMP563]]
17133 // CHECK-NEXT:    store i8 [[TMP565]], ptr [[UCV]], align 1
17134 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17135 // CHECK-NEXT:    [[TMP566:%.*]] = load i8, ptr [[UCE]], align 1
17136 // CHECK-NEXT:    [[TMP567:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP566]] acq_rel, align 1
17137 // CHECK-NEXT:    [[TMP568:%.*]] = icmp ult i8 [[TMP567]], [[TMP566]]
17138 // CHECK-NEXT:    [[TMP569:%.*]] = select i1 [[TMP568]], i8 [[TMP566]], i8 [[TMP567]]
17139 // CHECK-NEXT:    store i8 [[TMP569]], ptr [[UCV]], align 1
17140 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17141 // CHECK-NEXT:    [[TMP570:%.*]] = load i8, ptr [[UCE]], align 1
17142 // CHECK-NEXT:    [[TMP571:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP570]] acq_rel, align 1
17143 // CHECK-NEXT:    [[TMP572:%.*]] = icmp ult i8 [[TMP571]], [[TMP570]]
17144 // CHECK-NEXT:    [[TMP573:%.*]] = select i1 [[TMP572]], i8 [[TMP570]], i8 [[TMP571]]
17145 // CHECK-NEXT:    store i8 [[TMP573]], ptr [[UCV]], align 1
17146 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17147 // CHECK-NEXT:    [[TMP574:%.*]] = load i8, ptr [[UCE]], align 1
17148 // CHECK-NEXT:    [[TMP575:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP574]] acq_rel, align 1
17149 // CHECK-NEXT:    [[TMP576:%.*]] = icmp ugt i8 [[TMP575]], [[TMP574]]
17150 // CHECK-NEXT:    [[TMP577:%.*]] = select i1 [[TMP576]], i8 [[TMP574]], i8 [[TMP575]]
17151 // CHECK-NEXT:    store i8 [[TMP577]], ptr [[UCV]], align 1
17152 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17153 // CHECK-NEXT:    [[TMP578:%.*]] = load i8, ptr [[UCE]], align 1
17154 // CHECK-NEXT:    [[TMP579:%.*]] = load i8, ptr [[UCD]], align 1
17155 // CHECK-NEXT:    [[TMP580:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP578]], i8 [[TMP579]] acq_rel acquire, align 1
17156 // CHECK-NEXT:    [[TMP581:%.*]] = extractvalue { i8, i1 } [[TMP580]], 0
17157 // CHECK-NEXT:    [[TMP582:%.*]] = extractvalue { i8, i1 } [[TMP580]], 1
17158 // CHECK-NEXT:    [[TMP583:%.*]] = select i1 [[TMP582]], i8 [[TMP578]], i8 [[TMP581]]
17159 // CHECK-NEXT:    store i8 [[TMP583]], ptr [[UCV]], align 1
17160 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17161 // CHECK-NEXT:    [[TMP584:%.*]] = load i8, ptr [[UCE]], align 1
17162 // CHECK-NEXT:    [[TMP585:%.*]] = load i8, ptr [[UCD]], align 1
17163 // CHECK-NEXT:    [[TMP586:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP584]], i8 [[TMP585]] acq_rel acquire, align 1
17164 // CHECK-NEXT:    [[TMP587:%.*]] = extractvalue { i8, i1 } [[TMP586]], 0
17165 // CHECK-NEXT:    [[TMP588:%.*]] = extractvalue { i8, i1 } [[TMP586]], 1
17166 // CHECK-NEXT:    [[TMP589:%.*]] = select i1 [[TMP588]], i8 [[TMP584]], i8 [[TMP587]]
17167 // CHECK-NEXT:    store i8 [[TMP589]], ptr [[UCV]], align 1
17168 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17169 // CHECK-NEXT:    [[TMP590:%.*]] = load i8, ptr [[UCE]], align 1
17170 // CHECK-NEXT:    [[TMP591:%.*]] = load i8, ptr [[UCD]], align 1
17171 // CHECK-NEXT:    [[TMP592:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP590]], i8 [[TMP591]] acq_rel acquire, align 1
17172 // CHECK-NEXT:    [[TMP593:%.*]] = extractvalue { i8, i1 } [[TMP592]], 0
17173 // CHECK-NEXT:    [[TMP594:%.*]] = extractvalue { i8, i1 } [[TMP592]], 1
17174 // CHECK-NEXT:    br i1 [[TMP594]], label [[UCX_ATOMIC_EXIT53:%.*]], label [[UCX_ATOMIC_CONT54:%.*]]
17175 // CHECK:       ucx.atomic.cont54:
17176 // CHECK-NEXT:    store i8 [[TMP593]], ptr [[UCV]], align 1
17177 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT53]]
17178 // CHECK:       ucx.atomic.exit53:
17179 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17180 // CHECK-NEXT:    [[TMP595:%.*]] = load i8, ptr [[UCE]], align 1
17181 // CHECK-NEXT:    [[TMP596:%.*]] = load i8, ptr [[UCD]], align 1
17182 // CHECK-NEXT:    [[TMP597:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP595]], i8 [[TMP596]] acq_rel acquire, align 1
17183 // CHECK-NEXT:    [[TMP598:%.*]] = extractvalue { i8, i1 } [[TMP597]], 0
17184 // CHECK-NEXT:    [[TMP599:%.*]] = extractvalue { i8, i1 } [[TMP597]], 1
17185 // CHECK-NEXT:    br i1 [[TMP599]], label [[UCX_ATOMIC_EXIT55:%.*]], label [[UCX_ATOMIC_CONT56:%.*]]
17186 // CHECK:       ucx.atomic.cont56:
17187 // CHECK-NEXT:    store i8 [[TMP598]], ptr [[UCV]], align 1
17188 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT55]]
17189 // CHECK:       ucx.atomic.exit55:
17190 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17191 // CHECK-NEXT:    [[TMP600:%.*]] = load i8, ptr [[UCE]], align 1
17192 // CHECK-NEXT:    [[TMP601:%.*]] = load i8, ptr [[UCD]], align 1
17193 // CHECK-NEXT:    [[TMP602:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP600]], i8 [[TMP601]] acq_rel acquire, align 1
17194 // CHECK-NEXT:    [[TMP603:%.*]] = extractvalue { i8, i1 } [[TMP602]], 1
17195 // CHECK-NEXT:    [[TMP604:%.*]] = zext i1 [[TMP603]] to i8
17196 // CHECK-NEXT:    store i8 [[TMP604]], ptr [[UCR]], align 1
17197 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17198 // CHECK-NEXT:    [[TMP605:%.*]] = load i8, ptr [[UCE]], align 1
17199 // CHECK-NEXT:    [[TMP606:%.*]] = load i8, ptr [[UCD]], align 1
17200 // CHECK-NEXT:    [[TMP607:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP605]], i8 [[TMP606]] acq_rel acquire, align 1
17201 // CHECK-NEXT:    [[TMP608:%.*]] = extractvalue { i8, i1 } [[TMP607]], 1
17202 // CHECK-NEXT:    [[TMP609:%.*]] = zext i1 [[TMP608]] to i8
17203 // CHECK-NEXT:    store i8 [[TMP609]], ptr [[UCR]], align 1
17204 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17205 // CHECK-NEXT:    [[TMP610:%.*]] = load i8, ptr [[UCE]], align 1
17206 // CHECK-NEXT:    [[TMP611:%.*]] = load i8, ptr [[UCD]], align 1
17207 // CHECK-NEXT:    [[TMP612:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP610]], i8 [[TMP611]] acq_rel acquire, align 1
17208 // CHECK-NEXT:    [[TMP613:%.*]] = extractvalue { i8, i1 } [[TMP612]], 0
17209 // CHECK-NEXT:    [[TMP614:%.*]] = extractvalue { i8, i1 } [[TMP612]], 1
17210 // CHECK-NEXT:    br i1 [[TMP614]], label [[UCX_ATOMIC_EXIT57:%.*]], label [[UCX_ATOMIC_CONT58:%.*]]
17211 // CHECK:       ucx.atomic.cont58:
17212 // CHECK-NEXT:    store i8 [[TMP613]], ptr [[UCV]], align 1
17213 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT57]]
17214 // CHECK:       ucx.atomic.exit57:
17215 // CHECK-NEXT:    [[TMP615:%.*]] = extractvalue { i8, i1 } [[TMP612]], 1
17216 // CHECK-NEXT:    [[TMP616:%.*]] = zext i1 [[TMP615]] to i8
17217 // CHECK-NEXT:    store i8 [[TMP616]], ptr [[UCR]], align 1
17218 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17219 // CHECK-NEXT:    [[TMP617:%.*]] = load i8, ptr [[UCE]], align 1
17220 // CHECK-NEXT:    [[TMP618:%.*]] = load i8, ptr [[UCD]], align 1
17221 // CHECK-NEXT:    [[TMP619:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP617]], i8 [[TMP618]] acq_rel acquire, align 1
17222 // CHECK-NEXT:    [[TMP620:%.*]] = extractvalue { i8, i1 } [[TMP619]], 0
17223 // CHECK-NEXT:    [[TMP621:%.*]] = extractvalue { i8, i1 } [[TMP619]], 1
17224 // CHECK-NEXT:    br i1 [[TMP621]], label [[UCX_ATOMIC_EXIT59:%.*]], label [[UCX_ATOMIC_CONT60:%.*]]
17225 // CHECK:       ucx.atomic.cont60:
17226 // CHECK-NEXT:    store i8 [[TMP620]], ptr [[UCV]], align 1
17227 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT59]]
17228 // CHECK:       ucx.atomic.exit59:
17229 // CHECK-NEXT:    [[TMP622:%.*]] = extractvalue { i8, i1 } [[TMP619]], 1
17230 // CHECK-NEXT:    [[TMP623:%.*]] = zext i1 [[TMP622]] to i8
17231 // CHECK-NEXT:    store i8 [[TMP623]], ptr [[UCR]], align 1
17232 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17233 // CHECK-NEXT:    [[TMP624:%.*]] = load i8, ptr [[UCE]], align 1
17234 // CHECK-NEXT:    [[TMP625:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP624]] acquire, align 1
17235 // CHECK-NEXT:    store i8 [[TMP625]], ptr [[UCV]], align 1
17236 // CHECK-NEXT:    [[TMP626:%.*]] = load i8, ptr [[UCE]], align 1
17237 // CHECK-NEXT:    [[TMP627:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP626]] acquire, align 1
17238 // CHECK-NEXT:    store i8 [[TMP627]], ptr [[UCV]], align 1
17239 // CHECK-NEXT:    [[TMP628:%.*]] = load i8, ptr [[UCE]], align 1
17240 // CHECK-NEXT:    [[TMP629:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP628]] acquire, align 1
17241 // CHECK-NEXT:    store i8 [[TMP629]], ptr [[UCV]], align 1
17242 // CHECK-NEXT:    [[TMP630:%.*]] = load i8, ptr [[UCE]], align 1
17243 // CHECK-NEXT:    [[TMP631:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP630]] acquire, align 1
17244 // CHECK-NEXT:    store i8 [[TMP631]], ptr [[UCV]], align 1
17245 // CHECK-NEXT:    [[TMP632:%.*]] = load i8, ptr [[UCE]], align 1
17246 // CHECK-NEXT:    [[TMP633:%.*]] = load i8, ptr [[UCD]], align 1
17247 // CHECK-NEXT:    [[TMP634:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP632]], i8 [[TMP633]] acquire acquire, align 1
17248 // CHECK-NEXT:    [[TMP635:%.*]] = extractvalue { i8, i1 } [[TMP634]], 0
17249 // CHECK-NEXT:    store i8 [[TMP635]], ptr [[UCV]], align 1
17250 // CHECK-NEXT:    [[TMP636:%.*]] = load i8, ptr [[UCE]], align 1
17251 // CHECK-NEXT:    [[TMP637:%.*]] = load i8, ptr [[UCD]], align 1
17252 // CHECK-NEXT:    [[TMP638:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP636]], i8 [[TMP637]] acquire acquire, align 1
17253 // CHECK-NEXT:    [[TMP639:%.*]] = extractvalue { i8, i1 } [[TMP638]], 0
17254 // CHECK-NEXT:    store i8 [[TMP639]], ptr [[UCV]], align 1
17255 // CHECK-NEXT:    [[TMP640:%.*]] = load i8, ptr [[UCE]], align 1
17256 // CHECK-NEXT:    [[TMP641:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP640]] acquire, align 1
17257 // CHECK-NEXT:    [[TMP642:%.*]] = icmp ugt i8 [[TMP641]], [[TMP640]]
17258 // CHECK-NEXT:    [[TMP643:%.*]] = select i1 [[TMP642]], i8 [[TMP640]], i8 [[TMP641]]
17259 // CHECK-NEXT:    store i8 [[TMP643]], ptr [[UCV]], align 1
17260 // CHECK-NEXT:    [[TMP644:%.*]] = load i8, ptr [[UCE]], align 1
17261 // CHECK-NEXT:    [[TMP645:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP644]] acquire, align 1
17262 // CHECK-NEXT:    [[TMP646:%.*]] = icmp ult i8 [[TMP645]], [[TMP644]]
17263 // CHECK-NEXT:    [[TMP647:%.*]] = select i1 [[TMP646]], i8 [[TMP644]], i8 [[TMP645]]
17264 // CHECK-NEXT:    store i8 [[TMP647]], ptr [[UCV]], align 1
17265 // CHECK-NEXT:    [[TMP648:%.*]] = load i8, ptr [[UCE]], align 1
17266 // CHECK-NEXT:    [[TMP649:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP648]] acquire, align 1
17267 // CHECK-NEXT:    [[TMP650:%.*]] = icmp ult i8 [[TMP649]], [[TMP648]]
17268 // CHECK-NEXT:    [[TMP651:%.*]] = select i1 [[TMP650]], i8 [[TMP648]], i8 [[TMP649]]
17269 // CHECK-NEXT:    store i8 [[TMP651]], ptr [[UCV]], align 1
17270 // CHECK-NEXT:    [[TMP652:%.*]] = load i8, ptr [[UCE]], align 1
17271 // CHECK-NEXT:    [[TMP653:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP652]] acquire, align 1
17272 // CHECK-NEXT:    [[TMP654:%.*]] = icmp ugt i8 [[TMP653]], [[TMP652]]
17273 // CHECK-NEXT:    [[TMP655:%.*]] = select i1 [[TMP654]], i8 [[TMP652]], i8 [[TMP653]]
17274 // CHECK-NEXT:    store i8 [[TMP655]], ptr [[UCV]], align 1
17275 // CHECK-NEXT:    [[TMP656:%.*]] = load i8, ptr [[UCE]], align 1
17276 // CHECK-NEXT:    [[TMP657:%.*]] = load i8, ptr [[UCD]], align 1
17277 // CHECK-NEXT:    [[TMP658:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP656]], i8 [[TMP657]] acquire acquire, align 1
17278 // CHECK-NEXT:    [[TMP659:%.*]] = extractvalue { i8, i1 } [[TMP658]], 0
17279 // CHECK-NEXT:    [[TMP660:%.*]] = extractvalue { i8, i1 } [[TMP658]], 1
17280 // CHECK-NEXT:    [[TMP661:%.*]] = select i1 [[TMP660]], i8 [[TMP656]], i8 [[TMP659]]
17281 // CHECK-NEXT:    store i8 [[TMP661]], ptr [[UCV]], align 1
17282 // CHECK-NEXT:    [[TMP662:%.*]] = load i8, ptr [[UCE]], align 1
17283 // CHECK-NEXT:    [[TMP663:%.*]] = load i8, ptr [[UCD]], align 1
17284 // CHECK-NEXT:    [[TMP664:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP662]], i8 [[TMP663]] acquire acquire, align 1
17285 // CHECK-NEXT:    [[TMP665:%.*]] = extractvalue { i8, i1 } [[TMP664]], 0
17286 // CHECK-NEXT:    [[TMP666:%.*]] = extractvalue { i8, i1 } [[TMP664]], 1
17287 // CHECK-NEXT:    [[TMP667:%.*]] = select i1 [[TMP666]], i8 [[TMP662]], i8 [[TMP665]]
17288 // CHECK-NEXT:    store i8 [[TMP667]], ptr [[UCV]], align 1
17289 // CHECK-NEXT:    [[TMP668:%.*]] = load i8, ptr [[UCE]], align 1
17290 // CHECK-NEXT:    [[TMP669:%.*]] = load i8, ptr [[UCD]], align 1
17291 // CHECK-NEXT:    [[TMP670:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP668]], i8 [[TMP669]] acquire acquire, align 1
17292 // CHECK-NEXT:    [[TMP671:%.*]] = extractvalue { i8, i1 } [[TMP670]], 0
17293 // CHECK-NEXT:    [[TMP672:%.*]] = extractvalue { i8, i1 } [[TMP670]], 1
17294 // CHECK-NEXT:    br i1 [[TMP672]], label [[UCX_ATOMIC_EXIT61:%.*]], label [[UCX_ATOMIC_CONT62:%.*]]
17295 // CHECK:       ucx.atomic.cont62:
17296 // CHECK-NEXT:    store i8 [[TMP671]], ptr [[UCV]], align 1
17297 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT61]]
17298 // CHECK:       ucx.atomic.exit61:
17299 // CHECK-NEXT:    [[TMP673:%.*]] = load i8, ptr [[UCE]], align 1
17300 // CHECK-NEXT:    [[TMP674:%.*]] = load i8, ptr [[UCD]], align 1
17301 // CHECK-NEXT:    [[TMP675:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP673]], i8 [[TMP674]] acquire acquire, align 1
17302 // CHECK-NEXT:    [[TMP676:%.*]] = extractvalue { i8, i1 } [[TMP675]], 0
17303 // CHECK-NEXT:    [[TMP677:%.*]] = extractvalue { i8, i1 } [[TMP675]], 1
17304 // CHECK-NEXT:    br i1 [[TMP677]], label [[UCX_ATOMIC_EXIT63:%.*]], label [[UCX_ATOMIC_CONT64:%.*]]
17305 // CHECK:       ucx.atomic.cont64:
17306 // CHECK-NEXT:    store i8 [[TMP676]], ptr [[UCV]], align 1
17307 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT63]]
17308 // CHECK:       ucx.atomic.exit63:
17309 // CHECK-NEXT:    [[TMP678:%.*]] = load i8, ptr [[UCE]], align 1
17310 // CHECK-NEXT:    [[TMP679:%.*]] = load i8, ptr [[UCD]], align 1
17311 // CHECK-NEXT:    [[TMP680:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP678]], i8 [[TMP679]] acquire acquire, align 1
17312 // CHECK-NEXT:    [[TMP681:%.*]] = extractvalue { i8, i1 } [[TMP680]], 1
17313 // CHECK-NEXT:    [[TMP682:%.*]] = zext i1 [[TMP681]] to i8
17314 // CHECK-NEXT:    store i8 [[TMP682]], ptr [[UCR]], align 1
17315 // CHECK-NEXT:    [[TMP683:%.*]] = load i8, ptr [[UCE]], align 1
17316 // CHECK-NEXT:    [[TMP684:%.*]] = load i8, ptr [[UCD]], align 1
17317 // CHECK-NEXT:    [[TMP685:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP683]], i8 [[TMP684]] acquire acquire, align 1
17318 // CHECK-NEXT:    [[TMP686:%.*]] = extractvalue { i8, i1 } [[TMP685]], 1
17319 // CHECK-NEXT:    [[TMP687:%.*]] = zext i1 [[TMP686]] to i8
17320 // CHECK-NEXT:    store i8 [[TMP687]], ptr [[UCR]], align 1
17321 // CHECK-NEXT:    [[TMP688:%.*]] = load i8, ptr [[UCE]], align 1
17322 // CHECK-NEXT:    [[TMP689:%.*]] = load i8, ptr [[UCD]], align 1
17323 // CHECK-NEXT:    [[TMP690:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP688]], i8 [[TMP689]] acquire acquire, align 1
17324 // CHECK-NEXT:    [[TMP691:%.*]] = extractvalue { i8, i1 } [[TMP690]], 0
17325 // CHECK-NEXT:    [[TMP692:%.*]] = extractvalue { i8, i1 } [[TMP690]], 1
17326 // CHECK-NEXT:    br i1 [[TMP692]], label [[UCX_ATOMIC_EXIT65:%.*]], label [[UCX_ATOMIC_CONT66:%.*]]
17327 // CHECK:       ucx.atomic.cont66:
17328 // CHECK-NEXT:    store i8 [[TMP691]], ptr [[UCV]], align 1
17329 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT65]]
17330 // CHECK:       ucx.atomic.exit65:
17331 // CHECK-NEXT:    [[TMP693:%.*]] = extractvalue { i8, i1 } [[TMP690]], 1
17332 // CHECK-NEXT:    [[TMP694:%.*]] = zext i1 [[TMP693]] to i8
17333 // CHECK-NEXT:    store i8 [[TMP694]], ptr [[UCR]], align 1
17334 // CHECK-NEXT:    [[TMP695:%.*]] = load i8, ptr [[UCE]], align 1
17335 // CHECK-NEXT:    [[TMP696:%.*]] = load i8, ptr [[UCD]], align 1
17336 // CHECK-NEXT:    [[TMP697:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP695]], i8 [[TMP696]] acquire acquire, align 1
17337 // CHECK-NEXT:    [[TMP698:%.*]] = extractvalue { i8, i1 } [[TMP697]], 0
17338 // CHECK-NEXT:    [[TMP699:%.*]] = extractvalue { i8, i1 } [[TMP697]], 1
17339 // CHECK-NEXT:    br i1 [[TMP699]], label [[UCX_ATOMIC_EXIT67:%.*]], label [[UCX_ATOMIC_CONT68:%.*]]
17340 // CHECK:       ucx.atomic.cont68:
17341 // CHECK-NEXT:    store i8 [[TMP698]], ptr [[UCV]], align 1
17342 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT67]]
17343 // CHECK:       ucx.atomic.exit67:
17344 // CHECK-NEXT:    [[TMP700:%.*]] = extractvalue { i8, i1 } [[TMP697]], 1
17345 // CHECK-NEXT:    [[TMP701:%.*]] = zext i1 [[TMP700]] to i8
17346 // CHECK-NEXT:    store i8 [[TMP701]], ptr [[UCR]], align 1
17347 // CHECK-NEXT:    [[TMP702:%.*]] = load i8, ptr [[UCE]], align 1
17348 // CHECK-NEXT:    [[TMP703:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP702]] monotonic, align 1
17349 // CHECK-NEXT:    store i8 [[TMP703]], ptr [[UCV]], align 1
17350 // CHECK-NEXT:    [[TMP704:%.*]] = load i8, ptr [[UCE]], align 1
17351 // CHECK-NEXT:    [[TMP705:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP704]] monotonic, align 1
17352 // CHECK-NEXT:    store i8 [[TMP705]], ptr [[UCV]], align 1
17353 // CHECK-NEXT:    [[TMP706:%.*]] = load i8, ptr [[UCE]], align 1
17354 // CHECK-NEXT:    [[TMP707:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP706]] monotonic, align 1
17355 // CHECK-NEXT:    store i8 [[TMP707]], ptr [[UCV]], align 1
17356 // CHECK-NEXT:    [[TMP708:%.*]] = load i8, ptr [[UCE]], align 1
17357 // CHECK-NEXT:    [[TMP709:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP708]] monotonic, align 1
17358 // CHECK-NEXT:    store i8 [[TMP709]], ptr [[UCV]], align 1
17359 // CHECK-NEXT:    [[TMP710:%.*]] = load i8, ptr [[UCE]], align 1
17360 // CHECK-NEXT:    [[TMP711:%.*]] = load i8, ptr [[UCD]], align 1
17361 // CHECK-NEXT:    [[TMP712:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP710]], i8 [[TMP711]] monotonic monotonic, align 1
17362 // CHECK-NEXT:    [[TMP713:%.*]] = extractvalue { i8, i1 } [[TMP712]], 0
17363 // CHECK-NEXT:    store i8 [[TMP713]], ptr [[UCV]], align 1
17364 // CHECK-NEXT:    [[TMP714:%.*]] = load i8, ptr [[UCE]], align 1
17365 // CHECK-NEXT:    [[TMP715:%.*]] = load i8, ptr [[UCD]], align 1
17366 // CHECK-NEXT:    [[TMP716:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP714]], i8 [[TMP715]] monotonic monotonic, align 1
17367 // CHECK-NEXT:    [[TMP717:%.*]] = extractvalue { i8, i1 } [[TMP716]], 0
17368 // CHECK-NEXT:    store i8 [[TMP717]], ptr [[UCV]], align 1
17369 // CHECK-NEXT:    [[TMP718:%.*]] = load i8, ptr [[UCE]], align 1
17370 // CHECK-NEXT:    [[TMP719:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP718]] monotonic, align 1
17371 // CHECK-NEXT:    [[TMP720:%.*]] = icmp ugt i8 [[TMP719]], [[TMP718]]
17372 // CHECK-NEXT:    [[TMP721:%.*]] = select i1 [[TMP720]], i8 [[TMP718]], i8 [[TMP719]]
17373 // CHECK-NEXT:    store i8 [[TMP721]], ptr [[UCV]], align 1
17374 // CHECK-NEXT:    [[TMP722:%.*]] = load i8, ptr [[UCE]], align 1
17375 // CHECK-NEXT:    [[TMP723:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP722]] monotonic, align 1
17376 // CHECK-NEXT:    [[TMP724:%.*]] = icmp ult i8 [[TMP723]], [[TMP722]]
17377 // CHECK-NEXT:    [[TMP725:%.*]] = select i1 [[TMP724]], i8 [[TMP722]], i8 [[TMP723]]
17378 // CHECK-NEXT:    store i8 [[TMP725]], ptr [[UCV]], align 1
17379 // CHECK-NEXT:    [[TMP726:%.*]] = load i8, ptr [[UCE]], align 1
17380 // CHECK-NEXT:    [[TMP727:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP726]] monotonic, align 1
17381 // CHECK-NEXT:    [[TMP728:%.*]] = icmp ult i8 [[TMP727]], [[TMP726]]
17382 // CHECK-NEXT:    [[TMP729:%.*]] = select i1 [[TMP728]], i8 [[TMP726]], i8 [[TMP727]]
17383 // CHECK-NEXT:    store i8 [[TMP729]], ptr [[UCV]], align 1
17384 // CHECK-NEXT:    [[TMP730:%.*]] = load i8, ptr [[UCE]], align 1
17385 // CHECK-NEXT:    [[TMP731:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP730]] monotonic, align 1
17386 // CHECK-NEXT:    [[TMP732:%.*]] = icmp ugt i8 [[TMP731]], [[TMP730]]
17387 // CHECK-NEXT:    [[TMP733:%.*]] = select i1 [[TMP732]], i8 [[TMP730]], i8 [[TMP731]]
17388 // CHECK-NEXT:    store i8 [[TMP733]], ptr [[UCV]], align 1
17389 // CHECK-NEXT:    [[TMP734:%.*]] = load i8, ptr [[UCE]], align 1
17390 // CHECK-NEXT:    [[TMP735:%.*]] = load i8, ptr [[UCD]], align 1
17391 // CHECK-NEXT:    [[TMP736:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP734]], i8 [[TMP735]] monotonic monotonic, align 1
17392 // CHECK-NEXT:    [[TMP737:%.*]] = extractvalue { i8, i1 } [[TMP736]], 0
17393 // CHECK-NEXT:    [[TMP738:%.*]] = extractvalue { i8, i1 } [[TMP736]], 1
17394 // CHECK-NEXT:    [[TMP739:%.*]] = select i1 [[TMP738]], i8 [[TMP734]], i8 [[TMP737]]
17395 // CHECK-NEXT:    store i8 [[TMP739]], ptr [[UCV]], align 1
17396 // CHECK-NEXT:    [[TMP740:%.*]] = load i8, ptr [[UCE]], align 1
17397 // CHECK-NEXT:    [[TMP741:%.*]] = load i8, ptr [[UCD]], align 1
17398 // CHECK-NEXT:    [[TMP742:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP740]], i8 [[TMP741]] monotonic monotonic, align 1
17399 // CHECK-NEXT:    [[TMP743:%.*]] = extractvalue { i8, i1 } [[TMP742]], 0
17400 // CHECK-NEXT:    [[TMP744:%.*]] = extractvalue { i8, i1 } [[TMP742]], 1
17401 // CHECK-NEXT:    [[TMP745:%.*]] = select i1 [[TMP744]], i8 [[TMP740]], i8 [[TMP743]]
17402 // CHECK-NEXT:    store i8 [[TMP745]], ptr [[UCV]], align 1
17403 // CHECK-NEXT:    [[TMP746:%.*]] = load i8, ptr [[UCE]], align 1
17404 // CHECK-NEXT:    [[TMP747:%.*]] = load i8, ptr [[UCD]], align 1
17405 // CHECK-NEXT:    [[TMP748:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP746]], i8 [[TMP747]] monotonic monotonic, align 1
17406 // CHECK-NEXT:    [[TMP749:%.*]] = extractvalue { i8, i1 } [[TMP748]], 0
17407 // CHECK-NEXT:    [[TMP750:%.*]] = extractvalue { i8, i1 } [[TMP748]], 1
17408 // CHECK-NEXT:    br i1 [[TMP750]], label [[UCX_ATOMIC_EXIT69:%.*]], label [[UCX_ATOMIC_CONT70:%.*]]
17409 // CHECK:       ucx.atomic.cont70:
17410 // CHECK-NEXT:    store i8 [[TMP749]], ptr [[UCV]], align 1
17411 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT69]]
17412 // CHECK:       ucx.atomic.exit69:
17413 // CHECK-NEXT:    [[TMP751:%.*]] = load i8, ptr [[UCE]], align 1
17414 // CHECK-NEXT:    [[TMP752:%.*]] = load i8, ptr [[UCD]], align 1
17415 // CHECK-NEXT:    [[TMP753:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP751]], i8 [[TMP752]] monotonic monotonic, align 1
17416 // CHECK-NEXT:    [[TMP754:%.*]] = extractvalue { i8, i1 } [[TMP753]], 0
17417 // CHECK-NEXT:    [[TMP755:%.*]] = extractvalue { i8, i1 } [[TMP753]], 1
17418 // CHECK-NEXT:    br i1 [[TMP755]], label [[UCX_ATOMIC_EXIT71:%.*]], label [[UCX_ATOMIC_CONT72:%.*]]
17419 // CHECK:       ucx.atomic.cont72:
17420 // CHECK-NEXT:    store i8 [[TMP754]], ptr [[UCV]], align 1
17421 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT71]]
17422 // CHECK:       ucx.atomic.exit71:
17423 // CHECK-NEXT:    [[TMP756:%.*]] = load i8, ptr [[UCE]], align 1
17424 // CHECK-NEXT:    [[TMP757:%.*]] = load i8, ptr [[UCD]], align 1
17425 // CHECK-NEXT:    [[TMP758:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP756]], i8 [[TMP757]] monotonic monotonic, align 1
17426 // CHECK-NEXT:    [[TMP759:%.*]] = extractvalue { i8, i1 } [[TMP758]], 1
17427 // CHECK-NEXT:    [[TMP760:%.*]] = zext i1 [[TMP759]] to i8
17428 // CHECK-NEXT:    store i8 [[TMP760]], ptr [[UCR]], align 1
17429 // CHECK-NEXT:    [[TMP761:%.*]] = load i8, ptr [[UCE]], align 1
17430 // CHECK-NEXT:    [[TMP762:%.*]] = load i8, ptr [[UCD]], align 1
17431 // CHECK-NEXT:    [[TMP763:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP761]], i8 [[TMP762]] monotonic monotonic, align 1
17432 // CHECK-NEXT:    [[TMP764:%.*]] = extractvalue { i8, i1 } [[TMP763]], 1
17433 // CHECK-NEXT:    [[TMP765:%.*]] = zext i1 [[TMP764]] to i8
17434 // CHECK-NEXT:    store i8 [[TMP765]], ptr [[UCR]], align 1
17435 // CHECK-NEXT:    [[TMP766:%.*]] = load i8, ptr [[UCE]], align 1
17436 // CHECK-NEXT:    [[TMP767:%.*]] = load i8, ptr [[UCD]], align 1
17437 // CHECK-NEXT:    [[TMP768:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP766]], i8 [[TMP767]] monotonic monotonic, align 1
17438 // CHECK-NEXT:    [[TMP769:%.*]] = extractvalue { i8, i1 } [[TMP768]], 0
17439 // CHECK-NEXT:    [[TMP770:%.*]] = extractvalue { i8, i1 } [[TMP768]], 1
17440 // CHECK-NEXT:    br i1 [[TMP770]], label [[UCX_ATOMIC_EXIT73:%.*]], label [[UCX_ATOMIC_CONT74:%.*]]
17441 // CHECK:       ucx.atomic.cont74:
17442 // CHECK-NEXT:    store i8 [[TMP769]], ptr [[UCV]], align 1
17443 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT73]]
17444 // CHECK:       ucx.atomic.exit73:
17445 // CHECK-NEXT:    [[TMP771:%.*]] = extractvalue { i8, i1 } [[TMP768]], 1
17446 // CHECK-NEXT:    [[TMP772:%.*]] = zext i1 [[TMP771]] to i8
17447 // CHECK-NEXT:    store i8 [[TMP772]], ptr [[UCR]], align 1
17448 // CHECK-NEXT:    [[TMP773:%.*]] = load i8, ptr [[UCE]], align 1
17449 // CHECK-NEXT:    [[TMP774:%.*]] = load i8, ptr [[UCD]], align 1
17450 // CHECK-NEXT:    [[TMP775:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP773]], i8 [[TMP774]] monotonic monotonic, align 1
17451 // CHECK-NEXT:    [[TMP776:%.*]] = extractvalue { i8, i1 } [[TMP775]], 0
17452 // CHECK-NEXT:    [[TMP777:%.*]] = extractvalue { i8, i1 } [[TMP775]], 1
17453 // CHECK-NEXT:    br i1 [[TMP777]], label [[UCX_ATOMIC_EXIT75:%.*]], label [[UCX_ATOMIC_CONT76:%.*]]
17454 // CHECK:       ucx.atomic.cont76:
17455 // CHECK-NEXT:    store i8 [[TMP776]], ptr [[UCV]], align 1
17456 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT75]]
17457 // CHECK:       ucx.atomic.exit75:
17458 // CHECK-NEXT:    [[TMP778:%.*]] = extractvalue { i8, i1 } [[TMP775]], 1
17459 // CHECK-NEXT:    [[TMP779:%.*]] = zext i1 [[TMP778]] to i8
17460 // CHECK-NEXT:    store i8 [[TMP779]], ptr [[UCR]], align 1
17461 // CHECK-NEXT:    [[TMP780:%.*]] = load i8, ptr [[UCE]], align 1
17462 // CHECK-NEXT:    [[TMP781:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP780]] release, align 1
17463 // CHECK-NEXT:    store i8 [[TMP781]], ptr [[UCV]], align 1
17464 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17465 // CHECK-NEXT:    [[TMP782:%.*]] = load i8, ptr [[UCE]], align 1
17466 // CHECK-NEXT:    [[TMP783:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP782]] release, align 1
17467 // CHECK-NEXT:    store i8 [[TMP783]], ptr [[UCV]], align 1
17468 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17469 // CHECK-NEXT:    [[TMP784:%.*]] = load i8, ptr [[UCE]], align 1
17470 // CHECK-NEXT:    [[TMP785:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP784]] release, align 1
17471 // CHECK-NEXT:    store i8 [[TMP785]], ptr [[UCV]], align 1
17472 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17473 // CHECK-NEXT:    [[TMP786:%.*]] = load i8, ptr [[UCE]], align 1
17474 // CHECK-NEXT:    [[TMP787:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP786]] release, align 1
17475 // CHECK-NEXT:    store i8 [[TMP787]], ptr [[UCV]], align 1
17476 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17477 // CHECK-NEXT:    [[TMP788:%.*]] = load i8, ptr [[UCE]], align 1
17478 // CHECK-NEXT:    [[TMP789:%.*]] = load i8, ptr [[UCD]], align 1
17479 // CHECK-NEXT:    [[TMP790:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP788]], i8 [[TMP789]] release monotonic, align 1
17480 // CHECK-NEXT:    [[TMP791:%.*]] = extractvalue { i8, i1 } [[TMP790]], 0
17481 // CHECK-NEXT:    store i8 [[TMP791]], ptr [[UCV]], align 1
17482 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17483 // CHECK-NEXT:    [[TMP792:%.*]] = load i8, ptr [[UCE]], align 1
17484 // CHECK-NEXT:    [[TMP793:%.*]] = load i8, ptr [[UCD]], align 1
17485 // CHECK-NEXT:    [[TMP794:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP792]], i8 [[TMP793]] release monotonic, align 1
17486 // CHECK-NEXT:    [[TMP795:%.*]] = extractvalue { i8, i1 } [[TMP794]], 0
17487 // CHECK-NEXT:    store i8 [[TMP795]], ptr [[UCV]], align 1
17488 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17489 // CHECK-NEXT:    [[TMP796:%.*]] = load i8, ptr [[UCE]], align 1
17490 // CHECK-NEXT:    [[TMP797:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP796]] release, align 1
17491 // CHECK-NEXT:    [[TMP798:%.*]] = icmp ugt i8 [[TMP797]], [[TMP796]]
17492 // CHECK-NEXT:    [[TMP799:%.*]] = select i1 [[TMP798]], i8 [[TMP796]], i8 [[TMP797]]
17493 // CHECK-NEXT:    store i8 [[TMP799]], ptr [[UCV]], align 1
17494 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17495 // CHECK-NEXT:    [[TMP800:%.*]] = load i8, ptr [[UCE]], align 1
17496 // CHECK-NEXT:    [[TMP801:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP800]] release, align 1
17497 // CHECK-NEXT:    [[TMP802:%.*]] = icmp ult i8 [[TMP801]], [[TMP800]]
17498 // CHECK-NEXT:    [[TMP803:%.*]] = select i1 [[TMP802]], i8 [[TMP800]], i8 [[TMP801]]
17499 // CHECK-NEXT:    store i8 [[TMP803]], ptr [[UCV]], align 1
17500 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17501 // CHECK-NEXT:    [[TMP804:%.*]] = load i8, ptr [[UCE]], align 1
17502 // CHECK-NEXT:    [[TMP805:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP804]] release, align 1
17503 // CHECK-NEXT:    [[TMP806:%.*]] = icmp ult i8 [[TMP805]], [[TMP804]]
17504 // CHECK-NEXT:    [[TMP807:%.*]] = select i1 [[TMP806]], i8 [[TMP804]], i8 [[TMP805]]
17505 // CHECK-NEXT:    store i8 [[TMP807]], ptr [[UCV]], align 1
17506 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17507 // CHECK-NEXT:    [[TMP808:%.*]] = load i8, ptr [[UCE]], align 1
17508 // CHECK-NEXT:    [[TMP809:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP808]] release, align 1
17509 // CHECK-NEXT:    [[TMP810:%.*]] = icmp ugt i8 [[TMP809]], [[TMP808]]
17510 // CHECK-NEXT:    [[TMP811:%.*]] = select i1 [[TMP810]], i8 [[TMP808]], i8 [[TMP809]]
17511 // CHECK-NEXT:    store i8 [[TMP811]], ptr [[UCV]], align 1
17512 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17513 // CHECK-NEXT:    [[TMP812:%.*]] = load i8, ptr [[UCE]], align 1
17514 // CHECK-NEXT:    [[TMP813:%.*]] = load i8, ptr [[UCD]], align 1
17515 // CHECK-NEXT:    [[TMP814:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP812]], i8 [[TMP813]] release monotonic, align 1
17516 // CHECK-NEXT:    [[TMP815:%.*]] = extractvalue { i8, i1 } [[TMP814]], 0
17517 // CHECK-NEXT:    [[TMP816:%.*]] = extractvalue { i8, i1 } [[TMP814]], 1
17518 // CHECK-NEXT:    [[TMP817:%.*]] = select i1 [[TMP816]], i8 [[TMP812]], i8 [[TMP815]]
17519 // CHECK-NEXT:    store i8 [[TMP817]], ptr [[UCV]], align 1
17520 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17521 // CHECK-NEXT:    [[TMP818:%.*]] = load i8, ptr [[UCE]], align 1
17522 // CHECK-NEXT:    [[TMP819:%.*]] = load i8, ptr [[UCD]], align 1
17523 // CHECK-NEXT:    [[TMP820:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP818]], i8 [[TMP819]] release monotonic, align 1
17524 // CHECK-NEXT:    [[TMP821:%.*]] = extractvalue { i8, i1 } [[TMP820]], 0
17525 // CHECK-NEXT:    [[TMP822:%.*]] = extractvalue { i8, i1 } [[TMP820]], 1
17526 // CHECK-NEXT:    [[TMP823:%.*]] = select i1 [[TMP822]], i8 [[TMP818]], i8 [[TMP821]]
17527 // CHECK-NEXT:    store i8 [[TMP823]], ptr [[UCV]], align 1
17528 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17529 // CHECK-NEXT:    [[TMP824:%.*]] = load i8, ptr [[UCE]], align 1
17530 // CHECK-NEXT:    [[TMP825:%.*]] = load i8, ptr [[UCD]], align 1
17531 // CHECK-NEXT:    [[TMP826:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP824]], i8 [[TMP825]] release monotonic, align 1
17532 // CHECK-NEXT:    [[TMP827:%.*]] = extractvalue { i8, i1 } [[TMP826]], 0
17533 // CHECK-NEXT:    [[TMP828:%.*]] = extractvalue { i8, i1 } [[TMP826]], 1
17534 // CHECK-NEXT:    br i1 [[TMP828]], label [[UCX_ATOMIC_EXIT77:%.*]], label [[UCX_ATOMIC_CONT78:%.*]]
17535 // CHECK:       ucx.atomic.cont78:
17536 // CHECK-NEXT:    store i8 [[TMP827]], ptr [[UCV]], align 1
17537 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT77]]
17538 // CHECK:       ucx.atomic.exit77:
17539 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17540 // CHECK-NEXT:    [[TMP829:%.*]] = load i8, ptr [[UCE]], align 1
17541 // CHECK-NEXT:    [[TMP830:%.*]] = load i8, ptr [[UCD]], align 1
17542 // CHECK-NEXT:    [[TMP831:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP829]], i8 [[TMP830]] release monotonic, align 1
17543 // CHECK-NEXT:    [[TMP832:%.*]] = extractvalue { i8, i1 } [[TMP831]], 0
17544 // CHECK-NEXT:    [[TMP833:%.*]] = extractvalue { i8, i1 } [[TMP831]], 1
17545 // CHECK-NEXT:    br i1 [[TMP833]], label [[UCX_ATOMIC_EXIT79:%.*]], label [[UCX_ATOMIC_CONT80:%.*]]
17546 // CHECK:       ucx.atomic.cont80:
17547 // CHECK-NEXT:    store i8 [[TMP832]], ptr [[UCV]], align 1
17548 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT79]]
17549 // CHECK:       ucx.atomic.exit79:
17550 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17551 // CHECK-NEXT:    [[TMP834:%.*]] = load i8, ptr [[UCE]], align 1
17552 // CHECK-NEXT:    [[TMP835:%.*]] = load i8, ptr [[UCD]], align 1
17553 // CHECK-NEXT:    [[TMP836:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP834]], i8 [[TMP835]] release monotonic, align 1
17554 // CHECK-NEXT:    [[TMP837:%.*]] = extractvalue { i8, i1 } [[TMP836]], 1
17555 // CHECK-NEXT:    [[TMP838:%.*]] = zext i1 [[TMP837]] to i8
17556 // CHECK-NEXT:    store i8 [[TMP838]], ptr [[UCR]], align 1
17557 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17558 // CHECK-NEXT:    [[TMP839:%.*]] = load i8, ptr [[UCE]], align 1
17559 // CHECK-NEXT:    [[TMP840:%.*]] = load i8, ptr [[UCD]], align 1
17560 // CHECK-NEXT:    [[TMP841:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP839]], i8 [[TMP840]] release monotonic, align 1
17561 // CHECK-NEXT:    [[TMP842:%.*]] = extractvalue { i8, i1 } [[TMP841]], 1
17562 // CHECK-NEXT:    [[TMP843:%.*]] = zext i1 [[TMP842]] to i8
17563 // CHECK-NEXT:    store i8 [[TMP843]], ptr [[UCR]], align 1
17564 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17565 // CHECK-NEXT:    [[TMP844:%.*]] = load i8, ptr [[UCE]], align 1
17566 // CHECK-NEXT:    [[TMP845:%.*]] = load i8, ptr [[UCD]], align 1
17567 // CHECK-NEXT:    [[TMP846:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP844]], i8 [[TMP845]] release monotonic, align 1
17568 // CHECK-NEXT:    [[TMP847:%.*]] = extractvalue { i8, i1 } [[TMP846]], 0
17569 // CHECK-NEXT:    [[TMP848:%.*]] = extractvalue { i8, i1 } [[TMP846]], 1
17570 // CHECK-NEXT:    br i1 [[TMP848]], label [[UCX_ATOMIC_EXIT81:%.*]], label [[UCX_ATOMIC_CONT82:%.*]]
17571 // CHECK:       ucx.atomic.cont82:
17572 // CHECK-NEXT:    store i8 [[TMP847]], ptr [[UCV]], align 1
17573 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT81]]
17574 // CHECK:       ucx.atomic.exit81:
17575 // CHECK-NEXT:    [[TMP849:%.*]] = extractvalue { i8, i1 } [[TMP846]], 1
17576 // CHECK-NEXT:    [[TMP850:%.*]] = zext i1 [[TMP849]] to i8
17577 // CHECK-NEXT:    store i8 [[TMP850]], ptr [[UCR]], align 1
17578 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17579 // CHECK-NEXT:    [[TMP851:%.*]] = load i8, ptr [[UCE]], align 1
17580 // CHECK-NEXT:    [[TMP852:%.*]] = load i8, ptr [[UCD]], align 1
17581 // CHECK-NEXT:    [[TMP853:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP851]], i8 [[TMP852]] release monotonic, align 1
17582 // CHECK-NEXT:    [[TMP854:%.*]] = extractvalue { i8, i1 } [[TMP853]], 0
17583 // CHECK-NEXT:    [[TMP855:%.*]] = extractvalue { i8, i1 } [[TMP853]], 1
17584 // CHECK-NEXT:    br i1 [[TMP855]], label [[UCX_ATOMIC_EXIT83:%.*]], label [[UCX_ATOMIC_CONT84:%.*]]
17585 // CHECK:       ucx.atomic.cont84:
17586 // CHECK-NEXT:    store i8 [[TMP854]], ptr [[UCV]], align 1
17587 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT83]]
17588 // CHECK:       ucx.atomic.exit83:
17589 // CHECK-NEXT:    [[TMP856:%.*]] = extractvalue { i8, i1 } [[TMP853]], 1
17590 // CHECK-NEXT:    [[TMP857:%.*]] = zext i1 [[TMP856]] to i8
17591 // CHECK-NEXT:    store i8 [[TMP857]], ptr [[UCR]], align 1
17592 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17593 // CHECK-NEXT:    [[TMP858:%.*]] = load i8, ptr [[UCE]], align 1
17594 // CHECK-NEXT:    [[TMP859:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP858]] seq_cst, align 1
17595 // CHECK-NEXT:    store i8 [[TMP859]], ptr [[UCV]], align 1
17596 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17597 // CHECK-NEXT:    [[TMP860:%.*]] = load i8, ptr [[UCE]], align 1
17598 // CHECK-NEXT:    [[TMP861:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP860]] seq_cst, align 1
17599 // CHECK-NEXT:    store i8 [[TMP861]], ptr [[UCV]], align 1
17600 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17601 // CHECK-NEXT:    [[TMP862:%.*]] = load i8, ptr [[UCE]], align 1
17602 // CHECK-NEXT:    [[TMP863:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP862]] seq_cst, align 1
17603 // CHECK-NEXT:    store i8 [[TMP863]], ptr [[UCV]], align 1
17604 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17605 // CHECK-NEXT:    [[TMP864:%.*]] = load i8, ptr [[UCE]], align 1
17606 // CHECK-NEXT:    [[TMP865:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP864]] seq_cst, align 1
17607 // CHECK-NEXT:    store i8 [[TMP865]], ptr [[UCV]], align 1
17608 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17609 // CHECK-NEXT:    [[TMP866:%.*]] = load i8, ptr [[UCE]], align 1
17610 // CHECK-NEXT:    [[TMP867:%.*]] = load i8, ptr [[UCD]], align 1
17611 // CHECK-NEXT:    [[TMP868:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP866]], i8 [[TMP867]] seq_cst seq_cst, align 1
17612 // CHECK-NEXT:    [[TMP869:%.*]] = extractvalue { i8, i1 } [[TMP868]], 0
17613 // CHECK-NEXT:    store i8 [[TMP869]], ptr [[UCV]], align 1
17614 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17615 // CHECK-NEXT:    [[TMP870:%.*]] = load i8, ptr [[UCE]], align 1
17616 // CHECK-NEXT:    [[TMP871:%.*]] = load i8, ptr [[UCD]], align 1
17617 // CHECK-NEXT:    [[TMP872:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP870]], i8 [[TMP871]] seq_cst seq_cst, align 1
17618 // CHECK-NEXT:    [[TMP873:%.*]] = extractvalue { i8, i1 } [[TMP872]], 0
17619 // CHECK-NEXT:    store i8 [[TMP873]], ptr [[UCV]], align 1
17620 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17621 // CHECK-NEXT:    [[TMP874:%.*]] = load i8, ptr [[UCE]], align 1
17622 // CHECK-NEXT:    [[TMP875:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP874]] seq_cst, align 1
17623 // CHECK-NEXT:    [[TMP876:%.*]] = icmp ugt i8 [[TMP875]], [[TMP874]]
17624 // CHECK-NEXT:    [[TMP877:%.*]] = select i1 [[TMP876]], i8 [[TMP874]], i8 [[TMP875]]
17625 // CHECK-NEXT:    store i8 [[TMP877]], ptr [[UCV]], align 1
17626 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17627 // CHECK-NEXT:    [[TMP878:%.*]] = load i8, ptr [[UCE]], align 1
17628 // CHECK-NEXT:    [[TMP879:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP878]] seq_cst, align 1
17629 // CHECK-NEXT:    [[TMP880:%.*]] = icmp ult i8 [[TMP879]], [[TMP878]]
17630 // CHECK-NEXT:    [[TMP881:%.*]] = select i1 [[TMP880]], i8 [[TMP878]], i8 [[TMP879]]
17631 // CHECK-NEXT:    store i8 [[TMP881]], ptr [[UCV]], align 1
17632 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17633 // CHECK-NEXT:    [[TMP882:%.*]] = load i8, ptr [[UCE]], align 1
17634 // CHECK-NEXT:    [[TMP883:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP882]] seq_cst, align 1
17635 // CHECK-NEXT:    [[TMP884:%.*]] = icmp ult i8 [[TMP883]], [[TMP882]]
17636 // CHECK-NEXT:    [[TMP885:%.*]] = select i1 [[TMP884]], i8 [[TMP882]], i8 [[TMP883]]
17637 // CHECK-NEXT:    store i8 [[TMP885]], ptr [[UCV]], align 1
17638 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17639 // CHECK-NEXT:    [[TMP886:%.*]] = load i8, ptr [[UCE]], align 1
17640 // CHECK-NEXT:    [[TMP887:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP886]] seq_cst, align 1
17641 // CHECK-NEXT:    [[TMP888:%.*]] = icmp ugt i8 [[TMP887]], [[TMP886]]
17642 // CHECK-NEXT:    [[TMP889:%.*]] = select i1 [[TMP888]], i8 [[TMP886]], i8 [[TMP887]]
17643 // CHECK-NEXT:    store i8 [[TMP889]], ptr [[UCV]], align 1
17644 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17645 // CHECK-NEXT:    [[TMP890:%.*]] = load i8, ptr [[UCE]], align 1
17646 // CHECK-NEXT:    [[TMP891:%.*]] = load i8, ptr [[UCD]], align 1
17647 // CHECK-NEXT:    [[TMP892:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP890]], i8 [[TMP891]] seq_cst seq_cst, align 1
17648 // CHECK-NEXT:    [[TMP893:%.*]] = extractvalue { i8, i1 } [[TMP892]], 0
17649 // CHECK-NEXT:    [[TMP894:%.*]] = extractvalue { i8, i1 } [[TMP892]], 1
17650 // CHECK-NEXT:    [[TMP895:%.*]] = select i1 [[TMP894]], i8 [[TMP890]], i8 [[TMP893]]
17651 // CHECK-NEXT:    store i8 [[TMP895]], ptr [[UCV]], align 1
17652 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17653 // CHECK-NEXT:    [[TMP896:%.*]] = load i8, ptr [[UCE]], align 1
17654 // CHECK-NEXT:    [[TMP897:%.*]] = load i8, ptr [[UCD]], align 1
17655 // CHECK-NEXT:    [[TMP898:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP896]], i8 [[TMP897]] seq_cst seq_cst, align 1
17656 // CHECK-NEXT:    [[TMP899:%.*]] = extractvalue { i8, i1 } [[TMP898]], 0
17657 // CHECK-NEXT:    [[TMP900:%.*]] = extractvalue { i8, i1 } [[TMP898]], 1
17658 // CHECK-NEXT:    [[TMP901:%.*]] = select i1 [[TMP900]], i8 [[TMP896]], i8 [[TMP899]]
17659 // CHECK-NEXT:    store i8 [[TMP901]], ptr [[UCV]], align 1
17660 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17661 // CHECK-NEXT:    [[TMP902:%.*]] = load i8, ptr [[UCE]], align 1
17662 // CHECK-NEXT:    [[TMP903:%.*]] = load i8, ptr [[UCD]], align 1
17663 // CHECK-NEXT:    [[TMP904:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP902]], i8 [[TMP903]] seq_cst seq_cst, align 1
17664 // CHECK-NEXT:    [[TMP905:%.*]] = extractvalue { i8, i1 } [[TMP904]], 0
17665 // CHECK-NEXT:    [[TMP906:%.*]] = extractvalue { i8, i1 } [[TMP904]], 1
17666 // CHECK-NEXT:    br i1 [[TMP906]], label [[UCX_ATOMIC_EXIT85:%.*]], label [[UCX_ATOMIC_CONT86:%.*]]
17667 // CHECK:       ucx.atomic.cont86:
17668 // CHECK-NEXT:    store i8 [[TMP905]], ptr [[UCV]], align 1
17669 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT85]]
17670 // CHECK:       ucx.atomic.exit85:
17671 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17672 // CHECK-NEXT:    [[TMP907:%.*]] = load i8, ptr [[UCE]], align 1
17673 // CHECK-NEXT:    [[TMP908:%.*]] = load i8, ptr [[UCD]], align 1
17674 // CHECK-NEXT:    [[TMP909:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP907]], i8 [[TMP908]] seq_cst seq_cst, align 1
17675 // CHECK-NEXT:    [[TMP910:%.*]] = extractvalue { i8, i1 } [[TMP909]], 0
17676 // CHECK-NEXT:    [[TMP911:%.*]] = extractvalue { i8, i1 } [[TMP909]], 1
17677 // CHECK-NEXT:    br i1 [[TMP911]], label [[UCX_ATOMIC_EXIT87:%.*]], label [[UCX_ATOMIC_CONT88:%.*]]
17678 // CHECK:       ucx.atomic.cont88:
17679 // CHECK-NEXT:    store i8 [[TMP910]], ptr [[UCV]], align 1
17680 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT87]]
17681 // CHECK:       ucx.atomic.exit87:
17682 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17683 // CHECK-NEXT:    [[TMP912:%.*]] = load i8, ptr [[UCE]], align 1
17684 // CHECK-NEXT:    [[TMP913:%.*]] = load i8, ptr [[UCD]], align 1
17685 // CHECK-NEXT:    [[TMP914:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP912]], i8 [[TMP913]] seq_cst seq_cst, align 1
17686 // CHECK-NEXT:    [[TMP915:%.*]] = extractvalue { i8, i1 } [[TMP914]], 1
17687 // CHECK-NEXT:    [[TMP916:%.*]] = zext i1 [[TMP915]] to i8
17688 // CHECK-NEXT:    store i8 [[TMP916]], ptr [[UCR]], align 1
17689 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17690 // CHECK-NEXT:    [[TMP917:%.*]] = load i8, ptr [[UCE]], align 1
17691 // CHECK-NEXT:    [[TMP918:%.*]] = load i8, ptr [[UCD]], align 1
17692 // CHECK-NEXT:    [[TMP919:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP917]], i8 [[TMP918]] seq_cst seq_cst, align 1
17693 // CHECK-NEXT:    [[TMP920:%.*]] = extractvalue { i8, i1 } [[TMP919]], 1
17694 // CHECK-NEXT:    [[TMP921:%.*]] = zext i1 [[TMP920]] to i8
17695 // CHECK-NEXT:    store i8 [[TMP921]], ptr [[UCR]], align 1
17696 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17697 // CHECK-NEXT:    [[TMP922:%.*]] = load i8, ptr [[UCE]], align 1
17698 // CHECK-NEXT:    [[TMP923:%.*]] = load i8, ptr [[UCD]], align 1
17699 // CHECK-NEXT:    [[TMP924:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP922]], i8 [[TMP923]] seq_cst seq_cst, align 1
17700 // CHECK-NEXT:    [[TMP925:%.*]] = extractvalue { i8, i1 } [[TMP924]], 0
17701 // CHECK-NEXT:    [[TMP926:%.*]] = extractvalue { i8, i1 } [[TMP924]], 1
17702 // CHECK-NEXT:    br i1 [[TMP926]], label [[UCX_ATOMIC_EXIT89:%.*]], label [[UCX_ATOMIC_CONT90:%.*]]
17703 // CHECK:       ucx.atomic.cont90:
17704 // CHECK-NEXT:    store i8 [[TMP925]], ptr [[UCV]], align 1
17705 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT89]]
17706 // CHECK:       ucx.atomic.exit89:
17707 // CHECK-NEXT:    [[TMP927:%.*]] = extractvalue { i8, i1 } [[TMP924]], 1
17708 // CHECK-NEXT:    [[TMP928:%.*]] = zext i1 [[TMP927]] to i8
17709 // CHECK-NEXT:    store i8 [[TMP928]], ptr [[UCR]], align 1
17710 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17711 // CHECK-NEXT:    [[TMP929:%.*]] = load i8, ptr [[UCE]], align 1
17712 // CHECK-NEXT:    [[TMP930:%.*]] = load i8, ptr [[UCD]], align 1
17713 // CHECK-NEXT:    [[TMP931:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP929]], i8 [[TMP930]] seq_cst seq_cst, align 1
17714 // CHECK-NEXT:    [[TMP932:%.*]] = extractvalue { i8, i1 } [[TMP931]], 0
17715 // CHECK-NEXT:    [[TMP933:%.*]] = extractvalue { i8, i1 } [[TMP931]], 1
17716 // CHECK-NEXT:    br i1 [[TMP933]], label [[UCX_ATOMIC_EXIT91:%.*]], label [[UCX_ATOMIC_CONT92:%.*]]
17717 // CHECK:       ucx.atomic.cont92:
17718 // CHECK-NEXT:    store i8 [[TMP932]], ptr [[UCV]], align 1
17719 // CHECK-NEXT:    br label [[UCX_ATOMIC_EXIT91]]
17720 // CHECK:       ucx.atomic.exit91:
17721 // CHECK-NEXT:    [[TMP934:%.*]] = extractvalue { i8, i1 } [[TMP931]], 1
17722 // CHECK-NEXT:    [[TMP935:%.*]] = zext i1 [[TMP934]] to i8
17723 // CHECK-NEXT:    store i8 [[TMP935]], ptr [[UCR]], align 1
17724 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17725 // CHECK-NEXT:    [[TMP936:%.*]] = load i16, ptr [[SE]], align 2
17726 // CHECK-NEXT:    [[TMP937:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP936]] monotonic, align 2
17727 // CHECK-NEXT:    store i16 [[TMP937]], ptr [[SV]], align 2
17728 // CHECK-NEXT:    [[TMP938:%.*]] = load i16, ptr [[SE]], align 2
17729 // CHECK-NEXT:    [[TMP939:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP938]] monotonic, align 2
17730 // CHECK-NEXT:    store i16 [[TMP939]], ptr [[SV]], align 2
17731 // CHECK-NEXT:    [[TMP940:%.*]] = load i16, ptr [[SE]], align 2
17732 // CHECK-NEXT:    [[TMP941:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP940]] monotonic, align 2
17733 // CHECK-NEXT:    store i16 [[TMP941]], ptr [[SV]], align 2
17734 // CHECK-NEXT:    [[TMP942:%.*]] = load i16, ptr [[SE]], align 2
17735 // CHECK-NEXT:    [[TMP943:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP942]] monotonic, align 2
17736 // CHECK-NEXT:    store i16 [[TMP943]], ptr [[SV]], align 2
17737 // CHECK-NEXT:    [[TMP944:%.*]] = load i16, ptr [[SE]], align 2
17738 // CHECK-NEXT:    [[TMP945:%.*]] = load i16, ptr [[SD]], align 2
17739 // CHECK-NEXT:    [[TMP946:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP944]], i16 [[TMP945]] monotonic monotonic, align 2
17740 // CHECK-NEXT:    [[TMP947:%.*]] = extractvalue { i16, i1 } [[TMP946]], 0
17741 // CHECK-NEXT:    store i16 [[TMP947]], ptr [[SV]], align 2
17742 // CHECK-NEXT:    [[TMP948:%.*]] = load i16, ptr [[SE]], align 2
17743 // CHECK-NEXT:    [[TMP949:%.*]] = load i16, ptr [[SD]], align 2
17744 // CHECK-NEXT:    [[TMP950:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP948]], i16 [[TMP949]] monotonic monotonic, align 2
17745 // CHECK-NEXT:    [[TMP951:%.*]] = extractvalue { i16, i1 } [[TMP950]], 0
17746 // CHECK-NEXT:    store i16 [[TMP951]], ptr [[SV]], align 2
17747 // CHECK-NEXT:    [[TMP952:%.*]] = load i16, ptr [[SE]], align 2
17748 // CHECK-NEXT:    [[TMP953:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP952]] monotonic, align 2
17749 // CHECK-NEXT:    [[TMP954:%.*]] = icmp sgt i16 [[TMP953]], [[TMP952]]
17750 // CHECK-NEXT:    [[TMP955:%.*]] = select i1 [[TMP954]], i16 [[TMP952]], i16 [[TMP953]]
17751 // CHECK-NEXT:    store i16 [[TMP955]], ptr [[SV]], align 2
17752 // CHECK-NEXT:    [[TMP956:%.*]] = load i16, ptr [[SE]], align 2
17753 // CHECK-NEXT:    [[TMP957:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP956]] monotonic, align 2
17754 // CHECK-NEXT:    [[TMP958:%.*]] = icmp slt i16 [[TMP957]], [[TMP956]]
17755 // CHECK-NEXT:    [[TMP959:%.*]] = select i1 [[TMP958]], i16 [[TMP956]], i16 [[TMP957]]
17756 // CHECK-NEXT:    store i16 [[TMP959]], ptr [[SV]], align 2
17757 // CHECK-NEXT:    [[TMP960:%.*]] = load i16, ptr [[SE]], align 2
17758 // CHECK-NEXT:    [[TMP961:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP960]] monotonic, align 2
17759 // CHECK-NEXT:    [[TMP962:%.*]] = icmp slt i16 [[TMP961]], [[TMP960]]
17760 // CHECK-NEXT:    [[TMP963:%.*]] = select i1 [[TMP962]], i16 [[TMP960]], i16 [[TMP961]]
17761 // CHECK-NEXT:    store i16 [[TMP963]], ptr [[SV]], align 2
17762 // CHECK-NEXT:    [[TMP964:%.*]] = load i16, ptr [[SE]], align 2
17763 // CHECK-NEXT:    [[TMP965:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP964]] monotonic, align 2
17764 // CHECK-NEXT:    [[TMP966:%.*]] = icmp sgt i16 [[TMP965]], [[TMP964]]
17765 // CHECK-NEXT:    [[TMP967:%.*]] = select i1 [[TMP966]], i16 [[TMP964]], i16 [[TMP965]]
17766 // CHECK-NEXT:    store i16 [[TMP967]], ptr [[SV]], align 2
17767 // CHECK-NEXT:    [[TMP968:%.*]] = load i16, ptr [[SE]], align 2
17768 // CHECK-NEXT:    [[TMP969:%.*]] = load i16, ptr [[SD]], align 2
17769 // CHECK-NEXT:    [[TMP970:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP968]], i16 [[TMP969]] monotonic monotonic, align 2
17770 // CHECK-NEXT:    [[TMP971:%.*]] = extractvalue { i16, i1 } [[TMP970]], 0
17771 // CHECK-NEXT:    [[TMP972:%.*]] = extractvalue { i16, i1 } [[TMP970]], 1
17772 // CHECK-NEXT:    [[TMP973:%.*]] = select i1 [[TMP972]], i16 [[TMP968]], i16 [[TMP971]]
17773 // CHECK-NEXT:    store i16 [[TMP973]], ptr [[SV]], align 2
17774 // CHECK-NEXT:    [[TMP974:%.*]] = load i16, ptr [[SE]], align 2
17775 // CHECK-NEXT:    [[TMP975:%.*]] = load i16, ptr [[SD]], align 2
17776 // CHECK-NEXT:    [[TMP976:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP974]], i16 [[TMP975]] monotonic monotonic, align 2
17777 // CHECK-NEXT:    [[TMP977:%.*]] = extractvalue { i16, i1 } [[TMP976]], 0
17778 // CHECK-NEXT:    [[TMP978:%.*]] = extractvalue { i16, i1 } [[TMP976]], 1
17779 // CHECK-NEXT:    [[TMP979:%.*]] = select i1 [[TMP978]], i16 [[TMP974]], i16 [[TMP977]]
17780 // CHECK-NEXT:    store i16 [[TMP979]], ptr [[SV]], align 2
17781 // CHECK-NEXT:    [[TMP980:%.*]] = load i16, ptr [[SE]], align 2
17782 // CHECK-NEXT:    [[TMP981:%.*]] = load i16, ptr [[SD]], align 2
17783 // CHECK-NEXT:    [[TMP982:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP980]], i16 [[TMP981]] monotonic monotonic, align 2
17784 // CHECK-NEXT:    [[TMP983:%.*]] = extractvalue { i16, i1 } [[TMP982]], 0
17785 // CHECK-NEXT:    [[TMP984:%.*]] = extractvalue { i16, i1 } [[TMP982]], 1
17786 // CHECK-NEXT:    br i1 [[TMP984]], label [[SX_ATOMIC_EXIT:%.*]], label [[SX_ATOMIC_CONT:%.*]]
17787 // CHECK:       sx.atomic.cont:
17788 // CHECK-NEXT:    store i16 [[TMP983]], ptr [[SV]], align 2
17789 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT]]
17790 // CHECK:       sx.atomic.exit:
17791 // CHECK-NEXT:    [[TMP985:%.*]] = load i16, ptr [[SE]], align 2
17792 // CHECK-NEXT:    [[TMP986:%.*]] = load i16, ptr [[SD]], align 2
17793 // CHECK-NEXT:    [[TMP987:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP985]], i16 [[TMP986]] monotonic monotonic, align 2
17794 // CHECK-NEXT:    [[TMP988:%.*]] = extractvalue { i16, i1 } [[TMP987]], 0
17795 // CHECK-NEXT:    [[TMP989:%.*]] = extractvalue { i16, i1 } [[TMP987]], 1
17796 // CHECK-NEXT:    br i1 [[TMP989]], label [[SX_ATOMIC_EXIT93:%.*]], label [[SX_ATOMIC_CONT94:%.*]]
17797 // CHECK:       sx.atomic.cont94:
17798 // CHECK-NEXT:    store i16 [[TMP988]], ptr [[SV]], align 2
17799 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT93]]
17800 // CHECK:       sx.atomic.exit93:
17801 // CHECK-NEXT:    [[TMP990:%.*]] = load i16, ptr [[SE]], align 2
17802 // CHECK-NEXT:    [[TMP991:%.*]] = load i16, ptr [[SD]], align 2
17803 // CHECK-NEXT:    [[TMP992:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP990]], i16 [[TMP991]] monotonic monotonic, align 2
17804 // CHECK-NEXT:    [[TMP993:%.*]] = extractvalue { i16, i1 } [[TMP992]], 1
17805 // CHECK-NEXT:    [[TMP994:%.*]] = sext i1 [[TMP993]] to i16
17806 // CHECK-NEXT:    store i16 [[TMP994]], ptr [[SR]], align 2
17807 // CHECK-NEXT:    [[TMP995:%.*]] = load i16, ptr [[SE]], align 2
17808 // CHECK-NEXT:    [[TMP996:%.*]] = load i16, ptr [[SD]], align 2
17809 // CHECK-NEXT:    [[TMP997:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP995]], i16 [[TMP996]] monotonic monotonic, align 2
17810 // CHECK-NEXT:    [[TMP998:%.*]] = extractvalue { i16, i1 } [[TMP997]], 1
17811 // CHECK-NEXT:    [[TMP999:%.*]] = sext i1 [[TMP998]] to i16
17812 // CHECK-NEXT:    store i16 [[TMP999]], ptr [[SR]], align 2
17813 // CHECK-NEXT:    [[TMP1000:%.*]] = load i16, ptr [[SE]], align 2
17814 // CHECK-NEXT:    [[TMP1001:%.*]] = load i16, ptr [[SD]], align 2
17815 // CHECK-NEXT:    [[TMP1002:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1000]], i16 [[TMP1001]] monotonic monotonic, align 2
17816 // CHECK-NEXT:    [[TMP1003:%.*]] = extractvalue { i16, i1 } [[TMP1002]], 0
17817 // CHECK-NEXT:    [[TMP1004:%.*]] = extractvalue { i16, i1 } [[TMP1002]], 1
17818 // CHECK-NEXT:    br i1 [[TMP1004]], label [[SX_ATOMIC_EXIT95:%.*]], label [[SX_ATOMIC_CONT96:%.*]]
17819 // CHECK:       sx.atomic.cont96:
17820 // CHECK-NEXT:    store i16 [[TMP1003]], ptr [[SV]], align 2
17821 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT95]]
17822 // CHECK:       sx.atomic.exit95:
17823 // CHECK-NEXT:    [[TMP1005:%.*]] = extractvalue { i16, i1 } [[TMP1002]], 1
17824 // CHECK-NEXT:    [[TMP1006:%.*]] = sext i1 [[TMP1005]] to i16
17825 // CHECK-NEXT:    store i16 [[TMP1006]], ptr [[SR]], align 2
17826 // CHECK-NEXT:    [[TMP1007:%.*]] = load i16, ptr [[SE]], align 2
17827 // CHECK-NEXT:    [[TMP1008:%.*]] = load i16, ptr [[SD]], align 2
17828 // CHECK-NEXT:    [[TMP1009:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1007]], i16 [[TMP1008]] monotonic monotonic, align 2
17829 // CHECK-NEXT:    [[TMP1010:%.*]] = extractvalue { i16, i1 } [[TMP1009]], 0
17830 // CHECK-NEXT:    [[TMP1011:%.*]] = extractvalue { i16, i1 } [[TMP1009]], 1
17831 // CHECK-NEXT:    br i1 [[TMP1011]], label [[SX_ATOMIC_EXIT97:%.*]], label [[SX_ATOMIC_CONT98:%.*]]
17832 // CHECK:       sx.atomic.cont98:
17833 // CHECK-NEXT:    store i16 [[TMP1010]], ptr [[SV]], align 2
17834 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT97]]
17835 // CHECK:       sx.atomic.exit97:
17836 // CHECK-NEXT:    [[TMP1012:%.*]] = extractvalue { i16, i1 } [[TMP1009]], 1
17837 // CHECK-NEXT:    [[TMP1013:%.*]] = sext i1 [[TMP1012]] to i16
17838 // CHECK-NEXT:    store i16 [[TMP1013]], ptr [[SR]], align 2
17839 // CHECK-NEXT:    [[TMP1014:%.*]] = load i16, ptr [[SE]], align 2
17840 // CHECK-NEXT:    [[TMP1015:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1014]] acq_rel, align 2
17841 // CHECK-NEXT:    store i16 [[TMP1015]], ptr [[SV]], align 2
17842 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17843 // CHECK-NEXT:    [[TMP1016:%.*]] = load i16, ptr [[SE]], align 2
17844 // CHECK-NEXT:    [[TMP1017:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1016]] acq_rel, align 2
17845 // CHECK-NEXT:    store i16 [[TMP1017]], ptr [[SV]], align 2
17846 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17847 // CHECK-NEXT:    [[TMP1018:%.*]] = load i16, ptr [[SE]], align 2
17848 // CHECK-NEXT:    [[TMP1019:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1018]] acq_rel, align 2
17849 // CHECK-NEXT:    store i16 [[TMP1019]], ptr [[SV]], align 2
17850 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17851 // CHECK-NEXT:    [[TMP1020:%.*]] = load i16, ptr [[SE]], align 2
17852 // CHECK-NEXT:    [[TMP1021:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1020]] acq_rel, align 2
17853 // CHECK-NEXT:    store i16 [[TMP1021]], ptr [[SV]], align 2
17854 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17855 // CHECK-NEXT:    [[TMP1022:%.*]] = load i16, ptr [[SE]], align 2
17856 // CHECK-NEXT:    [[TMP1023:%.*]] = load i16, ptr [[SD]], align 2
17857 // CHECK-NEXT:    [[TMP1024:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1022]], i16 [[TMP1023]] acq_rel acquire, align 2
17858 // CHECK-NEXT:    [[TMP1025:%.*]] = extractvalue { i16, i1 } [[TMP1024]], 0
17859 // CHECK-NEXT:    store i16 [[TMP1025]], ptr [[SV]], align 2
17860 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17861 // CHECK-NEXT:    [[TMP1026:%.*]] = load i16, ptr [[SE]], align 2
17862 // CHECK-NEXT:    [[TMP1027:%.*]] = load i16, ptr [[SD]], align 2
17863 // CHECK-NEXT:    [[TMP1028:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1026]], i16 [[TMP1027]] acq_rel acquire, align 2
17864 // CHECK-NEXT:    [[TMP1029:%.*]] = extractvalue { i16, i1 } [[TMP1028]], 0
17865 // CHECK-NEXT:    store i16 [[TMP1029]], ptr [[SV]], align 2
17866 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17867 // CHECK-NEXT:    [[TMP1030:%.*]] = load i16, ptr [[SE]], align 2
17868 // CHECK-NEXT:    [[TMP1031:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1030]] acq_rel, align 2
17869 // CHECK-NEXT:    [[TMP1032:%.*]] = icmp sgt i16 [[TMP1031]], [[TMP1030]]
17870 // CHECK-NEXT:    [[TMP1033:%.*]] = select i1 [[TMP1032]], i16 [[TMP1030]], i16 [[TMP1031]]
17871 // CHECK-NEXT:    store i16 [[TMP1033]], ptr [[SV]], align 2
17872 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17873 // CHECK-NEXT:    [[TMP1034:%.*]] = load i16, ptr [[SE]], align 2
17874 // CHECK-NEXT:    [[TMP1035:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1034]] acq_rel, align 2
17875 // CHECK-NEXT:    [[TMP1036:%.*]] = icmp slt i16 [[TMP1035]], [[TMP1034]]
17876 // CHECK-NEXT:    [[TMP1037:%.*]] = select i1 [[TMP1036]], i16 [[TMP1034]], i16 [[TMP1035]]
17877 // CHECK-NEXT:    store i16 [[TMP1037]], ptr [[SV]], align 2
17878 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17879 // CHECK-NEXT:    [[TMP1038:%.*]] = load i16, ptr [[SE]], align 2
17880 // CHECK-NEXT:    [[TMP1039:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1038]] acq_rel, align 2
17881 // CHECK-NEXT:    [[TMP1040:%.*]] = icmp slt i16 [[TMP1039]], [[TMP1038]]
17882 // CHECK-NEXT:    [[TMP1041:%.*]] = select i1 [[TMP1040]], i16 [[TMP1038]], i16 [[TMP1039]]
17883 // CHECK-NEXT:    store i16 [[TMP1041]], ptr [[SV]], align 2
17884 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17885 // CHECK-NEXT:    [[TMP1042:%.*]] = load i16, ptr [[SE]], align 2
17886 // CHECK-NEXT:    [[TMP1043:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1042]] acq_rel, align 2
17887 // CHECK-NEXT:    [[TMP1044:%.*]] = icmp sgt i16 [[TMP1043]], [[TMP1042]]
17888 // CHECK-NEXT:    [[TMP1045:%.*]] = select i1 [[TMP1044]], i16 [[TMP1042]], i16 [[TMP1043]]
17889 // CHECK-NEXT:    store i16 [[TMP1045]], ptr [[SV]], align 2
17890 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17891 // CHECK-NEXT:    [[TMP1046:%.*]] = load i16, ptr [[SE]], align 2
17892 // CHECK-NEXT:    [[TMP1047:%.*]] = load i16, ptr [[SD]], align 2
17893 // CHECK-NEXT:    [[TMP1048:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1046]], i16 [[TMP1047]] acq_rel acquire, align 2
17894 // CHECK-NEXT:    [[TMP1049:%.*]] = extractvalue { i16, i1 } [[TMP1048]], 0
17895 // CHECK-NEXT:    [[TMP1050:%.*]] = extractvalue { i16, i1 } [[TMP1048]], 1
17896 // CHECK-NEXT:    [[TMP1051:%.*]] = select i1 [[TMP1050]], i16 [[TMP1046]], i16 [[TMP1049]]
17897 // CHECK-NEXT:    store i16 [[TMP1051]], ptr [[SV]], align 2
17898 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17899 // CHECK-NEXT:    [[TMP1052:%.*]] = load i16, ptr [[SE]], align 2
17900 // CHECK-NEXT:    [[TMP1053:%.*]] = load i16, ptr [[SD]], align 2
17901 // CHECK-NEXT:    [[TMP1054:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1052]], i16 [[TMP1053]] acq_rel acquire, align 2
17902 // CHECK-NEXT:    [[TMP1055:%.*]] = extractvalue { i16, i1 } [[TMP1054]], 0
17903 // CHECK-NEXT:    [[TMP1056:%.*]] = extractvalue { i16, i1 } [[TMP1054]], 1
17904 // CHECK-NEXT:    [[TMP1057:%.*]] = select i1 [[TMP1056]], i16 [[TMP1052]], i16 [[TMP1055]]
17905 // CHECK-NEXT:    store i16 [[TMP1057]], ptr [[SV]], align 2
17906 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17907 // CHECK-NEXT:    [[TMP1058:%.*]] = load i16, ptr [[SE]], align 2
17908 // CHECK-NEXT:    [[TMP1059:%.*]] = load i16, ptr [[SD]], align 2
17909 // CHECK-NEXT:    [[TMP1060:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1058]], i16 [[TMP1059]] acq_rel acquire, align 2
17910 // CHECK-NEXT:    [[TMP1061:%.*]] = extractvalue { i16, i1 } [[TMP1060]], 0
17911 // CHECK-NEXT:    [[TMP1062:%.*]] = extractvalue { i16, i1 } [[TMP1060]], 1
17912 // CHECK-NEXT:    br i1 [[TMP1062]], label [[SX_ATOMIC_EXIT99:%.*]], label [[SX_ATOMIC_CONT100:%.*]]
17913 // CHECK:       sx.atomic.cont100:
17914 // CHECK-NEXT:    store i16 [[TMP1061]], ptr [[SV]], align 2
17915 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT99]]
17916 // CHECK:       sx.atomic.exit99:
17917 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17918 // CHECK-NEXT:    [[TMP1063:%.*]] = load i16, ptr [[SE]], align 2
17919 // CHECK-NEXT:    [[TMP1064:%.*]] = load i16, ptr [[SD]], align 2
17920 // CHECK-NEXT:    [[TMP1065:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1063]], i16 [[TMP1064]] acq_rel acquire, align 2
17921 // CHECK-NEXT:    [[TMP1066:%.*]] = extractvalue { i16, i1 } [[TMP1065]], 0
17922 // CHECK-NEXT:    [[TMP1067:%.*]] = extractvalue { i16, i1 } [[TMP1065]], 1
17923 // CHECK-NEXT:    br i1 [[TMP1067]], label [[SX_ATOMIC_EXIT101:%.*]], label [[SX_ATOMIC_CONT102:%.*]]
17924 // CHECK:       sx.atomic.cont102:
17925 // CHECK-NEXT:    store i16 [[TMP1066]], ptr [[SV]], align 2
17926 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT101]]
17927 // CHECK:       sx.atomic.exit101:
17928 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17929 // CHECK-NEXT:    [[TMP1068:%.*]] = load i16, ptr [[SE]], align 2
17930 // CHECK-NEXT:    [[TMP1069:%.*]] = load i16, ptr [[SD]], align 2
17931 // CHECK-NEXT:    [[TMP1070:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1068]], i16 [[TMP1069]] acq_rel acquire, align 2
17932 // CHECK-NEXT:    [[TMP1071:%.*]] = extractvalue { i16, i1 } [[TMP1070]], 1
17933 // CHECK-NEXT:    [[TMP1072:%.*]] = sext i1 [[TMP1071]] to i16
17934 // CHECK-NEXT:    store i16 [[TMP1072]], ptr [[SR]], align 2
17935 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17936 // CHECK-NEXT:    [[TMP1073:%.*]] = load i16, ptr [[SE]], align 2
17937 // CHECK-NEXT:    [[TMP1074:%.*]] = load i16, ptr [[SD]], align 2
17938 // CHECK-NEXT:    [[TMP1075:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1073]], i16 [[TMP1074]] acq_rel acquire, align 2
17939 // CHECK-NEXT:    [[TMP1076:%.*]] = extractvalue { i16, i1 } [[TMP1075]], 1
17940 // CHECK-NEXT:    [[TMP1077:%.*]] = sext i1 [[TMP1076]] to i16
17941 // CHECK-NEXT:    store i16 [[TMP1077]], ptr [[SR]], align 2
17942 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17943 // CHECK-NEXT:    [[TMP1078:%.*]] = load i16, ptr [[SE]], align 2
17944 // CHECK-NEXT:    [[TMP1079:%.*]] = load i16, ptr [[SD]], align 2
17945 // CHECK-NEXT:    [[TMP1080:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1078]], i16 [[TMP1079]] acq_rel acquire, align 2
17946 // CHECK-NEXT:    [[TMP1081:%.*]] = extractvalue { i16, i1 } [[TMP1080]], 0
17947 // CHECK-NEXT:    [[TMP1082:%.*]] = extractvalue { i16, i1 } [[TMP1080]], 1
17948 // CHECK-NEXT:    br i1 [[TMP1082]], label [[SX_ATOMIC_EXIT103:%.*]], label [[SX_ATOMIC_CONT104:%.*]]
17949 // CHECK:       sx.atomic.cont104:
17950 // CHECK-NEXT:    store i16 [[TMP1081]], ptr [[SV]], align 2
17951 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT103]]
17952 // CHECK:       sx.atomic.exit103:
17953 // CHECK-NEXT:    [[TMP1083:%.*]] = extractvalue { i16, i1 } [[TMP1080]], 1
17954 // CHECK-NEXT:    [[TMP1084:%.*]] = sext i1 [[TMP1083]] to i16
17955 // CHECK-NEXT:    store i16 [[TMP1084]], ptr [[SR]], align 2
17956 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17957 // CHECK-NEXT:    [[TMP1085:%.*]] = load i16, ptr [[SE]], align 2
17958 // CHECK-NEXT:    [[TMP1086:%.*]] = load i16, ptr [[SD]], align 2
17959 // CHECK-NEXT:    [[TMP1087:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1085]], i16 [[TMP1086]] acq_rel acquire, align 2
17960 // CHECK-NEXT:    [[TMP1088:%.*]] = extractvalue { i16, i1 } [[TMP1087]], 0
17961 // CHECK-NEXT:    [[TMP1089:%.*]] = extractvalue { i16, i1 } [[TMP1087]], 1
17962 // CHECK-NEXT:    br i1 [[TMP1089]], label [[SX_ATOMIC_EXIT105:%.*]], label [[SX_ATOMIC_CONT106:%.*]]
17963 // CHECK:       sx.atomic.cont106:
17964 // CHECK-NEXT:    store i16 [[TMP1088]], ptr [[SV]], align 2
17965 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT105]]
17966 // CHECK:       sx.atomic.exit105:
17967 // CHECK-NEXT:    [[TMP1090:%.*]] = extractvalue { i16, i1 } [[TMP1087]], 1
17968 // CHECK-NEXT:    [[TMP1091:%.*]] = sext i1 [[TMP1090]] to i16
17969 // CHECK-NEXT:    store i16 [[TMP1091]], ptr [[SR]], align 2
17970 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
17971 // CHECK-NEXT:    [[TMP1092:%.*]] = load i16, ptr [[SE]], align 2
17972 // CHECK-NEXT:    [[TMP1093:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1092]] acquire, align 2
17973 // CHECK-NEXT:    store i16 [[TMP1093]], ptr [[SV]], align 2
17974 // CHECK-NEXT:    [[TMP1094:%.*]] = load i16, ptr [[SE]], align 2
17975 // CHECK-NEXT:    [[TMP1095:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1094]] acquire, align 2
17976 // CHECK-NEXT:    store i16 [[TMP1095]], ptr [[SV]], align 2
17977 // CHECK-NEXT:    [[TMP1096:%.*]] = load i16, ptr [[SE]], align 2
17978 // CHECK-NEXT:    [[TMP1097:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1096]] acquire, align 2
17979 // CHECK-NEXT:    store i16 [[TMP1097]], ptr [[SV]], align 2
17980 // CHECK-NEXT:    [[TMP1098:%.*]] = load i16, ptr [[SE]], align 2
17981 // CHECK-NEXT:    [[TMP1099:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1098]] acquire, align 2
17982 // CHECK-NEXT:    store i16 [[TMP1099]], ptr [[SV]], align 2
17983 // CHECK-NEXT:    [[TMP1100:%.*]] = load i16, ptr [[SE]], align 2
17984 // CHECK-NEXT:    [[TMP1101:%.*]] = load i16, ptr [[SD]], align 2
17985 // CHECK-NEXT:    [[TMP1102:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1100]], i16 [[TMP1101]] acquire acquire, align 2
17986 // CHECK-NEXT:    [[TMP1103:%.*]] = extractvalue { i16, i1 } [[TMP1102]], 0
17987 // CHECK-NEXT:    store i16 [[TMP1103]], ptr [[SV]], align 2
17988 // CHECK-NEXT:    [[TMP1104:%.*]] = load i16, ptr [[SE]], align 2
17989 // CHECK-NEXT:    [[TMP1105:%.*]] = load i16, ptr [[SD]], align 2
17990 // CHECK-NEXT:    [[TMP1106:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1104]], i16 [[TMP1105]] acquire acquire, align 2
17991 // CHECK-NEXT:    [[TMP1107:%.*]] = extractvalue { i16, i1 } [[TMP1106]], 0
17992 // CHECK-NEXT:    store i16 [[TMP1107]], ptr [[SV]], align 2
17993 // CHECK-NEXT:    [[TMP1108:%.*]] = load i16, ptr [[SE]], align 2
17994 // CHECK-NEXT:    [[TMP1109:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1108]] acquire, align 2
17995 // CHECK-NEXT:    [[TMP1110:%.*]] = icmp sgt i16 [[TMP1109]], [[TMP1108]]
17996 // CHECK-NEXT:    [[TMP1111:%.*]] = select i1 [[TMP1110]], i16 [[TMP1108]], i16 [[TMP1109]]
17997 // CHECK-NEXT:    store i16 [[TMP1111]], ptr [[SV]], align 2
17998 // CHECK-NEXT:    [[TMP1112:%.*]] = load i16, ptr [[SE]], align 2
17999 // CHECK-NEXT:    [[TMP1113:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1112]] acquire, align 2
18000 // CHECK-NEXT:    [[TMP1114:%.*]] = icmp slt i16 [[TMP1113]], [[TMP1112]]
18001 // CHECK-NEXT:    [[TMP1115:%.*]] = select i1 [[TMP1114]], i16 [[TMP1112]], i16 [[TMP1113]]
18002 // CHECK-NEXT:    store i16 [[TMP1115]], ptr [[SV]], align 2
18003 // CHECK-NEXT:    [[TMP1116:%.*]] = load i16, ptr [[SE]], align 2
18004 // CHECK-NEXT:    [[TMP1117:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1116]] acquire, align 2
18005 // CHECK-NEXT:    [[TMP1118:%.*]] = icmp slt i16 [[TMP1117]], [[TMP1116]]
18006 // CHECK-NEXT:    [[TMP1119:%.*]] = select i1 [[TMP1118]], i16 [[TMP1116]], i16 [[TMP1117]]
18007 // CHECK-NEXT:    store i16 [[TMP1119]], ptr [[SV]], align 2
18008 // CHECK-NEXT:    [[TMP1120:%.*]] = load i16, ptr [[SE]], align 2
18009 // CHECK-NEXT:    [[TMP1121:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1120]] acquire, align 2
18010 // CHECK-NEXT:    [[TMP1122:%.*]] = icmp sgt i16 [[TMP1121]], [[TMP1120]]
18011 // CHECK-NEXT:    [[TMP1123:%.*]] = select i1 [[TMP1122]], i16 [[TMP1120]], i16 [[TMP1121]]
18012 // CHECK-NEXT:    store i16 [[TMP1123]], ptr [[SV]], align 2
18013 // CHECK-NEXT:    [[TMP1124:%.*]] = load i16, ptr [[SE]], align 2
18014 // CHECK-NEXT:    [[TMP1125:%.*]] = load i16, ptr [[SD]], align 2
18015 // CHECK-NEXT:    [[TMP1126:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1124]], i16 [[TMP1125]] acquire acquire, align 2
18016 // CHECK-NEXT:    [[TMP1127:%.*]] = extractvalue { i16, i1 } [[TMP1126]], 0
18017 // CHECK-NEXT:    [[TMP1128:%.*]] = extractvalue { i16, i1 } [[TMP1126]], 1
18018 // CHECK-NEXT:    [[TMP1129:%.*]] = select i1 [[TMP1128]], i16 [[TMP1124]], i16 [[TMP1127]]
18019 // CHECK-NEXT:    store i16 [[TMP1129]], ptr [[SV]], align 2
18020 // CHECK-NEXT:    [[TMP1130:%.*]] = load i16, ptr [[SE]], align 2
18021 // CHECK-NEXT:    [[TMP1131:%.*]] = load i16, ptr [[SD]], align 2
18022 // CHECK-NEXT:    [[TMP1132:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1130]], i16 [[TMP1131]] acquire acquire, align 2
18023 // CHECK-NEXT:    [[TMP1133:%.*]] = extractvalue { i16, i1 } [[TMP1132]], 0
18024 // CHECK-NEXT:    [[TMP1134:%.*]] = extractvalue { i16, i1 } [[TMP1132]], 1
18025 // CHECK-NEXT:    [[TMP1135:%.*]] = select i1 [[TMP1134]], i16 [[TMP1130]], i16 [[TMP1133]]
18026 // CHECK-NEXT:    store i16 [[TMP1135]], ptr [[SV]], align 2
18027 // CHECK-NEXT:    [[TMP1136:%.*]] = load i16, ptr [[SE]], align 2
18028 // CHECK-NEXT:    [[TMP1137:%.*]] = load i16, ptr [[SD]], align 2
18029 // CHECK-NEXT:    [[TMP1138:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1136]], i16 [[TMP1137]] acquire acquire, align 2
18030 // CHECK-NEXT:    [[TMP1139:%.*]] = extractvalue { i16, i1 } [[TMP1138]], 0
18031 // CHECK-NEXT:    [[TMP1140:%.*]] = extractvalue { i16, i1 } [[TMP1138]], 1
18032 // CHECK-NEXT:    br i1 [[TMP1140]], label [[SX_ATOMIC_EXIT107:%.*]], label [[SX_ATOMIC_CONT108:%.*]]
18033 // CHECK:       sx.atomic.cont108:
18034 // CHECK-NEXT:    store i16 [[TMP1139]], ptr [[SV]], align 2
18035 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT107]]
18036 // CHECK:       sx.atomic.exit107:
18037 // CHECK-NEXT:    [[TMP1141:%.*]] = load i16, ptr [[SE]], align 2
18038 // CHECK-NEXT:    [[TMP1142:%.*]] = load i16, ptr [[SD]], align 2
18039 // CHECK-NEXT:    [[TMP1143:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1141]], i16 [[TMP1142]] acquire acquire, align 2
18040 // CHECK-NEXT:    [[TMP1144:%.*]] = extractvalue { i16, i1 } [[TMP1143]], 0
18041 // CHECK-NEXT:    [[TMP1145:%.*]] = extractvalue { i16, i1 } [[TMP1143]], 1
18042 // CHECK-NEXT:    br i1 [[TMP1145]], label [[SX_ATOMIC_EXIT109:%.*]], label [[SX_ATOMIC_CONT110:%.*]]
18043 // CHECK:       sx.atomic.cont110:
18044 // CHECK-NEXT:    store i16 [[TMP1144]], ptr [[SV]], align 2
18045 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT109]]
18046 // CHECK:       sx.atomic.exit109:
18047 // CHECK-NEXT:    [[TMP1146:%.*]] = load i16, ptr [[SE]], align 2
18048 // CHECK-NEXT:    [[TMP1147:%.*]] = load i16, ptr [[SD]], align 2
18049 // CHECK-NEXT:    [[TMP1148:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1146]], i16 [[TMP1147]] acquire acquire, align 2
18050 // CHECK-NEXT:    [[TMP1149:%.*]] = extractvalue { i16, i1 } [[TMP1148]], 1
18051 // CHECK-NEXT:    [[TMP1150:%.*]] = sext i1 [[TMP1149]] to i16
18052 // CHECK-NEXT:    store i16 [[TMP1150]], ptr [[SR]], align 2
18053 // CHECK-NEXT:    [[TMP1151:%.*]] = load i16, ptr [[SE]], align 2
18054 // CHECK-NEXT:    [[TMP1152:%.*]] = load i16, ptr [[SD]], align 2
18055 // CHECK-NEXT:    [[TMP1153:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1151]], i16 [[TMP1152]] acquire acquire, align 2
18056 // CHECK-NEXT:    [[TMP1154:%.*]] = extractvalue { i16, i1 } [[TMP1153]], 1
18057 // CHECK-NEXT:    [[TMP1155:%.*]] = sext i1 [[TMP1154]] to i16
18058 // CHECK-NEXT:    store i16 [[TMP1155]], ptr [[SR]], align 2
18059 // CHECK-NEXT:    [[TMP1156:%.*]] = load i16, ptr [[SE]], align 2
18060 // CHECK-NEXT:    [[TMP1157:%.*]] = load i16, ptr [[SD]], align 2
18061 // CHECK-NEXT:    [[TMP1158:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1156]], i16 [[TMP1157]] acquire acquire, align 2
18062 // CHECK-NEXT:    [[TMP1159:%.*]] = extractvalue { i16, i1 } [[TMP1158]], 0
18063 // CHECK-NEXT:    [[TMP1160:%.*]] = extractvalue { i16, i1 } [[TMP1158]], 1
18064 // CHECK-NEXT:    br i1 [[TMP1160]], label [[SX_ATOMIC_EXIT111:%.*]], label [[SX_ATOMIC_CONT112:%.*]]
18065 // CHECK:       sx.atomic.cont112:
18066 // CHECK-NEXT:    store i16 [[TMP1159]], ptr [[SV]], align 2
18067 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT111]]
18068 // CHECK:       sx.atomic.exit111:
18069 // CHECK-NEXT:    [[TMP1161:%.*]] = extractvalue { i16, i1 } [[TMP1158]], 1
18070 // CHECK-NEXT:    [[TMP1162:%.*]] = sext i1 [[TMP1161]] to i16
18071 // CHECK-NEXT:    store i16 [[TMP1162]], ptr [[SR]], align 2
18072 // CHECK-NEXT:    [[TMP1163:%.*]] = load i16, ptr [[SE]], align 2
18073 // CHECK-NEXT:    [[TMP1164:%.*]] = load i16, ptr [[SD]], align 2
18074 // CHECK-NEXT:    [[TMP1165:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1163]], i16 [[TMP1164]] acquire acquire, align 2
18075 // CHECK-NEXT:    [[TMP1166:%.*]] = extractvalue { i16, i1 } [[TMP1165]], 0
18076 // CHECK-NEXT:    [[TMP1167:%.*]] = extractvalue { i16, i1 } [[TMP1165]], 1
18077 // CHECK-NEXT:    br i1 [[TMP1167]], label [[SX_ATOMIC_EXIT113:%.*]], label [[SX_ATOMIC_CONT114:%.*]]
18078 // CHECK:       sx.atomic.cont114:
18079 // CHECK-NEXT:    store i16 [[TMP1166]], ptr [[SV]], align 2
18080 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT113]]
18081 // CHECK:       sx.atomic.exit113:
18082 // CHECK-NEXT:    [[TMP1168:%.*]] = extractvalue { i16, i1 } [[TMP1165]], 1
18083 // CHECK-NEXT:    [[TMP1169:%.*]] = sext i1 [[TMP1168]] to i16
18084 // CHECK-NEXT:    store i16 [[TMP1169]], ptr [[SR]], align 2
18085 // CHECK-NEXT:    [[TMP1170:%.*]] = load i16, ptr [[SE]], align 2
18086 // CHECK-NEXT:    [[TMP1171:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1170]] monotonic, align 2
18087 // CHECK-NEXT:    store i16 [[TMP1171]], ptr [[SV]], align 2
18088 // CHECK-NEXT:    [[TMP1172:%.*]] = load i16, ptr [[SE]], align 2
18089 // CHECK-NEXT:    [[TMP1173:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1172]] monotonic, align 2
18090 // CHECK-NEXT:    store i16 [[TMP1173]], ptr [[SV]], align 2
18091 // CHECK-NEXT:    [[TMP1174:%.*]] = load i16, ptr [[SE]], align 2
18092 // CHECK-NEXT:    [[TMP1175:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1174]] monotonic, align 2
18093 // CHECK-NEXT:    store i16 [[TMP1175]], ptr [[SV]], align 2
18094 // CHECK-NEXT:    [[TMP1176:%.*]] = load i16, ptr [[SE]], align 2
18095 // CHECK-NEXT:    [[TMP1177:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1176]] monotonic, align 2
18096 // CHECK-NEXT:    store i16 [[TMP1177]], ptr [[SV]], align 2
18097 // CHECK-NEXT:    [[TMP1178:%.*]] = load i16, ptr [[SE]], align 2
18098 // CHECK-NEXT:    [[TMP1179:%.*]] = load i16, ptr [[SD]], align 2
18099 // CHECK-NEXT:    [[TMP1180:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1178]], i16 [[TMP1179]] monotonic monotonic, align 2
18100 // CHECK-NEXT:    [[TMP1181:%.*]] = extractvalue { i16, i1 } [[TMP1180]], 0
18101 // CHECK-NEXT:    store i16 [[TMP1181]], ptr [[SV]], align 2
18102 // CHECK-NEXT:    [[TMP1182:%.*]] = load i16, ptr [[SE]], align 2
18103 // CHECK-NEXT:    [[TMP1183:%.*]] = load i16, ptr [[SD]], align 2
18104 // CHECK-NEXT:    [[TMP1184:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1182]], i16 [[TMP1183]] monotonic monotonic, align 2
18105 // CHECK-NEXT:    [[TMP1185:%.*]] = extractvalue { i16, i1 } [[TMP1184]], 0
18106 // CHECK-NEXT:    store i16 [[TMP1185]], ptr [[SV]], align 2
18107 // CHECK-NEXT:    [[TMP1186:%.*]] = load i16, ptr [[SE]], align 2
18108 // CHECK-NEXT:    [[TMP1187:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1186]] monotonic, align 2
18109 // CHECK-NEXT:    [[TMP1188:%.*]] = icmp sgt i16 [[TMP1187]], [[TMP1186]]
18110 // CHECK-NEXT:    [[TMP1189:%.*]] = select i1 [[TMP1188]], i16 [[TMP1186]], i16 [[TMP1187]]
18111 // CHECK-NEXT:    store i16 [[TMP1189]], ptr [[SV]], align 2
18112 // CHECK-NEXT:    [[TMP1190:%.*]] = load i16, ptr [[SE]], align 2
18113 // CHECK-NEXT:    [[TMP1191:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1190]] monotonic, align 2
18114 // CHECK-NEXT:    [[TMP1192:%.*]] = icmp slt i16 [[TMP1191]], [[TMP1190]]
18115 // CHECK-NEXT:    [[TMP1193:%.*]] = select i1 [[TMP1192]], i16 [[TMP1190]], i16 [[TMP1191]]
18116 // CHECK-NEXT:    store i16 [[TMP1193]], ptr [[SV]], align 2
18117 // CHECK-NEXT:    [[TMP1194:%.*]] = load i16, ptr [[SE]], align 2
18118 // CHECK-NEXT:    [[TMP1195:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1194]] monotonic, align 2
18119 // CHECK-NEXT:    [[TMP1196:%.*]] = icmp slt i16 [[TMP1195]], [[TMP1194]]
18120 // CHECK-NEXT:    [[TMP1197:%.*]] = select i1 [[TMP1196]], i16 [[TMP1194]], i16 [[TMP1195]]
18121 // CHECK-NEXT:    store i16 [[TMP1197]], ptr [[SV]], align 2
18122 // CHECK-NEXT:    [[TMP1198:%.*]] = load i16, ptr [[SE]], align 2
18123 // CHECK-NEXT:    [[TMP1199:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1198]] monotonic, align 2
18124 // CHECK-NEXT:    [[TMP1200:%.*]] = icmp sgt i16 [[TMP1199]], [[TMP1198]]
18125 // CHECK-NEXT:    [[TMP1201:%.*]] = select i1 [[TMP1200]], i16 [[TMP1198]], i16 [[TMP1199]]
18126 // CHECK-NEXT:    store i16 [[TMP1201]], ptr [[SV]], align 2
18127 // CHECK-NEXT:    [[TMP1202:%.*]] = load i16, ptr [[SE]], align 2
18128 // CHECK-NEXT:    [[TMP1203:%.*]] = load i16, ptr [[SD]], align 2
18129 // CHECK-NEXT:    [[TMP1204:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1202]], i16 [[TMP1203]] monotonic monotonic, align 2
18130 // CHECK-NEXT:    [[TMP1205:%.*]] = extractvalue { i16, i1 } [[TMP1204]], 0
18131 // CHECK-NEXT:    [[TMP1206:%.*]] = extractvalue { i16, i1 } [[TMP1204]], 1
18132 // CHECK-NEXT:    [[TMP1207:%.*]] = select i1 [[TMP1206]], i16 [[TMP1202]], i16 [[TMP1205]]
18133 // CHECK-NEXT:    store i16 [[TMP1207]], ptr [[SV]], align 2
18134 // CHECK-NEXT:    [[TMP1208:%.*]] = load i16, ptr [[SE]], align 2
18135 // CHECK-NEXT:    [[TMP1209:%.*]] = load i16, ptr [[SD]], align 2
18136 // CHECK-NEXT:    [[TMP1210:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1208]], i16 [[TMP1209]] monotonic monotonic, align 2
18137 // CHECK-NEXT:    [[TMP1211:%.*]] = extractvalue { i16, i1 } [[TMP1210]], 0
18138 // CHECK-NEXT:    [[TMP1212:%.*]] = extractvalue { i16, i1 } [[TMP1210]], 1
18139 // CHECK-NEXT:    [[TMP1213:%.*]] = select i1 [[TMP1212]], i16 [[TMP1208]], i16 [[TMP1211]]
18140 // CHECK-NEXT:    store i16 [[TMP1213]], ptr [[SV]], align 2
18141 // CHECK-NEXT:    [[TMP1214:%.*]] = load i16, ptr [[SE]], align 2
18142 // CHECK-NEXT:    [[TMP1215:%.*]] = load i16, ptr [[SD]], align 2
18143 // CHECK-NEXT:    [[TMP1216:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1214]], i16 [[TMP1215]] monotonic monotonic, align 2
18144 // CHECK-NEXT:    [[TMP1217:%.*]] = extractvalue { i16, i1 } [[TMP1216]], 0
18145 // CHECK-NEXT:    [[TMP1218:%.*]] = extractvalue { i16, i1 } [[TMP1216]], 1
18146 // CHECK-NEXT:    br i1 [[TMP1218]], label [[SX_ATOMIC_EXIT115:%.*]], label [[SX_ATOMIC_CONT116:%.*]]
18147 // CHECK:       sx.atomic.cont116:
18148 // CHECK-NEXT:    store i16 [[TMP1217]], ptr [[SV]], align 2
18149 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT115]]
18150 // CHECK:       sx.atomic.exit115:
18151 // CHECK-NEXT:    [[TMP1219:%.*]] = load i16, ptr [[SE]], align 2
18152 // CHECK-NEXT:    [[TMP1220:%.*]] = load i16, ptr [[SD]], align 2
18153 // CHECK-NEXT:    [[TMP1221:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1219]], i16 [[TMP1220]] monotonic monotonic, align 2
18154 // CHECK-NEXT:    [[TMP1222:%.*]] = extractvalue { i16, i1 } [[TMP1221]], 0
18155 // CHECK-NEXT:    [[TMP1223:%.*]] = extractvalue { i16, i1 } [[TMP1221]], 1
18156 // CHECK-NEXT:    br i1 [[TMP1223]], label [[SX_ATOMIC_EXIT117:%.*]], label [[SX_ATOMIC_CONT118:%.*]]
18157 // CHECK:       sx.atomic.cont118:
18158 // CHECK-NEXT:    store i16 [[TMP1222]], ptr [[SV]], align 2
18159 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT117]]
18160 // CHECK:       sx.atomic.exit117:
18161 // CHECK-NEXT:    [[TMP1224:%.*]] = load i16, ptr [[SE]], align 2
18162 // CHECK-NEXT:    [[TMP1225:%.*]] = load i16, ptr [[SD]], align 2
18163 // CHECK-NEXT:    [[TMP1226:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1224]], i16 [[TMP1225]] monotonic monotonic, align 2
18164 // CHECK-NEXT:    [[TMP1227:%.*]] = extractvalue { i16, i1 } [[TMP1226]], 1
18165 // CHECK-NEXT:    [[TMP1228:%.*]] = sext i1 [[TMP1227]] to i16
18166 // CHECK-NEXT:    store i16 [[TMP1228]], ptr [[SR]], align 2
18167 // CHECK-NEXT:    [[TMP1229:%.*]] = load i16, ptr [[SE]], align 2
18168 // CHECK-NEXT:    [[TMP1230:%.*]] = load i16, ptr [[SD]], align 2
18169 // CHECK-NEXT:    [[TMP1231:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1229]], i16 [[TMP1230]] monotonic monotonic, align 2
18170 // CHECK-NEXT:    [[TMP1232:%.*]] = extractvalue { i16, i1 } [[TMP1231]], 1
18171 // CHECK-NEXT:    [[TMP1233:%.*]] = sext i1 [[TMP1232]] to i16
18172 // CHECK-NEXT:    store i16 [[TMP1233]], ptr [[SR]], align 2
18173 // CHECK-NEXT:    [[TMP1234:%.*]] = load i16, ptr [[SE]], align 2
18174 // CHECK-NEXT:    [[TMP1235:%.*]] = load i16, ptr [[SD]], align 2
18175 // CHECK-NEXT:    [[TMP1236:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1234]], i16 [[TMP1235]] monotonic monotonic, align 2
18176 // CHECK-NEXT:    [[TMP1237:%.*]] = extractvalue { i16, i1 } [[TMP1236]], 0
18177 // CHECK-NEXT:    [[TMP1238:%.*]] = extractvalue { i16, i1 } [[TMP1236]], 1
18178 // CHECK-NEXT:    br i1 [[TMP1238]], label [[SX_ATOMIC_EXIT119:%.*]], label [[SX_ATOMIC_CONT120:%.*]]
18179 // CHECK:       sx.atomic.cont120:
18180 // CHECK-NEXT:    store i16 [[TMP1237]], ptr [[SV]], align 2
18181 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT119]]
18182 // CHECK:       sx.atomic.exit119:
18183 // CHECK-NEXT:    [[TMP1239:%.*]] = extractvalue { i16, i1 } [[TMP1236]], 1
18184 // CHECK-NEXT:    [[TMP1240:%.*]] = sext i1 [[TMP1239]] to i16
18185 // CHECK-NEXT:    store i16 [[TMP1240]], ptr [[SR]], align 2
18186 // CHECK-NEXT:    [[TMP1241:%.*]] = load i16, ptr [[SE]], align 2
18187 // CHECK-NEXT:    [[TMP1242:%.*]] = load i16, ptr [[SD]], align 2
18188 // CHECK-NEXT:    [[TMP1243:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1241]], i16 [[TMP1242]] monotonic monotonic, align 2
18189 // CHECK-NEXT:    [[TMP1244:%.*]] = extractvalue { i16, i1 } [[TMP1243]], 0
18190 // CHECK-NEXT:    [[TMP1245:%.*]] = extractvalue { i16, i1 } [[TMP1243]], 1
18191 // CHECK-NEXT:    br i1 [[TMP1245]], label [[SX_ATOMIC_EXIT121:%.*]], label [[SX_ATOMIC_CONT122:%.*]]
18192 // CHECK:       sx.atomic.cont122:
18193 // CHECK-NEXT:    store i16 [[TMP1244]], ptr [[SV]], align 2
18194 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT121]]
18195 // CHECK:       sx.atomic.exit121:
18196 // CHECK-NEXT:    [[TMP1246:%.*]] = extractvalue { i16, i1 } [[TMP1243]], 1
18197 // CHECK-NEXT:    [[TMP1247:%.*]] = sext i1 [[TMP1246]] to i16
18198 // CHECK-NEXT:    store i16 [[TMP1247]], ptr [[SR]], align 2
18199 // CHECK-NEXT:    [[TMP1248:%.*]] = load i16, ptr [[SE]], align 2
18200 // CHECK-NEXT:    [[TMP1249:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1248]] release, align 2
18201 // CHECK-NEXT:    store i16 [[TMP1249]], ptr [[SV]], align 2
18202 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18203 // CHECK-NEXT:    [[TMP1250:%.*]] = load i16, ptr [[SE]], align 2
18204 // CHECK-NEXT:    [[TMP1251:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1250]] release, align 2
18205 // CHECK-NEXT:    store i16 [[TMP1251]], ptr [[SV]], align 2
18206 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18207 // CHECK-NEXT:    [[TMP1252:%.*]] = load i16, ptr [[SE]], align 2
18208 // CHECK-NEXT:    [[TMP1253:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1252]] release, align 2
18209 // CHECK-NEXT:    store i16 [[TMP1253]], ptr [[SV]], align 2
18210 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18211 // CHECK-NEXT:    [[TMP1254:%.*]] = load i16, ptr [[SE]], align 2
18212 // CHECK-NEXT:    [[TMP1255:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1254]] release, align 2
18213 // CHECK-NEXT:    store i16 [[TMP1255]], ptr [[SV]], align 2
18214 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18215 // CHECK-NEXT:    [[TMP1256:%.*]] = load i16, ptr [[SE]], align 2
18216 // CHECK-NEXT:    [[TMP1257:%.*]] = load i16, ptr [[SD]], align 2
18217 // CHECK-NEXT:    [[TMP1258:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1256]], i16 [[TMP1257]] release monotonic, align 2
18218 // CHECK-NEXT:    [[TMP1259:%.*]] = extractvalue { i16, i1 } [[TMP1258]], 0
18219 // CHECK-NEXT:    store i16 [[TMP1259]], ptr [[SV]], align 2
18220 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18221 // CHECK-NEXT:    [[TMP1260:%.*]] = load i16, ptr [[SE]], align 2
18222 // CHECK-NEXT:    [[TMP1261:%.*]] = load i16, ptr [[SD]], align 2
18223 // CHECK-NEXT:    [[TMP1262:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1260]], i16 [[TMP1261]] release monotonic, align 2
18224 // CHECK-NEXT:    [[TMP1263:%.*]] = extractvalue { i16, i1 } [[TMP1262]], 0
18225 // CHECK-NEXT:    store i16 [[TMP1263]], ptr [[SV]], align 2
18226 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18227 // CHECK-NEXT:    [[TMP1264:%.*]] = load i16, ptr [[SE]], align 2
18228 // CHECK-NEXT:    [[TMP1265:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1264]] release, align 2
18229 // CHECK-NEXT:    [[TMP1266:%.*]] = icmp sgt i16 [[TMP1265]], [[TMP1264]]
18230 // CHECK-NEXT:    [[TMP1267:%.*]] = select i1 [[TMP1266]], i16 [[TMP1264]], i16 [[TMP1265]]
18231 // CHECK-NEXT:    store i16 [[TMP1267]], ptr [[SV]], align 2
18232 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18233 // CHECK-NEXT:    [[TMP1268:%.*]] = load i16, ptr [[SE]], align 2
18234 // CHECK-NEXT:    [[TMP1269:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1268]] release, align 2
18235 // CHECK-NEXT:    [[TMP1270:%.*]] = icmp slt i16 [[TMP1269]], [[TMP1268]]
18236 // CHECK-NEXT:    [[TMP1271:%.*]] = select i1 [[TMP1270]], i16 [[TMP1268]], i16 [[TMP1269]]
18237 // CHECK-NEXT:    store i16 [[TMP1271]], ptr [[SV]], align 2
18238 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18239 // CHECK-NEXT:    [[TMP1272:%.*]] = load i16, ptr [[SE]], align 2
18240 // CHECK-NEXT:    [[TMP1273:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1272]] release, align 2
18241 // CHECK-NEXT:    [[TMP1274:%.*]] = icmp slt i16 [[TMP1273]], [[TMP1272]]
18242 // CHECK-NEXT:    [[TMP1275:%.*]] = select i1 [[TMP1274]], i16 [[TMP1272]], i16 [[TMP1273]]
18243 // CHECK-NEXT:    store i16 [[TMP1275]], ptr [[SV]], align 2
18244 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18245 // CHECK-NEXT:    [[TMP1276:%.*]] = load i16, ptr [[SE]], align 2
18246 // CHECK-NEXT:    [[TMP1277:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1276]] release, align 2
18247 // CHECK-NEXT:    [[TMP1278:%.*]] = icmp sgt i16 [[TMP1277]], [[TMP1276]]
18248 // CHECK-NEXT:    [[TMP1279:%.*]] = select i1 [[TMP1278]], i16 [[TMP1276]], i16 [[TMP1277]]
18249 // CHECK-NEXT:    store i16 [[TMP1279]], ptr [[SV]], align 2
18250 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18251 // CHECK-NEXT:    [[TMP1280:%.*]] = load i16, ptr [[SE]], align 2
18252 // CHECK-NEXT:    [[TMP1281:%.*]] = load i16, ptr [[SD]], align 2
18253 // CHECK-NEXT:    [[TMP1282:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1280]], i16 [[TMP1281]] release monotonic, align 2
18254 // CHECK-NEXT:    [[TMP1283:%.*]] = extractvalue { i16, i1 } [[TMP1282]], 0
18255 // CHECK-NEXT:    [[TMP1284:%.*]] = extractvalue { i16, i1 } [[TMP1282]], 1
18256 // CHECK-NEXT:    [[TMP1285:%.*]] = select i1 [[TMP1284]], i16 [[TMP1280]], i16 [[TMP1283]]
18257 // CHECK-NEXT:    store i16 [[TMP1285]], ptr [[SV]], align 2
18258 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18259 // CHECK-NEXT:    [[TMP1286:%.*]] = load i16, ptr [[SE]], align 2
18260 // CHECK-NEXT:    [[TMP1287:%.*]] = load i16, ptr [[SD]], align 2
18261 // CHECK-NEXT:    [[TMP1288:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1286]], i16 [[TMP1287]] release monotonic, align 2
18262 // CHECK-NEXT:    [[TMP1289:%.*]] = extractvalue { i16, i1 } [[TMP1288]], 0
18263 // CHECK-NEXT:    [[TMP1290:%.*]] = extractvalue { i16, i1 } [[TMP1288]], 1
18264 // CHECK-NEXT:    [[TMP1291:%.*]] = select i1 [[TMP1290]], i16 [[TMP1286]], i16 [[TMP1289]]
18265 // CHECK-NEXT:    store i16 [[TMP1291]], ptr [[SV]], align 2
18266 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18267 // CHECK-NEXT:    [[TMP1292:%.*]] = load i16, ptr [[SE]], align 2
18268 // CHECK-NEXT:    [[TMP1293:%.*]] = load i16, ptr [[SD]], align 2
18269 // CHECK-NEXT:    [[TMP1294:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1292]], i16 [[TMP1293]] release monotonic, align 2
18270 // CHECK-NEXT:    [[TMP1295:%.*]] = extractvalue { i16, i1 } [[TMP1294]], 0
18271 // CHECK-NEXT:    [[TMP1296:%.*]] = extractvalue { i16, i1 } [[TMP1294]], 1
18272 // CHECK-NEXT:    br i1 [[TMP1296]], label [[SX_ATOMIC_EXIT123:%.*]], label [[SX_ATOMIC_CONT124:%.*]]
18273 // CHECK:       sx.atomic.cont124:
18274 // CHECK-NEXT:    store i16 [[TMP1295]], ptr [[SV]], align 2
18275 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT123]]
18276 // CHECK:       sx.atomic.exit123:
18277 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18278 // CHECK-NEXT:    [[TMP1297:%.*]] = load i16, ptr [[SE]], align 2
18279 // CHECK-NEXT:    [[TMP1298:%.*]] = load i16, ptr [[SD]], align 2
18280 // CHECK-NEXT:    [[TMP1299:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1297]], i16 [[TMP1298]] release monotonic, align 2
18281 // CHECK-NEXT:    [[TMP1300:%.*]] = extractvalue { i16, i1 } [[TMP1299]], 0
18282 // CHECK-NEXT:    [[TMP1301:%.*]] = extractvalue { i16, i1 } [[TMP1299]], 1
18283 // CHECK-NEXT:    br i1 [[TMP1301]], label [[SX_ATOMIC_EXIT125:%.*]], label [[SX_ATOMIC_CONT126:%.*]]
18284 // CHECK:       sx.atomic.cont126:
18285 // CHECK-NEXT:    store i16 [[TMP1300]], ptr [[SV]], align 2
18286 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT125]]
18287 // CHECK:       sx.atomic.exit125:
18288 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18289 // CHECK-NEXT:    [[TMP1302:%.*]] = load i16, ptr [[SE]], align 2
18290 // CHECK-NEXT:    [[TMP1303:%.*]] = load i16, ptr [[SD]], align 2
18291 // CHECK-NEXT:    [[TMP1304:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1302]], i16 [[TMP1303]] release monotonic, align 2
18292 // CHECK-NEXT:    [[TMP1305:%.*]] = extractvalue { i16, i1 } [[TMP1304]], 1
18293 // CHECK-NEXT:    [[TMP1306:%.*]] = sext i1 [[TMP1305]] to i16
18294 // CHECK-NEXT:    store i16 [[TMP1306]], ptr [[SR]], align 2
18295 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18296 // CHECK-NEXT:    [[TMP1307:%.*]] = load i16, ptr [[SE]], align 2
18297 // CHECK-NEXT:    [[TMP1308:%.*]] = load i16, ptr [[SD]], align 2
18298 // CHECK-NEXT:    [[TMP1309:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1307]], i16 [[TMP1308]] release monotonic, align 2
18299 // CHECK-NEXT:    [[TMP1310:%.*]] = extractvalue { i16, i1 } [[TMP1309]], 1
18300 // CHECK-NEXT:    [[TMP1311:%.*]] = sext i1 [[TMP1310]] to i16
18301 // CHECK-NEXT:    store i16 [[TMP1311]], ptr [[SR]], align 2
18302 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18303 // CHECK-NEXT:    [[TMP1312:%.*]] = load i16, ptr [[SE]], align 2
18304 // CHECK-NEXT:    [[TMP1313:%.*]] = load i16, ptr [[SD]], align 2
18305 // CHECK-NEXT:    [[TMP1314:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1312]], i16 [[TMP1313]] release monotonic, align 2
18306 // CHECK-NEXT:    [[TMP1315:%.*]] = extractvalue { i16, i1 } [[TMP1314]], 0
18307 // CHECK-NEXT:    [[TMP1316:%.*]] = extractvalue { i16, i1 } [[TMP1314]], 1
18308 // CHECK-NEXT:    br i1 [[TMP1316]], label [[SX_ATOMIC_EXIT127:%.*]], label [[SX_ATOMIC_CONT128:%.*]]
18309 // CHECK:       sx.atomic.cont128:
18310 // CHECK-NEXT:    store i16 [[TMP1315]], ptr [[SV]], align 2
18311 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT127]]
18312 // CHECK:       sx.atomic.exit127:
18313 // CHECK-NEXT:    [[TMP1317:%.*]] = extractvalue { i16, i1 } [[TMP1314]], 1
18314 // CHECK-NEXT:    [[TMP1318:%.*]] = sext i1 [[TMP1317]] to i16
18315 // CHECK-NEXT:    store i16 [[TMP1318]], ptr [[SR]], align 2
18316 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18317 // CHECK-NEXT:    [[TMP1319:%.*]] = load i16, ptr [[SE]], align 2
18318 // CHECK-NEXT:    [[TMP1320:%.*]] = load i16, ptr [[SD]], align 2
18319 // CHECK-NEXT:    [[TMP1321:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1319]], i16 [[TMP1320]] release monotonic, align 2
18320 // CHECK-NEXT:    [[TMP1322:%.*]] = extractvalue { i16, i1 } [[TMP1321]], 0
18321 // CHECK-NEXT:    [[TMP1323:%.*]] = extractvalue { i16, i1 } [[TMP1321]], 1
18322 // CHECK-NEXT:    br i1 [[TMP1323]], label [[SX_ATOMIC_EXIT129:%.*]], label [[SX_ATOMIC_CONT130:%.*]]
18323 // CHECK:       sx.atomic.cont130:
18324 // CHECK-NEXT:    store i16 [[TMP1322]], ptr [[SV]], align 2
18325 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT129]]
18326 // CHECK:       sx.atomic.exit129:
18327 // CHECK-NEXT:    [[TMP1324:%.*]] = extractvalue { i16, i1 } [[TMP1321]], 1
18328 // CHECK-NEXT:    [[TMP1325:%.*]] = sext i1 [[TMP1324]] to i16
18329 // CHECK-NEXT:    store i16 [[TMP1325]], ptr [[SR]], align 2
18330 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18331 // CHECK-NEXT:    [[TMP1326:%.*]] = load i16, ptr [[SE]], align 2
18332 // CHECK-NEXT:    [[TMP1327:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1326]] seq_cst, align 2
18333 // CHECK-NEXT:    store i16 [[TMP1327]], ptr [[SV]], align 2
18334 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18335 // CHECK-NEXT:    [[TMP1328:%.*]] = load i16, ptr [[SE]], align 2
18336 // CHECK-NEXT:    [[TMP1329:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1328]] seq_cst, align 2
18337 // CHECK-NEXT:    store i16 [[TMP1329]], ptr [[SV]], align 2
18338 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18339 // CHECK-NEXT:    [[TMP1330:%.*]] = load i16, ptr [[SE]], align 2
18340 // CHECK-NEXT:    [[TMP1331:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1330]] seq_cst, align 2
18341 // CHECK-NEXT:    store i16 [[TMP1331]], ptr [[SV]], align 2
18342 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18343 // CHECK-NEXT:    [[TMP1332:%.*]] = load i16, ptr [[SE]], align 2
18344 // CHECK-NEXT:    [[TMP1333:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1332]] seq_cst, align 2
18345 // CHECK-NEXT:    store i16 [[TMP1333]], ptr [[SV]], align 2
18346 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18347 // CHECK-NEXT:    [[TMP1334:%.*]] = load i16, ptr [[SE]], align 2
18348 // CHECK-NEXT:    [[TMP1335:%.*]] = load i16, ptr [[SD]], align 2
18349 // CHECK-NEXT:    [[TMP1336:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1334]], i16 [[TMP1335]] seq_cst seq_cst, align 2
18350 // CHECK-NEXT:    [[TMP1337:%.*]] = extractvalue { i16, i1 } [[TMP1336]], 0
18351 // CHECK-NEXT:    store i16 [[TMP1337]], ptr [[SV]], align 2
18352 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18353 // CHECK-NEXT:    [[TMP1338:%.*]] = load i16, ptr [[SE]], align 2
18354 // CHECK-NEXT:    [[TMP1339:%.*]] = load i16, ptr [[SD]], align 2
18355 // CHECK-NEXT:    [[TMP1340:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1338]], i16 [[TMP1339]] seq_cst seq_cst, align 2
18356 // CHECK-NEXT:    [[TMP1341:%.*]] = extractvalue { i16, i1 } [[TMP1340]], 0
18357 // CHECK-NEXT:    store i16 [[TMP1341]], ptr [[SV]], align 2
18358 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18359 // CHECK-NEXT:    [[TMP1342:%.*]] = load i16, ptr [[SE]], align 2
18360 // CHECK-NEXT:    [[TMP1343:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1342]] seq_cst, align 2
18361 // CHECK-NEXT:    [[TMP1344:%.*]] = icmp sgt i16 [[TMP1343]], [[TMP1342]]
18362 // CHECK-NEXT:    [[TMP1345:%.*]] = select i1 [[TMP1344]], i16 [[TMP1342]], i16 [[TMP1343]]
18363 // CHECK-NEXT:    store i16 [[TMP1345]], ptr [[SV]], align 2
18364 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18365 // CHECK-NEXT:    [[TMP1346:%.*]] = load i16, ptr [[SE]], align 2
18366 // CHECK-NEXT:    [[TMP1347:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1346]] seq_cst, align 2
18367 // CHECK-NEXT:    [[TMP1348:%.*]] = icmp slt i16 [[TMP1347]], [[TMP1346]]
18368 // CHECK-NEXT:    [[TMP1349:%.*]] = select i1 [[TMP1348]], i16 [[TMP1346]], i16 [[TMP1347]]
18369 // CHECK-NEXT:    store i16 [[TMP1349]], ptr [[SV]], align 2
18370 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18371 // CHECK-NEXT:    [[TMP1350:%.*]] = load i16, ptr [[SE]], align 2
18372 // CHECK-NEXT:    [[TMP1351:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1350]] seq_cst, align 2
18373 // CHECK-NEXT:    [[TMP1352:%.*]] = icmp slt i16 [[TMP1351]], [[TMP1350]]
18374 // CHECK-NEXT:    [[TMP1353:%.*]] = select i1 [[TMP1352]], i16 [[TMP1350]], i16 [[TMP1351]]
18375 // CHECK-NEXT:    store i16 [[TMP1353]], ptr [[SV]], align 2
18376 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18377 // CHECK-NEXT:    [[TMP1354:%.*]] = load i16, ptr [[SE]], align 2
18378 // CHECK-NEXT:    [[TMP1355:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1354]] seq_cst, align 2
18379 // CHECK-NEXT:    [[TMP1356:%.*]] = icmp sgt i16 [[TMP1355]], [[TMP1354]]
18380 // CHECK-NEXT:    [[TMP1357:%.*]] = select i1 [[TMP1356]], i16 [[TMP1354]], i16 [[TMP1355]]
18381 // CHECK-NEXT:    store i16 [[TMP1357]], ptr [[SV]], align 2
18382 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18383 // CHECK-NEXT:    [[TMP1358:%.*]] = load i16, ptr [[SE]], align 2
18384 // CHECK-NEXT:    [[TMP1359:%.*]] = load i16, ptr [[SD]], align 2
18385 // CHECK-NEXT:    [[TMP1360:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1358]], i16 [[TMP1359]] seq_cst seq_cst, align 2
18386 // CHECK-NEXT:    [[TMP1361:%.*]] = extractvalue { i16, i1 } [[TMP1360]], 0
18387 // CHECK-NEXT:    [[TMP1362:%.*]] = extractvalue { i16, i1 } [[TMP1360]], 1
18388 // CHECK-NEXT:    [[TMP1363:%.*]] = select i1 [[TMP1362]], i16 [[TMP1358]], i16 [[TMP1361]]
18389 // CHECK-NEXT:    store i16 [[TMP1363]], ptr [[SV]], align 2
18390 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18391 // CHECK-NEXT:    [[TMP1364:%.*]] = load i16, ptr [[SE]], align 2
18392 // CHECK-NEXT:    [[TMP1365:%.*]] = load i16, ptr [[SD]], align 2
18393 // CHECK-NEXT:    [[TMP1366:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1364]], i16 [[TMP1365]] seq_cst seq_cst, align 2
18394 // CHECK-NEXT:    [[TMP1367:%.*]] = extractvalue { i16, i1 } [[TMP1366]], 0
18395 // CHECK-NEXT:    [[TMP1368:%.*]] = extractvalue { i16, i1 } [[TMP1366]], 1
18396 // CHECK-NEXT:    [[TMP1369:%.*]] = select i1 [[TMP1368]], i16 [[TMP1364]], i16 [[TMP1367]]
18397 // CHECK-NEXT:    store i16 [[TMP1369]], ptr [[SV]], align 2
18398 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18399 // CHECK-NEXT:    [[TMP1370:%.*]] = load i16, ptr [[SE]], align 2
18400 // CHECK-NEXT:    [[TMP1371:%.*]] = load i16, ptr [[SD]], align 2
18401 // CHECK-NEXT:    [[TMP1372:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1370]], i16 [[TMP1371]] seq_cst seq_cst, align 2
18402 // CHECK-NEXT:    [[TMP1373:%.*]] = extractvalue { i16, i1 } [[TMP1372]], 0
18403 // CHECK-NEXT:    [[TMP1374:%.*]] = extractvalue { i16, i1 } [[TMP1372]], 1
18404 // CHECK-NEXT:    br i1 [[TMP1374]], label [[SX_ATOMIC_EXIT131:%.*]], label [[SX_ATOMIC_CONT132:%.*]]
18405 // CHECK:       sx.atomic.cont132:
18406 // CHECK-NEXT:    store i16 [[TMP1373]], ptr [[SV]], align 2
18407 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT131]]
18408 // CHECK:       sx.atomic.exit131:
18409 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18410 // CHECK-NEXT:    [[TMP1375:%.*]] = load i16, ptr [[SE]], align 2
18411 // CHECK-NEXT:    [[TMP1376:%.*]] = load i16, ptr [[SD]], align 2
18412 // CHECK-NEXT:    [[TMP1377:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1375]], i16 [[TMP1376]] seq_cst seq_cst, align 2
18413 // CHECK-NEXT:    [[TMP1378:%.*]] = extractvalue { i16, i1 } [[TMP1377]], 0
18414 // CHECK-NEXT:    [[TMP1379:%.*]] = extractvalue { i16, i1 } [[TMP1377]], 1
18415 // CHECK-NEXT:    br i1 [[TMP1379]], label [[SX_ATOMIC_EXIT133:%.*]], label [[SX_ATOMIC_CONT134:%.*]]
18416 // CHECK:       sx.atomic.cont134:
18417 // CHECK-NEXT:    store i16 [[TMP1378]], ptr [[SV]], align 2
18418 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT133]]
18419 // CHECK:       sx.atomic.exit133:
18420 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18421 // CHECK-NEXT:    [[TMP1380:%.*]] = load i16, ptr [[SE]], align 2
18422 // CHECK-NEXT:    [[TMP1381:%.*]] = load i16, ptr [[SD]], align 2
18423 // CHECK-NEXT:    [[TMP1382:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1380]], i16 [[TMP1381]] seq_cst seq_cst, align 2
18424 // CHECK-NEXT:    [[TMP1383:%.*]] = extractvalue { i16, i1 } [[TMP1382]], 1
18425 // CHECK-NEXT:    [[TMP1384:%.*]] = sext i1 [[TMP1383]] to i16
18426 // CHECK-NEXT:    store i16 [[TMP1384]], ptr [[SR]], align 2
18427 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18428 // CHECK-NEXT:    [[TMP1385:%.*]] = load i16, ptr [[SE]], align 2
18429 // CHECK-NEXT:    [[TMP1386:%.*]] = load i16, ptr [[SD]], align 2
18430 // CHECK-NEXT:    [[TMP1387:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1385]], i16 [[TMP1386]] seq_cst seq_cst, align 2
18431 // CHECK-NEXT:    [[TMP1388:%.*]] = extractvalue { i16, i1 } [[TMP1387]], 1
18432 // CHECK-NEXT:    [[TMP1389:%.*]] = sext i1 [[TMP1388]] to i16
18433 // CHECK-NEXT:    store i16 [[TMP1389]], ptr [[SR]], align 2
18434 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18435 // CHECK-NEXT:    [[TMP1390:%.*]] = load i16, ptr [[SE]], align 2
18436 // CHECK-NEXT:    [[TMP1391:%.*]] = load i16, ptr [[SD]], align 2
18437 // CHECK-NEXT:    [[TMP1392:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1390]], i16 [[TMP1391]] seq_cst seq_cst, align 2
18438 // CHECK-NEXT:    [[TMP1393:%.*]] = extractvalue { i16, i1 } [[TMP1392]], 0
18439 // CHECK-NEXT:    [[TMP1394:%.*]] = extractvalue { i16, i1 } [[TMP1392]], 1
18440 // CHECK-NEXT:    br i1 [[TMP1394]], label [[SX_ATOMIC_EXIT135:%.*]], label [[SX_ATOMIC_CONT136:%.*]]
18441 // CHECK:       sx.atomic.cont136:
18442 // CHECK-NEXT:    store i16 [[TMP1393]], ptr [[SV]], align 2
18443 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT135]]
18444 // CHECK:       sx.atomic.exit135:
18445 // CHECK-NEXT:    [[TMP1395:%.*]] = extractvalue { i16, i1 } [[TMP1392]], 1
18446 // CHECK-NEXT:    [[TMP1396:%.*]] = sext i1 [[TMP1395]] to i16
18447 // CHECK-NEXT:    store i16 [[TMP1396]], ptr [[SR]], align 2
18448 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18449 // CHECK-NEXT:    [[TMP1397:%.*]] = load i16, ptr [[SE]], align 2
18450 // CHECK-NEXT:    [[TMP1398:%.*]] = load i16, ptr [[SD]], align 2
18451 // CHECK-NEXT:    [[TMP1399:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1397]], i16 [[TMP1398]] seq_cst seq_cst, align 2
18452 // CHECK-NEXT:    [[TMP1400:%.*]] = extractvalue { i16, i1 } [[TMP1399]], 0
18453 // CHECK-NEXT:    [[TMP1401:%.*]] = extractvalue { i16, i1 } [[TMP1399]], 1
18454 // CHECK-NEXT:    br i1 [[TMP1401]], label [[SX_ATOMIC_EXIT137:%.*]], label [[SX_ATOMIC_CONT138:%.*]]
18455 // CHECK:       sx.atomic.cont138:
18456 // CHECK-NEXT:    store i16 [[TMP1400]], ptr [[SV]], align 2
18457 // CHECK-NEXT:    br label [[SX_ATOMIC_EXIT137]]
18458 // CHECK:       sx.atomic.exit137:
18459 // CHECK-NEXT:    [[TMP1402:%.*]] = extractvalue { i16, i1 } [[TMP1399]], 1
18460 // CHECK-NEXT:    [[TMP1403:%.*]] = sext i1 [[TMP1402]] to i16
18461 // CHECK-NEXT:    store i16 [[TMP1403]], ptr [[SR]], align 2
18462 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18463 // CHECK-NEXT:    [[TMP1404:%.*]] = load i16, ptr [[USE]], align 2
18464 // CHECK-NEXT:    [[TMP1405:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1404]] monotonic, align 2
18465 // CHECK-NEXT:    store i16 [[TMP1405]], ptr [[USV]], align 2
18466 // CHECK-NEXT:    [[TMP1406:%.*]] = load i16, ptr [[USE]], align 2
18467 // CHECK-NEXT:    [[TMP1407:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1406]] monotonic, align 2
18468 // CHECK-NEXT:    store i16 [[TMP1407]], ptr [[USV]], align 2
18469 // CHECK-NEXT:    [[TMP1408:%.*]] = load i16, ptr [[USE]], align 2
18470 // CHECK-NEXT:    [[TMP1409:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1408]] monotonic, align 2
18471 // CHECK-NEXT:    store i16 [[TMP1409]], ptr [[USV]], align 2
18472 // CHECK-NEXT:    [[TMP1410:%.*]] = load i16, ptr [[USE]], align 2
18473 // CHECK-NEXT:    [[TMP1411:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1410]] monotonic, align 2
18474 // CHECK-NEXT:    store i16 [[TMP1411]], ptr [[USV]], align 2
18475 // CHECK-NEXT:    [[TMP1412:%.*]] = load i16, ptr [[USE]], align 2
18476 // CHECK-NEXT:    [[TMP1413:%.*]] = load i16, ptr [[USD]], align 2
18477 // CHECK-NEXT:    [[TMP1414:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1412]], i16 [[TMP1413]] monotonic monotonic, align 2
18478 // CHECK-NEXT:    [[TMP1415:%.*]] = extractvalue { i16, i1 } [[TMP1414]], 0
18479 // CHECK-NEXT:    store i16 [[TMP1415]], ptr [[USV]], align 2
18480 // CHECK-NEXT:    [[TMP1416:%.*]] = load i16, ptr [[USE]], align 2
18481 // CHECK-NEXT:    [[TMP1417:%.*]] = load i16, ptr [[USD]], align 2
18482 // CHECK-NEXT:    [[TMP1418:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1416]], i16 [[TMP1417]] monotonic monotonic, align 2
18483 // CHECK-NEXT:    [[TMP1419:%.*]] = extractvalue { i16, i1 } [[TMP1418]], 0
18484 // CHECK-NEXT:    store i16 [[TMP1419]], ptr [[USV]], align 2
18485 // CHECK-NEXT:    [[TMP1420:%.*]] = load i16, ptr [[USE]], align 2
18486 // CHECK-NEXT:    [[TMP1421:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1420]] monotonic, align 2
18487 // CHECK-NEXT:    [[TMP1422:%.*]] = icmp ugt i16 [[TMP1421]], [[TMP1420]]
18488 // CHECK-NEXT:    [[TMP1423:%.*]] = select i1 [[TMP1422]], i16 [[TMP1420]], i16 [[TMP1421]]
18489 // CHECK-NEXT:    store i16 [[TMP1423]], ptr [[USV]], align 2
18490 // CHECK-NEXT:    [[TMP1424:%.*]] = load i16, ptr [[USE]], align 2
18491 // CHECK-NEXT:    [[TMP1425:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1424]] monotonic, align 2
18492 // CHECK-NEXT:    [[TMP1426:%.*]] = icmp ult i16 [[TMP1425]], [[TMP1424]]
18493 // CHECK-NEXT:    [[TMP1427:%.*]] = select i1 [[TMP1426]], i16 [[TMP1424]], i16 [[TMP1425]]
18494 // CHECK-NEXT:    store i16 [[TMP1427]], ptr [[USV]], align 2
18495 // CHECK-NEXT:    [[TMP1428:%.*]] = load i16, ptr [[USE]], align 2
18496 // CHECK-NEXT:    [[TMP1429:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1428]] monotonic, align 2
18497 // CHECK-NEXT:    [[TMP1430:%.*]] = icmp ult i16 [[TMP1429]], [[TMP1428]]
18498 // CHECK-NEXT:    [[TMP1431:%.*]] = select i1 [[TMP1430]], i16 [[TMP1428]], i16 [[TMP1429]]
18499 // CHECK-NEXT:    store i16 [[TMP1431]], ptr [[USV]], align 2
18500 // CHECK-NEXT:    [[TMP1432:%.*]] = load i16, ptr [[USE]], align 2
18501 // CHECK-NEXT:    [[TMP1433:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1432]] monotonic, align 2
18502 // CHECK-NEXT:    [[TMP1434:%.*]] = icmp ugt i16 [[TMP1433]], [[TMP1432]]
18503 // CHECK-NEXT:    [[TMP1435:%.*]] = select i1 [[TMP1434]], i16 [[TMP1432]], i16 [[TMP1433]]
18504 // CHECK-NEXT:    store i16 [[TMP1435]], ptr [[USV]], align 2
18505 // CHECK-NEXT:    [[TMP1436:%.*]] = load i16, ptr [[USE]], align 2
18506 // CHECK-NEXT:    [[TMP1437:%.*]] = load i16, ptr [[USD]], align 2
18507 // CHECK-NEXT:    [[TMP1438:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1436]], i16 [[TMP1437]] monotonic monotonic, align 2
18508 // CHECK-NEXT:    [[TMP1439:%.*]] = extractvalue { i16, i1 } [[TMP1438]], 0
18509 // CHECK-NEXT:    [[TMP1440:%.*]] = extractvalue { i16, i1 } [[TMP1438]], 1
18510 // CHECK-NEXT:    [[TMP1441:%.*]] = select i1 [[TMP1440]], i16 [[TMP1436]], i16 [[TMP1439]]
18511 // CHECK-NEXT:    store i16 [[TMP1441]], ptr [[USV]], align 2
18512 // CHECK-NEXT:    [[TMP1442:%.*]] = load i16, ptr [[USE]], align 2
18513 // CHECK-NEXT:    [[TMP1443:%.*]] = load i16, ptr [[USD]], align 2
18514 // CHECK-NEXT:    [[TMP1444:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1442]], i16 [[TMP1443]] monotonic monotonic, align 2
18515 // CHECK-NEXT:    [[TMP1445:%.*]] = extractvalue { i16, i1 } [[TMP1444]], 0
18516 // CHECK-NEXT:    [[TMP1446:%.*]] = extractvalue { i16, i1 } [[TMP1444]], 1
18517 // CHECK-NEXT:    [[TMP1447:%.*]] = select i1 [[TMP1446]], i16 [[TMP1442]], i16 [[TMP1445]]
18518 // CHECK-NEXT:    store i16 [[TMP1447]], ptr [[USV]], align 2
18519 // CHECK-NEXT:    [[TMP1448:%.*]] = load i16, ptr [[USE]], align 2
18520 // CHECK-NEXT:    [[TMP1449:%.*]] = load i16, ptr [[USD]], align 2
18521 // CHECK-NEXT:    [[TMP1450:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1448]], i16 [[TMP1449]] monotonic monotonic, align 2
18522 // CHECK-NEXT:    [[TMP1451:%.*]] = extractvalue { i16, i1 } [[TMP1450]], 0
18523 // CHECK-NEXT:    [[TMP1452:%.*]] = extractvalue { i16, i1 } [[TMP1450]], 1
18524 // CHECK-NEXT:    br i1 [[TMP1452]], label [[USX_ATOMIC_EXIT:%.*]], label [[USX_ATOMIC_CONT:%.*]]
18525 // CHECK:       usx.atomic.cont:
18526 // CHECK-NEXT:    store i16 [[TMP1451]], ptr [[USV]], align 2
18527 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT]]
18528 // CHECK:       usx.atomic.exit:
18529 // CHECK-NEXT:    [[TMP1453:%.*]] = load i16, ptr [[USE]], align 2
18530 // CHECK-NEXT:    [[TMP1454:%.*]] = load i16, ptr [[USD]], align 2
18531 // CHECK-NEXT:    [[TMP1455:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1453]], i16 [[TMP1454]] monotonic monotonic, align 2
18532 // CHECK-NEXT:    [[TMP1456:%.*]] = extractvalue { i16, i1 } [[TMP1455]], 0
18533 // CHECK-NEXT:    [[TMP1457:%.*]] = extractvalue { i16, i1 } [[TMP1455]], 1
18534 // CHECK-NEXT:    br i1 [[TMP1457]], label [[USX_ATOMIC_EXIT139:%.*]], label [[USX_ATOMIC_CONT140:%.*]]
18535 // CHECK:       usx.atomic.cont140:
18536 // CHECK-NEXT:    store i16 [[TMP1456]], ptr [[USV]], align 2
18537 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT139]]
18538 // CHECK:       usx.atomic.exit139:
18539 // CHECK-NEXT:    [[TMP1458:%.*]] = load i16, ptr [[USE]], align 2
18540 // CHECK-NEXT:    [[TMP1459:%.*]] = load i16, ptr [[USD]], align 2
18541 // CHECK-NEXT:    [[TMP1460:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1458]], i16 [[TMP1459]] monotonic monotonic, align 2
18542 // CHECK-NEXT:    [[TMP1461:%.*]] = extractvalue { i16, i1 } [[TMP1460]], 1
18543 // CHECK-NEXT:    [[TMP1462:%.*]] = zext i1 [[TMP1461]] to i16
18544 // CHECK-NEXT:    store i16 [[TMP1462]], ptr [[USR]], align 2
18545 // CHECK-NEXT:    [[TMP1463:%.*]] = load i16, ptr [[USE]], align 2
18546 // CHECK-NEXT:    [[TMP1464:%.*]] = load i16, ptr [[USD]], align 2
18547 // CHECK-NEXT:    [[TMP1465:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1463]], i16 [[TMP1464]] monotonic monotonic, align 2
18548 // CHECK-NEXT:    [[TMP1466:%.*]] = extractvalue { i16, i1 } [[TMP1465]], 1
18549 // CHECK-NEXT:    [[TMP1467:%.*]] = zext i1 [[TMP1466]] to i16
18550 // CHECK-NEXT:    store i16 [[TMP1467]], ptr [[USR]], align 2
18551 // CHECK-NEXT:    [[TMP1468:%.*]] = load i16, ptr [[USE]], align 2
18552 // CHECK-NEXT:    [[TMP1469:%.*]] = load i16, ptr [[USD]], align 2
18553 // CHECK-NEXT:    [[TMP1470:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1468]], i16 [[TMP1469]] monotonic monotonic, align 2
18554 // CHECK-NEXT:    [[TMP1471:%.*]] = extractvalue { i16, i1 } [[TMP1470]], 0
18555 // CHECK-NEXT:    [[TMP1472:%.*]] = extractvalue { i16, i1 } [[TMP1470]], 1
18556 // CHECK-NEXT:    br i1 [[TMP1472]], label [[USX_ATOMIC_EXIT141:%.*]], label [[USX_ATOMIC_CONT142:%.*]]
18557 // CHECK:       usx.atomic.cont142:
18558 // CHECK-NEXT:    store i16 [[TMP1471]], ptr [[USV]], align 2
18559 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT141]]
18560 // CHECK:       usx.atomic.exit141:
18561 // CHECK-NEXT:    [[TMP1473:%.*]] = extractvalue { i16, i1 } [[TMP1470]], 1
18562 // CHECK-NEXT:    [[TMP1474:%.*]] = zext i1 [[TMP1473]] to i16
18563 // CHECK-NEXT:    store i16 [[TMP1474]], ptr [[USR]], align 2
18564 // CHECK-NEXT:    [[TMP1475:%.*]] = load i16, ptr [[USE]], align 2
18565 // CHECK-NEXT:    [[TMP1476:%.*]] = load i16, ptr [[USD]], align 2
18566 // CHECK-NEXT:    [[TMP1477:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1475]], i16 [[TMP1476]] monotonic monotonic, align 2
18567 // CHECK-NEXT:    [[TMP1478:%.*]] = extractvalue { i16, i1 } [[TMP1477]], 0
18568 // CHECK-NEXT:    [[TMP1479:%.*]] = extractvalue { i16, i1 } [[TMP1477]], 1
18569 // CHECK-NEXT:    br i1 [[TMP1479]], label [[USX_ATOMIC_EXIT143:%.*]], label [[USX_ATOMIC_CONT144:%.*]]
18570 // CHECK:       usx.atomic.cont144:
18571 // CHECK-NEXT:    store i16 [[TMP1478]], ptr [[USV]], align 2
18572 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT143]]
18573 // CHECK:       usx.atomic.exit143:
18574 // CHECK-NEXT:    [[TMP1480:%.*]] = extractvalue { i16, i1 } [[TMP1477]], 1
18575 // CHECK-NEXT:    [[TMP1481:%.*]] = zext i1 [[TMP1480]] to i16
18576 // CHECK-NEXT:    store i16 [[TMP1481]], ptr [[USR]], align 2
18577 // CHECK-NEXT:    [[TMP1482:%.*]] = load i16, ptr [[USE]], align 2
18578 // CHECK-NEXT:    [[TMP1483:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1482]] acq_rel, align 2
18579 // CHECK-NEXT:    store i16 [[TMP1483]], ptr [[USV]], align 2
18580 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18581 // CHECK-NEXT:    [[TMP1484:%.*]] = load i16, ptr [[USE]], align 2
18582 // CHECK-NEXT:    [[TMP1485:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1484]] acq_rel, align 2
18583 // CHECK-NEXT:    store i16 [[TMP1485]], ptr [[USV]], align 2
18584 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18585 // CHECK-NEXT:    [[TMP1486:%.*]] = load i16, ptr [[USE]], align 2
18586 // CHECK-NEXT:    [[TMP1487:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1486]] acq_rel, align 2
18587 // CHECK-NEXT:    store i16 [[TMP1487]], ptr [[USV]], align 2
18588 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18589 // CHECK-NEXT:    [[TMP1488:%.*]] = load i16, ptr [[USE]], align 2
18590 // CHECK-NEXT:    [[TMP1489:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1488]] acq_rel, align 2
18591 // CHECK-NEXT:    store i16 [[TMP1489]], ptr [[USV]], align 2
18592 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18593 // CHECK-NEXT:    [[TMP1490:%.*]] = load i16, ptr [[USE]], align 2
18594 // CHECK-NEXT:    [[TMP1491:%.*]] = load i16, ptr [[USD]], align 2
18595 // CHECK-NEXT:    [[TMP1492:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1490]], i16 [[TMP1491]] acq_rel acquire, align 2
18596 // CHECK-NEXT:    [[TMP1493:%.*]] = extractvalue { i16, i1 } [[TMP1492]], 0
18597 // CHECK-NEXT:    store i16 [[TMP1493]], ptr [[USV]], align 2
18598 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18599 // CHECK-NEXT:    [[TMP1494:%.*]] = load i16, ptr [[USE]], align 2
18600 // CHECK-NEXT:    [[TMP1495:%.*]] = load i16, ptr [[USD]], align 2
18601 // CHECK-NEXT:    [[TMP1496:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1494]], i16 [[TMP1495]] acq_rel acquire, align 2
18602 // CHECK-NEXT:    [[TMP1497:%.*]] = extractvalue { i16, i1 } [[TMP1496]], 0
18603 // CHECK-NEXT:    store i16 [[TMP1497]], ptr [[USV]], align 2
18604 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18605 // CHECK-NEXT:    [[TMP1498:%.*]] = load i16, ptr [[USE]], align 2
18606 // CHECK-NEXT:    [[TMP1499:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1498]] acq_rel, align 2
18607 // CHECK-NEXT:    [[TMP1500:%.*]] = icmp ugt i16 [[TMP1499]], [[TMP1498]]
18608 // CHECK-NEXT:    [[TMP1501:%.*]] = select i1 [[TMP1500]], i16 [[TMP1498]], i16 [[TMP1499]]
18609 // CHECK-NEXT:    store i16 [[TMP1501]], ptr [[USV]], align 2
18610 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18611 // CHECK-NEXT:    [[TMP1502:%.*]] = load i16, ptr [[USE]], align 2
18612 // CHECK-NEXT:    [[TMP1503:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1502]] acq_rel, align 2
18613 // CHECK-NEXT:    [[TMP1504:%.*]] = icmp ult i16 [[TMP1503]], [[TMP1502]]
18614 // CHECK-NEXT:    [[TMP1505:%.*]] = select i1 [[TMP1504]], i16 [[TMP1502]], i16 [[TMP1503]]
18615 // CHECK-NEXT:    store i16 [[TMP1505]], ptr [[USV]], align 2
18616 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18617 // CHECK-NEXT:    [[TMP1506:%.*]] = load i16, ptr [[USE]], align 2
18618 // CHECK-NEXT:    [[TMP1507:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1506]] acq_rel, align 2
18619 // CHECK-NEXT:    [[TMP1508:%.*]] = icmp ult i16 [[TMP1507]], [[TMP1506]]
18620 // CHECK-NEXT:    [[TMP1509:%.*]] = select i1 [[TMP1508]], i16 [[TMP1506]], i16 [[TMP1507]]
18621 // CHECK-NEXT:    store i16 [[TMP1509]], ptr [[USV]], align 2
18622 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18623 // CHECK-NEXT:    [[TMP1510:%.*]] = load i16, ptr [[USE]], align 2
18624 // CHECK-NEXT:    [[TMP1511:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1510]] acq_rel, align 2
18625 // CHECK-NEXT:    [[TMP1512:%.*]] = icmp ugt i16 [[TMP1511]], [[TMP1510]]
18626 // CHECK-NEXT:    [[TMP1513:%.*]] = select i1 [[TMP1512]], i16 [[TMP1510]], i16 [[TMP1511]]
18627 // CHECK-NEXT:    store i16 [[TMP1513]], ptr [[USV]], align 2
18628 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18629 // CHECK-NEXT:    [[TMP1514:%.*]] = load i16, ptr [[USE]], align 2
18630 // CHECK-NEXT:    [[TMP1515:%.*]] = load i16, ptr [[USD]], align 2
18631 // CHECK-NEXT:    [[TMP1516:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1514]], i16 [[TMP1515]] acq_rel acquire, align 2
18632 // CHECK-NEXT:    [[TMP1517:%.*]] = extractvalue { i16, i1 } [[TMP1516]], 0
18633 // CHECK-NEXT:    [[TMP1518:%.*]] = extractvalue { i16, i1 } [[TMP1516]], 1
18634 // CHECK-NEXT:    [[TMP1519:%.*]] = select i1 [[TMP1518]], i16 [[TMP1514]], i16 [[TMP1517]]
18635 // CHECK-NEXT:    store i16 [[TMP1519]], ptr [[USV]], align 2
18636 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18637 // CHECK-NEXT:    [[TMP1520:%.*]] = load i16, ptr [[USE]], align 2
18638 // CHECK-NEXT:    [[TMP1521:%.*]] = load i16, ptr [[USD]], align 2
18639 // CHECK-NEXT:    [[TMP1522:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1520]], i16 [[TMP1521]] acq_rel acquire, align 2
18640 // CHECK-NEXT:    [[TMP1523:%.*]] = extractvalue { i16, i1 } [[TMP1522]], 0
18641 // CHECK-NEXT:    [[TMP1524:%.*]] = extractvalue { i16, i1 } [[TMP1522]], 1
18642 // CHECK-NEXT:    [[TMP1525:%.*]] = select i1 [[TMP1524]], i16 [[TMP1520]], i16 [[TMP1523]]
18643 // CHECK-NEXT:    store i16 [[TMP1525]], ptr [[USV]], align 2
18644 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18645 // CHECK-NEXT:    [[TMP1526:%.*]] = load i16, ptr [[USE]], align 2
18646 // CHECK-NEXT:    [[TMP1527:%.*]] = load i16, ptr [[USD]], align 2
18647 // CHECK-NEXT:    [[TMP1528:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1526]], i16 [[TMP1527]] acq_rel acquire, align 2
18648 // CHECK-NEXT:    [[TMP1529:%.*]] = extractvalue { i16, i1 } [[TMP1528]], 0
18649 // CHECK-NEXT:    [[TMP1530:%.*]] = extractvalue { i16, i1 } [[TMP1528]], 1
18650 // CHECK-NEXT:    br i1 [[TMP1530]], label [[USX_ATOMIC_EXIT145:%.*]], label [[USX_ATOMIC_CONT146:%.*]]
18651 // CHECK:       usx.atomic.cont146:
18652 // CHECK-NEXT:    store i16 [[TMP1529]], ptr [[USV]], align 2
18653 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT145]]
18654 // CHECK:       usx.atomic.exit145:
18655 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18656 // CHECK-NEXT:    [[TMP1531:%.*]] = load i16, ptr [[USE]], align 2
18657 // CHECK-NEXT:    [[TMP1532:%.*]] = load i16, ptr [[USD]], align 2
18658 // CHECK-NEXT:    [[TMP1533:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1531]], i16 [[TMP1532]] acq_rel acquire, align 2
18659 // CHECK-NEXT:    [[TMP1534:%.*]] = extractvalue { i16, i1 } [[TMP1533]], 0
18660 // CHECK-NEXT:    [[TMP1535:%.*]] = extractvalue { i16, i1 } [[TMP1533]], 1
18661 // CHECK-NEXT:    br i1 [[TMP1535]], label [[USX_ATOMIC_EXIT147:%.*]], label [[USX_ATOMIC_CONT148:%.*]]
18662 // CHECK:       usx.atomic.cont148:
18663 // CHECK-NEXT:    store i16 [[TMP1534]], ptr [[USV]], align 2
18664 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT147]]
18665 // CHECK:       usx.atomic.exit147:
18666 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18667 // CHECK-NEXT:    [[TMP1536:%.*]] = load i16, ptr [[USE]], align 2
18668 // CHECK-NEXT:    [[TMP1537:%.*]] = load i16, ptr [[USD]], align 2
18669 // CHECK-NEXT:    [[TMP1538:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1536]], i16 [[TMP1537]] acq_rel acquire, align 2
18670 // CHECK-NEXT:    [[TMP1539:%.*]] = extractvalue { i16, i1 } [[TMP1538]], 1
18671 // CHECK-NEXT:    [[TMP1540:%.*]] = zext i1 [[TMP1539]] to i16
18672 // CHECK-NEXT:    store i16 [[TMP1540]], ptr [[USR]], align 2
18673 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18674 // CHECK-NEXT:    [[TMP1541:%.*]] = load i16, ptr [[USE]], align 2
18675 // CHECK-NEXT:    [[TMP1542:%.*]] = load i16, ptr [[USD]], align 2
18676 // CHECK-NEXT:    [[TMP1543:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1541]], i16 [[TMP1542]] acq_rel acquire, align 2
18677 // CHECK-NEXT:    [[TMP1544:%.*]] = extractvalue { i16, i1 } [[TMP1543]], 1
18678 // CHECK-NEXT:    [[TMP1545:%.*]] = zext i1 [[TMP1544]] to i16
18679 // CHECK-NEXT:    store i16 [[TMP1545]], ptr [[USR]], align 2
18680 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18681 // CHECK-NEXT:    [[TMP1546:%.*]] = load i16, ptr [[USE]], align 2
18682 // CHECK-NEXT:    [[TMP1547:%.*]] = load i16, ptr [[USD]], align 2
18683 // CHECK-NEXT:    [[TMP1548:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1546]], i16 [[TMP1547]] acq_rel acquire, align 2
18684 // CHECK-NEXT:    [[TMP1549:%.*]] = extractvalue { i16, i1 } [[TMP1548]], 0
18685 // CHECK-NEXT:    [[TMP1550:%.*]] = extractvalue { i16, i1 } [[TMP1548]], 1
18686 // CHECK-NEXT:    br i1 [[TMP1550]], label [[USX_ATOMIC_EXIT149:%.*]], label [[USX_ATOMIC_CONT150:%.*]]
18687 // CHECK:       usx.atomic.cont150:
18688 // CHECK-NEXT:    store i16 [[TMP1549]], ptr [[USV]], align 2
18689 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT149]]
18690 // CHECK:       usx.atomic.exit149:
18691 // CHECK-NEXT:    [[TMP1551:%.*]] = extractvalue { i16, i1 } [[TMP1548]], 1
18692 // CHECK-NEXT:    [[TMP1552:%.*]] = zext i1 [[TMP1551]] to i16
18693 // CHECK-NEXT:    store i16 [[TMP1552]], ptr [[USR]], align 2
18694 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18695 // CHECK-NEXT:    [[TMP1553:%.*]] = load i16, ptr [[USE]], align 2
18696 // CHECK-NEXT:    [[TMP1554:%.*]] = load i16, ptr [[USD]], align 2
18697 // CHECK-NEXT:    [[TMP1555:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1553]], i16 [[TMP1554]] acq_rel acquire, align 2
18698 // CHECK-NEXT:    [[TMP1556:%.*]] = extractvalue { i16, i1 } [[TMP1555]], 0
18699 // CHECK-NEXT:    [[TMP1557:%.*]] = extractvalue { i16, i1 } [[TMP1555]], 1
18700 // CHECK-NEXT:    br i1 [[TMP1557]], label [[USX_ATOMIC_EXIT151:%.*]], label [[USX_ATOMIC_CONT152:%.*]]
18701 // CHECK:       usx.atomic.cont152:
18702 // CHECK-NEXT:    store i16 [[TMP1556]], ptr [[USV]], align 2
18703 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT151]]
18704 // CHECK:       usx.atomic.exit151:
18705 // CHECK-NEXT:    [[TMP1558:%.*]] = extractvalue { i16, i1 } [[TMP1555]], 1
18706 // CHECK-NEXT:    [[TMP1559:%.*]] = zext i1 [[TMP1558]] to i16
18707 // CHECK-NEXT:    store i16 [[TMP1559]], ptr [[USR]], align 2
18708 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18709 // CHECK-NEXT:    [[TMP1560:%.*]] = load i16, ptr [[USE]], align 2
18710 // CHECK-NEXT:    [[TMP1561:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1560]] acquire, align 2
18711 // CHECK-NEXT:    store i16 [[TMP1561]], ptr [[USV]], align 2
18712 // CHECK-NEXT:    [[TMP1562:%.*]] = load i16, ptr [[USE]], align 2
18713 // CHECK-NEXT:    [[TMP1563:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1562]] acquire, align 2
18714 // CHECK-NEXT:    store i16 [[TMP1563]], ptr [[USV]], align 2
18715 // CHECK-NEXT:    [[TMP1564:%.*]] = load i16, ptr [[USE]], align 2
18716 // CHECK-NEXT:    [[TMP1565:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1564]] acquire, align 2
18717 // CHECK-NEXT:    store i16 [[TMP1565]], ptr [[USV]], align 2
18718 // CHECK-NEXT:    [[TMP1566:%.*]] = load i16, ptr [[USE]], align 2
18719 // CHECK-NEXT:    [[TMP1567:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1566]] acquire, align 2
18720 // CHECK-NEXT:    store i16 [[TMP1567]], ptr [[USV]], align 2
18721 // CHECK-NEXT:    [[TMP1568:%.*]] = load i16, ptr [[USE]], align 2
18722 // CHECK-NEXT:    [[TMP1569:%.*]] = load i16, ptr [[USD]], align 2
18723 // CHECK-NEXT:    [[TMP1570:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1568]], i16 [[TMP1569]] acquire acquire, align 2
18724 // CHECK-NEXT:    [[TMP1571:%.*]] = extractvalue { i16, i1 } [[TMP1570]], 0
18725 // CHECK-NEXT:    store i16 [[TMP1571]], ptr [[USV]], align 2
18726 // CHECK-NEXT:    [[TMP1572:%.*]] = load i16, ptr [[USE]], align 2
18727 // CHECK-NEXT:    [[TMP1573:%.*]] = load i16, ptr [[USD]], align 2
18728 // CHECK-NEXT:    [[TMP1574:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1572]], i16 [[TMP1573]] acquire acquire, align 2
18729 // CHECK-NEXT:    [[TMP1575:%.*]] = extractvalue { i16, i1 } [[TMP1574]], 0
18730 // CHECK-NEXT:    store i16 [[TMP1575]], ptr [[USV]], align 2
18731 // CHECK-NEXT:    [[TMP1576:%.*]] = load i16, ptr [[USE]], align 2
18732 // CHECK-NEXT:    [[TMP1577:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1576]] acquire, align 2
18733 // CHECK-NEXT:    [[TMP1578:%.*]] = icmp ugt i16 [[TMP1577]], [[TMP1576]]
18734 // CHECK-NEXT:    [[TMP1579:%.*]] = select i1 [[TMP1578]], i16 [[TMP1576]], i16 [[TMP1577]]
18735 // CHECK-NEXT:    store i16 [[TMP1579]], ptr [[USV]], align 2
18736 // CHECK-NEXT:    [[TMP1580:%.*]] = load i16, ptr [[USE]], align 2
18737 // CHECK-NEXT:    [[TMP1581:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1580]] acquire, align 2
18738 // CHECK-NEXT:    [[TMP1582:%.*]] = icmp ult i16 [[TMP1581]], [[TMP1580]]
18739 // CHECK-NEXT:    [[TMP1583:%.*]] = select i1 [[TMP1582]], i16 [[TMP1580]], i16 [[TMP1581]]
18740 // CHECK-NEXT:    store i16 [[TMP1583]], ptr [[USV]], align 2
18741 // CHECK-NEXT:    [[TMP1584:%.*]] = load i16, ptr [[USE]], align 2
18742 // CHECK-NEXT:    [[TMP1585:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1584]] acquire, align 2
18743 // CHECK-NEXT:    [[TMP1586:%.*]] = icmp ult i16 [[TMP1585]], [[TMP1584]]
18744 // CHECK-NEXT:    [[TMP1587:%.*]] = select i1 [[TMP1586]], i16 [[TMP1584]], i16 [[TMP1585]]
18745 // CHECK-NEXT:    store i16 [[TMP1587]], ptr [[USV]], align 2
18746 // CHECK-NEXT:    [[TMP1588:%.*]] = load i16, ptr [[USE]], align 2
18747 // CHECK-NEXT:    [[TMP1589:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1588]] acquire, align 2
18748 // CHECK-NEXT:    [[TMP1590:%.*]] = icmp ugt i16 [[TMP1589]], [[TMP1588]]
18749 // CHECK-NEXT:    [[TMP1591:%.*]] = select i1 [[TMP1590]], i16 [[TMP1588]], i16 [[TMP1589]]
18750 // CHECK-NEXT:    store i16 [[TMP1591]], ptr [[USV]], align 2
18751 // CHECK-NEXT:    [[TMP1592:%.*]] = load i16, ptr [[USE]], align 2
18752 // CHECK-NEXT:    [[TMP1593:%.*]] = load i16, ptr [[USD]], align 2
18753 // CHECK-NEXT:    [[TMP1594:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1592]], i16 [[TMP1593]] acquire acquire, align 2
18754 // CHECK-NEXT:    [[TMP1595:%.*]] = extractvalue { i16, i1 } [[TMP1594]], 0
18755 // CHECK-NEXT:    [[TMP1596:%.*]] = extractvalue { i16, i1 } [[TMP1594]], 1
18756 // CHECK-NEXT:    [[TMP1597:%.*]] = select i1 [[TMP1596]], i16 [[TMP1592]], i16 [[TMP1595]]
18757 // CHECK-NEXT:    store i16 [[TMP1597]], ptr [[USV]], align 2
18758 // CHECK-NEXT:    [[TMP1598:%.*]] = load i16, ptr [[USE]], align 2
18759 // CHECK-NEXT:    [[TMP1599:%.*]] = load i16, ptr [[USD]], align 2
18760 // CHECK-NEXT:    [[TMP1600:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1598]], i16 [[TMP1599]] acquire acquire, align 2
18761 // CHECK-NEXT:    [[TMP1601:%.*]] = extractvalue { i16, i1 } [[TMP1600]], 0
18762 // CHECK-NEXT:    [[TMP1602:%.*]] = extractvalue { i16, i1 } [[TMP1600]], 1
18763 // CHECK-NEXT:    [[TMP1603:%.*]] = select i1 [[TMP1602]], i16 [[TMP1598]], i16 [[TMP1601]]
18764 // CHECK-NEXT:    store i16 [[TMP1603]], ptr [[USV]], align 2
18765 // CHECK-NEXT:    [[TMP1604:%.*]] = load i16, ptr [[USE]], align 2
18766 // CHECK-NEXT:    [[TMP1605:%.*]] = load i16, ptr [[USD]], align 2
18767 // CHECK-NEXT:    [[TMP1606:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1604]], i16 [[TMP1605]] acquire acquire, align 2
18768 // CHECK-NEXT:    [[TMP1607:%.*]] = extractvalue { i16, i1 } [[TMP1606]], 0
18769 // CHECK-NEXT:    [[TMP1608:%.*]] = extractvalue { i16, i1 } [[TMP1606]], 1
18770 // CHECK-NEXT:    br i1 [[TMP1608]], label [[USX_ATOMIC_EXIT153:%.*]], label [[USX_ATOMIC_CONT154:%.*]]
18771 // CHECK:       usx.atomic.cont154:
18772 // CHECK-NEXT:    store i16 [[TMP1607]], ptr [[USV]], align 2
18773 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT153]]
18774 // CHECK:       usx.atomic.exit153:
18775 // CHECK-NEXT:    [[TMP1609:%.*]] = load i16, ptr [[USE]], align 2
18776 // CHECK-NEXT:    [[TMP1610:%.*]] = load i16, ptr [[USD]], align 2
18777 // CHECK-NEXT:    [[TMP1611:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1609]], i16 [[TMP1610]] acquire acquire, align 2
18778 // CHECK-NEXT:    [[TMP1612:%.*]] = extractvalue { i16, i1 } [[TMP1611]], 0
18779 // CHECK-NEXT:    [[TMP1613:%.*]] = extractvalue { i16, i1 } [[TMP1611]], 1
18780 // CHECK-NEXT:    br i1 [[TMP1613]], label [[USX_ATOMIC_EXIT155:%.*]], label [[USX_ATOMIC_CONT156:%.*]]
18781 // CHECK:       usx.atomic.cont156:
18782 // CHECK-NEXT:    store i16 [[TMP1612]], ptr [[USV]], align 2
18783 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT155]]
18784 // CHECK:       usx.atomic.exit155:
18785 // CHECK-NEXT:    [[TMP1614:%.*]] = load i16, ptr [[USE]], align 2
18786 // CHECK-NEXT:    [[TMP1615:%.*]] = load i16, ptr [[USD]], align 2
18787 // CHECK-NEXT:    [[TMP1616:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1614]], i16 [[TMP1615]] acquire acquire, align 2
18788 // CHECK-NEXT:    [[TMP1617:%.*]] = extractvalue { i16, i1 } [[TMP1616]], 1
18789 // CHECK-NEXT:    [[TMP1618:%.*]] = zext i1 [[TMP1617]] to i16
18790 // CHECK-NEXT:    store i16 [[TMP1618]], ptr [[USR]], align 2
18791 // CHECK-NEXT:    [[TMP1619:%.*]] = load i16, ptr [[USE]], align 2
18792 // CHECK-NEXT:    [[TMP1620:%.*]] = load i16, ptr [[USD]], align 2
18793 // CHECK-NEXT:    [[TMP1621:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1619]], i16 [[TMP1620]] acquire acquire, align 2
18794 // CHECK-NEXT:    [[TMP1622:%.*]] = extractvalue { i16, i1 } [[TMP1621]], 1
18795 // CHECK-NEXT:    [[TMP1623:%.*]] = zext i1 [[TMP1622]] to i16
18796 // CHECK-NEXT:    store i16 [[TMP1623]], ptr [[USR]], align 2
18797 // CHECK-NEXT:    [[TMP1624:%.*]] = load i16, ptr [[USE]], align 2
18798 // CHECK-NEXT:    [[TMP1625:%.*]] = load i16, ptr [[USD]], align 2
18799 // CHECK-NEXT:    [[TMP1626:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1624]], i16 [[TMP1625]] acquire acquire, align 2
18800 // CHECK-NEXT:    [[TMP1627:%.*]] = extractvalue { i16, i1 } [[TMP1626]], 0
18801 // CHECK-NEXT:    [[TMP1628:%.*]] = extractvalue { i16, i1 } [[TMP1626]], 1
18802 // CHECK-NEXT:    br i1 [[TMP1628]], label [[USX_ATOMIC_EXIT157:%.*]], label [[USX_ATOMIC_CONT158:%.*]]
18803 // CHECK:       usx.atomic.cont158:
18804 // CHECK-NEXT:    store i16 [[TMP1627]], ptr [[USV]], align 2
18805 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT157]]
18806 // CHECK:       usx.atomic.exit157:
18807 // CHECK-NEXT:    [[TMP1629:%.*]] = extractvalue { i16, i1 } [[TMP1626]], 1
18808 // CHECK-NEXT:    [[TMP1630:%.*]] = zext i1 [[TMP1629]] to i16
18809 // CHECK-NEXT:    store i16 [[TMP1630]], ptr [[USR]], align 2
18810 // CHECK-NEXT:    [[TMP1631:%.*]] = load i16, ptr [[USE]], align 2
18811 // CHECK-NEXT:    [[TMP1632:%.*]] = load i16, ptr [[USD]], align 2
18812 // CHECK-NEXT:    [[TMP1633:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1631]], i16 [[TMP1632]] acquire acquire, align 2
18813 // CHECK-NEXT:    [[TMP1634:%.*]] = extractvalue { i16, i1 } [[TMP1633]], 0
18814 // CHECK-NEXT:    [[TMP1635:%.*]] = extractvalue { i16, i1 } [[TMP1633]], 1
18815 // CHECK-NEXT:    br i1 [[TMP1635]], label [[USX_ATOMIC_EXIT159:%.*]], label [[USX_ATOMIC_CONT160:%.*]]
18816 // CHECK:       usx.atomic.cont160:
18817 // CHECK-NEXT:    store i16 [[TMP1634]], ptr [[USV]], align 2
18818 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT159]]
18819 // CHECK:       usx.atomic.exit159:
18820 // CHECK-NEXT:    [[TMP1636:%.*]] = extractvalue { i16, i1 } [[TMP1633]], 1
18821 // CHECK-NEXT:    [[TMP1637:%.*]] = zext i1 [[TMP1636]] to i16
18822 // CHECK-NEXT:    store i16 [[TMP1637]], ptr [[USR]], align 2
18823 // CHECK-NEXT:    [[TMP1638:%.*]] = load i16, ptr [[USE]], align 2
18824 // CHECK-NEXT:    [[TMP1639:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1638]] monotonic, align 2
18825 // CHECK-NEXT:    store i16 [[TMP1639]], ptr [[USV]], align 2
18826 // CHECK-NEXT:    [[TMP1640:%.*]] = load i16, ptr [[USE]], align 2
18827 // CHECK-NEXT:    [[TMP1641:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1640]] monotonic, align 2
18828 // CHECK-NEXT:    store i16 [[TMP1641]], ptr [[USV]], align 2
18829 // CHECK-NEXT:    [[TMP1642:%.*]] = load i16, ptr [[USE]], align 2
18830 // CHECK-NEXT:    [[TMP1643:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1642]] monotonic, align 2
18831 // CHECK-NEXT:    store i16 [[TMP1643]], ptr [[USV]], align 2
18832 // CHECK-NEXT:    [[TMP1644:%.*]] = load i16, ptr [[USE]], align 2
18833 // CHECK-NEXT:    [[TMP1645:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1644]] monotonic, align 2
18834 // CHECK-NEXT:    store i16 [[TMP1645]], ptr [[USV]], align 2
18835 // CHECK-NEXT:    [[TMP1646:%.*]] = load i16, ptr [[USE]], align 2
18836 // CHECK-NEXT:    [[TMP1647:%.*]] = load i16, ptr [[USD]], align 2
18837 // CHECK-NEXT:    [[TMP1648:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1646]], i16 [[TMP1647]] monotonic monotonic, align 2
18838 // CHECK-NEXT:    [[TMP1649:%.*]] = extractvalue { i16, i1 } [[TMP1648]], 0
18839 // CHECK-NEXT:    store i16 [[TMP1649]], ptr [[USV]], align 2
18840 // CHECK-NEXT:    [[TMP1650:%.*]] = load i16, ptr [[USE]], align 2
18841 // CHECK-NEXT:    [[TMP1651:%.*]] = load i16, ptr [[USD]], align 2
18842 // CHECK-NEXT:    [[TMP1652:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1650]], i16 [[TMP1651]] monotonic monotonic, align 2
18843 // CHECK-NEXT:    [[TMP1653:%.*]] = extractvalue { i16, i1 } [[TMP1652]], 0
18844 // CHECK-NEXT:    store i16 [[TMP1653]], ptr [[USV]], align 2
18845 // CHECK-NEXT:    [[TMP1654:%.*]] = load i16, ptr [[USE]], align 2
18846 // CHECK-NEXT:    [[TMP1655:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1654]] monotonic, align 2
18847 // CHECK-NEXT:    [[TMP1656:%.*]] = icmp ugt i16 [[TMP1655]], [[TMP1654]]
18848 // CHECK-NEXT:    [[TMP1657:%.*]] = select i1 [[TMP1656]], i16 [[TMP1654]], i16 [[TMP1655]]
18849 // CHECK-NEXT:    store i16 [[TMP1657]], ptr [[USV]], align 2
18850 // CHECK-NEXT:    [[TMP1658:%.*]] = load i16, ptr [[USE]], align 2
18851 // CHECK-NEXT:    [[TMP1659:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1658]] monotonic, align 2
18852 // CHECK-NEXT:    [[TMP1660:%.*]] = icmp ult i16 [[TMP1659]], [[TMP1658]]
18853 // CHECK-NEXT:    [[TMP1661:%.*]] = select i1 [[TMP1660]], i16 [[TMP1658]], i16 [[TMP1659]]
18854 // CHECK-NEXT:    store i16 [[TMP1661]], ptr [[USV]], align 2
18855 // CHECK-NEXT:    [[TMP1662:%.*]] = load i16, ptr [[USE]], align 2
18856 // CHECK-NEXT:    [[TMP1663:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1662]] monotonic, align 2
18857 // CHECK-NEXT:    [[TMP1664:%.*]] = icmp ult i16 [[TMP1663]], [[TMP1662]]
18858 // CHECK-NEXT:    [[TMP1665:%.*]] = select i1 [[TMP1664]], i16 [[TMP1662]], i16 [[TMP1663]]
18859 // CHECK-NEXT:    store i16 [[TMP1665]], ptr [[USV]], align 2
18860 // CHECK-NEXT:    [[TMP1666:%.*]] = load i16, ptr [[USE]], align 2
18861 // CHECK-NEXT:    [[TMP1667:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1666]] monotonic, align 2
18862 // CHECK-NEXT:    [[TMP1668:%.*]] = icmp ugt i16 [[TMP1667]], [[TMP1666]]
18863 // CHECK-NEXT:    [[TMP1669:%.*]] = select i1 [[TMP1668]], i16 [[TMP1666]], i16 [[TMP1667]]
18864 // CHECK-NEXT:    store i16 [[TMP1669]], ptr [[USV]], align 2
18865 // CHECK-NEXT:    [[TMP1670:%.*]] = load i16, ptr [[USE]], align 2
18866 // CHECK-NEXT:    [[TMP1671:%.*]] = load i16, ptr [[USD]], align 2
18867 // CHECK-NEXT:    [[TMP1672:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1670]], i16 [[TMP1671]] monotonic monotonic, align 2
18868 // CHECK-NEXT:    [[TMP1673:%.*]] = extractvalue { i16, i1 } [[TMP1672]], 0
18869 // CHECK-NEXT:    [[TMP1674:%.*]] = extractvalue { i16, i1 } [[TMP1672]], 1
18870 // CHECK-NEXT:    [[TMP1675:%.*]] = select i1 [[TMP1674]], i16 [[TMP1670]], i16 [[TMP1673]]
18871 // CHECK-NEXT:    store i16 [[TMP1675]], ptr [[USV]], align 2
18872 // CHECK-NEXT:    [[TMP1676:%.*]] = load i16, ptr [[USE]], align 2
18873 // CHECK-NEXT:    [[TMP1677:%.*]] = load i16, ptr [[USD]], align 2
18874 // CHECK-NEXT:    [[TMP1678:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1676]], i16 [[TMP1677]] monotonic monotonic, align 2
18875 // CHECK-NEXT:    [[TMP1679:%.*]] = extractvalue { i16, i1 } [[TMP1678]], 0
18876 // CHECK-NEXT:    [[TMP1680:%.*]] = extractvalue { i16, i1 } [[TMP1678]], 1
18877 // CHECK-NEXT:    [[TMP1681:%.*]] = select i1 [[TMP1680]], i16 [[TMP1676]], i16 [[TMP1679]]
18878 // CHECK-NEXT:    store i16 [[TMP1681]], ptr [[USV]], align 2
18879 // CHECK-NEXT:    [[TMP1682:%.*]] = load i16, ptr [[USE]], align 2
18880 // CHECK-NEXT:    [[TMP1683:%.*]] = load i16, ptr [[USD]], align 2
18881 // CHECK-NEXT:    [[TMP1684:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1682]], i16 [[TMP1683]] monotonic monotonic, align 2
18882 // CHECK-NEXT:    [[TMP1685:%.*]] = extractvalue { i16, i1 } [[TMP1684]], 0
18883 // CHECK-NEXT:    [[TMP1686:%.*]] = extractvalue { i16, i1 } [[TMP1684]], 1
18884 // CHECK-NEXT:    br i1 [[TMP1686]], label [[USX_ATOMIC_EXIT161:%.*]], label [[USX_ATOMIC_CONT162:%.*]]
18885 // CHECK:       usx.atomic.cont162:
18886 // CHECK-NEXT:    store i16 [[TMP1685]], ptr [[USV]], align 2
18887 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT161]]
18888 // CHECK:       usx.atomic.exit161:
18889 // CHECK-NEXT:    [[TMP1687:%.*]] = load i16, ptr [[USE]], align 2
18890 // CHECK-NEXT:    [[TMP1688:%.*]] = load i16, ptr [[USD]], align 2
18891 // CHECK-NEXT:    [[TMP1689:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1687]], i16 [[TMP1688]] monotonic monotonic, align 2
18892 // CHECK-NEXT:    [[TMP1690:%.*]] = extractvalue { i16, i1 } [[TMP1689]], 0
18893 // CHECK-NEXT:    [[TMP1691:%.*]] = extractvalue { i16, i1 } [[TMP1689]], 1
18894 // CHECK-NEXT:    br i1 [[TMP1691]], label [[USX_ATOMIC_EXIT163:%.*]], label [[USX_ATOMIC_CONT164:%.*]]
18895 // CHECK:       usx.atomic.cont164:
18896 // CHECK-NEXT:    store i16 [[TMP1690]], ptr [[USV]], align 2
18897 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT163]]
18898 // CHECK:       usx.atomic.exit163:
18899 // CHECK-NEXT:    [[TMP1692:%.*]] = load i16, ptr [[USE]], align 2
18900 // CHECK-NEXT:    [[TMP1693:%.*]] = load i16, ptr [[USD]], align 2
18901 // CHECK-NEXT:    [[TMP1694:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1692]], i16 [[TMP1693]] monotonic monotonic, align 2
18902 // CHECK-NEXT:    [[TMP1695:%.*]] = extractvalue { i16, i1 } [[TMP1694]], 1
18903 // CHECK-NEXT:    [[TMP1696:%.*]] = zext i1 [[TMP1695]] to i16
18904 // CHECK-NEXT:    store i16 [[TMP1696]], ptr [[USR]], align 2
18905 // CHECK-NEXT:    [[TMP1697:%.*]] = load i16, ptr [[USE]], align 2
18906 // CHECK-NEXT:    [[TMP1698:%.*]] = load i16, ptr [[USD]], align 2
18907 // CHECK-NEXT:    [[TMP1699:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1697]], i16 [[TMP1698]] monotonic monotonic, align 2
18908 // CHECK-NEXT:    [[TMP1700:%.*]] = extractvalue { i16, i1 } [[TMP1699]], 1
18909 // CHECK-NEXT:    [[TMP1701:%.*]] = zext i1 [[TMP1700]] to i16
18910 // CHECK-NEXT:    store i16 [[TMP1701]], ptr [[USR]], align 2
18911 // CHECK-NEXT:    [[TMP1702:%.*]] = load i16, ptr [[USE]], align 2
18912 // CHECK-NEXT:    [[TMP1703:%.*]] = load i16, ptr [[USD]], align 2
18913 // CHECK-NEXT:    [[TMP1704:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1702]], i16 [[TMP1703]] monotonic monotonic, align 2
18914 // CHECK-NEXT:    [[TMP1705:%.*]] = extractvalue { i16, i1 } [[TMP1704]], 0
18915 // CHECK-NEXT:    [[TMP1706:%.*]] = extractvalue { i16, i1 } [[TMP1704]], 1
18916 // CHECK-NEXT:    br i1 [[TMP1706]], label [[USX_ATOMIC_EXIT165:%.*]], label [[USX_ATOMIC_CONT166:%.*]]
18917 // CHECK:       usx.atomic.cont166:
18918 // CHECK-NEXT:    store i16 [[TMP1705]], ptr [[USV]], align 2
18919 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT165]]
18920 // CHECK:       usx.atomic.exit165:
18921 // CHECK-NEXT:    [[TMP1707:%.*]] = extractvalue { i16, i1 } [[TMP1704]], 1
18922 // CHECK-NEXT:    [[TMP1708:%.*]] = zext i1 [[TMP1707]] to i16
18923 // CHECK-NEXT:    store i16 [[TMP1708]], ptr [[USR]], align 2
18924 // CHECK-NEXT:    [[TMP1709:%.*]] = load i16, ptr [[USE]], align 2
18925 // CHECK-NEXT:    [[TMP1710:%.*]] = load i16, ptr [[USD]], align 2
18926 // CHECK-NEXT:    [[TMP1711:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1709]], i16 [[TMP1710]] monotonic monotonic, align 2
18927 // CHECK-NEXT:    [[TMP1712:%.*]] = extractvalue { i16, i1 } [[TMP1711]], 0
18928 // CHECK-NEXT:    [[TMP1713:%.*]] = extractvalue { i16, i1 } [[TMP1711]], 1
18929 // CHECK-NEXT:    br i1 [[TMP1713]], label [[USX_ATOMIC_EXIT167:%.*]], label [[USX_ATOMIC_CONT168:%.*]]
18930 // CHECK:       usx.atomic.cont168:
18931 // CHECK-NEXT:    store i16 [[TMP1712]], ptr [[USV]], align 2
18932 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT167]]
18933 // CHECK:       usx.atomic.exit167:
18934 // CHECK-NEXT:    [[TMP1714:%.*]] = extractvalue { i16, i1 } [[TMP1711]], 1
18935 // CHECK-NEXT:    [[TMP1715:%.*]] = zext i1 [[TMP1714]] to i16
18936 // CHECK-NEXT:    store i16 [[TMP1715]], ptr [[USR]], align 2
18937 // CHECK-NEXT:    [[TMP1716:%.*]] = load i16, ptr [[USE]], align 2
18938 // CHECK-NEXT:    [[TMP1717:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1716]] release, align 2
18939 // CHECK-NEXT:    store i16 [[TMP1717]], ptr [[USV]], align 2
18940 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18941 // CHECK-NEXT:    [[TMP1718:%.*]] = load i16, ptr [[USE]], align 2
18942 // CHECK-NEXT:    [[TMP1719:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1718]] release, align 2
18943 // CHECK-NEXT:    store i16 [[TMP1719]], ptr [[USV]], align 2
18944 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18945 // CHECK-NEXT:    [[TMP1720:%.*]] = load i16, ptr [[USE]], align 2
18946 // CHECK-NEXT:    [[TMP1721:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1720]] release, align 2
18947 // CHECK-NEXT:    store i16 [[TMP1721]], ptr [[USV]], align 2
18948 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18949 // CHECK-NEXT:    [[TMP1722:%.*]] = load i16, ptr [[USE]], align 2
18950 // CHECK-NEXT:    [[TMP1723:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1722]] release, align 2
18951 // CHECK-NEXT:    store i16 [[TMP1723]], ptr [[USV]], align 2
18952 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18953 // CHECK-NEXT:    [[TMP1724:%.*]] = load i16, ptr [[USE]], align 2
18954 // CHECK-NEXT:    [[TMP1725:%.*]] = load i16, ptr [[USD]], align 2
18955 // CHECK-NEXT:    [[TMP1726:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1724]], i16 [[TMP1725]] release monotonic, align 2
18956 // CHECK-NEXT:    [[TMP1727:%.*]] = extractvalue { i16, i1 } [[TMP1726]], 0
18957 // CHECK-NEXT:    store i16 [[TMP1727]], ptr [[USV]], align 2
18958 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18959 // CHECK-NEXT:    [[TMP1728:%.*]] = load i16, ptr [[USE]], align 2
18960 // CHECK-NEXT:    [[TMP1729:%.*]] = load i16, ptr [[USD]], align 2
18961 // CHECK-NEXT:    [[TMP1730:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1728]], i16 [[TMP1729]] release monotonic, align 2
18962 // CHECK-NEXT:    [[TMP1731:%.*]] = extractvalue { i16, i1 } [[TMP1730]], 0
18963 // CHECK-NEXT:    store i16 [[TMP1731]], ptr [[USV]], align 2
18964 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18965 // CHECK-NEXT:    [[TMP1732:%.*]] = load i16, ptr [[USE]], align 2
18966 // CHECK-NEXT:    [[TMP1733:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1732]] release, align 2
18967 // CHECK-NEXT:    [[TMP1734:%.*]] = icmp ugt i16 [[TMP1733]], [[TMP1732]]
18968 // CHECK-NEXT:    [[TMP1735:%.*]] = select i1 [[TMP1734]], i16 [[TMP1732]], i16 [[TMP1733]]
18969 // CHECK-NEXT:    store i16 [[TMP1735]], ptr [[USV]], align 2
18970 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18971 // CHECK-NEXT:    [[TMP1736:%.*]] = load i16, ptr [[USE]], align 2
18972 // CHECK-NEXT:    [[TMP1737:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1736]] release, align 2
18973 // CHECK-NEXT:    [[TMP1738:%.*]] = icmp ult i16 [[TMP1737]], [[TMP1736]]
18974 // CHECK-NEXT:    [[TMP1739:%.*]] = select i1 [[TMP1738]], i16 [[TMP1736]], i16 [[TMP1737]]
18975 // CHECK-NEXT:    store i16 [[TMP1739]], ptr [[USV]], align 2
18976 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18977 // CHECK-NEXT:    [[TMP1740:%.*]] = load i16, ptr [[USE]], align 2
18978 // CHECK-NEXT:    [[TMP1741:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1740]] release, align 2
18979 // CHECK-NEXT:    [[TMP1742:%.*]] = icmp ult i16 [[TMP1741]], [[TMP1740]]
18980 // CHECK-NEXT:    [[TMP1743:%.*]] = select i1 [[TMP1742]], i16 [[TMP1740]], i16 [[TMP1741]]
18981 // CHECK-NEXT:    store i16 [[TMP1743]], ptr [[USV]], align 2
18982 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18983 // CHECK-NEXT:    [[TMP1744:%.*]] = load i16, ptr [[USE]], align 2
18984 // CHECK-NEXT:    [[TMP1745:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1744]] release, align 2
18985 // CHECK-NEXT:    [[TMP1746:%.*]] = icmp ugt i16 [[TMP1745]], [[TMP1744]]
18986 // CHECK-NEXT:    [[TMP1747:%.*]] = select i1 [[TMP1746]], i16 [[TMP1744]], i16 [[TMP1745]]
18987 // CHECK-NEXT:    store i16 [[TMP1747]], ptr [[USV]], align 2
18988 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18989 // CHECK-NEXT:    [[TMP1748:%.*]] = load i16, ptr [[USE]], align 2
18990 // CHECK-NEXT:    [[TMP1749:%.*]] = load i16, ptr [[USD]], align 2
18991 // CHECK-NEXT:    [[TMP1750:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1748]], i16 [[TMP1749]] release monotonic, align 2
18992 // CHECK-NEXT:    [[TMP1751:%.*]] = extractvalue { i16, i1 } [[TMP1750]], 0
18993 // CHECK-NEXT:    [[TMP1752:%.*]] = extractvalue { i16, i1 } [[TMP1750]], 1
18994 // CHECK-NEXT:    [[TMP1753:%.*]] = select i1 [[TMP1752]], i16 [[TMP1748]], i16 [[TMP1751]]
18995 // CHECK-NEXT:    store i16 [[TMP1753]], ptr [[USV]], align 2
18996 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
18997 // CHECK-NEXT:    [[TMP1754:%.*]] = load i16, ptr [[USE]], align 2
18998 // CHECK-NEXT:    [[TMP1755:%.*]] = load i16, ptr [[USD]], align 2
18999 // CHECK-NEXT:    [[TMP1756:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1754]], i16 [[TMP1755]] release monotonic, align 2
19000 // CHECK-NEXT:    [[TMP1757:%.*]] = extractvalue { i16, i1 } [[TMP1756]], 0
19001 // CHECK-NEXT:    [[TMP1758:%.*]] = extractvalue { i16, i1 } [[TMP1756]], 1
19002 // CHECK-NEXT:    [[TMP1759:%.*]] = select i1 [[TMP1758]], i16 [[TMP1754]], i16 [[TMP1757]]
19003 // CHECK-NEXT:    store i16 [[TMP1759]], ptr [[USV]], align 2
19004 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19005 // CHECK-NEXT:    [[TMP1760:%.*]] = load i16, ptr [[USE]], align 2
19006 // CHECK-NEXT:    [[TMP1761:%.*]] = load i16, ptr [[USD]], align 2
19007 // CHECK-NEXT:    [[TMP1762:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1760]], i16 [[TMP1761]] release monotonic, align 2
19008 // CHECK-NEXT:    [[TMP1763:%.*]] = extractvalue { i16, i1 } [[TMP1762]], 0
19009 // CHECK-NEXT:    [[TMP1764:%.*]] = extractvalue { i16, i1 } [[TMP1762]], 1
19010 // CHECK-NEXT:    br i1 [[TMP1764]], label [[USX_ATOMIC_EXIT169:%.*]], label [[USX_ATOMIC_CONT170:%.*]]
19011 // CHECK:       usx.atomic.cont170:
19012 // CHECK-NEXT:    store i16 [[TMP1763]], ptr [[USV]], align 2
19013 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT169]]
19014 // CHECK:       usx.atomic.exit169:
19015 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19016 // CHECK-NEXT:    [[TMP1765:%.*]] = load i16, ptr [[USE]], align 2
19017 // CHECK-NEXT:    [[TMP1766:%.*]] = load i16, ptr [[USD]], align 2
19018 // CHECK-NEXT:    [[TMP1767:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1765]], i16 [[TMP1766]] release monotonic, align 2
19019 // CHECK-NEXT:    [[TMP1768:%.*]] = extractvalue { i16, i1 } [[TMP1767]], 0
19020 // CHECK-NEXT:    [[TMP1769:%.*]] = extractvalue { i16, i1 } [[TMP1767]], 1
19021 // CHECK-NEXT:    br i1 [[TMP1769]], label [[USX_ATOMIC_EXIT171:%.*]], label [[USX_ATOMIC_CONT172:%.*]]
19022 // CHECK:       usx.atomic.cont172:
19023 // CHECK-NEXT:    store i16 [[TMP1768]], ptr [[USV]], align 2
19024 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT171]]
19025 // CHECK:       usx.atomic.exit171:
19026 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19027 // CHECK-NEXT:    [[TMP1770:%.*]] = load i16, ptr [[USE]], align 2
19028 // CHECK-NEXT:    [[TMP1771:%.*]] = load i16, ptr [[USD]], align 2
19029 // CHECK-NEXT:    [[TMP1772:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1770]], i16 [[TMP1771]] release monotonic, align 2
19030 // CHECK-NEXT:    [[TMP1773:%.*]] = extractvalue { i16, i1 } [[TMP1772]], 1
19031 // CHECK-NEXT:    [[TMP1774:%.*]] = zext i1 [[TMP1773]] to i16
19032 // CHECK-NEXT:    store i16 [[TMP1774]], ptr [[USR]], align 2
19033 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19034 // CHECK-NEXT:    [[TMP1775:%.*]] = load i16, ptr [[USE]], align 2
19035 // CHECK-NEXT:    [[TMP1776:%.*]] = load i16, ptr [[USD]], align 2
19036 // CHECK-NEXT:    [[TMP1777:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1775]], i16 [[TMP1776]] release monotonic, align 2
19037 // CHECK-NEXT:    [[TMP1778:%.*]] = extractvalue { i16, i1 } [[TMP1777]], 1
19038 // CHECK-NEXT:    [[TMP1779:%.*]] = zext i1 [[TMP1778]] to i16
19039 // CHECK-NEXT:    store i16 [[TMP1779]], ptr [[USR]], align 2
19040 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19041 // CHECK-NEXT:    [[TMP1780:%.*]] = load i16, ptr [[USE]], align 2
19042 // CHECK-NEXT:    [[TMP1781:%.*]] = load i16, ptr [[USD]], align 2
19043 // CHECK-NEXT:    [[TMP1782:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1780]], i16 [[TMP1781]] release monotonic, align 2
19044 // CHECK-NEXT:    [[TMP1783:%.*]] = extractvalue { i16, i1 } [[TMP1782]], 0
19045 // CHECK-NEXT:    [[TMP1784:%.*]] = extractvalue { i16, i1 } [[TMP1782]], 1
19046 // CHECK-NEXT:    br i1 [[TMP1784]], label [[USX_ATOMIC_EXIT173:%.*]], label [[USX_ATOMIC_CONT174:%.*]]
19047 // CHECK:       usx.atomic.cont174:
19048 // CHECK-NEXT:    store i16 [[TMP1783]], ptr [[USV]], align 2
19049 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT173]]
19050 // CHECK:       usx.atomic.exit173:
19051 // CHECK-NEXT:    [[TMP1785:%.*]] = extractvalue { i16, i1 } [[TMP1782]], 1
19052 // CHECK-NEXT:    [[TMP1786:%.*]] = zext i1 [[TMP1785]] to i16
19053 // CHECK-NEXT:    store i16 [[TMP1786]], ptr [[USR]], align 2
19054 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19055 // CHECK-NEXT:    [[TMP1787:%.*]] = load i16, ptr [[USE]], align 2
19056 // CHECK-NEXT:    [[TMP1788:%.*]] = load i16, ptr [[USD]], align 2
19057 // CHECK-NEXT:    [[TMP1789:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1787]], i16 [[TMP1788]] release monotonic, align 2
19058 // CHECK-NEXT:    [[TMP1790:%.*]] = extractvalue { i16, i1 } [[TMP1789]], 0
19059 // CHECK-NEXT:    [[TMP1791:%.*]] = extractvalue { i16, i1 } [[TMP1789]], 1
19060 // CHECK-NEXT:    br i1 [[TMP1791]], label [[USX_ATOMIC_EXIT175:%.*]], label [[USX_ATOMIC_CONT176:%.*]]
19061 // CHECK:       usx.atomic.cont176:
19062 // CHECK-NEXT:    store i16 [[TMP1790]], ptr [[USV]], align 2
19063 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT175]]
19064 // CHECK:       usx.atomic.exit175:
19065 // CHECK-NEXT:    [[TMP1792:%.*]] = extractvalue { i16, i1 } [[TMP1789]], 1
19066 // CHECK-NEXT:    [[TMP1793:%.*]] = zext i1 [[TMP1792]] to i16
19067 // CHECK-NEXT:    store i16 [[TMP1793]], ptr [[USR]], align 2
19068 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19069 // CHECK-NEXT:    [[TMP1794:%.*]] = load i16, ptr [[USE]], align 2
19070 // CHECK-NEXT:    [[TMP1795:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1794]] seq_cst, align 2
19071 // CHECK-NEXT:    store i16 [[TMP1795]], ptr [[USV]], align 2
19072 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19073 // CHECK-NEXT:    [[TMP1796:%.*]] = load i16, ptr [[USE]], align 2
19074 // CHECK-NEXT:    [[TMP1797:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1796]] seq_cst, align 2
19075 // CHECK-NEXT:    store i16 [[TMP1797]], ptr [[USV]], align 2
19076 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19077 // CHECK-NEXT:    [[TMP1798:%.*]] = load i16, ptr [[USE]], align 2
19078 // CHECK-NEXT:    [[TMP1799:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1798]] seq_cst, align 2
19079 // CHECK-NEXT:    store i16 [[TMP1799]], ptr [[USV]], align 2
19080 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19081 // CHECK-NEXT:    [[TMP1800:%.*]] = load i16, ptr [[USE]], align 2
19082 // CHECK-NEXT:    [[TMP1801:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1800]] seq_cst, align 2
19083 // CHECK-NEXT:    store i16 [[TMP1801]], ptr [[USV]], align 2
19084 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19085 // CHECK-NEXT:    [[TMP1802:%.*]] = load i16, ptr [[USE]], align 2
19086 // CHECK-NEXT:    [[TMP1803:%.*]] = load i16, ptr [[USD]], align 2
19087 // CHECK-NEXT:    [[TMP1804:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1802]], i16 [[TMP1803]] seq_cst seq_cst, align 2
19088 // CHECK-NEXT:    [[TMP1805:%.*]] = extractvalue { i16, i1 } [[TMP1804]], 0
19089 // CHECK-NEXT:    store i16 [[TMP1805]], ptr [[USV]], align 2
19090 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19091 // CHECK-NEXT:    [[TMP1806:%.*]] = load i16, ptr [[USE]], align 2
19092 // CHECK-NEXT:    [[TMP1807:%.*]] = load i16, ptr [[USD]], align 2
19093 // CHECK-NEXT:    [[TMP1808:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1806]], i16 [[TMP1807]] seq_cst seq_cst, align 2
19094 // CHECK-NEXT:    [[TMP1809:%.*]] = extractvalue { i16, i1 } [[TMP1808]], 0
19095 // CHECK-NEXT:    store i16 [[TMP1809]], ptr [[USV]], align 2
19096 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19097 // CHECK-NEXT:    [[TMP1810:%.*]] = load i16, ptr [[USE]], align 2
19098 // CHECK-NEXT:    [[TMP1811:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1810]] seq_cst, align 2
19099 // CHECK-NEXT:    [[TMP1812:%.*]] = icmp ugt i16 [[TMP1811]], [[TMP1810]]
19100 // CHECK-NEXT:    [[TMP1813:%.*]] = select i1 [[TMP1812]], i16 [[TMP1810]], i16 [[TMP1811]]
19101 // CHECK-NEXT:    store i16 [[TMP1813]], ptr [[USV]], align 2
19102 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19103 // CHECK-NEXT:    [[TMP1814:%.*]] = load i16, ptr [[USE]], align 2
19104 // CHECK-NEXT:    [[TMP1815:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1814]] seq_cst, align 2
19105 // CHECK-NEXT:    [[TMP1816:%.*]] = icmp ult i16 [[TMP1815]], [[TMP1814]]
19106 // CHECK-NEXT:    [[TMP1817:%.*]] = select i1 [[TMP1816]], i16 [[TMP1814]], i16 [[TMP1815]]
19107 // CHECK-NEXT:    store i16 [[TMP1817]], ptr [[USV]], align 2
19108 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19109 // CHECK-NEXT:    [[TMP1818:%.*]] = load i16, ptr [[USE]], align 2
19110 // CHECK-NEXT:    [[TMP1819:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1818]] seq_cst, align 2
19111 // CHECK-NEXT:    [[TMP1820:%.*]] = icmp ult i16 [[TMP1819]], [[TMP1818]]
19112 // CHECK-NEXT:    [[TMP1821:%.*]] = select i1 [[TMP1820]], i16 [[TMP1818]], i16 [[TMP1819]]
19113 // CHECK-NEXT:    store i16 [[TMP1821]], ptr [[USV]], align 2
19114 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19115 // CHECK-NEXT:    [[TMP1822:%.*]] = load i16, ptr [[USE]], align 2
19116 // CHECK-NEXT:    [[TMP1823:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1822]] seq_cst, align 2
19117 // CHECK-NEXT:    [[TMP1824:%.*]] = icmp ugt i16 [[TMP1823]], [[TMP1822]]
19118 // CHECK-NEXT:    [[TMP1825:%.*]] = select i1 [[TMP1824]], i16 [[TMP1822]], i16 [[TMP1823]]
19119 // CHECK-NEXT:    store i16 [[TMP1825]], ptr [[USV]], align 2
19120 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19121 // CHECK-NEXT:    [[TMP1826:%.*]] = load i16, ptr [[USE]], align 2
19122 // CHECK-NEXT:    [[TMP1827:%.*]] = load i16, ptr [[USD]], align 2
19123 // CHECK-NEXT:    [[TMP1828:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1826]], i16 [[TMP1827]] seq_cst seq_cst, align 2
19124 // CHECK-NEXT:    [[TMP1829:%.*]] = extractvalue { i16, i1 } [[TMP1828]], 0
19125 // CHECK-NEXT:    [[TMP1830:%.*]] = extractvalue { i16, i1 } [[TMP1828]], 1
19126 // CHECK-NEXT:    [[TMP1831:%.*]] = select i1 [[TMP1830]], i16 [[TMP1826]], i16 [[TMP1829]]
19127 // CHECK-NEXT:    store i16 [[TMP1831]], ptr [[USV]], align 2
19128 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19129 // CHECK-NEXT:    [[TMP1832:%.*]] = load i16, ptr [[USE]], align 2
19130 // CHECK-NEXT:    [[TMP1833:%.*]] = load i16, ptr [[USD]], align 2
19131 // CHECK-NEXT:    [[TMP1834:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1832]], i16 [[TMP1833]] seq_cst seq_cst, align 2
19132 // CHECK-NEXT:    [[TMP1835:%.*]] = extractvalue { i16, i1 } [[TMP1834]], 0
19133 // CHECK-NEXT:    [[TMP1836:%.*]] = extractvalue { i16, i1 } [[TMP1834]], 1
19134 // CHECK-NEXT:    [[TMP1837:%.*]] = select i1 [[TMP1836]], i16 [[TMP1832]], i16 [[TMP1835]]
19135 // CHECK-NEXT:    store i16 [[TMP1837]], ptr [[USV]], align 2
19136 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19137 // CHECK-NEXT:    [[TMP1838:%.*]] = load i16, ptr [[USE]], align 2
19138 // CHECK-NEXT:    [[TMP1839:%.*]] = load i16, ptr [[USD]], align 2
19139 // CHECK-NEXT:    [[TMP1840:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1838]], i16 [[TMP1839]] seq_cst seq_cst, align 2
19140 // CHECK-NEXT:    [[TMP1841:%.*]] = extractvalue { i16, i1 } [[TMP1840]], 0
19141 // CHECK-NEXT:    [[TMP1842:%.*]] = extractvalue { i16, i1 } [[TMP1840]], 1
19142 // CHECK-NEXT:    br i1 [[TMP1842]], label [[USX_ATOMIC_EXIT177:%.*]], label [[USX_ATOMIC_CONT178:%.*]]
19143 // CHECK:       usx.atomic.cont178:
19144 // CHECK-NEXT:    store i16 [[TMP1841]], ptr [[USV]], align 2
19145 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT177]]
19146 // CHECK:       usx.atomic.exit177:
19147 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19148 // CHECK-NEXT:    [[TMP1843:%.*]] = load i16, ptr [[USE]], align 2
19149 // CHECK-NEXT:    [[TMP1844:%.*]] = load i16, ptr [[USD]], align 2
19150 // CHECK-NEXT:    [[TMP1845:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1843]], i16 [[TMP1844]] seq_cst seq_cst, align 2
19151 // CHECK-NEXT:    [[TMP1846:%.*]] = extractvalue { i16, i1 } [[TMP1845]], 0
19152 // CHECK-NEXT:    [[TMP1847:%.*]] = extractvalue { i16, i1 } [[TMP1845]], 1
19153 // CHECK-NEXT:    br i1 [[TMP1847]], label [[USX_ATOMIC_EXIT179:%.*]], label [[USX_ATOMIC_CONT180:%.*]]
19154 // CHECK:       usx.atomic.cont180:
19155 // CHECK-NEXT:    store i16 [[TMP1846]], ptr [[USV]], align 2
19156 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT179]]
19157 // CHECK:       usx.atomic.exit179:
19158 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19159 // CHECK-NEXT:    [[TMP1848:%.*]] = load i16, ptr [[USE]], align 2
19160 // CHECK-NEXT:    [[TMP1849:%.*]] = load i16, ptr [[USD]], align 2
19161 // CHECK-NEXT:    [[TMP1850:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1848]], i16 [[TMP1849]] seq_cst seq_cst, align 2
19162 // CHECK-NEXT:    [[TMP1851:%.*]] = extractvalue { i16, i1 } [[TMP1850]], 1
19163 // CHECK-NEXT:    [[TMP1852:%.*]] = zext i1 [[TMP1851]] to i16
19164 // CHECK-NEXT:    store i16 [[TMP1852]], ptr [[USR]], align 2
19165 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19166 // CHECK-NEXT:    [[TMP1853:%.*]] = load i16, ptr [[USE]], align 2
19167 // CHECK-NEXT:    [[TMP1854:%.*]] = load i16, ptr [[USD]], align 2
19168 // CHECK-NEXT:    [[TMP1855:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1853]], i16 [[TMP1854]] seq_cst seq_cst, align 2
19169 // CHECK-NEXT:    [[TMP1856:%.*]] = extractvalue { i16, i1 } [[TMP1855]], 1
19170 // CHECK-NEXT:    [[TMP1857:%.*]] = zext i1 [[TMP1856]] to i16
19171 // CHECK-NEXT:    store i16 [[TMP1857]], ptr [[USR]], align 2
19172 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19173 // CHECK-NEXT:    [[TMP1858:%.*]] = load i16, ptr [[USE]], align 2
19174 // CHECK-NEXT:    [[TMP1859:%.*]] = load i16, ptr [[USD]], align 2
19175 // CHECK-NEXT:    [[TMP1860:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1858]], i16 [[TMP1859]] seq_cst seq_cst, align 2
19176 // CHECK-NEXT:    [[TMP1861:%.*]] = extractvalue { i16, i1 } [[TMP1860]], 0
19177 // CHECK-NEXT:    [[TMP1862:%.*]] = extractvalue { i16, i1 } [[TMP1860]], 1
19178 // CHECK-NEXT:    br i1 [[TMP1862]], label [[USX_ATOMIC_EXIT181:%.*]], label [[USX_ATOMIC_CONT182:%.*]]
19179 // CHECK:       usx.atomic.cont182:
19180 // CHECK-NEXT:    store i16 [[TMP1861]], ptr [[USV]], align 2
19181 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT181]]
19182 // CHECK:       usx.atomic.exit181:
19183 // CHECK-NEXT:    [[TMP1863:%.*]] = extractvalue { i16, i1 } [[TMP1860]], 1
19184 // CHECK-NEXT:    [[TMP1864:%.*]] = zext i1 [[TMP1863]] to i16
19185 // CHECK-NEXT:    store i16 [[TMP1864]], ptr [[USR]], align 2
19186 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19187 // CHECK-NEXT:    [[TMP1865:%.*]] = load i16, ptr [[USE]], align 2
19188 // CHECK-NEXT:    [[TMP1866:%.*]] = load i16, ptr [[USD]], align 2
19189 // CHECK-NEXT:    [[TMP1867:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1865]], i16 [[TMP1866]] seq_cst seq_cst, align 2
19190 // CHECK-NEXT:    [[TMP1868:%.*]] = extractvalue { i16, i1 } [[TMP1867]], 0
19191 // CHECK-NEXT:    [[TMP1869:%.*]] = extractvalue { i16, i1 } [[TMP1867]], 1
19192 // CHECK-NEXT:    br i1 [[TMP1869]], label [[USX_ATOMIC_EXIT183:%.*]], label [[USX_ATOMIC_CONT184:%.*]]
19193 // CHECK:       usx.atomic.cont184:
19194 // CHECK-NEXT:    store i16 [[TMP1868]], ptr [[USV]], align 2
19195 // CHECK-NEXT:    br label [[USX_ATOMIC_EXIT183]]
19196 // CHECK:       usx.atomic.exit183:
19197 // CHECK-NEXT:    [[TMP1870:%.*]] = extractvalue { i16, i1 } [[TMP1867]], 1
19198 // CHECK-NEXT:    [[TMP1871:%.*]] = zext i1 [[TMP1870]] to i16
19199 // CHECK-NEXT:    store i16 [[TMP1871]], ptr [[USR]], align 2
19200 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19201 // CHECK-NEXT:    [[TMP1872:%.*]] = load i32, ptr [[IE]], align 4
19202 // CHECK-NEXT:    [[TMP1873:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1872]] monotonic, align 4
19203 // CHECK-NEXT:    store i32 [[TMP1873]], ptr [[IV]], align 4
19204 // CHECK-NEXT:    [[TMP1874:%.*]] = load i32, ptr [[IE]], align 4
19205 // CHECK-NEXT:    [[TMP1875:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1874]] monotonic, align 4
19206 // CHECK-NEXT:    store i32 [[TMP1875]], ptr [[IV]], align 4
19207 // CHECK-NEXT:    [[TMP1876:%.*]] = load i32, ptr [[IE]], align 4
19208 // CHECK-NEXT:    [[TMP1877:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1876]] monotonic, align 4
19209 // CHECK-NEXT:    store i32 [[TMP1877]], ptr [[IV]], align 4
19210 // CHECK-NEXT:    [[TMP1878:%.*]] = load i32, ptr [[IE]], align 4
19211 // CHECK-NEXT:    [[TMP1879:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1878]] monotonic, align 4
19212 // CHECK-NEXT:    store i32 [[TMP1879]], ptr [[IV]], align 4
19213 // CHECK-NEXT:    [[TMP1880:%.*]] = load i32, ptr [[IE]], align 4
19214 // CHECK-NEXT:    [[TMP1881:%.*]] = load i32, ptr [[ID]], align 4
19215 // CHECK-NEXT:    [[TMP1882:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1880]], i32 [[TMP1881]] monotonic monotonic, align 4
19216 // CHECK-NEXT:    [[TMP1883:%.*]] = extractvalue { i32, i1 } [[TMP1882]], 0
19217 // CHECK-NEXT:    store i32 [[TMP1883]], ptr [[IV]], align 4
19218 // CHECK-NEXT:    [[TMP1884:%.*]] = load i32, ptr [[IE]], align 4
19219 // CHECK-NEXT:    [[TMP1885:%.*]] = load i32, ptr [[ID]], align 4
19220 // CHECK-NEXT:    [[TMP1886:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1884]], i32 [[TMP1885]] monotonic monotonic, align 4
19221 // CHECK-NEXT:    [[TMP1887:%.*]] = extractvalue { i32, i1 } [[TMP1886]], 0
19222 // CHECK-NEXT:    store i32 [[TMP1887]], ptr [[IV]], align 4
19223 // CHECK-NEXT:    [[TMP1888:%.*]] = load i32, ptr [[IE]], align 4
19224 // CHECK-NEXT:    [[TMP1889:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1888]] monotonic, align 4
19225 // CHECK-NEXT:    [[TMP1890:%.*]] = icmp sgt i32 [[TMP1889]], [[TMP1888]]
19226 // CHECK-NEXT:    [[TMP1891:%.*]] = select i1 [[TMP1890]], i32 [[TMP1888]], i32 [[TMP1889]]
19227 // CHECK-NEXT:    store i32 [[TMP1891]], ptr [[IV]], align 4
19228 // CHECK-NEXT:    [[TMP1892:%.*]] = load i32, ptr [[IE]], align 4
19229 // CHECK-NEXT:    [[TMP1893:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1892]] monotonic, align 4
19230 // CHECK-NEXT:    [[TMP1894:%.*]] = icmp slt i32 [[TMP1893]], [[TMP1892]]
19231 // CHECK-NEXT:    [[TMP1895:%.*]] = select i1 [[TMP1894]], i32 [[TMP1892]], i32 [[TMP1893]]
19232 // CHECK-NEXT:    store i32 [[TMP1895]], ptr [[IV]], align 4
19233 // CHECK-NEXT:    [[TMP1896:%.*]] = load i32, ptr [[IE]], align 4
19234 // CHECK-NEXT:    [[TMP1897:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1896]] monotonic, align 4
19235 // CHECK-NEXT:    [[TMP1898:%.*]] = icmp slt i32 [[TMP1897]], [[TMP1896]]
19236 // CHECK-NEXT:    [[TMP1899:%.*]] = select i1 [[TMP1898]], i32 [[TMP1896]], i32 [[TMP1897]]
19237 // CHECK-NEXT:    store i32 [[TMP1899]], ptr [[IV]], align 4
19238 // CHECK-NEXT:    [[TMP1900:%.*]] = load i32, ptr [[IE]], align 4
19239 // CHECK-NEXT:    [[TMP1901:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1900]] monotonic, align 4
19240 // CHECK-NEXT:    [[TMP1902:%.*]] = icmp sgt i32 [[TMP1901]], [[TMP1900]]
19241 // CHECK-NEXT:    [[TMP1903:%.*]] = select i1 [[TMP1902]], i32 [[TMP1900]], i32 [[TMP1901]]
19242 // CHECK-NEXT:    store i32 [[TMP1903]], ptr [[IV]], align 4
19243 // CHECK-NEXT:    [[TMP1904:%.*]] = load i32, ptr [[IE]], align 4
19244 // CHECK-NEXT:    [[TMP1905:%.*]] = load i32, ptr [[ID]], align 4
19245 // CHECK-NEXT:    [[TMP1906:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1904]], i32 [[TMP1905]] monotonic monotonic, align 4
19246 // CHECK-NEXT:    [[TMP1907:%.*]] = extractvalue { i32, i1 } [[TMP1906]], 0
19247 // CHECK-NEXT:    [[TMP1908:%.*]] = extractvalue { i32, i1 } [[TMP1906]], 1
19248 // CHECK-NEXT:    [[TMP1909:%.*]] = select i1 [[TMP1908]], i32 [[TMP1904]], i32 [[TMP1907]]
19249 // CHECK-NEXT:    store i32 [[TMP1909]], ptr [[IV]], align 4
19250 // CHECK-NEXT:    [[TMP1910:%.*]] = load i32, ptr [[IE]], align 4
19251 // CHECK-NEXT:    [[TMP1911:%.*]] = load i32, ptr [[ID]], align 4
19252 // CHECK-NEXT:    [[TMP1912:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1910]], i32 [[TMP1911]] monotonic monotonic, align 4
19253 // CHECK-NEXT:    [[TMP1913:%.*]] = extractvalue { i32, i1 } [[TMP1912]], 0
19254 // CHECK-NEXT:    [[TMP1914:%.*]] = extractvalue { i32, i1 } [[TMP1912]], 1
19255 // CHECK-NEXT:    [[TMP1915:%.*]] = select i1 [[TMP1914]], i32 [[TMP1910]], i32 [[TMP1913]]
19256 // CHECK-NEXT:    store i32 [[TMP1915]], ptr [[IV]], align 4
19257 // CHECK-NEXT:    [[TMP1916:%.*]] = load i32, ptr [[IE]], align 4
19258 // CHECK-NEXT:    [[TMP1917:%.*]] = load i32, ptr [[ID]], align 4
19259 // CHECK-NEXT:    [[TMP1918:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1916]], i32 [[TMP1917]] monotonic monotonic, align 4
19260 // CHECK-NEXT:    [[TMP1919:%.*]] = extractvalue { i32, i1 } [[TMP1918]], 0
19261 // CHECK-NEXT:    [[TMP1920:%.*]] = extractvalue { i32, i1 } [[TMP1918]], 1
19262 // CHECK-NEXT:    br i1 [[TMP1920]], label [[IX_ATOMIC_EXIT:%.*]], label [[IX_ATOMIC_CONT:%.*]]
19263 // CHECK:       ix.atomic.cont:
19264 // CHECK-NEXT:    store i32 [[TMP1919]], ptr [[IV]], align 4
19265 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT]]
19266 // CHECK:       ix.atomic.exit:
19267 // CHECK-NEXT:    [[TMP1921:%.*]] = load i32, ptr [[IE]], align 4
19268 // CHECK-NEXT:    [[TMP1922:%.*]] = load i32, ptr [[ID]], align 4
19269 // CHECK-NEXT:    [[TMP1923:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1921]], i32 [[TMP1922]] monotonic monotonic, align 4
19270 // CHECK-NEXT:    [[TMP1924:%.*]] = extractvalue { i32, i1 } [[TMP1923]], 0
19271 // CHECK-NEXT:    [[TMP1925:%.*]] = extractvalue { i32, i1 } [[TMP1923]], 1
19272 // CHECK-NEXT:    br i1 [[TMP1925]], label [[IX_ATOMIC_EXIT185:%.*]], label [[IX_ATOMIC_CONT186:%.*]]
19273 // CHECK:       ix.atomic.cont186:
19274 // CHECK-NEXT:    store i32 [[TMP1924]], ptr [[IV]], align 4
19275 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT185]]
19276 // CHECK:       ix.atomic.exit185:
19277 // CHECK-NEXT:    [[TMP1926:%.*]] = load i32, ptr [[IE]], align 4
19278 // CHECK-NEXT:    [[TMP1927:%.*]] = load i32, ptr [[ID]], align 4
19279 // CHECK-NEXT:    [[TMP1928:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1926]], i32 [[TMP1927]] monotonic monotonic, align 4
19280 // CHECK-NEXT:    [[TMP1929:%.*]] = extractvalue { i32, i1 } [[TMP1928]], 1
19281 // CHECK-NEXT:    [[TMP1930:%.*]] = sext i1 [[TMP1929]] to i32
19282 // CHECK-NEXT:    store i32 [[TMP1930]], ptr [[IR]], align 4
19283 // CHECK-NEXT:    [[TMP1931:%.*]] = load i32, ptr [[IE]], align 4
19284 // CHECK-NEXT:    [[TMP1932:%.*]] = load i32, ptr [[ID]], align 4
19285 // CHECK-NEXT:    [[TMP1933:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1931]], i32 [[TMP1932]] monotonic monotonic, align 4
19286 // CHECK-NEXT:    [[TMP1934:%.*]] = extractvalue { i32, i1 } [[TMP1933]], 1
19287 // CHECK-NEXT:    [[TMP1935:%.*]] = sext i1 [[TMP1934]] to i32
19288 // CHECK-NEXT:    store i32 [[TMP1935]], ptr [[IR]], align 4
19289 // CHECK-NEXT:    [[TMP1936:%.*]] = load i32, ptr [[IE]], align 4
19290 // CHECK-NEXT:    [[TMP1937:%.*]] = load i32, ptr [[ID]], align 4
19291 // CHECK-NEXT:    [[TMP1938:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1936]], i32 [[TMP1937]] monotonic monotonic, align 4
19292 // CHECK-NEXT:    [[TMP1939:%.*]] = extractvalue { i32, i1 } [[TMP1938]], 0
19293 // CHECK-NEXT:    [[TMP1940:%.*]] = extractvalue { i32, i1 } [[TMP1938]], 1
19294 // CHECK-NEXT:    br i1 [[TMP1940]], label [[IX_ATOMIC_EXIT187:%.*]], label [[IX_ATOMIC_CONT188:%.*]]
19295 // CHECK:       ix.atomic.cont188:
19296 // CHECK-NEXT:    store i32 [[TMP1939]], ptr [[IV]], align 4
19297 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT187]]
19298 // CHECK:       ix.atomic.exit187:
19299 // CHECK-NEXT:    [[TMP1941:%.*]] = extractvalue { i32, i1 } [[TMP1938]], 1
19300 // CHECK-NEXT:    [[TMP1942:%.*]] = sext i1 [[TMP1941]] to i32
19301 // CHECK-NEXT:    store i32 [[TMP1942]], ptr [[IR]], align 4
19302 // CHECK-NEXT:    [[TMP1943:%.*]] = load i32, ptr [[IE]], align 4
19303 // CHECK-NEXT:    [[TMP1944:%.*]] = load i32, ptr [[ID]], align 4
19304 // CHECK-NEXT:    [[TMP1945:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1943]], i32 [[TMP1944]] monotonic monotonic, align 4
19305 // CHECK-NEXT:    [[TMP1946:%.*]] = extractvalue { i32, i1 } [[TMP1945]], 0
19306 // CHECK-NEXT:    [[TMP1947:%.*]] = extractvalue { i32, i1 } [[TMP1945]], 1
19307 // CHECK-NEXT:    br i1 [[TMP1947]], label [[IX_ATOMIC_EXIT189:%.*]], label [[IX_ATOMIC_CONT190:%.*]]
19308 // CHECK:       ix.atomic.cont190:
19309 // CHECK-NEXT:    store i32 [[TMP1946]], ptr [[IV]], align 4
19310 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT189]]
19311 // CHECK:       ix.atomic.exit189:
19312 // CHECK-NEXT:    [[TMP1948:%.*]] = extractvalue { i32, i1 } [[TMP1945]], 1
19313 // CHECK-NEXT:    [[TMP1949:%.*]] = sext i1 [[TMP1948]] to i32
19314 // CHECK-NEXT:    store i32 [[TMP1949]], ptr [[IR]], align 4
19315 // CHECK-NEXT:    [[TMP1950:%.*]] = load i32, ptr [[IE]], align 4
19316 // CHECK-NEXT:    [[TMP1951:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1950]] acq_rel, align 4
19317 // CHECK-NEXT:    store i32 [[TMP1951]], ptr [[IV]], align 4
19318 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19319 // CHECK-NEXT:    [[TMP1952:%.*]] = load i32, ptr [[IE]], align 4
19320 // CHECK-NEXT:    [[TMP1953:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1952]] acq_rel, align 4
19321 // CHECK-NEXT:    store i32 [[TMP1953]], ptr [[IV]], align 4
19322 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19323 // CHECK-NEXT:    [[TMP1954:%.*]] = load i32, ptr [[IE]], align 4
19324 // CHECK-NEXT:    [[TMP1955:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1954]] acq_rel, align 4
19325 // CHECK-NEXT:    store i32 [[TMP1955]], ptr [[IV]], align 4
19326 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19327 // CHECK-NEXT:    [[TMP1956:%.*]] = load i32, ptr [[IE]], align 4
19328 // CHECK-NEXT:    [[TMP1957:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1956]] acq_rel, align 4
19329 // CHECK-NEXT:    store i32 [[TMP1957]], ptr [[IV]], align 4
19330 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19331 // CHECK-NEXT:    [[TMP1958:%.*]] = load i32, ptr [[IE]], align 4
19332 // CHECK-NEXT:    [[TMP1959:%.*]] = load i32, ptr [[ID]], align 4
19333 // CHECK-NEXT:    [[TMP1960:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1958]], i32 [[TMP1959]] acq_rel acquire, align 4
19334 // CHECK-NEXT:    [[TMP1961:%.*]] = extractvalue { i32, i1 } [[TMP1960]], 0
19335 // CHECK-NEXT:    store i32 [[TMP1961]], ptr [[IV]], align 4
19336 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19337 // CHECK-NEXT:    [[TMP1962:%.*]] = load i32, ptr [[IE]], align 4
19338 // CHECK-NEXT:    [[TMP1963:%.*]] = load i32, ptr [[ID]], align 4
19339 // CHECK-NEXT:    [[TMP1964:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1962]], i32 [[TMP1963]] acq_rel acquire, align 4
19340 // CHECK-NEXT:    [[TMP1965:%.*]] = extractvalue { i32, i1 } [[TMP1964]], 0
19341 // CHECK-NEXT:    store i32 [[TMP1965]], ptr [[IV]], align 4
19342 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19343 // CHECK-NEXT:    [[TMP1966:%.*]] = load i32, ptr [[IE]], align 4
19344 // CHECK-NEXT:    [[TMP1967:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1966]] acq_rel, align 4
19345 // CHECK-NEXT:    [[TMP1968:%.*]] = icmp sgt i32 [[TMP1967]], [[TMP1966]]
19346 // CHECK-NEXT:    [[TMP1969:%.*]] = select i1 [[TMP1968]], i32 [[TMP1966]], i32 [[TMP1967]]
19347 // CHECK-NEXT:    store i32 [[TMP1969]], ptr [[IV]], align 4
19348 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19349 // CHECK-NEXT:    [[TMP1970:%.*]] = load i32, ptr [[IE]], align 4
19350 // CHECK-NEXT:    [[TMP1971:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1970]] acq_rel, align 4
19351 // CHECK-NEXT:    [[TMP1972:%.*]] = icmp slt i32 [[TMP1971]], [[TMP1970]]
19352 // CHECK-NEXT:    [[TMP1973:%.*]] = select i1 [[TMP1972]], i32 [[TMP1970]], i32 [[TMP1971]]
19353 // CHECK-NEXT:    store i32 [[TMP1973]], ptr [[IV]], align 4
19354 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19355 // CHECK-NEXT:    [[TMP1974:%.*]] = load i32, ptr [[IE]], align 4
19356 // CHECK-NEXT:    [[TMP1975:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1974]] acq_rel, align 4
19357 // CHECK-NEXT:    [[TMP1976:%.*]] = icmp slt i32 [[TMP1975]], [[TMP1974]]
19358 // CHECK-NEXT:    [[TMP1977:%.*]] = select i1 [[TMP1976]], i32 [[TMP1974]], i32 [[TMP1975]]
19359 // CHECK-NEXT:    store i32 [[TMP1977]], ptr [[IV]], align 4
19360 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19361 // CHECK-NEXT:    [[TMP1978:%.*]] = load i32, ptr [[IE]], align 4
19362 // CHECK-NEXT:    [[TMP1979:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1978]] acq_rel, align 4
19363 // CHECK-NEXT:    [[TMP1980:%.*]] = icmp sgt i32 [[TMP1979]], [[TMP1978]]
19364 // CHECK-NEXT:    [[TMP1981:%.*]] = select i1 [[TMP1980]], i32 [[TMP1978]], i32 [[TMP1979]]
19365 // CHECK-NEXT:    store i32 [[TMP1981]], ptr [[IV]], align 4
19366 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19367 // CHECK-NEXT:    [[TMP1982:%.*]] = load i32, ptr [[IE]], align 4
19368 // CHECK-NEXT:    [[TMP1983:%.*]] = load i32, ptr [[ID]], align 4
19369 // CHECK-NEXT:    [[TMP1984:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1982]], i32 [[TMP1983]] acq_rel acquire, align 4
19370 // CHECK-NEXT:    [[TMP1985:%.*]] = extractvalue { i32, i1 } [[TMP1984]], 0
19371 // CHECK-NEXT:    [[TMP1986:%.*]] = extractvalue { i32, i1 } [[TMP1984]], 1
19372 // CHECK-NEXT:    [[TMP1987:%.*]] = select i1 [[TMP1986]], i32 [[TMP1982]], i32 [[TMP1985]]
19373 // CHECK-NEXT:    store i32 [[TMP1987]], ptr [[IV]], align 4
19374 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19375 // CHECK-NEXT:    [[TMP1988:%.*]] = load i32, ptr [[IE]], align 4
19376 // CHECK-NEXT:    [[TMP1989:%.*]] = load i32, ptr [[ID]], align 4
19377 // CHECK-NEXT:    [[TMP1990:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1988]], i32 [[TMP1989]] acq_rel acquire, align 4
19378 // CHECK-NEXT:    [[TMP1991:%.*]] = extractvalue { i32, i1 } [[TMP1990]], 0
19379 // CHECK-NEXT:    [[TMP1992:%.*]] = extractvalue { i32, i1 } [[TMP1990]], 1
19380 // CHECK-NEXT:    [[TMP1993:%.*]] = select i1 [[TMP1992]], i32 [[TMP1988]], i32 [[TMP1991]]
19381 // CHECK-NEXT:    store i32 [[TMP1993]], ptr [[IV]], align 4
19382 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19383 // CHECK-NEXT:    [[TMP1994:%.*]] = load i32, ptr [[IE]], align 4
19384 // CHECK-NEXT:    [[TMP1995:%.*]] = load i32, ptr [[ID]], align 4
19385 // CHECK-NEXT:    [[TMP1996:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1994]], i32 [[TMP1995]] acq_rel acquire, align 4
19386 // CHECK-NEXT:    [[TMP1997:%.*]] = extractvalue { i32, i1 } [[TMP1996]], 0
19387 // CHECK-NEXT:    [[TMP1998:%.*]] = extractvalue { i32, i1 } [[TMP1996]], 1
19388 // CHECK-NEXT:    br i1 [[TMP1998]], label [[IX_ATOMIC_EXIT191:%.*]], label [[IX_ATOMIC_CONT192:%.*]]
19389 // CHECK:       ix.atomic.cont192:
19390 // CHECK-NEXT:    store i32 [[TMP1997]], ptr [[IV]], align 4
19391 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT191]]
19392 // CHECK:       ix.atomic.exit191:
19393 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19394 // CHECK-NEXT:    [[TMP1999:%.*]] = load i32, ptr [[IE]], align 4
19395 // CHECK-NEXT:    [[TMP2000:%.*]] = load i32, ptr [[ID]], align 4
19396 // CHECK-NEXT:    [[TMP2001:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1999]], i32 [[TMP2000]] acq_rel acquire, align 4
19397 // CHECK-NEXT:    [[TMP2002:%.*]] = extractvalue { i32, i1 } [[TMP2001]], 0
19398 // CHECK-NEXT:    [[TMP2003:%.*]] = extractvalue { i32, i1 } [[TMP2001]], 1
19399 // CHECK-NEXT:    br i1 [[TMP2003]], label [[IX_ATOMIC_EXIT193:%.*]], label [[IX_ATOMIC_CONT194:%.*]]
19400 // CHECK:       ix.atomic.cont194:
19401 // CHECK-NEXT:    store i32 [[TMP2002]], ptr [[IV]], align 4
19402 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT193]]
19403 // CHECK:       ix.atomic.exit193:
19404 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19405 // CHECK-NEXT:    [[TMP2004:%.*]] = load i32, ptr [[IE]], align 4
19406 // CHECK-NEXT:    [[TMP2005:%.*]] = load i32, ptr [[ID]], align 4
19407 // CHECK-NEXT:    [[TMP2006:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2004]], i32 [[TMP2005]] acq_rel acquire, align 4
19408 // CHECK-NEXT:    [[TMP2007:%.*]] = extractvalue { i32, i1 } [[TMP2006]], 1
19409 // CHECK-NEXT:    [[TMP2008:%.*]] = sext i1 [[TMP2007]] to i32
19410 // CHECK-NEXT:    store i32 [[TMP2008]], ptr [[IR]], align 4
19411 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19412 // CHECK-NEXT:    [[TMP2009:%.*]] = load i32, ptr [[IE]], align 4
19413 // CHECK-NEXT:    [[TMP2010:%.*]] = load i32, ptr [[ID]], align 4
19414 // CHECK-NEXT:    [[TMP2011:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2009]], i32 [[TMP2010]] acq_rel acquire, align 4
19415 // CHECK-NEXT:    [[TMP2012:%.*]] = extractvalue { i32, i1 } [[TMP2011]], 1
19416 // CHECK-NEXT:    [[TMP2013:%.*]] = sext i1 [[TMP2012]] to i32
19417 // CHECK-NEXT:    store i32 [[TMP2013]], ptr [[IR]], align 4
19418 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19419 // CHECK-NEXT:    [[TMP2014:%.*]] = load i32, ptr [[IE]], align 4
19420 // CHECK-NEXT:    [[TMP2015:%.*]] = load i32, ptr [[ID]], align 4
19421 // CHECK-NEXT:    [[TMP2016:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2014]], i32 [[TMP2015]] acq_rel acquire, align 4
19422 // CHECK-NEXT:    [[TMP2017:%.*]] = extractvalue { i32, i1 } [[TMP2016]], 0
19423 // CHECK-NEXT:    [[TMP2018:%.*]] = extractvalue { i32, i1 } [[TMP2016]], 1
19424 // CHECK-NEXT:    br i1 [[TMP2018]], label [[IX_ATOMIC_EXIT195:%.*]], label [[IX_ATOMIC_CONT196:%.*]]
19425 // CHECK:       ix.atomic.cont196:
19426 // CHECK-NEXT:    store i32 [[TMP2017]], ptr [[IV]], align 4
19427 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT195]]
19428 // CHECK:       ix.atomic.exit195:
19429 // CHECK-NEXT:    [[TMP2019:%.*]] = extractvalue { i32, i1 } [[TMP2016]], 1
19430 // CHECK-NEXT:    [[TMP2020:%.*]] = sext i1 [[TMP2019]] to i32
19431 // CHECK-NEXT:    store i32 [[TMP2020]], ptr [[IR]], align 4
19432 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19433 // CHECK-NEXT:    [[TMP2021:%.*]] = load i32, ptr [[IE]], align 4
19434 // CHECK-NEXT:    [[TMP2022:%.*]] = load i32, ptr [[ID]], align 4
19435 // CHECK-NEXT:    [[TMP2023:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2021]], i32 [[TMP2022]] acq_rel acquire, align 4
19436 // CHECK-NEXT:    [[TMP2024:%.*]] = extractvalue { i32, i1 } [[TMP2023]], 0
19437 // CHECK-NEXT:    [[TMP2025:%.*]] = extractvalue { i32, i1 } [[TMP2023]], 1
19438 // CHECK-NEXT:    br i1 [[TMP2025]], label [[IX_ATOMIC_EXIT197:%.*]], label [[IX_ATOMIC_CONT198:%.*]]
19439 // CHECK:       ix.atomic.cont198:
19440 // CHECK-NEXT:    store i32 [[TMP2024]], ptr [[IV]], align 4
19441 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT197]]
19442 // CHECK:       ix.atomic.exit197:
19443 // CHECK-NEXT:    [[TMP2026:%.*]] = extractvalue { i32, i1 } [[TMP2023]], 1
19444 // CHECK-NEXT:    [[TMP2027:%.*]] = sext i1 [[TMP2026]] to i32
19445 // CHECK-NEXT:    store i32 [[TMP2027]], ptr [[IR]], align 4
19446 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19447 // CHECK-NEXT:    [[TMP2028:%.*]] = load i32, ptr [[IE]], align 4
19448 // CHECK-NEXT:    [[TMP2029:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2028]] acquire, align 4
19449 // CHECK-NEXT:    store i32 [[TMP2029]], ptr [[IV]], align 4
19450 // CHECK-NEXT:    [[TMP2030:%.*]] = load i32, ptr [[IE]], align 4
19451 // CHECK-NEXT:    [[TMP2031:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2030]] acquire, align 4
19452 // CHECK-NEXT:    store i32 [[TMP2031]], ptr [[IV]], align 4
19453 // CHECK-NEXT:    [[TMP2032:%.*]] = load i32, ptr [[IE]], align 4
19454 // CHECK-NEXT:    [[TMP2033:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2032]] acquire, align 4
19455 // CHECK-NEXT:    store i32 [[TMP2033]], ptr [[IV]], align 4
19456 // CHECK-NEXT:    [[TMP2034:%.*]] = load i32, ptr [[IE]], align 4
19457 // CHECK-NEXT:    [[TMP2035:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2034]] acquire, align 4
19458 // CHECK-NEXT:    store i32 [[TMP2035]], ptr [[IV]], align 4
19459 // CHECK-NEXT:    [[TMP2036:%.*]] = load i32, ptr [[IE]], align 4
19460 // CHECK-NEXT:    [[TMP2037:%.*]] = load i32, ptr [[ID]], align 4
19461 // CHECK-NEXT:    [[TMP2038:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2036]], i32 [[TMP2037]] acquire acquire, align 4
19462 // CHECK-NEXT:    [[TMP2039:%.*]] = extractvalue { i32, i1 } [[TMP2038]], 0
19463 // CHECK-NEXT:    store i32 [[TMP2039]], ptr [[IV]], align 4
19464 // CHECK-NEXT:    [[TMP2040:%.*]] = load i32, ptr [[IE]], align 4
19465 // CHECK-NEXT:    [[TMP2041:%.*]] = load i32, ptr [[ID]], align 4
19466 // CHECK-NEXT:    [[TMP2042:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2040]], i32 [[TMP2041]] acquire acquire, align 4
19467 // CHECK-NEXT:    [[TMP2043:%.*]] = extractvalue { i32, i1 } [[TMP2042]], 0
19468 // CHECK-NEXT:    store i32 [[TMP2043]], ptr [[IV]], align 4
19469 // CHECK-NEXT:    [[TMP2044:%.*]] = load i32, ptr [[IE]], align 4
19470 // CHECK-NEXT:    [[TMP2045:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2044]] acquire, align 4
19471 // CHECK-NEXT:    [[TMP2046:%.*]] = icmp sgt i32 [[TMP2045]], [[TMP2044]]
19472 // CHECK-NEXT:    [[TMP2047:%.*]] = select i1 [[TMP2046]], i32 [[TMP2044]], i32 [[TMP2045]]
19473 // CHECK-NEXT:    store i32 [[TMP2047]], ptr [[IV]], align 4
19474 // CHECK-NEXT:    [[TMP2048:%.*]] = load i32, ptr [[IE]], align 4
19475 // CHECK-NEXT:    [[TMP2049:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2048]] acquire, align 4
19476 // CHECK-NEXT:    [[TMP2050:%.*]] = icmp slt i32 [[TMP2049]], [[TMP2048]]
19477 // CHECK-NEXT:    [[TMP2051:%.*]] = select i1 [[TMP2050]], i32 [[TMP2048]], i32 [[TMP2049]]
19478 // CHECK-NEXT:    store i32 [[TMP2051]], ptr [[IV]], align 4
19479 // CHECK-NEXT:    [[TMP2052:%.*]] = load i32, ptr [[IE]], align 4
19480 // CHECK-NEXT:    [[TMP2053:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2052]] acquire, align 4
19481 // CHECK-NEXT:    [[TMP2054:%.*]] = icmp slt i32 [[TMP2053]], [[TMP2052]]
19482 // CHECK-NEXT:    [[TMP2055:%.*]] = select i1 [[TMP2054]], i32 [[TMP2052]], i32 [[TMP2053]]
19483 // CHECK-NEXT:    store i32 [[TMP2055]], ptr [[IV]], align 4
19484 // CHECK-NEXT:    [[TMP2056:%.*]] = load i32, ptr [[IE]], align 4
19485 // CHECK-NEXT:    [[TMP2057:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2056]] acquire, align 4
19486 // CHECK-NEXT:    [[TMP2058:%.*]] = icmp sgt i32 [[TMP2057]], [[TMP2056]]
19487 // CHECK-NEXT:    [[TMP2059:%.*]] = select i1 [[TMP2058]], i32 [[TMP2056]], i32 [[TMP2057]]
19488 // CHECK-NEXT:    store i32 [[TMP2059]], ptr [[IV]], align 4
19489 // CHECK-NEXT:    [[TMP2060:%.*]] = load i32, ptr [[IE]], align 4
19490 // CHECK-NEXT:    [[TMP2061:%.*]] = load i32, ptr [[ID]], align 4
19491 // CHECK-NEXT:    [[TMP2062:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2060]], i32 [[TMP2061]] acquire acquire, align 4
19492 // CHECK-NEXT:    [[TMP2063:%.*]] = extractvalue { i32, i1 } [[TMP2062]], 0
19493 // CHECK-NEXT:    [[TMP2064:%.*]] = extractvalue { i32, i1 } [[TMP2062]], 1
19494 // CHECK-NEXT:    [[TMP2065:%.*]] = select i1 [[TMP2064]], i32 [[TMP2060]], i32 [[TMP2063]]
19495 // CHECK-NEXT:    store i32 [[TMP2065]], ptr [[IV]], align 4
19496 // CHECK-NEXT:    [[TMP2066:%.*]] = load i32, ptr [[IE]], align 4
19497 // CHECK-NEXT:    [[TMP2067:%.*]] = load i32, ptr [[ID]], align 4
19498 // CHECK-NEXT:    [[TMP2068:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2066]], i32 [[TMP2067]] acquire acquire, align 4
19499 // CHECK-NEXT:    [[TMP2069:%.*]] = extractvalue { i32, i1 } [[TMP2068]], 0
19500 // CHECK-NEXT:    [[TMP2070:%.*]] = extractvalue { i32, i1 } [[TMP2068]], 1
19501 // CHECK-NEXT:    [[TMP2071:%.*]] = select i1 [[TMP2070]], i32 [[TMP2066]], i32 [[TMP2069]]
19502 // CHECK-NEXT:    store i32 [[TMP2071]], ptr [[IV]], align 4
19503 // CHECK-NEXT:    [[TMP2072:%.*]] = load i32, ptr [[IE]], align 4
19504 // CHECK-NEXT:    [[TMP2073:%.*]] = load i32, ptr [[ID]], align 4
19505 // CHECK-NEXT:    [[TMP2074:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2072]], i32 [[TMP2073]] acquire acquire, align 4
19506 // CHECK-NEXT:    [[TMP2075:%.*]] = extractvalue { i32, i1 } [[TMP2074]], 0
19507 // CHECK-NEXT:    [[TMP2076:%.*]] = extractvalue { i32, i1 } [[TMP2074]], 1
19508 // CHECK-NEXT:    br i1 [[TMP2076]], label [[IX_ATOMIC_EXIT199:%.*]], label [[IX_ATOMIC_CONT200:%.*]]
19509 // CHECK:       ix.atomic.cont200:
19510 // CHECK-NEXT:    store i32 [[TMP2075]], ptr [[IV]], align 4
19511 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT199]]
19512 // CHECK:       ix.atomic.exit199:
19513 // CHECK-NEXT:    [[TMP2077:%.*]] = load i32, ptr [[IE]], align 4
19514 // CHECK-NEXT:    [[TMP2078:%.*]] = load i32, ptr [[ID]], align 4
19515 // CHECK-NEXT:    [[TMP2079:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2077]], i32 [[TMP2078]] acquire acquire, align 4
19516 // CHECK-NEXT:    [[TMP2080:%.*]] = extractvalue { i32, i1 } [[TMP2079]], 0
19517 // CHECK-NEXT:    [[TMP2081:%.*]] = extractvalue { i32, i1 } [[TMP2079]], 1
19518 // CHECK-NEXT:    br i1 [[TMP2081]], label [[IX_ATOMIC_EXIT201:%.*]], label [[IX_ATOMIC_CONT202:%.*]]
19519 // CHECK:       ix.atomic.cont202:
19520 // CHECK-NEXT:    store i32 [[TMP2080]], ptr [[IV]], align 4
19521 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT201]]
19522 // CHECK:       ix.atomic.exit201:
19523 // CHECK-NEXT:    [[TMP2082:%.*]] = load i32, ptr [[IE]], align 4
19524 // CHECK-NEXT:    [[TMP2083:%.*]] = load i32, ptr [[ID]], align 4
19525 // CHECK-NEXT:    [[TMP2084:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2082]], i32 [[TMP2083]] acquire acquire, align 4
19526 // CHECK-NEXT:    [[TMP2085:%.*]] = extractvalue { i32, i1 } [[TMP2084]], 1
19527 // CHECK-NEXT:    [[TMP2086:%.*]] = sext i1 [[TMP2085]] to i32
19528 // CHECK-NEXT:    store i32 [[TMP2086]], ptr [[IR]], align 4
19529 // CHECK-NEXT:    [[TMP2087:%.*]] = load i32, ptr [[IE]], align 4
19530 // CHECK-NEXT:    [[TMP2088:%.*]] = load i32, ptr [[ID]], align 4
19531 // CHECK-NEXT:    [[TMP2089:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2087]], i32 [[TMP2088]] acquire acquire, align 4
19532 // CHECK-NEXT:    [[TMP2090:%.*]] = extractvalue { i32, i1 } [[TMP2089]], 1
19533 // CHECK-NEXT:    [[TMP2091:%.*]] = sext i1 [[TMP2090]] to i32
19534 // CHECK-NEXT:    store i32 [[TMP2091]], ptr [[IR]], align 4
19535 // CHECK-NEXT:    [[TMP2092:%.*]] = load i32, ptr [[IE]], align 4
19536 // CHECK-NEXT:    [[TMP2093:%.*]] = load i32, ptr [[ID]], align 4
19537 // CHECK-NEXT:    [[TMP2094:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2092]], i32 [[TMP2093]] acquire acquire, align 4
19538 // CHECK-NEXT:    [[TMP2095:%.*]] = extractvalue { i32, i1 } [[TMP2094]], 0
19539 // CHECK-NEXT:    [[TMP2096:%.*]] = extractvalue { i32, i1 } [[TMP2094]], 1
19540 // CHECK-NEXT:    br i1 [[TMP2096]], label [[IX_ATOMIC_EXIT203:%.*]], label [[IX_ATOMIC_CONT204:%.*]]
19541 // CHECK:       ix.atomic.cont204:
19542 // CHECK-NEXT:    store i32 [[TMP2095]], ptr [[IV]], align 4
19543 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT203]]
19544 // CHECK:       ix.atomic.exit203:
19545 // CHECK-NEXT:    [[TMP2097:%.*]] = extractvalue { i32, i1 } [[TMP2094]], 1
19546 // CHECK-NEXT:    [[TMP2098:%.*]] = sext i1 [[TMP2097]] to i32
19547 // CHECK-NEXT:    store i32 [[TMP2098]], ptr [[IR]], align 4
19548 // CHECK-NEXT:    [[TMP2099:%.*]] = load i32, ptr [[IE]], align 4
19549 // CHECK-NEXT:    [[TMP2100:%.*]] = load i32, ptr [[ID]], align 4
19550 // CHECK-NEXT:    [[TMP2101:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2099]], i32 [[TMP2100]] acquire acquire, align 4
19551 // CHECK-NEXT:    [[TMP2102:%.*]] = extractvalue { i32, i1 } [[TMP2101]], 0
19552 // CHECK-NEXT:    [[TMP2103:%.*]] = extractvalue { i32, i1 } [[TMP2101]], 1
19553 // CHECK-NEXT:    br i1 [[TMP2103]], label [[IX_ATOMIC_EXIT205:%.*]], label [[IX_ATOMIC_CONT206:%.*]]
19554 // CHECK:       ix.atomic.cont206:
19555 // CHECK-NEXT:    store i32 [[TMP2102]], ptr [[IV]], align 4
19556 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT205]]
19557 // CHECK:       ix.atomic.exit205:
19558 // CHECK-NEXT:    [[TMP2104:%.*]] = extractvalue { i32, i1 } [[TMP2101]], 1
19559 // CHECK-NEXT:    [[TMP2105:%.*]] = sext i1 [[TMP2104]] to i32
19560 // CHECK-NEXT:    store i32 [[TMP2105]], ptr [[IR]], align 4
19561 // CHECK-NEXT:    [[TMP2106:%.*]] = load i32, ptr [[IE]], align 4
19562 // CHECK-NEXT:    [[TMP2107:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2106]] monotonic, align 4
19563 // CHECK-NEXT:    store i32 [[TMP2107]], ptr [[IV]], align 4
19564 // CHECK-NEXT:    [[TMP2108:%.*]] = load i32, ptr [[IE]], align 4
19565 // CHECK-NEXT:    [[TMP2109:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2108]] monotonic, align 4
19566 // CHECK-NEXT:    store i32 [[TMP2109]], ptr [[IV]], align 4
19567 // CHECK-NEXT:    [[TMP2110:%.*]] = load i32, ptr [[IE]], align 4
19568 // CHECK-NEXT:    [[TMP2111:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2110]] monotonic, align 4
19569 // CHECK-NEXT:    store i32 [[TMP2111]], ptr [[IV]], align 4
19570 // CHECK-NEXT:    [[TMP2112:%.*]] = load i32, ptr [[IE]], align 4
19571 // CHECK-NEXT:    [[TMP2113:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2112]] monotonic, align 4
19572 // CHECK-NEXT:    store i32 [[TMP2113]], ptr [[IV]], align 4
19573 // CHECK-NEXT:    [[TMP2114:%.*]] = load i32, ptr [[IE]], align 4
19574 // CHECK-NEXT:    [[TMP2115:%.*]] = load i32, ptr [[ID]], align 4
19575 // CHECK-NEXT:    [[TMP2116:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2114]], i32 [[TMP2115]] monotonic monotonic, align 4
19576 // CHECK-NEXT:    [[TMP2117:%.*]] = extractvalue { i32, i1 } [[TMP2116]], 0
19577 // CHECK-NEXT:    store i32 [[TMP2117]], ptr [[IV]], align 4
19578 // CHECK-NEXT:    [[TMP2118:%.*]] = load i32, ptr [[IE]], align 4
19579 // CHECK-NEXT:    [[TMP2119:%.*]] = load i32, ptr [[ID]], align 4
19580 // CHECK-NEXT:    [[TMP2120:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2118]], i32 [[TMP2119]] monotonic monotonic, align 4
19581 // CHECK-NEXT:    [[TMP2121:%.*]] = extractvalue { i32, i1 } [[TMP2120]], 0
19582 // CHECK-NEXT:    store i32 [[TMP2121]], ptr [[IV]], align 4
19583 // CHECK-NEXT:    [[TMP2122:%.*]] = load i32, ptr [[IE]], align 4
19584 // CHECK-NEXT:    [[TMP2123:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2122]] monotonic, align 4
19585 // CHECK-NEXT:    [[TMP2124:%.*]] = icmp sgt i32 [[TMP2123]], [[TMP2122]]
19586 // CHECK-NEXT:    [[TMP2125:%.*]] = select i1 [[TMP2124]], i32 [[TMP2122]], i32 [[TMP2123]]
19587 // CHECK-NEXT:    store i32 [[TMP2125]], ptr [[IV]], align 4
19588 // CHECK-NEXT:    [[TMP2126:%.*]] = load i32, ptr [[IE]], align 4
19589 // CHECK-NEXT:    [[TMP2127:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2126]] monotonic, align 4
19590 // CHECK-NEXT:    [[TMP2128:%.*]] = icmp slt i32 [[TMP2127]], [[TMP2126]]
19591 // CHECK-NEXT:    [[TMP2129:%.*]] = select i1 [[TMP2128]], i32 [[TMP2126]], i32 [[TMP2127]]
19592 // CHECK-NEXT:    store i32 [[TMP2129]], ptr [[IV]], align 4
19593 // CHECK-NEXT:    [[TMP2130:%.*]] = load i32, ptr [[IE]], align 4
19594 // CHECK-NEXT:    [[TMP2131:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2130]] monotonic, align 4
19595 // CHECK-NEXT:    [[TMP2132:%.*]] = icmp slt i32 [[TMP2131]], [[TMP2130]]
19596 // CHECK-NEXT:    [[TMP2133:%.*]] = select i1 [[TMP2132]], i32 [[TMP2130]], i32 [[TMP2131]]
19597 // CHECK-NEXT:    store i32 [[TMP2133]], ptr [[IV]], align 4
19598 // CHECK-NEXT:    [[TMP2134:%.*]] = load i32, ptr [[IE]], align 4
19599 // CHECK-NEXT:    [[TMP2135:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2134]] monotonic, align 4
19600 // CHECK-NEXT:    [[TMP2136:%.*]] = icmp sgt i32 [[TMP2135]], [[TMP2134]]
19601 // CHECK-NEXT:    [[TMP2137:%.*]] = select i1 [[TMP2136]], i32 [[TMP2134]], i32 [[TMP2135]]
19602 // CHECK-NEXT:    store i32 [[TMP2137]], ptr [[IV]], align 4
19603 // CHECK-NEXT:    [[TMP2138:%.*]] = load i32, ptr [[IE]], align 4
19604 // CHECK-NEXT:    [[TMP2139:%.*]] = load i32, ptr [[ID]], align 4
19605 // CHECK-NEXT:    [[TMP2140:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2138]], i32 [[TMP2139]] monotonic monotonic, align 4
19606 // CHECK-NEXT:    [[TMP2141:%.*]] = extractvalue { i32, i1 } [[TMP2140]], 0
19607 // CHECK-NEXT:    [[TMP2142:%.*]] = extractvalue { i32, i1 } [[TMP2140]], 1
19608 // CHECK-NEXT:    [[TMP2143:%.*]] = select i1 [[TMP2142]], i32 [[TMP2138]], i32 [[TMP2141]]
19609 // CHECK-NEXT:    store i32 [[TMP2143]], ptr [[IV]], align 4
19610 // CHECK-NEXT:    [[TMP2144:%.*]] = load i32, ptr [[IE]], align 4
19611 // CHECK-NEXT:    [[TMP2145:%.*]] = load i32, ptr [[ID]], align 4
19612 // CHECK-NEXT:    [[TMP2146:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2144]], i32 [[TMP2145]] monotonic monotonic, align 4
19613 // CHECK-NEXT:    [[TMP2147:%.*]] = extractvalue { i32, i1 } [[TMP2146]], 0
19614 // CHECK-NEXT:    [[TMP2148:%.*]] = extractvalue { i32, i1 } [[TMP2146]], 1
19615 // CHECK-NEXT:    [[TMP2149:%.*]] = select i1 [[TMP2148]], i32 [[TMP2144]], i32 [[TMP2147]]
19616 // CHECK-NEXT:    store i32 [[TMP2149]], ptr [[IV]], align 4
19617 // CHECK-NEXT:    [[TMP2150:%.*]] = load i32, ptr [[IE]], align 4
19618 // CHECK-NEXT:    [[TMP2151:%.*]] = load i32, ptr [[ID]], align 4
19619 // CHECK-NEXT:    [[TMP2152:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2150]], i32 [[TMP2151]] monotonic monotonic, align 4
19620 // CHECK-NEXT:    [[TMP2153:%.*]] = extractvalue { i32, i1 } [[TMP2152]], 0
19621 // CHECK-NEXT:    [[TMP2154:%.*]] = extractvalue { i32, i1 } [[TMP2152]], 1
19622 // CHECK-NEXT:    br i1 [[TMP2154]], label [[IX_ATOMIC_EXIT207:%.*]], label [[IX_ATOMIC_CONT208:%.*]]
19623 // CHECK:       ix.atomic.cont208:
19624 // CHECK-NEXT:    store i32 [[TMP2153]], ptr [[IV]], align 4
19625 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT207]]
19626 // CHECK:       ix.atomic.exit207:
19627 // CHECK-NEXT:    [[TMP2155:%.*]] = load i32, ptr [[IE]], align 4
19628 // CHECK-NEXT:    [[TMP2156:%.*]] = load i32, ptr [[ID]], align 4
19629 // CHECK-NEXT:    [[TMP2157:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2155]], i32 [[TMP2156]] monotonic monotonic, align 4
19630 // CHECK-NEXT:    [[TMP2158:%.*]] = extractvalue { i32, i1 } [[TMP2157]], 0
19631 // CHECK-NEXT:    [[TMP2159:%.*]] = extractvalue { i32, i1 } [[TMP2157]], 1
19632 // CHECK-NEXT:    br i1 [[TMP2159]], label [[IX_ATOMIC_EXIT209:%.*]], label [[IX_ATOMIC_CONT210:%.*]]
19633 // CHECK:       ix.atomic.cont210:
19634 // CHECK-NEXT:    store i32 [[TMP2158]], ptr [[IV]], align 4
19635 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT209]]
19636 // CHECK:       ix.atomic.exit209:
19637 // CHECK-NEXT:    [[TMP2160:%.*]] = load i32, ptr [[IE]], align 4
19638 // CHECK-NEXT:    [[TMP2161:%.*]] = load i32, ptr [[ID]], align 4
19639 // CHECK-NEXT:    [[TMP2162:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2160]], i32 [[TMP2161]] monotonic monotonic, align 4
19640 // CHECK-NEXT:    [[TMP2163:%.*]] = extractvalue { i32, i1 } [[TMP2162]], 1
19641 // CHECK-NEXT:    [[TMP2164:%.*]] = sext i1 [[TMP2163]] to i32
19642 // CHECK-NEXT:    store i32 [[TMP2164]], ptr [[IR]], align 4
19643 // CHECK-NEXT:    [[TMP2165:%.*]] = load i32, ptr [[IE]], align 4
19644 // CHECK-NEXT:    [[TMP2166:%.*]] = load i32, ptr [[ID]], align 4
19645 // CHECK-NEXT:    [[TMP2167:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2165]], i32 [[TMP2166]] monotonic monotonic, align 4
19646 // CHECK-NEXT:    [[TMP2168:%.*]] = extractvalue { i32, i1 } [[TMP2167]], 1
19647 // CHECK-NEXT:    [[TMP2169:%.*]] = sext i1 [[TMP2168]] to i32
19648 // CHECK-NEXT:    store i32 [[TMP2169]], ptr [[IR]], align 4
19649 // CHECK-NEXT:    [[TMP2170:%.*]] = load i32, ptr [[IE]], align 4
19650 // CHECK-NEXT:    [[TMP2171:%.*]] = load i32, ptr [[ID]], align 4
19651 // CHECK-NEXT:    [[TMP2172:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2170]], i32 [[TMP2171]] monotonic monotonic, align 4
19652 // CHECK-NEXT:    [[TMP2173:%.*]] = extractvalue { i32, i1 } [[TMP2172]], 0
19653 // CHECK-NEXT:    [[TMP2174:%.*]] = extractvalue { i32, i1 } [[TMP2172]], 1
19654 // CHECK-NEXT:    br i1 [[TMP2174]], label [[IX_ATOMIC_EXIT211:%.*]], label [[IX_ATOMIC_CONT212:%.*]]
19655 // CHECK:       ix.atomic.cont212:
19656 // CHECK-NEXT:    store i32 [[TMP2173]], ptr [[IV]], align 4
19657 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT211]]
19658 // CHECK:       ix.atomic.exit211:
19659 // CHECK-NEXT:    [[TMP2175:%.*]] = extractvalue { i32, i1 } [[TMP2172]], 1
19660 // CHECK-NEXT:    [[TMP2176:%.*]] = sext i1 [[TMP2175]] to i32
19661 // CHECK-NEXT:    store i32 [[TMP2176]], ptr [[IR]], align 4
19662 // CHECK-NEXT:    [[TMP2177:%.*]] = load i32, ptr [[IE]], align 4
19663 // CHECK-NEXT:    [[TMP2178:%.*]] = load i32, ptr [[ID]], align 4
19664 // CHECK-NEXT:    [[TMP2179:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2177]], i32 [[TMP2178]] monotonic monotonic, align 4
19665 // CHECK-NEXT:    [[TMP2180:%.*]] = extractvalue { i32, i1 } [[TMP2179]], 0
19666 // CHECK-NEXT:    [[TMP2181:%.*]] = extractvalue { i32, i1 } [[TMP2179]], 1
19667 // CHECK-NEXT:    br i1 [[TMP2181]], label [[IX_ATOMIC_EXIT213:%.*]], label [[IX_ATOMIC_CONT214:%.*]]
19668 // CHECK:       ix.atomic.cont214:
19669 // CHECK-NEXT:    store i32 [[TMP2180]], ptr [[IV]], align 4
19670 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT213]]
19671 // CHECK:       ix.atomic.exit213:
19672 // CHECK-NEXT:    [[TMP2182:%.*]] = extractvalue { i32, i1 } [[TMP2179]], 1
19673 // CHECK-NEXT:    [[TMP2183:%.*]] = sext i1 [[TMP2182]] to i32
19674 // CHECK-NEXT:    store i32 [[TMP2183]], ptr [[IR]], align 4
19675 // CHECK-NEXT:    [[TMP2184:%.*]] = load i32, ptr [[IE]], align 4
19676 // CHECK-NEXT:    [[TMP2185:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2184]] release, align 4
19677 // CHECK-NEXT:    store i32 [[TMP2185]], ptr [[IV]], align 4
19678 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19679 // CHECK-NEXT:    [[TMP2186:%.*]] = load i32, ptr [[IE]], align 4
19680 // CHECK-NEXT:    [[TMP2187:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2186]] release, align 4
19681 // CHECK-NEXT:    store i32 [[TMP2187]], ptr [[IV]], align 4
19682 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19683 // CHECK-NEXT:    [[TMP2188:%.*]] = load i32, ptr [[IE]], align 4
19684 // CHECK-NEXT:    [[TMP2189:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2188]] release, align 4
19685 // CHECK-NEXT:    store i32 [[TMP2189]], ptr [[IV]], align 4
19686 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19687 // CHECK-NEXT:    [[TMP2190:%.*]] = load i32, ptr [[IE]], align 4
19688 // CHECK-NEXT:    [[TMP2191:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2190]] release, align 4
19689 // CHECK-NEXT:    store i32 [[TMP2191]], ptr [[IV]], align 4
19690 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19691 // CHECK-NEXT:    [[TMP2192:%.*]] = load i32, ptr [[IE]], align 4
19692 // CHECK-NEXT:    [[TMP2193:%.*]] = load i32, ptr [[ID]], align 4
19693 // CHECK-NEXT:    [[TMP2194:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2192]], i32 [[TMP2193]] release monotonic, align 4
19694 // CHECK-NEXT:    [[TMP2195:%.*]] = extractvalue { i32, i1 } [[TMP2194]], 0
19695 // CHECK-NEXT:    store i32 [[TMP2195]], ptr [[IV]], align 4
19696 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19697 // CHECK-NEXT:    [[TMP2196:%.*]] = load i32, ptr [[IE]], align 4
19698 // CHECK-NEXT:    [[TMP2197:%.*]] = load i32, ptr [[ID]], align 4
19699 // CHECK-NEXT:    [[TMP2198:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2196]], i32 [[TMP2197]] release monotonic, align 4
19700 // CHECK-NEXT:    [[TMP2199:%.*]] = extractvalue { i32, i1 } [[TMP2198]], 0
19701 // CHECK-NEXT:    store i32 [[TMP2199]], ptr [[IV]], align 4
19702 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19703 // CHECK-NEXT:    [[TMP2200:%.*]] = load i32, ptr [[IE]], align 4
19704 // CHECK-NEXT:    [[TMP2201:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2200]] release, align 4
19705 // CHECK-NEXT:    [[TMP2202:%.*]] = icmp sgt i32 [[TMP2201]], [[TMP2200]]
19706 // CHECK-NEXT:    [[TMP2203:%.*]] = select i1 [[TMP2202]], i32 [[TMP2200]], i32 [[TMP2201]]
19707 // CHECK-NEXT:    store i32 [[TMP2203]], ptr [[IV]], align 4
19708 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19709 // CHECK-NEXT:    [[TMP2204:%.*]] = load i32, ptr [[IE]], align 4
19710 // CHECK-NEXT:    [[TMP2205:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2204]] release, align 4
19711 // CHECK-NEXT:    [[TMP2206:%.*]] = icmp slt i32 [[TMP2205]], [[TMP2204]]
19712 // CHECK-NEXT:    [[TMP2207:%.*]] = select i1 [[TMP2206]], i32 [[TMP2204]], i32 [[TMP2205]]
19713 // CHECK-NEXT:    store i32 [[TMP2207]], ptr [[IV]], align 4
19714 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19715 // CHECK-NEXT:    [[TMP2208:%.*]] = load i32, ptr [[IE]], align 4
19716 // CHECK-NEXT:    [[TMP2209:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2208]] release, align 4
19717 // CHECK-NEXT:    [[TMP2210:%.*]] = icmp slt i32 [[TMP2209]], [[TMP2208]]
19718 // CHECK-NEXT:    [[TMP2211:%.*]] = select i1 [[TMP2210]], i32 [[TMP2208]], i32 [[TMP2209]]
19719 // CHECK-NEXT:    store i32 [[TMP2211]], ptr [[IV]], align 4
19720 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19721 // CHECK-NEXT:    [[TMP2212:%.*]] = load i32, ptr [[IE]], align 4
19722 // CHECK-NEXT:    [[TMP2213:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2212]] release, align 4
19723 // CHECK-NEXT:    [[TMP2214:%.*]] = icmp sgt i32 [[TMP2213]], [[TMP2212]]
19724 // CHECK-NEXT:    [[TMP2215:%.*]] = select i1 [[TMP2214]], i32 [[TMP2212]], i32 [[TMP2213]]
19725 // CHECK-NEXT:    store i32 [[TMP2215]], ptr [[IV]], align 4
19726 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19727 // CHECK-NEXT:    [[TMP2216:%.*]] = load i32, ptr [[IE]], align 4
19728 // CHECK-NEXT:    [[TMP2217:%.*]] = load i32, ptr [[ID]], align 4
19729 // CHECK-NEXT:    [[TMP2218:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2216]], i32 [[TMP2217]] release monotonic, align 4
19730 // CHECK-NEXT:    [[TMP2219:%.*]] = extractvalue { i32, i1 } [[TMP2218]], 0
19731 // CHECK-NEXT:    [[TMP2220:%.*]] = extractvalue { i32, i1 } [[TMP2218]], 1
19732 // CHECK-NEXT:    [[TMP2221:%.*]] = select i1 [[TMP2220]], i32 [[TMP2216]], i32 [[TMP2219]]
19733 // CHECK-NEXT:    store i32 [[TMP2221]], ptr [[IV]], align 4
19734 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19735 // CHECK-NEXT:    [[TMP2222:%.*]] = load i32, ptr [[IE]], align 4
19736 // CHECK-NEXT:    [[TMP2223:%.*]] = load i32, ptr [[ID]], align 4
19737 // CHECK-NEXT:    [[TMP2224:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2222]], i32 [[TMP2223]] release monotonic, align 4
19738 // CHECK-NEXT:    [[TMP2225:%.*]] = extractvalue { i32, i1 } [[TMP2224]], 0
19739 // CHECK-NEXT:    [[TMP2226:%.*]] = extractvalue { i32, i1 } [[TMP2224]], 1
19740 // CHECK-NEXT:    [[TMP2227:%.*]] = select i1 [[TMP2226]], i32 [[TMP2222]], i32 [[TMP2225]]
19741 // CHECK-NEXT:    store i32 [[TMP2227]], ptr [[IV]], align 4
19742 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19743 // CHECK-NEXT:    [[TMP2228:%.*]] = load i32, ptr [[IE]], align 4
19744 // CHECK-NEXT:    [[TMP2229:%.*]] = load i32, ptr [[ID]], align 4
19745 // CHECK-NEXT:    [[TMP2230:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2228]], i32 [[TMP2229]] release monotonic, align 4
19746 // CHECK-NEXT:    [[TMP2231:%.*]] = extractvalue { i32, i1 } [[TMP2230]], 0
19747 // CHECK-NEXT:    [[TMP2232:%.*]] = extractvalue { i32, i1 } [[TMP2230]], 1
19748 // CHECK-NEXT:    br i1 [[TMP2232]], label [[IX_ATOMIC_EXIT215:%.*]], label [[IX_ATOMIC_CONT216:%.*]]
19749 // CHECK:       ix.atomic.cont216:
19750 // CHECK-NEXT:    store i32 [[TMP2231]], ptr [[IV]], align 4
19751 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT215]]
19752 // CHECK:       ix.atomic.exit215:
19753 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19754 // CHECK-NEXT:    [[TMP2233:%.*]] = load i32, ptr [[IE]], align 4
19755 // CHECK-NEXT:    [[TMP2234:%.*]] = load i32, ptr [[ID]], align 4
19756 // CHECK-NEXT:    [[TMP2235:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2233]], i32 [[TMP2234]] release monotonic, align 4
19757 // CHECK-NEXT:    [[TMP2236:%.*]] = extractvalue { i32, i1 } [[TMP2235]], 0
19758 // CHECK-NEXT:    [[TMP2237:%.*]] = extractvalue { i32, i1 } [[TMP2235]], 1
19759 // CHECK-NEXT:    br i1 [[TMP2237]], label [[IX_ATOMIC_EXIT217:%.*]], label [[IX_ATOMIC_CONT218:%.*]]
19760 // CHECK:       ix.atomic.cont218:
19761 // CHECK-NEXT:    store i32 [[TMP2236]], ptr [[IV]], align 4
19762 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT217]]
19763 // CHECK:       ix.atomic.exit217:
19764 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19765 // CHECK-NEXT:    [[TMP2238:%.*]] = load i32, ptr [[IE]], align 4
19766 // CHECK-NEXT:    [[TMP2239:%.*]] = load i32, ptr [[ID]], align 4
19767 // CHECK-NEXT:    [[TMP2240:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2238]], i32 [[TMP2239]] release monotonic, align 4
19768 // CHECK-NEXT:    [[TMP2241:%.*]] = extractvalue { i32, i1 } [[TMP2240]], 1
19769 // CHECK-NEXT:    [[TMP2242:%.*]] = sext i1 [[TMP2241]] to i32
19770 // CHECK-NEXT:    store i32 [[TMP2242]], ptr [[IR]], align 4
19771 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19772 // CHECK-NEXT:    [[TMP2243:%.*]] = load i32, ptr [[IE]], align 4
19773 // CHECK-NEXT:    [[TMP2244:%.*]] = load i32, ptr [[ID]], align 4
19774 // CHECK-NEXT:    [[TMP2245:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2243]], i32 [[TMP2244]] release monotonic, align 4
19775 // CHECK-NEXT:    [[TMP2246:%.*]] = extractvalue { i32, i1 } [[TMP2245]], 1
19776 // CHECK-NEXT:    [[TMP2247:%.*]] = sext i1 [[TMP2246]] to i32
19777 // CHECK-NEXT:    store i32 [[TMP2247]], ptr [[IR]], align 4
19778 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19779 // CHECK-NEXT:    [[TMP2248:%.*]] = load i32, ptr [[IE]], align 4
19780 // CHECK-NEXT:    [[TMP2249:%.*]] = load i32, ptr [[ID]], align 4
19781 // CHECK-NEXT:    [[TMP2250:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2248]], i32 [[TMP2249]] release monotonic, align 4
19782 // CHECK-NEXT:    [[TMP2251:%.*]] = extractvalue { i32, i1 } [[TMP2250]], 0
19783 // CHECK-NEXT:    [[TMP2252:%.*]] = extractvalue { i32, i1 } [[TMP2250]], 1
19784 // CHECK-NEXT:    br i1 [[TMP2252]], label [[IX_ATOMIC_EXIT219:%.*]], label [[IX_ATOMIC_CONT220:%.*]]
19785 // CHECK:       ix.atomic.cont220:
19786 // CHECK-NEXT:    store i32 [[TMP2251]], ptr [[IV]], align 4
19787 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT219]]
19788 // CHECK:       ix.atomic.exit219:
19789 // CHECK-NEXT:    [[TMP2253:%.*]] = extractvalue { i32, i1 } [[TMP2250]], 1
19790 // CHECK-NEXT:    [[TMP2254:%.*]] = sext i1 [[TMP2253]] to i32
19791 // CHECK-NEXT:    store i32 [[TMP2254]], ptr [[IR]], align 4
19792 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19793 // CHECK-NEXT:    [[TMP2255:%.*]] = load i32, ptr [[IE]], align 4
19794 // CHECK-NEXT:    [[TMP2256:%.*]] = load i32, ptr [[ID]], align 4
19795 // CHECK-NEXT:    [[TMP2257:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2255]], i32 [[TMP2256]] release monotonic, align 4
19796 // CHECK-NEXT:    [[TMP2258:%.*]] = extractvalue { i32, i1 } [[TMP2257]], 0
19797 // CHECK-NEXT:    [[TMP2259:%.*]] = extractvalue { i32, i1 } [[TMP2257]], 1
19798 // CHECK-NEXT:    br i1 [[TMP2259]], label [[IX_ATOMIC_EXIT221:%.*]], label [[IX_ATOMIC_CONT222:%.*]]
19799 // CHECK:       ix.atomic.cont222:
19800 // CHECK-NEXT:    store i32 [[TMP2258]], ptr [[IV]], align 4
19801 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT221]]
19802 // CHECK:       ix.atomic.exit221:
19803 // CHECK-NEXT:    [[TMP2260:%.*]] = extractvalue { i32, i1 } [[TMP2257]], 1
19804 // CHECK-NEXT:    [[TMP2261:%.*]] = sext i1 [[TMP2260]] to i32
19805 // CHECK-NEXT:    store i32 [[TMP2261]], ptr [[IR]], align 4
19806 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19807 // CHECK-NEXT:    [[TMP2262:%.*]] = load i32, ptr [[IE]], align 4
19808 // CHECK-NEXT:    [[TMP2263:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2262]] seq_cst, align 4
19809 // CHECK-NEXT:    store i32 [[TMP2263]], ptr [[IV]], align 4
19810 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19811 // CHECK-NEXT:    [[TMP2264:%.*]] = load i32, ptr [[IE]], align 4
19812 // CHECK-NEXT:    [[TMP2265:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2264]] seq_cst, align 4
19813 // CHECK-NEXT:    store i32 [[TMP2265]], ptr [[IV]], align 4
19814 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19815 // CHECK-NEXT:    [[TMP2266:%.*]] = load i32, ptr [[IE]], align 4
19816 // CHECK-NEXT:    [[TMP2267:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2266]] seq_cst, align 4
19817 // CHECK-NEXT:    store i32 [[TMP2267]], ptr [[IV]], align 4
19818 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19819 // CHECK-NEXT:    [[TMP2268:%.*]] = load i32, ptr [[IE]], align 4
19820 // CHECK-NEXT:    [[TMP2269:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2268]] seq_cst, align 4
19821 // CHECK-NEXT:    store i32 [[TMP2269]], ptr [[IV]], align 4
19822 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19823 // CHECK-NEXT:    [[TMP2270:%.*]] = load i32, ptr [[IE]], align 4
19824 // CHECK-NEXT:    [[TMP2271:%.*]] = load i32, ptr [[ID]], align 4
19825 // CHECK-NEXT:    [[TMP2272:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2270]], i32 [[TMP2271]] seq_cst seq_cst, align 4
19826 // CHECK-NEXT:    [[TMP2273:%.*]] = extractvalue { i32, i1 } [[TMP2272]], 0
19827 // CHECK-NEXT:    store i32 [[TMP2273]], ptr [[IV]], align 4
19828 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19829 // CHECK-NEXT:    [[TMP2274:%.*]] = load i32, ptr [[IE]], align 4
19830 // CHECK-NEXT:    [[TMP2275:%.*]] = load i32, ptr [[ID]], align 4
19831 // CHECK-NEXT:    [[TMP2276:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2274]], i32 [[TMP2275]] seq_cst seq_cst, align 4
19832 // CHECK-NEXT:    [[TMP2277:%.*]] = extractvalue { i32, i1 } [[TMP2276]], 0
19833 // CHECK-NEXT:    store i32 [[TMP2277]], ptr [[IV]], align 4
19834 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19835 // CHECK-NEXT:    [[TMP2278:%.*]] = load i32, ptr [[IE]], align 4
19836 // CHECK-NEXT:    [[TMP2279:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2278]] seq_cst, align 4
19837 // CHECK-NEXT:    [[TMP2280:%.*]] = icmp sgt i32 [[TMP2279]], [[TMP2278]]
19838 // CHECK-NEXT:    [[TMP2281:%.*]] = select i1 [[TMP2280]], i32 [[TMP2278]], i32 [[TMP2279]]
19839 // CHECK-NEXT:    store i32 [[TMP2281]], ptr [[IV]], align 4
19840 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19841 // CHECK-NEXT:    [[TMP2282:%.*]] = load i32, ptr [[IE]], align 4
19842 // CHECK-NEXT:    [[TMP2283:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2282]] seq_cst, align 4
19843 // CHECK-NEXT:    [[TMP2284:%.*]] = icmp slt i32 [[TMP2283]], [[TMP2282]]
19844 // CHECK-NEXT:    [[TMP2285:%.*]] = select i1 [[TMP2284]], i32 [[TMP2282]], i32 [[TMP2283]]
19845 // CHECK-NEXT:    store i32 [[TMP2285]], ptr [[IV]], align 4
19846 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19847 // CHECK-NEXT:    [[TMP2286:%.*]] = load i32, ptr [[IE]], align 4
19848 // CHECK-NEXT:    [[TMP2287:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2286]] seq_cst, align 4
19849 // CHECK-NEXT:    [[TMP2288:%.*]] = icmp slt i32 [[TMP2287]], [[TMP2286]]
19850 // CHECK-NEXT:    [[TMP2289:%.*]] = select i1 [[TMP2288]], i32 [[TMP2286]], i32 [[TMP2287]]
19851 // CHECK-NEXT:    store i32 [[TMP2289]], ptr [[IV]], align 4
19852 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19853 // CHECK-NEXT:    [[TMP2290:%.*]] = load i32, ptr [[IE]], align 4
19854 // CHECK-NEXT:    [[TMP2291:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2290]] seq_cst, align 4
19855 // CHECK-NEXT:    [[TMP2292:%.*]] = icmp sgt i32 [[TMP2291]], [[TMP2290]]
19856 // CHECK-NEXT:    [[TMP2293:%.*]] = select i1 [[TMP2292]], i32 [[TMP2290]], i32 [[TMP2291]]
19857 // CHECK-NEXT:    store i32 [[TMP2293]], ptr [[IV]], align 4
19858 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19859 // CHECK-NEXT:    [[TMP2294:%.*]] = load i32, ptr [[IE]], align 4
19860 // CHECK-NEXT:    [[TMP2295:%.*]] = load i32, ptr [[ID]], align 4
19861 // CHECK-NEXT:    [[TMP2296:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2294]], i32 [[TMP2295]] seq_cst seq_cst, align 4
19862 // CHECK-NEXT:    [[TMP2297:%.*]] = extractvalue { i32, i1 } [[TMP2296]], 0
19863 // CHECK-NEXT:    [[TMP2298:%.*]] = extractvalue { i32, i1 } [[TMP2296]], 1
19864 // CHECK-NEXT:    [[TMP2299:%.*]] = select i1 [[TMP2298]], i32 [[TMP2294]], i32 [[TMP2297]]
19865 // CHECK-NEXT:    store i32 [[TMP2299]], ptr [[IV]], align 4
19866 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19867 // CHECK-NEXT:    [[TMP2300:%.*]] = load i32, ptr [[IE]], align 4
19868 // CHECK-NEXT:    [[TMP2301:%.*]] = load i32, ptr [[ID]], align 4
19869 // CHECK-NEXT:    [[TMP2302:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2300]], i32 [[TMP2301]] seq_cst seq_cst, align 4
19870 // CHECK-NEXT:    [[TMP2303:%.*]] = extractvalue { i32, i1 } [[TMP2302]], 0
19871 // CHECK-NEXT:    [[TMP2304:%.*]] = extractvalue { i32, i1 } [[TMP2302]], 1
19872 // CHECK-NEXT:    [[TMP2305:%.*]] = select i1 [[TMP2304]], i32 [[TMP2300]], i32 [[TMP2303]]
19873 // CHECK-NEXT:    store i32 [[TMP2305]], ptr [[IV]], align 4
19874 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19875 // CHECK-NEXT:    [[TMP2306:%.*]] = load i32, ptr [[IE]], align 4
19876 // CHECK-NEXT:    [[TMP2307:%.*]] = load i32, ptr [[ID]], align 4
19877 // CHECK-NEXT:    [[TMP2308:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2306]], i32 [[TMP2307]] seq_cst seq_cst, align 4
19878 // CHECK-NEXT:    [[TMP2309:%.*]] = extractvalue { i32, i1 } [[TMP2308]], 0
19879 // CHECK-NEXT:    [[TMP2310:%.*]] = extractvalue { i32, i1 } [[TMP2308]], 1
19880 // CHECK-NEXT:    br i1 [[TMP2310]], label [[IX_ATOMIC_EXIT223:%.*]], label [[IX_ATOMIC_CONT224:%.*]]
19881 // CHECK:       ix.atomic.cont224:
19882 // CHECK-NEXT:    store i32 [[TMP2309]], ptr [[IV]], align 4
19883 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT223]]
19884 // CHECK:       ix.atomic.exit223:
19885 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19886 // CHECK-NEXT:    [[TMP2311:%.*]] = load i32, ptr [[IE]], align 4
19887 // CHECK-NEXT:    [[TMP2312:%.*]] = load i32, ptr [[ID]], align 4
19888 // CHECK-NEXT:    [[TMP2313:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2311]], i32 [[TMP2312]] seq_cst seq_cst, align 4
19889 // CHECK-NEXT:    [[TMP2314:%.*]] = extractvalue { i32, i1 } [[TMP2313]], 0
19890 // CHECK-NEXT:    [[TMP2315:%.*]] = extractvalue { i32, i1 } [[TMP2313]], 1
19891 // CHECK-NEXT:    br i1 [[TMP2315]], label [[IX_ATOMIC_EXIT225:%.*]], label [[IX_ATOMIC_CONT226:%.*]]
19892 // CHECK:       ix.atomic.cont226:
19893 // CHECK-NEXT:    store i32 [[TMP2314]], ptr [[IV]], align 4
19894 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT225]]
19895 // CHECK:       ix.atomic.exit225:
19896 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19897 // CHECK-NEXT:    [[TMP2316:%.*]] = load i32, ptr [[IE]], align 4
19898 // CHECK-NEXT:    [[TMP2317:%.*]] = load i32, ptr [[ID]], align 4
19899 // CHECK-NEXT:    [[TMP2318:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2316]], i32 [[TMP2317]] seq_cst seq_cst, align 4
19900 // CHECK-NEXT:    [[TMP2319:%.*]] = extractvalue { i32, i1 } [[TMP2318]], 1
19901 // CHECK-NEXT:    [[TMP2320:%.*]] = sext i1 [[TMP2319]] to i32
19902 // CHECK-NEXT:    store i32 [[TMP2320]], ptr [[IR]], align 4
19903 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19904 // CHECK-NEXT:    [[TMP2321:%.*]] = load i32, ptr [[IE]], align 4
19905 // CHECK-NEXT:    [[TMP2322:%.*]] = load i32, ptr [[ID]], align 4
19906 // CHECK-NEXT:    [[TMP2323:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2321]], i32 [[TMP2322]] seq_cst seq_cst, align 4
19907 // CHECK-NEXT:    [[TMP2324:%.*]] = extractvalue { i32, i1 } [[TMP2323]], 1
19908 // CHECK-NEXT:    [[TMP2325:%.*]] = sext i1 [[TMP2324]] to i32
19909 // CHECK-NEXT:    store i32 [[TMP2325]], ptr [[IR]], align 4
19910 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19911 // CHECK-NEXT:    [[TMP2326:%.*]] = load i32, ptr [[IE]], align 4
19912 // CHECK-NEXT:    [[TMP2327:%.*]] = load i32, ptr [[ID]], align 4
19913 // CHECK-NEXT:    [[TMP2328:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2326]], i32 [[TMP2327]] seq_cst seq_cst, align 4
19914 // CHECK-NEXT:    [[TMP2329:%.*]] = extractvalue { i32, i1 } [[TMP2328]], 0
19915 // CHECK-NEXT:    [[TMP2330:%.*]] = extractvalue { i32, i1 } [[TMP2328]], 1
19916 // CHECK-NEXT:    br i1 [[TMP2330]], label [[IX_ATOMIC_EXIT227:%.*]], label [[IX_ATOMIC_CONT228:%.*]]
19917 // CHECK:       ix.atomic.cont228:
19918 // CHECK-NEXT:    store i32 [[TMP2329]], ptr [[IV]], align 4
19919 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT227]]
19920 // CHECK:       ix.atomic.exit227:
19921 // CHECK-NEXT:    [[TMP2331:%.*]] = extractvalue { i32, i1 } [[TMP2328]], 1
19922 // CHECK-NEXT:    [[TMP2332:%.*]] = sext i1 [[TMP2331]] to i32
19923 // CHECK-NEXT:    store i32 [[TMP2332]], ptr [[IR]], align 4
19924 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19925 // CHECK-NEXT:    [[TMP2333:%.*]] = load i32, ptr [[IE]], align 4
19926 // CHECK-NEXT:    [[TMP2334:%.*]] = load i32, ptr [[ID]], align 4
19927 // CHECK-NEXT:    [[TMP2335:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2333]], i32 [[TMP2334]] seq_cst seq_cst, align 4
19928 // CHECK-NEXT:    [[TMP2336:%.*]] = extractvalue { i32, i1 } [[TMP2335]], 0
19929 // CHECK-NEXT:    [[TMP2337:%.*]] = extractvalue { i32, i1 } [[TMP2335]], 1
19930 // CHECK-NEXT:    br i1 [[TMP2337]], label [[IX_ATOMIC_EXIT229:%.*]], label [[IX_ATOMIC_CONT230:%.*]]
19931 // CHECK:       ix.atomic.cont230:
19932 // CHECK-NEXT:    store i32 [[TMP2336]], ptr [[IV]], align 4
19933 // CHECK-NEXT:    br label [[IX_ATOMIC_EXIT229]]
19934 // CHECK:       ix.atomic.exit229:
19935 // CHECK-NEXT:    [[TMP2338:%.*]] = extractvalue { i32, i1 } [[TMP2335]], 1
19936 // CHECK-NEXT:    [[TMP2339:%.*]] = sext i1 [[TMP2338]] to i32
19937 // CHECK-NEXT:    store i32 [[TMP2339]], ptr [[IR]], align 4
19938 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
19939 // CHECK-NEXT:    [[TMP2340:%.*]] = load i32, ptr [[UIE]], align 4
19940 // CHECK-NEXT:    [[TMP2341:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2340]] monotonic, align 4
19941 // CHECK-NEXT:    store i32 [[TMP2341]], ptr [[UIV]], align 4
19942 // CHECK-NEXT:    [[TMP2342:%.*]] = load i32, ptr [[UIE]], align 4
19943 // CHECK-NEXT:    [[TMP2343:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2342]] monotonic, align 4
19944 // CHECK-NEXT:    store i32 [[TMP2343]], ptr [[UIV]], align 4
19945 // CHECK-NEXT:    [[TMP2344:%.*]] = load i32, ptr [[UIE]], align 4
19946 // CHECK-NEXT:    [[TMP2345:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2344]] monotonic, align 4
19947 // CHECK-NEXT:    store i32 [[TMP2345]], ptr [[UIV]], align 4
19948 // CHECK-NEXT:    [[TMP2346:%.*]] = load i32, ptr [[UIE]], align 4
19949 // CHECK-NEXT:    [[TMP2347:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2346]] monotonic, align 4
19950 // CHECK-NEXT:    store i32 [[TMP2347]], ptr [[UIV]], align 4
19951 // CHECK-NEXT:    [[TMP2348:%.*]] = load i32, ptr [[UIE]], align 4
19952 // CHECK-NEXT:    [[TMP2349:%.*]] = load i32, ptr [[UID]], align 4
19953 // CHECK-NEXT:    [[TMP2350:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2348]], i32 [[TMP2349]] monotonic monotonic, align 4
19954 // CHECK-NEXT:    [[TMP2351:%.*]] = extractvalue { i32, i1 } [[TMP2350]], 0
19955 // CHECK-NEXT:    store i32 [[TMP2351]], ptr [[UIV]], align 4
19956 // CHECK-NEXT:    [[TMP2352:%.*]] = load i32, ptr [[UIE]], align 4
19957 // CHECK-NEXT:    [[TMP2353:%.*]] = load i32, ptr [[UID]], align 4
19958 // CHECK-NEXT:    [[TMP2354:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2352]], i32 [[TMP2353]] monotonic monotonic, align 4
19959 // CHECK-NEXT:    [[TMP2355:%.*]] = extractvalue { i32, i1 } [[TMP2354]], 0
19960 // CHECK-NEXT:    store i32 [[TMP2355]], ptr [[UIV]], align 4
19961 // CHECK-NEXT:    [[TMP2356:%.*]] = load i32, ptr [[UIE]], align 4
19962 // CHECK-NEXT:    [[TMP2357:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2356]] monotonic, align 4
19963 // CHECK-NEXT:    [[TMP2358:%.*]] = icmp ugt i32 [[TMP2357]], [[TMP2356]]
19964 // CHECK-NEXT:    [[TMP2359:%.*]] = select i1 [[TMP2358]], i32 [[TMP2356]], i32 [[TMP2357]]
19965 // CHECK-NEXT:    store i32 [[TMP2359]], ptr [[UIV]], align 4
19966 // CHECK-NEXT:    [[TMP2360:%.*]] = load i32, ptr [[UIE]], align 4
19967 // CHECK-NEXT:    [[TMP2361:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2360]] monotonic, align 4
19968 // CHECK-NEXT:    [[TMP2362:%.*]] = icmp ult i32 [[TMP2361]], [[TMP2360]]
19969 // CHECK-NEXT:    [[TMP2363:%.*]] = select i1 [[TMP2362]], i32 [[TMP2360]], i32 [[TMP2361]]
19970 // CHECK-NEXT:    store i32 [[TMP2363]], ptr [[UIV]], align 4
19971 // CHECK-NEXT:    [[TMP2364:%.*]] = load i32, ptr [[UIE]], align 4
19972 // CHECK-NEXT:    [[TMP2365:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2364]] monotonic, align 4
19973 // CHECK-NEXT:    [[TMP2366:%.*]] = icmp ult i32 [[TMP2365]], [[TMP2364]]
19974 // CHECK-NEXT:    [[TMP2367:%.*]] = select i1 [[TMP2366]], i32 [[TMP2364]], i32 [[TMP2365]]
19975 // CHECK-NEXT:    store i32 [[TMP2367]], ptr [[UIV]], align 4
19976 // CHECK-NEXT:    [[TMP2368:%.*]] = load i32, ptr [[UIE]], align 4
19977 // CHECK-NEXT:    [[TMP2369:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2368]] monotonic, align 4
19978 // CHECK-NEXT:    [[TMP2370:%.*]] = icmp ugt i32 [[TMP2369]], [[TMP2368]]
19979 // CHECK-NEXT:    [[TMP2371:%.*]] = select i1 [[TMP2370]], i32 [[TMP2368]], i32 [[TMP2369]]
19980 // CHECK-NEXT:    store i32 [[TMP2371]], ptr [[UIV]], align 4
19981 // CHECK-NEXT:    [[TMP2372:%.*]] = load i32, ptr [[UIE]], align 4
19982 // CHECK-NEXT:    [[TMP2373:%.*]] = load i32, ptr [[UID]], align 4
19983 // CHECK-NEXT:    [[TMP2374:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2372]], i32 [[TMP2373]] monotonic monotonic, align 4
19984 // CHECK-NEXT:    [[TMP2375:%.*]] = extractvalue { i32, i1 } [[TMP2374]], 0
19985 // CHECK-NEXT:    [[TMP2376:%.*]] = extractvalue { i32, i1 } [[TMP2374]], 1
19986 // CHECK-NEXT:    [[TMP2377:%.*]] = select i1 [[TMP2376]], i32 [[TMP2372]], i32 [[TMP2375]]
19987 // CHECK-NEXT:    store i32 [[TMP2377]], ptr [[UIV]], align 4
19988 // CHECK-NEXT:    [[TMP2378:%.*]] = load i32, ptr [[UIE]], align 4
19989 // CHECK-NEXT:    [[TMP2379:%.*]] = load i32, ptr [[UID]], align 4
19990 // CHECK-NEXT:    [[TMP2380:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2378]], i32 [[TMP2379]] monotonic monotonic, align 4
19991 // CHECK-NEXT:    [[TMP2381:%.*]] = extractvalue { i32, i1 } [[TMP2380]], 0
19992 // CHECK-NEXT:    [[TMP2382:%.*]] = extractvalue { i32, i1 } [[TMP2380]], 1
19993 // CHECK-NEXT:    [[TMP2383:%.*]] = select i1 [[TMP2382]], i32 [[TMP2378]], i32 [[TMP2381]]
19994 // CHECK-NEXT:    store i32 [[TMP2383]], ptr [[UIV]], align 4
19995 // CHECK-NEXT:    [[TMP2384:%.*]] = load i32, ptr [[UIE]], align 4
19996 // CHECK-NEXT:    [[TMP2385:%.*]] = load i32, ptr [[UID]], align 4
19997 // CHECK-NEXT:    [[TMP2386:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2384]], i32 [[TMP2385]] monotonic monotonic, align 4
19998 // CHECK-NEXT:    [[TMP2387:%.*]] = extractvalue { i32, i1 } [[TMP2386]], 0
19999 // CHECK-NEXT:    [[TMP2388:%.*]] = extractvalue { i32, i1 } [[TMP2386]], 1
20000 // CHECK-NEXT:    br i1 [[TMP2388]], label [[UIX_ATOMIC_EXIT:%.*]], label [[UIX_ATOMIC_CONT:%.*]]
20001 // CHECK:       uix.atomic.cont:
20002 // CHECK-NEXT:    store i32 [[TMP2387]], ptr [[UIV]], align 4
20003 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT]]
20004 // CHECK:       uix.atomic.exit:
20005 // CHECK-NEXT:    [[TMP2389:%.*]] = load i32, ptr [[UIE]], align 4
20006 // CHECK-NEXT:    [[TMP2390:%.*]] = load i32, ptr [[UID]], align 4
20007 // CHECK-NEXT:    [[TMP2391:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2389]], i32 [[TMP2390]] monotonic monotonic, align 4
20008 // CHECK-NEXT:    [[TMP2392:%.*]] = extractvalue { i32, i1 } [[TMP2391]], 0
20009 // CHECK-NEXT:    [[TMP2393:%.*]] = extractvalue { i32, i1 } [[TMP2391]], 1
20010 // CHECK-NEXT:    br i1 [[TMP2393]], label [[UIX_ATOMIC_EXIT231:%.*]], label [[UIX_ATOMIC_CONT232:%.*]]
20011 // CHECK:       uix.atomic.cont232:
20012 // CHECK-NEXT:    store i32 [[TMP2392]], ptr [[UIV]], align 4
20013 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT231]]
20014 // CHECK:       uix.atomic.exit231:
20015 // CHECK-NEXT:    [[TMP2394:%.*]] = load i32, ptr [[UIE]], align 4
20016 // CHECK-NEXT:    [[TMP2395:%.*]] = load i32, ptr [[UID]], align 4
20017 // CHECK-NEXT:    [[TMP2396:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2394]], i32 [[TMP2395]] monotonic monotonic, align 4
20018 // CHECK-NEXT:    [[TMP2397:%.*]] = extractvalue { i32, i1 } [[TMP2396]], 1
20019 // CHECK-NEXT:    [[TMP2398:%.*]] = zext i1 [[TMP2397]] to i32
20020 // CHECK-NEXT:    store i32 [[TMP2398]], ptr [[UIR]], align 4
20021 // CHECK-NEXT:    [[TMP2399:%.*]] = load i32, ptr [[UIE]], align 4
20022 // CHECK-NEXT:    [[TMP2400:%.*]] = load i32, ptr [[UID]], align 4
20023 // CHECK-NEXT:    [[TMP2401:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2399]], i32 [[TMP2400]] monotonic monotonic, align 4
20024 // CHECK-NEXT:    [[TMP2402:%.*]] = extractvalue { i32, i1 } [[TMP2401]], 1
20025 // CHECK-NEXT:    [[TMP2403:%.*]] = zext i1 [[TMP2402]] to i32
20026 // CHECK-NEXT:    store i32 [[TMP2403]], ptr [[UIR]], align 4
20027 // CHECK-NEXT:    [[TMP2404:%.*]] = load i32, ptr [[UIE]], align 4
20028 // CHECK-NEXT:    [[TMP2405:%.*]] = load i32, ptr [[UID]], align 4
20029 // CHECK-NEXT:    [[TMP2406:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2404]], i32 [[TMP2405]] monotonic monotonic, align 4
20030 // CHECK-NEXT:    [[TMP2407:%.*]] = extractvalue { i32, i1 } [[TMP2406]], 0
20031 // CHECK-NEXT:    [[TMP2408:%.*]] = extractvalue { i32, i1 } [[TMP2406]], 1
20032 // CHECK-NEXT:    br i1 [[TMP2408]], label [[UIX_ATOMIC_EXIT233:%.*]], label [[UIX_ATOMIC_CONT234:%.*]]
20033 // CHECK:       uix.atomic.cont234:
20034 // CHECK-NEXT:    store i32 [[TMP2407]], ptr [[UIV]], align 4
20035 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT233]]
20036 // CHECK:       uix.atomic.exit233:
20037 // CHECK-NEXT:    [[TMP2409:%.*]] = extractvalue { i32, i1 } [[TMP2406]], 1
20038 // CHECK-NEXT:    [[TMP2410:%.*]] = zext i1 [[TMP2409]] to i32
20039 // CHECK-NEXT:    store i32 [[TMP2410]], ptr [[UIR]], align 4
20040 // CHECK-NEXT:    [[TMP2411:%.*]] = load i32, ptr [[UIE]], align 4
20041 // CHECK-NEXT:    [[TMP2412:%.*]] = load i32, ptr [[UID]], align 4
20042 // CHECK-NEXT:    [[TMP2413:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2411]], i32 [[TMP2412]] monotonic monotonic, align 4
20043 // CHECK-NEXT:    [[TMP2414:%.*]] = extractvalue { i32, i1 } [[TMP2413]], 0
20044 // CHECK-NEXT:    [[TMP2415:%.*]] = extractvalue { i32, i1 } [[TMP2413]], 1
20045 // CHECK-NEXT:    br i1 [[TMP2415]], label [[UIX_ATOMIC_EXIT235:%.*]], label [[UIX_ATOMIC_CONT236:%.*]]
20046 // CHECK:       uix.atomic.cont236:
20047 // CHECK-NEXT:    store i32 [[TMP2414]], ptr [[UIV]], align 4
20048 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT235]]
20049 // CHECK:       uix.atomic.exit235:
20050 // CHECK-NEXT:    [[TMP2416:%.*]] = extractvalue { i32, i1 } [[TMP2413]], 1
20051 // CHECK-NEXT:    [[TMP2417:%.*]] = zext i1 [[TMP2416]] to i32
20052 // CHECK-NEXT:    store i32 [[TMP2417]], ptr [[UIR]], align 4
20053 // CHECK-NEXT:    [[TMP2418:%.*]] = load i32, ptr [[UIE]], align 4
20054 // CHECK-NEXT:    [[TMP2419:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2418]] acq_rel, align 4
20055 // CHECK-NEXT:    store i32 [[TMP2419]], ptr [[UIV]], align 4
20056 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20057 // CHECK-NEXT:    [[TMP2420:%.*]] = load i32, ptr [[UIE]], align 4
20058 // CHECK-NEXT:    [[TMP2421:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2420]] acq_rel, align 4
20059 // CHECK-NEXT:    store i32 [[TMP2421]], ptr [[UIV]], align 4
20060 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20061 // CHECK-NEXT:    [[TMP2422:%.*]] = load i32, ptr [[UIE]], align 4
20062 // CHECK-NEXT:    [[TMP2423:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2422]] acq_rel, align 4
20063 // CHECK-NEXT:    store i32 [[TMP2423]], ptr [[UIV]], align 4
20064 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20065 // CHECK-NEXT:    [[TMP2424:%.*]] = load i32, ptr [[UIE]], align 4
20066 // CHECK-NEXT:    [[TMP2425:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2424]] acq_rel, align 4
20067 // CHECK-NEXT:    store i32 [[TMP2425]], ptr [[UIV]], align 4
20068 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20069 // CHECK-NEXT:    [[TMP2426:%.*]] = load i32, ptr [[UIE]], align 4
20070 // CHECK-NEXT:    [[TMP2427:%.*]] = load i32, ptr [[UID]], align 4
20071 // CHECK-NEXT:    [[TMP2428:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2426]], i32 [[TMP2427]] acq_rel acquire, align 4
20072 // CHECK-NEXT:    [[TMP2429:%.*]] = extractvalue { i32, i1 } [[TMP2428]], 0
20073 // CHECK-NEXT:    store i32 [[TMP2429]], ptr [[UIV]], align 4
20074 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20075 // CHECK-NEXT:    [[TMP2430:%.*]] = load i32, ptr [[UIE]], align 4
20076 // CHECK-NEXT:    [[TMP2431:%.*]] = load i32, ptr [[UID]], align 4
20077 // CHECK-NEXT:    [[TMP2432:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2430]], i32 [[TMP2431]] acq_rel acquire, align 4
20078 // CHECK-NEXT:    [[TMP2433:%.*]] = extractvalue { i32, i1 } [[TMP2432]], 0
20079 // CHECK-NEXT:    store i32 [[TMP2433]], ptr [[UIV]], align 4
20080 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20081 // CHECK-NEXT:    [[TMP2434:%.*]] = load i32, ptr [[UIE]], align 4
20082 // CHECK-NEXT:    [[TMP2435:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2434]] acq_rel, align 4
20083 // CHECK-NEXT:    [[TMP2436:%.*]] = icmp ugt i32 [[TMP2435]], [[TMP2434]]
20084 // CHECK-NEXT:    [[TMP2437:%.*]] = select i1 [[TMP2436]], i32 [[TMP2434]], i32 [[TMP2435]]
20085 // CHECK-NEXT:    store i32 [[TMP2437]], ptr [[UIV]], align 4
20086 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20087 // CHECK-NEXT:    [[TMP2438:%.*]] = load i32, ptr [[UIE]], align 4
20088 // CHECK-NEXT:    [[TMP2439:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2438]] acq_rel, align 4
20089 // CHECK-NEXT:    [[TMP2440:%.*]] = icmp ult i32 [[TMP2439]], [[TMP2438]]
20090 // CHECK-NEXT:    [[TMP2441:%.*]] = select i1 [[TMP2440]], i32 [[TMP2438]], i32 [[TMP2439]]
20091 // CHECK-NEXT:    store i32 [[TMP2441]], ptr [[UIV]], align 4
20092 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20093 // CHECK-NEXT:    [[TMP2442:%.*]] = load i32, ptr [[UIE]], align 4
20094 // CHECK-NEXT:    [[TMP2443:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2442]] acq_rel, align 4
20095 // CHECK-NEXT:    [[TMP2444:%.*]] = icmp ult i32 [[TMP2443]], [[TMP2442]]
20096 // CHECK-NEXT:    [[TMP2445:%.*]] = select i1 [[TMP2444]], i32 [[TMP2442]], i32 [[TMP2443]]
20097 // CHECK-NEXT:    store i32 [[TMP2445]], ptr [[UIV]], align 4
20098 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20099 // CHECK-NEXT:    [[TMP2446:%.*]] = load i32, ptr [[UIE]], align 4
20100 // CHECK-NEXT:    [[TMP2447:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2446]] acq_rel, align 4
20101 // CHECK-NEXT:    [[TMP2448:%.*]] = icmp ugt i32 [[TMP2447]], [[TMP2446]]
20102 // CHECK-NEXT:    [[TMP2449:%.*]] = select i1 [[TMP2448]], i32 [[TMP2446]], i32 [[TMP2447]]
20103 // CHECK-NEXT:    store i32 [[TMP2449]], ptr [[UIV]], align 4
20104 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20105 // CHECK-NEXT:    [[TMP2450:%.*]] = load i32, ptr [[UIE]], align 4
20106 // CHECK-NEXT:    [[TMP2451:%.*]] = load i32, ptr [[UID]], align 4
20107 // CHECK-NEXT:    [[TMP2452:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2450]], i32 [[TMP2451]] acq_rel acquire, align 4
20108 // CHECK-NEXT:    [[TMP2453:%.*]] = extractvalue { i32, i1 } [[TMP2452]], 0
20109 // CHECK-NEXT:    [[TMP2454:%.*]] = extractvalue { i32, i1 } [[TMP2452]], 1
20110 // CHECK-NEXT:    [[TMP2455:%.*]] = select i1 [[TMP2454]], i32 [[TMP2450]], i32 [[TMP2453]]
20111 // CHECK-NEXT:    store i32 [[TMP2455]], ptr [[UIV]], align 4
20112 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20113 // CHECK-NEXT:    [[TMP2456:%.*]] = load i32, ptr [[UIE]], align 4
20114 // CHECK-NEXT:    [[TMP2457:%.*]] = load i32, ptr [[UID]], align 4
20115 // CHECK-NEXT:    [[TMP2458:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2456]], i32 [[TMP2457]] acq_rel acquire, align 4
20116 // CHECK-NEXT:    [[TMP2459:%.*]] = extractvalue { i32, i1 } [[TMP2458]], 0
20117 // CHECK-NEXT:    [[TMP2460:%.*]] = extractvalue { i32, i1 } [[TMP2458]], 1
20118 // CHECK-NEXT:    [[TMP2461:%.*]] = select i1 [[TMP2460]], i32 [[TMP2456]], i32 [[TMP2459]]
20119 // CHECK-NEXT:    store i32 [[TMP2461]], ptr [[UIV]], align 4
20120 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20121 // CHECK-NEXT:    [[TMP2462:%.*]] = load i32, ptr [[UIE]], align 4
20122 // CHECK-NEXT:    [[TMP2463:%.*]] = load i32, ptr [[UID]], align 4
20123 // CHECK-NEXT:    [[TMP2464:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2462]], i32 [[TMP2463]] acq_rel acquire, align 4
20124 // CHECK-NEXT:    [[TMP2465:%.*]] = extractvalue { i32, i1 } [[TMP2464]], 0
20125 // CHECK-NEXT:    [[TMP2466:%.*]] = extractvalue { i32, i1 } [[TMP2464]], 1
20126 // CHECK-NEXT:    br i1 [[TMP2466]], label [[UIX_ATOMIC_EXIT237:%.*]], label [[UIX_ATOMIC_CONT238:%.*]]
20127 // CHECK:       uix.atomic.cont238:
20128 // CHECK-NEXT:    store i32 [[TMP2465]], ptr [[UIV]], align 4
20129 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT237]]
20130 // CHECK:       uix.atomic.exit237:
20131 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20132 // CHECK-NEXT:    [[TMP2467:%.*]] = load i32, ptr [[UIE]], align 4
20133 // CHECK-NEXT:    [[TMP2468:%.*]] = load i32, ptr [[UID]], align 4
20134 // CHECK-NEXT:    [[TMP2469:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2467]], i32 [[TMP2468]] acq_rel acquire, align 4
20135 // CHECK-NEXT:    [[TMP2470:%.*]] = extractvalue { i32, i1 } [[TMP2469]], 0
20136 // CHECK-NEXT:    [[TMP2471:%.*]] = extractvalue { i32, i1 } [[TMP2469]], 1
20137 // CHECK-NEXT:    br i1 [[TMP2471]], label [[UIX_ATOMIC_EXIT239:%.*]], label [[UIX_ATOMIC_CONT240:%.*]]
20138 // CHECK:       uix.atomic.cont240:
20139 // CHECK-NEXT:    store i32 [[TMP2470]], ptr [[UIV]], align 4
20140 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT239]]
20141 // CHECK:       uix.atomic.exit239:
20142 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20143 // CHECK-NEXT:    [[TMP2472:%.*]] = load i32, ptr [[UIE]], align 4
20144 // CHECK-NEXT:    [[TMP2473:%.*]] = load i32, ptr [[UID]], align 4
20145 // CHECK-NEXT:    [[TMP2474:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2472]], i32 [[TMP2473]] acq_rel acquire, align 4
20146 // CHECK-NEXT:    [[TMP2475:%.*]] = extractvalue { i32, i1 } [[TMP2474]], 1
20147 // CHECK-NEXT:    [[TMP2476:%.*]] = zext i1 [[TMP2475]] to i32
20148 // CHECK-NEXT:    store i32 [[TMP2476]], ptr [[UIR]], align 4
20149 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20150 // CHECK-NEXT:    [[TMP2477:%.*]] = load i32, ptr [[UIE]], align 4
20151 // CHECK-NEXT:    [[TMP2478:%.*]] = load i32, ptr [[UID]], align 4
20152 // CHECK-NEXT:    [[TMP2479:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2477]], i32 [[TMP2478]] acq_rel acquire, align 4
20153 // CHECK-NEXT:    [[TMP2480:%.*]] = extractvalue { i32, i1 } [[TMP2479]], 1
20154 // CHECK-NEXT:    [[TMP2481:%.*]] = zext i1 [[TMP2480]] to i32
20155 // CHECK-NEXT:    store i32 [[TMP2481]], ptr [[UIR]], align 4
20156 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20157 // CHECK-NEXT:    [[TMP2482:%.*]] = load i32, ptr [[UIE]], align 4
20158 // CHECK-NEXT:    [[TMP2483:%.*]] = load i32, ptr [[UID]], align 4
20159 // CHECK-NEXT:    [[TMP2484:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2482]], i32 [[TMP2483]] acq_rel acquire, align 4
20160 // CHECK-NEXT:    [[TMP2485:%.*]] = extractvalue { i32, i1 } [[TMP2484]], 0
20161 // CHECK-NEXT:    [[TMP2486:%.*]] = extractvalue { i32, i1 } [[TMP2484]], 1
20162 // CHECK-NEXT:    br i1 [[TMP2486]], label [[UIX_ATOMIC_EXIT241:%.*]], label [[UIX_ATOMIC_CONT242:%.*]]
20163 // CHECK:       uix.atomic.cont242:
20164 // CHECK-NEXT:    store i32 [[TMP2485]], ptr [[UIV]], align 4
20165 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT241]]
20166 // CHECK:       uix.atomic.exit241:
20167 // CHECK-NEXT:    [[TMP2487:%.*]] = extractvalue { i32, i1 } [[TMP2484]], 1
20168 // CHECK-NEXT:    [[TMP2488:%.*]] = zext i1 [[TMP2487]] to i32
20169 // CHECK-NEXT:    store i32 [[TMP2488]], ptr [[UIR]], align 4
20170 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20171 // CHECK-NEXT:    [[TMP2489:%.*]] = load i32, ptr [[UIE]], align 4
20172 // CHECK-NEXT:    [[TMP2490:%.*]] = load i32, ptr [[UID]], align 4
20173 // CHECK-NEXT:    [[TMP2491:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2489]], i32 [[TMP2490]] acq_rel acquire, align 4
20174 // CHECK-NEXT:    [[TMP2492:%.*]] = extractvalue { i32, i1 } [[TMP2491]], 0
20175 // CHECK-NEXT:    [[TMP2493:%.*]] = extractvalue { i32, i1 } [[TMP2491]], 1
20176 // CHECK-NEXT:    br i1 [[TMP2493]], label [[UIX_ATOMIC_EXIT243:%.*]], label [[UIX_ATOMIC_CONT244:%.*]]
20177 // CHECK:       uix.atomic.cont244:
20178 // CHECK-NEXT:    store i32 [[TMP2492]], ptr [[UIV]], align 4
20179 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT243]]
20180 // CHECK:       uix.atomic.exit243:
20181 // CHECK-NEXT:    [[TMP2494:%.*]] = extractvalue { i32, i1 } [[TMP2491]], 1
20182 // CHECK-NEXT:    [[TMP2495:%.*]] = zext i1 [[TMP2494]] to i32
20183 // CHECK-NEXT:    store i32 [[TMP2495]], ptr [[UIR]], align 4
20184 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20185 // CHECK-NEXT:    [[TMP2496:%.*]] = load i32, ptr [[UIE]], align 4
20186 // CHECK-NEXT:    [[TMP2497:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2496]] acquire, align 4
20187 // CHECK-NEXT:    store i32 [[TMP2497]], ptr [[UIV]], align 4
20188 // CHECK-NEXT:    [[TMP2498:%.*]] = load i32, ptr [[UIE]], align 4
20189 // CHECK-NEXT:    [[TMP2499:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2498]] acquire, align 4
20190 // CHECK-NEXT:    store i32 [[TMP2499]], ptr [[UIV]], align 4
20191 // CHECK-NEXT:    [[TMP2500:%.*]] = load i32, ptr [[UIE]], align 4
20192 // CHECK-NEXT:    [[TMP2501:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2500]] acquire, align 4
20193 // CHECK-NEXT:    store i32 [[TMP2501]], ptr [[UIV]], align 4
20194 // CHECK-NEXT:    [[TMP2502:%.*]] = load i32, ptr [[UIE]], align 4
20195 // CHECK-NEXT:    [[TMP2503:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2502]] acquire, align 4
20196 // CHECK-NEXT:    store i32 [[TMP2503]], ptr [[UIV]], align 4
20197 // CHECK-NEXT:    [[TMP2504:%.*]] = load i32, ptr [[UIE]], align 4
20198 // CHECK-NEXT:    [[TMP2505:%.*]] = load i32, ptr [[UID]], align 4
20199 // CHECK-NEXT:    [[TMP2506:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2504]], i32 [[TMP2505]] acquire acquire, align 4
20200 // CHECK-NEXT:    [[TMP2507:%.*]] = extractvalue { i32, i1 } [[TMP2506]], 0
20201 // CHECK-NEXT:    store i32 [[TMP2507]], ptr [[UIV]], align 4
20202 // CHECK-NEXT:    [[TMP2508:%.*]] = load i32, ptr [[UIE]], align 4
20203 // CHECK-NEXT:    [[TMP2509:%.*]] = load i32, ptr [[UID]], align 4
20204 // CHECK-NEXT:    [[TMP2510:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2508]], i32 [[TMP2509]] acquire acquire, align 4
20205 // CHECK-NEXT:    [[TMP2511:%.*]] = extractvalue { i32, i1 } [[TMP2510]], 0
20206 // CHECK-NEXT:    store i32 [[TMP2511]], ptr [[UIV]], align 4
20207 // CHECK-NEXT:    [[TMP2512:%.*]] = load i32, ptr [[UIE]], align 4
20208 // CHECK-NEXT:    [[TMP2513:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2512]] acquire, align 4
20209 // CHECK-NEXT:    [[TMP2514:%.*]] = icmp ugt i32 [[TMP2513]], [[TMP2512]]
20210 // CHECK-NEXT:    [[TMP2515:%.*]] = select i1 [[TMP2514]], i32 [[TMP2512]], i32 [[TMP2513]]
20211 // CHECK-NEXT:    store i32 [[TMP2515]], ptr [[UIV]], align 4
20212 // CHECK-NEXT:    [[TMP2516:%.*]] = load i32, ptr [[UIE]], align 4
20213 // CHECK-NEXT:    [[TMP2517:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2516]] acquire, align 4
20214 // CHECK-NEXT:    [[TMP2518:%.*]] = icmp ult i32 [[TMP2517]], [[TMP2516]]
20215 // CHECK-NEXT:    [[TMP2519:%.*]] = select i1 [[TMP2518]], i32 [[TMP2516]], i32 [[TMP2517]]
20216 // CHECK-NEXT:    store i32 [[TMP2519]], ptr [[UIV]], align 4
20217 // CHECK-NEXT:    [[TMP2520:%.*]] = load i32, ptr [[UIE]], align 4
20218 // CHECK-NEXT:    [[TMP2521:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2520]] acquire, align 4
20219 // CHECK-NEXT:    [[TMP2522:%.*]] = icmp ult i32 [[TMP2521]], [[TMP2520]]
20220 // CHECK-NEXT:    [[TMP2523:%.*]] = select i1 [[TMP2522]], i32 [[TMP2520]], i32 [[TMP2521]]
20221 // CHECK-NEXT:    store i32 [[TMP2523]], ptr [[UIV]], align 4
20222 // CHECK-NEXT:    [[TMP2524:%.*]] = load i32, ptr [[UIE]], align 4
20223 // CHECK-NEXT:    [[TMP2525:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2524]] acquire, align 4
20224 // CHECK-NEXT:    [[TMP2526:%.*]] = icmp ugt i32 [[TMP2525]], [[TMP2524]]
20225 // CHECK-NEXT:    [[TMP2527:%.*]] = select i1 [[TMP2526]], i32 [[TMP2524]], i32 [[TMP2525]]
20226 // CHECK-NEXT:    store i32 [[TMP2527]], ptr [[UIV]], align 4
20227 // CHECK-NEXT:    [[TMP2528:%.*]] = load i32, ptr [[UIE]], align 4
20228 // CHECK-NEXT:    [[TMP2529:%.*]] = load i32, ptr [[UID]], align 4
20229 // CHECK-NEXT:    [[TMP2530:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2528]], i32 [[TMP2529]] acquire acquire, align 4
20230 // CHECK-NEXT:    [[TMP2531:%.*]] = extractvalue { i32, i1 } [[TMP2530]], 0
20231 // CHECK-NEXT:    [[TMP2532:%.*]] = extractvalue { i32, i1 } [[TMP2530]], 1
20232 // CHECK-NEXT:    [[TMP2533:%.*]] = select i1 [[TMP2532]], i32 [[TMP2528]], i32 [[TMP2531]]
20233 // CHECK-NEXT:    store i32 [[TMP2533]], ptr [[UIV]], align 4
20234 // CHECK-NEXT:    [[TMP2534:%.*]] = load i32, ptr [[UIE]], align 4
20235 // CHECK-NEXT:    [[TMP2535:%.*]] = load i32, ptr [[UID]], align 4
20236 // CHECK-NEXT:    [[TMP2536:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2534]], i32 [[TMP2535]] acquire acquire, align 4
20237 // CHECK-NEXT:    [[TMP2537:%.*]] = extractvalue { i32, i1 } [[TMP2536]], 0
20238 // CHECK-NEXT:    [[TMP2538:%.*]] = extractvalue { i32, i1 } [[TMP2536]], 1
20239 // CHECK-NEXT:    [[TMP2539:%.*]] = select i1 [[TMP2538]], i32 [[TMP2534]], i32 [[TMP2537]]
20240 // CHECK-NEXT:    store i32 [[TMP2539]], ptr [[UIV]], align 4
20241 // CHECK-NEXT:    [[TMP2540:%.*]] = load i32, ptr [[UIE]], align 4
20242 // CHECK-NEXT:    [[TMP2541:%.*]] = load i32, ptr [[UID]], align 4
20243 // CHECK-NEXT:    [[TMP2542:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2540]], i32 [[TMP2541]] acquire acquire, align 4
20244 // CHECK-NEXT:    [[TMP2543:%.*]] = extractvalue { i32, i1 } [[TMP2542]], 0
20245 // CHECK-NEXT:    [[TMP2544:%.*]] = extractvalue { i32, i1 } [[TMP2542]], 1
20246 // CHECK-NEXT:    br i1 [[TMP2544]], label [[UIX_ATOMIC_EXIT245:%.*]], label [[UIX_ATOMIC_CONT246:%.*]]
20247 // CHECK:       uix.atomic.cont246:
20248 // CHECK-NEXT:    store i32 [[TMP2543]], ptr [[UIV]], align 4
20249 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT245]]
20250 // CHECK:       uix.atomic.exit245:
20251 // CHECK-NEXT:    [[TMP2545:%.*]] = load i32, ptr [[UIE]], align 4
20252 // CHECK-NEXT:    [[TMP2546:%.*]] = load i32, ptr [[UID]], align 4
20253 // CHECK-NEXT:    [[TMP2547:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2545]], i32 [[TMP2546]] acquire acquire, align 4
20254 // CHECK-NEXT:    [[TMP2548:%.*]] = extractvalue { i32, i1 } [[TMP2547]], 0
20255 // CHECK-NEXT:    [[TMP2549:%.*]] = extractvalue { i32, i1 } [[TMP2547]], 1
20256 // CHECK-NEXT:    br i1 [[TMP2549]], label [[UIX_ATOMIC_EXIT247:%.*]], label [[UIX_ATOMIC_CONT248:%.*]]
20257 // CHECK:       uix.atomic.cont248:
20258 // CHECK-NEXT:    store i32 [[TMP2548]], ptr [[UIV]], align 4
20259 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT247]]
20260 // CHECK:       uix.atomic.exit247:
20261 // CHECK-NEXT:    [[TMP2550:%.*]] = load i32, ptr [[UIE]], align 4
20262 // CHECK-NEXT:    [[TMP2551:%.*]] = load i32, ptr [[UID]], align 4
20263 // CHECK-NEXT:    [[TMP2552:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2550]], i32 [[TMP2551]] acquire acquire, align 4
20264 // CHECK-NEXT:    [[TMP2553:%.*]] = extractvalue { i32, i1 } [[TMP2552]], 1
20265 // CHECK-NEXT:    [[TMP2554:%.*]] = zext i1 [[TMP2553]] to i32
20266 // CHECK-NEXT:    store i32 [[TMP2554]], ptr [[UIR]], align 4
20267 // CHECK-NEXT:    [[TMP2555:%.*]] = load i32, ptr [[UIE]], align 4
20268 // CHECK-NEXT:    [[TMP2556:%.*]] = load i32, ptr [[UID]], align 4
20269 // CHECK-NEXT:    [[TMP2557:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2555]], i32 [[TMP2556]] acquire acquire, align 4
20270 // CHECK-NEXT:    [[TMP2558:%.*]] = extractvalue { i32, i1 } [[TMP2557]], 1
20271 // CHECK-NEXT:    [[TMP2559:%.*]] = zext i1 [[TMP2558]] to i32
20272 // CHECK-NEXT:    store i32 [[TMP2559]], ptr [[UIR]], align 4
20273 // CHECK-NEXT:    [[TMP2560:%.*]] = load i32, ptr [[UIE]], align 4
20274 // CHECK-NEXT:    [[TMP2561:%.*]] = load i32, ptr [[UID]], align 4
20275 // CHECK-NEXT:    [[TMP2562:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2560]], i32 [[TMP2561]] acquire acquire, align 4
20276 // CHECK-NEXT:    [[TMP2563:%.*]] = extractvalue { i32, i1 } [[TMP2562]], 0
20277 // CHECK-NEXT:    [[TMP2564:%.*]] = extractvalue { i32, i1 } [[TMP2562]], 1
20278 // CHECK-NEXT:    br i1 [[TMP2564]], label [[UIX_ATOMIC_EXIT249:%.*]], label [[UIX_ATOMIC_CONT250:%.*]]
20279 // CHECK:       uix.atomic.cont250:
20280 // CHECK-NEXT:    store i32 [[TMP2563]], ptr [[UIV]], align 4
20281 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT249]]
20282 // CHECK:       uix.atomic.exit249:
20283 // CHECK-NEXT:    [[TMP2565:%.*]] = extractvalue { i32, i1 } [[TMP2562]], 1
20284 // CHECK-NEXT:    [[TMP2566:%.*]] = zext i1 [[TMP2565]] to i32
20285 // CHECK-NEXT:    store i32 [[TMP2566]], ptr [[UIR]], align 4
20286 // CHECK-NEXT:    [[TMP2567:%.*]] = load i32, ptr [[UIE]], align 4
20287 // CHECK-NEXT:    [[TMP2568:%.*]] = load i32, ptr [[UID]], align 4
20288 // CHECK-NEXT:    [[TMP2569:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2567]], i32 [[TMP2568]] acquire acquire, align 4
20289 // CHECK-NEXT:    [[TMP2570:%.*]] = extractvalue { i32, i1 } [[TMP2569]], 0
20290 // CHECK-NEXT:    [[TMP2571:%.*]] = extractvalue { i32, i1 } [[TMP2569]], 1
20291 // CHECK-NEXT:    br i1 [[TMP2571]], label [[UIX_ATOMIC_EXIT251:%.*]], label [[UIX_ATOMIC_CONT252:%.*]]
20292 // CHECK:       uix.atomic.cont252:
20293 // CHECK-NEXT:    store i32 [[TMP2570]], ptr [[UIV]], align 4
20294 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT251]]
20295 // CHECK:       uix.atomic.exit251:
20296 // CHECK-NEXT:    [[TMP2572:%.*]] = extractvalue { i32, i1 } [[TMP2569]], 1
20297 // CHECK-NEXT:    [[TMP2573:%.*]] = zext i1 [[TMP2572]] to i32
20298 // CHECK-NEXT:    store i32 [[TMP2573]], ptr [[UIR]], align 4
20299 // CHECK-NEXT:    [[TMP2574:%.*]] = load i32, ptr [[UIE]], align 4
20300 // CHECK-NEXT:    [[TMP2575:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2574]] monotonic, align 4
20301 // CHECK-NEXT:    store i32 [[TMP2575]], ptr [[UIV]], align 4
20302 // CHECK-NEXT:    [[TMP2576:%.*]] = load i32, ptr [[UIE]], align 4
20303 // CHECK-NEXT:    [[TMP2577:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2576]] monotonic, align 4
20304 // CHECK-NEXT:    store i32 [[TMP2577]], ptr [[UIV]], align 4
20305 // CHECK-NEXT:    [[TMP2578:%.*]] = load i32, ptr [[UIE]], align 4
20306 // CHECK-NEXT:    [[TMP2579:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2578]] monotonic, align 4
20307 // CHECK-NEXT:    store i32 [[TMP2579]], ptr [[UIV]], align 4
20308 // CHECK-NEXT:    [[TMP2580:%.*]] = load i32, ptr [[UIE]], align 4
20309 // CHECK-NEXT:    [[TMP2581:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2580]] monotonic, align 4
20310 // CHECK-NEXT:    store i32 [[TMP2581]], ptr [[UIV]], align 4
20311 // CHECK-NEXT:    [[TMP2582:%.*]] = load i32, ptr [[UIE]], align 4
20312 // CHECK-NEXT:    [[TMP2583:%.*]] = load i32, ptr [[UID]], align 4
20313 // CHECK-NEXT:    [[TMP2584:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2582]], i32 [[TMP2583]] monotonic monotonic, align 4
20314 // CHECK-NEXT:    [[TMP2585:%.*]] = extractvalue { i32, i1 } [[TMP2584]], 0
20315 // CHECK-NEXT:    store i32 [[TMP2585]], ptr [[UIV]], align 4
20316 // CHECK-NEXT:    [[TMP2586:%.*]] = load i32, ptr [[UIE]], align 4
20317 // CHECK-NEXT:    [[TMP2587:%.*]] = load i32, ptr [[UID]], align 4
20318 // CHECK-NEXT:    [[TMP2588:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2586]], i32 [[TMP2587]] monotonic monotonic, align 4
20319 // CHECK-NEXT:    [[TMP2589:%.*]] = extractvalue { i32, i1 } [[TMP2588]], 0
20320 // CHECK-NEXT:    store i32 [[TMP2589]], ptr [[UIV]], align 4
20321 // CHECK-NEXT:    [[TMP2590:%.*]] = load i32, ptr [[UIE]], align 4
20322 // CHECK-NEXT:    [[TMP2591:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2590]] monotonic, align 4
20323 // CHECK-NEXT:    [[TMP2592:%.*]] = icmp ugt i32 [[TMP2591]], [[TMP2590]]
20324 // CHECK-NEXT:    [[TMP2593:%.*]] = select i1 [[TMP2592]], i32 [[TMP2590]], i32 [[TMP2591]]
20325 // CHECK-NEXT:    store i32 [[TMP2593]], ptr [[UIV]], align 4
20326 // CHECK-NEXT:    [[TMP2594:%.*]] = load i32, ptr [[UIE]], align 4
20327 // CHECK-NEXT:    [[TMP2595:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2594]] monotonic, align 4
20328 // CHECK-NEXT:    [[TMP2596:%.*]] = icmp ult i32 [[TMP2595]], [[TMP2594]]
20329 // CHECK-NEXT:    [[TMP2597:%.*]] = select i1 [[TMP2596]], i32 [[TMP2594]], i32 [[TMP2595]]
20330 // CHECK-NEXT:    store i32 [[TMP2597]], ptr [[UIV]], align 4
20331 // CHECK-NEXT:    [[TMP2598:%.*]] = load i32, ptr [[UIE]], align 4
20332 // CHECK-NEXT:    [[TMP2599:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2598]] monotonic, align 4
20333 // CHECK-NEXT:    [[TMP2600:%.*]] = icmp ult i32 [[TMP2599]], [[TMP2598]]
20334 // CHECK-NEXT:    [[TMP2601:%.*]] = select i1 [[TMP2600]], i32 [[TMP2598]], i32 [[TMP2599]]
20335 // CHECK-NEXT:    store i32 [[TMP2601]], ptr [[UIV]], align 4
20336 // CHECK-NEXT:    [[TMP2602:%.*]] = load i32, ptr [[UIE]], align 4
20337 // CHECK-NEXT:    [[TMP2603:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2602]] monotonic, align 4
20338 // CHECK-NEXT:    [[TMP2604:%.*]] = icmp ugt i32 [[TMP2603]], [[TMP2602]]
20339 // CHECK-NEXT:    [[TMP2605:%.*]] = select i1 [[TMP2604]], i32 [[TMP2602]], i32 [[TMP2603]]
20340 // CHECK-NEXT:    store i32 [[TMP2605]], ptr [[UIV]], align 4
20341 // CHECK-NEXT:    [[TMP2606:%.*]] = load i32, ptr [[UIE]], align 4
20342 // CHECK-NEXT:    [[TMP2607:%.*]] = load i32, ptr [[UID]], align 4
20343 // CHECK-NEXT:    [[TMP2608:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2606]], i32 [[TMP2607]] monotonic monotonic, align 4
20344 // CHECK-NEXT:    [[TMP2609:%.*]] = extractvalue { i32, i1 } [[TMP2608]], 0
20345 // CHECK-NEXT:    [[TMP2610:%.*]] = extractvalue { i32, i1 } [[TMP2608]], 1
20346 // CHECK-NEXT:    [[TMP2611:%.*]] = select i1 [[TMP2610]], i32 [[TMP2606]], i32 [[TMP2609]]
20347 // CHECK-NEXT:    store i32 [[TMP2611]], ptr [[UIV]], align 4
20348 // CHECK-NEXT:    [[TMP2612:%.*]] = load i32, ptr [[UIE]], align 4
20349 // CHECK-NEXT:    [[TMP2613:%.*]] = load i32, ptr [[UID]], align 4
20350 // CHECK-NEXT:    [[TMP2614:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2612]], i32 [[TMP2613]] monotonic monotonic, align 4
20351 // CHECK-NEXT:    [[TMP2615:%.*]] = extractvalue { i32, i1 } [[TMP2614]], 0
20352 // CHECK-NEXT:    [[TMP2616:%.*]] = extractvalue { i32, i1 } [[TMP2614]], 1
20353 // CHECK-NEXT:    [[TMP2617:%.*]] = select i1 [[TMP2616]], i32 [[TMP2612]], i32 [[TMP2615]]
20354 // CHECK-NEXT:    store i32 [[TMP2617]], ptr [[UIV]], align 4
20355 // CHECK-NEXT:    [[TMP2618:%.*]] = load i32, ptr [[UIE]], align 4
20356 // CHECK-NEXT:    [[TMP2619:%.*]] = load i32, ptr [[UID]], align 4
20357 // CHECK-NEXT:    [[TMP2620:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2618]], i32 [[TMP2619]] monotonic monotonic, align 4
20358 // CHECK-NEXT:    [[TMP2621:%.*]] = extractvalue { i32, i1 } [[TMP2620]], 0
20359 // CHECK-NEXT:    [[TMP2622:%.*]] = extractvalue { i32, i1 } [[TMP2620]], 1
20360 // CHECK-NEXT:    br i1 [[TMP2622]], label [[UIX_ATOMIC_EXIT253:%.*]], label [[UIX_ATOMIC_CONT254:%.*]]
20361 // CHECK:       uix.atomic.cont254:
20362 // CHECK-NEXT:    store i32 [[TMP2621]], ptr [[UIV]], align 4
20363 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT253]]
20364 // CHECK:       uix.atomic.exit253:
20365 // CHECK-NEXT:    [[TMP2623:%.*]] = load i32, ptr [[UIE]], align 4
20366 // CHECK-NEXT:    [[TMP2624:%.*]] = load i32, ptr [[UID]], align 4
20367 // CHECK-NEXT:    [[TMP2625:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2623]], i32 [[TMP2624]] monotonic monotonic, align 4
20368 // CHECK-NEXT:    [[TMP2626:%.*]] = extractvalue { i32, i1 } [[TMP2625]], 0
20369 // CHECK-NEXT:    [[TMP2627:%.*]] = extractvalue { i32, i1 } [[TMP2625]], 1
20370 // CHECK-NEXT:    br i1 [[TMP2627]], label [[UIX_ATOMIC_EXIT255:%.*]], label [[UIX_ATOMIC_CONT256:%.*]]
20371 // CHECK:       uix.atomic.cont256:
20372 // CHECK-NEXT:    store i32 [[TMP2626]], ptr [[UIV]], align 4
20373 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT255]]
20374 // CHECK:       uix.atomic.exit255:
20375 // CHECK-NEXT:    [[TMP2628:%.*]] = load i32, ptr [[UIE]], align 4
20376 // CHECK-NEXT:    [[TMP2629:%.*]] = load i32, ptr [[UID]], align 4
20377 // CHECK-NEXT:    [[TMP2630:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2628]], i32 [[TMP2629]] monotonic monotonic, align 4
20378 // CHECK-NEXT:    [[TMP2631:%.*]] = extractvalue { i32, i1 } [[TMP2630]], 1
20379 // CHECK-NEXT:    [[TMP2632:%.*]] = zext i1 [[TMP2631]] to i32
20380 // CHECK-NEXT:    store i32 [[TMP2632]], ptr [[UIR]], align 4
20381 // CHECK-NEXT:    [[TMP2633:%.*]] = load i32, ptr [[UIE]], align 4
20382 // CHECK-NEXT:    [[TMP2634:%.*]] = load i32, ptr [[UID]], align 4
20383 // CHECK-NEXT:    [[TMP2635:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2633]], i32 [[TMP2634]] monotonic monotonic, align 4
20384 // CHECK-NEXT:    [[TMP2636:%.*]] = extractvalue { i32, i1 } [[TMP2635]], 1
20385 // CHECK-NEXT:    [[TMP2637:%.*]] = zext i1 [[TMP2636]] to i32
20386 // CHECK-NEXT:    store i32 [[TMP2637]], ptr [[UIR]], align 4
20387 // CHECK-NEXT:    [[TMP2638:%.*]] = load i32, ptr [[UIE]], align 4
20388 // CHECK-NEXT:    [[TMP2639:%.*]] = load i32, ptr [[UID]], align 4
20389 // CHECK-NEXT:    [[TMP2640:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2638]], i32 [[TMP2639]] monotonic monotonic, align 4
20390 // CHECK-NEXT:    [[TMP2641:%.*]] = extractvalue { i32, i1 } [[TMP2640]], 0
20391 // CHECK-NEXT:    [[TMP2642:%.*]] = extractvalue { i32, i1 } [[TMP2640]], 1
20392 // CHECK-NEXT:    br i1 [[TMP2642]], label [[UIX_ATOMIC_EXIT257:%.*]], label [[UIX_ATOMIC_CONT258:%.*]]
20393 // CHECK:       uix.atomic.cont258:
20394 // CHECK-NEXT:    store i32 [[TMP2641]], ptr [[UIV]], align 4
20395 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT257]]
20396 // CHECK:       uix.atomic.exit257:
20397 // CHECK-NEXT:    [[TMP2643:%.*]] = extractvalue { i32, i1 } [[TMP2640]], 1
20398 // CHECK-NEXT:    [[TMP2644:%.*]] = zext i1 [[TMP2643]] to i32
20399 // CHECK-NEXT:    store i32 [[TMP2644]], ptr [[UIR]], align 4
20400 // CHECK-NEXT:    [[TMP2645:%.*]] = load i32, ptr [[UIE]], align 4
20401 // CHECK-NEXT:    [[TMP2646:%.*]] = load i32, ptr [[UID]], align 4
20402 // CHECK-NEXT:    [[TMP2647:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2645]], i32 [[TMP2646]] monotonic monotonic, align 4
20403 // CHECK-NEXT:    [[TMP2648:%.*]] = extractvalue { i32, i1 } [[TMP2647]], 0
20404 // CHECK-NEXT:    [[TMP2649:%.*]] = extractvalue { i32, i1 } [[TMP2647]], 1
20405 // CHECK-NEXT:    br i1 [[TMP2649]], label [[UIX_ATOMIC_EXIT259:%.*]], label [[UIX_ATOMIC_CONT260:%.*]]
20406 // CHECK:       uix.atomic.cont260:
20407 // CHECK-NEXT:    store i32 [[TMP2648]], ptr [[UIV]], align 4
20408 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT259]]
20409 // CHECK:       uix.atomic.exit259:
20410 // CHECK-NEXT:    [[TMP2650:%.*]] = extractvalue { i32, i1 } [[TMP2647]], 1
20411 // CHECK-NEXT:    [[TMP2651:%.*]] = zext i1 [[TMP2650]] to i32
20412 // CHECK-NEXT:    store i32 [[TMP2651]], ptr [[UIR]], align 4
20413 // CHECK-NEXT:    [[TMP2652:%.*]] = load i32, ptr [[UIE]], align 4
20414 // CHECK-NEXT:    [[TMP2653:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2652]] release, align 4
20415 // CHECK-NEXT:    store i32 [[TMP2653]], ptr [[UIV]], align 4
20416 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20417 // CHECK-NEXT:    [[TMP2654:%.*]] = load i32, ptr [[UIE]], align 4
20418 // CHECK-NEXT:    [[TMP2655:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2654]] release, align 4
20419 // CHECK-NEXT:    store i32 [[TMP2655]], ptr [[UIV]], align 4
20420 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20421 // CHECK-NEXT:    [[TMP2656:%.*]] = load i32, ptr [[UIE]], align 4
20422 // CHECK-NEXT:    [[TMP2657:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2656]] release, align 4
20423 // CHECK-NEXT:    store i32 [[TMP2657]], ptr [[UIV]], align 4
20424 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20425 // CHECK-NEXT:    [[TMP2658:%.*]] = load i32, ptr [[UIE]], align 4
20426 // CHECK-NEXT:    [[TMP2659:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2658]] release, align 4
20427 // CHECK-NEXT:    store i32 [[TMP2659]], ptr [[UIV]], align 4
20428 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20429 // CHECK-NEXT:    [[TMP2660:%.*]] = load i32, ptr [[UIE]], align 4
20430 // CHECK-NEXT:    [[TMP2661:%.*]] = load i32, ptr [[UID]], align 4
20431 // CHECK-NEXT:    [[TMP2662:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2660]], i32 [[TMP2661]] release monotonic, align 4
20432 // CHECK-NEXT:    [[TMP2663:%.*]] = extractvalue { i32, i1 } [[TMP2662]], 0
20433 // CHECK-NEXT:    store i32 [[TMP2663]], ptr [[UIV]], align 4
20434 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20435 // CHECK-NEXT:    [[TMP2664:%.*]] = load i32, ptr [[UIE]], align 4
20436 // CHECK-NEXT:    [[TMP2665:%.*]] = load i32, ptr [[UID]], align 4
20437 // CHECK-NEXT:    [[TMP2666:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2664]], i32 [[TMP2665]] release monotonic, align 4
20438 // CHECK-NEXT:    [[TMP2667:%.*]] = extractvalue { i32, i1 } [[TMP2666]], 0
20439 // CHECK-NEXT:    store i32 [[TMP2667]], ptr [[UIV]], align 4
20440 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20441 // CHECK-NEXT:    [[TMP2668:%.*]] = load i32, ptr [[UIE]], align 4
20442 // CHECK-NEXT:    [[TMP2669:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2668]] release, align 4
20443 // CHECK-NEXT:    [[TMP2670:%.*]] = icmp ugt i32 [[TMP2669]], [[TMP2668]]
20444 // CHECK-NEXT:    [[TMP2671:%.*]] = select i1 [[TMP2670]], i32 [[TMP2668]], i32 [[TMP2669]]
20445 // CHECK-NEXT:    store i32 [[TMP2671]], ptr [[UIV]], align 4
20446 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20447 // CHECK-NEXT:    [[TMP2672:%.*]] = load i32, ptr [[UIE]], align 4
20448 // CHECK-NEXT:    [[TMP2673:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2672]] release, align 4
20449 // CHECK-NEXT:    [[TMP2674:%.*]] = icmp ult i32 [[TMP2673]], [[TMP2672]]
20450 // CHECK-NEXT:    [[TMP2675:%.*]] = select i1 [[TMP2674]], i32 [[TMP2672]], i32 [[TMP2673]]
20451 // CHECK-NEXT:    store i32 [[TMP2675]], ptr [[UIV]], align 4
20452 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20453 // CHECK-NEXT:    [[TMP2676:%.*]] = load i32, ptr [[UIE]], align 4
20454 // CHECK-NEXT:    [[TMP2677:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2676]] release, align 4
20455 // CHECK-NEXT:    [[TMP2678:%.*]] = icmp ult i32 [[TMP2677]], [[TMP2676]]
20456 // CHECK-NEXT:    [[TMP2679:%.*]] = select i1 [[TMP2678]], i32 [[TMP2676]], i32 [[TMP2677]]
20457 // CHECK-NEXT:    store i32 [[TMP2679]], ptr [[UIV]], align 4
20458 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20459 // CHECK-NEXT:    [[TMP2680:%.*]] = load i32, ptr [[UIE]], align 4
20460 // CHECK-NEXT:    [[TMP2681:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2680]] release, align 4
20461 // CHECK-NEXT:    [[TMP2682:%.*]] = icmp ugt i32 [[TMP2681]], [[TMP2680]]
20462 // CHECK-NEXT:    [[TMP2683:%.*]] = select i1 [[TMP2682]], i32 [[TMP2680]], i32 [[TMP2681]]
20463 // CHECK-NEXT:    store i32 [[TMP2683]], ptr [[UIV]], align 4
20464 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20465 // CHECK-NEXT:    [[TMP2684:%.*]] = load i32, ptr [[UIE]], align 4
20466 // CHECK-NEXT:    [[TMP2685:%.*]] = load i32, ptr [[UID]], align 4
20467 // CHECK-NEXT:    [[TMP2686:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2684]], i32 [[TMP2685]] release monotonic, align 4
20468 // CHECK-NEXT:    [[TMP2687:%.*]] = extractvalue { i32, i1 } [[TMP2686]], 0
20469 // CHECK-NEXT:    [[TMP2688:%.*]] = extractvalue { i32, i1 } [[TMP2686]], 1
20470 // CHECK-NEXT:    [[TMP2689:%.*]] = select i1 [[TMP2688]], i32 [[TMP2684]], i32 [[TMP2687]]
20471 // CHECK-NEXT:    store i32 [[TMP2689]], ptr [[UIV]], align 4
20472 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20473 // CHECK-NEXT:    [[TMP2690:%.*]] = load i32, ptr [[UIE]], align 4
20474 // CHECK-NEXT:    [[TMP2691:%.*]] = load i32, ptr [[UID]], align 4
20475 // CHECK-NEXT:    [[TMP2692:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2690]], i32 [[TMP2691]] release monotonic, align 4
20476 // CHECK-NEXT:    [[TMP2693:%.*]] = extractvalue { i32, i1 } [[TMP2692]], 0
20477 // CHECK-NEXT:    [[TMP2694:%.*]] = extractvalue { i32, i1 } [[TMP2692]], 1
20478 // CHECK-NEXT:    [[TMP2695:%.*]] = select i1 [[TMP2694]], i32 [[TMP2690]], i32 [[TMP2693]]
20479 // CHECK-NEXT:    store i32 [[TMP2695]], ptr [[UIV]], align 4
20480 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20481 // CHECK-NEXT:    [[TMP2696:%.*]] = load i32, ptr [[UIE]], align 4
20482 // CHECK-NEXT:    [[TMP2697:%.*]] = load i32, ptr [[UID]], align 4
20483 // CHECK-NEXT:    [[TMP2698:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2696]], i32 [[TMP2697]] release monotonic, align 4
20484 // CHECK-NEXT:    [[TMP2699:%.*]] = extractvalue { i32, i1 } [[TMP2698]], 0
20485 // CHECK-NEXT:    [[TMP2700:%.*]] = extractvalue { i32, i1 } [[TMP2698]], 1
20486 // CHECK-NEXT:    br i1 [[TMP2700]], label [[UIX_ATOMIC_EXIT261:%.*]], label [[UIX_ATOMIC_CONT262:%.*]]
20487 // CHECK:       uix.atomic.cont262:
20488 // CHECK-NEXT:    store i32 [[TMP2699]], ptr [[UIV]], align 4
20489 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT261]]
20490 // CHECK:       uix.atomic.exit261:
20491 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20492 // CHECK-NEXT:    [[TMP2701:%.*]] = load i32, ptr [[UIE]], align 4
20493 // CHECK-NEXT:    [[TMP2702:%.*]] = load i32, ptr [[UID]], align 4
20494 // CHECK-NEXT:    [[TMP2703:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2701]], i32 [[TMP2702]] release monotonic, align 4
20495 // CHECK-NEXT:    [[TMP2704:%.*]] = extractvalue { i32, i1 } [[TMP2703]], 0
20496 // CHECK-NEXT:    [[TMP2705:%.*]] = extractvalue { i32, i1 } [[TMP2703]], 1
20497 // CHECK-NEXT:    br i1 [[TMP2705]], label [[UIX_ATOMIC_EXIT263:%.*]], label [[UIX_ATOMIC_CONT264:%.*]]
20498 // CHECK:       uix.atomic.cont264:
20499 // CHECK-NEXT:    store i32 [[TMP2704]], ptr [[UIV]], align 4
20500 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT263]]
20501 // CHECK:       uix.atomic.exit263:
20502 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20503 // CHECK-NEXT:    [[TMP2706:%.*]] = load i32, ptr [[UIE]], align 4
20504 // CHECK-NEXT:    [[TMP2707:%.*]] = load i32, ptr [[UID]], align 4
20505 // CHECK-NEXT:    [[TMP2708:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2706]], i32 [[TMP2707]] release monotonic, align 4
20506 // CHECK-NEXT:    [[TMP2709:%.*]] = extractvalue { i32, i1 } [[TMP2708]], 1
20507 // CHECK-NEXT:    [[TMP2710:%.*]] = zext i1 [[TMP2709]] to i32
20508 // CHECK-NEXT:    store i32 [[TMP2710]], ptr [[UIR]], align 4
20509 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20510 // CHECK-NEXT:    [[TMP2711:%.*]] = load i32, ptr [[UIE]], align 4
20511 // CHECK-NEXT:    [[TMP2712:%.*]] = load i32, ptr [[UID]], align 4
20512 // CHECK-NEXT:    [[TMP2713:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2711]], i32 [[TMP2712]] release monotonic, align 4
20513 // CHECK-NEXT:    [[TMP2714:%.*]] = extractvalue { i32, i1 } [[TMP2713]], 1
20514 // CHECK-NEXT:    [[TMP2715:%.*]] = zext i1 [[TMP2714]] to i32
20515 // CHECK-NEXT:    store i32 [[TMP2715]], ptr [[UIR]], align 4
20516 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20517 // CHECK-NEXT:    [[TMP2716:%.*]] = load i32, ptr [[UIE]], align 4
20518 // CHECK-NEXT:    [[TMP2717:%.*]] = load i32, ptr [[UID]], align 4
20519 // CHECK-NEXT:    [[TMP2718:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2716]], i32 [[TMP2717]] release monotonic, align 4
20520 // CHECK-NEXT:    [[TMP2719:%.*]] = extractvalue { i32, i1 } [[TMP2718]], 0
20521 // CHECK-NEXT:    [[TMP2720:%.*]] = extractvalue { i32, i1 } [[TMP2718]], 1
20522 // CHECK-NEXT:    br i1 [[TMP2720]], label [[UIX_ATOMIC_EXIT265:%.*]], label [[UIX_ATOMIC_CONT266:%.*]]
20523 // CHECK:       uix.atomic.cont266:
20524 // CHECK-NEXT:    store i32 [[TMP2719]], ptr [[UIV]], align 4
20525 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT265]]
20526 // CHECK:       uix.atomic.exit265:
20527 // CHECK-NEXT:    [[TMP2721:%.*]] = extractvalue { i32, i1 } [[TMP2718]], 1
20528 // CHECK-NEXT:    [[TMP2722:%.*]] = zext i1 [[TMP2721]] to i32
20529 // CHECK-NEXT:    store i32 [[TMP2722]], ptr [[UIR]], align 4
20530 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20531 // CHECK-NEXT:    [[TMP2723:%.*]] = load i32, ptr [[UIE]], align 4
20532 // CHECK-NEXT:    [[TMP2724:%.*]] = load i32, ptr [[UID]], align 4
20533 // CHECK-NEXT:    [[TMP2725:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2723]], i32 [[TMP2724]] release monotonic, align 4
20534 // CHECK-NEXT:    [[TMP2726:%.*]] = extractvalue { i32, i1 } [[TMP2725]], 0
20535 // CHECK-NEXT:    [[TMP2727:%.*]] = extractvalue { i32, i1 } [[TMP2725]], 1
20536 // CHECK-NEXT:    br i1 [[TMP2727]], label [[UIX_ATOMIC_EXIT267:%.*]], label [[UIX_ATOMIC_CONT268:%.*]]
20537 // CHECK:       uix.atomic.cont268:
20538 // CHECK-NEXT:    store i32 [[TMP2726]], ptr [[UIV]], align 4
20539 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT267]]
20540 // CHECK:       uix.atomic.exit267:
20541 // CHECK-NEXT:    [[TMP2728:%.*]] = extractvalue { i32, i1 } [[TMP2725]], 1
20542 // CHECK-NEXT:    [[TMP2729:%.*]] = zext i1 [[TMP2728]] to i32
20543 // CHECK-NEXT:    store i32 [[TMP2729]], ptr [[UIR]], align 4
20544 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20545 // CHECK-NEXT:    [[TMP2730:%.*]] = load i32, ptr [[UIE]], align 4
20546 // CHECK-NEXT:    [[TMP2731:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2730]] seq_cst, align 4
20547 // CHECK-NEXT:    store i32 [[TMP2731]], ptr [[UIV]], align 4
20548 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20549 // CHECK-NEXT:    [[TMP2732:%.*]] = load i32, ptr [[UIE]], align 4
20550 // CHECK-NEXT:    [[TMP2733:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2732]] seq_cst, align 4
20551 // CHECK-NEXT:    store i32 [[TMP2733]], ptr [[UIV]], align 4
20552 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20553 // CHECK-NEXT:    [[TMP2734:%.*]] = load i32, ptr [[UIE]], align 4
20554 // CHECK-NEXT:    [[TMP2735:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2734]] seq_cst, align 4
20555 // CHECK-NEXT:    store i32 [[TMP2735]], ptr [[UIV]], align 4
20556 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20557 // CHECK-NEXT:    [[TMP2736:%.*]] = load i32, ptr [[UIE]], align 4
20558 // CHECK-NEXT:    [[TMP2737:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2736]] seq_cst, align 4
20559 // CHECK-NEXT:    store i32 [[TMP2737]], ptr [[UIV]], align 4
20560 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20561 // CHECK-NEXT:    [[TMP2738:%.*]] = load i32, ptr [[UIE]], align 4
20562 // CHECK-NEXT:    [[TMP2739:%.*]] = load i32, ptr [[UID]], align 4
20563 // CHECK-NEXT:    [[TMP2740:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2738]], i32 [[TMP2739]] seq_cst seq_cst, align 4
20564 // CHECK-NEXT:    [[TMP2741:%.*]] = extractvalue { i32, i1 } [[TMP2740]], 0
20565 // CHECK-NEXT:    store i32 [[TMP2741]], ptr [[UIV]], align 4
20566 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20567 // CHECK-NEXT:    [[TMP2742:%.*]] = load i32, ptr [[UIE]], align 4
20568 // CHECK-NEXT:    [[TMP2743:%.*]] = load i32, ptr [[UID]], align 4
20569 // CHECK-NEXT:    [[TMP2744:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2742]], i32 [[TMP2743]] seq_cst seq_cst, align 4
20570 // CHECK-NEXT:    [[TMP2745:%.*]] = extractvalue { i32, i1 } [[TMP2744]], 0
20571 // CHECK-NEXT:    store i32 [[TMP2745]], ptr [[UIV]], align 4
20572 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20573 // CHECK-NEXT:    [[TMP2746:%.*]] = load i32, ptr [[UIE]], align 4
20574 // CHECK-NEXT:    [[TMP2747:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2746]] seq_cst, align 4
20575 // CHECK-NEXT:    [[TMP2748:%.*]] = icmp ugt i32 [[TMP2747]], [[TMP2746]]
20576 // CHECK-NEXT:    [[TMP2749:%.*]] = select i1 [[TMP2748]], i32 [[TMP2746]], i32 [[TMP2747]]
20577 // CHECK-NEXT:    store i32 [[TMP2749]], ptr [[UIV]], align 4
20578 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20579 // CHECK-NEXT:    [[TMP2750:%.*]] = load i32, ptr [[UIE]], align 4
20580 // CHECK-NEXT:    [[TMP2751:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2750]] seq_cst, align 4
20581 // CHECK-NEXT:    [[TMP2752:%.*]] = icmp ult i32 [[TMP2751]], [[TMP2750]]
20582 // CHECK-NEXT:    [[TMP2753:%.*]] = select i1 [[TMP2752]], i32 [[TMP2750]], i32 [[TMP2751]]
20583 // CHECK-NEXT:    store i32 [[TMP2753]], ptr [[UIV]], align 4
20584 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20585 // CHECK-NEXT:    [[TMP2754:%.*]] = load i32, ptr [[UIE]], align 4
20586 // CHECK-NEXT:    [[TMP2755:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2754]] seq_cst, align 4
20587 // CHECK-NEXT:    [[TMP2756:%.*]] = icmp ult i32 [[TMP2755]], [[TMP2754]]
20588 // CHECK-NEXT:    [[TMP2757:%.*]] = select i1 [[TMP2756]], i32 [[TMP2754]], i32 [[TMP2755]]
20589 // CHECK-NEXT:    store i32 [[TMP2757]], ptr [[UIV]], align 4
20590 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20591 // CHECK-NEXT:    [[TMP2758:%.*]] = load i32, ptr [[UIE]], align 4
20592 // CHECK-NEXT:    [[TMP2759:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2758]] seq_cst, align 4
20593 // CHECK-NEXT:    [[TMP2760:%.*]] = icmp ugt i32 [[TMP2759]], [[TMP2758]]
20594 // CHECK-NEXT:    [[TMP2761:%.*]] = select i1 [[TMP2760]], i32 [[TMP2758]], i32 [[TMP2759]]
20595 // CHECK-NEXT:    store i32 [[TMP2761]], ptr [[UIV]], align 4
20596 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20597 // CHECK-NEXT:    [[TMP2762:%.*]] = load i32, ptr [[UIE]], align 4
20598 // CHECK-NEXT:    [[TMP2763:%.*]] = load i32, ptr [[UID]], align 4
20599 // CHECK-NEXT:    [[TMP2764:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2762]], i32 [[TMP2763]] seq_cst seq_cst, align 4
20600 // CHECK-NEXT:    [[TMP2765:%.*]] = extractvalue { i32, i1 } [[TMP2764]], 0
20601 // CHECK-NEXT:    [[TMP2766:%.*]] = extractvalue { i32, i1 } [[TMP2764]], 1
20602 // CHECK-NEXT:    [[TMP2767:%.*]] = select i1 [[TMP2766]], i32 [[TMP2762]], i32 [[TMP2765]]
20603 // CHECK-NEXT:    store i32 [[TMP2767]], ptr [[UIV]], align 4
20604 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20605 // CHECK-NEXT:    [[TMP2768:%.*]] = load i32, ptr [[UIE]], align 4
20606 // CHECK-NEXT:    [[TMP2769:%.*]] = load i32, ptr [[UID]], align 4
20607 // CHECK-NEXT:    [[TMP2770:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2768]], i32 [[TMP2769]] seq_cst seq_cst, align 4
20608 // CHECK-NEXT:    [[TMP2771:%.*]] = extractvalue { i32, i1 } [[TMP2770]], 0
20609 // CHECK-NEXT:    [[TMP2772:%.*]] = extractvalue { i32, i1 } [[TMP2770]], 1
20610 // CHECK-NEXT:    [[TMP2773:%.*]] = select i1 [[TMP2772]], i32 [[TMP2768]], i32 [[TMP2771]]
20611 // CHECK-NEXT:    store i32 [[TMP2773]], ptr [[UIV]], align 4
20612 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20613 // CHECK-NEXT:    [[TMP2774:%.*]] = load i32, ptr [[UIE]], align 4
20614 // CHECK-NEXT:    [[TMP2775:%.*]] = load i32, ptr [[UID]], align 4
20615 // CHECK-NEXT:    [[TMP2776:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2774]], i32 [[TMP2775]] seq_cst seq_cst, align 4
20616 // CHECK-NEXT:    [[TMP2777:%.*]] = extractvalue { i32, i1 } [[TMP2776]], 0
20617 // CHECK-NEXT:    [[TMP2778:%.*]] = extractvalue { i32, i1 } [[TMP2776]], 1
20618 // CHECK-NEXT:    br i1 [[TMP2778]], label [[UIX_ATOMIC_EXIT269:%.*]], label [[UIX_ATOMIC_CONT270:%.*]]
20619 // CHECK:       uix.atomic.cont270:
20620 // CHECK-NEXT:    store i32 [[TMP2777]], ptr [[UIV]], align 4
20621 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT269]]
20622 // CHECK:       uix.atomic.exit269:
20623 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20624 // CHECK-NEXT:    [[TMP2779:%.*]] = load i32, ptr [[UIE]], align 4
20625 // CHECK-NEXT:    [[TMP2780:%.*]] = load i32, ptr [[UID]], align 4
20626 // CHECK-NEXT:    [[TMP2781:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2779]], i32 [[TMP2780]] seq_cst seq_cst, align 4
20627 // CHECK-NEXT:    [[TMP2782:%.*]] = extractvalue { i32, i1 } [[TMP2781]], 0
20628 // CHECK-NEXT:    [[TMP2783:%.*]] = extractvalue { i32, i1 } [[TMP2781]], 1
20629 // CHECK-NEXT:    br i1 [[TMP2783]], label [[UIX_ATOMIC_EXIT271:%.*]], label [[UIX_ATOMIC_CONT272:%.*]]
20630 // CHECK:       uix.atomic.cont272:
20631 // CHECK-NEXT:    store i32 [[TMP2782]], ptr [[UIV]], align 4
20632 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT271]]
20633 // CHECK:       uix.atomic.exit271:
20634 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20635 // CHECK-NEXT:    [[TMP2784:%.*]] = load i32, ptr [[UIE]], align 4
20636 // CHECK-NEXT:    [[TMP2785:%.*]] = load i32, ptr [[UID]], align 4
20637 // CHECK-NEXT:    [[TMP2786:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2784]], i32 [[TMP2785]] seq_cst seq_cst, align 4
20638 // CHECK-NEXT:    [[TMP2787:%.*]] = extractvalue { i32, i1 } [[TMP2786]], 1
20639 // CHECK-NEXT:    [[TMP2788:%.*]] = zext i1 [[TMP2787]] to i32
20640 // CHECK-NEXT:    store i32 [[TMP2788]], ptr [[UIR]], align 4
20641 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20642 // CHECK-NEXT:    [[TMP2789:%.*]] = load i32, ptr [[UIE]], align 4
20643 // CHECK-NEXT:    [[TMP2790:%.*]] = load i32, ptr [[UID]], align 4
20644 // CHECK-NEXT:    [[TMP2791:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2789]], i32 [[TMP2790]] seq_cst seq_cst, align 4
20645 // CHECK-NEXT:    [[TMP2792:%.*]] = extractvalue { i32, i1 } [[TMP2791]], 1
20646 // CHECK-NEXT:    [[TMP2793:%.*]] = zext i1 [[TMP2792]] to i32
20647 // CHECK-NEXT:    store i32 [[TMP2793]], ptr [[UIR]], align 4
20648 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20649 // CHECK-NEXT:    [[TMP2794:%.*]] = load i32, ptr [[UIE]], align 4
20650 // CHECK-NEXT:    [[TMP2795:%.*]] = load i32, ptr [[UID]], align 4
20651 // CHECK-NEXT:    [[TMP2796:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2794]], i32 [[TMP2795]] seq_cst seq_cst, align 4
20652 // CHECK-NEXT:    [[TMP2797:%.*]] = extractvalue { i32, i1 } [[TMP2796]], 0
20653 // CHECK-NEXT:    [[TMP2798:%.*]] = extractvalue { i32, i1 } [[TMP2796]], 1
20654 // CHECK-NEXT:    br i1 [[TMP2798]], label [[UIX_ATOMIC_EXIT273:%.*]], label [[UIX_ATOMIC_CONT274:%.*]]
20655 // CHECK:       uix.atomic.cont274:
20656 // CHECK-NEXT:    store i32 [[TMP2797]], ptr [[UIV]], align 4
20657 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT273]]
20658 // CHECK:       uix.atomic.exit273:
20659 // CHECK-NEXT:    [[TMP2799:%.*]] = extractvalue { i32, i1 } [[TMP2796]], 1
20660 // CHECK-NEXT:    [[TMP2800:%.*]] = zext i1 [[TMP2799]] to i32
20661 // CHECK-NEXT:    store i32 [[TMP2800]], ptr [[UIR]], align 4
20662 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20663 // CHECK-NEXT:    [[TMP2801:%.*]] = load i32, ptr [[UIE]], align 4
20664 // CHECK-NEXT:    [[TMP2802:%.*]] = load i32, ptr [[UID]], align 4
20665 // CHECK-NEXT:    [[TMP2803:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2801]], i32 [[TMP2802]] seq_cst seq_cst, align 4
20666 // CHECK-NEXT:    [[TMP2804:%.*]] = extractvalue { i32, i1 } [[TMP2803]], 0
20667 // CHECK-NEXT:    [[TMP2805:%.*]] = extractvalue { i32, i1 } [[TMP2803]], 1
20668 // CHECK-NEXT:    br i1 [[TMP2805]], label [[UIX_ATOMIC_EXIT275:%.*]], label [[UIX_ATOMIC_CONT276:%.*]]
20669 // CHECK:       uix.atomic.cont276:
20670 // CHECK-NEXT:    store i32 [[TMP2804]], ptr [[UIV]], align 4
20671 // CHECK-NEXT:    br label [[UIX_ATOMIC_EXIT275]]
20672 // CHECK:       uix.atomic.exit275:
20673 // CHECK-NEXT:    [[TMP2806:%.*]] = extractvalue { i32, i1 } [[TMP2803]], 1
20674 // CHECK-NEXT:    [[TMP2807:%.*]] = zext i1 [[TMP2806]] to i32
20675 // CHECK-NEXT:    store i32 [[TMP2807]], ptr [[UIR]], align 4
20676 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20677 // CHECK-NEXT:    [[TMP2808:%.*]] = load i64, ptr [[LE]], align 8
20678 // CHECK-NEXT:    [[TMP2809:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2808]] monotonic, align 8
20679 // CHECK-NEXT:    store i64 [[TMP2809]], ptr [[LV]], align 8
20680 // CHECK-NEXT:    [[TMP2810:%.*]] = load i64, ptr [[LE]], align 8
20681 // CHECK-NEXT:    [[TMP2811:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2810]] monotonic, align 8
20682 // CHECK-NEXT:    store i64 [[TMP2811]], ptr [[LV]], align 8
20683 // CHECK-NEXT:    [[TMP2812:%.*]] = load i64, ptr [[LE]], align 8
20684 // CHECK-NEXT:    [[TMP2813:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2812]] monotonic, align 8
20685 // CHECK-NEXT:    store i64 [[TMP2813]], ptr [[LV]], align 8
20686 // CHECK-NEXT:    [[TMP2814:%.*]] = load i64, ptr [[LE]], align 8
20687 // CHECK-NEXT:    [[TMP2815:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2814]] monotonic, align 8
20688 // CHECK-NEXT:    store i64 [[TMP2815]], ptr [[LV]], align 8
20689 // CHECK-NEXT:    [[TMP2816:%.*]] = load i64, ptr [[LE]], align 8
20690 // CHECK-NEXT:    [[TMP2817:%.*]] = load i64, ptr [[LD]], align 8
20691 // CHECK-NEXT:    [[TMP2818:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2816]], i64 [[TMP2817]] monotonic monotonic, align 8
20692 // CHECK-NEXT:    [[TMP2819:%.*]] = extractvalue { i64, i1 } [[TMP2818]], 0
20693 // CHECK-NEXT:    store i64 [[TMP2819]], ptr [[LV]], align 8
20694 // CHECK-NEXT:    [[TMP2820:%.*]] = load i64, ptr [[LE]], align 8
20695 // CHECK-NEXT:    [[TMP2821:%.*]] = load i64, ptr [[LD]], align 8
20696 // CHECK-NEXT:    [[TMP2822:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2820]], i64 [[TMP2821]] monotonic monotonic, align 8
20697 // CHECK-NEXT:    [[TMP2823:%.*]] = extractvalue { i64, i1 } [[TMP2822]], 0
20698 // CHECK-NEXT:    store i64 [[TMP2823]], ptr [[LV]], align 8
20699 // CHECK-NEXT:    [[TMP2824:%.*]] = load i64, ptr [[LE]], align 8
20700 // CHECK-NEXT:    [[TMP2825:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2824]] monotonic, align 8
20701 // CHECK-NEXT:    [[TMP2826:%.*]] = icmp sgt i64 [[TMP2825]], [[TMP2824]]
20702 // CHECK-NEXT:    [[TMP2827:%.*]] = select i1 [[TMP2826]], i64 [[TMP2824]], i64 [[TMP2825]]
20703 // CHECK-NEXT:    store i64 [[TMP2827]], ptr [[LV]], align 8
20704 // CHECK-NEXT:    [[TMP2828:%.*]] = load i64, ptr [[LE]], align 8
20705 // CHECK-NEXT:    [[TMP2829:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2828]] monotonic, align 8
20706 // CHECK-NEXT:    [[TMP2830:%.*]] = icmp slt i64 [[TMP2829]], [[TMP2828]]
20707 // CHECK-NEXT:    [[TMP2831:%.*]] = select i1 [[TMP2830]], i64 [[TMP2828]], i64 [[TMP2829]]
20708 // CHECK-NEXT:    store i64 [[TMP2831]], ptr [[LV]], align 8
20709 // CHECK-NEXT:    [[TMP2832:%.*]] = load i64, ptr [[LE]], align 8
20710 // CHECK-NEXT:    [[TMP2833:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2832]] monotonic, align 8
20711 // CHECK-NEXT:    [[TMP2834:%.*]] = icmp slt i64 [[TMP2833]], [[TMP2832]]
20712 // CHECK-NEXT:    [[TMP2835:%.*]] = select i1 [[TMP2834]], i64 [[TMP2832]], i64 [[TMP2833]]
20713 // CHECK-NEXT:    store i64 [[TMP2835]], ptr [[LV]], align 8
20714 // CHECK-NEXT:    [[TMP2836:%.*]] = load i64, ptr [[LE]], align 8
20715 // CHECK-NEXT:    [[TMP2837:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2836]] monotonic, align 8
20716 // CHECK-NEXT:    [[TMP2838:%.*]] = icmp sgt i64 [[TMP2837]], [[TMP2836]]
20717 // CHECK-NEXT:    [[TMP2839:%.*]] = select i1 [[TMP2838]], i64 [[TMP2836]], i64 [[TMP2837]]
20718 // CHECK-NEXT:    store i64 [[TMP2839]], ptr [[LV]], align 8
20719 // CHECK-NEXT:    [[TMP2840:%.*]] = load i64, ptr [[LE]], align 8
20720 // CHECK-NEXT:    [[TMP2841:%.*]] = load i64, ptr [[LD]], align 8
20721 // CHECK-NEXT:    [[TMP2842:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2840]], i64 [[TMP2841]] monotonic monotonic, align 8
20722 // CHECK-NEXT:    [[TMP2843:%.*]] = extractvalue { i64, i1 } [[TMP2842]], 0
20723 // CHECK-NEXT:    [[TMP2844:%.*]] = extractvalue { i64, i1 } [[TMP2842]], 1
20724 // CHECK-NEXT:    [[TMP2845:%.*]] = select i1 [[TMP2844]], i64 [[TMP2840]], i64 [[TMP2843]]
20725 // CHECK-NEXT:    store i64 [[TMP2845]], ptr [[LV]], align 8
20726 // CHECK-NEXT:    [[TMP2846:%.*]] = load i64, ptr [[LE]], align 8
20727 // CHECK-NEXT:    [[TMP2847:%.*]] = load i64, ptr [[LD]], align 8
20728 // CHECK-NEXT:    [[TMP2848:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2846]], i64 [[TMP2847]] monotonic monotonic, align 8
20729 // CHECK-NEXT:    [[TMP2849:%.*]] = extractvalue { i64, i1 } [[TMP2848]], 0
20730 // CHECK-NEXT:    [[TMP2850:%.*]] = extractvalue { i64, i1 } [[TMP2848]], 1
20731 // CHECK-NEXT:    [[TMP2851:%.*]] = select i1 [[TMP2850]], i64 [[TMP2846]], i64 [[TMP2849]]
20732 // CHECK-NEXT:    store i64 [[TMP2851]], ptr [[LV]], align 8
20733 // CHECK-NEXT:    [[TMP2852:%.*]] = load i64, ptr [[LE]], align 8
20734 // CHECK-NEXT:    [[TMP2853:%.*]] = load i64, ptr [[LD]], align 8
20735 // CHECK-NEXT:    [[TMP2854:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2852]], i64 [[TMP2853]] monotonic monotonic, align 8
20736 // CHECK-NEXT:    [[TMP2855:%.*]] = extractvalue { i64, i1 } [[TMP2854]], 0
20737 // CHECK-NEXT:    [[TMP2856:%.*]] = extractvalue { i64, i1 } [[TMP2854]], 1
20738 // CHECK-NEXT:    br i1 [[TMP2856]], label [[LX_ATOMIC_EXIT:%.*]], label [[LX_ATOMIC_CONT:%.*]]
20739 // CHECK:       lx.atomic.cont:
20740 // CHECK-NEXT:    store i64 [[TMP2855]], ptr [[LV]], align 8
20741 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT]]
20742 // CHECK:       lx.atomic.exit:
20743 // CHECK-NEXT:    [[TMP2857:%.*]] = load i64, ptr [[LE]], align 8
20744 // CHECK-NEXT:    [[TMP2858:%.*]] = load i64, ptr [[LD]], align 8
20745 // CHECK-NEXT:    [[TMP2859:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2857]], i64 [[TMP2858]] monotonic monotonic, align 8
20746 // CHECK-NEXT:    [[TMP2860:%.*]] = extractvalue { i64, i1 } [[TMP2859]], 0
20747 // CHECK-NEXT:    [[TMP2861:%.*]] = extractvalue { i64, i1 } [[TMP2859]], 1
20748 // CHECK-NEXT:    br i1 [[TMP2861]], label [[LX_ATOMIC_EXIT277:%.*]], label [[LX_ATOMIC_CONT278:%.*]]
20749 // CHECK:       lx.atomic.cont278:
20750 // CHECK-NEXT:    store i64 [[TMP2860]], ptr [[LV]], align 8
20751 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT277]]
20752 // CHECK:       lx.atomic.exit277:
20753 // CHECK-NEXT:    [[TMP2862:%.*]] = load i64, ptr [[LE]], align 8
20754 // CHECK-NEXT:    [[TMP2863:%.*]] = load i64, ptr [[LD]], align 8
20755 // CHECK-NEXT:    [[TMP2864:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2862]], i64 [[TMP2863]] monotonic monotonic, align 8
20756 // CHECK-NEXT:    [[TMP2865:%.*]] = extractvalue { i64, i1 } [[TMP2864]], 1
20757 // CHECK-NEXT:    [[TMP2866:%.*]] = sext i1 [[TMP2865]] to i64
20758 // CHECK-NEXT:    store i64 [[TMP2866]], ptr [[LR]], align 8
20759 // CHECK-NEXT:    [[TMP2867:%.*]] = load i64, ptr [[LE]], align 8
20760 // CHECK-NEXT:    [[TMP2868:%.*]] = load i64, ptr [[LD]], align 8
20761 // CHECK-NEXT:    [[TMP2869:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2867]], i64 [[TMP2868]] monotonic monotonic, align 8
20762 // CHECK-NEXT:    [[TMP2870:%.*]] = extractvalue { i64, i1 } [[TMP2869]], 1
20763 // CHECK-NEXT:    [[TMP2871:%.*]] = sext i1 [[TMP2870]] to i64
20764 // CHECK-NEXT:    store i64 [[TMP2871]], ptr [[LR]], align 8
20765 // CHECK-NEXT:    [[TMP2872:%.*]] = load i64, ptr [[LE]], align 8
20766 // CHECK-NEXT:    [[TMP2873:%.*]] = load i64, ptr [[LD]], align 8
20767 // CHECK-NEXT:    [[TMP2874:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2872]], i64 [[TMP2873]] monotonic monotonic, align 8
20768 // CHECK-NEXT:    [[TMP2875:%.*]] = extractvalue { i64, i1 } [[TMP2874]], 0
20769 // CHECK-NEXT:    [[TMP2876:%.*]] = extractvalue { i64, i1 } [[TMP2874]], 1
20770 // CHECK-NEXT:    br i1 [[TMP2876]], label [[LX_ATOMIC_EXIT279:%.*]], label [[LX_ATOMIC_CONT280:%.*]]
20771 // CHECK:       lx.atomic.cont280:
20772 // CHECK-NEXT:    store i64 [[TMP2875]], ptr [[LV]], align 8
20773 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT279]]
20774 // CHECK:       lx.atomic.exit279:
20775 // CHECK-NEXT:    [[TMP2877:%.*]] = extractvalue { i64, i1 } [[TMP2874]], 1
20776 // CHECK-NEXT:    [[TMP2878:%.*]] = sext i1 [[TMP2877]] to i64
20777 // CHECK-NEXT:    store i64 [[TMP2878]], ptr [[LR]], align 8
20778 // CHECK-NEXT:    [[TMP2879:%.*]] = load i64, ptr [[LE]], align 8
20779 // CHECK-NEXT:    [[TMP2880:%.*]] = load i64, ptr [[LD]], align 8
20780 // CHECK-NEXT:    [[TMP2881:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2879]], i64 [[TMP2880]] monotonic monotonic, align 8
20781 // CHECK-NEXT:    [[TMP2882:%.*]] = extractvalue { i64, i1 } [[TMP2881]], 0
20782 // CHECK-NEXT:    [[TMP2883:%.*]] = extractvalue { i64, i1 } [[TMP2881]], 1
20783 // CHECK-NEXT:    br i1 [[TMP2883]], label [[LX_ATOMIC_EXIT281:%.*]], label [[LX_ATOMIC_CONT282:%.*]]
20784 // CHECK:       lx.atomic.cont282:
20785 // CHECK-NEXT:    store i64 [[TMP2882]], ptr [[LV]], align 8
20786 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT281]]
20787 // CHECK:       lx.atomic.exit281:
20788 // CHECK-NEXT:    [[TMP2884:%.*]] = extractvalue { i64, i1 } [[TMP2881]], 1
20789 // CHECK-NEXT:    [[TMP2885:%.*]] = sext i1 [[TMP2884]] to i64
20790 // CHECK-NEXT:    store i64 [[TMP2885]], ptr [[LR]], align 8
20791 // CHECK-NEXT:    [[TMP2886:%.*]] = load i64, ptr [[LE]], align 8
20792 // CHECK-NEXT:    [[TMP2887:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2886]] acq_rel, align 8
20793 // CHECK-NEXT:    store i64 [[TMP2887]], ptr [[LV]], align 8
20794 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20795 // CHECK-NEXT:    [[TMP2888:%.*]] = load i64, ptr [[LE]], align 8
20796 // CHECK-NEXT:    [[TMP2889:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2888]] acq_rel, align 8
20797 // CHECK-NEXT:    store i64 [[TMP2889]], ptr [[LV]], align 8
20798 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20799 // CHECK-NEXT:    [[TMP2890:%.*]] = load i64, ptr [[LE]], align 8
20800 // CHECK-NEXT:    [[TMP2891:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2890]] acq_rel, align 8
20801 // CHECK-NEXT:    store i64 [[TMP2891]], ptr [[LV]], align 8
20802 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20803 // CHECK-NEXT:    [[TMP2892:%.*]] = load i64, ptr [[LE]], align 8
20804 // CHECK-NEXT:    [[TMP2893:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2892]] acq_rel, align 8
20805 // CHECK-NEXT:    store i64 [[TMP2893]], ptr [[LV]], align 8
20806 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20807 // CHECK-NEXT:    [[TMP2894:%.*]] = load i64, ptr [[LE]], align 8
20808 // CHECK-NEXT:    [[TMP2895:%.*]] = load i64, ptr [[LD]], align 8
20809 // CHECK-NEXT:    [[TMP2896:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2894]], i64 [[TMP2895]] acq_rel acquire, align 8
20810 // CHECK-NEXT:    [[TMP2897:%.*]] = extractvalue { i64, i1 } [[TMP2896]], 0
20811 // CHECK-NEXT:    store i64 [[TMP2897]], ptr [[LV]], align 8
20812 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20813 // CHECK-NEXT:    [[TMP2898:%.*]] = load i64, ptr [[LE]], align 8
20814 // CHECK-NEXT:    [[TMP2899:%.*]] = load i64, ptr [[LD]], align 8
20815 // CHECK-NEXT:    [[TMP2900:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2898]], i64 [[TMP2899]] acq_rel acquire, align 8
20816 // CHECK-NEXT:    [[TMP2901:%.*]] = extractvalue { i64, i1 } [[TMP2900]], 0
20817 // CHECK-NEXT:    store i64 [[TMP2901]], ptr [[LV]], align 8
20818 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20819 // CHECK-NEXT:    [[TMP2902:%.*]] = load i64, ptr [[LE]], align 8
20820 // CHECK-NEXT:    [[TMP2903:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2902]] acq_rel, align 8
20821 // CHECK-NEXT:    [[TMP2904:%.*]] = icmp sgt i64 [[TMP2903]], [[TMP2902]]
20822 // CHECK-NEXT:    [[TMP2905:%.*]] = select i1 [[TMP2904]], i64 [[TMP2902]], i64 [[TMP2903]]
20823 // CHECK-NEXT:    store i64 [[TMP2905]], ptr [[LV]], align 8
20824 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20825 // CHECK-NEXT:    [[TMP2906:%.*]] = load i64, ptr [[LE]], align 8
20826 // CHECK-NEXT:    [[TMP2907:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2906]] acq_rel, align 8
20827 // CHECK-NEXT:    [[TMP2908:%.*]] = icmp slt i64 [[TMP2907]], [[TMP2906]]
20828 // CHECK-NEXT:    [[TMP2909:%.*]] = select i1 [[TMP2908]], i64 [[TMP2906]], i64 [[TMP2907]]
20829 // CHECK-NEXT:    store i64 [[TMP2909]], ptr [[LV]], align 8
20830 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20831 // CHECK-NEXT:    [[TMP2910:%.*]] = load i64, ptr [[LE]], align 8
20832 // CHECK-NEXT:    [[TMP2911:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2910]] acq_rel, align 8
20833 // CHECK-NEXT:    [[TMP2912:%.*]] = icmp slt i64 [[TMP2911]], [[TMP2910]]
20834 // CHECK-NEXT:    [[TMP2913:%.*]] = select i1 [[TMP2912]], i64 [[TMP2910]], i64 [[TMP2911]]
20835 // CHECK-NEXT:    store i64 [[TMP2913]], ptr [[LV]], align 8
20836 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20837 // CHECK-NEXT:    [[TMP2914:%.*]] = load i64, ptr [[LE]], align 8
20838 // CHECK-NEXT:    [[TMP2915:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2914]] acq_rel, align 8
20839 // CHECK-NEXT:    [[TMP2916:%.*]] = icmp sgt i64 [[TMP2915]], [[TMP2914]]
20840 // CHECK-NEXT:    [[TMP2917:%.*]] = select i1 [[TMP2916]], i64 [[TMP2914]], i64 [[TMP2915]]
20841 // CHECK-NEXT:    store i64 [[TMP2917]], ptr [[LV]], align 8
20842 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20843 // CHECK-NEXT:    [[TMP2918:%.*]] = load i64, ptr [[LE]], align 8
20844 // CHECK-NEXT:    [[TMP2919:%.*]] = load i64, ptr [[LD]], align 8
20845 // CHECK-NEXT:    [[TMP2920:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2918]], i64 [[TMP2919]] acq_rel acquire, align 8
20846 // CHECK-NEXT:    [[TMP2921:%.*]] = extractvalue { i64, i1 } [[TMP2920]], 0
20847 // CHECK-NEXT:    [[TMP2922:%.*]] = extractvalue { i64, i1 } [[TMP2920]], 1
20848 // CHECK-NEXT:    [[TMP2923:%.*]] = select i1 [[TMP2922]], i64 [[TMP2918]], i64 [[TMP2921]]
20849 // CHECK-NEXT:    store i64 [[TMP2923]], ptr [[LV]], align 8
20850 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20851 // CHECK-NEXT:    [[TMP2924:%.*]] = load i64, ptr [[LE]], align 8
20852 // CHECK-NEXT:    [[TMP2925:%.*]] = load i64, ptr [[LD]], align 8
20853 // CHECK-NEXT:    [[TMP2926:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2924]], i64 [[TMP2925]] acq_rel acquire, align 8
20854 // CHECK-NEXT:    [[TMP2927:%.*]] = extractvalue { i64, i1 } [[TMP2926]], 0
20855 // CHECK-NEXT:    [[TMP2928:%.*]] = extractvalue { i64, i1 } [[TMP2926]], 1
20856 // CHECK-NEXT:    [[TMP2929:%.*]] = select i1 [[TMP2928]], i64 [[TMP2924]], i64 [[TMP2927]]
20857 // CHECK-NEXT:    store i64 [[TMP2929]], ptr [[LV]], align 8
20858 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20859 // CHECK-NEXT:    [[TMP2930:%.*]] = load i64, ptr [[LE]], align 8
20860 // CHECK-NEXT:    [[TMP2931:%.*]] = load i64, ptr [[LD]], align 8
20861 // CHECK-NEXT:    [[TMP2932:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2930]], i64 [[TMP2931]] acq_rel acquire, align 8
20862 // CHECK-NEXT:    [[TMP2933:%.*]] = extractvalue { i64, i1 } [[TMP2932]], 0
20863 // CHECK-NEXT:    [[TMP2934:%.*]] = extractvalue { i64, i1 } [[TMP2932]], 1
20864 // CHECK-NEXT:    br i1 [[TMP2934]], label [[LX_ATOMIC_EXIT283:%.*]], label [[LX_ATOMIC_CONT284:%.*]]
20865 // CHECK:       lx.atomic.cont284:
20866 // CHECK-NEXT:    store i64 [[TMP2933]], ptr [[LV]], align 8
20867 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT283]]
20868 // CHECK:       lx.atomic.exit283:
20869 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20870 // CHECK-NEXT:    [[TMP2935:%.*]] = load i64, ptr [[LE]], align 8
20871 // CHECK-NEXT:    [[TMP2936:%.*]] = load i64, ptr [[LD]], align 8
20872 // CHECK-NEXT:    [[TMP2937:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2935]], i64 [[TMP2936]] acq_rel acquire, align 8
20873 // CHECK-NEXT:    [[TMP2938:%.*]] = extractvalue { i64, i1 } [[TMP2937]], 0
20874 // CHECK-NEXT:    [[TMP2939:%.*]] = extractvalue { i64, i1 } [[TMP2937]], 1
20875 // CHECK-NEXT:    br i1 [[TMP2939]], label [[LX_ATOMIC_EXIT285:%.*]], label [[LX_ATOMIC_CONT286:%.*]]
20876 // CHECK:       lx.atomic.cont286:
20877 // CHECK-NEXT:    store i64 [[TMP2938]], ptr [[LV]], align 8
20878 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT285]]
20879 // CHECK:       lx.atomic.exit285:
20880 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20881 // CHECK-NEXT:    [[TMP2940:%.*]] = load i64, ptr [[LE]], align 8
20882 // CHECK-NEXT:    [[TMP2941:%.*]] = load i64, ptr [[LD]], align 8
20883 // CHECK-NEXT:    [[TMP2942:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2940]], i64 [[TMP2941]] acq_rel acquire, align 8
20884 // CHECK-NEXT:    [[TMP2943:%.*]] = extractvalue { i64, i1 } [[TMP2942]], 1
20885 // CHECK-NEXT:    [[TMP2944:%.*]] = sext i1 [[TMP2943]] to i64
20886 // CHECK-NEXT:    store i64 [[TMP2944]], ptr [[LR]], align 8
20887 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20888 // CHECK-NEXT:    [[TMP2945:%.*]] = load i64, ptr [[LE]], align 8
20889 // CHECK-NEXT:    [[TMP2946:%.*]] = load i64, ptr [[LD]], align 8
20890 // CHECK-NEXT:    [[TMP2947:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2945]], i64 [[TMP2946]] acq_rel acquire, align 8
20891 // CHECK-NEXT:    [[TMP2948:%.*]] = extractvalue { i64, i1 } [[TMP2947]], 1
20892 // CHECK-NEXT:    [[TMP2949:%.*]] = sext i1 [[TMP2948]] to i64
20893 // CHECK-NEXT:    store i64 [[TMP2949]], ptr [[LR]], align 8
20894 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20895 // CHECK-NEXT:    [[TMP2950:%.*]] = load i64, ptr [[LE]], align 8
20896 // CHECK-NEXT:    [[TMP2951:%.*]] = load i64, ptr [[LD]], align 8
20897 // CHECK-NEXT:    [[TMP2952:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2950]], i64 [[TMP2951]] acq_rel acquire, align 8
20898 // CHECK-NEXT:    [[TMP2953:%.*]] = extractvalue { i64, i1 } [[TMP2952]], 0
20899 // CHECK-NEXT:    [[TMP2954:%.*]] = extractvalue { i64, i1 } [[TMP2952]], 1
20900 // CHECK-NEXT:    br i1 [[TMP2954]], label [[LX_ATOMIC_EXIT287:%.*]], label [[LX_ATOMIC_CONT288:%.*]]
20901 // CHECK:       lx.atomic.cont288:
20902 // CHECK-NEXT:    store i64 [[TMP2953]], ptr [[LV]], align 8
20903 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT287]]
20904 // CHECK:       lx.atomic.exit287:
20905 // CHECK-NEXT:    [[TMP2955:%.*]] = extractvalue { i64, i1 } [[TMP2952]], 1
20906 // CHECK-NEXT:    [[TMP2956:%.*]] = sext i1 [[TMP2955]] to i64
20907 // CHECK-NEXT:    store i64 [[TMP2956]], ptr [[LR]], align 8
20908 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20909 // CHECK-NEXT:    [[TMP2957:%.*]] = load i64, ptr [[LE]], align 8
20910 // CHECK-NEXT:    [[TMP2958:%.*]] = load i64, ptr [[LD]], align 8
20911 // CHECK-NEXT:    [[TMP2959:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2957]], i64 [[TMP2958]] acq_rel acquire, align 8
20912 // CHECK-NEXT:    [[TMP2960:%.*]] = extractvalue { i64, i1 } [[TMP2959]], 0
20913 // CHECK-NEXT:    [[TMP2961:%.*]] = extractvalue { i64, i1 } [[TMP2959]], 1
20914 // CHECK-NEXT:    br i1 [[TMP2961]], label [[LX_ATOMIC_EXIT289:%.*]], label [[LX_ATOMIC_CONT290:%.*]]
20915 // CHECK:       lx.atomic.cont290:
20916 // CHECK-NEXT:    store i64 [[TMP2960]], ptr [[LV]], align 8
20917 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT289]]
20918 // CHECK:       lx.atomic.exit289:
20919 // CHECK-NEXT:    [[TMP2962:%.*]] = extractvalue { i64, i1 } [[TMP2959]], 1
20920 // CHECK-NEXT:    [[TMP2963:%.*]] = sext i1 [[TMP2962]] to i64
20921 // CHECK-NEXT:    store i64 [[TMP2963]], ptr [[LR]], align 8
20922 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
20923 // CHECK-NEXT:    [[TMP2964:%.*]] = load i64, ptr [[LE]], align 8
20924 // CHECK-NEXT:    [[TMP2965:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2964]] acquire, align 8
20925 // CHECK-NEXT:    store i64 [[TMP2965]], ptr [[LV]], align 8
20926 // CHECK-NEXT:    [[TMP2966:%.*]] = load i64, ptr [[LE]], align 8
20927 // CHECK-NEXT:    [[TMP2967:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2966]] acquire, align 8
20928 // CHECK-NEXT:    store i64 [[TMP2967]], ptr [[LV]], align 8
20929 // CHECK-NEXT:    [[TMP2968:%.*]] = load i64, ptr [[LE]], align 8
20930 // CHECK-NEXT:    [[TMP2969:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2968]] acquire, align 8
20931 // CHECK-NEXT:    store i64 [[TMP2969]], ptr [[LV]], align 8
20932 // CHECK-NEXT:    [[TMP2970:%.*]] = load i64, ptr [[LE]], align 8
20933 // CHECK-NEXT:    [[TMP2971:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2970]] acquire, align 8
20934 // CHECK-NEXT:    store i64 [[TMP2971]], ptr [[LV]], align 8
20935 // CHECK-NEXT:    [[TMP2972:%.*]] = load i64, ptr [[LE]], align 8
20936 // CHECK-NEXT:    [[TMP2973:%.*]] = load i64, ptr [[LD]], align 8
20937 // CHECK-NEXT:    [[TMP2974:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2972]], i64 [[TMP2973]] acquire acquire, align 8
20938 // CHECK-NEXT:    [[TMP2975:%.*]] = extractvalue { i64, i1 } [[TMP2974]], 0
20939 // CHECK-NEXT:    store i64 [[TMP2975]], ptr [[LV]], align 8
20940 // CHECK-NEXT:    [[TMP2976:%.*]] = load i64, ptr [[LE]], align 8
20941 // CHECK-NEXT:    [[TMP2977:%.*]] = load i64, ptr [[LD]], align 8
20942 // CHECK-NEXT:    [[TMP2978:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2976]], i64 [[TMP2977]] acquire acquire, align 8
20943 // CHECK-NEXT:    [[TMP2979:%.*]] = extractvalue { i64, i1 } [[TMP2978]], 0
20944 // CHECK-NEXT:    store i64 [[TMP2979]], ptr [[LV]], align 8
20945 // CHECK-NEXT:    [[TMP2980:%.*]] = load i64, ptr [[LE]], align 8
20946 // CHECK-NEXT:    [[TMP2981:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2980]] acquire, align 8
20947 // CHECK-NEXT:    [[TMP2982:%.*]] = icmp sgt i64 [[TMP2981]], [[TMP2980]]
20948 // CHECK-NEXT:    [[TMP2983:%.*]] = select i1 [[TMP2982]], i64 [[TMP2980]], i64 [[TMP2981]]
20949 // CHECK-NEXT:    store i64 [[TMP2983]], ptr [[LV]], align 8
20950 // CHECK-NEXT:    [[TMP2984:%.*]] = load i64, ptr [[LE]], align 8
20951 // CHECK-NEXT:    [[TMP2985:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2984]] acquire, align 8
20952 // CHECK-NEXT:    [[TMP2986:%.*]] = icmp slt i64 [[TMP2985]], [[TMP2984]]
20953 // CHECK-NEXT:    [[TMP2987:%.*]] = select i1 [[TMP2986]], i64 [[TMP2984]], i64 [[TMP2985]]
20954 // CHECK-NEXT:    store i64 [[TMP2987]], ptr [[LV]], align 8
20955 // CHECK-NEXT:    [[TMP2988:%.*]] = load i64, ptr [[LE]], align 8
20956 // CHECK-NEXT:    [[TMP2989:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2988]] acquire, align 8
20957 // CHECK-NEXT:    [[TMP2990:%.*]] = icmp slt i64 [[TMP2989]], [[TMP2988]]
20958 // CHECK-NEXT:    [[TMP2991:%.*]] = select i1 [[TMP2990]], i64 [[TMP2988]], i64 [[TMP2989]]
20959 // CHECK-NEXT:    store i64 [[TMP2991]], ptr [[LV]], align 8
20960 // CHECK-NEXT:    [[TMP2992:%.*]] = load i64, ptr [[LE]], align 8
20961 // CHECK-NEXT:    [[TMP2993:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2992]] acquire, align 8
20962 // CHECK-NEXT:    [[TMP2994:%.*]] = icmp sgt i64 [[TMP2993]], [[TMP2992]]
20963 // CHECK-NEXT:    [[TMP2995:%.*]] = select i1 [[TMP2994]], i64 [[TMP2992]], i64 [[TMP2993]]
20964 // CHECK-NEXT:    store i64 [[TMP2995]], ptr [[LV]], align 8
20965 // CHECK-NEXT:    [[TMP2996:%.*]] = load i64, ptr [[LE]], align 8
20966 // CHECK-NEXT:    [[TMP2997:%.*]] = load i64, ptr [[LD]], align 8
20967 // CHECK-NEXT:    [[TMP2998:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2996]], i64 [[TMP2997]] acquire acquire, align 8
20968 // CHECK-NEXT:    [[TMP2999:%.*]] = extractvalue { i64, i1 } [[TMP2998]], 0
20969 // CHECK-NEXT:    [[TMP3000:%.*]] = extractvalue { i64, i1 } [[TMP2998]], 1
20970 // CHECK-NEXT:    [[TMP3001:%.*]] = select i1 [[TMP3000]], i64 [[TMP2996]], i64 [[TMP2999]]
20971 // CHECK-NEXT:    store i64 [[TMP3001]], ptr [[LV]], align 8
20972 // CHECK-NEXT:    [[TMP3002:%.*]] = load i64, ptr [[LE]], align 8
20973 // CHECK-NEXT:    [[TMP3003:%.*]] = load i64, ptr [[LD]], align 8
20974 // CHECK-NEXT:    [[TMP3004:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3002]], i64 [[TMP3003]] acquire acquire, align 8
20975 // CHECK-NEXT:    [[TMP3005:%.*]] = extractvalue { i64, i1 } [[TMP3004]], 0
20976 // CHECK-NEXT:    [[TMP3006:%.*]] = extractvalue { i64, i1 } [[TMP3004]], 1
20977 // CHECK-NEXT:    [[TMP3007:%.*]] = select i1 [[TMP3006]], i64 [[TMP3002]], i64 [[TMP3005]]
20978 // CHECK-NEXT:    store i64 [[TMP3007]], ptr [[LV]], align 8
20979 // CHECK-NEXT:    [[TMP3008:%.*]] = load i64, ptr [[LE]], align 8
20980 // CHECK-NEXT:    [[TMP3009:%.*]] = load i64, ptr [[LD]], align 8
20981 // CHECK-NEXT:    [[TMP3010:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3008]], i64 [[TMP3009]] acquire acquire, align 8
20982 // CHECK-NEXT:    [[TMP3011:%.*]] = extractvalue { i64, i1 } [[TMP3010]], 0
20983 // CHECK-NEXT:    [[TMP3012:%.*]] = extractvalue { i64, i1 } [[TMP3010]], 1
20984 // CHECK-NEXT:    br i1 [[TMP3012]], label [[LX_ATOMIC_EXIT291:%.*]], label [[LX_ATOMIC_CONT292:%.*]]
20985 // CHECK:       lx.atomic.cont292:
20986 // CHECK-NEXT:    store i64 [[TMP3011]], ptr [[LV]], align 8
20987 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT291]]
20988 // CHECK:       lx.atomic.exit291:
20989 // CHECK-NEXT:    [[TMP3013:%.*]] = load i64, ptr [[LE]], align 8
20990 // CHECK-NEXT:    [[TMP3014:%.*]] = load i64, ptr [[LD]], align 8
20991 // CHECK-NEXT:    [[TMP3015:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3013]], i64 [[TMP3014]] acquire acquire, align 8
20992 // CHECK-NEXT:    [[TMP3016:%.*]] = extractvalue { i64, i1 } [[TMP3015]], 0
20993 // CHECK-NEXT:    [[TMP3017:%.*]] = extractvalue { i64, i1 } [[TMP3015]], 1
20994 // CHECK-NEXT:    br i1 [[TMP3017]], label [[LX_ATOMIC_EXIT293:%.*]], label [[LX_ATOMIC_CONT294:%.*]]
20995 // CHECK:       lx.atomic.cont294:
20996 // CHECK-NEXT:    store i64 [[TMP3016]], ptr [[LV]], align 8
20997 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT293]]
20998 // CHECK:       lx.atomic.exit293:
20999 // CHECK-NEXT:    [[TMP3018:%.*]] = load i64, ptr [[LE]], align 8
21000 // CHECK-NEXT:    [[TMP3019:%.*]] = load i64, ptr [[LD]], align 8
21001 // CHECK-NEXT:    [[TMP3020:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3018]], i64 [[TMP3019]] acquire acquire, align 8
21002 // CHECK-NEXT:    [[TMP3021:%.*]] = extractvalue { i64, i1 } [[TMP3020]], 1
21003 // CHECK-NEXT:    [[TMP3022:%.*]] = sext i1 [[TMP3021]] to i64
21004 // CHECK-NEXT:    store i64 [[TMP3022]], ptr [[LR]], align 8
21005 // CHECK-NEXT:    [[TMP3023:%.*]] = load i64, ptr [[LE]], align 8
21006 // CHECK-NEXT:    [[TMP3024:%.*]] = load i64, ptr [[LD]], align 8
21007 // CHECK-NEXT:    [[TMP3025:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3023]], i64 [[TMP3024]] acquire acquire, align 8
21008 // CHECK-NEXT:    [[TMP3026:%.*]] = extractvalue { i64, i1 } [[TMP3025]], 1
21009 // CHECK-NEXT:    [[TMP3027:%.*]] = sext i1 [[TMP3026]] to i64
21010 // CHECK-NEXT:    store i64 [[TMP3027]], ptr [[LR]], align 8
21011 // CHECK-NEXT:    [[TMP3028:%.*]] = load i64, ptr [[LE]], align 8
21012 // CHECK-NEXT:    [[TMP3029:%.*]] = load i64, ptr [[LD]], align 8
21013 // CHECK-NEXT:    [[TMP3030:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3028]], i64 [[TMP3029]] acquire acquire, align 8
21014 // CHECK-NEXT:    [[TMP3031:%.*]] = extractvalue { i64, i1 } [[TMP3030]], 0
21015 // CHECK-NEXT:    [[TMP3032:%.*]] = extractvalue { i64, i1 } [[TMP3030]], 1
21016 // CHECK-NEXT:    br i1 [[TMP3032]], label [[LX_ATOMIC_EXIT295:%.*]], label [[LX_ATOMIC_CONT296:%.*]]
21017 // CHECK:       lx.atomic.cont296:
21018 // CHECK-NEXT:    store i64 [[TMP3031]], ptr [[LV]], align 8
21019 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT295]]
21020 // CHECK:       lx.atomic.exit295:
21021 // CHECK-NEXT:    [[TMP3033:%.*]] = extractvalue { i64, i1 } [[TMP3030]], 1
21022 // CHECK-NEXT:    [[TMP3034:%.*]] = sext i1 [[TMP3033]] to i64
21023 // CHECK-NEXT:    store i64 [[TMP3034]], ptr [[LR]], align 8
21024 // CHECK-NEXT:    [[TMP3035:%.*]] = load i64, ptr [[LE]], align 8
21025 // CHECK-NEXT:    [[TMP3036:%.*]] = load i64, ptr [[LD]], align 8
21026 // CHECK-NEXT:    [[TMP3037:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3035]], i64 [[TMP3036]] acquire acquire, align 8
21027 // CHECK-NEXT:    [[TMP3038:%.*]] = extractvalue { i64, i1 } [[TMP3037]], 0
21028 // CHECK-NEXT:    [[TMP3039:%.*]] = extractvalue { i64, i1 } [[TMP3037]], 1
21029 // CHECK-NEXT:    br i1 [[TMP3039]], label [[LX_ATOMIC_EXIT297:%.*]], label [[LX_ATOMIC_CONT298:%.*]]
21030 // CHECK:       lx.atomic.cont298:
21031 // CHECK-NEXT:    store i64 [[TMP3038]], ptr [[LV]], align 8
21032 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT297]]
21033 // CHECK:       lx.atomic.exit297:
21034 // CHECK-NEXT:    [[TMP3040:%.*]] = extractvalue { i64, i1 } [[TMP3037]], 1
21035 // CHECK-NEXT:    [[TMP3041:%.*]] = sext i1 [[TMP3040]] to i64
21036 // CHECK-NEXT:    store i64 [[TMP3041]], ptr [[LR]], align 8
21037 // CHECK-NEXT:    [[TMP3042:%.*]] = load i64, ptr [[LE]], align 8
21038 // CHECK-NEXT:    [[TMP3043:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3042]] monotonic, align 8
21039 // CHECK-NEXT:    store i64 [[TMP3043]], ptr [[LV]], align 8
21040 // CHECK-NEXT:    [[TMP3044:%.*]] = load i64, ptr [[LE]], align 8
21041 // CHECK-NEXT:    [[TMP3045:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3044]] monotonic, align 8
21042 // CHECK-NEXT:    store i64 [[TMP3045]], ptr [[LV]], align 8
21043 // CHECK-NEXT:    [[TMP3046:%.*]] = load i64, ptr [[LE]], align 8
21044 // CHECK-NEXT:    [[TMP3047:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3046]] monotonic, align 8
21045 // CHECK-NEXT:    store i64 [[TMP3047]], ptr [[LV]], align 8
21046 // CHECK-NEXT:    [[TMP3048:%.*]] = load i64, ptr [[LE]], align 8
21047 // CHECK-NEXT:    [[TMP3049:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3048]] monotonic, align 8
21048 // CHECK-NEXT:    store i64 [[TMP3049]], ptr [[LV]], align 8
21049 // CHECK-NEXT:    [[TMP3050:%.*]] = load i64, ptr [[LE]], align 8
21050 // CHECK-NEXT:    [[TMP3051:%.*]] = load i64, ptr [[LD]], align 8
21051 // CHECK-NEXT:    [[TMP3052:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3050]], i64 [[TMP3051]] monotonic monotonic, align 8
21052 // CHECK-NEXT:    [[TMP3053:%.*]] = extractvalue { i64, i1 } [[TMP3052]], 0
21053 // CHECK-NEXT:    store i64 [[TMP3053]], ptr [[LV]], align 8
21054 // CHECK-NEXT:    [[TMP3054:%.*]] = load i64, ptr [[LE]], align 8
21055 // CHECK-NEXT:    [[TMP3055:%.*]] = load i64, ptr [[LD]], align 8
21056 // CHECK-NEXT:    [[TMP3056:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3054]], i64 [[TMP3055]] monotonic monotonic, align 8
21057 // CHECK-NEXT:    [[TMP3057:%.*]] = extractvalue { i64, i1 } [[TMP3056]], 0
21058 // CHECK-NEXT:    store i64 [[TMP3057]], ptr [[LV]], align 8
21059 // CHECK-NEXT:    [[TMP3058:%.*]] = load i64, ptr [[LE]], align 8
21060 // CHECK-NEXT:    [[TMP3059:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3058]] monotonic, align 8
21061 // CHECK-NEXT:    [[TMP3060:%.*]] = icmp sgt i64 [[TMP3059]], [[TMP3058]]
21062 // CHECK-NEXT:    [[TMP3061:%.*]] = select i1 [[TMP3060]], i64 [[TMP3058]], i64 [[TMP3059]]
21063 // CHECK-NEXT:    store i64 [[TMP3061]], ptr [[LV]], align 8
21064 // CHECK-NEXT:    [[TMP3062:%.*]] = load i64, ptr [[LE]], align 8
21065 // CHECK-NEXT:    [[TMP3063:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3062]] monotonic, align 8
21066 // CHECK-NEXT:    [[TMP3064:%.*]] = icmp slt i64 [[TMP3063]], [[TMP3062]]
21067 // CHECK-NEXT:    [[TMP3065:%.*]] = select i1 [[TMP3064]], i64 [[TMP3062]], i64 [[TMP3063]]
21068 // CHECK-NEXT:    store i64 [[TMP3065]], ptr [[LV]], align 8
21069 // CHECK-NEXT:    [[TMP3066:%.*]] = load i64, ptr [[LE]], align 8
21070 // CHECK-NEXT:    [[TMP3067:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3066]] monotonic, align 8
21071 // CHECK-NEXT:    [[TMP3068:%.*]] = icmp slt i64 [[TMP3067]], [[TMP3066]]
21072 // CHECK-NEXT:    [[TMP3069:%.*]] = select i1 [[TMP3068]], i64 [[TMP3066]], i64 [[TMP3067]]
21073 // CHECK-NEXT:    store i64 [[TMP3069]], ptr [[LV]], align 8
21074 // CHECK-NEXT:    [[TMP3070:%.*]] = load i64, ptr [[LE]], align 8
21075 // CHECK-NEXT:    [[TMP3071:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3070]] monotonic, align 8
21076 // CHECK-NEXT:    [[TMP3072:%.*]] = icmp sgt i64 [[TMP3071]], [[TMP3070]]
21077 // CHECK-NEXT:    [[TMP3073:%.*]] = select i1 [[TMP3072]], i64 [[TMP3070]], i64 [[TMP3071]]
21078 // CHECK-NEXT:    store i64 [[TMP3073]], ptr [[LV]], align 8
21079 // CHECK-NEXT:    [[TMP3074:%.*]] = load i64, ptr [[LE]], align 8
21080 // CHECK-NEXT:    [[TMP3075:%.*]] = load i64, ptr [[LD]], align 8
21081 // CHECK-NEXT:    [[TMP3076:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3074]], i64 [[TMP3075]] monotonic monotonic, align 8
21082 // CHECK-NEXT:    [[TMP3077:%.*]] = extractvalue { i64, i1 } [[TMP3076]], 0
21083 // CHECK-NEXT:    [[TMP3078:%.*]] = extractvalue { i64, i1 } [[TMP3076]], 1
21084 // CHECK-NEXT:    [[TMP3079:%.*]] = select i1 [[TMP3078]], i64 [[TMP3074]], i64 [[TMP3077]]
21085 // CHECK-NEXT:    store i64 [[TMP3079]], ptr [[LV]], align 8
21086 // CHECK-NEXT:    [[TMP3080:%.*]] = load i64, ptr [[LE]], align 8
21087 // CHECK-NEXT:    [[TMP3081:%.*]] = load i64, ptr [[LD]], align 8
21088 // CHECK-NEXT:    [[TMP3082:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3080]], i64 [[TMP3081]] monotonic monotonic, align 8
21089 // CHECK-NEXT:    [[TMP3083:%.*]] = extractvalue { i64, i1 } [[TMP3082]], 0
21090 // CHECK-NEXT:    [[TMP3084:%.*]] = extractvalue { i64, i1 } [[TMP3082]], 1
21091 // CHECK-NEXT:    [[TMP3085:%.*]] = select i1 [[TMP3084]], i64 [[TMP3080]], i64 [[TMP3083]]
21092 // CHECK-NEXT:    store i64 [[TMP3085]], ptr [[LV]], align 8
21093 // CHECK-NEXT:    [[TMP3086:%.*]] = load i64, ptr [[LE]], align 8
21094 // CHECK-NEXT:    [[TMP3087:%.*]] = load i64, ptr [[LD]], align 8
21095 // CHECK-NEXT:    [[TMP3088:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3086]], i64 [[TMP3087]] monotonic monotonic, align 8
21096 // CHECK-NEXT:    [[TMP3089:%.*]] = extractvalue { i64, i1 } [[TMP3088]], 0
21097 // CHECK-NEXT:    [[TMP3090:%.*]] = extractvalue { i64, i1 } [[TMP3088]], 1
21098 // CHECK-NEXT:    br i1 [[TMP3090]], label [[LX_ATOMIC_EXIT299:%.*]], label [[LX_ATOMIC_CONT300:%.*]]
21099 // CHECK:       lx.atomic.cont300:
21100 // CHECK-NEXT:    store i64 [[TMP3089]], ptr [[LV]], align 8
21101 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT299]]
21102 // CHECK:       lx.atomic.exit299:
21103 // CHECK-NEXT:    [[TMP3091:%.*]] = load i64, ptr [[LE]], align 8
21104 // CHECK-NEXT:    [[TMP3092:%.*]] = load i64, ptr [[LD]], align 8
21105 // CHECK-NEXT:    [[TMP3093:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3091]], i64 [[TMP3092]] monotonic monotonic, align 8
21106 // CHECK-NEXT:    [[TMP3094:%.*]] = extractvalue { i64, i1 } [[TMP3093]], 0
21107 // CHECK-NEXT:    [[TMP3095:%.*]] = extractvalue { i64, i1 } [[TMP3093]], 1
21108 // CHECK-NEXT:    br i1 [[TMP3095]], label [[LX_ATOMIC_EXIT301:%.*]], label [[LX_ATOMIC_CONT302:%.*]]
21109 // CHECK:       lx.atomic.cont302:
21110 // CHECK-NEXT:    store i64 [[TMP3094]], ptr [[LV]], align 8
21111 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT301]]
21112 // CHECK:       lx.atomic.exit301:
21113 // CHECK-NEXT:    [[TMP3096:%.*]] = load i64, ptr [[LE]], align 8
21114 // CHECK-NEXT:    [[TMP3097:%.*]] = load i64, ptr [[LD]], align 8
21115 // CHECK-NEXT:    [[TMP3098:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3096]], i64 [[TMP3097]] monotonic monotonic, align 8
21116 // CHECK-NEXT:    [[TMP3099:%.*]] = extractvalue { i64, i1 } [[TMP3098]], 1
21117 // CHECK-NEXT:    [[TMP3100:%.*]] = sext i1 [[TMP3099]] to i64
21118 // CHECK-NEXT:    store i64 [[TMP3100]], ptr [[LR]], align 8
21119 // CHECK-NEXT:    [[TMP3101:%.*]] = load i64, ptr [[LE]], align 8
21120 // CHECK-NEXT:    [[TMP3102:%.*]] = load i64, ptr [[LD]], align 8
21121 // CHECK-NEXT:    [[TMP3103:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3101]], i64 [[TMP3102]] monotonic monotonic, align 8
21122 // CHECK-NEXT:    [[TMP3104:%.*]] = extractvalue { i64, i1 } [[TMP3103]], 1
21123 // CHECK-NEXT:    [[TMP3105:%.*]] = sext i1 [[TMP3104]] to i64
21124 // CHECK-NEXT:    store i64 [[TMP3105]], ptr [[LR]], align 8
21125 // CHECK-NEXT:    [[TMP3106:%.*]] = load i64, ptr [[LE]], align 8
21126 // CHECK-NEXT:    [[TMP3107:%.*]] = load i64, ptr [[LD]], align 8
21127 // CHECK-NEXT:    [[TMP3108:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3106]], i64 [[TMP3107]] monotonic monotonic, align 8
21128 // CHECK-NEXT:    [[TMP3109:%.*]] = extractvalue { i64, i1 } [[TMP3108]], 0
21129 // CHECK-NEXT:    [[TMP3110:%.*]] = extractvalue { i64, i1 } [[TMP3108]], 1
21130 // CHECK-NEXT:    br i1 [[TMP3110]], label [[LX_ATOMIC_EXIT303:%.*]], label [[LX_ATOMIC_CONT304:%.*]]
21131 // CHECK:       lx.atomic.cont304:
21132 // CHECK-NEXT:    store i64 [[TMP3109]], ptr [[LV]], align 8
21133 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT303]]
21134 // CHECK:       lx.atomic.exit303:
21135 // CHECK-NEXT:    [[TMP3111:%.*]] = extractvalue { i64, i1 } [[TMP3108]], 1
21136 // CHECK-NEXT:    [[TMP3112:%.*]] = sext i1 [[TMP3111]] to i64
21137 // CHECK-NEXT:    store i64 [[TMP3112]], ptr [[LR]], align 8
21138 // CHECK-NEXT:    [[TMP3113:%.*]] = load i64, ptr [[LE]], align 8
21139 // CHECK-NEXT:    [[TMP3114:%.*]] = load i64, ptr [[LD]], align 8
21140 // CHECK-NEXT:    [[TMP3115:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3113]], i64 [[TMP3114]] monotonic monotonic, align 8
21141 // CHECK-NEXT:    [[TMP3116:%.*]] = extractvalue { i64, i1 } [[TMP3115]], 0
21142 // CHECK-NEXT:    [[TMP3117:%.*]] = extractvalue { i64, i1 } [[TMP3115]], 1
21143 // CHECK-NEXT:    br i1 [[TMP3117]], label [[LX_ATOMIC_EXIT305:%.*]], label [[LX_ATOMIC_CONT306:%.*]]
21144 // CHECK:       lx.atomic.cont306:
21145 // CHECK-NEXT:    store i64 [[TMP3116]], ptr [[LV]], align 8
21146 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT305]]
21147 // CHECK:       lx.atomic.exit305:
21148 // CHECK-NEXT:    [[TMP3118:%.*]] = extractvalue { i64, i1 } [[TMP3115]], 1
21149 // CHECK-NEXT:    [[TMP3119:%.*]] = sext i1 [[TMP3118]] to i64
21150 // CHECK-NEXT:    store i64 [[TMP3119]], ptr [[LR]], align 8
21151 // CHECK-NEXT:    [[TMP3120:%.*]] = load i64, ptr [[LE]], align 8
21152 // CHECK-NEXT:    [[TMP3121:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3120]] release, align 8
21153 // CHECK-NEXT:    store i64 [[TMP3121]], ptr [[LV]], align 8
21154 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21155 // CHECK-NEXT:    [[TMP3122:%.*]] = load i64, ptr [[LE]], align 8
21156 // CHECK-NEXT:    [[TMP3123:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3122]] release, align 8
21157 // CHECK-NEXT:    store i64 [[TMP3123]], ptr [[LV]], align 8
21158 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21159 // CHECK-NEXT:    [[TMP3124:%.*]] = load i64, ptr [[LE]], align 8
21160 // CHECK-NEXT:    [[TMP3125:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3124]] release, align 8
21161 // CHECK-NEXT:    store i64 [[TMP3125]], ptr [[LV]], align 8
21162 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21163 // CHECK-NEXT:    [[TMP3126:%.*]] = load i64, ptr [[LE]], align 8
21164 // CHECK-NEXT:    [[TMP3127:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3126]] release, align 8
21165 // CHECK-NEXT:    store i64 [[TMP3127]], ptr [[LV]], align 8
21166 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21167 // CHECK-NEXT:    [[TMP3128:%.*]] = load i64, ptr [[LE]], align 8
21168 // CHECK-NEXT:    [[TMP3129:%.*]] = load i64, ptr [[LD]], align 8
21169 // CHECK-NEXT:    [[TMP3130:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3128]], i64 [[TMP3129]] release monotonic, align 8
21170 // CHECK-NEXT:    [[TMP3131:%.*]] = extractvalue { i64, i1 } [[TMP3130]], 0
21171 // CHECK-NEXT:    store i64 [[TMP3131]], ptr [[LV]], align 8
21172 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21173 // CHECK-NEXT:    [[TMP3132:%.*]] = load i64, ptr [[LE]], align 8
21174 // CHECK-NEXT:    [[TMP3133:%.*]] = load i64, ptr [[LD]], align 8
21175 // CHECK-NEXT:    [[TMP3134:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3132]], i64 [[TMP3133]] release monotonic, align 8
21176 // CHECK-NEXT:    [[TMP3135:%.*]] = extractvalue { i64, i1 } [[TMP3134]], 0
21177 // CHECK-NEXT:    store i64 [[TMP3135]], ptr [[LV]], align 8
21178 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21179 // CHECK-NEXT:    [[TMP3136:%.*]] = load i64, ptr [[LE]], align 8
21180 // CHECK-NEXT:    [[TMP3137:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3136]] release, align 8
21181 // CHECK-NEXT:    [[TMP3138:%.*]] = icmp sgt i64 [[TMP3137]], [[TMP3136]]
21182 // CHECK-NEXT:    [[TMP3139:%.*]] = select i1 [[TMP3138]], i64 [[TMP3136]], i64 [[TMP3137]]
21183 // CHECK-NEXT:    store i64 [[TMP3139]], ptr [[LV]], align 8
21184 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21185 // CHECK-NEXT:    [[TMP3140:%.*]] = load i64, ptr [[LE]], align 8
21186 // CHECK-NEXT:    [[TMP3141:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3140]] release, align 8
21187 // CHECK-NEXT:    [[TMP3142:%.*]] = icmp slt i64 [[TMP3141]], [[TMP3140]]
21188 // CHECK-NEXT:    [[TMP3143:%.*]] = select i1 [[TMP3142]], i64 [[TMP3140]], i64 [[TMP3141]]
21189 // CHECK-NEXT:    store i64 [[TMP3143]], ptr [[LV]], align 8
21190 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21191 // CHECK-NEXT:    [[TMP3144:%.*]] = load i64, ptr [[LE]], align 8
21192 // CHECK-NEXT:    [[TMP3145:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3144]] release, align 8
21193 // CHECK-NEXT:    [[TMP3146:%.*]] = icmp slt i64 [[TMP3145]], [[TMP3144]]
21194 // CHECK-NEXT:    [[TMP3147:%.*]] = select i1 [[TMP3146]], i64 [[TMP3144]], i64 [[TMP3145]]
21195 // CHECK-NEXT:    store i64 [[TMP3147]], ptr [[LV]], align 8
21196 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21197 // CHECK-NEXT:    [[TMP3148:%.*]] = load i64, ptr [[LE]], align 8
21198 // CHECK-NEXT:    [[TMP3149:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3148]] release, align 8
21199 // CHECK-NEXT:    [[TMP3150:%.*]] = icmp sgt i64 [[TMP3149]], [[TMP3148]]
21200 // CHECK-NEXT:    [[TMP3151:%.*]] = select i1 [[TMP3150]], i64 [[TMP3148]], i64 [[TMP3149]]
21201 // CHECK-NEXT:    store i64 [[TMP3151]], ptr [[LV]], align 8
21202 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21203 // CHECK-NEXT:    [[TMP3152:%.*]] = load i64, ptr [[LE]], align 8
21204 // CHECK-NEXT:    [[TMP3153:%.*]] = load i64, ptr [[LD]], align 8
21205 // CHECK-NEXT:    [[TMP3154:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3152]], i64 [[TMP3153]] release monotonic, align 8
21206 // CHECK-NEXT:    [[TMP3155:%.*]] = extractvalue { i64, i1 } [[TMP3154]], 0
21207 // CHECK-NEXT:    [[TMP3156:%.*]] = extractvalue { i64, i1 } [[TMP3154]], 1
21208 // CHECK-NEXT:    [[TMP3157:%.*]] = select i1 [[TMP3156]], i64 [[TMP3152]], i64 [[TMP3155]]
21209 // CHECK-NEXT:    store i64 [[TMP3157]], ptr [[LV]], align 8
21210 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21211 // CHECK-NEXT:    [[TMP3158:%.*]] = load i64, ptr [[LE]], align 8
21212 // CHECK-NEXT:    [[TMP3159:%.*]] = load i64, ptr [[LD]], align 8
21213 // CHECK-NEXT:    [[TMP3160:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3158]], i64 [[TMP3159]] release monotonic, align 8
21214 // CHECK-NEXT:    [[TMP3161:%.*]] = extractvalue { i64, i1 } [[TMP3160]], 0
21215 // CHECK-NEXT:    [[TMP3162:%.*]] = extractvalue { i64, i1 } [[TMP3160]], 1
21216 // CHECK-NEXT:    [[TMP3163:%.*]] = select i1 [[TMP3162]], i64 [[TMP3158]], i64 [[TMP3161]]
21217 // CHECK-NEXT:    store i64 [[TMP3163]], ptr [[LV]], align 8
21218 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21219 // CHECK-NEXT:    [[TMP3164:%.*]] = load i64, ptr [[LE]], align 8
21220 // CHECK-NEXT:    [[TMP3165:%.*]] = load i64, ptr [[LD]], align 8
21221 // CHECK-NEXT:    [[TMP3166:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3164]], i64 [[TMP3165]] release monotonic, align 8
21222 // CHECK-NEXT:    [[TMP3167:%.*]] = extractvalue { i64, i1 } [[TMP3166]], 0
21223 // CHECK-NEXT:    [[TMP3168:%.*]] = extractvalue { i64, i1 } [[TMP3166]], 1
21224 // CHECK-NEXT:    br i1 [[TMP3168]], label [[LX_ATOMIC_EXIT307:%.*]], label [[LX_ATOMIC_CONT308:%.*]]
21225 // CHECK:       lx.atomic.cont308:
21226 // CHECK-NEXT:    store i64 [[TMP3167]], ptr [[LV]], align 8
21227 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT307]]
21228 // CHECK:       lx.atomic.exit307:
21229 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21230 // CHECK-NEXT:    [[TMP3169:%.*]] = load i64, ptr [[LE]], align 8
21231 // CHECK-NEXT:    [[TMP3170:%.*]] = load i64, ptr [[LD]], align 8
21232 // CHECK-NEXT:    [[TMP3171:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3169]], i64 [[TMP3170]] release monotonic, align 8
21233 // CHECK-NEXT:    [[TMP3172:%.*]] = extractvalue { i64, i1 } [[TMP3171]], 0
21234 // CHECK-NEXT:    [[TMP3173:%.*]] = extractvalue { i64, i1 } [[TMP3171]], 1
21235 // CHECK-NEXT:    br i1 [[TMP3173]], label [[LX_ATOMIC_EXIT309:%.*]], label [[LX_ATOMIC_CONT310:%.*]]
21236 // CHECK:       lx.atomic.cont310:
21237 // CHECK-NEXT:    store i64 [[TMP3172]], ptr [[LV]], align 8
21238 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT309]]
21239 // CHECK:       lx.atomic.exit309:
21240 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21241 // CHECK-NEXT:    [[TMP3174:%.*]] = load i64, ptr [[LE]], align 8
21242 // CHECK-NEXT:    [[TMP3175:%.*]] = load i64, ptr [[LD]], align 8
21243 // CHECK-NEXT:    [[TMP3176:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3174]], i64 [[TMP3175]] release monotonic, align 8
21244 // CHECK-NEXT:    [[TMP3177:%.*]] = extractvalue { i64, i1 } [[TMP3176]], 1
21245 // CHECK-NEXT:    [[TMP3178:%.*]] = sext i1 [[TMP3177]] to i64
21246 // CHECK-NEXT:    store i64 [[TMP3178]], ptr [[LR]], align 8
21247 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21248 // CHECK-NEXT:    [[TMP3179:%.*]] = load i64, ptr [[LE]], align 8
21249 // CHECK-NEXT:    [[TMP3180:%.*]] = load i64, ptr [[LD]], align 8
21250 // CHECK-NEXT:    [[TMP3181:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3179]], i64 [[TMP3180]] release monotonic, align 8
21251 // CHECK-NEXT:    [[TMP3182:%.*]] = extractvalue { i64, i1 } [[TMP3181]], 1
21252 // CHECK-NEXT:    [[TMP3183:%.*]] = sext i1 [[TMP3182]] to i64
21253 // CHECK-NEXT:    store i64 [[TMP3183]], ptr [[LR]], align 8
21254 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21255 // CHECK-NEXT:    [[TMP3184:%.*]] = load i64, ptr [[LE]], align 8
21256 // CHECK-NEXT:    [[TMP3185:%.*]] = load i64, ptr [[LD]], align 8
21257 // CHECK-NEXT:    [[TMP3186:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3184]], i64 [[TMP3185]] release monotonic, align 8
21258 // CHECK-NEXT:    [[TMP3187:%.*]] = extractvalue { i64, i1 } [[TMP3186]], 0
21259 // CHECK-NEXT:    [[TMP3188:%.*]] = extractvalue { i64, i1 } [[TMP3186]], 1
21260 // CHECK-NEXT:    br i1 [[TMP3188]], label [[LX_ATOMIC_EXIT311:%.*]], label [[LX_ATOMIC_CONT312:%.*]]
21261 // CHECK:       lx.atomic.cont312:
21262 // CHECK-NEXT:    store i64 [[TMP3187]], ptr [[LV]], align 8
21263 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT311]]
21264 // CHECK:       lx.atomic.exit311:
21265 // CHECK-NEXT:    [[TMP3189:%.*]] = extractvalue { i64, i1 } [[TMP3186]], 1
21266 // CHECK-NEXT:    [[TMP3190:%.*]] = sext i1 [[TMP3189]] to i64
21267 // CHECK-NEXT:    store i64 [[TMP3190]], ptr [[LR]], align 8
21268 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21269 // CHECK-NEXT:    [[TMP3191:%.*]] = load i64, ptr [[LE]], align 8
21270 // CHECK-NEXT:    [[TMP3192:%.*]] = load i64, ptr [[LD]], align 8
21271 // CHECK-NEXT:    [[TMP3193:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3191]], i64 [[TMP3192]] release monotonic, align 8
21272 // CHECK-NEXT:    [[TMP3194:%.*]] = extractvalue { i64, i1 } [[TMP3193]], 0
21273 // CHECK-NEXT:    [[TMP3195:%.*]] = extractvalue { i64, i1 } [[TMP3193]], 1
21274 // CHECK-NEXT:    br i1 [[TMP3195]], label [[LX_ATOMIC_EXIT313:%.*]], label [[LX_ATOMIC_CONT314:%.*]]
21275 // CHECK:       lx.atomic.cont314:
21276 // CHECK-NEXT:    store i64 [[TMP3194]], ptr [[LV]], align 8
21277 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT313]]
21278 // CHECK:       lx.atomic.exit313:
21279 // CHECK-NEXT:    [[TMP3196:%.*]] = extractvalue { i64, i1 } [[TMP3193]], 1
21280 // CHECK-NEXT:    [[TMP3197:%.*]] = sext i1 [[TMP3196]] to i64
21281 // CHECK-NEXT:    store i64 [[TMP3197]], ptr [[LR]], align 8
21282 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21283 // CHECK-NEXT:    [[TMP3198:%.*]] = load i64, ptr [[LE]], align 8
21284 // CHECK-NEXT:    [[TMP3199:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3198]] seq_cst, align 8
21285 // CHECK-NEXT:    store i64 [[TMP3199]], ptr [[LV]], align 8
21286 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21287 // CHECK-NEXT:    [[TMP3200:%.*]] = load i64, ptr [[LE]], align 8
21288 // CHECK-NEXT:    [[TMP3201:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3200]] seq_cst, align 8
21289 // CHECK-NEXT:    store i64 [[TMP3201]], ptr [[LV]], align 8
21290 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21291 // CHECK-NEXT:    [[TMP3202:%.*]] = load i64, ptr [[LE]], align 8
21292 // CHECK-NEXT:    [[TMP3203:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3202]] seq_cst, align 8
21293 // CHECK-NEXT:    store i64 [[TMP3203]], ptr [[LV]], align 8
21294 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21295 // CHECK-NEXT:    [[TMP3204:%.*]] = load i64, ptr [[LE]], align 8
21296 // CHECK-NEXT:    [[TMP3205:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3204]] seq_cst, align 8
21297 // CHECK-NEXT:    store i64 [[TMP3205]], ptr [[LV]], align 8
21298 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21299 // CHECK-NEXT:    [[TMP3206:%.*]] = load i64, ptr [[LE]], align 8
21300 // CHECK-NEXT:    [[TMP3207:%.*]] = load i64, ptr [[LD]], align 8
21301 // CHECK-NEXT:    [[TMP3208:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3206]], i64 [[TMP3207]] seq_cst seq_cst, align 8
21302 // CHECK-NEXT:    [[TMP3209:%.*]] = extractvalue { i64, i1 } [[TMP3208]], 0
21303 // CHECK-NEXT:    store i64 [[TMP3209]], ptr [[LV]], align 8
21304 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21305 // CHECK-NEXT:    [[TMP3210:%.*]] = load i64, ptr [[LE]], align 8
21306 // CHECK-NEXT:    [[TMP3211:%.*]] = load i64, ptr [[LD]], align 8
21307 // CHECK-NEXT:    [[TMP3212:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3210]], i64 [[TMP3211]] seq_cst seq_cst, align 8
21308 // CHECK-NEXT:    [[TMP3213:%.*]] = extractvalue { i64, i1 } [[TMP3212]], 0
21309 // CHECK-NEXT:    store i64 [[TMP3213]], ptr [[LV]], align 8
21310 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21311 // CHECK-NEXT:    [[TMP3214:%.*]] = load i64, ptr [[LE]], align 8
21312 // CHECK-NEXT:    [[TMP3215:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3214]] seq_cst, align 8
21313 // CHECK-NEXT:    [[TMP3216:%.*]] = icmp sgt i64 [[TMP3215]], [[TMP3214]]
21314 // CHECK-NEXT:    [[TMP3217:%.*]] = select i1 [[TMP3216]], i64 [[TMP3214]], i64 [[TMP3215]]
21315 // CHECK-NEXT:    store i64 [[TMP3217]], ptr [[LV]], align 8
21316 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21317 // CHECK-NEXT:    [[TMP3218:%.*]] = load i64, ptr [[LE]], align 8
21318 // CHECK-NEXT:    [[TMP3219:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3218]] seq_cst, align 8
21319 // CHECK-NEXT:    [[TMP3220:%.*]] = icmp slt i64 [[TMP3219]], [[TMP3218]]
21320 // CHECK-NEXT:    [[TMP3221:%.*]] = select i1 [[TMP3220]], i64 [[TMP3218]], i64 [[TMP3219]]
21321 // CHECK-NEXT:    store i64 [[TMP3221]], ptr [[LV]], align 8
21322 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21323 // CHECK-NEXT:    [[TMP3222:%.*]] = load i64, ptr [[LE]], align 8
21324 // CHECK-NEXT:    [[TMP3223:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3222]] seq_cst, align 8
21325 // CHECK-NEXT:    [[TMP3224:%.*]] = icmp slt i64 [[TMP3223]], [[TMP3222]]
21326 // CHECK-NEXT:    [[TMP3225:%.*]] = select i1 [[TMP3224]], i64 [[TMP3222]], i64 [[TMP3223]]
21327 // CHECK-NEXT:    store i64 [[TMP3225]], ptr [[LV]], align 8
21328 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21329 // CHECK-NEXT:    [[TMP3226:%.*]] = load i64, ptr [[LE]], align 8
21330 // CHECK-NEXT:    [[TMP3227:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3226]] seq_cst, align 8
21331 // CHECK-NEXT:    [[TMP3228:%.*]] = icmp sgt i64 [[TMP3227]], [[TMP3226]]
21332 // CHECK-NEXT:    [[TMP3229:%.*]] = select i1 [[TMP3228]], i64 [[TMP3226]], i64 [[TMP3227]]
21333 // CHECK-NEXT:    store i64 [[TMP3229]], ptr [[LV]], align 8
21334 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21335 // CHECK-NEXT:    [[TMP3230:%.*]] = load i64, ptr [[LE]], align 8
21336 // CHECK-NEXT:    [[TMP3231:%.*]] = load i64, ptr [[LD]], align 8
21337 // CHECK-NEXT:    [[TMP3232:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3230]], i64 [[TMP3231]] seq_cst seq_cst, align 8
21338 // CHECK-NEXT:    [[TMP3233:%.*]] = extractvalue { i64, i1 } [[TMP3232]], 0
21339 // CHECK-NEXT:    [[TMP3234:%.*]] = extractvalue { i64, i1 } [[TMP3232]], 1
21340 // CHECK-NEXT:    [[TMP3235:%.*]] = select i1 [[TMP3234]], i64 [[TMP3230]], i64 [[TMP3233]]
21341 // CHECK-NEXT:    store i64 [[TMP3235]], ptr [[LV]], align 8
21342 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21343 // CHECK-NEXT:    [[TMP3236:%.*]] = load i64, ptr [[LE]], align 8
21344 // CHECK-NEXT:    [[TMP3237:%.*]] = load i64, ptr [[LD]], align 8
21345 // CHECK-NEXT:    [[TMP3238:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3236]], i64 [[TMP3237]] seq_cst seq_cst, align 8
21346 // CHECK-NEXT:    [[TMP3239:%.*]] = extractvalue { i64, i1 } [[TMP3238]], 0
21347 // CHECK-NEXT:    [[TMP3240:%.*]] = extractvalue { i64, i1 } [[TMP3238]], 1
21348 // CHECK-NEXT:    [[TMP3241:%.*]] = select i1 [[TMP3240]], i64 [[TMP3236]], i64 [[TMP3239]]
21349 // CHECK-NEXT:    store i64 [[TMP3241]], ptr [[LV]], align 8
21350 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21351 // CHECK-NEXT:    [[TMP3242:%.*]] = load i64, ptr [[LE]], align 8
21352 // CHECK-NEXT:    [[TMP3243:%.*]] = load i64, ptr [[LD]], align 8
21353 // CHECK-NEXT:    [[TMP3244:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3242]], i64 [[TMP3243]] seq_cst seq_cst, align 8
21354 // CHECK-NEXT:    [[TMP3245:%.*]] = extractvalue { i64, i1 } [[TMP3244]], 0
21355 // CHECK-NEXT:    [[TMP3246:%.*]] = extractvalue { i64, i1 } [[TMP3244]], 1
21356 // CHECK-NEXT:    br i1 [[TMP3246]], label [[LX_ATOMIC_EXIT315:%.*]], label [[LX_ATOMIC_CONT316:%.*]]
21357 // CHECK:       lx.atomic.cont316:
21358 // CHECK-NEXT:    store i64 [[TMP3245]], ptr [[LV]], align 8
21359 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT315]]
21360 // CHECK:       lx.atomic.exit315:
21361 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21362 // CHECK-NEXT:    [[TMP3247:%.*]] = load i64, ptr [[LE]], align 8
21363 // CHECK-NEXT:    [[TMP3248:%.*]] = load i64, ptr [[LD]], align 8
21364 // CHECK-NEXT:    [[TMP3249:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3247]], i64 [[TMP3248]] seq_cst seq_cst, align 8
21365 // CHECK-NEXT:    [[TMP3250:%.*]] = extractvalue { i64, i1 } [[TMP3249]], 0
21366 // CHECK-NEXT:    [[TMP3251:%.*]] = extractvalue { i64, i1 } [[TMP3249]], 1
21367 // CHECK-NEXT:    br i1 [[TMP3251]], label [[LX_ATOMIC_EXIT317:%.*]], label [[LX_ATOMIC_CONT318:%.*]]
21368 // CHECK:       lx.atomic.cont318:
21369 // CHECK-NEXT:    store i64 [[TMP3250]], ptr [[LV]], align 8
21370 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT317]]
21371 // CHECK:       lx.atomic.exit317:
21372 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21373 // CHECK-NEXT:    [[TMP3252:%.*]] = load i64, ptr [[LE]], align 8
21374 // CHECK-NEXT:    [[TMP3253:%.*]] = load i64, ptr [[LD]], align 8
21375 // CHECK-NEXT:    [[TMP3254:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3252]], i64 [[TMP3253]] seq_cst seq_cst, align 8
21376 // CHECK-NEXT:    [[TMP3255:%.*]] = extractvalue { i64, i1 } [[TMP3254]], 1
21377 // CHECK-NEXT:    [[TMP3256:%.*]] = sext i1 [[TMP3255]] to i64
21378 // CHECK-NEXT:    store i64 [[TMP3256]], ptr [[LR]], align 8
21379 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21380 // CHECK-NEXT:    [[TMP3257:%.*]] = load i64, ptr [[LE]], align 8
21381 // CHECK-NEXT:    [[TMP3258:%.*]] = load i64, ptr [[LD]], align 8
21382 // CHECK-NEXT:    [[TMP3259:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3257]], i64 [[TMP3258]] seq_cst seq_cst, align 8
21383 // CHECK-NEXT:    [[TMP3260:%.*]] = extractvalue { i64, i1 } [[TMP3259]], 1
21384 // CHECK-NEXT:    [[TMP3261:%.*]] = sext i1 [[TMP3260]] to i64
21385 // CHECK-NEXT:    store i64 [[TMP3261]], ptr [[LR]], align 8
21386 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21387 // CHECK-NEXT:    [[TMP3262:%.*]] = load i64, ptr [[LE]], align 8
21388 // CHECK-NEXT:    [[TMP3263:%.*]] = load i64, ptr [[LD]], align 8
21389 // CHECK-NEXT:    [[TMP3264:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3262]], i64 [[TMP3263]] seq_cst seq_cst, align 8
21390 // CHECK-NEXT:    [[TMP3265:%.*]] = extractvalue { i64, i1 } [[TMP3264]], 0
21391 // CHECK-NEXT:    [[TMP3266:%.*]] = extractvalue { i64, i1 } [[TMP3264]], 1
21392 // CHECK-NEXT:    br i1 [[TMP3266]], label [[LX_ATOMIC_EXIT319:%.*]], label [[LX_ATOMIC_CONT320:%.*]]
21393 // CHECK:       lx.atomic.cont320:
21394 // CHECK-NEXT:    store i64 [[TMP3265]], ptr [[LV]], align 8
21395 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT319]]
21396 // CHECK:       lx.atomic.exit319:
21397 // CHECK-NEXT:    [[TMP3267:%.*]] = extractvalue { i64, i1 } [[TMP3264]], 1
21398 // CHECK-NEXT:    [[TMP3268:%.*]] = sext i1 [[TMP3267]] to i64
21399 // CHECK-NEXT:    store i64 [[TMP3268]], ptr [[LR]], align 8
21400 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21401 // CHECK-NEXT:    [[TMP3269:%.*]] = load i64, ptr [[LE]], align 8
21402 // CHECK-NEXT:    [[TMP3270:%.*]] = load i64, ptr [[LD]], align 8
21403 // CHECK-NEXT:    [[TMP3271:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3269]], i64 [[TMP3270]] seq_cst seq_cst, align 8
21404 // CHECK-NEXT:    [[TMP3272:%.*]] = extractvalue { i64, i1 } [[TMP3271]], 0
21405 // CHECK-NEXT:    [[TMP3273:%.*]] = extractvalue { i64, i1 } [[TMP3271]], 1
21406 // CHECK-NEXT:    br i1 [[TMP3273]], label [[LX_ATOMIC_EXIT321:%.*]], label [[LX_ATOMIC_CONT322:%.*]]
21407 // CHECK:       lx.atomic.cont322:
21408 // CHECK-NEXT:    store i64 [[TMP3272]], ptr [[LV]], align 8
21409 // CHECK-NEXT:    br label [[LX_ATOMIC_EXIT321]]
21410 // CHECK:       lx.atomic.exit321:
21411 // CHECK-NEXT:    [[TMP3274:%.*]] = extractvalue { i64, i1 } [[TMP3271]], 1
21412 // CHECK-NEXT:    [[TMP3275:%.*]] = sext i1 [[TMP3274]] to i64
21413 // CHECK-NEXT:    store i64 [[TMP3275]], ptr [[LR]], align 8
21414 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21415 // CHECK-NEXT:    [[TMP3276:%.*]] = load i64, ptr [[ULE]], align 8
21416 // CHECK-NEXT:    [[TMP3277:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3276]] monotonic, align 8
21417 // CHECK-NEXT:    store i64 [[TMP3277]], ptr [[ULV]], align 8
21418 // CHECK-NEXT:    [[TMP3278:%.*]] = load i64, ptr [[ULE]], align 8
21419 // CHECK-NEXT:    [[TMP3279:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3278]] monotonic, align 8
21420 // CHECK-NEXT:    store i64 [[TMP3279]], ptr [[ULV]], align 8
21421 // CHECK-NEXT:    [[TMP3280:%.*]] = load i64, ptr [[ULE]], align 8
21422 // CHECK-NEXT:    [[TMP3281:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3280]] monotonic, align 8
21423 // CHECK-NEXT:    store i64 [[TMP3281]], ptr [[ULV]], align 8
21424 // CHECK-NEXT:    [[TMP3282:%.*]] = load i64, ptr [[ULE]], align 8
21425 // CHECK-NEXT:    [[TMP3283:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3282]] monotonic, align 8
21426 // CHECK-NEXT:    store i64 [[TMP3283]], ptr [[ULV]], align 8
21427 // CHECK-NEXT:    [[TMP3284:%.*]] = load i64, ptr [[ULE]], align 8
21428 // CHECK-NEXT:    [[TMP3285:%.*]] = load i64, ptr [[ULD]], align 8
21429 // CHECK-NEXT:    [[TMP3286:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3284]], i64 [[TMP3285]] monotonic monotonic, align 8
21430 // CHECK-NEXT:    [[TMP3287:%.*]] = extractvalue { i64, i1 } [[TMP3286]], 0
21431 // CHECK-NEXT:    store i64 [[TMP3287]], ptr [[ULV]], align 8
21432 // CHECK-NEXT:    [[TMP3288:%.*]] = load i64, ptr [[ULE]], align 8
21433 // CHECK-NEXT:    [[TMP3289:%.*]] = load i64, ptr [[ULD]], align 8
21434 // CHECK-NEXT:    [[TMP3290:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3288]], i64 [[TMP3289]] monotonic monotonic, align 8
21435 // CHECK-NEXT:    [[TMP3291:%.*]] = extractvalue { i64, i1 } [[TMP3290]], 0
21436 // CHECK-NEXT:    store i64 [[TMP3291]], ptr [[ULV]], align 8
21437 // CHECK-NEXT:    [[TMP3292:%.*]] = load i64, ptr [[ULE]], align 8
21438 // CHECK-NEXT:    [[TMP3293:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3292]] monotonic, align 8
21439 // CHECK-NEXT:    [[TMP3294:%.*]] = icmp ugt i64 [[TMP3293]], [[TMP3292]]
21440 // CHECK-NEXT:    [[TMP3295:%.*]] = select i1 [[TMP3294]], i64 [[TMP3292]], i64 [[TMP3293]]
21441 // CHECK-NEXT:    store i64 [[TMP3295]], ptr [[ULV]], align 8
21442 // CHECK-NEXT:    [[TMP3296:%.*]] = load i64, ptr [[ULE]], align 8
21443 // CHECK-NEXT:    [[TMP3297:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3296]] monotonic, align 8
21444 // CHECK-NEXT:    [[TMP3298:%.*]] = icmp ult i64 [[TMP3297]], [[TMP3296]]
21445 // CHECK-NEXT:    [[TMP3299:%.*]] = select i1 [[TMP3298]], i64 [[TMP3296]], i64 [[TMP3297]]
21446 // CHECK-NEXT:    store i64 [[TMP3299]], ptr [[ULV]], align 8
21447 // CHECK-NEXT:    [[TMP3300:%.*]] = load i64, ptr [[ULE]], align 8
21448 // CHECK-NEXT:    [[TMP3301:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3300]] monotonic, align 8
21449 // CHECK-NEXT:    [[TMP3302:%.*]] = icmp ult i64 [[TMP3301]], [[TMP3300]]
21450 // CHECK-NEXT:    [[TMP3303:%.*]] = select i1 [[TMP3302]], i64 [[TMP3300]], i64 [[TMP3301]]
21451 // CHECK-NEXT:    store i64 [[TMP3303]], ptr [[ULV]], align 8
21452 // CHECK-NEXT:    [[TMP3304:%.*]] = load i64, ptr [[ULE]], align 8
21453 // CHECK-NEXT:    [[TMP3305:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3304]] monotonic, align 8
21454 // CHECK-NEXT:    [[TMP3306:%.*]] = icmp ugt i64 [[TMP3305]], [[TMP3304]]
21455 // CHECK-NEXT:    [[TMP3307:%.*]] = select i1 [[TMP3306]], i64 [[TMP3304]], i64 [[TMP3305]]
21456 // CHECK-NEXT:    store i64 [[TMP3307]], ptr [[ULV]], align 8
21457 // CHECK-NEXT:    [[TMP3308:%.*]] = load i64, ptr [[ULE]], align 8
21458 // CHECK-NEXT:    [[TMP3309:%.*]] = load i64, ptr [[ULD]], align 8
21459 // CHECK-NEXT:    [[TMP3310:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3308]], i64 [[TMP3309]] monotonic monotonic, align 8
21460 // CHECK-NEXT:    [[TMP3311:%.*]] = extractvalue { i64, i1 } [[TMP3310]], 0
21461 // CHECK-NEXT:    [[TMP3312:%.*]] = extractvalue { i64, i1 } [[TMP3310]], 1
21462 // CHECK-NEXT:    [[TMP3313:%.*]] = select i1 [[TMP3312]], i64 [[TMP3308]], i64 [[TMP3311]]
21463 // CHECK-NEXT:    store i64 [[TMP3313]], ptr [[ULV]], align 8
21464 // CHECK-NEXT:    [[TMP3314:%.*]] = load i64, ptr [[ULE]], align 8
21465 // CHECK-NEXT:    [[TMP3315:%.*]] = load i64, ptr [[ULD]], align 8
21466 // CHECK-NEXT:    [[TMP3316:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3314]], i64 [[TMP3315]] monotonic monotonic, align 8
21467 // CHECK-NEXT:    [[TMP3317:%.*]] = extractvalue { i64, i1 } [[TMP3316]], 0
21468 // CHECK-NEXT:    [[TMP3318:%.*]] = extractvalue { i64, i1 } [[TMP3316]], 1
21469 // CHECK-NEXT:    [[TMP3319:%.*]] = select i1 [[TMP3318]], i64 [[TMP3314]], i64 [[TMP3317]]
21470 // CHECK-NEXT:    store i64 [[TMP3319]], ptr [[ULV]], align 8
21471 // CHECK-NEXT:    [[TMP3320:%.*]] = load i64, ptr [[ULE]], align 8
21472 // CHECK-NEXT:    [[TMP3321:%.*]] = load i64, ptr [[ULD]], align 8
21473 // CHECK-NEXT:    [[TMP3322:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3320]], i64 [[TMP3321]] monotonic monotonic, align 8
21474 // CHECK-NEXT:    [[TMP3323:%.*]] = extractvalue { i64, i1 } [[TMP3322]], 0
21475 // CHECK-NEXT:    [[TMP3324:%.*]] = extractvalue { i64, i1 } [[TMP3322]], 1
21476 // CHECK-NEXT:    br i1 [[TMP3324]], label [[ULX_ATOMIC_EXIT:%.*]], label [[ULX_ATOMIC_CONT:%.*]]
21477 // CHECK:       ulx.atomic.cont:
21478 // CHECK-NEXT:    store i64 [[TMP3323]], ptr [[ULV]], align 8
21479 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT]]
21480 // CHECK:       ulx.atomic.exit:
21481 // CHECK-NEXT:    [[TMP3325:%.*]] = load i64, ptr [[ULE]], align 8
21482 // CHECK-NEXT:    [[TMP3326:%.*]] = load i64, ptr [[ULD]], align 8
21483 // CHECK-NEXT:    [[TMP3327:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3325]], i64 [[TMP3326]] monotonic monotonic, align 8
21484 // CHECK-NEXT:    [[TMP3328:%.*]] = extractvalue { i64, i1 } [[TMP3327]], 0
21485 // CHECK-NEXT:    [[TMP3329:%.*]] = extractvalue { i64, i1 } [[TMP3327]], 1
21486 // CHECK-NEXT:    br i1 [[TMP3329]], label [[ULX_ATOMIC_EXIT323:%.*]], label [[ULX_ATOMIC_CONT324:%.*]]
21487 // CHECK:       ulx.atomic.cont324:
21488 // CHECK-NEXT:    store i64 [[TMP3328]], ptr [[ULV]], align 8
21489 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT323]]
21490 // CHECK:       ulx.atomic.exit323:
21491 // CHECK-NEXT:    [[TMP3330:%.*]] = load i64, ptr [[ULE]], align 8
21492 // CHECK-NEXT:    [[TMP3331:%.*]] = load i64, ptr [[ULD]], align 8
21493 // CHECK-NEXT:    [[TMP3332:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3330]], i64 [[TMP3331]] monotonic monotonic, align 8
21494 // CHECK-NEXT:    [[TMP3333:%.*]] = extractvalue { i64, i1 } [[TMP3332]], 1
21495 // CHECK-NEXT:    [[TMP3334:%.*]] = zext i1 [[TMP3333]] to i64
21496 // CHECK-NEXT:    store i64 [[TMP3334]], ptr [[ULR]], align 8
21497 // CHECK-NEXT:    [[TMP3335:%.*]] = load i64, ptr [[ULE]], align 8
21498 // CHECK-NEXT:    [[TMP3336:%.*]] = load i64, ptr [[ULD]], align 8
21499 // CHECK-NEXT:    [[TMP3337:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3335]], i64 [[TMP3336]] monotonic monotonic, align 8
21500 // CHECK-NEXT:    [[TMP3338:%.*]] = extractvalue { i64, i1 } [[TMP3337]], 1
21501 // CHECK-NEXT:    [[TMP3339:%.*]] = zext i1 [[TMP3338]] to i64
21502 // CHECK-NEXT:    store i64 [[TMP3339]], ptr [[ULR]], align 8
21503 // CHECK-NEXT:    [[TMP3340:%.*]] = load i64, ptr [[ULE]], align 8
21504 // CHECK-NEXT:    [[TMP3341:%.*]] = load i64, ptr [[ULD]], align 8
21505 // CHECK-NEXT:    [[TMP3342:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3340]], i64 [[TMP3341]] monotonic monotonic, align 8
21506 // CHECK-NEXT:    [[TMP3343:%.*]] = extractvalue { i64, i1 } [[TMP3342]], 0
21507 // CHECK-NEXT:    [[TMP3344:%.*]] = extractvalue { i64, i1 } [[TMP3342]], 1
21508 // CHECK-NEXT:    br i1 [[TMP3344]], label [[ULX_ATOMIC_EXIT325:%.*]], label [[ULX_ATOMIC_CONT326:%.*]]
21509 // CHECK:       ulx.atomic.cont326:
21510 // CHECK-NEXT:    store i64 [[TMP3343]], ptr [[ULV]], align 8
21511 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT325]]
21512 // CHECK:       ulx.atomic.exit325:
21513 // CHECK-NEXT:    [[TMP3345:%.*]] = extractvalue { i64, i1 } [[TMP3342]], 1
21514 // CHECK-NEXT:    [[TMP3346:%.*]] = zext i1 [[TMP3345]] to i64
21515 // CHECK-NEXT:    store i64 [[TMP3346]], ptr [[ULR]], align 8
21516 // CHECK-NEXT:    [[TMP3347:%.*]] = load i64, ptr [[ULE]], align 8
21517 // CHECK-NEXT:    [[TMP3348:%.*]] = load i64, ptr [[ULD]], align 8
21518 // CHECK-NEXT:    [[TMP3349:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3347]], i64 [[TMP3348]] monotonic monotonic, align 8
21519 // CHECK-NEXT:    [[TMP3350:%.*]] = extractvalue { i64, i1 } [[TMP3349]], 0
21520 // CHECK-NEXT:    [[TMP3351:%.*]] = extractvalue { i64, i1 } [[TMP3349]], 1
21521 // CHECK-NEXT:    br i1 [[TMP3351]], label [[ULX_ATOMIC_EXIT327:%.*]], label [[ULX_ATOMIC_CONT328:%.*]]
21522 // CHECK:       ulx.atomic.cont328:
21523 // CHECK-NEXT:    store i64 [[TMP3350]], ptr [[ULV]], align 8
21524 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT327]]
21525 // CHECK:       ulx.atomic.exit327:
21526 // CHECK-NEXT:    [[TMP3352:%.*]] = extractvalue { i64, i1 } [[TMP3349]], 1
21527 // CHECK-NEXT:    [[TMP3353:%.*]] = zext i1 [[TMP3352]] to i64
21528 // CHECK-NEXT:    store i64 [[TMP3353]], ptr [[ULR]], align 8
21529 // CHECK-NEXT:    [[TMP3354:%.*]] = load i64, ptr [[ULE]], align 8
21530 // CHECK-NEXT:    [[TMP3355:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3354]] acq_rel, align 8
21531 // CHECK-NEXT:    store i64 [[TMP3355]], ptr [[ULV]], align 8
21532 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21533 // CHECK-NEXT:    [[TMP3356:%.*]] = load i64, ptr [[ULE]], align 8
21534 // CHECK-NEXT:    [[TMP3357:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3356]] acq_rel, align 8
21535 // CHECK-NEXT:    store i64 [[TMP3357]], ptr [[ULV]], align 8
21536 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21537 // CHECK-NEXT:    [[TMP3358:%.*]] = load i64, ptr [[ULE]], align 8
21538 // CHECK-NEXT:    [[TMP3359:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3358]] acq_rel, align 8
21539 // CHECK-NEXT:    store i64 [[TMP3359]], ptr [[ULV]], align 8
21540 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21541 // CHECK-NEXT:    [[TMP3360:%.*]] = load i64, ptr [[ULE]], align 8
21542 // CHECK-NEXT:    [[TMP3361:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3360]] acq_rel, align 8
21543 // CHECK-NEXT:    store i64 [[TMP3361]], ptr [[ULV]], align 8
21544 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21545 // CHECK-NEXT:    [[TMP3362:%.*]] = load i64, ptr [[ULE]], align 8
21546 // CHECK-NEXT:    [[TMP3363:%.*]] = load i64, ptr [[ULD]], align 8
21547 // CHECK-NEXT:    [[TMP3364:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3362]], i64 [[TMP3363]] acq_rel acquire, align 8
21548 // CHECK-NEXT:    [[TMP3365:%.*]] = extractvalue { i64, i1 } [[TMP3364]], 0
21549 // CHECK-NEXT:    store i64 [[TMP3365]], ptr [[ULV]], align 8
21550 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21551 // CHECK-NEXT:    [[TMP3366:%.*]] = load i64, ptr [[ULE]], align 8
21552 // CHECK-NEXT:    [[TMP3367:%.*]] = load i64, ptr [[ULD]], align 8
21553 // CHECK-NEXT:    [[TMP3368:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3366]], i64 [[TMP3367]] acq_rel acquire, align 8
21554 // CHECK-NEXT:    [[TMP3369:%.*]] = extractvalue { i64, i1 } [[TMP3368]], 0
21555 // CHECK-NEXT:    store i64 [[TMP3369]], ptr [[ULV]], align 8
21556 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21557 // CHECK-NEXT:    [[TMP3370:%.*]] = load i64, ptr [[ULE]], align 8
21558 // CHECK-NEXT:    [[TMP3371:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3370]] acq_rel, align 8
21559 // CHECK-NEXT:    [[TMP3372:%.*]] = icmp ugt i64 [[TMP3371]], [[TMP3370]]
21560 // CHECK-NEXT:    [[TMP3373:%.*]] = select i1 [[TMP3372]], i64 [[TMP3370]], i64 [[TMP3371]]
21561 // CHECK-NEXT:    store i64 [[TMP3373]], ptr [[ULV]], align 8
21562 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21563 // CHECK-NEXT:    [[TMP3374:%.*]] = load i64, ptr [[ULE]], align 8
21564 // CHECK-NEXT:    [[TMP3375:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3374]] acq_rel, align 8
21565 // CHECK-NEXT:    [[TMP3376:%.*]] = icmp ult i64 [[TMP3375]], [[TMP3374]]
21566 // CHECK-NEXT:    [[TMP3377:%.*]] = select i1 [[TMP3376]], i64 [[TMP3374]], i64 [[TMP3375]]
21567 // CHECK-NEXT:    store i64 [[TMP3377]], ptr [[ULV]], align 8
21568 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21569 // CHECK-NEXT:    [[TMP3378:%.*]] = load i64, ptr [[ULE]], align 8
21570 // CHECK-NEXT:    [[TMP3379:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3378]] acq_rel, align 8
21571 // CHECK-NEXT:    [[TMP3380:%.*]] = icmp ult i64 [[TMP3379]], [[TMP3378]]
21572 // CHECK-NEXT:    [[TMP3381:%.*]] = select i1 [[TMP3380]], i64 [[TMP3378]], i64 [[TMP3379]]
21573 // CHECK-NEXT:    store i64 [[TMP3381]], ptr [[ULV]], align 8
21574 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21575 // CHECK-NEXT:    [[TMP3382:%.*]] = load i64, ptr [[ULE]], align 8
21576 // CHECK-NEXT:    [[TMP3383:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3382]] acq_rel, align 8
21577 // CHECK-NEXT:    [[TMP3384:%.*]] = icmp ugt i64 [[TMP3383]], [[TMP3382]]
21578 // CHECK-NEXT:    [[TMP3385:%.*]] = select i1 [[TMP3384]], i64 [[TMP3382]], i64 [[TMP3383]]
21579 // CHECK-NEXT:    store i64 [[TMP3385]], ptr [[ULV]], align 8
21580 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21581 // CHECK-NEXT:    [[TMP3386:%.*]] = load i64, ptr [[ULE]], align 8
21582 // CHECK-NEXT:    [[TMP3387:%.*]] = load i64, ptr [[ULD]], align 8
21583 // CHECK-NEXT:    [[TMP3388:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3386]], i64 [[TMP3387]] acq_rel acquire, align 8
21584 // CHECK-NEXT:    [[TMP3389:%.*]] = extractvalue { i64, i1 } [[TMP3388]], 0
21585 // CHECK-NEXT:    [[TMP3390:%.*]] = extractvalue { i64, i1 } [[TMP3388]], 1
21586 // CHECK-NEXT:    [[TMP3391:%.*]] = select i1 [[TMP3390]], i64 [[TMP3386]], i64 [[TMP3389]]
21587 // CHECK-NEXT:    store i64 [[TMP3391]], ptr [[ULV]], align 8
21588 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21589 // CHECK-NEXT:    [[TMP3392:%.*]] = load i64, ptr [[ULE]], align 8
21590 // CHECK-NEXT:    [[TMP3393:%.*]] = load i64, ptr [[ULD]], align 8
21591 // CHECK-NEXT:    [[TMP3394:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3392]], i64 [[TMP3393]] acq_rel acquire, align 8
21592 // CHECK-NEXT:    [[TMP3395:%.*]] = extractvalue { i64, i1 } [[TMP3394]], 0
21593 // CHECK-NEXT:    [[TMP3396:%.*]] = extractvalue { i64, i1 } [[TMP3394]], 1
21594 // CHECK-NEXT:    [[TMP3397:%.*]] = select i1 [[TMP3396]], i64 [[TMP3392]], i64 [[TMP3395]]
21595 // CHECK-NEXT:    store i64 [[TMP3397]], ptr [[ULV]], align 8
21596 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21597 // CHECK-NEXT:    [[TMP3398:%.*]] = load i64, ptr [[ULE]], align 8
21598 // CHECK-NEXT:    [[TMP3399:%.*]] = load i64, ptr [[ULD]], align 8
21599 // CHECK-NEXT:    [[TMP3400:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3398]], i64 [[TMP3399]] acq_rel acquire, align 8
21600 // CHECK-NEXT:    [[TMP3401:%.*]] = extractvalue { i64, i1 } [[TMP3400]], 0
21601 // CHECK-NEXT:    [[TMP3402:%.*]] = extractvalue { i64, i1 } [[TMP3400]], 1
21602 // CHECK-NEXT:    br i1 [[TMP3402]], label [[ULX_ATOMIC_EXIT329:%.*]], label [[ULX_ATOMIC_CONT330:%.*]]
21603 // CHECK:       ulx.atomic.cont330:
21604 // CHECK-NEXT:    store i64 [[TMP3401]], ptr [[ULV]], align 8
21605 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT329]]
21606 // CHECK:       ulx.atomic.exit329:
21607 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21608 // CHECK-NEXT:    [[TMP3403:%.*]] = load i64, ptr [[ULE]], align 8
21609 // CHECK-NEXT:    [[TMP3404:%.*]] = load i64, ptr [[ULD]], align 8
21610 // CHECK-NEXT:    [[TMP3405:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3403]], i64 [[TMP3404]] acq_rel acquire, align 8
21611 // CHECK-NEXT:    [[TMP3406:%.*]] = extractvalue { i64, i1 } [[TMP3405]], 0
21612 // CHECK-NEXT:    [[TMP3407:%.*]] = extractvalue { i64, i1 } [[TMP3405]], 1
21613 // CHECK-NEXT:    br i1 [[TMP3407]], label [[ULX_ATOMIC_EXIT331:%.*]], label [[ULX_ATOMIC_CONT332:%.*]]
21614 // CHECK:       ulx.atomic.cont332:
21615 // CHECK-NEXT:    store i64 [[TMP3406]], ptr [[ULV]], align 8
21616 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT331]]
21617 // CHECK:       ulx.atomic.exit331:
21618 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21619 // CHECK-NEXT:    [[TMP3408:%.*]] = load i64, ptr [[ULE]], align 8
21620 // CHECK-NEXT:    [[TMP3409:%.*]] = load i64, ptr [[ULD]], align 8
21621 // CHECK-NEXT:    [[TMP3410:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3408]], i64 [[TMP3409]] acq_rel acquire, align 8
21622 // CHECK-NEXT:    [[TMP3411:%.*]] = extractvalue { i64, i1 } [[TMP3410]], 1
21623 // CHECK-NEXT:    [[TMP3412:%.*]] = zext i1 [[TMP3411]] to i64
21624 // CHECK-NEXT:    store i64 [[TMP3412]], ptr [[ULR]], align 8
21625 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21626 // CHECK-NEXT:    [[TMP3413:%.*]] = load i64, ptr [[ULE]], align 8
21627 // CHECK-NEXT:    [[TMP3414:%.*]] = load i64, ptr [[ULD]], align 8
21628 // CHECK-NEXT:    [[TMP3415:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3413]], i64 [[TMP3414]] acq_rel acquire, align 8
21629 // CHECK-NEXT:    [[TMP3416:%.*]] = extractvalue { i64, i1 } [[TMP3415]], 1
21630 // CHECK-NEXT:    [[TMP3417:%.*]] = zext i1 [[TMP3416]] to i64
21631 // CHECK-NEXT:    store i64 [[TMP3417]], ptr [[ULR]], align 8
21632 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21633 // CHECK-NEXT:    [[TMP3418:%.*]] = load i64, ptr [[ULE]], align 8
21634 // CHECK-NEXT:    [[TMP3419:%.*]] = load i64, ptr [[ULD]], align 8
21635 // CHECK-NEXT:    [[TMP3420:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3418]], i64 [[TMP3419]] acq_rel acquire, align 8
21636 // CHECK-NEXT:    [[TMP3421:%.*]] = extractvalue { i64, i1 } [[TMP3420]], 0
21637 // CHECK-NEXT:    [[TMP3422:%.*]] = extractvalue { i64, i1 } [[TMP3420]], 1
21638 // CHECK-NEXT:    br i1 [[TMP3422]], label [[ULX_ATOMIC_EXIT333:%.*]], label [[ULX_ATOMIC_CONT334:%.*]]
21639 // CHECK:       ulx.atomic.cont334:
21640 // CHECK-NEXT:    store i64 [[TMP3421]], ptr [[ULV]], align 8
21641 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT333]]
21642 // CHECK:       ulx.atomic.exit333:
21643 // CHECK-NEXT:    [[TMP3423:%.*]] = extractvalue { i64, i1 } [[TMP3420]], 1
21644 // CHECK-NEXT:    [[TMP3424:%.*]] = zext i1 [[TMP3423]] to i64
21645 // CHECK-NEXT:    store i64 [[TMP3424]], ptr [[ULR]], align 8
21646 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21647 // CHECK-NEXT:    [[TMP3425:%.*]] = load i64, ptr [[ULE]], align 8
21648 // CHECK-NEXT:    [[TMP3426:%.*]] = load i64, ptr [[ULD]], align 8
21649 // CHECK-NEXT:    [[TMP3427:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3425]], i64 [[TMP3426]] acq_rel acquire, align 8
21650 // CHECK-NEXT:    [[TMP3428:%.*]] = extractvalue { i64, i1 } [[TMP3427]], 0
21651 // CHECK-NEXT:    [[TMP3429:%.*]] = extractvalue { i64, i1 } [[TMP3427]], 1
21652 // CHECK-NEXT:    br i1 [[TMP3429]], label [[ULX_ATOMIC_EXIT335:%.*]], label [[ULX_ATOMIC_CONT336:%.*]]
21653 // CHECK:       ulx.atomic.cont336:
21654 // CHECK-NEXT:    store i64 [[TMP3428]], ptr [[ULV]], align 8
21655 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT335]]
21656 // CHECK:       ulx.atomic.exit335:
21657 // CHECK-NEXT:    [[TMP3430:%.*]] = extractvalue { i64, i1 } [[TMP3427]], 1
21658 // CHECK-NEXT:    [[TMP3431:%.*]] = zext i1 [[TMP3430]] to i64
21659 // CHECK-NEXT:    store i64 [[TMP3431]], ptr [[ULR]], align 8
21660 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21661 // CHECK-NEXT:    [[TMP3432:%.*]] = load i64, ptr [[ULE]], align 8
21662 // CHECK-NEXT:    [[TMP3433:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3432]] acquire, align 8
21663 // CHECK-NEXT:    store i64 [[TMP3433]], ptr [[ULV]], align 8
21664 // CHECK-NEXT:    [[TMP3434:%.*]] = load i64, ptr [[ULE]], align 8
21665 // CHECK-NEXT:    [[TMP3435:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3434]] acquire, align 8
21666 // CHECK-NEXT:    store i64 [[TMP3435]], ptr [[ULV]], align 8
21667 // CHECK-NEXT:    [[TMP3436:%.*]] = load i64, ptr [[ULE]], align 8
21668 // CHECK-NEXT:    [[TMP3437:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3436]] acquire, align 8
21669 // CHECK-NEXT:    store i64 [[TMP3437]], ptr [[ULV]], align 8
21670 // CHECK-NEXT:    [[TMP3438:%.*]] = load i64, ptr [[ULE]], align 8
21671 // CHECK-NEXT:    [[TMP3439:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3438]] acquire, align 8
21672 // CHECK-NEXT:    store i64 [[TMP3439]], ptr [[ULV]], align 8
21673 // CHECK-NEXT:    [[TMP3440:%.*]] = load i64, ptr [[ULE]], align 8
21674 // CHECK-NEXT:    [[TMP3441:%.*]] = load i64, ptr [[ULD]], align 8
21675 // CHECK-NEXT:    [[TMP3442:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3440]], i64 [[TMP3441]] acquire acquire, align 8
21676 // CHECK-NEXT:    [[TMP3443:%.*]] = extractvalue { i64, i1 } [[TMP3442]], 0
21677 // CHECK-NEXT:    store i64 [[TMP3443]], ptr [[ULV]], align 8
21678 // CHECK-NEXT:    [[TMP3444:%.*]] = load i64, ptr [[ULE]], align 8
21679 // CHECK-NEXT:    [[TMP3445:%.*]] = load i64, ptr [[ULD]], align 8
21680 // CHECK-NEXT:    [[TMP3446:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3444]], i64 [[TMP3445]] acquire acquire, align 8
21681 // CHECK-NEXT:    [[TMP3447:%.*]] = extractvalue { i64, i1 } [[TMP3446]], 0
21682 // CHECK-NEXT:    store i64 [[TMP3447]], ptr [[ULV]], align 8
21683 // CHECK-NEXT:    [[TMP3448:%.*]] = load i64, ptr [[ULE]], align 8
21684 // CHECK-NEXT:    [[TMP3449:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3448]] acquire, align 8
21685 // CHECK-NEXT:    [[TMP3450:%.*]] = icmp ugt i64 [[TMP3449]], [[TMP3448]]
21686 // CHECK-NEXT:    [[TMP3451:%.*]] = select i1 [[TMP3450]], i64 [[TMP3448]], i64 [[TMP3449]]
21687 // CHECK-NEXT:    store i64 [[TMP3451]], ptr [[ULV]], align 8
21688 // CHECK-NEXT:    [[TMP3452:%.*]] = load i64, ptr [[ULE]], align 8
21689 // CHECK-NEXT:    [[TMP3453:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3452]] acquire, align 8
21690 // CHECK-NEXT:    [[TMP3454:%.*]] = icmp ult i64 [[TMP3453]], [[TMP3452]]
21691 // CHECK-NEXT:    [[TMP3455:%.*]] = select i1 [[TMP3454]], i64 [[TMP3452]], i64 [[TMP3453]]
21692 // CHECK-NEXT:    store i64 [[TMP3455]], ptr [[ULV]], align 8
21693 // CHECK-NEXT:    [[TMP3456:%.*]] = load i64, ptr [[ULE]], align 8
21694 // CHECK-NEXT:    [[TMP3457:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3456]] acquire, align 8
21695 // CHECK-NEXT:    [[TMP3458:%.*]] = icmp ult i64 [[TMP3457]], [[TMP3456]]
21696 // CHECK-NEXT:    [[TMP3459:%.*]] = select i1 [[TMP3458]], i64 [[TMP3456]], i64 [[TMP3457]]
21697 // CHECK-NEXT:    store i64 [[TMP3459]], ptr [[ULV]], align 8
21698 // CHECK-NEXT:    [[TMP3460:%.*]] = load i64, ptr [[ULE]], align 8
21699 // CHECK-NEXT:    [[TMP3461:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3460]] acquire, align 8
21700 // CHECK-NEXT:    [[TMP3462:%.*]] = icmp ugt i64 [[TMP3461]], [[TMP3460]]
21701 // CHECK-NEXT:    [[TMP3463:%.*]] = select i1 [[TMP3462]], i64 [[TMP3460]], i64 [[TMP3461]]
21702 // CHECK-NEXT:    store i64 [[TMP3463]], ptr [[ULV]], align 8
21703 // CHECK-NEXT:    [[TMP3464:%.*]] = load i64, ptr [[ULE]], align 8
21704 // CHECK-NEXT:    [[TMP3465:%.*]] = load i64, ptr [[ULD]], align 8
21705 // CHECK-NEXT:    [[TMP3466:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3464]], i64 [[TMP3465]] acquire acquire, align 8
21706 // CHECK-NEXT:    [[TMP3467:%.*]] = extractvalue { i64, i1 } [[TMP3466]], 0
21707 // CHECK-NEXT:    [[TMP3468:%.*]] = extractvalue { i64, i1 } [[TMP3466]], 1
21708 // CHECK-NEXT:    [[TMP3469:%.*]] = select i1 [[TMP3468]], i64 [[TMP3464]], i64 [[TMP3467]]
21709 // CHECK-NEXT:    store i64 [[TMP3469]], ptr [[ULV]], align 8
21710 // CHECK-NEXT:    [[TMP3470:%.*]] = load i64, ptr [[ULE]], align 8
21711 // CHECK-NEXT:    [[TMP3471:%.*]] = load i64, ptr [[ULD]], align 8
21712 // CHECK-NEXT:    [[TMP3472:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3470]], i64 [[TMP3471]] acquire acquire, align 8
21713 // CHECK-NEXT:    [[TMP3473:%.*]] = extractvalue { i64, i1 } [[TMP3472]], 0
21714 // CHECK-NEXT:    [[TMP3474:%.*]] = extractvalue { i64, i1 } [[TMP3472]], 1
21715 // CHECK-NEXT:    [[TMP3475:%.*]] = select i1 [[TMP3474]], i64 [[TMP3470]], i64 [[TMP3473]]
21716 // CHECK-NEXT:    store i64 [[TMP3475]], ptr [[ULV]], align 8
21717 // CHECK-NEXT:    [[TMP3476:%.*]] = load i64, ptr [[ULE]], align 8
21718 // CHECK-NEXT:    [[TMP3477:%.*]] = load i64, ptr [[ULD]], align 8
21719 // CHECK-NEXT:    [[TMP3478:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3476]], i64 [[TMP3477]] acquire acquire, align 8
21720 // CHECK-NEXT:    [[TMP3479:%.*]] = extractvalue { i64, i1 } [[TMP3478]], 0
21721 // CHECK-NEXT:    [[TMP3480:%.*]] = extractvalue { i64, i1 } [[TMP3478]], 1
21722 // CHECK-NEXT:    br i1 [[TMP3480]], label [[ULX_ATOMIC_EXIT337:%.*]], label [[ULX_ATOMIC_CONT338:%.*]]
21723 // CHECK:       ulx.atomic.cont338:
21724 // CHECK-NEXT:    store i64 [[TMP3479]], ptr [[ULV]], align 8
21725 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT337]]
21726 // CHECK:       ulx.atomic.exit337:
21727 // CHECK-NEXT:    [[TMP3481:%.*]] = load i64, ptr [[ULE]], align 8
21728 // CHECK-NEXT:    [[TMP3482:%.*]] = load i64, ptr [[ULD]], align 8
21729 // CHECK-NEXT:    [[TMP3483:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3481]], i64 [[TMP3482]] acquire acquire, align 8
21730 // CHECK-NEXT:    [[TMP3484:%.*]] = extractvalue { i64, i1 } [[TMP3483]], 0
21731 // CHECK-NEXT:    [[TMP3485:%.*]] = extractvalue { i64, i1 } [[TMP3483]], 1
21732 // CHECK-NEXT:    br i1 [[TMP3485]], label [[ULX_ATOMIC_EXIT339:%.*]], label [[ULX_ATOMIC_CONT340:%.*]]
21733 // CHECK:       ulx.atomic.cont340:
21734 // CHECK-NEXT:    store i64 [[TMP3484]], ptr [[ULV]], align 8
21735 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT339]]
21736 // CHECK:       ulx.atomic.exit339:
21737 // CHECK-NEXT:    [[TMP3486:%.*]] = load i64, ptr [[ULE]], align 8
21738 // CHECK-NEXT:    [[TMP3487:%.*]] = load i64, ptr [[ULD]], align 8
21739 // CHECK-NEXT:    [[TMP3488:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3486]], i64 [[TMP3487]] acquire acquire, align 8
21740 // CHECK-NEXT:    [[TMP3489:%.*]] = extractvalue { i64, i1 } [[TMP3488]], 1
21741 // CHECK-NEXT:    [[TMP3490:%.*]] = zext i1 [[TMP3489]] to i64
21742 // CHECK-NEXT:    store i64 [[TMP3490]], ptr [[ULR]], align 8
21743 // CHECK-NEXT:    [[TMP3491:%.*]] = load i64, ptr [[ULE]], align 8
21744 // CHECK-NEXT:    [[TMP3492:%.*]] = load i64, ptr [[ULD]], align 8
21745 // CHECK-NEXT:    [[TMP3493:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3491]], i64 [[TMP3492]] acquire acquire, align 8
21746 // CHECK-NEXT:    [[TMP3494:%.*]] = extractvalue { i64, i1 } [[TMP3493]], 1
21747 // CHECK-NEXT:    [[TMP3495:%.*]] = zext i1 [[TMP3494]] to i64
21748 // CHECK-NEXT:    store i64 [[TMP3495]], ptr [[ULR]], align 8
21749 // CHECK-NEXT:    [[TMP3496:%.*]] = load i64, ptr [[ULE]], align 8
21750 // CHECK-NEXT:    [[TMP3497:%.*]] = load i64, ptr [[ULD]], align 8
21751 // CHECK-NEXT:    [[TMP3498:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3496]], i64 [[TMP3497]] acquire acquire, align 8
21752 // CHECK-NEXT:    [[TMP3499:%.*]] = extractvalue { i64, i1 } [[TMP3498]], 0
21753 // CHECK-NEXT:    [[TMP3500:%.*]] = extractvalue { i64, i1 } [[TMP3498]], 1
21754 // CHECK-NEXT:    br i1 [[TMP3500]], label [[ULX_ATOMIC_EXIT341:%.*]], label [[ULX_ATOMIC_CONT342:%.*]]
21755 // CHECK:       ulx.atomic.cont342:
21756 // CHECK-NEXT:    store i64 [[TMP3499]], ptr [[ULV]], align 8
21757 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT341]]
21758 // CHECK:       ulx.atomic.exit341:
21759 // CHECK-NEXT:    [[TMP3501:%.*]] = extractvalue { i64, i1 } [[TMP3498]], 1
21760 // CHECK-NEXT:    [[TMP3502:%.*]] = zext i1 [[TMP3501]] to i64
21761 // CHECK-NEXT:    store i64 [[TMP3502]], ptr [[ULR]], align 8
21762 // CHECK-NEXT:    [[TMP3503:%.*]] = load i64, ptr [[ULE]], align 8
21763 // CHECK-NEXT:    [[TMP3504:%.*]] = load i64, ptr [[ULD]], align 8
21764 // CHECK-NEXT:    [[TMP3505:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3503]], i64 [[TMP3504]] acquire acquire, align 8
21765 // CHECK-NEXT:    [[TMP3506:%.*]] = extractvalue { i64, i1 } [[TMP3505]], 0
21766 // CHECK-NEXT:    [[TMP3507:%.*]] = extractvalue { i64, i1 } [[TMP3505]], 1
21767 // CHECK-NEXT:    br i1 [[TMP3507]], label [[ULX_ATOMIC_EXIT343:%.*]], label [[ULX_ATOMIC_CONT344:%.*]]
21768 // CHECK:       ulx.atomic.cont344:
21769 // CHECK-NEXT:    store i64 [[TMP3506]], ptr [[ULV]], align 8
21770 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT343]]
21771 // CHECK:       ulx.atomic.exit343:
21772 // CHECK-NEXT:    [[TMP3508:%.*]] = extractvalue { i64, i1 } [[TMP3505]], 1
21773 // CHECK-NEXT:    [[TMP3509:%.*]] = zext i1 [[TMP3508]] to i64
21774 // CHECK-NEXT:    store i64 [[TMP3509]], ptr [[ULR]], align 8
21775 // CHECK-NEXT:    [[TMP3510:%.*]] = load i64, ptr [[ULE]], align 8
21776 // CHECK-NEXT:    [[TMP3511:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3510]] monotonic, align 8
21777 // CHECK-NEXT:    store i64 [[TMP3511]], ptr [[ULV]], align 8
21778 // CHECK-NEXT:    [[TMP3512:%.*]] = load i64, ptr [[ULE]], align 8
21779 // CHECK-NEXT:    [[TMP3513:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3512]] monotonic, align 8
21780 // CHECK-NEXT:    store i64 [[TMP3513]], ptr [[ULV]], align 8
21781 // CHECK-NEXT:    [[TMP3514:%.*]] = load i64, ptr [[ULE]], align 8
21782 // CHECK-NEXT:    [[TMP3515:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3514]] monotonic, align 8
21783 // CHECK-NEXT:    store i64 [[TMP3515]], ptr [[ULV]], align 8
21784 // CHECK-NEXT:    [[TMP3516:%.*]] = load i64, ptr [[ULE]], align 8
21785 // CHECK-NEXT:    [[TMP3517:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3516]] monotonic, align 8
21786 // CHECK-NEXT:    store i64 [[TMP3517]], ptr [[ULV]], align 8
21787 // CHECK-NEXT:    [[TMP3518:%.*]] = load i64, ptr [[ULE]], align 8
21788 // CHECK-NEXT:    [[TMP3519:%.*]] = load i64, ptr [[ULD]], align 8
21789 // CHECK-NEXT:    [[TMP3520:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3518]], i64 [[TMP3519]] monotonic monotonic, align 8
21790 // CHECK-NEXT:    [[TMP3521:%.*]] = extractvalue { i64, i1 } [[TMP3520]], 0
21791 // CHECK-NEXT:    store i64 [[TMP3521]], ptr [[ULV]], align 8
21792 // CHECK-NEXT:    [[TMP3522:%.*]] = load i64, ptr [[ULE]], align 8
21793 // CHECK-NEXT:    [[TMP3523:%.*]] = load i64, ptr [[ULD]], align 8
21794 // CHECK-NEXT:    [[TMP3524:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3522]], i64 [[TMP3523]] monotonic monotonic, align 8
21795 // CHECK-NEXT:    [[TMP3525:%.*]] = extractvalue { i64, i1 } [[TMP3524]], 0
21796 // CHECK-NEXT:    store i64 [[TMP3525]], ptr [[ULV]], align 8
21797 // CHECK-NEXT:    [[TMP3526:%.*]] = load i64, ptr [[ULE]], align 8
21798 // CHECK-NEXT:    [[TMP3527:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3526]] monotonic, align 8
21799 // CHECK-NEXT:    [[TMP3528:%.*]] = icmp ugt i64 [[TMP3527]], [[TMP3526]]
21800 // CHECK-NEXT:    [[TMP3529:%.*]] = select i1 [[TMP3528]], i64 [[TMP3526]], i64 [[TMP3527]]
21801 // CHECK-NEXT:    store i64 [[TMP3529]], ptr [[ULV]], align 8
21802 // CHECK-NEXT:    [[TMP3530:%.*]] = load i64, ptr [[ULE]], align 8
21803 // CHECK-NEXT:    [[TMP3531:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3530]] monotonic, align 8
21804 // CHECK-NEXT:    [[TMP3532:%.*]] = icmp ult i64 [[TMP3531]], [[TMP3530]]
21805 // CHECK-NEXT:    [[TMP3533:%.*]] = select i1 [[TMP3532]], i64 [[TMP3530]], i64 [[TMP3531]]
21806 // CHECK-NEXT:    store i64 [[TMP3533]], ptr [[ULV]], align 8
21807 // CHECK-NEXT:    [[TMP3534:%.*]] = load i64, ptr [[ULE]], align 8
21808 // CHECK-NEXT:    [[TMP3535:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3534]] monotonic, align 8
21809 // CHECK-NEXT:    [[TMP3536:%.*]] = icmp ult i64 [[TMP3535]], [[TMP3534]]
21810 // CHECK-NEXT:    [[TMP3537:%.*]] = select i1 [[TMP3536]], i64 [[TMP3534]], i64 [[TMP3535]]
21811 // CHECK-NEXT:    store i64 [[TMP3537]], ptr [[ULV]], align 8
21812 // CHECK-NEXT:    [[TMP3538:%.*]] = load i64, ptr [[ULE]], align 8
21813 // CHECK-NEXT:    [[TMP3539:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3538]] monotonic, align 8
21814 // CHECK-NEXT:    [[TMP3540:%.*]] = icmp ugt i64 [[TMP3539]], [[TMP3538]]
21815 // CHECK-NEXT:    [[TMP3541:%.*]] = select i1 [[TMP3540]], i64 [[TMP3538]], i64 [[TMP3539]]
21816 // CHECK-NEXT:    store i64 [[TMP3541]], ptr [[ULV]], align 8
21817 // CHECK-NEXT:    [[TMP3542:%.*]] = load i64, ptr [[ULE]], align 8
21818 // CHECK-NEXT:    [[TMP3543:%.*]] = load i64, ptr [[ULD]], align 8
21819 // CHECK-NEXT:    [[TMP3544:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3542]], i64 [[TMP3543]] monotonic monotonic, align 8
21820 // CHECK-NEXT:    [[TMP3545:%.*]] = extractvalue { i64, i1 } [[TMP3544]], 0
21821 // CHECK-NEXT:    [[TMP3546:%.*]] = extractvalue { i64, i1 } [[TMP3544]], 1
21822 // CHECK-NEXT:    [[TMP3547:%.*]] = select i1 [[TMP3546]], i64 [[TMP3542]], i64 [[TMP3545]]
21823 // CHECK-NEXT:    store i64 [[TMP3547]], ptr [[ULV]], align 8
21824 // CHECK-NEXT:    [[TMP3548:%.*]] = load i64, ptr [[ULE]], align 8
21825 // CHECK-NEXT:    [[TMP3549:%.*]] = load i64, ptr [[ULD]], align 8
21826 // CHECK-NEXT:    [[TMP3550:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3548]], i64 [[TMP3549]] monotonic monotonic, align 8
21827 // CHECK-NEXT:    [[TMP3551:%.*]] = extractvalue { i64, i1 } [[TMP3550]], 0
21828 // CHECK-NEXT:    [[TMP3552:%.*]] = extractvalue { i64, i1 } [[TMP3550]], 1
21829 // CHECK-NEXT:    [[TMP3553:%.*]] = select i1 [[TMP3552]], i64 [[TMP3548]], i64 [[TMP3551]]
21830 // CHECK-NEXT:    store i64 [[TMP3553]], ptr [[ULV]], align 8
21831 // CHECK-NEXT:    [[TMP3554:%.*]] = load i64, ptr [[ULE]], align 8
21832 // CHECK-NEXT:    [[TMP3555:%.*]] = load i64, ptr [[ULD]], align 8
21833 // CHECK-NEXT:    [[TMP3556:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3554]], i64 [[TMP3555]] monotonic monotonic, align 8
21834 // CHECK-NEXT:    [[TMP3557:%.*]] = extractvalue { i64, i1 } [[TMP3556]], 0
21835 // CHECK-NEXT:    [[TMP3558:%.*]] = extractvalue { i64, i1 } [[TMP3556]], 1
21836 // CHECK-NEXT:    br i1 [[TMP3558]], label [[ULX_ATOMIC_EXIT345:%.*]], label [[ULX_ATOMIC_CONT346:%.*]]
21837 // CHECK:       ulx.atomic.cont346:
21838 // CHECK-NEXT:    store i64 [[TMP3557]], ptr [[ULV]], align 8
21839 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT345]]
21840 // CHECK:       ulx.atomic.exit345:
21841 // CHECK-NEXT:    [[TMP3559:%.*]] = load i64, ptr [[ULE]], align 8
21842 // CHECK-NEXT:    [[TMP3560:%.*]] = load i64, ptr [[ULD]], align 8
21843 // CHECK-NEXT:    [[TMP3561:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3559]], i64 [[TMP3560]] monotonic monotonic, align 8
21844 // CHECK-NEXT:    [[TMP3562:%.*]] = extractvalue { i64, i1 } [[TMP3561]], 0
21845 // CHECK-NEXT:    [[TMP3563:%.*]] = extractvalue { i64, i1 } [[TMP3561]], 1
21846 // CHECK-NEXT:    br i1 [[TMP3563]], label [[ULX_ATOMIC_EXIT347:%.*]], label [[ULX_ATOMIC_CONT348:%.*]]
21847 // CHECK:       ulx.atomic.cont348:
21848 // CHECK-NEXT:    store i64 [[TMP3562]], ptr [[ULV]], align 8
21849 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT347]]
21850 // CHECK:       ulx.atomic.exit347:
21851 // CHECK-NEXT:    [[TMP3564:%.*]] = load i64, ptr [[ULE]], align 8
21852 // CHECK-NEXT:    [[TMP3565:%.*]] = load i64, ptr [[ULD]], align 8
21853 // CHECK-NEXT:    [[TMP3566:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3564]], i64 [[TMP3565]] monotonic monotonic, align 8
21854 // CHECK-NEXT:    [[TMP3567:%.*]] = extractvalue { i64, i1 } [[TMP3566]], 1
21855 // CHECK-NEXT:    [[TMP3568:%.*]] = zext i1 [[TMP3567]] to i64
21856 // CHECK-NEXT:    store i64 [[TMP3568]], ptr [[ULR]], align 8
21857 // CHECK-NEXT:    [[TMP3569:%.*]] = load i64, ptr [[ULE]], align 8
21858 // CHECK-NEXT:    [[TMP3570:%.*]] = load i64, ptr [[ULD]], align 8
21859 // CHECK-NEXT:    [[TMP3571:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3569]], i64 [[TMP3570]] monotonic monotonic, align 8
21860 // CHECK-NEXT:    [[TMP3572:%.*]] = extractvalue { i64, i1 } [[TMP3571]], 1
21861 // CHECK-NEXT:    [[TMP3573:%.*]] = zext i1 [[TMP3572]] to i64
21862 // CHECK-NEXT:    store i64 [[TMP3573]], ptr [[ULR]], align 8
21863 // CHECK-NEXT:    [[TMP3574:%.*]] = load i64, ptr [[ULE]], align 8
21864 // CHECK-NEXT:    [[TMP3575:%.*]] = load i64, ptr [[ULD]], align 8
21865 // CHECK-NEXT:    [[TMP3576:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3574]], i64 [[TMP3575]] monotonic monotonic, align 8
21866 // CHECK-NEXT:    [[TMP3577:%.*]] = extractvalue { i64, i1 } [[TMP3576]], 0
21867 // CHECK-NEXT:    [[TMP3578:%.*]] = extractvalue { i64, i1 } [[TMP3576]], 1
21868 // CHECK-NEXT:    br i1 [[TMP3578]], label [[ULX_ATOMIC_EXIT349:%.*]], label [[ULX_ATOMIC_CONT350:%.*]]
21869 // CHECK:       ulx.atomic.cont350:
21870 // CHECK-NEXT:    store i64 [[TMP3577]], ptr [[ULV]], align 8
21871 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT349]]
21872 // CHECK:       ulx.atomic.exit349:
21873 // CHECK-NEXT:    [[TMP3579:%.*]] = extractvalue { i64, i1 } [[TMP3576]], 1
21874 // CHECK-NEXT:    [[TMP3580:%.*]] = zext i1 [[TMP3579]] to i64
21875 // CHECK-NEXT:    store i64 [[TMP3580]], ptr [[ULR]], align 8
21876 // CHECK-NEXT:    [[TMP3581:%.*]] = load i64, ptr [[ULE]], align 8
21877 // CHECK-NEXT:    [[TMP3582:%.*]] = load i64, ptr [[ULD]], align 8
21878 // CHECK-NEXT:    [[TMP3583:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3581]], i64 [[TMP3582]] monotonic monotonic, align 8
21879 // CHECK-NEXT:    [[TMP3584:%.*]] = extractvalue { i64, i1 } [[TMP3583]], 0
21880 // CHECK-NEXT:    [[TMP3585:%.*]] = extractvalue { i64, i1 } [[TMP3583]], 1
21881 // CHECK-NEXT:    br i1 [[TMP3585]], label [[ULX_ATOMIC_EXIT351:%.*]], label [[ULX_ATOMIC_CONT352:%.*]]
21882 // CHECK:       ulx.atomic.cont352:
21883 // CHECK-NEXT:    store i64 [[TMP3584]], ptr [[ULV]], align 8
21884 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT351]]
21885 // CHECK:       ulx.atomic.exit351:
21886 // CHECK-NEXT:    [[TMP3586:%.*]] = extractvalue { i64, i1 } [[TMP3583]], 1
21887 // CHECK-NEXT:    [[TMP3587:%.*]] = zext i1 [[TMP3586]] to i64
21888 // CHECK-NEXT:    store i64 [[TMP3587]], ptr [[ULR]], align 8
21889 // CHECK-NEXT:    [[TMP3588:%.*]] = load i64, ptr [[ULE]], align 8
21890 // CHECK-NEXT:    [[TMP3589:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3588]] release, align 8
21891 // CHECK-NEXT:    store i64 [[TMP3589]], ptr [[ULV]], align 8
21892 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21893 // CHECK-NEXT:    [[TMP3590:%.*]] = load i64, ptr [[ULE]], align 8
21894 // CHECK-NEXT:    [[TMP3591:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3590]] release, align 8
21895 // CHECK-NEXT:    store i64 [[TMP3591]], ptr [[ULV]], align 8
21896 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21897 // CHECK-NEXT:    [[TMP3592:%.*]] = load i64, ptr [[ULE]], align 8
21898 // CHECK-NEXT:    [[TMP3593:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3592]] release, align 8
21899 // CHECK-NEXT:    store i64 [[TMP3593]], ptr [[ULV]], align 8
21900 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21901 // CHECK-NEXT:    [[TMP3594:%.*]] = load i64, ptr [[ULE]], align 8
21902 // CHECK-NEXT:    [[TMP3595:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3594]] release, align 8
21903 // CHECK-NEXT:    store i64 [[TMP3595]], ptr [[ULV]], align 8
21904 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21905 // CHECK-NEXT:    [[TMP3596:%.*]] = load i64, ptr [[ULE]], align 8
21906 // CHECK-NEXT:    [[TMP3597:%.*]] = load i64, ptr [[ULD]], align 8
21907 // CHECK-NEXT:    [[TMP3598:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3596]], i64 [[TMP3597]] release monotonic, align 8
21908 // CHECK-NEXT:    [[TMP3599:%.*]] = extractvalue { i64, i1 } [[TMP3598]], 0
21909 // CHECK-NEXT:    store i64 [[TMP3599]], ptr [[ULV]], align 8
21910 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21911 // CHECK-NEXT:    [[TMP3600:%.*]] = load i64, ptr [[ULE]], align 8
21912 // CHECK-NEXT:    [[TMP3601:%.*]] = load i64, ptr [[ULD]], align 8
21913 // CHECK-NEXT:    [[TMP3602:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3600]], i64 [[TMP3601]] release monotonic, align 8
21914 // CHECK-NEXT:    [[TMP3603:%.*]] = extractvalue { i64, i1 } [[TMP3602]], 0
21915 // CHECK-NEXT:    store i64 [[TMP3603]], ptr [[ULV]], align 8
21916 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21917 // CHECK-NEXT:    [[TMP3604:%.*]] = load i64, ptr [[ULE]], align 8
21918 // CHECK-NEXT:    [[TMP3605:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3604]] release, align 8
21919 // CHECK-NEXT:    [[TMP3606:%.*]] = icmp ugt i64 [[TMP3605]], [[TMP3604]]
21920 // CHECK-NEXT:    [[TMP3607:%.*]] = select i1 [[TMP3606]], i64 [[TMP3604]], i64 [[TMP3605]]
21921 // CHECK-NEXT:    store i64 [[TMP3607]], ptr [[ULV]], align 8
21922 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21923 // CHECK-NEXT:    [[TMP3608:%.*]] = load i64, ptr [[ULE]], align 8
21924 // CHECK-NEXT:    [[TMP3609:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3608]] release, align 8
21925 // CHECK-NEXT:    [[TMP3610:%.*]] = icmp ult i64 [[TMP3609]], [[TMP3608]]
21926 // CHECK-NEXT:    [[TMP3611:%.*]] = select i1 [[TMP3610]], i64 [[TMP3608]], i64 [[TMP3609]]
21927 // CHECK-NEXT:    store i64 [[TMP3611]], ptr [[ULV]], align 8
21928 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21929 // CHECK-NEXT:    [[TMP3612:%.*]] = load i64, ptr [[ULE]], align 8
21930 // CHECK-NEXT:    [[TMP3613:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3612]] release, align 8
21931 // CHECK-NEXT:    [[TMP3614:%.*]] = icmp ult i64 [[TMP3613]], [[TMP3612]]
21932 // CHECK-NEXT:    [[TMP3615:%.*]] = select i1 [[TMP3614]], i64 [[TMP3612]], i64 [[TMP3613]]
21933 // CHECK-NEXT:    store i64 [[TMP3615]], ptr [[ULV]], align 8
21934 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21935 // CHECK-NEXT:    [[TMP3616:%.*]] = load i64, ptr [[ULE]], align 8
21936 // CHECK-NEXT:    [[TMP3617:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3616]] release, align 8
21937 // CHECK-NEXT:    [[TMP3618:%.*]] = icmp ugt i64 [[TMP3617]], [[TMP3616]]
21938 // CHECK-NEXT:    [[TMP3619:%.*]] = select i1 [[TMP3618]], i64 [[TMP3616]], i64 [[TMP3617]]
21939 // CHECK-NEXT:    store i64 [[TMP3619]], ptr [[ULV]], align 8
21940 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21941 // CHECK-NEXT:    [[TMP3620:%.*]] = load i64, ptr [[ULE]], align 8
21942 // CHECK-NEXT:    [[TMP3621:%.*]] = load i64, ptr [[ULD]], align 8
21943 // CHECK-NEXT:    [[TMP3622:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3620]], i64 [[TMP3621]] release monotonic, align 8
21944 // CHECK-NEXT:    [[TMP3623:%.*]] = extractvalue { i64, i1 } [[TMP3622]], 0
21945 // CHECK-NEXT:    [[TMP3624:%.*]] = extractvalue { i64, i1 } [[TMP3622]], 1
21946 // CHECK-NEXT:    [[TMP3625:%.*]] = select i1 [[TMP3624]], i64 [[TMP3620]], i64 [[TMP3623]]
21947 // CHECK-NEXT:    store i64 [[TMP3625]], ptr [[ULV]], align 8
21948 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21949 // CHECK-NEXT:    [[TMP3626:%.*]] = load i64, ptr [[ULE]], align 8
21950 // CHECK-NEXT:    [[TMP3627:%.*]] = load i64, ptr [[ULD]], align 8
21951 // CHECK-NEXT:    [[TMP3628:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3626]], i64 [[TMP3627]] release monotonic, align 8
21952 // CHECK-NEXT:    [[TMP3629:%.*]] = extractvalue { i64, i1 } [[TMP3628]], 0
21953 // CHECK-NEXT:    [[TMP3630:%.*]] = extractvalue { i64, i1 } [[TMP3628]], 1
21954 // CHECK-NEXT:    [[TMP3631:%.*]] = select i1 [[TMP3630]], i64 [[TMP3626]], i64 [[TMP3629]]
21955 // CHECK-NEXT:    store i64 [[TMP3631]], ptr [[ULV]], align 8
21956 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21957 // CHECK-NEXT:    [[TMP3632:%.*]] = load i64, ptr [[ULE]], align 8
21958 // CHECK-NEXT:    [[TMP3633:%.*]] = load i64, ptr [[ULD]], align 8
21959 // CHECK-NEXT:    [[TMP3634:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3632]], i64 [[TMP3633]] release monotonic, align 8
21960 // CHECK-NEXT:    [[TMP3635:%.*]] = extractvalue { i64, i1 } [[TMP3634]], 0
21961 // CHECK-NEXT:    [[TMP3636:%.*]] = extractvalue { i64, i1 } [[TMP3634]], 1
21962 // CHECK-NEXT:    br i1 [[TMP3636]], label [[ULX_ATOMIC_EXIT353:%.*]], label [[ULX_ATOMIC_CONT354:%.*]]
21963 // CHECK:       ulx.atomic.cont354:
21964 // CHECK-NEXT:    store i64 [[TMP3635]], ptr [[ULV]], align 8
21965 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT353]]
21966 // CHECK:       ulx.atomic.exit353:
21967 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21968 // CHECK-NEXT:    [[TMP3637:%.*]] = load i64, ptr [[ULE]], align 8
21969 // CHECK-NEXT:    [[TMP3638:%.*]] = load i64, ptr [[ULD]], align 8
21970 // CHECK-NEXT:    [[TMP3639:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3637]], i64 [[TMP3638]] release monotonic, align 8
21971 // CHECK-NEXT:    [[TMP3640:%.*]] = extractvalue { i64, i1 } [[TMP3639]], 0
21972 // CHECK-NEXT:    [[TMP3641:%.*]] = extractvalue { i64, i1 } [[TMP3639]], 1
21973 // CHECK-NEXT:    br i1 [[TMP3641]], label [[ULX_ATOMIC_EXIT355:%.*]], label [[ULX_ATOMIC_CONT356:%.*]]
21974 // CHECK:       ulx.atomic.cont356:
21975 // CHECK-NEXT:    store i64 [[TMP3640]], ptr [[ULV]], align 8
21976 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT355]]
21977 // CHECK:       ulx.atomic.exit355:
21978 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21979 // CHECK-NEXT:    [[TMP3642:%.*]] = load i64, ptr [[ULE]], align 8
21980 // CHECK-NEXT:    [[TMP3643:%.*]] = load i64, ptr [[ULD]], align 8
21981 // CHECK-NEXT:    [[TMP3644:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3642]], i64 [[TMP3643]] release monotonic, align 8
21982 // CHECK-NEXT:    [[TMP3645:%.*]] = extractvalue { i64, i1 } [[TMP3644]], 1
21983 // CHECK-NEXT:    [[TMP3646:%.*]] = zext i1 [[TMP3645]] to i64
21984 // CHECK-NEXT:    store i64 [[TMP3646]], ptr [[ULR]], align 8
21985 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21986 // CHECK-NEXT:    [[TMP3647:%.*]] = load i64, ptr [[ULE]], align 8
21987 // CHECK-NEXT:    [[TMP3648:%.*]] = load i64, ptr [[ULD]], align 8
21988 // CHECK-NEXT:    [[TMP3649:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3647]], i64 [[TMP3648]] release monotonic, align 8
21989 // CHECK-NEXT:    [[TMP3650:%.*]] = extractvalue { i64, i1 } [[TMP3649]], 1
21990 // CHECK-NEXT:    [[TMP3651:%.*]] = zext i1 [[TMP3650]] to i64
21991 // CHECK-NEXT:    store i64 [[TMP3651]], ptr [[ULR]], align 8
21992 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
21993 // CHECK-NEXT:    [[TMP3652:%.*]] = load i64, ptr [[ULE]], align 8
21994 // CHECK-NEXT:    [[TMP3653:%.*]] = load i64, ptr [[ULD]], align 8
21995 // CHECK-NEXT:    [[TMP3654:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3652]], i64 [[TMP3653]] release monotonic, align 8
21996 // CHECK-NEXT:    [[TMP3655:%.*]] = extractvalue { i64, i1 } [[TMP3654]], 0
21997 // CHECK-NEXT:    [[TMP3656:%.*]] = extractvalue { i64, i1 } [[TMP3654]], 1
21998 // CHECK-NEXT:    br i1 [[TMP3656]], label [[ULX_ATOMIC_EXIT357:%.*]], label [[ULX_ATOMIC_CONT358:%.*]]
21999 // CHECK:       ulx.atomic.cont358:
22000 // CHECK-NEXT:    store i64 [[TMP3655]], ptr [[ULV]], align 8
22001 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT357]]
22002 // CHECK:       ulx.atomic.exit357:
22003 // CHECK-NEXT:    [[TMP3657:%.*]] = extractvalue { i64, i1 } [[TMP3654]], 1
22004 // CHECK-NEXT:    [[TMP3658:%.*]] = zext i1 [[TMP3657]] to i64
22005 // CHECK-NEXT:    store i64 [[TMP3658]], ptr [[ULR]], align 8
22006 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22007 // CHECK-NEXT:    [[TMP3659:%.*]] = load i64, ptr [[ULE]], align 8
22008 // CHECK-NEXT:    [[TMP3660:%.*]] = load i64, ptr [[ULD]], align 8
22009 // CHECK-NEXT:    [[TMP3661:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3659]], i64 [[TMP3660]] release monotonic, align 8
22010 // CHECK-NEXT:    [[TMP3662:%.*]] = extractvalue { i64, i1 } [[TMP3661]], 0
22011 // CHECK-NEXT:    [[TMP3663:%.*]] = extractvalue { i64, i1 } [[TMP3661]], 1
22012 // CHECK-NEXT:    br i1 [[TMP3663]], label [[ULX_ATOMIC_EXIT359:%.*]], label [[ULX_ATOMIC_CONT360:%.*]]
22013 // CHECK:       ulx.atomic.cont360:
22014 // CHECK-NEXT:    store i64 [[TMP3662]], ptr [[ULV]], align 8
22015 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT359]]
22016 // CHECK:       ulx.atomic.exit359:
22017 // CHECK-NEXT:    [[TMP3664:%.*]] = extractvalue { i64, i1 } [[TMP3661]], 1
22018 // CHECK-NEXT:    [[TMP3665:%.*]] = zext i1 [[TMP3664]] to i64
22019 // CHECK-NEXT:    store i64 [[TMP3665]], ptr [[ULR]], align 8
22020 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22021 // CHECK-NEXT:    [[TMP3666:%.*]] = load i64, ptr [[ULE]], align 8
22022 // CHECK-NEXT:    [[TMP3667:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3666]] seq_cst, align 8
22023 // CHECK-NEXT:    store i64 [[TMP3667]], ptr [[ULV]], align 8
22024 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22025 // CHECK-NEXT:    [[TMP3668:%.*]] = load i64, ptr [[ULE]], align 8
22026 // CHECK-NEXT:    [[TMP3669:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3668]] seq_cst, align 8
22027 // CHECK-NEXT:    store i64 [[TMP3669]], ptr [[ULV]], align 8
22028 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22029 // CHECK-NEXT:    [[TMP3670:%.*]] = load i64, ptr [[ULE]], align 8
22030 // CHECK-NEXT:    [[TMP3671:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3670]] seq_cst, align 8
22031 // CHECK-NEXT:    store i64 [[TMP3671]], ptr [[ULV]], align 8
22032 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22033 // CHECK-NEXT:    [[TMP3672:%.*]] = load i64, ptr [[ULE]], align 8
22034 // CHECK-NEXT:    [[TMP3673:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3672]] seq_cst, align 8
22035 // CHECK-NEXT:    store i64 [[TMP3673]], ptr [[ULV]], align 8
22036 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22037 // CHECK-NEXT:    [[TMP3674:%.*]] = load i64, ptr [[ULE]], align 8
22038 // CHECK-NEXT:    [[TMP3675:%.*]] = load i64, ptr [[ULD]], align 8
22039 // CHECK-NEXT:    [[TMP3676:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3674]], i64 [[TMP3675]] seq_cst seq_cst, align 8
22040 // CHECK-NEXT:    [[TMP3677:%.*]] = extractvalue { i64, i1 } [[TMP3676]], 0
22041 // CHECK-NEXT:    store i64 [[TMP3677]], ptr [[ULV]], align 8
22042 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22043 // CHECK-NEXT:    [[TMP3678:%.*]] = load i64, ptr [[ULE]], align 8
22044 // CHECK-NEXT:    [[TMP3679:%.*]] = load i64, ptr [[ULD]], align 8
22045 // CHECK-NEXT:    [[TMP3680:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3678]], i64 [[TMP3679]] seq_cst seq_cst, align 8
22046 // CHECK-NEXT:    [[TMP3681:%.*]] = extractvalue { i64, i1 } [[TMP3680]], 0
22047 // CHECK-NEXT:    store i64 [[TMP3681]], ptr [[ULV]], align 8
22048 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22049 // CHECK-NEXT:    [[TMP3682:%.*]] = load i64, ptr [[ULE]], align 8
22050 // CHECK-NEXT:    [[TMP3683:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3682]] seq_cst, align 8
22051 // CHECK-NEXT:    [[TMP3684:%.*]] = icmp ugt i64 [[TMP3683]], [[TMP3682]]
22052 // CHECK-NEXT:    [[TMP3685:%.*]] = select i1 [[TMP3684]], i64 [[TMP3682]], i64 [[TMP3683]]
22053 // CHECK-NEXT:    store i64 [[TMP3685]], ptr [[ULV]], align 8
22054 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22055 // CHECK-NEXT:    [[TMP3686:%.*]] = load i64, ptr [[ULE]], align 8
22056 // CHECK-NEXT:    [[TMP3687:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3686]] seq_cst, align 8
22057 // CHECK-NEXT:    [[TMP3688:%.*]] = icmp ult i64 [[TMP3687]], [[TMP3686]]
22058 // CHECK-NEXT:    [[TMP3689:%.*]] = select i1 [[TMP3688]], i64 [[TMP3686]], i64 [[TMP3687]]
22059 // CHECK-NEXT:    store i64 [[TMP3689]], ptr [[ULV]], align 8
22060 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22061 // CHECK-NEXT:    [[TMP3690:%.*]] = load i64, ptr [[ULE]], align 8
22062 // CHECK-NEXT:    [[TMP3691:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3690]] seq_cst, align 8
22063 // CHECK-NEXT:    [[TMP3692:%.*]] = icmp ult i64 [[TMP3691]], [[TMP3690]]
22064 // CHECK-NEXT:    [[TMP3693:%.*]] = select i1 [[TMP3692]], i64 [[TMP3690]], i64 [[TMP3691]]
22065 // CHECK-NEXT:    store i64 [[TMP3693]], ptr [[ULV]], align 8
22066 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22067 // CHECK-NEXT:    [[TMP3694:%.*]] = load i64, ptr [[ULE]], align 8
22068 // CHECK-NEXT:    [[TMP3695:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3694]] seq_cst, align 8
22069 // CHECK-NEXT:    [[TMP3696:%.*]] = icmp ugt i64 [[TMP3695]], [[TMP3694]]
22070 // CHECK-NEXT:    [[TMP3697:%.*]] = select i1 [[TMP3696]], i64 [[TMP3694]], i64 [[TMP3695]]
22071 // CHECK-NEXT:    store i64 [[TMP3697]], ptr [[ULV]], align 8
22072 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22073 // CHECK-NEXT:    [[TMP3698:%.*]] = load i64, ptr [[ULE]], align 8
22074 // CHECK-NEXT:    [[TMP3699:%.*]] = load i64, ptr [[ULD]], align 8
22075 // CHECK-NEXT:    [[TMP3700:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3698]], i64 [[TMP3699]] seq_cst seq_cst, align 8
22076 // CHECK-NEXT:    [[TMP3701:%.*]] = extractvalue { i64, i1 } [[TMP3700]], 0
22077 // CHECK-NEXT:    [[TMP3702:%.*]] = extractvalue { i64, i1 } [[TMP3700]], 1
22078 // CHECK-NEXT:    [[TMP3703:%.*]] = select i1 [[TMP3702]], i64 [[TMP3698]], i64 [[TMP3701]]
22079 // CHECK-NEXT:    store i64 [[TMP3703]], ptr [[ULV]], align 8
22080 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22081 // CHECK-NEXT:    [[TMP3704:%.*]] = load i64, ptr [[ULE]], align 8
22082 // CHECK-NEXT:    [[TMP3705:%.*]] = load i64, ptr [[ULD]], align 8
22083 // CHECK-NEXT:    [[TMP3706:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3704]], i64 [[TMP3705]] seq_cst seq_cst, align 8
22084 // CHECK-NEXT:    [[TMP3707:%.*]] = extractvalue { i64, i1 } [[TMP3706]], 0
22085 // CHECK-NEXT:    [[TMP3708:%.*]] = extractvalue { i64, i1 } [[TMP3706]], 1
22086 // CHECK-NEXT:    [[TMP3709:%.*]] = select i1 [[TMP3708]], i64 [[TMP3704]], i64 [[TMP3707]]
22087 // CHECK-NEXT:    store i64 [[TMP3709]], ptr [[ULV]], align 8
22088 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22089 // CHECK-NEXT:    [[TMP3710:%.*]] = load i64, ptr [[ULE]], align 8
22090 // CHECK-NEXT:    [[TMP3711:%.*]] = load i64, ptr [[ULD]], align 8
22091 // CHECK-NEXT:    [[TMP3712:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3710]], i64 [[TMP3711]] seq_cst seq_cst, align 8
22092 // CHECK-NEXT:    [[TMP3713:%.*]] = extractvalue { i64, i1 } [[TMP3712]], 0
22093 // CHECK-NEXT:    [[TMP3714:%.*]] = extractvalue { i64, i1 } [[TMP3712]], 1
22094 // CHECK-NEXT:    br i1 [[TMP3714]], label [[ULX_ATOMIC_EXIT361:%.*]], label [[ULX_ATOMIC_CONT362:%.*]]
22095 // CHECK:       ulx.atomic.cont362:
22096 // CHECK-NEXT:    store i64 [[TMP3713]], ptr [[ULV]], align 8
22097 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT361]]
22098 // CHECK:       ulx.atomic.exit361:
22099 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22100 // CHECK-NEXT:    [[TMP3715:%.*]] = load i64, ptr [[ULE]], align 8
22101 // CHECK-NEXT:    [[TMP3716:%.*]] = load i64, ptr [[ULD]], align 8
22102 // CHECK-NEXT:    [[TMP3717:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3715]], i64 [[TMP3716]] seq_cst seq_cst, align 8
22103 // CHECK-NEXT:    [[TMP3718:%.*]] = extractvalue { i64, i1 } [[TMP3717]], 0
22104 // CHECK-NEXT:    [[TMP3719:%.*]] = extractvalue { i64, i1 } [[TMP3717]], 1
22105 // CHECK-NEXT:    br i1 [[TMP3719]], label [[ULX_ATOMIC_EXIT363:%.*]], label [[ULX_ATOMIC_CONT364:%.*]]
22106 // CHECK:       ulx.atomic.cont364:
22107 // CHECK-NEXT:    store i64 [[TMP3718]], ptr [[ULV]], align 8
22108 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT363]]
22109 // CHECK:       ulx.atomic.exit363:
22110 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22111 // CHECK-NEXT:    [[TMP3720:%.*]] = load i64, ptr [[ULE]], align 8
22112 // CHECK-NEXT:    [[TMP3721:%.*]] = load i64, ptr [[ULD]], align 8
22113 // CHECK-NEXT:    [[TMP3722:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3720]], i64 [[TMP3721]] seq_cst seq_cst, align 8
22114 // CHECK-NEXT:    [[TMP3723:%.*]] = extractvalue { i64, i1 } [[TMP3722]], 1
22115 // CHECK-NEXT:    [[TMP3724:%.*]] = zext i1 [[TMP3723]] to i64
22116 // CHECK-NEXT:    store i64 [[TMP3724]], ptr [[ULR]], align 8
22117 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22118 // CHECK-NEXT:    [[TMP3725:%.*]] = load i64, ptr [[ULE]], align 8
22119 // CHECK-NEXT:    [[TMP3726:%.*]] = load i64, ptr [[ULD]], align 8
22120 // CHECK-NEXT:    [[TMP3727:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3725]], i64 [[TMP3726]] seq_cst seq_cst, align 8
22121 // CHECK-NEXT:    [[TMP3728:%.*]] = extractvalue { i64, i1 } [[TMP3727]], 1
22122 // CHECK-NEXT:    [[TMP3729:%.*]] = zext i1 [[TMP3728]] to i64
22123 // CHECK-NEXT:    store i64 [[TMP3729]], ptr [[ULR]], align 8
22124 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22125 // CHECK-NEXT:    [[TMP3730:%.*]] = load i64, ptr [[ULE]], align 8
22126 // CHECK-NEXT:    [[TMP3731:%.*]] = load i64, ptr [[ULD]], align 8
22127 // CHECK-NEXT:    [[TMP3732:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3730]], i64 [[TMP3731]] seq_cst seq_cst, align 8
22128 // CHECK-NEXT:    [[TMP3733:%.*]] = extractvalue { i64, i1 } [[TMP3732]], 0
22129 // CHECK-NEXT:    [[TMP3734:%.*]] = extractvalue { i64, i1 } [[TMP3732]], 1
22130 // CHECK-NEXT:    br i1 [[TMP3734]], label [[ULX_ATOMIC_EXIT365:%.*]], label [[ULX_ATOMIC_CONT366:%.*]]
22131 // CHECK:       ulx.atomic.cont366:
22132 // CHECK-NEXT:    store i64 [[TMP3733]], ptr [[ULV]], align 8
22133 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT365]]
22134 // CHECK:       ulx.atomic.exit365:
22135 // CHECK-NEXT:    [[TMP3735:%.*]] = extractvalue { i64, i1 } [[TMP3732]], 1
22136 // CHECK-NEXT:    [[TMP3736:%.*]] = zext i1 [[TMP3735]] to i64
22137 // CHECK-NEXT:    store i64 [[TMP3736]], ptr [[ULR]], align 8
22138 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22139 // CHECK-NEXT:    [[TMP3737:%.*]] = load i64, ptr [[ULE]], align 8
22140 // CHECK-NEXT:    [[TMP3738:%.*]] = load i64, ptr [[ULD]], align 8
22141 // CHECK-NEXT:    [[TMP3739:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3737]], i64 [[TMP3738]] seq_cst seq_cst, align 8
22142 // CHECK-NEXT:    [[TMP3740:%.*]] = extractvalue { i64, i1 } [[TMP3739]], 0
22143 // CHECK-NEXT:    [[TMP3741:%.*]] = extractvalue { i64, i1 } [[TMP3739]], 1
22144 // CHECK-NEXT:    br i1 [[TMP3741]], label [[ULX_ATOMIC_EXIT367:%.*]], label [[ULX_ATOMIC_CONT368:%.*]]
22145 // CHECK:       ulx.atomic.cont368:
22146 // CHECK-NEXT:    store i64 [[TMP3740]], ptr [[ULV]], align 8
22147 // CHECK-NEXT:    br label [[ULX_ATOMIC_EXIT367]]
22148 // CHECK:       ulx.atomic.exit367:
22149 // CHECK-NEXT:    [[TMP3742:%.*]] = extractvalue { i64, i1 } [[TMP3739]], 1
22150 // CHECK-NEXT:    [[TMP3743:%.*]] = zext i1 [[TMP3742]] to i64
22151 // CHECK-NEXT:    store i64 [[TMP3743]], ptr [[ULR]], align 8
22152 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22153 // CHECK-NEXT:    [[TMP3744:%.*]] = load i64, ptr [[LLE]], align 8
22154 // CHECK-NEXT:    [[TMP3745:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3744]] monotonic, align 8
22155 // CHECK-NEXT:    store i64 [[TMP3745]], ptr [[LLV]], align 8
22156 // CHECK-NEXT:    [[TMP3746:%.*]] = load i64, ptr [[LLE]], align 8
22157 // CHECK-NEXT:    [[TMP3747:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3746]] monotonic, align 8
22158 // CHECK-NEXT:    store i64 [[TMP3747]], ptr [[LLV]], align 8
22159 // CHECK-NEXT:    [[TMP3748:%.*]] = load i64, ptr [[LLE]], align 8
22160 // CHECK-NEXT:    [[TMP3749:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3748]] monotonic, align 8
22161 // CHECK-NEXT:    store i64 [[TMP3749]], ptr [[LLV]], align 8
22162 // CHECK-NEXT:    [[TMP3750:%.*]] = load i64, ptr [[LLE]], align 8
22163 // CHECK-NEXT:    [[TMP3751:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3750]] monotonic, align 8
22164 // CHECK-NEXT:    store i64 [[TMP3751]], ptr [[LLV]], align 8
22165 // CHECK-NEXT:    [[TMP3752:%.*]] = load i64, ptr [[LLE]], align 8
22166 // CHECK-NEXT:    [[TMP3753:%.*]] = load i64, ptr [[LLD]], align 8
22167 // CHECK-NEXT:    [[TMP3754:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3752]], i64 [[TMP3753]] monotonic monotonic, align 8
22168 // CHECK-NEXT:    [[TMP3755:%.*]] = extractvalue { i64, i1 } [[TMP3754]], 0
22169 // CHECK-NEXT:    store i64 [[TMP3755]], ptr [[LLV]], align 8
22170 // CHECK-NEXT:    [[TMP3756:%.*]] = load i64, ptr [[LLE]], align 8
22171 // CHECK-NEXT:    [[TMP3757:%.*]] = load i64, ptr [[LLD]], align 8
22172 // CHECK-NEXT:    [[TMP3758:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3756]], i64 [[TMP3757]] monotonic monotonic, align 8
22173 // CHECK-NEXT:    [[TMP3759:%.*]] = extractvalue { i64, i1 } [[TMP3758]], 0
22174 // CHECK-NEXT:    store i64 [[TMP3759]], ptr [[LLV]], align 8
22175 // CHECK-NEXT:    [[TMP3760:%.*]] = load i64, ptr [[LLE]], align 8
22176 // CHECK-NEXT:    [[TMP3761:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3760]] monotonic, align 8
22177 // CHECK-NEXT:    [[TMP3762:%.*]] = icmp sgt i64 [[TMP3761]], [[TMP3760]]
22178 // CHECK-NEXT:    [[TMP3763:%.*]] = select i1 [[TMP3762]], i64 [[TMP3760]], i64 [[TMP3761]]
22179 // CHECK-NEXT:    store i64 [[TMP3763]], ptr [[LLV]], align 8
22180 // CHECK-NEXT:    [[TMP3764:%.*]] = load i64, ptr [[LLE]], align 8
22181 // CHECK-NEXT:    [[TMP3765:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3764]] monotonic, align 8
22182 // CHECK-NEXT:    [[TMP3766:%.*]] = icmp slt i64 [[TMP3765]], [[TMP3764]]
22183 // CHECK-NEXT:    [[TMP3767:%.*]] = select i1 [[TMP3766]], i64 [[TMP3764]], i64 [[TMP3765]]
22184 // CHECK-NEXT:    store i64 [[TMP3767]], ptr [[LLV]], align 8
22185 // CHECK-NEXT:    [[TMP3768:%.*]] = load i64, ptr [[LLE]], align 8
22186 // CHECK-NEXT:    [[TMP3769:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3768]] monotonic, align 8
22187 // CHECK-NEXT:    [[TMP3770:%.*]] = icmp slt i64 [[TMP3769]], [[TMP3768]]
22188 // CHECK-NEXT:    [[TMP3771:%.*]] = select i1 [[TMP3770]], i64 [[TMP3768]], i64 [[TMP3769]]
22189 // CHECK-NEXT:    store i64 [[TMP3771]], ptr [[LLV]], align 8
22190 // CHECK-NEXT:    [[TMP3772:%.*]] = load i64, ptr [[LLE]], align 8
22191 // CHECK-NEXT:    [[TMP3773:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3772]] monotonic, align 8
22192 // CHECK-NEXT:    [[TMP3774:%.*]] = icmp sgt i64 [[TMP3773]], [[TMP3772]]
22193 // CHECK-NEXT:    [[TMP3775:%.*]] = select i1 [[TMP3774]], i64 [[TMP3772]], i64 [[TMP3773]]
22194 // CHECK-NEXT:    store i64 [[TMP3775]], ptr [[LLV]], align 8
22195 // CHECK-NEXT:    [[TMP3776:%.*]] = load i64, ptr [[LLE]], align 8
22196 // CHECK-NEXT:    [[TMP3777:%.*]] = load i64, ptr [[LLD]], align 8
22197 // CHECK-NEXT:    [[TMP3778:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3776]], i64 [[TMP3777]] monotonic monotonic, align 8
22198 // CHECK-NEXT:    [[TMP3779:%.*]] = extractvalue { i64, i1 } [[TMP3778]], 0
22199 // CHECK-NEXT:    [[TMP3780:%.*]] = extractvalue { i64, i1 } [[TMP3778]], 1
22200 // CHECK-NEXT:    [[TMP3781:%.*]] = select i1 [[TMP3780]], i64 [[TMP3776]], i64 [[TMP3779]]
22201 // CHECK-NEXT:    store i64 [[TMP3781]], ptr [[LLV]], align 8
22202 // CHECK-NEXT:    [[TMP3782:%.*]] = load i64, ptr [[LLE]], align 8
22203 // CHECK-NEXT:    [[TMP3783:%.*]] = load i64, ptr [[LLD]], align 8
22204 // CHECK-NEXT:    [[TMP3784:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3782]], i64 [[TMP3783]] monotonic monotonic, align 8
22205 // CHECK-NEXT:    [[TMP3785:%.*]] = extractvalue { i64, i1 } [[TMP3784]], 0
22206 // CHECK-NEXT:    [[TMP3786:%.*]] = extractvalue { i64, i1 } [[TMP3784]], 1
22207 // CHECK-NEXT:    [[TMP3787:%.*]] = select i1 [[TMP3786]], i64 [[TMP3782]], i64 [[TMP3785]]
22208 // CHECK-NEXT:    store i64 [[TMP3787]], ptr [[LLV]], align 8
22209 // CHECK-NEXT:    [[TMP3788:%.*]] = load i64, ptr [[LLE]], align 8
22210 // CHECK-NEXT:    [[TMP3789:%.*]] = load i64, ptr [[LLD]], align 8
22211 // CHECK-NEXT:    [[TMP3790:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3788]], i64 [[TMP3789]] monotonic monotonic, align 8
22212 // CHECK-NEXT:    [[TMP3791:%.*]] = extractvalue { i64, i1 } [[TMP3790]], 0
22213 // CHECK-NEXT:    [[TMP3792:%.*]] = extractvalue { i64, i1 } [[TMP3790]], 1
22214 // CHECK-NEXT:    br i1 [[TMP3792]], label [[LLX_ATOMIC_EXIT:%.*]], label [[LLX_ATOMIC_CONT:%.*]]
22215 // CHECK:       llx.atomic.cont:
22216 // CHECK-NEXT:    store i64 [[TMP3791]], ptr [[LLV]], align 8
22217 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT]]
22218 // CHECK:       llx.atomic.exit:
22219 // CHECK-NEXT:    [[TMP3793:%.*]] = load i64, ptr [[LLE]], align 8
22220 // CHECK-NEXT:    [[TMP3794:%.*]] = load i64, ptr [[LLD]], align 8
22221 // CHECK-NEXT:    [[TMP3795:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3793]], i64 [[TMP3794]] monotonic monotonic, align 8
22222 // CHECK-NEXT:    [[TMP3796:%.*]] = extractvalue { i64, i1 } [[TMP3795]], 0
22223 // CHECK-NEXT:    [[TMP3797:%.*]] = extractvalue { i64, i1 } [[TMP3795]], 1
22224 // CHECK-NEXT:    br i1 [[TMP3797]], label [[LLX_ATOMIC_EXIT369:%.*]], label [[LLX_ATOMIC_CONT370:%.*]]
22225 // CHECK:       llx.atomic.cont370:
22226 // CHECK-NEXT:    store i64 [[TMP3796]], ptr [[LLV]], align 8
22227 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT369]]
22228 // CHECK:       llx.atomic.exit369:
22229 // CHECK-NEXT:    [[TMP3798:%.*]] = load i64, ptr [[LLE]], align 8
22230 // CHECK-NEXT:    [[TMP3799:%.*]] = load i64, ptr [[LLD]], align 8
22231 // CHECK-NEXT:    [[TMP3800:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3798]], i64 [[TMP3799]] monotonic monotonic, align 8
22232 // CHECK-NEXT:    [[TMP3801:%.*]] = extractvalue { i64, i1 } [[TMP3800]], 1
22233 // CHECK-NEXT:    [[TMP3802:%.*]] = sext i1 [[TMP3801]] to i64
22234 // CHECK-NEXT:    store i64 [[TMP3802]], ptr [[LLR]], align 8
22235 // CHECK-NEXT:    [[TMP3803:%.*]] = load i64, ptr [[LLE]], align 8
22236 // CHECK-NEXT:    [[TMP3804:%.*]] = load i64, ptr [[LLD]], align 8
22237 // CHECK-NEXT:    [[TMP3805:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3803]], i64 [[TMP3804]] monotonic monotonic, align 8
22238 // CHECK-NEXT:    [[TMP3806:%.*]] = extractvalue { i64, i1 } [[TMP3805]], 1
22239 // CHECK-NEXT:    [[TMP3807:%.*]] = sext i1 [[TMP3806]] to i64
22240 // CHECK-NEXT:    store i64 [[TMP3807]], ptr [[LLR]], align 8
22241 // CHECK-NEXT:    [[TMP3808:%.*]] = load i64, ptr [[LLE]], align 8
22242 // CHECK-NEXT:    [[TMP3809:%.*]] = load i64, ptr [[LLD]], align 8
22243 // CHECK-NEXT:    [[TMP3810:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3808]], i64 [[TMP3809]] monotonic monotonic, align 8
22244 // CHECK-NEXT:    [[TMP3811:%.*]] = extractvalue { i64, i1 } [[TMP3810]], 0
22245 // CHECK-NEXT:    [[TMP3812:%.*]] = extractvalue { i64, i1 } [[TMP3810]], 1
22246 // CHECK-NEXT:    br i1 [[TMP3812]], label [[LLX_ATOMIC_EXIT371:%.*]], label [[LLX_ATOMIC_CONT372:%.*]]
22247 // CHECK:       llx.atomic.cont372:
22248 // CHECK-NEXT:    store i64 [[TMP3811]], ptr [[LLV]], align 8
22249 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT371]]
22250 // CHECK:       llx.atomic.exit371:
22251 // CHECK-NEXT:    [[TMP3813:%.*]] = extractvalue { i64, i1 } [[TMP3810]], 1
22252 // CHECK-NEXT:    [[TMP3814:%.*]] = sext i1 [[TMP3813]] to i64
22253 // CHECK-NEXT:    store i64 [[TMP3814]], ptr [[LLR]], align 8
22254 // CHECK-NEXT:    [[TMP3815:%.*]] = load i64, ptr [[LLE]], align 8
22255 // CHECK-NEXT:    [[TMP3816:%.*]] = load i64, ptr [[LLD]], align 8
22256 // CHECK-NEXT:    [[TMP3817:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3815]], i64 [[TMP3816]] monotonic monotonic, align 8
22257 // CHECK-NEXT:    [[TMP3818:%.*]] = extractvalue { i64, i1 } [[TMP3817]], 0
22258 // CHECK-NEXT:    [[TMP3819:%.*]] = extractvalue { i64, i1 } [[TMP3817]], 1
22259 // CHECK-NEXT:    br i1 [[TMP3819]], label [[LLX_ATOMIC_EXIT373:%.*]], label [[LLX_ATOMIC_CONT374:%.*]]
22260 // CHECK:       llx.atomic.cont374:
22261 // CHECK-NEXT:    store i64 [[TMP3818]], ptr [[LLV]], align 8
22262 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT373]]
22263 // CHECK:       llx.atomic.exit373:
22264 // CHECK-NEXT:    [[TMP3820:%.*]] = extractvalue { i64, i1 } [[TMP3817]], 1
22265 // CHECK-NEXT:    [[TMP3821:%.*]] = sext i1 [[TMP3820]] to i64
22266 // CHECK-NEXT:    store i64 [[TMP3821]], ptr [[LLR]], align 8
22267 // CHECK-NEXT:    [[TMP3822:%.*]] = load i64, ptr [[LLE]], align 8
22268 // CHECK-NEXT:    [[TMP3823:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3822]] acq_rel, align 8
22269 // CHECK-NEXT:    store i64 [[TMP3823]], ptr [[LLV]], align 8
22270 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22271 // CHECK-NEXT:    [[TMP3824:%.*]] = load i64, ptr [[LLE]], align 8
22272 // CHECK-NEXT:    [[TMP3825:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3824]] acq_rel, align 8
22273 // CHECK-NEXT:    store i64 [[TMP3825]], ptr [[LLV]], align 8
22274 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22275 // CHECK-NEXT:    [[TMP3826:%.*]] = load i64, ptr [[LLE]], align 8
22276 // CHECK-NEXT:    [[TMP3827:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3826]] acq_rel, align 8
22277 // CHECK-NEXT:    store i64 [[TMP3827]], ptr [[LLV]], align 8
22278 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22279 // CHECK-NEXT:    [[TMP3828:%.*]] = load i64, ptr [[LLE]], align 8
22280 // CHECK-NEXT:    [[TMP3829:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3828]] acq_rel, align 8
22281 // CHECK-NEXT:    store i64 [[TMP3829]], ptr [[LLV]], align 8
22282 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22283 // CHECK-NEXT:    [[TMP3830:%.*]] = load i64, ptr [[LLE]], align 8
22284 // CHECK-NEXT:    [[TMP3831:%.*]] = load i64, ptr [[LLD]], align 8
22285 // CHECK-NEXT:    [[TMP3832:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3830]], i64 [[TMP3831]] acq_rel acquire, align 8
22286 // CHECK-NEXT:    [[TMP3833:%.*]] = extractvalue { i64, i1 } [[TMP3832]], 0
22287 // CHECK-NEXT:    store i64 [[TMP3833]], ptr [[LLV]], align 8
22288 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22289 // CHECK-NEXT:    [[TMP3834:%.*]] = load i64, ptr [[LLE]], align 8
22290 // CHECK-NEXT:    [[TMP3835:%.*]] = load i64, ptr [[LLD]], align 8
22291 // CHECK-NEXT:    [[TMP3836:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3834]], i64 [[TMP3835]] acq_rel acquire, align 8
22292 // CHECK-NEXT:    [[TMP3837:%.*]] = extractvalue { i64, i1 } [[TMP3836]], 0
22293 // CHECK-NEXT:    store i64 [[TMP3837]], ptr [[LLV]], align 8
22294 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22295 // CHECK-NEXT:    [[TMP3838:%.*]] = load i64, ptr [[LLE]], align 8
22296 // CHECK-NEXT:    [[TMP3839:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3838]] acq_rel, align 8
22297 // CHECK-NEXT:    [[TMP3840:%.*]] = icmp sgt i64 [[TMP3839]], [[TMP3838]]
22298 // CHECK-NEXT:    [[TMP3841:%.*]] = select i1 [[TMP3840]], i64 [[TMP3838]], i64 [[TMP3839]]
22299 // CHECK-NEXT:    store i64 [[TMP3841]], ptr [[LLV]], align 8
22300 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22301 // CHECK-NEXT:    [[TMP3842:%.*]] = load i64, ptr [[LLE]], align 8
22302 // CHECK-NEXT:    [[TMP3843:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3842]] acq_rel, align 8
22303 // CHECK-NEXT:    [[TMP3844:%.*]] = icmp slt i64 [[TMP3843]], [[TMP3842]]
22304 // CHECK-NEXT:    [[TMP3845:%.*]] = select i1 [[TMP3844]], i64 [[TMP3842]], i64 [[TMP3843]]
22305 // CHECK-NEXT:    store i64 [[TMP3845]], ptr [[LLV]], align 8
22306 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22307 // CHECK-NEXT:    [[TMP3846:%.*]] = load i64, ptr [[LLE]], align 8
22308 // CHECK-NEXT:    [[TMP3847:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3846]] acq_rel, align 8
22309 // CHECK-NEXT:    [[TMP3848:%.*]] = icmp slt i64 [[TMP3847]], [[TMP3846]]
22310 // CHECK-NEXT:    [[TMP3849:%.*]] = select i1 [[TMP3848]], i64 [[TMP3846]], i64 [[TMP3847]]
22311 // CHECK-NEXT:    store i64 [[TMP3849]], ptr [[LLV]], align 8
22312 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22313 // CHECK-NEXT:    [[TMP3850:%.*]] = load i64, ptr [[LLE]], align 8
22314 // CHECK-NEXT:    [[TMP3851:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3850]] acq_rel, align 8
22315 // CHECK-NEXT:    [[TMP3852:%.*]] = icmp sgt i64 [[TMP3851]], [[TMP3850]]
22316 // CHECK-NEXT:    [[TMP3853:%.*]] = select i1 [[TMP3852]], i64 [[TMP3850]], i64 [[TMP3851]]
22317 // CHECK-NEXT:    store i64 [[TMP3853]], ptr [[LLV]], align 8
22318 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22319 // CHECK-NEXT:    [[TMP3854:%.*]] = load i64, ptr [[LLE]], align 8
22320 // CHECK-NEXT:    [[TMP3855:%.*]] = load i64, ptr [[LLD]], align 8
22321 // CHECK-NEXT:    [[TMP3856:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3854]], i64 [[TMP3855]] acq_rel acquire, align 8
22322 // CHECK-NEXT:    [[TMP3857:%.*]] = extractvalue { i64, i1 } [[TMP3856]], 0
22323 // CHECK-NEXT:    [[TMP3858:%.*]] = extractvalue { i64, i1 } [[TMP3856]], 1
22324 // CHECK-NEXT:    [[TMP3859:%.*]] = select i1 [[TMP3858]], i64 [[TMP3854]], i64 [[TMP3857]]
22325 // CHECK-NEXT:    store i64 [[TMP3859]], ptr [[LLV]], align 8
22326 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22327 // CHECK-NEXT:    [[TMP3860:%.*]] = load i64, ptr [[LLE]], align 8
22328 // CHECK-NEXT:    [[TMP3861:%.*]] = load i64, ptr [[LLD]], align 8
22329 // CHECK-NEXT:    [[TMP3862:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3860]], i64 [[TMP3861]] acq_rel acquire, align 8
22330 // CHECK-NEXT:    [[TMP3863:%.*]] = extractvalue { i64, i1 } [[TMP3862]], 0
22331 // CHECK-NEXT:    [[TMP3864:%.*]] = extractvalue { i64, i1 } [[TMP3862]], 1
22332 // CHECK-NEXT:    [[TMP3865:%.*]] = select i1 [[TMP3864]], i64 [[TMP3860]], i64 [[TMP3863]]
22333 // CHECK-NEXT:    store i64 [[TMP3865]], ptr [[LLV]], align 8
22334 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22335 // CHECK-NEXT:    [[TMP3866:%.*]] = load i64, ptr [[LLE]], align 8
22336 // CHECK-NEXT:    [[TMP3867:%.*]] = load i64, ptr [[LLD]], align 8
22337 // CHECK-NEXT:    [[TMP3868:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3866]], i64 [[TMP3867]] acq_rel acquire, align 8
22338 // CHECK-NEXT:    [[TMP3869:%.*]] = extractvalue { i64, i1 } [[TMP3868]], 0
22339 // CHECK-NEXT:    [[TMP3870:%.*]] = extractvalue { i64, i1 } [[TMP3868]], 1
22340 // CHECK-NEXT:    br i1 [[TMP3870]], label [[LLX_ATOMIC_EXIT375:%.*]], label [[LLX_ATOMIC_CONT376:%.*]]
22341 // CHECK:       llx.atomic.cont376:
22342 // CHECK-NEXT:    store i64 [[TMP3869]], ptr [[LLV]], align 8
22343 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT375]]
22344 // CHECK:       llx.atomic.exit375:
22345 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22346 // CHECK-NEXT:    [[TMP3871:%.*]] = load i64, ptr [[LLE]], align 8
22347 // CHECK-NEXT:    [[TMP3872:%.*]] = load i64, ptr [[LLD]], align 8
22348 // CHECK-NEXT:    [[TMP3873:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3871]], i64 [[TMP3872]] acq_rel acquire, align 8
22349 // CHECK-NEXT:    [[TMP3874:%.*]] = extractvalue { i64, i1 } [[TMP3873]], 0
22350 // CHECK-NEXT:    [[TMP3875:%.*]] = extractvalue { i64, i1 } [[TMP3873]], 1
22351 // CHECK-NEXT:    br i1 [[TMP3875]], label [[LLX_ATOMIC_EXIT377:%.*]], label [[LLX_ATOMIC_CONT378:%.*]]
22352 // CHECK:       llx.atomic.cont378:
22353 // CHECK-NEXT:    store i64 [[TMP3874]], ptr [[LLV]], align 8
22354 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT377]]
22355 // CHECK:       llx.atomic.exit377:
22356 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22357 // CHECK-NEXT:    [[TMP3876:%.*]] = load i64, ptr [[LLE]], align 8
22358 // CHECK-NEXT:    [[TMP3877:%.*]] = load i64, ptr [[LLD]], align 8
22359 // CHECK-NEXT:    [[TMP3878:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3876]], i64 [[TMP3877]] acq_rel acquire, align 8
22360 // CHECK-NEXT:    [[TMP3879:%.*]] = extractvalue { i64, i1 } [[TMP3878]], 1
22361 // CHECK-NEXT:    [[TMP3880:%.*]] = sext i1 [[TMP3879]] to i64
22362 // CHECK-NEXT:    store i64 [[TMP3880]], ptr [[LLR]], align 8
22363 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22364 // CHECK-NEXT:    [[TMP3881:%.*]] = load i64, ptr [[LLE]], align 8
22365 // CHECK-NEXT:    [[TMP3882:%.*]] = load i64, ptr [[LLD]], align 8
22366 // CHECK-NEXT:    [[TMP3883:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3881]], i64 [[TMP3882]] acq_rel acquire, align 8
22367 // CHECK-NEXT:    [[TMP3884:%.*]] = extractvalue { i64, i1 } [[TMP3883]], 1
22368 // CHECK-NEXT:    [[TMP3885:%.*]] = sext i1 [[TMP3884]] to i64
22369 // CHECK-NEXT:    store i64 [[TMP3885]], ptr [[LLR]], align 8
22370 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22371 // CHECK-NEXT:    [[TMP3886:%.*]] = load i64, ptr [[LLE]], align 8
22372 // CHECK-NEXT:    [[TMP3887:%.*]] = load i64, ptr [[LLD]], align 8
22373 // CHECK-NEXT:    [[TMP3888:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3886]], i64 [[TMP3887]] acq_rel acquire, align 8
22374 // CHECK-NEXT:    [[TMP3889:%.*]] = extractvalue { i64, i1 } [[TMP3888]], 0
22375 // CHECK-NEXT:    [[TMP3890:%.*]] = extractvalue { i64, i1 } [[TMP3888]], 1
22376 // CHECK-NEXT:    br i1 [[TMP3890]], label [[LLX_ATOMIC_EXIT379:%.*]], label [[LLX_ATOMIC_CONT380:%.*]]
22377 // CHECK:       llx.atomic.cont380:
22378 // CHECK-NEXT:    store i64 [[TMP3889]], ptr [[LLV]], align 8
22379 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT379]]
22380 // CHECK:       llx.atomic.exit379:
22381 // CHECK-NEXT:    [[TMP3891:%.*]] = extractvalue { i64, i1 } [[TMP3888]], 1
22382 // CHECK-NEXT:    [[TMP3892:%.*]] = sext i1 [[TMP3891]] to i64
22383 // CHECK-NEXT:    store i64 [[TMP3892]], ptr [[LLR]], align 8
22384 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22385 // CHECK-NEXT:    [[TMP3893:%.*]] = load i64, ptr [[LLE]], align 8
22386 // CHECK-NEXT:    [[TMP3894:%.*]] = load i64, ptr [[LLD]], align 8
22387 // CHECK-NEXT:    [[TMP3895:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3893]], i64 [[TMP3894]] acq_rel acquire, align 8
22388 // CHECK-NEXT:    [[TMP3896:%.*]] = extractvalue { i64, i1 } [[TMP3895]], 0
22389 // CHECK-NEXT:    [[TMP3897:%.*]] = extractvalue { i64, i1 } [[TMP3895]], 1
22390 // CHECK-NEXT:    br i1 [[TMP3897]], label [[LLX_ATOMIC_EXIT381:%.*]], label [[LLX_ATOMIC_CONT382:%.*]]
22391 // CHECK:       llx.atomic.cont382:
22392 // CHECK-NEXT:    store i64 [[TMP3896]], ptr [[LLV]], align 8
22393 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT381]]
22394 // CHECK:       llx.atomic.exit381:
22395 // CHECK-NEXT:    [[TMP3898:%.*]] = extractvalue { i64, i1 } [[TMP3895]], 1
22396 // CHECK-NEXT:    [[TMP3899:%.*]] = sext i1 [[TMP3898]] to i64
22397 // CHECK-NEXT:    store i64 [[TMP3899]], ptr [[LLR]], align 8
22398 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22399 // CHECK-NEXT:    [[TMP3900:%.*]] = load i64, ptr [[LLE]], align 8
22400 // CHECK-NEXT:    [[TMP3901:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3900]] acquire, align 8
22401 // CHECK-NEXT:    store i64 [[TMP3901]], ptr [[LLV]], align 8
22402 // CHECK-NEXT:    [[TMP3902:%.*]] = load i64, ptr [[LLE]], align 8
22403 // CHECK-NEXT:    [[TMP3903:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3902]] acquire, align 8
22404 // CHECK-NEXT:    store i64 [[TMP3903]], ptr [[LLV]], align 8
22405 // CHECK-NEXT:    [[TMP3904:%.*]] = load i64, ptr [[LLE]], align 8
22406 // CHECK-NEXT:    [[TMP3905:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3904]] acquire, align 8
22407 // CHECK-NEXT:    store i64 [[TMP3905]], ptr [[LLV]], align 8
22408 // CHECK-NEXT:    [[TMP3906:%.*]] = load i64, ptr [[LLE]], align 8
22409 // CHECK-NEXT:    [[TMP3907:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3906]] acquire, align 8
22410 // CHECK-NEXT:    store i64 [[TMP3907]], ptr [[LLV]], align 8
22411 // CHECK-NEXT:    [[TMP3908:%.*]] = load i64, ptr [[LLE]], align 8
22412 // CHECK-NEXT:    [[TMP3909:%.*]] = load i64, ptr [[LLD]], align 8
22413 // CHECK-NEXT:    [[TMP3910:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3908]], i64 [[TMP3909]] acquire acquire, align 8
22414 // CHECK-NEXT:    [[TMP3911:%.*]] = extractvalue { i64, i1 } [[TMP3910]], 0
22415 // CHECK-NEXT:    store i64 [[TMP3911]], ptr [[LLV]], align 8
22416 // CHECK-NEXT:    [[TMP3912:%.*]] = load i64, ptr [[LLE]], align 8
22417 // CHECK-NEXT:    [[TMP3913:%.*]] = load i64, ptr [[LLD]], align 8
22418 // CHECK-NEXT:    [[TMP3914:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3912]], i64 [[TMP3913]] acquire acquire, align 8
22419 // CHECK-NEXT:    [[TMP3915:%.*]] = extractvalue { i64, i1 } [[TMP3914]], 0
22420 // CHECK-NEXT:    store i64 [[TMP3915]], ptr [[LLV]], align 8
22421 // CHECK-NEXT:    [[TMP3916:%.*]] = load i64, ptr [[LLE]], align 8
22422 // CHECK-NEXT:    [[TMP3917:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3916]] acquire, align 8
22423 // CHECK-NEXT:    [[TMP3918:%.*]] = icmp sgt i64 [[TMP3917]], [[TMP3916]]
22424 // CHECK-NEXT:    [[TMP3919:%.*]] = select i1 [[TMP3918]], i64 [[TMP3916]], i64 [[TMP3917]]
22425 // CHECK-NEXT:    store i64 [[TMP3919]], ptr [[LLV]], align 8
22426 // CHECK-NEXT:    [[TMP3920:%.*]] = load i64, ptr [[LLE]], align 8
22427 // CHECK-NEXT:    [[TMP3921:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3920]] acquire, align 8
22428 // CHECK-NEXT:    [[TMP3922:%.*]] = icmp slt i64 [[TMP3921]], [[TMP3920]]
22429 // CHECK-NEXT:    [[TMP3923:%.*]] = select i1 [[TMP3922]], i64 [[TMP3920]], i64 [[TMP3921]]
22430 // CHECK-NEXT:    store i64 [[TMP3923]], ptr [[LLV]], align 8
22431 // CHECK-NEXT:    [[TMP3924:%.*]] = load i64, ptr [[LLE]], align 8
22432 // CHECK-NEXT:    [[TMP3925:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3924]] acquire, align 8
22433 // CHECK-NEXT:    [[TMP3926:%.*]] = icmp slt i64 [[TMP3925]], [[TMP3924]]
22434 // CHECK-NEXT:    [[TMP3927:%.*]] = select i1 [[TMP3926]], i64 [[TMP3924]], i64 [[TMP3925]]
22435 // CHECK-NEXT:    store i64 [[TMP3927]], ptr [[LLV]], align 8
22436 // CHECK-NEXT:    [[TMP3928:%.*]] = load i64, ptr [[LLE]], align 8
22437 // CHECK-NEXT:    [[TMP3929:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3928]] acquire, align 8
22438 // CHECK-NEXT:    [[TMP3930:%.*]] = icmp sgt i64 [[TMP3929]], [[TMP3928]]
22439 // CHECK-NEXT:    [[TMP3931:%.*]] = select i1 [[TMP3930]], i64 [[TMP3928]], i64 [[TMP3929]]
22440 // CHECK-NEXT:    store i64 [[TMP3931]], ptr [[LLV]], align 8
22441 // CHECK-NEXT:    [[TMP3932:%.*]] = load i64, ptr [[LLE]], align 8
22442 // CHECK-NEXT:    [[TMP3933:%.*]] = load i64, ptr [[LLD]], align 8
22443 // CHECK-NEXT:    [[TMP3934:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3932]], i64 [[TMP3933]] acquire acquire, align 8
22444 // CHECK-NEXT:    [[TMP3935:%.*]] = extractvalue { i64, i1 } [[TMP3934]], 0
22445 // CHECK-NEXT:    [[TMP3936:%.*]] = extractvalue { i64, i1 } [[TMP3934]], 1
22446 // CHECK-NEXT:    [[TMP3937:%.*]] = select i1 [[TMP3936]], i64 [[TMP3932]], i64 [[TMP3935]]
22447 // CHECK-NEXT:    store i64 [[TMP3937]], ptr [[LLV]], align 8
22448 // CHECK-NEXT:    [[TMP3938:%.*]] = load i64, ptr [[LLE]], align 8
22449 // CHECK-NEXT:    [[TMP3939:%.*]] = load i64, ptr [[LLD]], align 8
22450 // CHECK-NEXT:    [[TMP3940:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3938]], i64 [[TMP3939]] acquire acquire, align 8
22451 // CHECK-NEXT:    [[TMP3941:%.*]] = extractvalue { i64, i1 } [[TMP3940]], 0
22452 // CHECK-NEXT:    [[TMP3942:%.*]] = extractvalue { i64, i1 } [[TMP3940]], 1
22453 // CHECK-NEXT:    [[TMP3943:%.*]] = select i1 [[TMP3942]], i64 [[TMP3938]], i64 [[TMP3941]]
22454 // CHECK-NEXT:    store i64 [[TMP3943]], ptr [[LLV]], align 8
22455 // CHECK-NEXT:    [[TMP3944:%.*]] = load i64, ptr [[LLE]], align 8
22456 // CHECK-NEXT:    [[TMP3945:%.*]] = load i64, ptr [[LLD]], align 8
22457 // CHECK-NEXT:    [[TMP3946:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3944]], i64 [[TMP3945]] acquire acquire, align 8
22458 // CHECK-NEXT:    [[TMP3947:%.*]] = extractvalue { i64, i1 } [[TMP3946]], 0
22459 // CHECK-NEXT:    [[TMP3948:%.*]] = extractvalue { i64, i1 } [[TMP3946]], 1
22460 // CHECK-NEXT:    br i1 [[TMP3948]], label [[LLX_ATOMIC_EXIT383:%.*]], label [[LLX_ATOMIC_CONT384:%.*]]
22461 // CHECK:       llx.atomic.cont384:
22462 // CHECK-NEXT:    store i64 [[TMP3947]], ptr [[LLV]], align 8
22463 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT383]]
22464 // CHECK:       llx.atomic.exit383:
22465 // CHECK-NEXT:    [[TMP3949:%.*]] = load i64, ptr [[LLE]], align 8
22466 // CHECK-NEXT:    [[TMP3950:%.*]] = load i64, ptr [[LLD]], align 8
22467 // CHECK-NEXT:    [[TMP3951:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3949]], i64 [[TMP3950]] acquire acquire, align 8
22468 // CHECK-NEXT:    [[TMP3952:%.*]] = extractvalue { i64, i1 } [[TMP3951]], 0
22469 // CHECK-NEXT:    [[TMP3953:%.*]] = extractvalue { i64, i1 } [[TMP3951]], 1
22470 // CHECK-NEXT:    br i1 [[TMP3953]], label [[LLX_ATOMIC_EXIT385:%.*]], label [[LLX_ATOMIC_CONT386:%.*]]
22471 // CHECK:       llx.atomic.cont386:
22472 // CHECK-NEXT:    store i64 [[TMP3952]], ptr [[LLV]], align 8
22473 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT385]]
22474 // CHECK:       llx.atomic.exit385:
22475 // CHECK-NEXT:    [[TMP3954:%.*]] = load i64, ptr [[LLE]], align 8
22476 // CHECK-NEXT:    [[TMP3955:%.*]] = load i64, ptr [[LLD]], align 8
22477 // CHECK-NEXT:    [[TMP3956:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3954]], i64 [[TMP3955]] acquire acquire, align 8
22478 // CHECK-NEXT:    [[TMP3957:%.*]] = extractvalue { i64, i1 } [[TMP3956]], 1
22479 // CHECK-NEXT:    [[TMP3958:%.*]] = sext i1 [[TMP3957]] to i64
22480 // CHECK-NEXT:    store i64 [[TMP3958]], ptr [[LLR]], align 8
22481 // CHECK-NEXT:    [[TMP3959:%.*]] = load i64, ptr [[LLE]], align 8
22482 // CHECK-NEXT:    [[TMP3960:%.*]] = load i64, ptr [[LLD]], align 8
22483 // CHECK-NEXT:    [[TMP3961:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3959]], i64 [[TMP3960]] acquire acquire, align 8
22484 // CHECK-NEXT:    [[TMP3962:%.*]] = extractvalue { i64, i1 } [[TMP3961]], 1
22485 // CHECK-NEXT:    [[TMP3963:%.*]] = sext i1 [[TMP3962]] to i64
22486 // CHECK-NEXT:    store i64 [[TMP3963]], ptr [[LLR]], align 8
22487 // CHECK-NEXT:    [[TMP3964:%.*]] = load i64, ptr [[LLE]], align 8
22488 // CHECK-NEXT:    [[TMP3965:%.*]] = load i64, ptr [[LLD]], align 8
22489 // CHECK-NEXT:    [[TMP3966:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3964]], i64 [[TMP3965]] acquire acquire, align 8
22490 // CHECK-NEXT:    [[TMP3967:%.*]] = extractvalue { i64, i1 } [[TMP3966]], 0
22491 // CHECK-NEXT:    [[TMP3968:%.*]] = extractvalue { i64, i1 } [[TMP3966]], 1
22492 // CHECK-NEXT:    br i1 [[TMP3968]], label [[LLX_ATOMIC_EXIT387:%.*]], label [[LLX_ATOMIC_CONT388:%.*]]
22493 // CHECK:       llx.atomic.cont388:
22494 // CHECK-NEXT:    store i64 [[TMP3967]], ptr [[LLV]], align 8
22495 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT387]]
22496 // CHECK:       llx.atomic.exit387:
22497 // CHECK-NEXT:    [[TMP3969:%.*]] = extractvalue { i64, i1 } [[TMP3966]], 1
22498 // CHECK-NEXT:    [[TMP3970:%.*]] = sext i1 [[TMP3969]] to i64
22499 // CHECK-NEXT:    store i64 [[TMP3970]], ptr [[LLR]], align 8
22500 // CHECK-NEXT:    [[TMP3971:%.*]] = load i64, ptr [[LLE]], align 8
22501 // CHECK-NEXT:    [[TMP3972:%.*]] = load i64, ptr [[LLD]], align 8
22502 // CHECK-NEXT:    [[TMP3973:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3971]], i64 [[TMP3972]] acquire acquire, align 8
22503 // CHECK-NEXT:    [[TMP3974:%.*]] = extractvalue { i64, i1 } [[TMP3973]], 0
22504 // CHECK-NEXT:    [[TMP3975:%.*]] = extractvalue { i64, i1 } [[TMP3973]], 1
22505 // CHECK-NEXT:    br i1 [[TMP3975]], label [[LLX_ATOMIC_EXIT389:%.*]], label [[LLX_ATOMIC_CONT390:%.*]]
22506 // CHECK:       llx.atomic.cont390:
22507 // CHECK-NEXT:    store i64 [[TMP3974]], ptr [[LLV]], align 8
22508 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT389]]
22509 // CHECK:       llx.atomic.exit389:
22510 // CHECK-NEXT:    [[TMP3976:%.*]] = extractvalue { i64, i1 } [[TMP3973]], 1
22511 // CHECK-NEXT:    [[TMP3977:%.*]] = sext i1 [[TMP3976]] to i64
22512 // CHECK-NEXT:    store i64 [[TMP3977]], ptr [[LLR]], align 8
22513 // CHECK-NEXT:    [[TMP3978:%.*]] = load i64, ptr [[LLE]], align 8
22514 // CHECK-NEXT:    [[TMP3979:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3978]] monotonic, align 8
22515 // CHECK-NEXT:    store i64 [[TMP3979]], ptr [[LLV]], align 8
22516 // CHECK-NEXT:    [[TMP3980:%.*]] = load i64, ptr [[LLE]], align 8
22517 // CHECK-NEXT:    [[TMP3981:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3980]] monotonic, align 8
22518 // CHECK-NEXT:    store i64 [[TMP3981]], ptr [[LLV]], align 8
22519 // CHECK-NEXT:    [[TMP3982:%.*]] = load i64, ptr [[LLE]], align 8
22520 // CHECK-NEXT:    [[TMP3983:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3982]] monotonic, align 8
22521 // CHECK-NEXT:    store i64 [[TMP3983]], ptr [[LLV]], align 8
22522 // CHECK-NEXT:    [[TMP3984:%.*]] = load i64, ptr [[LLE]], align 8
22523 // CHECK-NEXT:    [[TMP3985:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3984]] monotonic, align 8
22524 // CHECK-NEXT:    store i64 [[TMP3985]], ptr [[LLV]], align 8
22525 // CHECK-NEXT:    [[TMP3986:%.*]] = load i64, ptr [[LLE]], align 8
22526 // CHECK-NEXT:    [[TMP3987:%.*]] = load i64, ptr [[LLD]], align 8
22527 // CHECK-NEXT:    [[TMP3988:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3986]], i64 [[TMP3987]] monotonic monotonic, align 8
22528 // CHECK-NEXT:    [[TMP3989:%.*]] = extractvalue { i64, i1 } [[TMP3988]], 0
22529 // CHECK-NEXT:    store i64 [[TMP3989]], ptr [[LLV]], align 8
22530 // CHECK-NEXT:    [[TMP3990:%.*]] = load i64, ptr [[LLE]], align 8
22531 // CHECK-NEXT:    [[TMP3991:%.*]] = load i64, ptr [[LLD]], align 8
22532 // CHECK-NEXT:    [[TMP3992:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3990]], i64 [[TMP3991]] monotonic monotonic, align 8
22533 // CHECK-NEXT:    [[TMP3993:%.*]] = extractvalue { i64, i1 } [[TMP3992]], 0
22534 // CHECK-NEXT:    store i64 [[TMP3993]], ptr [[LLV]], align 8
22535 // CHECK-NEXT:    [[TMP3994:%.*]] = load i64, ptr [[LLE]], align 8
22536 // CHECK-NEXT:    [[TMP3995:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3994]] monotonic, align 8
22537 // CHECK-NEXT:    [[TMP3996:%.*]] = icmp sgt i64 [[TMP3995]], [[TMP3994]]
22538 // CHECK-NEXT:    [[TMP3997:%.*]] = select i1 [[TMP3996]], i64 [[TMP3994]], i64 [[TMP3995]]
22539 // CHECK-NEXT:    store i64 [[TMP3997]], ptr [[LLV]], align 8
22540 // CHECK-NEXT:    [[TMP3998:%.*]] = load i64, ptr [[LLE]], align 8
22541 // CHECK-NEXT:    [[TMP3999:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3998]] monotonic, align 8
22542 // CHECK-NEXT:    [[TMP4000:%.*]] = icmp slt i64 [[TMP3999]], [[TMP3998]]
22543 // CHECK-NEXT:    [[TMP4001:%.*]] = select i1 [[TMP4000]], i64 [[TMP3998]], i64 [[TMP3999]]
22544 // CHECK-NEXT:    store i64 [[TMP4001]], ptr [[LLV]], align 8
22545 // CHECK-NEXT:    [[TMP4002:%.*]] = load i64, ptr [[LLE]], align 8
22546 // CHECK-NEXT:    [[TMP4003:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4002]] monotonic, align 8
22547 // CHECK-NEXT:    [[TMP4004:%.*]] = icmp slt i64 [[TMP4003]], [[TMP4002]]
22548 // CHECK-NEXT:    [[TMP4005:%.*]] = select i1 [[TMP4004]], i64 [[TMP4002]], i64 [[TMP4003]]
22549 // CHECK-NEXT:    store i64 [[TMP4005]], ptr [[LLV]], align 8
22550 // CHECK-NEXT:    [[TMP4006:%.*]] = load i64, ptr [[LLE]], align 8
22551 // CHECK-NEXT:    [[TMP4007:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4006]] monotonic, align 8
22552 // CHECK-NEXT:    [[TMP4008:%.*]] = icmp sgt i64 [[TMP4007]], [[TMP4006]]
22553 // CHECK-NEXT:    [[TMP4009:%.*]] = select i1 [[TMP4008]], i64 [[TMP4006]], i64 [[TMP4007]]
22554 // CHECK-NEXT:    store i64 [[TMP4009]], ptr [[LLV]], align 8
22555 // CHECK-NEXT:    [[TMP4010:%.*]] = load i64, ptr [[LLE]], align 8
22556 // CHECK-NEXT:    [[TMP4011:%.*]] = load i64, ptr [[LLD]], align 8
22557 // CHECK-NEXT:    [[TMP4012:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4010]], i64 [[TMP4011]] monotonic monotonic, align 8
22558 // CHECK-NEXT:    [[TMP4013:%.*]] = extractvalue { i64, i1 } [[TMP4012]], 0
22559 // CHECK-NEXT:    [[TMP4014:%.*]] = extractvalue { i64, i1 } [[TMP4012]], 1
22560 // CHECK-NEXT:    [[TMP4015:%.*]] = select i1 [[TMP4014]], i64 [[TMP4010]], i64 [[TMP4013]]
22561 // CHECK-NEXT:    store i64 [[TMP4015]], ptr [[LLV]], align 8
22562 // CHECK-NEXT:    [[TMP4016:%.*]] = load i64, ptr [[LLE]], align 8
22563 // CHECK-NEXT:    [[TMP4017:%.*]] = load i64, ptr [[LLD]], align 8
22564 // CHECK-NEXT:    [[TMP4018:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4016]], i64 [[TMP4017]] monotonic monotonic, align 8
22565 // CHECK-NEXT:    [[TMP4019:%.*]] = extractvalue { i64, i1 } [[TMP4018]], 0
22566 // CHECK-NEXT:    [[TMP4020:%.*]] = extractvalue { i64, i1 } [[TMP4018]], 1
22567 // CHECK-NEXT:    [[TMP4021:%.*]] = select i1 [[TMP4020]], i64 [[TMP4016]], i64 [[TMP4019]]
22568 // CHECK-NEXT:    store i64 [[TMP4021]], ptr [[LLV]], align 8
22569 // CHECK-NEXT:    [[TMP4022:%.*]] = load i64, ptr [[LLE]], align 8
22570 // CHECK-NEXT:    [[TMP4023:%.*]] = load i64, ptr [[LLD]], align 8
22571 // CHECK-NEXT:    [[TMP4024:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4022]], i64 [[TMP4023]] monotonic monotonic, align 8
22572 // CHECK-NEXT:    [[TMP4025:%.*]] = extractvalue { i64, i1 } [[TMP4024]], 0
22573 // CHECK-NEXT:    [[TMP4026:%.*]] = extractvalue { i64, i1 } [[TMP4024]], 1
22574 // CHECK-NEXT:    br i1 [[TMP4026]], label [[LLX_ATOMIC_EXIT391:%.*]], label [[LLX_ATOMIC_CONT392:%.*]]
22575 // CHECK:       llx.atomic.cont392:
22576 // CHECK-NEXT:    store i64 [[TMP4025]], ptr [[LLV]], align 8
22577 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT391]]
22578 // CHECK:       llx.atomic.exit391:
22579 // CHECK-NEXT:    [[TMP4027:%.*]] = load i64, ptr [[LLE]], align 8
22580 // CHECK-NEXT:    [[TMP4028:%.*]] = load i64, ptr [[LLD]], align 8
22581 // CHECK-NEXT:    [[TMP4029:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4027]], i64 [[TMP4028]] monotonic monotonic, align 8
22582 // CHECK-NEXT:    [[TMP4030:%.*]] = extractvalue { i64, i1 } [[TMP4029]], 0
22583 // CHECK-NEXT:    [[TMP4031:%.*]] = extractvalue { i64, i1 } [[TMP4029]], 1
22584 // CHECK-NEXT:    br i1 [[TMP4031]], label [[LLX_ATOMIC_EXIT393:%.*]], label [[LLX_ATOMIC_CONT394:%.*]]
22585 // CHECK:       llx.atomic.cont394:
22586 // CHECK-NEXT:    store i64 [[TMP4030]], ptr [[LLV]], align 8
22587 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT393]]
22588 // CHECK:       llx.atomic.exit393:
22589 // CHECK-NEXT:    [[TMP4032:%.*]] = load i64, ptr [[LLE]], align 8
22590 // CHECK-NEXT:    [[TMP4033:%.*]] = load i64, ptr [[LLD]], align 8
22591 // CHECK-NEXT:    [[TMP4034:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4032]], i64 [[TMP4033]] monotonic monotonic, align 8
22592 // CHECK-NEXT:    [[TMP4035:%.*]] = extractvalue { i64, i1 } [[TMP4034]], 1
22593 // CHECK-NEXT:    [[TMP4036:%.*]] = sext i1 [[TMP4035]] to i64
22594 // CHECK-NEXT:    store i64 [[TMP4036]], ptr [[LLR]], align 8
22595 // CHECK-NEXT:    [[TMP4037:%.*]] = load i64, ptr [[LLE]], align 8
22596 // CHECK-NEXT:    [[TMP4038:%.*]] = load i64, ptr [[LLD]], align 8
22597 // CHECK-NEXT:    [[TMP4039:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4037]], i64 [[TMP4038]] monotonic monotonic, align 8
22598 // CHECK-NEXT:    [[TMP4040:%.*]] = extractvalue { i64, i1 } [[TMP4039]], 1
22599 // CHECK-NEXT:    [[TMP4041:%.*]] = sext i1 [[TMP4040]] to i64
22600 // CHECK-NEXT:    store i64 [[TMP4041]], ptr [[LLR]], align 8
22601 // CHECK-NEXT:    [[TMP4042:%.*]] = load i64, ptr [[LLE]], align 8
22602 // CHECK-NEXT:    [[TMP4043:%.*]] = load i64, ptr [[LLD]], align 8
22603 // CHECK-NEXT:    [[TMP4044:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4042]], i64 [[TMP4043]] monotonic monotonic, align 8
22604 // CHECK-NEXT:    [[TMP4045:%.*]] = extractvalue { i64, i1 } [[TMP4044]], 0
22605 // CHECK-NEXT:    [[TMP4046:%.*]] = extractvalue { i64, i1 } [[TMP4044]], 1
22606 // CHECK-NEXT:    br i1 [[TMP4046]], label [[LLX_ATOMIC_EXIT395:%.*]], label [[LLX_ATOMIC_CONT396:%.*]]
22607 // CHECK:       llx.atomic.cont396:
22608 // CHECK-NEXT:    store i64 [[TMP4045]], ptr [[LLV]], align 8
22609 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT395]]
22610 // CHECK:       llx.atomic.exit395:
22611 // CHECK-NEXT:    [[TMP4047:%.*]] = extractvalue { i64, i1 } [[TMP4044]], 1
22612 // CHECK-NEXT:    [[TMP4048:%.*]] = sext i1 [[TMP4047]] to i64
22613 // CHECK-NEXT:    store i64 [[TMP4048]], ptr [[LLR]], align 8
22614 // CHECK-NEXT:    [[TMP4049:%.*]] = load i64, ptr [[LLE]], align 8
22615 // CHECK-NEXT:    [[TMP4050:%.*]] = load i64, ptr [[LLD]], align 8
22616 // CHECK-NEXT:    [[TMP4051:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4049]], i64 [[TMP4050]] monotonic monotonic, align 8
22617 // CHECK-NEXT:    [[TMP4052:%.*]] = extractvalue { i64, i1 } [[TMP4051]], 0
22618 // CHECK-NEXT:    [[TMP4053:%.*]] = extractvalue { i64, i1 } [[TMP4051]], 1
22619 // CHECK-NEXT:    br i1 [[TMP4053]], label [[LLX_ATOMIC_EXIT397:%.*]], label [[LLX_ATOMIC_CONT398:%.*]]
22620 // CHECK:       llx.atomic.cont398:
22621 // CHECK-NEXT:    store i64 [[TMP4052]], ptr [[LLV]], align 8
22622 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT397]]
22623 // CHECK:       llx.atomic.exit397:
22624 // CHECK-NEXT:    [[TMP4054:%.*]] = extractvalue { i64, i1 } [[TMP4051]], 1
22625 // CHECK-NEXT:    [[TMP4055:%.*]] = sext i1 [[TMP4054]] to i64
22626 // CHECK-NEXT:    store i64 [[TMP4055]], ptr [[LLR]], align 8
22627 // CHECK-NEXT:    [[TMP4056:%.*]] = load i64, ptr [[LLE]], align 8
22628 // CHECK-NEXT:    [[TMP4057:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4056]] release, align 8
22629 // CHECK-NEXT:    store i64 [[TMP4057]], ptr [[LLV]], align 8
22630 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22631 // CHECK-NEXT:    [[TMP4058:%.*]] = load i64, ptr [[LLE]], align 8
22632 // CHECK-NEXT:    [[TMP4059:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4058]] release, align 8
22633 // CHECK-NEXT:    store i64 [[TMP4059]], ptr [[LLV]], align 8
22634 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22635 // CHECK-NEXT:    [[TMP4060:%.*]] = load i64, ptr [[LLE]], align 8
22636 // CHECK-NEXT:    [[TMP4061:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4060]] release, align 8
22637 // CHECK-NEXT:    store i64 [[TMP4061]], ptr [[LLV]], align 8
22638 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22639 // CHECK-NEXT:    [[TMP4062:%.*]] = load i64, ptr [[LLE]], align 8
22640 // CHECK-NEXT:    [[TMP4063:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4062]] release, align 8
22641 // CHECK-NEXT:    store i64 [[TMP4063]], ptr [[LLV]], align 8
22642 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22643 // CHECK-NEXT:    [[TMP4064:%.*]] = load i64, ptr [[LLE]], align 8
22644 // CHECK-NEXT:    [[TMP4065:%.*]] = load i64, ptr [[LLD]], align 8
22645 // CHECK-NEXT:    [[TMP4066:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4064]], i64 [[TMP4065]] release monotonic, align 8
22646 // CHECK-NEXT:    [[TMP4067:%.*]] = extractvalue { i64, i1 } [[TMP4066]], 0
22647 // CHECK-NEXT:    store i64 [[TMP4067]], ptr [[LLV]], align 8
22648 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22649 // CHECK-NEXT:    [[TMP4068:%.*]] = load i64, ptr [[LLE]], align 8
22650 // CHECK-NEXT:    [[TMP4069:%.*]] = load i64, ptr [[LLD]], align 8
22651 // CHECK-NEXT:    [[TMP4070:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4068]], i64 [[TMP4069]] release monotonic, align 8
22652 // CHECK-NEXT:    [[TMP4071:%.*]] = extractvalue { i64, i1 } [[TMP4070]], 0
22653 // CHECK-NEXT:    store i64 [[TMP4071]], ptr [[LLV]], align 8
22654 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22655 // CHECK-NEXT:    [[TMP4072:%.*]] = load i64, ptr [[LLE]], align 8
22656 // CHECK-NEXT:    [[TMP4073:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4072]] release, align 8
22657 // CHECK-NEXT:    [[TMP4074:%.*]] = icmp sgt i64 [[TMP4073]], [[TMP4072]]
22658 // CHECK-NEXT:    [[TMP4075:%.*]] = select i1 [[TMP4074]], i64 [[TMP4072]], i64 [[TMP4073]]
22659 // CHECK-NEXT:    store i64 [[TMP4075]], ptr [[LLV]], align 8
22660 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22661 // CHECK-NEXT:    [[TMP4076:%.*]] = load i64, ptr [[LLE]], align 8
22662 // CHECK-NEXT:    [[TMP4077:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4076]] release, align 8
22663 // CHECK-NEXT:    [[TMP4078:%.*]] = icmp slt i64 [[TMP4077]], [[TMP4076]]
22664 // CHECK-NEXT:    [[TMP4079:%.*]] = select i1 [[TMP4078]], i64 [[TMP4076]], i64 [[TMP4077]]
22665 // CHECK-NEXT:    store i64 [[TMP4079]], ptr [[LLV]], align 8
22666 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22667 // CHECK-NEXT:    [[TMP4080:%.*]] = load i64, ptr [[LLE]], align 8
22668 // CHECK-NEXT:    [[TMP4081:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4080]] release, align 8
22669 // CHECK-NEXT:    [[TMP4082:%.*]] = icmp slt i64 [[TMP4081]], [[TMP4080]]
22670 // CHECK-NEXT:    [[TMP4083:%.*]] = select i1 [[TMP4082]], i64 [[TMP4080]], i64 [[TMP4081]]
22671 // CHECK-NEXT:    store i64 [[TMP4083]], ptr [[LLV]], align 8
22672 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22673 // CHECK-NEXT:    [[TMP4084:%.*]] = load i64, ptr [[LLE]], align 8
22674 // CHECK-NEXT:    [[TMP4085:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4084]] release, align 8
22675 // CHECK-NEXT:    [[TMP4086:%.*]] = icmp sgt i64 [[TMP4085]], [[TMP4084]]
22676 // CHECK-NEXT:    [[TMP4087:%.*]] = select i1 [[TMP4086]], i64 [[TMP4084]], i64 [[TMP4085]]
22677 // CHECK-NEXT:    store i64 [[TMP4087]], ptr [[LLV]], align 8
22678 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22679 // CHECK-NEXT:    [[TMP4088:%.*]] = load i64, ptr [[LLE]], align 8
22680 // CHECK-NEXT:    [[TMP4089:%.*]] = load i64, ptr [[LLD]], align 8
22681 // CHECK-NEXT:    [[TMP4090:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4088]], i64 [[TMP4089]] release monotonic, align 8
22682 // CHECK-NEXT:    [[TMP4091:%.*]] = extractvalue { i64, i1 } [[TMP4090]], 0
22683 // CHECK-NEXT:    [[TMP4092:%.*]] = extractvalue { i64, i1 } [[TMP4090]], 1
22684 // CHECK-NEXT:    [[TMP4093:%.*]] = select i1 [[TMP4092]], i64 [[TMP4088]], i64 [[TMP4091]]
22685 // CHECK-NEXT:    store i64 [[TMP4093]], ptr [[LLV]], align 8
22686 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22687 // CHECK-NEXT:    [[TMP4094:%.*]] = load i64, ptr [[LLE]], align 8
22688 // CHECK-NEXT:    [[TMP4095:%.*]] = load i64, ptr [[LLD]], align 8
22689 // CHECK-NEXT:    [[TMP4096:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4094]], i64 [[TMP4095]] release monotonic, align 8
22690 // CHECK-NEXT:    [[TMP4097:%.*]] = extractvalue { i64, i1 } [[TMP4096]], 0
22691 // CHECK-NEXT:    [[TMP4098:%.*]] = extractvalue { i64, i1 } [[TMP4096]], 1
22692 // CHECK-NEXT:    [[TMP4099:%.*]] = select i1 [[TMP4098]], i64 [[TMP4094]], i64 [[TMP4097]]
22693 // CHECK-NEXT:    store i64 [[TMP4099]], ptr [[LLV]], align 8
22694 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22695 // CHECK-NEXT:    [[TMP4100:%.*]] = load i64, ptr [[LLE]], align 8
22696 // CHECK-NEXT:    [[TMP4101:%.*]] = load i64, ptr [[LLD]], align 8
22697 // CHECK-NEXT:    [[TMP4102:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4100]], i64 [[TMP4101]] release monotonic, align 8
22698 // CHECK-NEXT:    [[TMP4103:%.*]] = extractvalue { i64, i1 } [[TMP4102]], 0
22699 // CHECK-NEXT:    [[TMP4104:%.*]] = extractvalue { i64, i1 } [[TMP4102]], 1
22700 // CHECK-NEXT:    br i1 [[TMP4104]], label [[LLX_ATOMIC_EXIT399:%.*]], label [[LLX_ATOMIC_CONT400:%.*]]
22701 // CHECK:       llx.atomic.cont400:
22702 // CHECK-NEXT:    store i64 [[TMP4103]], ptr [[LLV]], align 8
22703 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT399]]
22704 // CHECK:       llx.atomic.exit399:
22705 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22706 // CHECK-NEXT:    [[TMP4105:%.*]] = load i64, ptr [[LLE]], align 8
22707 // CHECK-NEXT:    [[TMP4106:%.*]] = load i64, ptr [[LLD]], align 8
22708 // CHECK-NEXT:    [[TMP4107:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4105]], i64 [[TMP4106]] release monotonic, align 8
22709 // CHECK-NEXT:    [[TMP4108:%.*]] = extractvalue { i64, i1 } [[TMP4107]], 0
22710 // CHECK-NEXT:    [[TMP4109:%.*]] = extractvalue { i64, i1 } [[TMP4107]], 1
22711 // CHECK-NEXT:    br i1 [[TMP4109]], label [[LLX_ATOMIC_EXIT401:%.*]], label [[LLX_ATOMIC_CONT402:%.*]]
22712 // CHECK:       llx.atomic.cont402:
22713 // CHECK-NEXT:    store i64 [[TMP4108]], ptr [[LLV]], align 8
22714 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT401]]
22715 // CHECK:       llx.atomic.exit401:
22716 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22717 // CHECK-NEXT:    [[TMP4110:%.*]] = load i64, ptr [[LLE]], align 8
22718 // CHECK-NEXT:    [[TMP4111:%.*]] = load i64, ptr [[LLD]], align 8
22719 // CHECK-NEXT:    [[TMP4112:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4110]], i64 [[TMP4111]] release monotonic, align 8
22720 // CHECK-NEXT:    [[TMP4113:%.*]] = extractvalue { i64, i1 } [[TMP4112]], 1
22721 // CHECK-NEXT:    [[TMP4114:%.*]] = sext i1 [[TMP4113]] to i64
22722 // CHECK-NEXT:    store i64 [[TMP4114]], ptr [[LLR]], align 8
22723 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22724 // CHECK-NEXT:    [[TMP4115:%.*]] = load i64, ptr [[LLE]], align 8
22725 // CHECK-NEXT:    [[TMP4116:%.*]] = load i64, ptr [[LLD]], align 8
22726 // CHECK-NEXT:    [[TMP4117:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4115]], i64 [[TMP4116]] release monotonic, align 8
22727 // CHECK-NEXT:    [[TMP4118:%.*]] = extractvalue { i64, i1 } [[TMP4117]], 1
22728 // CHECK-NEXT:    [[TMP4119:%.*]] = sext i1 [[TMP4118]] to i64
22729 // CHECK-NEXT:    store i64 [[TMP4119]], ptr [[LLR]], align 8
22730 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22731 // CHECK-NEXT:    [[TMP4120:%.*]] = load i64, ptr [[LLE]], align 8
22732 // CHECK-NEXT:    [[TMP4121:%.*]] = load i64, ptr [[LLD]], align 8
22733 // CHECK-NEXT:    [[TMP4122:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4120]], i64 [[TMP4121]] release monotonic, align 8
22734 // CHECK-NEXT:    [[TMP4123:%.*]] = extractvalue { i64, i1 } [[TMP4122]], 0
22735 // CHECK-NEXT:    [[TMP4124:%.*]] = extractvalue { i64, i1 } [[TMP4122]], 1
22736 // CHECK-NEXT:    br i1 [[TMP4124]], label [[LLX_ATOMIC_EXIT403:%.*]], label [[LLX_ATOMIC_CONT404:%.*]]
22737 // CHECK:       llx.atomic.cont404:
22738 // CHECK-NEXT:    store i64 [[TMP4123]], ptr [[LLV]], align 8
22739 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT403]]
22740 // CHECK:       llx.atomic.exit403:
22741 // CHECK-NEXT:    [[TMP4125:%.*]] = extractvalue { i64, i1 } [[TMP4122]], 1
22742 // CHECK-NEXT:    [[TMP4126:%.*]] = sext i1 [[TMP4125]] to i64
22743 // CHECK-NEXT:    store i64 [[TMP4126]], ptr [[LLR]], align 8
22744 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22745 // CHECK-NEXT:    [[TMP4127:%.*]] = load i64, ptr [[LLE]], align 8
22746 // CHECK-NEXT:    [[TMP4128:%.*]] = load i64, ptr [[LLD]], align 8
22747 // CHECK-NEXT:    [[TMP4129:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4127]], i64 [[TMP4128]] release monotonic, align 8
22748 // CHECK-NEXT:    [[TMP4130:%.*]] = extractvalue { i64, i1 } [[TMP4129]], 0
22749 // CHECK-NEXT:    [[TMP4131:%.*]] = extractvalue { i64, i1 } [[TMP4129]], 1
22750 // CHECK-NEXT:    br i1 [[TMP4131]], label [[LLX_ATOMIC_EXIT405:%.*]], label [[LLX_ATOMIC_CONT406:%.*]]
22751 // CHECK:       llx.atomic.cont406:
22752 // CHECK-NEXT:    store i64 [[TMP4130]], ptr [[LLV]], align 8
22753 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT405]]
22754 // CHECK:       llx.atomic.exit405:
22755 // CHECK-NEXT:    [[TMP4132:%.*]] = extractvalue { i64, i1 } [[TMP4129]], 1
22756 // CHECK-NEXT:    [[TMP4133:%.*]] = sext i1 [[TMP4132]] to i64
22757 // CHECK-NEXT:    store i64 [[TMP4133]], ptr [[LLR]], align 8
22758 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22759 // CHECK-NEXT:    [[TMP4134:%.*]] = load i64, ptr [[LLE]], align 8
22760 // CHECK-NEXT:    [[TMP4135:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4134]] seq_cst, align 8
22761 // CHECK-NEXT:    store i64 [[TMP4135]], ptr [[LLV]], align 8
22762 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22763 // CHECK-NEXT:    [[TMP4136:%.*]] = load i64, ptr [[LLE]], align 8
22764 // CHECK-NEXT:    [[TMP4137:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4136]] seq_cst, align 8
22765 // CHECK-NEXT:    store i64 [[TMP4137]], ptr [[LLV]], align 8
22766 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22767 // CHECK-NEXT:    [[TMP4138:%.*]] = load i64, ptr [[LLE]], align 8
22768 // CHECK-NEXT:    [[TMP4139:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4138]] seq_cst, align 8
22769 // CHECK-NEXT:    store i64 [[TMP4139]], ptr [[LLV]], align 8
22770 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22771 // CHECK-NEXT:    [[TMP4140:%.*]] = load i64, ptr [[LLE]], align 8
22772 // CHECK-NEXT:    [[TMP4141:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4140]] seq_cst, align 8
22773 // CHECK-NEXT:    store i64 [[TMP4141]], ptr [[LLV]], align 8
22774 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22775 // CHECK-NEXT:    [[TMP4142:%.*]] = load i64, ptr [[LLE]], align 8
22776 // CHECK-NEXT:    [[TMP4143:%.*]] = load i64, ptr [[LLD]], align 8
22777 // CHECK-NEXT:    [[TMP4144:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4142]], i64 [[TMP4143]] seq_cst seq_cst, align 8
22778 // CHECK-NEXT:    [[TMP4145:%.*]] = extractvalue { i64, i1 } [[TMP4144]], 0
22779 // CHECK-NEXT:    store i64 [[TMP4145]], ptr [[LLV]], align 8
22780 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22781 // CHECK-NEXT:    [[TMP4146:%.*]] = load i64, ptr [[LLE]], align 8
22782 // CHECK-NEXT:    [[TMP4147:%.*]] = load i64, ptr [[LLD]], align 8
22783 // CHECK-NEXT:    [[TMP4148:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4146]], i64 [[TMP4147]] seq_cst seq_cst, align 8
22784 // CHECK-NEXT:    [[TMP4149:%.*]] = extractvalue { i64, i1 } [[TMP4148]], 0
22785 // CHECK-NEXT:    store i64 [[TMP4149]], ptr [[LLV]], align 8
22786 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22787 // CHECK-NEXT:    [[TMP4150:%.*]] = load i64, ptr [[LLE]], align 8
22788 // CHECK-NEXT:    [[TMP4151:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4150]] seq_cst, align 8
22789 // CHECK-NEXT:    [[TMP4152:%.*]] = icmp sgt i64 [[TMP4151]], [[TMP4150]]
22790 // CHECK-NEXT:    [[TMP4153:%.*]] = select i1 [[TMP4152]], i64 [[TMP4150]], i64 [[TMP4151]]
22791 // CHECK-NEXT:    store i64 [[TMP4153]], ptr [[LLV]], align 8
22792 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22793 // CHECK-NEXT:    [[TMP4154:%.*]] = load i64, ptr [[LLE]], align 8
22794 // CHECK-NEXT:    [[TMP4155:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4154]] seq_cst, align 8
22795 // CHECK-NEXT:    [[TMP4156:%.*]] = icmp slt i64 [[TMP4155]], [[TMP4154]]
22796 // CHECK-NEXT:    [[TMP4157:%.*]] = select i1 [[TMP4156]], i64 [[TMP4154]], i64 [[TMP4155]]
22797 // CHECK-NEXT:    store i64 [[TMP4157]], ptr [[LLV]], align 8
22798 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22799 // CHECK-NEXT:    [[TMP4158:%.*]] = load i64, ptr [[LLE]], align 8
22800 // CHECK-NEXT:    [[TMP4159:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4158]] seq_cst, align 8
22801 // CHECK-NEXT:    [[TMP4160:%.*]] = icmp slt i64 [[TMP4159]], [[TMP4158]]
22802 // CHECK-NEXT:    [[TMP4161:%.*]] = select i1 [[TMP4160]], i64 [[TMP4158]], i64 [[TMP4159]]
22803 // CHECK-NEXT:    store i64 [[TMP4161]], ptr [[LLV]], align 8
22804 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22805 // CHECK-NEXT:    [[TMP4162:%.*]] = load i64, ptr [[LLE]], align 8
22806 // CHECK-NEXT:    [[TMP4163:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4162]] seq_cst, align 8
22807 // CHECK-NEXT:    [[TMP4164:%.*]] = icmp sgt i64 [[TMP4163]], [[TMP4162]]
22808 // CHECK-NEXT:    [[TMP4165:%.*]] = select i1 [[TMP4164]], i64 [[TMP4162]], i64 [[TMP4163]]
22809 // CHECK-NEXT:    store i64 [[TMP4165]], ptr [[LLV]], align 8
22810 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22811 // CHECK-NEXT:    [[TMP4166:%.*]] = load i64, ptr [[LLE]], align 8
22812 // CHECK-NEXT:    [[TMP4167:%.*]] = load i64, ptr [[LLD]], align 8
22813 // CHECK-NEXT:    [[TMP4168:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4166]], i64 [[TMP4167]] seq_cst seq_cst, align 8
22814 // CHECK-NEXT:    [[TMP4169:%.*]] = extractvalue { i64, i1 } [[TMP4168]], 0
22815 // CHECK-NEXT:    [[TMP4170:%.*]] = extractvalue { i64, i1 } [[TMP4168]], 1
22816 // CHECK-NEXT:    [[TMP4171:%.*]] = select i1 [[TMP4170]], i64 [[TMP4166]], i64 [[TMP4169]]
22817 // CHECK-NEXT:    store i64 [[TMP4171]], ptr [[LLV]], align 8
22818 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22819 // CHECK-NEXT:    [[TMP4172:%.*]] = load i64, ptr [[LLE]], align 8
22820 // CHECK-NEXT:    [[TMP4173:%.*]] = load i64, ptr [[LLD]], align 8
22821 // CHECK-NEXT:    [[TMP4174:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4172]], i64 [[TMP4173]] seq_cst seq_cst, align 8
22822 // CHECK-NEXT:    [[TMP4175:%.*]] = extractvalue { i64, i1 } [[TMP4174]], 0
22823 // CHECK-NEXT:    [[TMP4176:%.*]] = extractvalue { i64, i1 } [[TMP4174]], 1
22824 // CHECK-NEXT:    [[TMP4177:%.*]] = select i1 [[TMP4176]], i64 [[TMP4172]], i64 [[TMP4175]]
22825 // CHECK-NEXT:    store i64 [[TMP4177]], ptr [[LLV]], align 8
22826 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22827 // CHECK-NEXT:    [[TMP4178:%.*]] = load i64, ptr [[LLE]], align 8
22828 // CHECK-NEXT:    [[TMP4179:%.*]] = load i64, ptr [[LLD]], align 8
22829 // CHECK-NEXT:    [[TMP4180:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4178]], i64 [[TMP4179]] seq_cst seq_cst, align 8
22830 // CHECK-NEXT:    [[TMP4181:%.*]] = extractvalue { i64, i1 } [[TMP4180]], 0
22831 // CHECK-NEXT:    [[TMP4182:%.*]] = extractvalue { i64, i1 } [[TMP4180]], 1
22832 // CHECK-NEXT:    br i1 [[TMP4182]], label [[LLX_ATOMIC_EXIT407:%.*]], label [[LLX_ATOMIC_CONT408:%.*]]
22833 // CHECK:       llx.atomic.cont408:
22834 // CHECK-NEXT:    store i64 [[TMP4181]], ptr [[LLV]], align 8
22835 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT407]]
22836 // CHECK:       llx.atomic.exit407:
22837 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22838 // CHECK-NEXT:    [[TMP4183:%.*]] = load i64, ptr [[LLE]], align 8
22839 // CHECK-NEXT:    [[TMP4184:%.*]] = load i64, ptr [[LLD]], align 8
22840 // CHECK-NEXT:    [[TMP4185:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4183]], i64 [[TMP4184]] seq_cst seq_cst, align 8
22841 // CHECK-NEXT:    [[TMP4186:%.*]] = extractvalue { i64, i1 } [[TMP4185]], 0
22842 // CHECK-NEXT:    [[TMP4187:%.*]] = extractvalue { i64, i1 } [[TMP4185]], 1
22843 // CHECK-NEXT:    br i1 [[TMP4187]], label [[LLX_ATOMIC_EXIT409:%.*]], label [[LLX_ATOMIC_CONT410:%.*]]
22844 // CHECK:       llx.atomic.cont410:
22845 // CHECK-NEXT:    store i64 [[TMP4186]], ptr [[LLV]], align 8
22846 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT409]]
22847 // CHECK:       llx.atomic.exit409:
22848 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22849 // CHECK-NEXT:    [[TMP4188:%.*]] = load i64, ptr [[LLE]], align 8
22850 // CHECK-NEXT:    [[TMP4189:%.*]] = load i64, ptr [[LLD]], align 8
22851 // CHECK-NEXT:    [[TMP4190:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4188]], i64 [[TMP4189]] seq_cst seq_cst, align 8
22852 // CHECK-NEXT:    [[TMP4191:%.*]] = extractvalue { i64, i1 } [[TMP4190]], 1
22853 // CHECK-NEXT:    [[TMP4192:%.*]] = sext i1 [[TMP4191]] to i64
22854 // CHECK-NEXT:    store i64 [[TMP4192]], ptr [[LLR]], align 8
22855 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22856 // CHECK-NEXT:    [[TMP4193:%.*]] = load i64, ptr [[LLE]], align 8
22857 // CHECK-NEXT:    [[TMP4194:%.*]] = load i64, ptr [[LLD]], align 8
22858 // CHECK-NEXT:    [[TMP4195:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4193]], i64 [[TMP4194]] seq_cst seq_cst, align 8
22859 // CHECK-NEXT:    [[TMP4196:%.*]] = extractvalue { i64, i1 } [[TMP4195]], 1
22860 // CHECK-NEXT:    [[TMP4197:%.*]] = sext i1 [[TMP4196]] to i64
22861 // CHECK-NEXT:    store i64 [[TMP4197]], ptr [[LLR]], align 8
22862 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22863 // CHECK-NEXT:    [[TMP4198:%.*]] = load i64, ptr [[LLE]], align 8
22864 // CHECK-NEXT:    [[TMP4199:%.*]] = load i64, ptr [[LLD]], align 8
22865 // CHECK-NEXT:    [[TMP4200:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4198]], i64 [[TMP4199]] seq_cst seq_cst, align 8
22866 // CHECK-NEXT:    [[TMP4201:%.*]] = extractvalue { i64, i1 } [[TMP4200]], 0
22867 // CHECK-NEXT:    [[TMP4202:%.*]] = extractvalue { i64, i1 } [[TMP4200]], 1
22868 // CHECK-NEXT:    br i1 [[TMP4202]], label [[LLX_ATOMIC_EXIT411:%.*]], label [[LLX_ATOMIC_CONT412:%.*]]
22869 // CHECK:       llx.atomic.cont412:
22870 // CHECK-NEXT:    store i64 [[TMP4201]], ptr [[LLV]], align 8
22871 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT411]]
22872 // CHECK:       llx.atomic.exit411:
22873 // CHECK-NEXT:    [[TMP4203:%.*]] = extractvalue { i64, i1 } [[TMP4200]], 1
22874 // CHECK-NEXT:    [[TMP4204:%.*]] = sext i1 [[TMP4203]] to i64
22875 // CHECK-NEXT:    store i64 [[TMP4204]], ptr [[LLR]], align 8
22876 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22877 // CHECK-NEXT:    [[TMP4205:%.*]] = load i64, ptr [[LLE]], align 8
22878 // CHECK-NEXT:    [[TMP4206:%.*]] = load i64, ptr [[LLD]], align 8
22879 // CHECK-NEXT:    [[TMP4207:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4205]], i64 [[TMP4206]] seq_cst seq_cst, align 8
22880 // CHECK-NEXT:    [[TMP4208:%.*]] = extractvalue { i64, i1 } [[TMP4207]], 0
22881 // CHECK-NEXT:    [[TMP4209:%.*]] = extractvalue { i64, i1 } [[TMP4207]], 1
22882 // CHECK-NEXT:    br i1 [[TMP4209]], label [[LLX_ATOMIC_EXIT413:%.*]], label [[LLX_ATOMIC_CONT414:%.*]]
22883 // CHECK:       llx.atomic.cont414:
22884 // CHECK-NEXT:    store i64 [[TMP4208]], ptr [[LLV]], align 8
22885 // CHECK-NEXT:    br label [[LLX_ATOMIC_EXIT413]]
22886 // CHECK:       llx.atomic.exit413:
22887 // CHECK-NEXT:    [[TMP4210:%.*]] = extractvalue { i64, i1 } [[TMP4207]], 1
22888 // CHECK-NEXT:    [[TMP4211:%.*]] = sext i1 [[TMP4210]] to i64
22889 // CHECK-NEXT:    store i64 [[TMP4211]], ptr [[LLR]], align 8
22890 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
22891 // CHECK-NEXT:    [[TMP4212:%.*]] = load i64, ptr [[ULLE]], align 8
22892 // CHECK-NEXT:    [[TMP4213:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4212]] monotonic, align 8
22893 // CHECK-NEXT:    store i64 [[TMP4213]], ptr [[ULLV]], align 8
22894 // CHECK-NEXT:    [[TMP4214:%.*]] = load i64, ptr [[ULLE]], align 8
22895 // CHECK-NEXT:    [[TMP4215:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4214]] monotonic, align 8
22896 // CHECK-NEXT:    store i64 [[TMP4215]], ptr [[ULLV]], align 8
22897 // CHECK-NEXT:    [[TMP4216:%.*]] = load i64, ptr [[ULLE]], align 8
22898 // CHECK-NEXT:    [[TMP4217:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4216]] monotonic, align 8
22899 // CHECK-NEXT:    store i64 [[TMP4217]], ptr [[ULLV]], align 8
22900 // CHECK-NEXT:    [[TMP4218:%.*]] = load i64, ptr [[ULLE]], align 8
22901 // CHECK-NEXT:    [[TMP4219:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4218]] monotonic, align 8
22902 // CHECK-NEXT:    store i64 [[TMP4219]], ptr [[ULLV]], align 8
22903 // CHECK-NEXT:    [[TMP4220:%.*]] = load i64, ptr [[ULLE]], align 8
22904 // CHECK-NEXT:    [[TMP4221:%.*]] = load i64, ptr [[ULLD]], align 8
22905 // CHECK-NEXT:    [[TMP4222:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4220]], i64 [[TMP4221]] monotonic monotonic, align 8
22906 // CHECK-NEXT:    [[TMP4223:%.*]] = extractvalue { i64, i1 } [[TMP4222]], 0
22907 // CHECK-NEXT:    store i64 [[TMP4223]], ptr [[ULLV]], align 8
22908 // CHECK-NEXT:    [[TMP4224:%.*]] = load i64, ptr [[ULLE]], align 8
22909 // CHECK-NEXT:    [[TMP4225:%.*]] = load i64, ptr [[ULLD]], align 8
22910 // CHECK-NEXT:    [[TMP4226:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4224]], i64 [[TMP4225]] monotonic monotonic, align 8
22911 // CHECK-NEXT:    [[TMP4227:%.*]] = extractvalue { i64, i1 } [[TMP4226]], 0
22912 // CHECK-NEXT:    store i64 [[TMP4227]], ptr [[ULLV]], align 8
22913 // CHECK-NEXT:    [[TMP4228:%.*]] = load i64, ptr [[ULLE]], align 8
22914 // CHECK-NEXT:    [[TMP4229:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4228]] monotonic, align 8
22915 // CHECK-NEXT:    [[TMP4230:%.*]] = icmp ugt i64 [[TMP4229]], [[TMP4228]]
22916 // CHECK-NEXT:    [[TMP4231:%.*]] = select i1 [[TMP4230]], i64 [[TMP4228]], i64 [[TMP4229]]
22917 // CHECK-NEXT:    store i64 [[TMP4231]], ptr [[ULLV]], align 8
22918 // CHECK-NEXT:    [[TMP4232:%.*]] = load i64, ptr [[ULLE]], align 8
22919 // CHECK-NEXT:    [[TMP4233:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4232]] monotonic, align 8
22920 // CHECK-NEXT:    [[TMP4234:%.*]] = icmp ult i64 [[TMP4233]], [[TMP4232]]
22921 // CHECK-NEXT:    [[TMP4235:%.*]] = select i1 [[TMP4234]], i64 [[TMP4232]], i64 [[TMP4233]]
22922 // CHECK-NEXT:    store i64 [[TMP4235]], ptr [[ULLV]], align 8
22923 // CHECK-NEXT:    [[TMP4236:%.*]] = load i64, ptr [[ULLE]], align 8
22924 // CHECK-NEXT:    [[TMP4237:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4236]] monotonic, align 8
22925 // CHECK-NEXT:    [[TMP4238:%.*]] = icmp ult i64 [[TMP4237]], [[TMP4236]]
22926 // CHECK-NEXT:    [[TMP4239:%.*]] = select i1 [[TMP4238]], i64 [[TMP4236]], i64 [[TMP4237]]
22927 // CHECK-NEXT:    store i64 [[TMP4239]], ptr [[ULLV]], align 8
22928 // CHECK-NEXT:    [[TMP4240:%.*]] = load i64, ptr [[ULLE]], align 8
22929 // CHECK-NEXT:    [[TMP4241:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4240]] monotonic, align 8
22930 // CHECK-NEXT:    [[TMP4242:%.*]] = icmp ugt i64 [[TMP4241]], [[TMP4240]]
22931 // CHECK-NEXT:    [[TMP4243:%.*]] = select i1 [[TMP4242]], i64 [[TMP4240]], i64 [[TMP4241]]
22932 // CHECK-NEXT:    store i64 [[TMP4243]], ptr [[ULLV]], align 8
22933 // CHECK-NEXT:    [[TMP4244:%.*]] = load i64, ptr [[ULLE]], align 8
22934 // CHECK-NEXT:    [[TMP4245:%.*]] = load i64, ptr [[ULLD]], align 8
22935 // CHECK-NEXT:    [[TMP4246:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4244]], i64 [[TMP4245]] monotonic monotonic, align 8
22936 // CHECK-NEXT:    [[TMP4247:%.*]] = extractvalue { i64, i1 } [[TMP4246]], 0
22937 // CHECK-NEXT:    [[TMP4248:%.*]] = extractvalue { i64, i1 } [[TMP4246]], 1
22938 // CHECK-NEXT:    [[TMP4249:%.*]] = select i1 [[TMP4248]], i64 [[TMP4244]], i64 [[TMP4247]]
22939 // CHECK-NEXT:    store i64 [[TMP4249]], ptr [[ULLV]], align 8
22940 // CHECK-NEXT:    [[TMP4250:%.*]] = load i64, ptr [[ULLE]], align 8
22941 // CHECK-NEXT:    [[TMP4251:%.*]] = load i64, ptr [[ULLD]], align 8
22942 // CHECK-NEXT:    [[TMP4252:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4250]], i64 [[TMP4251]] monotonic monotonic, align 8
22943 // CHECK-NEXT:    [[TMP4253:%.*]] = extractvalue { i64, i1 } [[TMP4252]], 0
22944 // CHECK-NEXT:    [[TMP4254:%.*]] = extractvalue { i64, i1 } [[TMP4252]], 1
22945 // CHECK-NEXT:    [[TMP4255:%.*]] = select i1 [[TMP4254]], i64 [[TMP4250]], i64 [[TMP4253]]
22946 // CHECK-NEXT:    store i64 [[TMP4255]], ptr [[ULLV]], align 8
22947 // CHECK-NEXT:    [[TMP4256:%.*]] = load i64, ptr [[ULLE]], align 8
22948 // CHECK-NEXT:    [[TMP4257:%.*]] = load i64, ptr [[ULLD]], align 8
22949 // CHECK-NEXT:    [[TMP4258:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4256]], i64 [[TMP4257]] monotonic monotonic, align 8
22950 // CHECK-NEXT:    [[TMP4259:%.*]] = extractvalue { i64, i1 } [[TMP4258]], 0
22951 // CHECK-NEXT:    [[TMP4260:%.*]] = extractvalue { i64, i1 } [[TMP4258]], 1
22952 // CHECK-NEXT:    br i1 [[TMP4260]], label [[ULLX_ATOMIC_EXIT:%.*]], label [[ULLX_ATOMIC_CONT:%.*]]
22953 // CHECK:       ullx.atomic.cont:
22954 // CHECK-NEXT:    store i64 [[TMP4259]], ptr [[ULLV]], align 8
22955 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT]]
22956 // CHECK:       ullx.atomic.exit:
22957 // CHECK-NEXT:    [[TMP4261:%.*]] = load i64, ptr [[ULLE]], align 8
22958 // CHECK-NEXT:    [[TMP4262:%.*]] = load i64, ptr [[ULLD]], align 8
22959 // CHECK-NEXT:    [[TMP4263:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4261]], i64 [[TMP4262]] monotonic monotonic, align 8
22960 // CHECK-NEXT:    [[TMP4264:%.*]] = extractvalue { i64, i1 } [[TMP4263]], 0
22961 // CHECK-NEXT:    [[TMP4265:%.*]] = extractvalue { i64, i1 } [[TMP4263]], 1
22962 // CHECK-NEXT:    br i1 [[TMP4265]], label [[ULLX_ATOMIC_EXIT415:%.*]], label [[ULLX_ATOMIC_CONT416:%.*]]
22963 // CHECK:       ullx.atomic.cont416:
22964 // CHECK-NEXT:    store i64 [[TMP4264]], ptr [[ULLV]], align 8
22965 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT415]]
22966 // CHECK:       ullx.atomic.exit415:
22967 // CHECK-NEXT:    [[TMP4266:%.*]] = load i64, ptr [[ULLE]], align 8
22968 // CHECK-NEXT:    [[TMP4267:%.*]] = load i64, ptr [[ULLD]], align 8
22969 // CHECK-NEXT:    [[TMP4268:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4266]], i64 [[TMP4267]] monotonic monotonic, align 8
22970 // CHECK-NEXT:    [[TMP4269:%.*]] = extractvalue { i64, i1 } [[TMP4268]], 1
22971 // CHECK-NEXT:    [[TMP4270:%.*]] = zext i1 [[TMP4269]] to i64
22972 // CHECK-NEXT:    store i64 [[TMP4270]], ptr [[ULLR]], align 8
22973 // CHECK-NEXT:    [[TMP4271:%.*]] = load i64, ptr [[ULLE]], align 8
22974 // CHECK-NEXT:    [[TMP4272:%.*]] = load i64, ptr [[ULLD]], align 8
22975 // CHECK-NEXT:    [[TMP4273:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4271]], i64 [[TMP4272]] monotonic monotonic, align 8
22976 // CHECK-NEXT:    [[TMP4274:%.*]] = extractvalue { i64, i1 } [[TMP4273]], 1
22977 // CHECK-NEXT:    [[TMP4275:%.*]] = zext i1 [[TMP4274]] to i64
22978 // CHECK-NEXT:    store i64 [[TMP4275]], ptr [[ULLR]], align 8
22979 // CHECK-NEXT:    [[TMP4276:%.*]] = load i64, ptr [[ULLE]], align 8
22980 // CHECK-NEXT:    [[TMP4277:%.*]] = load i64, ptr [[ULLD]], align 8
22981 // CHECK-NEXT:    [[TMP4278:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4276]], i64 [[TMP4277]] monotonic monotonic, align 8
22982 // CHECK-NEXT:    [[TMP4279:%.*]] = extractvalue { i64, i1 } [[TMP4278]], 0
22983 // CHECK-NEXT:    [[TMP4280:%.*]] = extractvalue { i64, i1 } [[TMP4278]], 1
22984 // CHECK-NEXT:    br i1 [[TMP4280]], label [[ULLX_ATOMIC_EXIT417:%.*]], label [[ULLX_ATOMIC_CONT418:%.*]]
22985 // CHECK:       ullx.atomic.cont418:
22986 // CHECK-NEXT:    store i64 [[TMP4279]], ptr [[ULLV]], align 8
22987 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT417]]
22988 // CHECK:       ullx.atomic.exit417:
22989 // CHECK-NEXT:    [[TMP4281:%.*]] = extractvalue { i64, i1 } [[TMP4278]], 1
22990 // CHECK-NEXT:    [[TMP4282:%.*]] = zext i1 [[TMP4281]] to i64
22991 // CHECK-NEXT:    store i64 [[TMP4282]], ptr [[ULLR]], align 8
22992 // CHECK-NEXT:    [[TMP4283:%.*]] = load i64, ptr [[ULLE]], align 8
22993 // CHECK-NEXT:    [[TMP4284:%.*]] = load i64, ptr [[ULLD]], align 8
22994 // CHECK-NEXT:    [[TMP4285:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4283]], i64 [[TMP4284]] monotonic monotonic, align 8
22995 // CHECK-NEXT:    [[TMP4286:%.*]] = extractvalue { i64, i1 } [[TMP4285]], 0
22996 // CHECK-NEXT:    [[TMP4287:%.*]] = extractvalue { i64, i1 } [[TMP4285]], 1
22997 // CHECK-NEXT:    br i1 [[TMP4287]], label [[ULLX_ATOMIC_EXIT419:%.*]], label [[ULLX_ATOMIC_CONT420:%.*]]
22998 // CHECK:       ullx.atomic.cont420:
22999 // CHECK-NEXT:    store i64 [[TMP4286]], ptr [[ULLV]], align 8
23000 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT419]]
23001 // CHECK:       ullx.atomic.exit419:
23002 // CHECK-NEXT:    [[TMP4288:%.*]] = extractvalue { i64, i1 } [[TMP4285]], 1
23003 // CHECK-NEXT:    [[TMP4289:%.*]] = zext i1 [[TMP4288]] to i64
23004 // CHECK-NEXT:    store i64 [[TMP4289]], ptr [[ULLR]], align 8
23005 // CHECK-NEXT:    [[TMP4290:%.*]] = load i64, ptr [[ULLE]], align 8
23006 // CHECK-NEXT:    [[TMP4291:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4290]] acq_rel, align 8
23007 // CHECK-NEXT:    store i64 [[TMP4291]], ptr [[ULLV]], align 8
23008 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23009 // CHECK-NEXT:    [[TMP4292:%.*]] = load i64, ptr [[ULLE]], align 8
23010 // CHECK-NEXT:    [[TMP4293:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4292]] acq_rel, align 8
23011 // CHECK-NEXT:    store i64 [[TMP4293]], ptr [[ULLV]], align 8
23012 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23013 // CHECK-NEXT:    [[TMP4294:%.*]] = load i64, ptr [[ULLE]], align 8
23014 // CHECK-NEXT:    [[TMP4295:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4294]] acq_rel, align 8
23015 // CHECK-NEXT:    store i64 [[TMP4295]], ptr [[ULLV]], align 8
23016 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23017 // CHECK-NEXT:    [[TMP4296:%.*]] = load i64, ptr [[ULLE]], align 8
23018 // CHECK-NEXT:    [[TMP4297:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4296]] acq_rel, align 8
23019 // CHECK-NEXT:    store i64 [[TMP4297]], ptr [[ULLV]], align 8
23020 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23021 // CHECK-NEXT:    [[TMP4298:%.*]] = load i64, ptr [[ULLE]], align 8
23022 // CHECK-NEXT:    [[TMP4299:%.*]] = load i64, ptr [[ULLD]], align 8
23023 // CHECK-NEXT:    [[TMP4300:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4298]], i64 [[TMP4299]] acq_rel acquire, align 8
23024 // CHECK-NEXT:    [[TMP4301:%.*]] = extractvalue { i64, i1 } [[TMP4300]], 0
23025 // CHECK-NEXT:    store i64 [[TMP4301]], ptr [[ULLV]], align 8
23026 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23027 // CHECK-NEXT:    [[TMP4302:%.*]] = load i64, ptr [[ULLE]], align 8
23028 // CHECK-NEXT:    [[TMP4303:%.*]] = load i64, ptr [[ULLD]], align 8
23029 // CHECK-NEXT:    [[TMP4304:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4302]], i64 [[TMP4303]] acq_rel acquire, align 8
23030 // CHECK-NEXT:    [[TMP4305:%.*]] = extractvalue { i64, i1 } [[TMP4304]], 0
23031 // CHECK-NEXT:    store i64 [[TMP4305]], ptr [[ULLV]], align 8
23032 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23033 // CHECK-NEXT:    [[TMP4306:%.*]] = load i64, ptr [[ULLE]], align 8
23034 // CHECK-NEXT:    [[TMP4307:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4306]] acq_rel, align 8
23035 // CHECK-NEXT:    [[TMP4308:%.*]] = icmp ugt i64 [[TMP4307]], [[TMP4306]]
23036 // CHECK-NEXT:    [[TMP4309:%.*]] = select i1 [[TMP4308]], i64 [[TMP4306]], i64 [[TMP4307]]
23037 // CHECK-NEXT:    store i64 [[TMP4309]], ptr [[ULLV]], align 8
23038 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23039 // CHECK-NEXT:    [[TMP4310:%.*]] = load i64, ptr [[ULLE]], align 8
23040 // CHECK-NEXT:    [[TMP4311:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4310]] acq_rel, align 8
23041 // CHECK-NEXT:    [[TMP4312:%.*]] = icmp ult i64 [[TMP4311]], [[TMP4310]]
23042 // CHECK-NEXT:    [[TMP4313:%.*]] = select i1 [[TMP4312]], i64 [[TMP4310]], i64 [[TMP4311]]
23043 // CHECK-NEXT:    store i64 [[TMP4313]], ptr [[ULLV]], align 8
23044 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23045 // CHECK-NEXT:    [[TMP4314:%.*]] = load i64, ptr [[ULLE]], align 8
23046 // CHECK-NEXT:    [[TMP4315:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4314]] acq_rel, align 8
23047 // CHECK-NEXT:    [[TMP4316:%.*]] = icmp ult i64 [[TMP4315]], [[TMP4314]]
23048 // CHECK-NEXT:    [[TMP4317:%.*]] = select i1 [[TMP4316]], i64 [[TMP4314]], i64 [[TMP4315]]
23049 // CHECK-NEXT:    store i64 [[TMP4317]], ptr [[ULLV]], align 8
23050 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23051 // CHECK-NEXT:    [[TMP4318:%.*]] = load i64, ptr [[ULLE]], align 8
23052 // CHECK-NEXT:    [[TMP4319:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4318]] acq_rel, align 8
23053 // CHECK-NEXT:    [[TMP4320:%.*]] = icmp ugt i64 [[TMP4319]], [[TMP4318]]
23054 // CHECK-NEXT:    [[TMP4321:%.*]] = select i1 [[TMP4320]], i64 [[TMP4318]], i64 [[TMP4319]]
23055 // CHECK-NEXT:    store i64 [[TMP4321]], ptr [[ULLV]], align 8
23056 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23057 // CHECK-NEXT:    [[TMP4322:%.*]] = load i64, ptr [[ULLE]], align 8
23058 // CHECK-NEXT:    [[TMP4323:%.*]] = load i64, ptr [[ULLD]], align 8
23059 // CHECK-NEXT:    [[TMP4324:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4322]], i64 [[TMP4323]] acq_rel acquire, align 8
23060 // CHECK-NEXT:    [[TMP4325:%.*]] = extractvalue { i64, i1 } [[TMP4324]], 0
23061 // CHECK-NEXT:    [[TMP4326:%.*]] = extractvalue { i64, i1 } [[TMP4324]], 1
23062 // CHECK-NEXT:    [[TMP4327:%.*]] = select i1 [[TMP4326]], i64 [[TMP4322]], i64 [[TMP4325]]
23063 // CHECK-NEXT:    store i64 [[TMP4327]], ptr [[ULLV]], align 8
23064 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23065 // CHECK-NEXT:    [[TMP4328:%.*]] = load i64, ptr [[ULLE]], align 8
23066 // CHECK-NEXT:    [[TMP4329:%.*]] = load i64, ptr [[ULLD]], align 8
23067 // CHECK-NEXT:    [[TMP4330:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4328]], i64 [[TMP4329]] acq_rel acquire, align 8
23068 // CHECK-NEXT:    [[TMP4331:%.*]] = extractvalue { i64, i1 } [[TMP4330]], 0
23069 // CHECK-NEXT:    [[TMP4332:%.*]] = extractvalue { i64, i1 } [[TMP4330]], 1
23070 // CHECK-NEXT:    [[TMP4333:%.*]] = select i1 [[TMP4332]], i64 [[TMP4328]], i64 [[TMP4331]]
23071 // CHECK-NEXT:    store i64 [[TMP4333]], ptr [[ULLV]], align 8
23072 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23073 // CHECK-NEXT:    [[TMP4334:%.*]] = load i64, ptr [[ULLE]], align 8
23074 // CHECK-NEXT:    [[TMP4335:%.*]] = load i64, ptr [[ULLD]], align 8
23075 // CHECK-NEXT:    [[TMP4336:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4334]], i64 [[TMP4335]] acq_rel acquire, align 8
23076 // CHECK-NEXT:    [[TMP4337:%.*]] = extractvalue { i64, i1 } [[TMP4336]], 0
23077 // CHECK-NEXT:    [[TMP4338:%.*]] = extractvalue { i64, i1 } [[TMP4336]], 1
23078 // CHECK-NEXT:    br i1 [[TMP4338]], label [[ULLX_ATOMIC_EXIT421:%.*]], label [[ULLX_ATOMIC_CONT422:%.*]]
23079 // CHECK:       ullx.atomic.cont422:
23080 // CHECK-NEXT:    store i64 [[TMP4337]], ptr [[ULLV]], align 8
23081 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT421]]
23082 // CHECK:       ullx.atomic.exit421:
23083 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23084 // CHECK-NEXT:    [[TMP4339:%.*]] = load i64, ptr [[ULLE]], align 8
23085 // CHECK-NEXT:    [[TMP4340:%.*]] = load i64, ptr [[ULLD]], align 8
23086 // CHECK-NEXT:    [[TMP4341:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4339]], i64 [[TMP4340]] acq_rel acquire, align 8
23087 // CHECK-NEXT:    [[TMP4342:%.*]] = extractvalue { i64, i1 } [[TMP4341]], 0
23088 // CHECK-NEXT:    [[TMP4343:%.*]] = extractvalue { i64, i1 } [[TMP4341]], 1
23089 // CHECK-NEXT:    br i1 [[TMP4343]], label [[ULLX_ATOMIC_EXIT423:%.*]], label [[ULLX_ATOMIC_CONT424:%.*]]
23090 // CHECK:       ullx.atomic.cont424:
23091 // CHECK-NEXT:    store i64 [[TMP4342]], ptr [[ULLV]], align 8
23092 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT423]]
23093 // CHECK:       ullx.atomic.exit423:
23094 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23095 // CHECK-NEXT:    [[TMP4344:%.*]] = load i64, ptr [[ULLE]], align 8
23096 // CHECK-NEXT:    [[TMP4345:%.*]] = load i64, ptr [[ULLD]], align 8
23097 // CHECK-NEXT:    [[TMP4346:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4344]], i64 [[TMP4345]] acq_rel acquire, align 8
23098 // CHECK-NEXT:    [[TMP4347:%.*]] = extractvalue { i64, i1 } [[TMP4346]], 1
23099 // CHECK-NEXT:    [[TMP4348:%.*]] = zext i1 [[TMP4347]] to i64
23100 // CHECK-NEXT:    store i64 [[TMP4348]], ptr [[ULLR]], align 8
23101 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23102 // CHECK-NEXT:    [[TMP4349:%.*]] = load i64, ptr [[ULLE]], align 8
23103 // CHECK-NEXT:    [[TMP4350:%.*]] = load i64, ptr [[ULLD]], align 8
23104 // CHECK-NEXT:    [[TMP4351:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4349]], i64 [[TMP4350]] acq_rel acquire, align 8
23105 // CHECK-NEXT:    [[TMP4352:%.*]] = extractvalue { i64, i1 } [[TMP4351]], 1
23106 // CHECK-NEXT:    [[TMP4353:%.*]] = zext i1 [[TMP4352]] to i64
23107 // CHECK-NEXT:    store i64 [[TMP4353]], ptr [[ULLR]], align 8
23108 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23109 // CHECK-NEXT:    [[TMP4354:%.*]] = load i64, ptr [[ULLE]], align 8
23110 // CHECK-NEXT:    [[TMP4355:%.*]] = load i64, ptr [[ULLD]], align 8
23111 // CHECK-NEXT:    [[TMP4356:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4354]], i64 [[TMP4355]] acq_rel acquire, align 8
23112 // CHECK-NEXT:    [[TMP4357:%.*]] = extractvalue { i64, i1 } [[TMP4356]], 0
23113 // CHECK-NEXT:    [[TMP4358:%.*]] = extractvalue { i64, i1 } [[TMP4356]], 1
23114 // CHECK-NEXT:    br i1 [[TMP4358]], label [[ULLX_ATOMIC_EXIT425:%.*]], label [[ULLX_ATOMIC_CONT426:%.*]]
23115 // CHECK:       ullx.atomic.cont426:
23116 // CHECK-NEXT:    store i64 [[TMP4357]], ptr [[ULLV]], align 8
23117 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT425]]
23118 // CHECK:       ullx.atomic.exit425:
23119 // CHECK-NEXT:    [[TMP4359:%.*]] = extractvalue { i64, i1 } [[TMP4356]], 1
23120 // CHECK-NEXT:    [[TMP4360:%.*]] = zext i1 [[TMP4359]] to i64
23121 // CHECK-NEXT:    store i64 [[TMP4360]], ptr [[ULLR]], align 8
23122 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23123 // CHECK-NEXT:    [[TMP4361:%.*]] = load i64, ptr [[ULLE]], align 8
23124 // CHECK-NEXT:    [[TMP4362:%.*]] = load i64, ptr [[ULLD]], align 8
23125 // CHECK-NEXT:    [[TMP4363:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4361]], i64 [[TMP4362]] acq_rel acquire, align 8
23126 // CHECK-NEXT:    [[TMP4364:%.*]] = extractvalue { i64, i1 } [[TMP4363]], 0
23127 // CHECK-NEXT:    [[TMP4365:%.*]] = extractvalue { i64, i1 } [[TMP4363]], 1
23128 // CHECK-NEXT:    br i1 [[TMP4365]], label [[ULLX_ATOMIC_EXIT427:%.*]], label [[ULLX_ATOMIC_CONT428:%.*]]
23129 // CHECK:       ullx.atomic.cont428:
23130 // CHECK-NEXT:    store i64 [[TMP4364]], ptr [[ULLV]], align 8
23131 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT427]]
23132 // CHECK:       ullx.atomic.exit427:
23133 // CHECK-NEXT:    [[TMP4366:%.*]] = extractvalue { i64, i1 } [[TMP4363]], 1
23134 // CHECK-NEXT:    [[TMP4367:%.*]] = zext i1 [[TMP4366]] to i64
23135 // CHECK-NEXT:    store i64 [[TMP4367]], ptr [[ULLR]], align 8
23136 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23137 // CHECK-NEXT:    [[TMP4368:%.*]] = load i64, ptr [[ULLE]], align 8
23138 // CHECK-NEXT:    [[TMP4369:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4368]] acquire, align 8
23139 // CHECK-NEXT:    store i64 [[TMP4369]], ptr [[ULLV]], align 8
23140 // CHECK-NEXT:    [[TMP4370:%.*]] = load i64, ptr [[ULLE]], align 8
23141 // CHECK-NEXT:    [[TMP4371:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4370]] acquire, align 8
23142 // CHECK-NEXT:    store i64 [[TMP4371]], ptr [[ULLV]], align 8
23143 // CHECK-NEXT:    [[TMP4372:%.*]] = load i64, ptr [[ULLE]], align 8
23144 // CHECK-NEXT:    [[TMP4373:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4372]] acquire, align 8
23145 // CHECK-NEXT:    store i64 [[TMP4373]], ptr [[ULLV]], align 8
23146 // CHECK-NEXT:    [[TMP4374:%.*]] = load i64, ptr [[ULLE]], align 8
23147 // CHECK-NEXT:    [[TMP4375:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4374]] acquire, align 8
23148 // CHECK-NEXT:    store i64 [[TMP4375]], ptr [[ULLV]], align 8
23149 // CHECK-NEXT:    [[TMP4376:%.*]] = load i64, ptr [[ULLE]], align 8
23150 // CHECK-NEXT:    [[TMP4377:%.*]] = load i64, ptr [[ULLD]], align 8
23151 // CHECK-NEXT:    [[TMP4378:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4376]], i64 [[TMP4377]] acquire acquire, align 8
23152 // CHECK-NEXT:    [[TMP4379:%.*]] = extractvalue { i64, i1 } [[TMP4378]], 0
23153 // CHECK-NEXT:    store i64 [[TMP4379]], ptr [[ULLV]], align 8
23154 // CHECK-NEXT:    [[TMP4380:%.*]] = load i64, ptr [[ULLE]], align 8
23155 // CHECK-NEXT:    [[TMP4381:%.*]] = load i64, ptr [[ULLD]], align 8
23156 // CHECK-NEXT:    [[TMP4382:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4380]], i64 [[TMP4381]] acquire acquire, align 8
23157 // CHECK-NEXT:    [[TMP4383:%.*]] = extractvalue { i64, i1 } [[TMP4382]], 0
23158 // CHECK-NEXT:    store i64 [[TMP4383]], ptr [[ULLV]], align 8
23159 // CHECK-NEXT:    [[TMP4384:%.*]] = load i64, ptr [[ULLE]], align 8
23160 // CHECK-NEXT:    [[TMP4385:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4384]] acquire, align 8
23161 // CHECK-NEXT:    [[TMP4386:%.*]] = icmp ugt i64 [[TMP4385]], [[TMP4384]]
23162 // CHECK-NEXT:    [[TMP4387:%.*]] = select i1 [[TMP4386]], i64 [[TMP4384]], i64 [[TMP4385]]
23163 // CHECK-NEXT:    store i64 [[TMP4387]], ptr [[ULLV]], align 8
23164 // CHECK-NEXT:    [[TMP4388:%.*]] = load i64, ptr [[ULLE]], align 8
23165 // CHECK-NEXT:    [[TMP4389:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4388]] acquire, align 8
23166 // CHECK-NEXT:    [[TMP4390:%.*]] = icmp ult i64 [[TMP4389]], [[TMP4388]]
23167 // CHECK-NEXT:    [[TMP4391:%.*]] = select i1 [[TMP4390]], i64 [[TMP4388]], i64 [[TMP4389]]
23168 // CHECK-NEXT:    store i64 [[TMP4391]], ptr [[ULLV]], align 8
23169 // CHECK-NEXT:    [[TMP4392:%.*]] = load i64, ptr [[ULLE]], align 8
23170 // CHECK-NEXT:    [[TMP4393:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4392]] acquire, align 8
23171 // CHECK-NEXT:    [[TMP4394:%.*]] = icmp ult i64 [[TMP4393]], [[TMP4392]]
23172 // CHECK-NEXT:    [[TMP4395:%.*]] = select i1 [[TMP4394]], i64 [[TMP4392]], i64 [[TMP4393]]
23173 // CHECK-NEXT:    store i64 [[TMP4395]], ptr [[ULLV]], align 8
23174 // CHECK-NEXT:    [[TMP4396:%.*]] = load i64, ptr [[ULLE]], align 8
23175 // CHECK-NEXT:    [[TMP4397:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4396]] acquire, align 8
23176 // CHECK-NEXT:    [[TMP4398:%.*]] = icmp ugt i64 [[TMP4397]], [[TMP4396]]
23177 // CHECK-NEXT:    [[TMP4399:%.*]] = select i1 [[TMP4398]], i64 [[TMP4396]], i64 [[TMP4397]]
23178 // CHECK-NEXT:    store i64 [[TMP4399]], ptr [[ULLV]], align 8
23179 // CHECK-NEXT:    [[TMP4400:%.*]] = load i64, ptr [[ULLE]], align 8
23180 // CHECK-NEXT:    [[TMP4401:%.*]] = load i64, ptr [[ULLD]], align 8
23181 // CHECK-NEXT:    [[TMP4402:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4400]], i64 [[TMP4401]] acquire acquire, align 8
23182 // CHECK-NEXT:    [[TMP4403:%.*]] = extractvalue { i64, i1 } [[TMP4402]], 0
23183 // CHECK-NEXT:    [[TMP4404:%.*]] = extractvalue { i64, i1 } [[TMP4402]], 1
23184 // CHECK-NEXT:    [[TMP4405:%.*]] = select i1 [[TMP4404]], i64 [[TMP4400]], i64 [[TMP4403]]
23185 // CHECK-NEXT:    store i64 [[TMP4405]], ptr [[ULLV]], align 8
23186 // CHECK-NEXT:    [[TMP4406:%.*]] = load i64, ptr [[ULLE]], align 8
23187 // CHECK-NEXT:    [[TMP4407:%.*]] = load i64, ptr [[ULLD]], align 8
23188 // CHECK-NEXT:    [[TMP4408:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4406]], i64 [[TMP4407]] acquire acquire, align 8
23189 // CHECK-NEXT:    [[TMP4409:%.*]] = extractvalue { i64, i1 } [[TMP4408]], 0
23190 // CHECK-NEXT:    [[TMP4410:%.*]] = extractvalue { i64, i1 } [[TMP4408]], 1
23191 // CHECK-NEXT:    [[TMP4411:%.*]] = select i1 [[TMP4410]], i64 [[TMP4406]], i64 [[TMP4409]]
23192 // CHECK-NEXT:    store i64 [[TMP4411]], ptr [[ULLV]], align 8
23193 // CHECK-NEXT:    [[TMP4412:%.*]] = load i64, ptr [[ULLE]], align 8
23194 // CHECK-NEXT:    [[TMP4413:%.*]] = load i64, ptr [[ULLD]], align 8
23195 // CHECK-NEXT:    [[TMP4414:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4412]], i64 [[TMP4413]] acquire acquire, align 8
23196 // CHECK-NEXT:    [[TMP4415:%.*]] = extractvalue { i64, i1 } [[TMP4414]], 0
23197 // CHECK-NEXT:    [[TMP4416:%.*]] = extractvalue { i64, i1 } [[TMP4414]], 1
23198 // CHECK-NEXT:    br i1 [[TMP4416]], label [[ULLX_ATOMIC_EXIT429:%.*]], label [[ULLX_ATOMIC_CONT430:%.*]]
23199 // CHECK:       ullx.atomic.cont430:
23200 // CHECK-NEXT:    store i64 [[TMP4415]], ptr [[ULLV]], align 8
23201 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT429]]
23202 // CHECK:       ullx.atomic.exit429:
23203 // CHECK-NEXT:    [[TMP4417:%.*]] = load i64, ptr [[ULLE]], align 8
23204 // CHECK-NEXT:    [[TMP4418:%.*]] = load i64, ptr [[ULLD]], align 8
23205 // CHECK-NEXT:    [[TMP4419:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4417]], i64 [[TMP4418]] acquire acquire, align 8
23206 // CHECK-NEXT:    [[TMP4420:%.*]] = extractvalue { i64, i1 } [[TMP4419]], 0
23207 // CHECK-NEXT:    [[TMP4421:%.*]] = extractvalue { i64, i1 } [[TMP4419]], 1
23208 // CHECK-NEXT:    br i1 [[TMP4421]], label [[ULLX_ATOMIC_EXIT431:%.*]], label [[ULLX_ATOMIC_CONT432:%.*]]
23209 // CHECK:       ullx.atomic.cont432:
23210 // CHECK-NEXT:    store i64 [[TMP4420]], ptr [[ULLV]], align 8
23211 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT431]]
23212 // CHECK:       ullx.atomic.exit431:
23213 // CHECK-NEXT:    [[TMP4422:%.*]] = load i64, ptr [[ULLE]], align 8
23214 // CHECK-NEXT:    [[TMP4423:%.*]] = load i64, ptr [[ULLD]], align 8
23215 // CHECK-NEXT:    [[TMP4424:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4422]], i64 [[TMP4423]] acquire acquire, align 8
23216 // CHECK-NEXT:    [[TMP4425:%.*]] = extractvalue { i64, i1 } [[TMP4424]], 1
23217 // CHECK-NEXT:    [[TMP4426:%.*]] = zext i1 [[TMP4425]] to i64
23218 // CHECK-NEXT:    store i64 [[TMP4426]], ptr [[ULLR]], align 8
23219 // CHECK-NEXT:    [[TMP4427:%.*]] = load i64, ptr [[ULLE]], align 8
23220 // CHECK-NEXT:    [[TMP4428:%.*]] = load i64, ptr [[ULLD]], align 8
23221 // CHECK-NEXT:    [[TMP4429:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4427]], i64 [[TMP4428]] acquire acquire, align 8
23222 // CHECK-NEXT:    [[TMP4430:%.*]] = extractvalue { i64, i1 } [[TMP4429]], 1
23223 // CHECK-NEXT:    [[TMP4431:%.*]] = zext i1 [[TMP4430]] to i64
23224 // CHECK-NEXT:    store i64 [[TMP4431]], ptr [[ULLR]], align 8
23225 // CHECK-NEXT:    [[TMP4432:%.*]] = load i64, ptr [[ULLE]], align 8
23226 // CHECK-NEXT:    [[TMP4433:%.*]] = load i64, ptr [[ULLD]], align 8
23227 // CHECK-NEXT:    [[TMP4434:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4432]], i64 [[TMP4433]] acquire acquire, align 8
23228 // CHECK-NEXT:    [[TMP4435:%.*]] = extractvalue { i64, i1 } [[TMP4434]], 0
23229 // CHECK-NEXT:    [[TMP4436:%.*]] = extractvalue { i64, i1 } [[TMP4434]], 1
23230 // CHECK-NEXT:    br i1 [[TMP4436]], label [[ULLX_ATOMIC_EXIT433:%.*]], label [[ULLX_ATOMIC_CONT434:%.*]]
23231 // CHECK:       ullx.atomic.cont434:
23232 // CHECK-NEXT:    store i64 [[TMP4435]], ptr [[ULLV]], align 8
23233 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT433]]
23234 // CHECK:       ullx.atomic.exit433:
23235 // CHECK-NEXT:    [[TMP4437:%.*]] = extractvalue { i64, i1 } [[TMP4434]], 1
23236 // CHECK-NEXT:    [[TMP4438:%.*]] = zext i1 [[TMP4437]] to i64
23237 // CHECK-NEXT:    store i64 [[TMP4438]], ptr [[ULLR]], align 8
23238 // CHECK-NEXT:    [[TMP4439:%.*]] = load i64, ptr [[ULLE]], align 8
23239 // CHECK-NEXT:    [[TMP4440:%.*]] = load i64, ptr [[ULLD]], align 8
23240 // CHECK-NEXT:    [[TMP4441:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4439]], i64 [[TMP4440]] acquire acquire, align 8
23241 // CHECK-NEXT:    [[TMP4442:%.*]] = extractvalue { i64, i1 } [[TMP4441]], 0
23242 // CHECK-NEXT:    [[TMP4443:%.*]] = extractvalue { i64, i1 } [[TMP4441]], 1
23243 // CHECK-NEXT:    br i1 [[TMP4443]], label [[ULLX_ATOMIC_EXIT435:%.*]], label [[ULLX_ATOMIC_CONT436:%.*]]
23244 // CHECK:       ullx.atomic.cont436:
23245 // CHECK-NEXT:    store i64 [[TMP4442]], ptr [[ULLV]], align 8
23246 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT435]]
23247 // CHECK:       ullx.atomic.exit435:
23248 // CHECK-NEXT:    [[TMP4444:%.*]] = extractvalue { i64, i1 } [[TMP4441]], 1
23249 // CHECK-NEXT:    [[TMP4445:%.*]] = zext i1 [[TMP4444]] to i64
23250 // CHECK-NEXT:    store i64 [[TMP4445]], ptr [[ULLR]], align 8
23251 // CHECK-NEXT:    [[TMP4446:%.*]] = load i64, ptr [[ULLE]], align 8
23252 // CHECK-NEXT:    [[TMP4447:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4446]] monotonic, align 8
23253 // CHECK-NEXT:    store i64 [[TMP4447]], ptr [[ULLV]], align 8
23254 // CHECK-NEXT:    [[TMP4448:%.*]] = load i64, ptr [[ULLE]], align 8
23255 // CHECK-NEXT:    [[TMP4449:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4448]] monotonic, align 8
23256 // CHECK-NEXT:    store i64 [[TMP4449]], ptr [[ULLV]], align 8
23257 // CHECK-NEXT:    [[TMP4450:%.*]] = load i64, ptr [[ULLE]], align 8
23258 // CHECK-NEXT:    [[TMP4451:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4450]] monotonic, align 8
23259 // CHECK-NEXT:    store i64 [[TMP4451]], ptr [[ULLV]], align 8
23260 // CHECK-NEXT:    [[TMP4452:%.*]] = load i64, ptr [[ULLE]], align 8
23261 // CHECK-NEXT:    [[TMP4453:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4452]] monotonic, align 8
23262 // CHECK-NEXT:    store i64 [[TMP4453]], ptr [[ULLV]], align 8
23263 // CHECK-NEXT:    [[TMP4454:%.*]] = load i64, ptr [[ULLE]], align 8
23264 // CHECK-NEXT:    [[TMP4455:%.*]] = load i64, ptr [[ULLD]], align 8
23265 // CHECK-NEXT:    [[TMP4456:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4454]], i64 [[TMP4455]] monotonic monotonic, align 8
23266 // CHECK-NEXT:    [[TMP4457:%.*]] = extractvalue { i64, i1 } [[TMP4456]], 0
23267 // CHECK-NEXT:    store i64 [[TMP4457]], ptr [[ULLV]], align 8
23268 // CHECK-NEXT:    [[TMP4458:%.*]] = load i64, ptr [[ULLE]], align 8
23269 // CHECK-NEXT:    [[TMP4459:%.*]] = load i64, ptr [[ULLD]], align 8
23270 // CHECK-NEXT:    [[TMP4460:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4458]], i64 [[TMP4459]] monotonic monotonic, align 8
23271 // CHECK-NEXT:    [[TMP4461:%.*]] = extractvalue { i64, i1 } [[TMP4460]], 0
23272 // CHECK-NEXT:    store i64 [[TMP4461]], ptr [[ULLV]], align 8
23273 // CHECK-NEXT:    [[TMP4462:%.*]] = load i64, ptr [[ULLE]], align 8
23274 // CHECK-NEXT:    [[TMP4463:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4462]] monotonic, align 8
23275 // CHECK-NEXT:    [[TMP4464:%.*]] = icmp ugt i64 [[TMP4463]], [[TMP4462]]
23276 // CHECK-NEXT:    [[TMP4465:%.*]] = select i1 [[TMP4464]], i64 [[TMP4462]], i64 [[TMP4463]]
23277 // CHECK-NEXT:    store i64 [[TMP4465]], ptr [[ULLV]], align 8
23278 // CHECK-NEXT:    [[TMP4466:%.*]] = load i64, ptr [[ULLE]], align 8
23279 // CHECK-NEXT:    [[TMP4467:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4466]] monotonic, align 8
23280 // CHECK-NEXT:    [[TMP4468:%.*]] = icmp ult i64 [[TMP4467]], [[TMP4466]]
23281 // CHECK-NEXT:    [[TMP4469:%.*]] = select i1 [[TMP4468]], i64 [[TMP4466]], i64 [[TMP4467]]
23282 // CHECK-NEXT:    store i64 [[TMP4469]], ptr [[ULLV]], align 8
23283 // CHECK-NEXT:    [[TMP4470:%.*]] = load i64, ptr [[ULLE]], align 8
23284 // CHECK-NEXT:    [[TMP4471:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4470]] monotonic, align 8
23285 // CHECK-NEXT:    [[TMP4472:%.*]] = icmp ult i64 [[TMP4471]], [[TMP4470]]
23286 // CHECK-NEXT:    [[TMP4473:%.*]] = select i1 [[TMP4472]], i64 [[TMP4470]], i64 [[TMP4471]]
23287 // CHECK-NEXT:    store i64 [[TMP4473]], ptr [[ULLV]], align 8
23288 // CHECK-NEXT:    [[TMP4474:%.*]] = load i64, ptr [[ULLE]], align 8
23289 // CHECK-NEXT:    [[TMP4475:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4474]] monotonic, align 8
23290 // CHECK-NEXT:    [[TMP4476:%.*]] = icmp ugt i64 [[TMP4475]], [[TMP4474]]
23291 // CHECK-NEXT:    [[TMP4477:%.*]] = select i1 [[TMP4476]], i64 [[TMP4474]], i64 [[TMP4475]]
23292 // CHECK-NEXT:    store i64 [[TMP4477]], ptr [[ULLV]], align 8
23293 // CHECK-NEXT:    [[TMP4478:%.*]] = load i64, ptr [[ULLE]], align 8
23294 // CHECK-NEXT:    [[TMP4479:%.*]] = load i64, ptr [[ULLD]], align 8
23295 // CHECK-NEXT:    [[TMP4480:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4478]], i64 [[TMP4479]] monotonic monotonic, align 8
23296 // CHECK-NEXT:    [[TMP4481:%.*]] = extractvalue { i64, i1 } [[TMP4480]], 0
23297 // CHECK-NEXT:    [[TMP4482:%.*]] = extractvalue { i64, i1 } [[TMP4480]], 1
23298 // CHECK-NEXT:    [[TMP4483:%.*]] = select i1 [[TMP4482]], i64 [[TMP4478]], i64 [[TMP4481]]
23299 // CHECK-NEXT:    store i64 [[TMP4483]], ptr [[ULLV]], align 8
23300 // CHECK-NEXT:    [[TMP4484:%.*]] = load i64, ptr [[ULLE]], align 8
23301 // CHECK-NEXT:    [[TMP4485:%.*]] = load i64, ptr [[ULLD]], align 8
23302 // CHECK-NEXT:    [[TMP4486:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4484]], i64 [[TMP4485]] monotonic monotonic, align 8
23303 // CHECK-NEXT:    [[TMP4487:%.*]] = extractvalue { i64, i1 } [[TMP4486]], 0
23304 // CHECK-NEXT:    [[TMP4488:%.*]] = extractvalue { i64, i1 } [[TMP4486]], 1
23305 // CHECK-NEXT:    [[TMP4489:%.*]] = select i1 [[TMP4488]], i64 [[TMP4484]], i64 [[TMP4487]]
23306 // CHECK-NEXT:    store i64 [[TMP4489]], ptr [[ULLV]], align 8
23307 // CHECK-NEXT:    [[TMP4490:%.*]] = load i64, ptr [[ULLE]], align 8
23308 // CHECK-NEXT:    [[TMP4491:%.*]] = load i64, ptr [[ULLD]], align 8
23309 // CHECK-NEXT:    [[TMP4492:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4490]], i64 [[TMP4491]] monotonic monotonic, align 8
23310 // CHECK-NEXT:    [[TMP4493:%.*]] = extractvalue { i64, i1 } [[TMP4492]], 0
23311 // CHECK-NEXT:    [[TMP4494:%.*]] = extractvalue { i64, i1 } [[TMP4492]], 1
23312 // CHECK-NEXT:    br i1 [[TMP4494]], label [[ULLX_ATOMIC_EXIT437:%.*]], label [[ULLX_ATOMIC_CONT438:%.*]]
23313 // CHECK:       ullx.atomic.cont438:
23314 // CHECK-NEXT:    store i64 [[TMP4493]], ptr [[ULLV]], align 8
23315 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT437]]
23316 // CHECK:       ullx.atomic.exit437:
23317 // CHECK-NEXT:    [[TMP4495:%.*]] = load i64, ptr [[ULLE]], align 8
23318 // CHECK-NEXT:    [[TMP4496:%.*]] = load i64, ptr [[ULLD]], align 8
23319 // CHECK-NEXT:    [[TMP4497:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4495]], i64 [[TMP4496]] monotonic monotonic, align 8
23320 // CHECK-NEXT:    [[TMP4498:%.*]] = extractvalue { i64, i1 } [[TMP4497]], 0
23321 // CHECK-NEXT:    [[TMP4499:%.*]] = extractvalue { i64, i1 } [[TMP4497]], 1
23322 // CHECK-NEXT:    br i1 [[TMP4499]], label [[ULLX_ATOMIC_EXIT439:%.*]], label [[ULLX_ATOMIC_CONT440:%.*]]
23323 // CHECK:       ullx.atomic.cont440:
23324 // CHECK-NEXT:    store i64 [[TMP4498]], ptr [[ULLV]], align 8
23325 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT439]]
23326 // CHECK:       ullx.atomic.exit439:
23327 // CHECK-NEXT:    [[TMP4500:%.*]] = load i64, ptr [[ULLE]], align 8
23328 // CHECK-NEXT:    [[TMP4501:%.*]] = load i64, ptr [[ULLD]], align 8
23329 // CHECK-NEXT:    [[TMP4502:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4500]], i64 [[TMP4501]] monotonic monotonic, align 8
23330 // CHECK-NEXT:    [[TMP4503:%.*]] = extractvalue { i64, i1 } [[TMP4502]], 1
23331 // CHECK-NEXT:    [[TMP4504:%.*]] = zext i1 [[TMP4503]] to i64
23332 // CHECK-NEXT:    store i64 [[TMP4504]], ptr [[ULLR]], align 8
23333 // CHECK-NEXT:    [[TMP4505:%.*]] = load i64, ptr [[ULLE]], align 8
23334 // CHECK-NEXT:    [[TMP4506:%.*]] = load i64, ptr [[ULLD]], align 8
23335 // CHECK-NEXT:    [[TMP4507:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4505]], i64 [[TMP4506]] monotonic monotonic, align 8
23336 // CHECK-NEXT:    [[TMP4508:%.*]] = extractvalue { i64, i1 } [[TMP4507]], 1
23337 // CHECK-NEXT:    [[TMP4509:%.*]] = zext i1 [[TMP4508]] to i64
23338 // CHECK-NEXT:    store i64 [[TMP4509]], ptr [[ULLR]], align 8
23339 // CHECK-NEXT:    [[TMP4510:%.*]] = load i64, ptr [[ULLE]], align 8
23340 // CHECK-NEXT:    [[TMP4511:%.*]] = load i64, ptr [[ULLD]], align 8
23341 // CHECK-NEXT:    [[TMP4512:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4510]], i64 [[TMP4511]] monotonic monotonic, align 8
23342 // CHECK-NEXT:    [[TMP4513:%.*]] = extractvalue { i64, i1 } [[TMP4512]], 0
23343 // CHECK-NEXT:    [[TMP4514:%.*]] = extractvalue { i64, i1 } [[TMP4512]], 1
23344 // CHECK-NEXT:    br i1 [[TMP4514]], label [[ULLX_ATOMIC_EXIT441:%.*]], label [[ULLX_ATOMIC_CONT442:%.*]]
23345 // CHECK:       ullx.atomic.cont442:
23346 // CHECK-NEXT:    store i64 [[TMP4513]], ptr [[ULLV]], align 8
23347 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT441]]
23348 // CHECK:       ullx.atomic.exit441:
23349 // CHECK-NEXT:    [[TMP4515:%.*]] = extractvalue { i64, i1 } [[TMP4512]], 1
23350 // CHECK-NEXT:    [[TMP4516:%.*]] = zext i1 [[TMP4515]] to i64
23351 // CHECK-NEXT:    store i64 [[TMP4516]], ptr [[ULLR]], align 8
23352 // CHECK-NEXT:    [[TMP4517:%.*]] = load i64, ptr [[ULLE]], align 8
23353 // CHECK-NEXT:    [[TMP4518:%.*]] = load i64, ptr [[ULLD]], align 8
23354 // CHECK-NEXT:    [[TMP4519:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4517]], i64 [[TMP4518]] monotonic monotonic, align 8
23355 // CHECK-NEXT:    [[TMP4520:%.*]] = extractvalue { i64, i1 } [[TMP4519]], 0
23356 // CHECK-NEXT:    [[TMP4521:%.*]] = extractvalue { i64, i1 } [[TMP4519]], 1
23357 // CHECK-NEXT:    br i1 [[TMP4521]], label [[ULLX_ATOMIC_EXIT443:%.*]], label [[ULLX_ATOMIC_CONT444:%.*]]
23358 // CHECK:       ullx.atomic.cont444:
23359 // CHECK-NEXT:    store i64 [[TMP4520]], ptr [[ULLV]], align 8
23360 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT443]]
23361 // CHECK:       ullx.atomic.exit443:
23362 // CHECK-NEXT:    [[TMP4522:%.*]] = extractvalue { i64, i1 } [[TMP4519]], 1
23363 // CHECK-NEXT:    [[TMP4523:%.*]] = zext i1 [[TMP4522]] to i64
23364 // CHECK-NEXT:    store i64 [[TMP4523]], ptr [[ULLR]], align 8
23365 // CHECK-NEXT:    [[TMP4524:%.*]] = load i64, ptr [[ULLE]], align 8
23366 // CHECK-NEXT:    [[TMP4525:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4524]] release, align 8
23367 // CHECK-NEXT:    store i64 [[TMP4525]], ptr [[ULLV]], align 8
23368 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23369 // CHECK-NEXT:    [[TMP4526:%.*]] = load i64, ptr [[ULLE]], align 8
23370 // CHECK-NEXT:    [[TMP4527:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4526]] release, align 8
23371 // CHECK-NEXT:    store i64 [[TMP4527]], ptr [[ULLV]], align 8
23372 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23373 // CHECK-NEXT:    [[TMP4528:%.*]] = load i64, ptr [[ULLE]], align 8
23374 // CHECK-NEXT:    [[TMP4529:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4528]] release, align 8
23375 // CHECK-NEXT:    store i64 [[TMP4529]], ptr [[ULLV]], align 8
23376 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23377 // CHECK-NEXT:    [[TMP4530:%.*]] = load i64, ptr [[ULLE]], align 8
23378 // CHECK-NEXT:    [[TMP4531:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4530]] release, align 8
23379 // CHECK-NEXT:    store i64 [[TMP4531]], ptr [[ULLV]], align 8
23380 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23381 // CHECK-NEXT:    [[TMP4532:%.*]] = load i64, ptr [[ULLE]], align 8
23382 // CHECK-NEXT:    [[TMP4533:%.*]] = load i64, ptr [[ULLD]], align 8
23383 // CHECK-NEXT:    [[TMP4534:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4532]], i64 [[TMP4533]] release monotonic, align 8
23384 // CHECK-NEXT:    [[TMP4535:%.*]] = extractvalue { i64, i1 } [[TMP4534]], 0
23385 // CHECK-NEXT:    store i64 [[TMP4535]], ptr [[ULLV]], align 8
23386 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23387 // CHECK-NEXT:    [[TMP4536:%.*]] = load i64, ptr [[ULLE]], align 8
23388 // CHECK-NEXT:    [[TMP4537:%.*]] = load i64, ptr [[ULLD]], align 8
23389 // CHECK-NEXT:    [[TMP4538:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4536]], i64 [[TMP4537]] release monotonic, align 8
23390 // CHECK-NEXT:    [[TMP4539:%.*]] = extractvalue { i64, i1 } [[TMP4538]], 0
23391 // CHECK-NEXT:    store i64 [[TMP4539]], ptr [[ULLV]], align 8
23392 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23393 // CHECK-NEXT:    [[TMP4540:%.*]] = load i64, ptr [[ULLE]], align 8
23394 // CHECK-NEXT:    [[TMP4541:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4540]] release, align 8
23395 // CHECK-NEXT:    [[TMP4542:%.*]] = icmp ugt i64 [[TMP4541]], [[TMP4540]]
23396 // CHECK-NEXT:    [[TMP4543:%.*]] = select i1 [[TMP4542]], i64 [[TMP4540]], i64 [[TMP4541]]
23397 // CHECK-NEXT:    store i64 [[TMP4543]], ptr [[ULLV]], align 8
23398 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23399 // CHECK-NEXT:    [[TMP4544:%.*]] = load i64, ptr [[ULLE]], align 8
23400 // CHECK-NEXT:    [[TMP4545:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4544]] release, align 8
23401 // CHECK-NEXT:    [[TMP4546:%.*]] = icmp ult i64 [[TMP4545]], [[TMP4544]]
23402 // CHECK-NEXT:    [[TMP4547:%.*]] = select i1 [[TMP4546]], i64 [[TMP4544]], i64 [[TMP4545]]
23403 // CHECK-NEXT:    store i64 [[TMP4547]], ptr [[ULLV]], align 8
23404 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23405 // CHECK-NEXT:    [[TMP4548:%.*]] = load i64, ptr [[ULLE]], align 8
23406 // CHECK-NEXT:    [[TMP4549:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4548]] release, align 8
23407 // CHECK-NEXT:    [[TMP4550:%.*]] = icmp ult i64 [[TMP4549]], [[TMP4548]]
23408 // CHECK-NEXT:    [[TMP4551:%.*]] = select i1 [[TMP4550]], i64 [[TMP4548]], i64 [[TMP4549]]
23409 // CHECK-NEXT:    store i64 [[TMP4551]], ptr [[ULLV]], align 8
23410 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23411 // CHECK-NEXT:    [[TMP4552:%.*]] = load i64, ptr [[ULLE]], align 8
23412 // CHECK-NEXT:    [[TMP4553:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4552]] release, align 8
23413 // CHECK-NEXT:    [[TMP4554:%.*]] = icmp ugt i64 [[TMP4553]], [[TMP4552]]
23414 // CHECK-NEXT:    [[TMP4555:%.*]] = select i1 [[TMP4554]], i64 [[TMP4552]], i64 [[TMP4553]]
23415 // CHECK-NEXT:    store i64 [[TMP4555]], ptr [[ULLV]], align 8
23416 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23417 // CHECK-NEXT:    [[TMP4556:%.*]] = load i64, ptr [[ULLE]], align 8
23418 // CHECK-NEXT:    [[TMP4557:%.*]] = load i64, ptr [[ULLD]], align 8
23419 // CHECK-NEXT:    [[TMP4558:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4556]], i64 [[TMP4557]] release monotonic, align 8
23420 // CHECK-NEXT:    [[TMP4559:%.*]] = extractvalue { i64, i1 } [[TMP4558]], 0
23421 // CHECK-NEXT:    [[TMP4560:%.*]] = extractvalue { i64, i1 } [[TMP4558]], 1
23422 // CHECK-NEXT:    [[TMP4561:%.*]] = select i1 [[TMP4560]], i64 [[TMP4556]], i64 [[TMP4559]]
23423 // CHECK-NEXT:    store i64 [[TMP4561]], ptr [[ULLV]], align 8
23424 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23425 // CHECK-NEXT:    [[TMP4562:%.*]] = load i64, ptr [[ULLE]], align 8
23426 // CHECK-NEXT:    [[TMP4563:%.*]] = load i64, ptr [[ULLD]], align 8
23427 // CHECK-NEXT:    [[TMP4564:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4562]], i64 [[TMP4563]] release monotonic, align 8
23428 // CHECK-NEXT:    [[TMP4565:%.*]] = extractvalue { i64, i1 } [[TMP4564]], 0
23429 // CHECK-NEXT:    [[TMP4566:%.*]] = extractvalue { i64, i1 } [[TMP4564]], 1
23430 // CHECK-NEXT:    [[TMP4567:%.*]] = select i1 [[TMP4566]], i64 [[TMP4562]], i64 [[TMP4565]]
23431 // CHECK-NEXT:    store i64 [[TMP4567]], ptr [[ULLV]], align 8
23432 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23433 // CHECK-NEXT:    [[TMP4568:%.*]] = load i64, ptr [[ULLE]], align 8
23434 // CHECK-NEXT:    [[TMP4569:%.*]] = load i64, ptr [[ULLD]], align 8
23435 // CHECK-NEXT:    [[TMP4570:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4568]], i64 [[TMP4569]] release monotonic, align 8
23436 // CHECK-NEXT:    [[TMP4571:%.*]] = extractvalue { i64, i1 } [[TMP4570]], 0
23437 // CHECK-NEXT:    [[TMP4572:%.*]] = extractvalue { i64, i1 } [[TMP4570]], 1
23438 // CHECK-NEXT:    br i1 [[TMP4572]], label [[ULLX_ATOMIC_EXIT445:%.*]], label [[ULLX_ATOMIC_CONT446:%.*]]
23439 // CHECK:       ullx.atomic.cont446:
23440 // CHECK-NEXT:    store i64 [[TMP4571]], ptr [[ULLV]], align 8
23441 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT445]]
23442 // CHECK:       ullx.atomic.exit445:
23443 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23444 // CHECK-NEXT:    [[TMP4573:%.*]] = load i64, ptr [[ULLE]], align 8
23445 // CHECK-NEXT:    [[TMP4574:%.*]] = load i64, ptr [[ULLD]], align 8
23446 // CHECK-NEXT:    [[TMP4575:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4573]], i64 [[TMP4574]] release monotonic, align 8
23447 // CHECK-NEXT:    [[TMP4576:%.*]] = extractvalue { i64, i1 } [[TMP4575]], 0
23448 // CHECK-NEXT:    [[TMP4577:%.*]] = extractvalue { i64, i1 } [[TMP4575]], 1
23449 // CHECK-NEXT:    br i1 [[TMP4577]], label [[ULLX_ATOMIC_EXIT447:%.*]], label [[ULLX_ATOMIC_CONT448:%.*]]
23450 // CHECK:       ullx.atomic.cont448:
23451 // CHECK-NEXT:    store i64 [[TMP4576]], ptr [[ULLV]], align 8
23452 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT447]]
23453 // CHECK:       ullx.atomic.exit447:
23454 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23455 // CHECK-NEXT:    [[TMP4578:%.*]] = load i64, ptr [[ULLE]], align 8
23456 // CHECK-NEXT:    [[TMP4579:%.*]] = load i64, ptr [[ULLD]], align 8
23457 // CHECK-NEXT:    [[TMP4580:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4578]], i64 [[TMP4579]] release monotonic, align 8
23458 // CHECK-NEXT:    [[TMP4581:%.*]] = extractvalue { i64, i1 } [[TMP4580]], 1
23459 // CHECK-NEXT:    [[TMP4582:%.*]] = zext i1 [[TMP4581]] to i64
23460 // CHECK-NEXT:    store i64 [[TMP4582]], ptr [[ULLR]], align 8
23461 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23462 // CHECK-NEXT:    [[TMP4583:%.*]] = load i64, ptr [[ULLE]], align 8
23463 // CHECK-NEXT:    [[TMP4584:%.*]] = load i64, ptr [[ULLD]], align 8
23464 // CHECK-NEXT:    [[TMP4585:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4583]], i64 [[TMP4584]] release monotonic, align 8
23465 // CHECK-NEXT:    [[TMP4586:%.*]] = extractvalue { i64, i1 } [[TMP4585]], 1
23466 // CHECK-NEXT:    [[TMP4587:%.*]] = zext i1 [[TMP4586]] to i64
23467 // CHECK-NEXT:    store i64 [[TMP4587]], ptr [[ULLR]], align 8
23468 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23469 // CHECK-NEXT:    [[TMP4588:%.*]] = load i64, ptr [[ULLE]], align 8
23470 // CHECK-NEXT:    [[TMP4589:%.*]] = load i64, ptr [[ULLD]], align 8
23471 // CHECK-NEXT:    [[TMP4590:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4588]], i64 [[TMP4589]] release monotonic, align 8
23472 // CHECK-NEXT:    [[TMP4591:%.*]] = extractvalue { i64, i1 } [[TMP4590]], 0
23473 // CHECK-NEXT:    [[TMP4592:%.*]] = extractvalue { i64, i1 } [[TMP4590]], 1
23474 // CHECK-NEXT:    br i1 [[TMP4592]], label [[ULLX_ATOMIC_EXIT449:%.*]], label [[ULLX_ATOMIC_CONT450:%.*]]
23475 // CHECK:       ullx.atomic.cont450:
23476 // CHECK-NEXT:    store i64 [[TMP4591]], ptr [[ULLV]], align 8
23477 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT449]]
23478 // CHECK:       ullx.atomic.exit449:
23479 // CHECK-NEXT:    [[TMP4593:%.*]] = extractvalue { i64, i1 } [[TMP4590]], 1
23480 // CHECK-NEXT:    [[TMP4594:%.*]] = zext i1 [[TMP4593]] to i64
23481 // CHECK-NEXT:    store i64 [[TMP4594]], ptr [[ULLR]], align 8
23482 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23483 // CHECK-NEXT:    [[TMP4595:%.*]] = load i64, ptr [[ULLE]], align 8
23484 // CHECK-NEXT:    [[TMP4596:%.*]] = load i64, ptr [[ULLD]], align 8
23485 // CHECK-NEXT:    [[TMP4597:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4595]], i64 [[TMP4596]] release monotonic, align 8
23486 // CHECK-NEXT:    [[TMP4598:%.*]] = extractvalue { i64, i1 } [[TMP4597]], 0
23487 // CHECK-NEXT:    [[TMP4599:%.*]] = extractvalue { i64, i1 } [[TMP4597]], 1
23488 // CHECK-NEXT:    br i1 [[TMP4599]], label [[ULLX_ATOMIC_EXIT451:%.*]], label [[ULLX_ATOMIC_CONT452:%.*]]
23489 // CHECK:       ullx.atomic.cont452:
23490 // CHECK-NEXT:    store i64 [[TMP4598]], ptr [[ULLV]], align 8
23491 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT451]]
23492 // CHECK:       ullx.atomic.exit451:
23493 // CHECK-NEXT:    [[TMP4600:%.*]] = extractvalue { i64, i1 } [[TMP4597]], 1
23494 // CHECK-NEXT:    [[TMP4601:%.*]] = zext i1 [[TMP4600]] to i64
23495 // CHECK-NEXT:    store i64 [[TMP4601]], ptr [[ULLR]], align 8
23496 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23497 // CHECK-NEXT:    [[TMP4602:%.*]] = load i64, ptr [[ULLE]], align 8
23498 // CHECK-NEXT:    [[TMP4603:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4602]] seq_cst, align 8
23499 // CHECK-NEXT:    store i64 [[TMP4603]], ptr [[ULLV]], align 8
23500 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23501 // CHECK-NEXT:    [[TMP4604:%.*]] = load i64, ptr [[ULLE]], align 8
23502 // CHECK-NEXT:    [[TMP4605:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4604]] seq_cst, align 8
23503 // CHECK-NEXT:    store i64 [[TMP4605]], ptr [[ULLV]], align 8
23504 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23505 // CHECK-NEXT:    [[TMP4606:%.*]] = load i64, ptr [[ULLE]], align 8
23506 // CHECK-NEXT:    [[TMP4607:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4606]] seq_cst, align 8
23507 // CHECK-NEXT:    store i64 [[TMP4607]], ptr [[ULLV]], align 8
23508 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23509 // CHECK-NEXT:    [[TMP4608:%.*]] = load i64, ptr [[ULLE]], align 8
23510 // CHECK-NEXT:    [[TMP4609:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4608]] seq_cst, align 8
23511 // CHECK-NEXT:    store i64 [[TMP4609]], ptr [[ULLV]], align 8
23512 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23513 // CHECK-NEXT:    [[TMP4610:%.*]] = load i64, ptr [[ULLE]], align 8
23514 // CHECK-NEXT:    [[TMP4611:%.*]] = load i64, ptr [[ULLD]], align 8
23515 // CHECK-NEXT:    [[TMP4612:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4610]], i64 [[TMP4611]] seq_cst seq_cst, align 8
23516 // CHECK-NEXT:    [[TMP4613:%.*]] = extractvalue { i64, i1 } [[TMP4612]], 0
23517 // CHECK-NEXT:    store i64 [[TMP4613]], ptr [[ULLV]], align 8
23518 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23519 // CHECK-NEXT:    [[TMP4614:%.*]] = load i64, ptr [[ULLE]], align 8
23520 // CHECK-NEXT:    [[TMP4615:%.*]] = load i64, ptr [[ULLD]], align 8
23521 // CHECK-NEXT:    [[TMP4616:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4614]], i64 [[TMP4615]] seq_cst seq_cst, align 8
23522 // CHECK-NEXT:    [[TMP4617:%.*]] = extractvalue { i64, i1 } [[TMP4616]], 0
23523 // CHECK-NEXT:    store i64 [[TMP4617]], ptr [[ULLV]], align 8
23524 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23525 // CHECK-NEXT:    [[TMP4618:%.*]] = load i64, ptr [[ULLE]], align 8
23526 // CHECK-NEXT:    [[TMP4619:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4618]] seq_cst, align 8
23527 // CHECK-NEXT:    [[TMP4620:%.*]] = icmp ugt i64 [[TMP4619]], [[TMP4618]]
23528 // CHECK-NEXT:    [[TMP4621:%.*]] = select i1 [[TMP4620]], i64 [[TMP4618]], i64 [[TMP4619]]
23529 // CHECK-NEXT:    store i64 [[TMP4621]], ptr [[ULLV]], align 8
23530 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23531 // CHECK-NEXT:    [[TMP4622:%.*]] = load i64, ptr [[ULLE]], align 8
23532 // CHECK-NEXT:    [[TMP4623:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4622]] seq_cst, align 8
23533 // CHECK-NEXT:    [[TMP4624:%.*]] = icmp ult i64 [[TMP4623]], [[TMP4622]]
23534 // CHECK-NEXT:    [[TMP4625:%.*]] = select i1 [[TMP4624]], i64 [[TMP4622]], i64 [[TMP4623]]
23535 // CHECK-NEXT:    store i64 [[TMP4625]], ptr [[ULLV]], align 8
23536 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23537 // CHECK-NEXT:    [[TMP4626:%.*]] = load i64, ptr [[ULLE]], align 8
23538 // CHECK-NEXT:    [[TMP4627:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4626]] seq_cst, align 8
23539 // CHECK-NEXT:    [[TMP4628:%.*]] = icmp ult i64 [[TMP4627]], [[TMP4626]]
23540 // CHECK-NEXT:    [[TMP4629:%.*]] = select i1 [[TMP4628]], i64 [[TMP4626]], i64 [[TMP4627]]
23541 // CHECK-NEXT:    store i64 [[TMP4629]], ptr [[ULLV]], align 8
23542 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23543 // CHECK-NEXT:    [[TMP4630:%.*]] = load i64, ptr [[ULLE]], align 8
23544 // CHECK-NEXT:    [[TMP4631:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4630]] seq_cst, align 8
23545 // CHECK-NEXT:    [[TMP4632:%.*]] = icmp ugt i64 [[TMP4631]], [[TMP4630]]
23546 // CHECK-NEXT:    [[TMP4633:%.*]] = select i1 [[TMP4632]], i64 [[TMP4630]], i64 [[TMP4631]]
23547 // CHECK-NEXT:    store i64 [[TMP4633]], ptr [[ULLV]], align 8
23548 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23549 // CHECK-NEXT:    [[TMP4634:%.*]] = load i64, ptr [[ULLE]], align 8
23550 // CHECK-NEXT:    [[TMP4635:%.*]] = load i64, ptr [[ULLD]], align 8
23551 // CHECK-NEXT:    [[TMP4636:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4634]], i64 [[TMP4635]] seq_cst seq_cst, align 8
23552 // CHECK-NEXT:    [[TMP4637:%.*]] = extractvalue { i64, i1 } [[TMP4636]], 0
23553 // CHECK-NEXT:    [[TMP4638:%.*]] = extractvalue { i64, i1 } [[TMP4636]], 1
23554 // CHECK-NEXT:    [[TMP4639:%.*]] = select i1 [[TMP4638]], i64 [[TMP4634]], i64 [[TMP4637]]
23555 // CHECK-NEXT:    store i64 [[TMP4639]], ptr [[ULLV]], align 8
23556 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23557 // CHECK-NEXT:    [[TMP4640:%.*]] = load i64, ptr [[ULLE]], align 8
23558 // CHECK-NEXT:    [[TMP4641:%.*]] = load i64, ptr [[ULLD]], align 8
23559 // CHECK-NEXT:    [[TMP4642:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4640]], i64 [[TMP4641]] seq_cst seq_cst, align 8
23560 // CHECK-NEXT:    [[TMP4643:%.*]] = extractvalue { i64, i1 } [[TMP4642]], 0
23561 // CHECK-NEXT:    [[TMP4644:%.*]] = extractvalue { i64, i1 } [[TMP4642]], 1
23562 // CHECK-NEXT:    [[TMP4645:%.*]] = select i1 [[TMP4644]], i64 [[TMP4640]], i64 [[TMP4643]]
23563 // CHECK-NEXT:    store i64 [[TMP4645]], ptr [[ULLV]], align 8
23564 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23565 // CHECK-NEXT:    [[TMP4646:%.*]] = load i64, ptr [[ULLE]], align 8
23566 // CHECK-NEXT:    [[TMP4647:%.*]] = load i64, ptr [[ULLD]], align 8
23567 // CHECK-NEXT:    [[TMP4648:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4646]], i64 [[TMP4647]] seq_cst seq_cst, align 8
23568 // CHECK-NEXT:    [[TMP4649:%.*]] = extractvalue { i64, i1 } [[TMP4648]], 0
23569 // CHECK-NEXT:    [[TMP4650:%.*]] = extractvalue { i64, i1 } [[TMP4648]], 1
23570 // CHECK-NEXT:    br i1 [[TMP4650]], label [[ULLX_ATOMIC_EXIT453:%.*]], label [[ULLX_ATOMIC_CONT454:%.*]]
23571 // CHECK:       ullx.atomic.cont454:
23572 // CHECK-NEXT:    store i64 [[TMP4649]], ptr [[ULLV]], align 8
23573 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT453]]
23574 // CHECK:       ullx.atomic.exit453:
23575 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23576 // CHECK-NEXT:    [[TMP4651:%.*]] = load i64, ptr [[ULLE]], align 8
23577 // CHECK-NEXT:    [[TMP4652:%.*]] = load i64, ptr [[ULLD]], align 8
23578 // CHECK-NEXT:    [[TMP4653:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4651]], i64 [[TMP4652]] seq_cst seq_cst, align 8
23579 // CHECK-NEXT:    [[TMP4654:%.*]] = extractvalue { i64, i1 } [[TMP4653]], 0
23580 // CHECK-NEXT:    [[TMP4655:%.*]] = extractvalue { i64, i1 } [[TMP4653]], 1
23581 // CHECK-NEXT:    br i1 [[TMP4655]], label [[ULLX_ATOMIC_EXIT455:%.*]], label [[ULLX_ATOMIC_CONT456:%.*]]
23582 // CHECK:       ullx.atomic.cont456:
23583 // CHECK-NEXT:    store i64 [[TMP4654]], ptr [[ULLV]], align 8
23584 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT455]]
23585 // CHECK:       ullx.atomic.exit455:
23586 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23587 // CHECK-NEXT:    [[TMP4656:%.*]] = load i64, ptr [[ULLE]], align 8
23588 // CHECK-NEXT:    [[TMP4657:%.*]] = load i64, ptr [[ULLD]], align 8
23589 // CHECK-NEXT:    [[TMP4658:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4656]], i64 [[TMP4657]] seq_cst seq_cst, align 8
23590 // CHECK-NEXT:    [[TMP4659:%.*]] = extractvalue { i64, i1 } [[TMP4658]], 1
23591 // CHECK-NEXT:    [[TMP4660:%.*]] = zext i1 [[TMP4659]] to i64
23592 // CHECK-NEXT:    store i64 [[TMP4660]], ptr [[ULLR]], align 8
23593 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23594 // CHECK-NEXT:    [[TMP4661:%.*]] = load i64, ptr [[ULLE]], align 8
23595 // CHECK-NEXT:    [[TMP4662:%.*]] = load i64, ptr [[ULLD]], align 8
23596 // CHECK-NEXT:    [[TMP4663:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4661]], i64 [[TMP4662]] seq_cst seq_cst, align 8
23597 // CHECK-NEXT:    [[TMP4664:%.*]] = extractvalue { i64, i1 } [[TMP4663]], 1
23598 // CHECK-NEXT:    [[TMP4665:%.*]] = zext i1 [[TMP4664]] to i64
23599 // CHECK-NEXT:    store i64 [[TMP4665]], ptr [[ULLR]], align 8
23600 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23601 // CHECK-NEXT:    [[TMP4666:%.*]] = load i64, ptr [[ULLE]], align 8
23602 // CHECK-NEXT:    [[TMP4667:%.*]] = load i64, ptr [[ULLD]], align 8
23603 // CHECK-NEXT:    [[TMP4668:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4666]], i64 [[TMP4667]] seq_cst seq_cst, align 8
23604 // CHECK-NEXT:    [[TMP4669:%.*]] = extractvalue { i64, i1 } [[TMP4668]], 0
23605 // CHECK-NEXT:    [[TMP4670:%.*]] = extractvalue { i64, i1 } [[TMP4668]], 1
23606 // CHECK-NEXT:    br i1 [[TMP4670]], label [[ULLX_ATOMIC_EXIT457:%.*]], label [[ULLX_ATOMIC_CONT458:%.*]]
23607 // CHECK:       ullx.atomic.cont458:
23608 // CHECK-NEXT:    store i64 [[TMP4669]], ptr [[ULLV]], align 8
23609 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT457]]
23610 // CHECK:       ullx.atomic.exit457:
23611 // CHECK-NEXT:    [[TMP4671:%.*]] = extractvalue { i64, i1 } [[TMP4668]], 1
23612 // CHECK-NEXT:    [[TMP4672:%.*]] = zext i1 [[TMP4671]] to i64
23613 // CHECK-NEXT:    store i64 [[TMP4672]], ptr [[ULLR]], align 8
23614 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23615 // CHECK-NEXT:    [[TMP4673:%.*]] = load i64, ptr [[ULLE]], align 8
23616 // CHECK-NEXT:    [[TMP4674:%.*]] = load i64, ptr [[ULLD]], align 8
23617 // CHECK-NEXT:    [[TMP4675:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4673]], i64 [[TMP4674]] seq_cst seq_cst, align 8
23618 // CHECK-NEXT:    [[TMP4676:%.*]] = extractvalue { i64, i1 } [[TMP4675]], 0
23619 // CHECK-NEXT:    [[TMP4677:%.*]] = extractvalue { i64, i1 } [[TMP4675]], 1
23620 // CHECK-NEXT:    br i1 [[TMP4677]], label [[ULLX_ATOMIC_EXIT459:%.*]], label [[ULLX_ATOMIC_CONT460:%.*]]
23621 // CHECK:       ullx.atomic.cont460:
23622 // CHECK-NEXT:    store i64 [[TMP4676]], ptr [[ULLV]], align 8
23623 // CHECK-NEXT:    br label [[ULLX_ATOMIC_EXIT459]]
23624 // CHECK:       ullx.atomic.exit459:
23625 // CHECK-NEXT:    [[TMP4678:%.*]] = extractvalue { i64, i1 } [[TMP4675]], 1
23626 // CHECK-NEXT:    [[TMP4679:%.*]] = zext i1 [[TMP4678]] to i64
23627 // CHECK-NEXT:    store i64 [[TMP4679]], ptr [[ULLR]], align 8
23628 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23629 // CHECK-NEXT:    [[TMP4680:%.*]] = load float, ptr [[FE]], align 4
23630 // CHECK-NEXT:    [[TMP4681:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4680]] monotonic, align 4
23631 // CHECK-NEXT:    store float [[TMP4681]], ptr [[FV]], align 4
23632 // CHECK-NEXT:    [[TMP4682:%.*]] = load float, ptr [[FE]], align 4
23633 // CHECK-NEXT:    [[TMP4683:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4682]] monotonic, align 4
23634 // CHECK-NEXT:    store float [[TMP4683]], ptr [[FV]], align 4
23635 // CHECK-NEXT:    [[TMP4684:%.*]] = load float, ptr [[FE]], align 4
23636 // CHECK-NEXT:    [[TMP4685:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4684]] monotonic, align 4
23637 // CHECK-NEXT:    store float [[TMP4685]], ptr [[FV]], align 4
23638 // CHECK-NEXT:    [[TMP4686:%.*]] = load float, ptr [[FE]], align 4
23639 // CHECK-NEXT:    [[TMP4687:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4686]] monotonic, align 4
23640 // CHECK-NEXT:    store float [[TMP4687]], ptr [[FV]], align 4
23641 // CHECK-NEXT:    [[TMP4688:%.*]] = load float, ptr [[FE]], align 4
23642 // CHECK-NEXT:    [[TMP4689:%.*]] = load float, ptr [[FD]], align 4
23643 // CHECK-NEXT:    [[TMP4690:%.*]] = bitcast float [[TMP4688]] to i32
23644 // CHECK-NEXT:    [[TMP4691:%.*]] = bitcast float [[TMP4689]] to i32
23645 // CHECK-NEXT:    [[TMP4692:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4690]], i32 [[TMP4691]] monotonic monotonic, align 4
23646 // CHECK-NEXT:    [[TMP4693:%.*]] = extractvalue { i32, i1 } [[TMP4692]], 0
23647 // CHECK-NEXT:    [[TMP4694:%.*]] = bitcast i32 [[TMP4693]] to float
23648 // CHECK-NEXT:    store float [[TMP4694]], ptr [[FV]], align 4
23649 // CHECK-NEXT:    [[TMP4695:%.*]] = load float, ptr [[FE]], align 4
23650 // CHECK-NEXT:    [[TMP4696:%.*]] = load float, ptr [[FD]], align 4
23651 // CHECK-NEXT:    [[TMP4697:%.*]] = bitcast float [[TMP4695]] to i32
23652 // CHECK-NEXT:    [[TMP4698:%.*]] = bitcast float [[TMP4696]] to i32
23653 // CHECK-NEXT:    [[TMP4699:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4697]], i32 [[TMP4698]] monotonic monotonic, align 4
23654 // CHECK-NEXT:    [[TMP4700:%.*]] = extractvalue { i32, i1 } [[TMP4699]], 0
23655 // CHECK-NEXT:    [[TMP4701:%.*]] = bitcast i32 [[TMP4700]] to float
23656 // CHECK-NEXT:    store float [[TMP4701]], ptr [[FV]], align 4
23657 // CHECK-NEXT:    [[TMP4702:%.*]] = load float, ptr [[FE]], align 4
23658 // CHECK-NEXT:    [[TMP4703:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4702]] monotonic, align 4
23659 // CHECK-NEXT:    [[TMP4704:%.*]] = fcmp ogt float [[TMP4703]], [[TMP4702]]
23660 // CHECK-NEXT:    [[TMP4705:%.*]] = select i1 [[TMP4704]], float [[TMP4702]], float [[TMP4703]]
23661 // CHECK-NEXT:    store float [[TMP4705]], ptr [[FV]], align 4
23662 // CHECK-NEXT:    [[TMP4706:%.*]] = load float, ptr [[FE]], align 4
23663 // CHECK-NEXT:    [[TMP4707:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4706]] monotonic, align 4
23664 // CHECK-NEXT:    [[TMP4708:%.*]] = fcmp olt float [[TMP4707]], [[TMP4706]]
23665 // CHECK-NEXT:    [[TMP4709:%.*]] = select i1 [[TMP4708]], float [[TMP4706]], float [[TMP4707]]
23666 // CHECK-NEXT:    store float [[TMP4709]], ptr [[FV]], align 4
23667 // CHECK-NEXT:    [[TMP4710:%.*]] = load float, ptr [[FE]], align 4
23668 // CHECK-NEXT:    [[TMP4711:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4710]] monotonic, align 4
23669 // CHECK-NEXT:    [[TMP4712:%.*]] = fcmp olt float [[TMP4711]], [[TMP4710]]
23670 // CHECK-NEXT:    [[TMP4713:%.*]] = select i1 [[TMP4712]], float [[TMP4710]], float [[TMP4711]]
23671 // CHECK-NEXT:    store float [[TMP4713]], ptr [[FV]], align 4
23672 // CHECK-NEXT:    [[TMP4714:%.*]] = load float, ptr [[FE]], align 4
23673 // CHECK-NEXT:    [[TMP4715:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4714]] monotonic, align 4
23674 // CHECK-NEXT:    [[TMP4716:%.*]] = fcmp ogt float [[TMP4715]], [[TMP4714]]
23675 // CHECK-NEXT:    [[TMP4717:%.*]] = select i1 [[TMP4716]], float [[TMP4714]], float [[TMP4715]]
23676 // CHECK-NEXT:    store float [[TMP4717]], ptr [[FV]], align 4
23677 // CHECK-NEXT:    [[TMP4718:%.*]] = load float, ptr [[FE]], align 4
23678 // CHECK-NEXT:    [[TMP4719:%.*]] = load float, ptr [[FD]], align 4
23679 // CHECK-NEXT:    [[TMP4720:%.*]] = bitcast float [[TMP4718]] to i32
23680 // CHECK-NEXT:    [[TMP4721:%.*]] = bitcast float [[TMP4719]] to i32
23681 // CHECK-NEXT:    [[TMP4722:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4720]], i32 [[TMP4721]] monotonic monotonic, align 4
23682 // CHECK-NEXT:    [[TMP4723:%.*]] = extractvalue { i32, i1 } [[TMP4722]], 0
23683 // CHECK-NEXT:    [[TMP4724:%.*]] = bitcast i32 [[TMP4723]] to float
23684 // CHECK-NEXT:    [[TMP4725:%.*]] = extractvalue { i32, i1 } [[TMP4722]], 1
23685 // CHECK-NEXT:    [[TMP4726:%.*]] = select i1 [[TMP4725]], float [[TMP4718]], float [[TMP4724]]
23686 // CHECK-NEXT:    store float [[TMP4726]], ptr [[FV]], align 4
23687 // CHECK-NEXT:    [[TMP4727:%.*]] = load float, ptr [[FE]], align 4
23688 // CHECK-NEXT:    [[TMP4728:%.*]] = load float, ptr [[FD]], align 4
23689 // CHECK-NEXT:    [[TMP4729:%.*]] = bitcast float [[TMP4727]] to i32
23690 // CHECK-NEXT:    [[TMP4730:%.*]] = bitcast float [[TMP4728]] to i32
23691 // CHECK-NEXT:    [[TMP4731:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4729]], i32 [[TMP4730]] monotonic monotonic, align 4
23692 // CHECK-NEXT:    [[TMP4732:%.*]] = extractvalue { i32, i1 } [[TMP4731]], 0
23693 // CHECK-NEXT:    [[TMP4733:%.*]] = bitcast i32 [[TMP4732]] to float
23694 // CHECK-NEXT:    [[TMP4734:%.*]] = extractvalue { i32, i1 } [[TMP4731]], 1
23695 // CHECK-NEXT:    [[TMP4735:%.*]] = select i1 [[TMP4734]], float [[TMP4727]], float [[TMP4733]]
23696 // CHECK-NEXT:    store float [[TMP4735]], ptr [[FV]], align 4
23697 // CHECK-NEXT:    [[TMP4736:%.*]] = load float, ptr [[FE]], align 4
23698 // CHECK-NEXT:    [[TMP4737:%.*]] = load float, ptr [[FD]], align 4
23699 // CHECK-NEXT:    [[TMP4738:%.*]] = bitcast float [[TMP4736]] to i32
23700 // CHECK-NEXT:    [[TMP4739:%.*]] = bitcast float [[TMP4737]] to i32
23701 // CHECK-NEXT:    [[TMP4740:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4738]], i32 [[TMP4739]] monotonic monotonic, align 4
23702 // CHECK-NEXT:    [[TMP4741:%.*]] = extractvalue { i32, i1 } [[TMP4740]], 0
23703 // CHECK-NEXT:    [[TMP4742:%.*]] = bitcast i32 [[TMP4741]] to float
23704 // CHECK-NEXT:    [[TMP4743:%.*]] = extractvalue { i32, i1 } [[TMP4740]], 1
23705 // CHECK-NEXT:    br i1 [[TMP4743]], label [[FX_ATOMIC_EXIT:%.*]], label [[FX_ATOMIC_CONT:%.*]]
23706 // CHECK:       fx.atomic.cont:
23707 // CHECK-NEXT:    store float [[TMP4742]], ptr [[FV]], align 4
23708 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT]]
23709 // CHECK:       fx.atomic.exit:
23710 // CHECK-NEXT:    [[TMP4744:%.*]] = load float, ptr [[FE]], align 4
23711 // CHECK-NEXT:    [[TMP4745:%.*]] = load float, ptr [[FD]], align 4
23712 // CHECK-NEXT:    [[TMP4746:%.*]] = bitcast float [[TMP4744]] to i32
23713 // CHECK-NEXT:    [[TMP4747:%.*]] = bitcast float [[TMP4745]] to i32
23714 // CHECK-NEXT:    [[TMP4748:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4746]], i32 [[TMP4747]] monotonic monotonic, align 4
23715 // CHECK-NEXT:    [[TMP4749:%.*]] = extractvalue { i32, i1 } [[TMP4748]], 0
23716 // CHECK-NEXT:    [[TMP4750:%.*]] = bitcast i32 [[TMP4749]] to float
23717 // CHECK-NEXT:    [[TMP4751:%.*]] = extractvalue { i32, i1 } [[TMP4748]], 1
23718 // CHECK-NEXT:    br i1 [[TMP4751]], label [[FX_ATOMIC_EXIT461:%.*]], label [[FX_ATOMIC_CONT462:%.*]]
23719 // CHECK:       fx.atomic.cont462:
23720 // CHECK-NEXT:    store float [[TMP4750]], ptr [[FV]], align 4
23721 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT461]]
23722 // CHECK:       fx.atomic.exit461:
23723 // CHECK-NEXT:    [[TMP4752:%.*]] = load float, ptr [[FE]], align 4
23724 // CHECK-NEXT:    [[TMP4753:%.*]] = load float, ptr [[FD]], align 4
23725 // CHECK-NEXT:    [[TMP4754:%.*]] = bitcast float [[TMP4752]] to i32
23726 // CHECK-NEXT:    [[TMP4755:%.*]] = bitcast float [[TMP4753]] to i32
23727 // CHECK-NEXT:    [[TMP4756:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4754]], i32 [[TMP4755]] monotonic monotonic, align 4
23728 // CHECK-NEXT:    [[TMP4757:%.*]] = extractvalue { i32, i1 } [[TMP4756]], 1
23729 // CHECK-NEXT:    [[TMP4758:%.*]] = sext i1 [[TMP4757]] to i32
23730 // CHECK-NEXT:    store i32 [[TMP4758]], ptr [[IR]], align 4
23731 // CHECK-NEXT:    [[TMP4759:%.*]] = load float, ptr [[FE]], align 4
23732 // CHECK-NEXT:    [[TMP4760:%.*]] = load float, ptr [[FD]], align 4
23733 // CHECK-NEXT:    [[TMP4761:%.*]] = bitcast float [[TMP4759]] to i32
23734 // CHECK-NEXT:    [[TMP4762:%.*]] = bitcast float [[TMP4760]] to i32
23735 // CHECK-NEXT:    [[TMP4763:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4761]], i32 [[TMP4762]] monotonic monotonic, align 4
23736 // CHECK-NEXT:    [[TMP4764:%.*]] = extractvalue { i32, i1 } [[TMP4763]], 1
23737 // CHECK-NEXT:    [[TMP4765:%.*]] = sext i1 [[TMP4764]] to i32
23738 // CHECK-NEXT:    store i32 [[TMP4765]], ptr [[IR]], align 4
23739 // CHECK-NEXT:    [[TMP4766:%.*]] = load float, ptr [[FE]], align 4
23740 // CHECK-NEXT:    [[TMP4767:%.*]] = load float, ptr [[FD]], align 4
23741 // CHECK-NEXT:    [[TMP4768:%.*]] = bitcast float [[TMP4766]] to i32
23742 // CHECK-NEXT:    [[TMP4769:%.*]] = bitcast float [[TMP4767]] to i32
23743 // CHECK-NEXT:    [[TMP4770:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4768]], i32 [[TMP4769]] monotonic monotonic, align 4
23744 // CHECK-NEXT:    [[TMP4771:%.*]] = extractvalue { i32, i1 } [[TMP4770]], 0
23745 // CHECK-NEXT:    [[TMP4772:%.*]] = bitcast i32 [[TMP4771]] to float
23746 // CHECK-NEXT:    [[TMP4773:%.*]] = extractvalue { i32, i1 } [[TMP4770]], 1
23747 // CHECK-NEXT:    br i1 [[TMP4773]], label [[FX_ATOMIC_EXIT463:%.*]], label [[FX_ATOMIC_CONT464:%.*]]
23748 // CHECK:       fx.atomic.cont464:
23749 // CHECK-NEXT:    store float [[TMP4772]], ptr [[FV]], align 4
23750 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT463]]
23751 // CHECK:       fx.atomic.exit463:
23752 // CHECK-NEXT:    [[TMP4774:%.*]] = extractvalue { i32, i1 } [[TMP4770]], 1
23753 // CHECK-NEXT:    [[TMP4775:%.*]] = sext i1 [[TMP4774]] to i32
23754 // CHECK-NEXT:    store i32 [[TMP4775]], ptr [[IR]], align 4
23755 // CHECK-NEXT:    [[TMP4776:%.*]] = load float, ptr [[FE]], align 4
23756 // CHECK-NEXT:    [[TMP4777:%.*]] = load float, ptr [[FD]], align 4
23757 // CHECK-NEXT:    [[TMP4778:%.*]] = bitcast float [[TMP4776]] to i32
23758 // CHECK-NEXT:    [[TMP4779:%.*]] = bitcast float [[TMP4777]] to i32
23759 // CHECK-NEXT:    [[TMP4780:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4778]], i32 [[TMP4779]] monotonic monotonic, align 4
23760 // CHECK-NEXT:    [[TMP4781:%.*]] = extractvalue { i32, i1 } [[TMP4780]], 0
23761 // CHECK-NEXT:    [[TMP4782:%.*]] = bitcast i32 [[TMP4781]] to float
23762 // CHECK-NEXT:    [[TMP4783:%.*]] = extractvalue { i32, i1 } [[TMP4780]], 1
23763 // CHECK-NEXT:    br i1 [[TMP4783]], label [[FX_ATOMIC_EXIT465:%.*]], label [[FX_ATOMIC_CONT466:%.*]]
23764 // CHECK:       fx.atomic.cont466:
23765 // CHECK-NEXT:    store float [[TMP4782]], ptr [[FV]], align 4
23766 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT465]]
23767 // CHECK:       fx.atomic.exit465:
23768 // CHECK-NEXT:    [[TMP4784:%.*]] = extractvalue { i32, i1 } [[TMP4780]], 1
23769 // CHECK-NEXT:    [[TMP4785:%.*]] = sext i1 [[TMP4784]] to i32
23770 // CHECK-NEXT:    store i32 [[TMP4785]], ptr [[IR]], align 4
23771 // CHECK-NEXT:    [[TMP4786:%.*]] = load float, ptr [[FE]], align 4
23772 // CHECK-NEXT:    [[TMP4787:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4786]] acq_rel, align 4
23773 // CHECK-NEXT:    store float [[TMP4787]], ptr [[FV]], align 4
23774 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23775 // CHECK-NEXT:    [[TMP4788:%.*]] = load float, ptr [[FE]], align 4
23776 // CHECK-NEXT:    [[TMP4789:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4788]] acq_rel, align 4
23777 // CHECK-NEXT:    store float [[TMP4789]], ptr [[FV]], align 4
23778 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23779 // CHECK-NEXT:    [[TMP4790:%.*]] = load float, ptr [[FE]], align 4
23780 // CHECK-NEXT:    [[TMP4791:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4790]] acq_rel, align 4
23781 // CHECK-NEXT:    store float [[TMP4791]], ptr [[FV]], align 4
23782 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23783 // CHECK-NEXT:    [[TMP4792:%.*]] = load float, ptr [[FE]], align 4
23784 // CHECK-NEXT:    [[TMP4793:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4792]] acq_rel, align 4
23785 // CHECK-NEXT:    store float [[TMP4793]], ptr [[FV]], align 4
23786 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23787 // CHECK-NEXT:    [[TMP4794:%.*]] = load float, ptr [[FE]], align 4
23788 // CHECK-NEXT:    [[TMP4795:%.*]] = load float, ptr [[FD]], align 4
23789 // CHECK-NEXT:    [[TMP4796:%.*]] = bitcast float [[TMP4794]] to i32
23790 // CHECK-NEXT:    [[TMP4797:%.*]] = bitcast float [[TMP4795]] to i32
23791 // CHECK-NEXT:    [[TMP4798:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4796]], i32 [[TMP4797]] acq_rel acquire, align 4
23792 // CHECK-NEXT:    [[TMP4799:%.*]] = extractvalue { i32, i1 } [[TMP4798]], 0
23793 // CHECK-NEXT:    [[TMP4800:%.*]] = bitcast i32 [[TMP4799]] to float
23794 // CHECK-NEXT:    store float [[TMP4800]], ptr [[FV]], align 4
23795 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23796 // CHECK-NEXT:    [[TMP4801:%.*]] = load float, ptr [[FE]], align 4
23797 // CHECK-NEXT:    [[TMP4802:%.*]] = load float, ptr [[FD]], align 4
23798 // CHECK-NEXT:    [[TMP4803:%.*]] = bitcast float [[TMP4801]] to i32
23799 // CHECK-NEXT:    [[TMP4804:%.*]] = bitcast float [[TMP4802]] to i32
23800 // CHECK-NEXT:    [[TMP4805:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4803]], i32 [[TMP4804]] acq_rel acquire, align 4
23801 // CHECK-NEXT:    [[TMP4806:%.*]] = extractvalue { i32, i1 } [[TMP4805]], 0
23802 // CHECK-NEXT:    [[TMP4807:%.*]] = bitcast i32 [[TMP4806]] to float
23803 // CHECK-NEXT:    store float [[TMP4807]], ptr [[FV]], align 4
23804 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23805 // CHECK-NEXT:    [[TMP4808:%.*]] = load float, ptr [[FE]], align 4
23806 // CHECK-NEXT:    [[TMP4809:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4808]] acq_rel, align 4
23807 // CHECK-NEXT:    [[TMP4810:%.*]] = fcmp ogt float [[TMP4809]], [[TMP4808]]
23808 // CHECK-NEXT:    [[TMP4811:%.*]] = select i1 [[TMP4810]], float [[TMP4808]], float [[TMP4809]]
23809 // CHECK-NEXT:    store float [[TMP4811]], ptr [[FV]], align 4
23810 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23811 // CHECK-NEXT:    [[TMP4812:%.*]] = load float, ptr [[FE]], align 4
23812 // CHECK-NEXT:    [[TMP4813:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4812]] acq_rel, align 4
23813 // CHECK-NEXT:    [[TMP4814:%.*]] = fcmp olt float [[TMP4813]], [[TMP4812]]
23814 // CHECK-NEXT:    [[TMP4815:%.*]] = select i1 [[TMP4814]], float [[TMP4812]], float [[TMP4813]]
23815 // CHECK-NEXT:    store float [[TMP4815]], ptr [[FV]], align 4
23816 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23817 // CHECK-NEXT:    [[TMP4816:%.*]] = load float, ptr [[FE]], align 4
23818 // CHECK-NEXT:    [[TMP4817:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4816]] acq_rel, align 4
23819 // CHECK-NEXT:    [[TMP4818:%.*]] = fcmp olt float [[TMP4817]], [[TMP4816]]
23820 // CHECK-NEXT:    [[TMP4819:%.*]] = select i1 [[TMP4818]], float [[TMP4816]], float [[TMP4817]]
23821 // CHECK-NEXT:    store float [[TMP4819]], ptr [[FV]], align 4
23822 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23823 // CHECK-NEXT:    [[TMP4820:%.*]] = load float, ptr [[FE]], align 4
23824 // CHECK-NEXT:    [[TMP4821:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4820]] acq_rel, align 4
23825 // CHECK-NEXT:    [[TMP4822:%.*]] = fcmp ogt float [[TMP4821]], [[TMP4820]]
23826 // CHECK-NEXT:    [[TMP4823:%.*]] = select i1 [[TMP4822]], float [[TMP4820]], float [[TMP4821]]
23827 // CHECK-NEXT:    store float [[TMP4823]], ptr [[FV]], align 4
23828 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23829 // CHECK-NEXT:    [[TMP4824:%.*]] = load float, ptr [[FE]], align 4
23830 // CHECK-NEXT:    [[TMP4825:%.*]] = load float, ptr [[FD]], align 4
23831 // CHECK-NEXT:    [[TMP4826:%.*]] = bitcast float [[TMP4824]] to i32
23832 // CHECK-NEXT:    [[TMP4827:%.*]] = bitcast float [[TMP4825]] to i32
23833 // CHECK-NEXT:    [[TMP4828:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4826]], i32 [[TMP4827]] acq_rel acquire, align 4
23834 // CHECK-NEXT:    [[TMP4829:%.*]] = extractvalue { i32, i1 } [[TMP4828]], 0
23835 // CHECK-NEXT:    [[TMP4830:%.*]] = bitcast i32 [[TMP4829]] to float
23836 // CHECK-NEXT:    [[TMP4831:%.*]] = extractvalue { i32, i1 } [[TMP4828]], 1
23837 // CHECK-NEXT:    [[TMP4832:%.*]] = select i1 [[TMP4831]], float [[TMP4824]], float [[TMP4830]]
23838 // CHECK-NEXT:    store float [[TMP4832]], ptr [[FV]], align 4
23839 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23840 // CHECK-NEXT:    [[TMP4833:%.*]] = load float, ptr [[FE]], align 4
23841 // CHECK-NEXT:    [[TMP4834:%.*]] = load float, ptr [[FD]], align 4
23842 // CHECK-NEXT:    [[TMP4835:%.*]] = bitcast float [[TMP4833]] to i32
23843 // CHECK-NEXT:    [[TMP4836:%.*]] = bitcast float [[TMP4834]] to i32
23844 // CHECK-NEXT:    [[TMP4837:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4835]], i32 [[TMP4836]] acq_rel acquire, align 4
23845 // CHECK-NEXT:    [[TMP4838:%.*]] = extractvalue { i32, i1 } [[TMP4837]], 0
23846 // CHECK-NEXT:    [[TMP4839:%.*]] = bitcast i32 [[TMP4838]] to float
23847 // CHECK-NEXT:    [[TMP4840:%.*]] = extractvalue { i32, i1 } [[TMP4837]], 1
23848 // CHECK-NEXT:    [[TMP4841:%.*]] = select i1 [[TMP4840]], float [[TMP4833]], float [[TMP4839]]
23849 // CHECK-NEXT:    store float [[TMP4841]], ptr [[FV]], align 4
23850 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23851 // CHECK-NEXT:    [[TMP4842:%.*]] = load float, ptr [[FE]], align 4
23852 // CHECK-NEXT:    [[TMP4843:%.*]] = load float, ptr [[FD]], align 4
23853 // CHECK-NEXT:    [[TMP4844:%.*]] = bitcast float [[TMP4842]] to i32
23854 // CHECK-NEXT:    [[TMP4845:%.*]] = bitcast float [[TMP4843]] to i32
23855 // CHECK-NEXT:    [[TMP4846:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4844]], i32 [[TMP4845]] acq_rel acquire, align 4
23856 // CHECK-NEXT:    [[TMP4847:%.*]] = extractvalue { i32, i1 } [[TMP4846]], 0
23857 // CHECK-NEXT:    [[TMP4848:%.*]] = bitcast i32 [[TMP4847]] to float
23858 // CHECK-NEXT:    [[TMP4849:%.*]] = extractvalue { i32, i1 } [[TMP4846]], 1
23859 // CHECK-NEXT:    br i1 [[TMP4849]], label [[FX_ATOMIC_EXIT467:%.*]], label [[FX_ATOMIC_CONT468:%.*]]
23860 // CHECK:       fx.atomic.cont468:
23861 // CHECK-NEXT:    store float [[TMP4848]], ptr [[FV]], align 4
23862 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT467]]
23863 // CHECK:       fx.atomic.exit467:
23864 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23865 // CHECK-NEXT:    [[TMP4850:%.*]] = load float, ptr [[FE]], align 4
23866 // CHECK-NEXT:    [[TMP4851:%.*]] = load float, ptr [[FD]], align 4
23867 // CHECK-NEXT:    [[TMP4852:%.*]] = bitcast float [[TMP4850]] to i32
23868 // CHECK-NEXT:    [[TMP4853:%.*]] = bitcast float [[TMP4851]] to i32
23869 // CHECK-NEXT:    [[TMP4854:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4852]], i32 [[TMP4853]] acq_rel acquire, align 4
23870 // CHECK-NEXT:    [[TMP4855:%.*]] = extractvalue { i32, i1 } [[TMP4854]], 0
23871 // CHECK-NEXT:    [[TMP4856:%.*]] = bitcast i32 [[TMP4855]] to float
23872 // CHECK-NEXT:    [[TMP4857:%.*]] = extractvalue { i32, i1 } [[TMP4854]], 1
23873 // CHECK-NEXT:    br i1 [[TMP4857]], label [[FX_ATOMIC_EXIT469:%.*]], label [[FX_ATOMIC_CONT470:%.*]]
23874 // CHECK:       fx.atomic.cont470:
23875 // CHECK-NEXT:    store float [[TMP4856]], ptr [[FV]], align 4
23876 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT469]]
23877 // CHECK:       fx.atomic.exit469:
23878 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23879 // CHECK-NEXT:    [[TMP4858:%.*]] = load float, ptr [[FE]], align 4
23880 // CHECK-NEXT:    [[TMP4859:%.*]] = load float, ptr [[FD]], align 4
23881 // CHECK-NEXT:    [[TMP4860:%.*]] = bitcast float [[TMP4858]] to i32
23882 // CHECK-NEXT:    [[TMP4861:%.*]] = bitcast float [[TMP4859]] to i32
23883 // CHECK-NEXT:    [[TMP4862:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4860]], i32 [[TMP4861]] acq_rel acquire, align 4
23884 // CHECK-NEXT:    [[TMP4863:%.*]] = extractvalue { i32, i1 } [[TMP4862]], 1
23885 // CHECK-NEXT:    [[TMP4864:%.*]] = sext i1 [[TMP4863]] to i32
23886 // CHECK-NEXT:    store i32 [[TMP4864]], ptr [[IR]], align 4
23887 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23888 // CHECK-NEXT:    [[TMP4865:%.*]] = load float, ptr [[FE]], align 4
23889 // CHECK-NEXT:    [[TMP4866:%.*]] = load float, ptr [[FD]], align 4
23890 // CHECK-NEXT:    [[TMP4867:%.*]] = bitcast float [[TMP4865]] to i32
23891 // CHECK-NEXT:    [[TMP4868:%.*]] = bitcast float [[TMP4866]] to i32
23892 // CHECK-NEXT:    [[TMP4869:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4867]], i32 [[TMP4868]] acq_rel acquire, align 4
23893 // CHECK-NEXT:    [[TMP4870:%.*]] = extractvalue { i32, i1 } [[TMP4869]], 1
23894 // CHECK-NEXT:    [[TMP4871:%.*]] = sext i1 [[TMP4870]] to i32
23895 // CHECK-NEXT:    store i32 [[TMP4871]], ptr [[IR]], align 4
23896 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23897 // CHECK-NEXT:    [[TMP4872:%.*]] = load float, ptr [[FE]], align 4
23898 // CHECK-NEXT:    [[TMP4873:%.*]] = load float, ptr [[FD]], align 4
23899 // CHECK-NEXT:    [[TMP4874:%.*]] = bitcast float [[TMP4872]] to i32
23900 // CHECK-NEXT:    [[TMP4875:%.*]] = bitcast float [[TMP4873]] to i32
23901 // CHECK-NEXT:    [[TMP4876:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4874]], i32 [[TMP4875]] acq_rel acquire, align 4
23902 // CHECK-NEXT:    [[TMP4877:%.*]] = extractvalue { i32, i1 } [[TMP4876]], 0
23903 // CHECK-NEXT:    [[TMP4878:%.*]] = bitcast i32 [[TMP4877]] to float
23904 // CHECK-NEXT:    [[TMP4879:%.*]] = extractvalue { i32, i1 } [[TMP4876]], 1
23905 // CHECK-NEXT:    br i1 [[TMP4879]], label [[FX_ATOMIC_EXIT471:%.*]], label [[FX_ATOMIC_CONT472:%.*]]
23906 // CHECK:       fx.atomic.cont472:
23907 // CHECK-NEXT:    store float [[TMP4878]], ptr [[FV]], align 4
23908 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT471]]
23909 // CHECK:       fx.atomic.exit471:
23910 // CHECK-NEXT:    [[TMP4880:%.*]] = extractvalue { i32, i1 } [[TMP4876]], 1
23911 // CHECK-NEXT:    [[TMP4881:%.*]] = sext i1 [[TMP4880]] to i32
23912 // CHECK-NEXT:    store i32 [[TMP4881]], ptr [[IR]], align 4
23913 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23914 // CHECK-NEXT:    [[TMP4882:%.*]] = load float, ptr [[FE]], align 4
23915 // CHECK-NEXT:    [[TMP4883:%.*]] = load float, ptr [[FD]], align 4
23916 // CHECK-NEXT:    [[TMP4884:%.*]] = bitcast float [[TMP4882]] to i32
23917 // CHECK-NEXT:    [[TMP4885:%.*]] = bitcast float [[TMP4883]] to i32
23918 // CHECK-NEXT:    [[TMP4886:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4884]], i32 [[TMP4885]] acq_rel acquire, align 4
23919 // CHECK-NEXT:    [[TMP4887:%.*]] = extractvalue { i32, i1 } [[TMP4886]], 0
23920 // CHECK-NEXT:    [[TMP4888:%.*]] = bitcast i32 [[TMP4887]] to float
23921 // CHECK-NEXT:    [[TMP4889:%.*]] = extractvalue { i32, i1 } [[TMP4886]], 1
23922 // CHECK-NEXT:    br i1 [[TMP4889]], label [[FX_ATOMIC_EXIT473:%.*]], label [[FX_ATOMIC_CONT474:%.*]]
23923 // CHECK:       fx.atomic.cont474:
23924 // CHECK-NEXT:    store float [[TMP4888]], ptr [[FV]], align 4
23925 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT473]]
23926 // CHECK:       fx.atomic.exit473:
23927 // CHECK-NEXT:    [[TMP4890:%.*]] = extractvalue { i32, i1 } [[TMP4886]], 1
23928 // CHECK-NEXT:    [[TMP4891:%.*]] = sext i1 [[TMP4890]] to i32
23929 // CHECK-NEXT:    store i32 [[TMP4891]], ptr [[IR]], align 4
23930 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
23931 // CHECK-NEXT:    [[TMP4892:%.*]] = load float, ptr [[FE]], align 4
23932 // CHECK-NEXT:    [[TMP4893:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4892]] acquire, align 4
23933 // CHECK-NEXT:    store float [[TMP4893]], ptr [[FV]], align 4
23934 // CHECK-NEXT:    [[TMP4894:%.*]] = load float, ptr [[FE]], align 4
23935 // CHECK-NEXT:    [[TMP4895:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4894]] acquire, align 4
23936 // CHECK-NEXT:    store float [[TMP4895]], ptr [[FV]], align 4
23937 // CHECK-NEXT:    [[TMP4896:%.*]] = load float, ptr [[FE]], align 4
23938 // CHECK-NEXT:    [[TMP4897:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4896]] acquire, align 4
23939 // CHECK-NEXT:    store float [[TMP4897]], ptr [[FV]], align 4
23940 // CHECK-NEXT:    [[TMP4898:%.*]] = load float, ptr [[FE]], align 4
23941 // CHECK-NEXT:    [[TMP4899:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4898]] acquire, align 4
23942 // CHECK-NEXT:    store float [[TMP4899]], ptr [[FV]], align 4
23943 // CHECK-NEXT:    [[TMP4900:%.*]] = load float, ptr [[FE]], align 4
23944 // CHECK-NEXT:    [[TMP4901:%.*]] = load float, ptr [[FD]], align 4
23945 // CHECK-NEXT:    [[TMP4902:%.*]] = bitcast float [[TMP4900]] to i32
23946 // CHECK-NEXT:    [[TMP4903:%.*]] = bitcast float [[TMP4901]] to i32
23947 // CHECK-NEXT:    [[TMP4904:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4902]], i32 [[TMP4903]] acquire acquire, align 4
23948 // CHECK-NEXT:    [[TMP4905:%.*]] = extractvalue { i32, i1 } [[TMP4904]], 0
23949 // CHECK-NEXT:    [[TMP4906:%.*]] = bitcast i32 [[TMP4905]] to float
23950 // CHECK-NEXT:    store float [[TMP4906]], ptr [[FV]], align 4
23951 // CHECK-NEXT:    [[TMP4907:%.*]] = load float, ptr [[FE]], align 4
23952 // CHECK-NEXT:    [[TMP4908:%.*]] = load float, ptr [[FD]], align 4
23953 // CHECK-NEXT:    [[TMP4909:%.*]] = bitcast float [[TMP4907]] to i32
23954 // CHECK-NEXT:    [[TMP4910:%.*]] = bitcast float [[TMP4908]] to i32
23955 // CHECK-NEXT:    [[TMP4911:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4909]], i32 [[TMP4910]] acquire acquire, align 4
23956 // CHECK-NEXT:    [[TMP4912:%.*]] = extractvalue { i32, i1 } [[TMP4911]], 0
23957 // CHECK-NEXT:    [[TMP4913:%.*]] = bitcast i32 [[TMP4912]] to float
23958 // CHECK-NEXT:    store float [[TMP4913]], ptr [[FV]], align 4
23959 // CHECK-NEXT:    [[TMP4914:%.*]] = load float, ptr [[FE]], align 4
23960 // CHECK-NEXT:    [[TMP4915:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4914]] acquire, align 4
23961 // CHECK-NEXT:    [[TMP4916:%.*]] = fcmp ogt float [[TMP4915]], [[TMP4914]]
23962 // CHECK-NEXT:    [[TMP4917:%.*]] = select i1 [[TMP4916]], float [[TMP4914]], float [[TMP4915]]
23963 // CHECK-NEXT:    store float [[TMP4917]], ptr [[FV]], align 4
23964 // CHECK-NEXT:    [[TMP4918:%.*]] = load float, ptr [[FE]], align 4
23965 // CHECK-NEXT:    [[TMP4919:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4918]] acquire, align 4
23966 // CHECK-NEXT:    [[TMP4920:%.*]] = fcmp olt float [[TMP4919]], [[TMP4918]]
23967 // CHECK-NEXT:    [[TMP4921:%.*]] = select i1 [[TMP4920]], float [[TMP4918]], float [[TMP4919]]
23968 // CHECK-NEXT:    store float [[TMP4921]], ptr [[FV]], align 4
23969 // CHECK-NEXT:    [[TMP4922:%.*]] = load float, ptr [[FE]], align 4
23970 // CHECK-NEXT:    [[TMP4923:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4922]] acquire, align 4
23971 // CHECK-NEXT:    [[TMP4924:%.*]] = fcmp olt float [[TMP4923]], [[TMP4922]]
23972 // CHECK-NEXT:    [[TMP4925:%.*]] = select i1 [[TMP4924]], float [[TMP4922]], float [[TMP4923]]
23973 // CHECK-NEXT:    store float [[TMP4925]], ptr [[FV]], align 4
23974 // CHECK-NEXT:    [[TMP4926:%.*]] = load float, ptr [[FE]], align 4
23975 // CHECK-NEXT:    [[TMP4927:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4926]] acquire, align 4
23976 // CHECK-NEXT:    [[TMP4928:%.*]] = fcmp ogt float [[TMP4927]], [[TMP4926]]
23977 // CHECK-NEXT:    [[TMP4929:%.*]] = select i1 [[TMP4928]], float [[TMP4926]], float [[TMP4927]]
23978 // CHECK-NEXT:    store float [[TMP4929]], ptr [[FV]], align 4
23979 // CHECK-NEXT:    [[TMP4930:%.*]] = load float, ptr [[FE]], align 4
23980 // CHECK-NEXT:    [[TMP4931:%.*]] = load float, ptr [[FD]], align 4
23981 // CHECK-NEXT:    [[TMP4932:%.*]] = bitcast float [[TMP4930]] to i32
23982 // CHECK-NEXT:    [[TMP4933:%.*]] = bitcast float [[TMP4931]] to i32
23983 // CHECK-NEXT:    [[TMP4934:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4932]], i32 [[TMP4933]] acquire acquire, align 4
23984 // CHECK-NEXT:    [[TMP4935:%.*]] = extractvalue { i32, i1 } [[TMP4934]], 0
23985 // CHECK-NEXT:    [[TMP4936:%.*]] = bitcast i32 [[TMP4935]] to float
23986 // CHECK-NEXT:    [[TMP4937:%.*]] = extractvalue { i32, i1 } [[TMP4934]], 1
23987 // CHECK-NEXT:    [[TMP4938:%.*]] = select i1 [[TMP4937]], float [[TMP4930]], float [[TMP4936]]
23988 // CHECK-NEXT:    store float [[TMP4938]], ptr [[FV]], align 4
23989 // CHECK-NEXT:    [[TMP4939:%.*]] = load float, ptr [[FE]], align 4
23990 // CHECK-NEXT:    [[TMP4940:%.*]] = load float, ptr [[FD]], align 4
23991 // CHECK-NEXT:    [[TMP4941:%.*]] = bitcast float [[TMP4939]] to i32
23992 // CHECK-NEXT:    [[TMP4942:%.*]] = bitcast float [[TMP4940]] to i32
23993 // CHECK-NEXT:    [[TMP4943:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4941]], i32 [[TMP4942]] acquire acquire, align 4
23994 // CHECK-NEXT:    [[TMP4944:%.*]] = extractvalue { i32, i1 } [[TMP4943]], 0
23995 // CHECK-NEXT:    [[TMP4945:%.*]] = bitcast i32 [[TMP4944]] to float
23996 // CHECK-NEXT:    [[TMP4946:%.*]] = extractvalue { i32, i1 } [[TMP4943]], 1
23997 // CHECK-NEXT:    [[TMP4947:%.*]] = select i1 [[TMP4946]], float [[TMP4939]], float [[TMP4945]]
23998 // CHECK-NEXT:    store float [[TMP4947]], ptr [[FV]], align 4
23999 // CHECK-NEXT:    [[TMP4948:%.*]] = load float, ptr [[FE]], align 4
24000 // CHECK-NEXT:    [[TMP4949:%.*]] = load float, ptr [[FD]], align 4
24001 // CHECK-NEXT:    [[TMP4950:%.*]] = bitcast float [[TMP4948]] to i32
24002 // CHECK-NEXT:    [[TMP4951:%.*]] = bitcast float [[TMP4949]] to i32
24003 // CHECK-NEXT:    [[TMP4952:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4950]], i32 [[TMP4951]] acquire acquire, align 4
24004 // CHECK-NEXT:    [[TMP4953:%.*]] = extractvalue { i32, i1 } [[TMP4952]], 0
24005 // CHECK-NEXT:    [[TMP4954:%.*]] = bitcast i32 [[TMP4953]] to float
24006 // CHECK-NEXT:    [[TMP4955:%.*]] = extractvalue { i32, i1 } [[TMP4952]], 1
24007 // CHECK-NEXT:    br i1 [[TMP4955]], label [[FX_ATOMIC_EXIT475:%.*]], label [[FX_ATOMIC_CONT476:%.*]]
24008 // CHECK:       fx.atomic.cont476:
24009 // CHECK-NEXT:    store float [[TMP4954]], ptr [[FV]], align 4
24010 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT475]]
24011 // CHECK:       fx.atomic.exit475:
24012 // CHECK-NEXT:    [[TMP4956:%.*]] = load float, ptr [[FE]], align 4
24013 // CHECK-NEXT:    [[TMP4957:%.*]] = load float, ptr [[FD]], align 4
24014 // CHECK-NEXT:    [[TMP4958:%.*]] = bitcast float [[TMP4956]] to i32
24015 // CHECK-NEXT:    [[TMP4959:%.*]] = bitcast float [[TMP4957]] to i32
24016 // CHECK-NEXT:    [[TMP4960:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4958]], i32 [[TMP4959]] acquire acquire, align 4
24017 // CHECK-NEXT:    [[TMP4961:%.*]] = extractvalue { i32, i1 } [[TMP4960]], 0
24018 // CHECK-NEXT:    [[TMP4962:%.*]] = bitcast i32 [[TMP4961]] to float
24019 // CHECK-NEXT:    [[TMP4963:%.*]] = extractvalue { i32, i1 } [[TMP4960]], 1
24020 // CHECK-NEXT:    br i1 [[TMP4963]], label [[FX_ATOMIC_EXIT477:%.*]], label [[FX_ATOMIC_CONT478:%.*]]
24021 // CHECK:       fx.atomic.cont478:
24022 // CHECK-NEXT:    store float [[TMP4962]], ptr [[FV]], align 4
24023 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT477]]
24024 // CHECK:       fx.atomic.exit477:
24025 // CHECK-NEXT:    [[TMP4964:%.*]] = load float, ptr [[FE]], align 4
24026 // CHECK-NEXT:    [[TMP4965:%.*]] = load float, ptr [[FD]], align 4
24027 // CHECK-NEXT:    [[TMP4966:%.*]] = bitcast float [[TMP4964]] to i32
24028 // CHECK-NEXT:    [[TMP4967:%.*]] = bitcast float [[TMP4965]] to i32
24029 // CHECK-NEXT:    [[TMP4968:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4966]], i32 [[TMP4967]] acquire acquire, align 4
24030 // CHECK-NEXT:    [[TMP4969:%.*]] = extractvalue { i32, i1 } [[TMP4968]], 1
24031 // CHECK-NEXT:    [[TMP4970:%.*]] = sext i1 [[TMP4969]] to i32
24032 // CHECK-NEXT:    store i32 [[TMP4970]], ptr [[IR]], align 4
24033 // CHECK-NEXT:    [[TMP4971:%.*]] = load float, ptr [[FE]], align 4
24034 // CHECK-NEXT:    [[TMP4972:%.*]] = load float, ptr [[FD]], align 4
24035 // CHECK-NEXT:    [[TMP4973:%.*]] = bitcast float [[TMP4971]] to i32
24036 // CHECK-NEXT:    [[TMP4974:%.*]] = bitcast float [[TMP4972]] to i32
24037 // CHECK-NEXT:    [[TMP4975:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4973]], i32 [[TMP4974]] acquire acquire, align 4
24038 // CHECK-NEXT:    [[TMP4976:%.*]] = extractvalue { i32, i1 } [[TMP4975]], 1
24039 // CHECK-NEXT:    [[TMP4977:%.*]] = sext i1 [[TMP4976]] to i32
24040 // CHECK-NEXT:    store i32 [[TMP4977]], ptr [[IR]], align 4
24041 // CHECK-NEXT:    [[TMP4978:%.*]] = load float, ptr [[FE]], align 4
24042 // CHECK-NEXT:    [[TMP4979:%.*]] = load float, ptr [[FD]], align 4
24043 // CHECK-NEXT:    [[TMP4980:%.*]] = bitcast float [[TMP4978]] to i32
24044 // CHECK-NEXT:    [[TMP4981:%.*]] = bitcast float [[TMP4979]] to i32
24045 // CHECK-NEXT:    [[TMP4982:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4980]], i32 [[TMP4981]] acquire acquire, align 4
24046 // CHECK-NEXT:    [[TMP4983:%.*]] = extractvalue { i32, i1 } [[TMP4982]], 0
24047 // CHECK-NEXT:    [[TMP4984:%.*]] = bitcast i32 [[TMP4983]] to float
24048 // CHECK-NEXT:    [[TMP4985:%.*]] = extractvalue { i32, i1 } [[TMP4982]], 1
24049 // CHECK-NEXT:    br i1 [[TMP4985]], label [[FX_ATOMIC_EXIT479:%.*]], label [[FX_ATOMIC_CONT480:%.*]]
24050 // CHECK:       fx.atomic.cont480:
24051 // CHECK-NEXT:    store float [[TMP4984]], ptr [[FV]], align 4
24052 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT479]]
24053 // CHECK:       fx.atomic.exit479:
24054 // CHECK-NEXT:    [[TMP4986:%.*]] = extractvalue { i32, i1 } [[TMP4982]], 1
24055 // CHECK-NEXT:    [[TMP4987:%.*]] = sext i1 [[TMP4986]] to i32
24056 // CHECK-NEXT:    store i32 [[TMP4987]], ptr [[IR]], align 4
24057 // CHECK-NEXT:    [[TMP4988:%.*]] = load float, ptr [[FE]], align 4
24058 // CHECK-NEXT:    [[TMP4989:%.*]] = load float, ptr [[FD]], align 4
24059 // CHECK-NEXT:    [[TMP4990:%.*]] = bitcast float [[TMP4988]] to i32
24060 // CHECK-NEXT:    [[TMP4991:%.*]] = bitcast float [[TMP4989]] to i32
24061 // CHECK-NEXT:    [[TMP4992:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4990]], i32 [[TMP4991]] acquire acquire, align 4
24062 // CHECK-NEXT:    [[TMP4993:%.*]] = extractvalue { i32, i1 } [[TMP4992]], 0
24063 // CHECK-NEXT:    [[TMP4994:%.*]] = bitcast i32 [[TMP4993]] to float
24064 // CHECK-NEXT:    [[TMP4995:%.*]] = extractvalue { i32, i1 } [[TMP4992]], 1
24065 // CHECK-NEXT:    br i1 [[TMP4995]], label [[FX_ATOMIC_EXIT481:%.*]], label [[FX_ATOMIC_CONT482:%.*]]
24066 // CHECK:       fx.atomic.cont482:
24067 // CHECK-NEXT:    store float [[TMP4994]], ptr [[FV]], align 4
24068 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT481]]
24069 // CHECK:       fx.atomic.exit481:
24070 // CHECK-NEXT:    [[TMP4996:%.*]] = extractvalue { i32, i1 } [[TMP4992]], 1
24071 // CHECK-NEXT:    [[TMP4997:%.*]] = sext i1 [[TMP4996]] to i32
24072 // CHECK-NEXT:    store i32 [[TMP4997]], ptr [[IR]], align 4
24073 // CHECK-NEXT:    [[TMP4998:%.*]] = load float, ptr [[FE]], align 4
24074 // CHECK-NEXT:    [[TMP4999:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4998]] monotonic, align 4
24075 // CHECK-NEXT:    store float [[TMP4999]], ptr [[FV]], align 4
24076 // CHECK-NEXT:    [[TMP5000:%.*]] = load float, ptr [[FE]], align 4
24077 // CHECK-NEXT:    [[TMP5001:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5000]] monotonic, align 4
24078 // CHECK-NEXT:    store float [[TMP5001]], ptr [[FV]], align 4
24079 // CHECK-NEXT:    [[TMP5002:%.*]] = load float, ptr [[FE]], align 4
24080 // CHECK-NEXT:    [[TMP5003:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5002]] monotonic, align 4
24081 // CHECK-NEXT:    store float [[TMP5003]], ptr [[FV]], align 4
24082 // CHECK-NEXT:    [[TMP5004:%.*]] = load float, ptr [[FE]], align 4
24083 // CHECK-NEXT:    [[TMP5005:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5004]] monotonic, align 4
24084 // CHECK-NEXT:    store float [[TMP5005]], ptr [[FV]], align 4
24085 // CHECK-NEXT:    [[TMP5006:%.*]] = load float, ptr [[FE]], align 4
24086 // CHECK-NEXT:    [[TMP5007:%.*]] = load float, ptr [[FD]], align 4
24087 // CHECK-NEXT:    [[TMP5008:%.*]] = bitcast float [[TMP5006]] to i32
24088 // CHECK-NEXT:    [[TMP5009:%.*]] = bitcast float [[TMP5007]] to i32
24089 // CHECK-NEXT:    [[TMP5010:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5008]], i32 [[TMP5009]] monotonic monotonic, align 4
24090 // CHECK-NEXT:    [[TMP5011:%.*]] = extractvalue { i32, i1 } [[TMP5010]], 0
24091 // CHECK-NEXT:    [[TMP5012:%.*]] = bitcast i32 [[TMP5011]] to float
24092 // CHECK-NEXT:    store float [[TMP5012]], ptr [[FV]], align 4
24093 // CHECK-NEXT:    [[TMP5013:%.*]] = load float, ptr [[FE]], align 4
24094 // CHECK-NEXT:    [[TMP5014:%.*]] = load float, ptr [[FD]], align 4
24095 // CHECK-NEXT:    [[TMP5015:%.*]] = bitcast float [[TMP5013]] to i32
24096 // CHECK-NEXT:    [[TMP5016:%.*]] = bitcast float [[TMP5014]] to i32
24097 // CHECK-NEXT:    [[TMP5017:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5015]], i32 [[TMP5016]] monotonic monotonic, align 4
24098 // CHECK-NEXT:    [[TMP5018:%.*]] = extractvalue { i32, i1 } [[TMP5017]], 0
24099 // CHECK-NEXT:    [[TMP5019:%.*]] = bitcast i32 [[TMP5018]] to float
24100 // CHECK-NEXT:    store float [[TMP5019]], ptr [[FV]], align 4
24101 // CHECK-NEXT:    [[TMP5020:%.*]] = load float, ptr [[FE]], align 4
24102 // CHECK-NEXT:    [[TMP5021:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5020]] monotonic, align 4
24103 // CHECK-NEXT:    [[TMP5022:%.*]] = fcmp ogt float [[TMP5021]], [[TMP5020]]
24104 // CHECK-NEXT:    [[TMP5023:%.*]] = select i1 [[TMP5022]], float [[TMP5020]], float [[TMP5021]]
24105 // CHECK-NEXT:    store float [[TMP5023]], ptr [[FV]], align 4
24106 // CHECK-NEXT:    [[TMP5024:%.*]] = load float, ptr [[FE]], align 4
24107 // CHECK-NEXT:    [[TMP5025:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5024]] monotonic, align 4
24108 // CHECK-NEXT:    [[TMP5026:%.*]] = fcmp olt float [[TMP5025]], [[TMP5024]]
24109 // CHECK-NEXT:    [[TMP5027:%.*]] = select i1 [[TMP5026]], float [[TMP5024]], float [[TMP5025]]
24110 // CHECK-NEXT:    store float [[TMP5027]], ptr [[FV]], align 4
24111 // CHECK-NEXT:    [[TMP5028:%.*]] = load float, ptr [[FE]], align 4
24112 // CHECK-NEXT:    [[TMP5029:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5028]] monotonic, align 4
24113 // CHECK-NEXT:    [[TMP5030:%.*]] = fcmp olt float [[TMP5029]], [[TMP5028]]
24114 // CHECK-NEXT:    [[TMP5031:%.*]] = select i1 [[TMP5030]], float [[TMP5028]], float [[TMP5029]]
24115 // CHECK-NEXT:    store float [[TMP5031]], ptr [[FV]], align 4
24116 // CHECK-NEXT:    [[TMP5032:%.*]] = load float, ptr [[FE]], align 4
24117 // CHECK-NEXT:    [[TMP5033:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5032]] monotonic, align 4
24118 // CHECK-NEXT:    [[TMP5034:%.*]] = fcmp ogt float [[TMP5033]], [[TMP5032]]
24119 // CHECK-NEXT:    [[TMP5035:%.*]] = select i1 [[TMP5034]], float [[TMP5032]], float [[TMP5033]]
24120 // CHECK-NEXT:    store float [[TMP5035]], ptr [[FV]], align 4
24121 // CHECK-NEXT:    [[TMP5036:%.*]] = load float, ptr [[FE]], align 4
24122 // CHECK-NEXT:    [[TMP5037:%.*]] = load float, ptr [[FD]], align 4
24123 // CHECK-NEXT:    [[TMP5038:%.*]] = bitcast float [[TMP5036]] to i32
24124 // CHECK-NEXT:    [[TMP5039:%.*]] = bitcast float [[TMP5037]] to i32
24125 // CHECK-NEXT:    [[TMP5040:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5038]], i32 [[TMP5039]] monotonic monotonic, align 4
24126 // CHECK-NEXT:    [[TMP5041:%.*]] = extractvalue { i32, i1 } [[TMP5040]], 0
24127 // CHECK-NEXT:    [[TMP5042:%.*]] = bitcast i32 [[TMP5041]] to float
24128 // CHECK-NEXT:    [[TMP5043:%.*]] = extractvalue { i32, i1 } [[TMP5040]], 1
24129 // CHECK-NEXT:    [[TMP5044:%.*]] = select i1 [[TMP5043]], float [[TMP5036]], float [[TMP5042]]
24130 // CHECK-NEXT:    store float [[TMP5044]], ptr [[FV]], align 4
24131 // CHECK-NEXT:    [[TMP5045:%.*]] = load float, ptr [[FE]], align 4
24132 // CHECK-NEXT:    [[TMP5046:%.*]] = load float, ptr [[FD]], align 4
24133 // CHECK-NEXT:    [[TMP5047:%.*]] = bitcast float [[TMP5045]] to i32
24134 // CHECK-NEXT:    [[TMP5048:%.*]] = bitcast float [[TMP5046]] to i32
24135 // CHECK-NEXT:    [[TMP5049:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5047]], i32 [[TMP5048]] monotonic monotonic, align 4
24136 // CHECK-NEXT:    [[TMP5050:%.*]] = extractvalue { i32, i1 } [[TMP5049]], 0
24137 // CHECK-NEXT:    [[TMP5051:%.*]] = bitcast i32 [[TMP5050]] to float
24138 // CHECK-NEXT:    [[TMP5052:%.*]] = extractvalue { i32, i1 } [[TMP5049]], 1
24139 // CHECK-NEXT:    [[TMP5053:%.*]] = select i1 [[TMP5052]], float [[TMP5045]], float [[TMP5051]]
24140 // CHECK-NEXT:    store float [[TMP5053]], ptr [[FV]], align 4
24141 // CHECK-NEXT:    [[TMP5054:%.*]] = load float, ptr [[FE]], align 4
24142 // CHECK-NEXT:    [[TMP5055:%.*]] = load float, ptr [[FD]], align 4
24143 // CHECK-NEXT:    [[TMP5056:%.*]] = bitcast float [[TMP5054]] to i32
24144 // CHECK-NEXT:    [[TMP5057:%.*]] = bitcast float [[TMP5055]] to i32
24145 // CHECK-NEXT:    [[TMP5058:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5056]], i32 [[TMP5057]] monotonic monotonic, align 4
24146 // CHECK-NEXT:    [[TMP5059:%.*]] = extractvalue { i32, i1 } [[TMP5058]], 0
24147 // CHECK-NEXT:    [[TMP5060:%.*]] = bitcast i32 [[TMP5059]] to float
24148 // CHECK-NEXT:    [[TMP5061:%.*]] = extractvalue { i32, i1 } [[TMP5058]], 1
24149 // CHECK-NEXT:    br i1 [[TMP5061]], label [[FX_ATOMIC_EXIT483:%.*]], label [[FX_ATOMIC_CONT484:%.*]]
24150 // CHECK:       fx.atomic.cont484:
24151 // CHECK-NEXT:    store float [[TMP5060]], ptr [[FV]], align 4
24152 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT483]]
24153 // CHECK:       fx.atomic.exit483:
24154 // CHECK-NEXT:    [[TMP5062:%.*]] = load float, ptr [[FE]], align 4
24155 // CHECK-NEXT:    [[TMP5063:%.*]] = load float, ptr [[FD]], align 4
24156 // CHECK-NEXT:    [[TMP5064:%.*]] = bitcast float [[TMP5062]] to i32
24157 // CHECK-NEXT:    [[TMP5065:%.*]] = bitcast float [[TMP5063]] to i32
24158 // CHECK-NEXT:    [[TMP5066:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5064]], i32 [[TMP5065]] monotonic monotonic, align 4
24159 // CHECK-NEXT:    [[TMP5067:%.*]] = extractvalue { i32, i1 } [[TMP5066]], 0
24160 // CHECK-NEXT:    [[TMP5068:%.*]] = bitcast i32 [[TMP5067]] to float
24161 // CHECK-NEXT:    [[TMP5069:%.*]] = extractvalue { i32, i1 } [[TMP5066]], 1
24162 // CHECK-NEXT:    br i1 [[TMP5069]], label [[FX_ATOMIC_EXIT485:%.*]], label [[FX_ATOMIC_CONT486:%.*]]
24163 // CHECK:       fx.atomic.cont486:
24164 // CHECK-NEXT:    store float [[TMP5068]], ptr [[FV]], align 4
24165 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT485]]
24166 // CHECK:       fx.atomic.exit485:
24167 // CHECK-NEXT:    [[TMP5070:%.*]] = load float, ptr [[FE]], align 4
24168 // CHECK-NEXT:    [[TMP5071:%.*]] = load float, ptr [[FD]], align 4
24169 // CHECK-NEXT:    [[TMP5072:%.*]] = bitcast float [[TMP5070]] to i32
24170 // CHECK-NEXT:    [[TMP5073:%.*]] = bitcast float [[TMP5071]] to i32
24171 // CHECK-NEXT:    [[TMP5074:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5072]], i32 [[TMP5073]] monotonic monotonic, align 4
24172 // CHECK-NEXT:    [[TMP5075:%.*]] = extractvalue { i32, i1 } [[TMP5074]], 1
24173 // CHECK-NEXT:    [[TMP5076:%.*]] = sext i1 [[TMP5075]] to i32
24174 // CHECK-NEXT:    store i32 [[TMP5076]], ptr [[IR]], align 4
24175 // CHECK-NEXT:    [[TMP5077:%.*]] = load float, ptr [[FE]], align 4
24176 // CHECK-NEXT:    [[TMP5078:%.*]] = load float, ptr [[FD]], align 4
24177 // CHECK-NEXT:    [[TMP5079:%.*]] = bitcast float [[TMP5077]] to i32
24178 // CHECK-NEXT:    [[TMP5080:%.*]] = bitcast float [[TMP5078]] to i32
24179 // CHECK-NEXT:    [[TMP5081:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5079]], i32 [[TMP5080]] monotonic monotonic, align 4
24180 // CHECK-NEXT:    [[TMP5082:%.*]] = extractvalue { i32, i1 } [[TMP5081]], 1
24181 // CHECK-NEXT:    [[TMP5083:%.*]] = sext i1 [[TMP5082]] to i32
24182 // CHECK-NEXT:    store i32 [[TMP5083]], ptr [[IR]], align 4
24183 // CHECK-NEXT:    [[TMP5084:%.*]] = load float, ptr [[FE]], align 4
24184 // CHECK-NEXT:    [[TMP5085:%.*]] = load float, ptr [[FD]], align 4
24185 // CHECK-NEXT:    [[TMP5086:%.*]] = bitcast float [[TMP5084]] to i32
24186 // CHECK-NEXT:    [[TMP5087:%.*]] = bitcast float [[TMP5085]] to i32
24187 // CHECK-NEXT:    [[TMP5088:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5086]], i32 [[TMP5087]] monotonic monotonic, align 4
24188 // CHECK-NEXT:    [[TMP5089:%.*]] = extractvalue { i32, i1 } [[TMP5088]], 0
24189 // CHECK-NEXT:    [[TMP5090:%.*]] = bitcast i32 [[TMP5089]] to float
24190 // CHECK-NEXT:    [[TMP5091:%.*]] = extractvalue { i32, i1 } [[TMP5088]], 1
24191 // CHECK-NEXT:    br i1 [[TMP5091]], label [[FX_ATOMIC_EXIT487:%.*]], label [[FX_ATOMIC_CONT488:%.*]]
24192 // CHECK:       fx.atomic.cont488:
24193 // CHECK-NEXT:    store float [[TMP5090]], ptr [[FV]], align 4
24194 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT487]]
24195 // CHECK:       fx.atomic.exit487:
24196 // CHECK-NEXT:    [[TMP5092:%.*]] = extractvalue { i32, i1 } [[TMP5088]], 1
24197 // CHECK-NEXT:    [[TMP5093:%.*]] = sext i1 [[TMP5092]] to i32
24198 // CHECK-NEXT:    store i32 [[TMP5093]], ptr [[IR]], align 4
24199 // CHECK-NEXT:    [[TMP5094:%.*]] = load float, ptr [[FE]], align 4
24200 // CHECK-NEXT:    [[TMP5095:%.*]] = load float, ptr [[FD]], align 4
24201 // CHECK-NEXT:    [[TMP5096:%.*]] = bitcast float [[TMP5094]] to i32
24202 // CHECK-NEXT:    [[TMP5097:%.*]] = bitcast float [[TMP5095]] to i32
24203 // CHECK-NEXT:    [[TMP5098:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5096]], i32 [[TMP5097]] monotonic monotonic, align 4
24204 // CHECK-NEXT:    [[TMP5099:%.*]] = extractvalue { i32, i1 } [[TMP5098]], 0
24205 // CHECK-NEXT:    [[TMP5100:%.*]] = bitcast i32 [[TMP5099]] to float
24206 // CHECK-NEXT:    [[TMP5101:%.*]] = extractvalue { i32, i1 } [[TMP5098]], 1
24207 // CHECK-NEXT:    br i1 [[TMP5101]], label [[FX_ATOMIC_EXIT489:%.*]], label [[FX_ATOMIC_CONT490:%.*]]
24208 // CHECK:       fx.atomic.cont490:
24209 // CHECK-NEXT:    store float [[TMP5100]], ptr [[FV]], align 4
24210 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT489]]
24211 // CHECK:       fx.atomic.exit489:
24212 // CHECK-NEXT:    [[TMP5102:%.*]] = extractvalue { i32, i1 } [[TMP5098]], 1
24213 // CHECK-NEXT:    [[TMP5103:%.*]] = sext i1 [[TMP5102]] to i32
24214 // CHECK-NEXT:    store i32 [[TMP5103]], ptr [[IR]], align 4
24215 // CHECK-NEXT:    [[TMP5104:%.*]] = load float, ptr [[FE]], align 4
24216 // CHECK-NEXT:    [[TMP5105:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5104]] release, align 4
24217 // CHECK-NEXT:    store float [[TMP5105]], ptr [[FV]], align 4
24218 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24219 // CHECK-NEXT:    [[TMP5106:%.*]] = load float, ptr [[FE]], align 4
24220 // CHECK-NEXT:    [[TMP5107:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5106]] release, align 4
24221 // CHECK-NEXT:    store float [[TMP5107]], ptr [[FV]], align 4
24222 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24223 // CHECK-NEXT:    [[TMP5108:%.*]] = load float, ptr [[FE]], align 4
24224 // CHECK-NEXT:    [[TMP5109:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5108]] release, align 4
24225 // CHECK-NEXT:    store float [[TMP5109]], ptr [[FV]], align 4
24226 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24227 // CHECK-NEXT:    [[TMP5110:%.*]] = load float, ptr [[FE]], align 4
24228 // CHECK-NEXT:    [[TMP5111:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5110]] release, align 4
24229 // CHECK-NEXT:    store float [[TMP5111]], ptr [[FV]], align 4
24230 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24231 // CHECK-NEXT:    [[TMP5112:%.*]] = load float, ptr [[FE]], align 4
24232 // CHECK-NEXT:    [[TMP5113:%.*]] = load float, ptr [[FD]], align 4
24233 // CHECK-NEXT:    [[TMP5114:%.*]] = bitcast float [[TMP5112]] to i32
24234 // CHECK-NEXT:    [[TMP5115:%.*]] = bitcast float [[TMP5113]] to i32
24235 // CHECK-NEXT:    [[TMP5116:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5114]], i32 [[TMP5115]] release monotonic, align 4
24236 // CHECK-NEXT:    [[TMP5117:%.*]] = extractvalue { i32, i1 } [[TMP5116]], 0
24237 // CHECK-NEXT:    [[TMP5118:%.*]] = bitcast i32 [[TMP5117]] to float
24238 // CHECK-NEXT:    store float [[TMP5118]], ptr [[FV]], align 4
24239 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24240 // CHECK-NEXT:    [[TMP5119:%.*]] = load float, ptr [[FE]], align 4
24241 // CHECK-NEXT:    [[TMP5120:%.*]] = load float, ptr [[FD]], align 4
24242 // CHECK-NEXT:    [[TMP5121:%.*]] = bitcast float [[TMP5119]] to i32
24243 // CHECK-NEXT:    [[TMP5122:%.*]] = bitcast float [[TMP5120]] to i32
24244 // CHECK-NEXT:    [[TMP5123:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5121]], i32 [[TMP5122]] release monotonic, align 4
24245 // CHECK-NEXT:    [[TMP5124:%.*]] = extractvalue { i32, i1 } [[TMP5123]], 0
24246 // CHECK-NEXT:    [[TMP5125:%.*]] = bitcast i32 [[TMP5124]] to float
24247 // CHECK-NEXT:    store float [[TMP5125]], ptr [[FV]], align 4
24248 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24249 // CHECK-NEXT:    [[TMP5126:%.*]] = load float, ptr [[FE]], align 4
24250 // CHECK-NEXT:    [[TMP5127:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5126]] release, align 4
24251 // CHECK-NEXT:    [[TMP5128:%.*]] = fcmp ogt float [[TMP5127]], [[TMP5126]]
24252 // CHECK-NEXT:    [[TMP5129:%.*]] = select i1 [[TMP5128]], float [[TMP5126]], float [[TMP5127]]
24253 // CHECK-NEXT:    store float [[TMP5129]], ptr [[FV]], align 4
24254 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24255 // CHECK-NEXT:    [[TMP5130:%.*]] = load float, ptr [[FE]], align 4
24256 // CHECK-NEXT:    [[TMP5131:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5130]] release, align 4
24257 // CHECK-NEXT:    [[TMP5132:%.*]] = fcmp olt float [[TMP5131]], [[TMP5130]]
24258 // CHECK-NEXT:    [[TMP5133:%.*]] = select i1 [[TMP5132]], float [[TMP5130]], float [[TMP5131]]
24259 // CHECK-NEXT:    store float [[TMP5133]], ptr [[FV]], align 4
24260 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24261 // CHECK-NEXT:    [[TMP5134:%.*]] = load float, ptr [[FE]], align 4
24262 // CHECK-NEXT:    [[TMP5135:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5134]] release, align 4
24263 // CHECK-NEXT:    [[TMP5136:%.*]] = fcmp olt float [[TMP5135]], [[TMP5134]]
24264 // CHECK-NEXT:    [[TMP5137:%.*]] = select i1 [[TMP5136]], float [[TMP5134]], float [[TMP5135]]
24265 // CHECK-NEXT:    store float [[TMP5137]], ptr [[FV]], align 4
24266 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24267 // CHECK-NEXT:    [[TMP5138:%.*]] = load float, ptr [[FE]], align 4
24268 // CHECK-NEXT:    [[TMP5139:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5138]] release, align 4
24269 // CHECK-NEXT:    [[TMP5140:%.*]] = fcmp ogt float [[TMP5139]], [[TMP5138]]
24270 // CHECK-NEXT:    [[TMP5141:%.*]] = select i1 [[TMP5140]], float [[TMP5138]], float [[TMP5139]]
24271 // CHECK-NEXT:    store float [[TMP5141]], ptr [[FV]], align 4
24272 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24273 // CHECK-NEXT:    [[TMP5142:%.*]] = load float, ptr [[FE]], align 4
24274 // CHECK-NEXT:    [[TMP5143:%.*]] = load float, ptr [[FD]], align 4
24275 // CHECK-NEXT:    [[TMP5144:%.*]] = bitcast float [[TMP5142]] to i32
24276 // CHECK-NEXT:    [[TMP5145:%.*]] = bitcast float [[TMP5143]] to i32
24277 // CHECK-NEXT:    [[TMP5146:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5144]], i32 [[TMP5145]] release monotonic, align 4
24278 // CHECK-NEXT:    [[TMP5147:%.*]] = extractvalue { i32, i1 } [[TMP5146]], 0
24279 // CHECK-NEXT:    [[TMP5148:%.*]] = bitcast i32 [[TMP5147]] to float
24280 // CHECK-NEXT:    [[TMP5149:%.*]] = extractvalue { i32, i1 } [[TMP5146]], 1
24281 // CHECK-NEXT:    [[TMP5150:%.*]] = select i1 [[TMP5149]], float [[TMP5142]], float [[TMP5148]]
24282 // CHECK-NEXT:    store float [[TMP5150]], ptr [[FV]], align 4
24283 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24284 // CHECK-NEXT:    [[TMP5151:%.*]] = load float, ptr [[FE]], align 4
24285 // CHECK-NEXT:    [[TMP5152:%.*]] = load float, ptr [[FD]], align 4
24286 // CHECK-NEXT:    [[TMP5153:%.*]] = bitcast float [[TMP5151]] to i32
24287 // CHECK-NEXT:    [[TMP5154:%.*]] = bitcast float [[TMP5152]] to i32
24288 // CHECK-NEXT:    [[TMP5155:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5153]], i32 [[TMP5154]] release monotonic, align 4
24289 // CHECK-NEXT:    [[TMP5156:%.*]] = extractvalue { i32, i1 } [[TMP5155]], 0
24290 // CHECK-NEXT:    [[TMP5157:%.*]] = bitcast i32 [[TMP5156]] to float
24291 // CHECK-NEXT:    [[TMP5158:%.*]] = extractvalue { i32, i1 } [[TMP5155]], 1
24292 // CHECK-NEXT:    [[TMP5159:%.*]] = select i1 [[TMP5158]], float [[TMP5151]], float [[TMP5157]]
24293 // CHECK-NEXT:    store float [[TMP5159]], ptr [[FV]], align 4
24294 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24295 // CHECK-NEXT:    [[TMP5160:%.*]] = load float, ptr [[FE]], align 4
24296 // CHECK-NEXT:    [[TMP5161:%.*]] = load float, ptr [[FD]], align 4
24297 // CHECK-NEXT:    [[TMP5162:%.*]] = bitcast float [[TMP5160]] to i32
24298 // CHECK-NEXT:    [[TMP5163:%.*]] = bitcast float [[TMP5161]] to i32
24299 // CHECK-NEXT:    [[TMP5164:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5162]], i32 [[TMP5163]] release monotonic, align 4
24300 // CHECK-NEXT:    [[TMP5165:%.*]] = extractvalue { i32, i1 } [[TMP5164]], 0
24301 // CHECK-NEXT:    [[TMP5166:%.*]] = bitcast i32 [[TMP5165]] to float
24302 // CHECK-NEXT:    [[TMP5167:%.*]] = extractvalue { i32, i1 } [[TMP5164]], 1
24303 // CHECK-NEXT:    br i1 [[TMP5167]], label [[FX_ATOMIC_EXIT491:%.*]], label [[FX_ATOMIC_CONT492:%.*]]
24304 // CHECK:       fx.atomic.cont492:
24305 // CHECK-NEXT:    store float [[TMP5166]], ptr [[FV]], align 4
24306 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT491]]
24307 // CHECK:       fx.atomic.exit491:
24308 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24309 // CHECK-NEXT:    [[TMP5168:%.*]] = load float, ptr [[FE]], align 4
24310 // CHECK-NEXT:    [[TMP5169:%.*]] = load float, ptr [[FD]], align 4
24311 // CHECK-NEXT:    [[TMP5170:%.*]] = bitcast float [[TMP5168]] to i32
24312 // CHECK-NEXT:    [[TMP5171:%.*]] = bitcast float [[TMP5169]] to i32
24313 // CHECK-NEXT:    [[TMP5172:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5170]], i32 [[TMP5171]] release monotonic, align 4
24314 // CHECK-NEXT:    [[TMP5173:%.*]] = extractvalue { i32, i1 } [[TMP5172]], 0
24315 // CHECK-NEXT:    [[TMP5174:%.*]] = bitcast i32 [[TMP5173]] to float
24316 // CHECK-NEXT:    [[TMP5175:%.*]] = extractvalue { i32, i1 } [[TMP5172]], 1
24317 // CHECK-NEXT:    br i1 [[TMP5175]], label [[FX_ATOMIC_EXIT493:%.*]], label [[FX_ATOMIC_CONT494:%.*]]
24318 // CHECK:       fx.atomic.cont494:
24319 // CHECK-NEXT:    store float [[TMP5174]], ptr [[FV]], align 4
24320 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT493]]
24321 // CHECK:       fx.atomic.exit493:
24322 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24323 // CHECK-NEXT:    [[TMP5176:%.*]] = load float, ptr [[FE]], align 4
24324 // CHECK-NEXT:    [[TMP5177:%.*]] = load float, ptr [[FD]], align 4
24325 // CHECK-NEXT:    [[TMP5178:%.*]] = bitcast float [[TMP5176]] to i32
24326 // CHECK-NEXT:    [[TMP5179:%.*]] = bitcast float [[TMP5177]] to i32
24327 // CHECK-NEXT:    [[TMP5180:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5178]], i32 [[TMP5179]] release monotonic, align 4
24328 // CHECK-NEXT:    [[TMP5181:%.*]] = extractvalue { i32, i1 } [[TMP5180]], 1
24329 // CHECK-NEXT:    [[TMP5182:%.*]] = sext i1 [[TMP5181]] to i32
24330 // CHECK-NEXT:    store i32 [[TMP5182]], ptr [[IR]], align 4
24331 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24332 // CHECK-NEXT:    [[TMP5183:%.*]] = load float, ptr [[FE]], align 4
24333 // CHECK-NEXT:    [[TMP5184:%.*]] = load float, ptr [[FD]], align 4
24334 // CHECK-NEXT:    [[TMP5185:%.*]] = bitcast float [[TMP5183]] to i32
24335 // CHECK-NEXT:    [[TMP5186:%.*]] = bitcast float [[TMP5184]] to i32
24336 // CHECK-NEXT:    [[TMP5187:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5185]], i32 [[TMP5186]] release monotonic, align 4
24337 // CHECK-NEXT:    [[TMP5188:%.*]] = extractvalue { i32, i1 } [[TMP5187]], 1
24338 // CHECK-NEXT:    [[TMP5189:%.*]] = sext i1 [[TMP5188]] to i32
24339 // CHECK-NEXT:    store i32 [[TMP5189]], ptr [[IR]], align 4
24340 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24341 // CHECK-NEXT:    [[TMP5190:%.*]] = load float, ptr [[FE]], align 4
24342 // CHECK-NEXT:    [[TMP5191:%.*]] = load float, ptr [[FD]], align 4
24343 // CHECK-NEXT:    [[TMP5192:%.*]] = bitcast float [[TMP5190]] to i32
24344 // CHECK-NEXT:    [[TMP5193:%.*]] = bitcast float [[TMP5191]] to i32
24345 // CHECK-NEXT:    [[TMP5194:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5192]], i32 [[TMP5193]] release monotonic, align 4
24346 // CHECK-NEXT:    [[TMP5195:%.*]] = extractvalue { i32, i1 } [[TMP5194]], 0
24347 // CHECK-NEXT:    [[TMP5196:%.*]] = bitcast i32 [[TMP5195]] to float
24348 // CHECK-NEXT:    [[TMP5197:%.*]] = extractvalue { i32, i1 } [[TMP5194]], 1
24349 // CHECK-NEXT:    br i1 [[TMP5197]], label [[FX_ATOMIC_EXIT495:%.*]], label [[FX_ATOMIC_CONT496:%.*]]
24350 // CHECK:       fx.atomic.cont496:
24351 // CHECK-NEXT:    store float [[TMP5196]], ptr [[FV]], align 4
24352 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT495]]
24353 // CHECK:       fx.atomic.exit495:
24354 // CHECK-NEXT:    [[TMP5198:%.*]] = extractvalue { i32, i1 } [[TMP5194]], 1
24355 // CHECK-NEXT:    [[TMP5199:%.*]] = sext i1 [[TMP5198]] to i32
24356 // CHECK-NEXT:    store i32 [[TMP5199]], ptr [[IR]], align 4
24357 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24358 // CHECK-NEXT:    [[TMP5200:%.*]] = load float, ptr [[FE]], align 4
24359 // CHECK-NEXT:    [[TMP5201:%.*]] = load float, ptr [[FD]], align 4
24360 // CHECK-NEXT:    [[TMP5202:%.*]] = bitcast float [[TMP5200]] to i32
24361 // CHECK-NEXT:    [[TMP5203:%.*]] = bitcast float [[TMP5201]] to i32
24362 // CHECK-NEXT:    [[TMP5204:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5202]], i32 [[TMP5203]] release monotonic, align 4
24363 // CHECK-NEXT:    [[TMP5205:%.*]] = extractvalue { i32, i1 } [[TMP5204]], 0
24364 // CHECK-NEXT:    [[TMP5206:%.*]] = bitcast i32 [[TMP5205]] to float
24365 // CHECK-NEXT:    [[TMP5207:%.*]] = extractvalue { i32, i1 } [[TMP5204]], 1
24366 // CHECK-NEXT:    br i1 [[TMP5207]], label [[FX_ATOMIC_EXIT497:%.*]], label [[FX_ATOMIC_CONT498:%.*]]
24367 // CHECK:       fx.atomic.cont498:
24368 // CHECK-NEXT:    store float [[TMP5206]], ptr [[FV]], align 4
24369 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT497]]
24370 // CHECK:       fx.atomic.exit497:
24371 // CHECK-NEXT:    [[TMP5208:%.*]] = extractvalue { i32, i1 } [[TMP5204]], 1
24372 // CHECK-NEXT:    [[TMP5209:%.*]] = sext i1 [[TMP5208]] to i32
24373 // CHECK-NEXT:    store i32 [[TMP5209]], ptr [[IR]], align 4
24374 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24375 // CHECK-NEXT:    [[TMP5210:%.*]] = load float, ptr [[FE]], align 4
24376 // CHECK-NEXT:    [[TMP5211:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5210]] seq_cst, align 4
24377 // CHECK-NEXT:    store float [[TMP5211]], ptr [[FV]], align 4
24378 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24379 // CHECK-NEXT:    [[TMP5212:%.*]] = load float, ptr [[FE]], align 4
24380 // CHECK-NEXT:    [[TMP5213:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5212]] seq_cst, align 4
24381 // CHECK-NEXT:    store float [[TMP5213]], ptr [[FV]], align 4
24382 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24383 // CHECK-NEXT:    [[TMP5214:%.*]] = load float, ptr [[FE]], align 4
24384 // CHECK-NEXT:    [[TMP5215:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5214]] seq_cst, align 4
24385 // CHECK-NEXT:    store float [[TMP5215]], ptr [[FV]], align 4
24386 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24387 // CHECK-NEXT:    [[TMP5216:%.*]] = load float, ptr [[FE]], align 4
24388 // CHECK-NEXT:    [[TMP5217:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5216]] seq_cst, align 4
24389 // CHECK-NEXT:    store float [[TMP5217]], ptr [[FV]], align 4
24390 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24391 // CHECK-NEXT:    [[TMP5218:%.*]] = load float, ptr [[FE]], align 4
24392 // CHECK-NEXT:    [[TMP5219:%.*]] = load float, ptr [[FD]], align 4
24393 // CHECK-NEXT:    [[TMP5220:%.*]] = bitcast float [[TMP5218]] to i32
24394 // CHECK-NEXT:    [[TMP5221:%.*]] = bitcast float [[TMP5219]] to i32
24395 // CHECK-NEXT:    [[TMP5222:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5220]], i32 [[TMP5221]] seq_cst seq_cst, align 4
24396 // CHECK-NEXT:    [[TMP5223:%.*]] = extractvalue { i32, i1 } [[TMP5222]], 0
24397 // CHECK-NEXT:    [[TMP5224:%.*]] = bitcast i32 [[TMP5223]] to float
24398 // CHECK-NEXT:    store float [[TMP5224]], ptr [[FV]], align 4
24399 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24400 // CHECK-NEXT:    [[TMP5225:%.*]] = load float, ptr [[FE]], align 4
24401 // CHECK-NEXT:    [[TMP5226:%.*]] = load float, ptr [[FD]], align 4
24402 // CHECK-NEXT:    [[TMP5227:%.*]] = bitcast float [[TMP5225]] to i32
24403 // CHECK-NEXT:    [[TMP5228:%.*]] = bitcast float [[TMP5226]] to i32
24404 // CHECK-NEXT:    [[TMP5229:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5227]], i32 [[TMP5228]] seq_cst seq_cst, align 4
24405 // CHECK-NEXT:    [[TMP5230:%.*]] = extractvalue { i32, i1 } [[TMP5229]], 0
24406 // CHECK-NEXT:    [[TMP5231:%.*]] = bitcast i32 [[TMP5230]] to float
24407 // CHECK-NEXT:    store float [[TMP5231]], ptr [[FV]], align 4
24408 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24409 // CHECK-NEXT:    [[TMP5232:%.*]] = load float, ptr [[FE]], align 4
24410 // CHECK-NEXT:    [[TMP5233:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5232]] seq_cst, align 4
24411 // CHECK-NEXT:    [[TMP5234:%.*]] = fcmp ogt float [[TMP5233]], [[TMP5232]]
24412 // CHECK-NEXT:    [[TMP5235:%.*]] = select i1 [[TMP5234]], float [[TMP5232]], float [[TMP5233]]
24413 // CHECK-NEXT:    store float [[TMP5235]], ptr [[FV]], align 4
24414 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24415 // CHECK-NEXT:    [[TMP5236:%.*]] = load float, ptr [[FE]], align 4
24416 // CHECK-NEXT:    [[TMP5237:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5236]] seq_cst, align 4
24417 // CHECK-NEXT:    [[TMP5238:%.*]] = fcmp olt float [[TMP5237]], [[TMP5236]]
24418 // CHECK-NEXT:    [[TMP5239:%.*]] = select i1 [[TMP5238]], float [[TMP5236]], float [[TMP5237]]
24419 // CHECK-NEXT:    store float [[TMP5239]], ptr [[FV]], align 4
24420 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24421 // CHECK-NEXT:    [[TMP5240:%.*]] = load float, ptr [[FE]], align 4
24422 // CHECK-NEXT:    [[TMP5241:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5240]] seq_cst, align 4
24423 // CHECK-NEXT:    [[TMP5242:%.*]] = fcmp olt float [[TMP5241]], [[TMP5240]]
24424 // CHECK-NEXT:    [[TMP5243:%.*]] = select i1 [[TMP5242]], float [[TMP5240]], float [[TMP5241]]
24425 // CHECK-NEXT:    store float [[TMP5243]], ptr [[FV]], align 4
24426 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24427 // CHECK-NEXT:    [[TMP5244:%.*]] = load float, ptr [[FE]], align 4
24428 // CHECK-NEXT:    [[TMP5245:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5244]] seq_cst, align 4
24429 // CHECK-NEXT:    [[TMP5246:%.*]] = fcmp ogt float [[TMP5245]], [[TMP5244]]
24430 // CHECK-NEXT:    [[TMP5247:%.*]] = select i1 [[TMP5246]], float [[TMP5244]], float [[TMP5245]]
24431 // CHECK-NEXT:    store float [[TMP5247]], ptr [[FV]], align 4
24432 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24433 // CHECK-NEXT:    [[TMP5248:%.*]] = load float, ptr [[FE]], align 4
24434 // CHECK-NEXT:    [[TMP5249:%.*]] = load float, ptr [[FD]], align 4
24435 // CHECK-NEXT:    [[TMP5250:%.*]] = bitcast float [[TMP5248]] to i32
24436 // CHECK-NEXT:    [[TMP5251:%.*]] = bitcast float [[TMP5249]] to i32
24437 // CHECK-NEXT:    [[TMP5252:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5250]], i32 [[TMP5251]] seq_cst seq_cst, align 4
24438 // CHECK-NEXT:    [[TMP5253:%.*]] = extractvalue { i32, i1 } [[TMP5252]], 0
24439 // CHECK-NEXT:    [[TMP5254:%.*]] = bitcast i32 [[TMP5253]] to float
24440 // CHECK-NEXT:    [[TMP5255:%.*]] = extractvalue { i32, i1 } [[TMP5252]], 1
24441 // CHECK-NEXT:    [[TMP5256:%.*]] = select i1 [[TMP5255]], float [[TMP5248]], float [[TMP5254]]
24442 // CHECK-NEXT:    store float [[TMP5256]], ptr [[FV]], align 4
24443 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24444 // CHECK-NEXT:    [[TMP5257:%.*]] = load float, ptr [[FE]], align 4
24445 // CHECK-NEXT:    [[TMP5258:%.*]] = load float, ptr [[FD]], align 4
24446 // CHECK-NEXT:    [[TMP5259:%.*]] = bitcast float [[TMP5257]] to i32
24447 // CHECK-NEXT:    [[TMP5260:%.*]] = bitcast float [[TMP5258]] to i32
24448 // CHECK-NEXT:    [[TMP5261:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5259]], i32 [[TMP5260]] seq_cst seq_cst, align 4
24449 // CHECK-NEXT:    [[TMP5262:%.*]] = extractvalue { i32, i1 } [[TMP5261]], 0
24450 // CHECK-NEXT:    [[TMP5263:%.*]] = bitcast i32 [[TMP5262]] to float
24451 // CHECK-NEXT:    [[TMP5264:%.*]] = extractvalue { i32, i1 } [[TMP5261]], 1
24452 // CHECK-NEXT:    [[TMP5265:%.*]] = select i1 [[TMP5264]], float [[TMP5257]], float [[TMP5263]]
24453 // CHECK-NEXT:    store float [[TMP5265]], ptr [[FV]], align 4
24454 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24455 // CHECK-NEXT:    [[TMP5266:%.*]] = load float, ptr [[FE]], align 4
24456 // CHECK-NEXT:    [[TMP5267:%.*]] = load float, ptr [[FD]], align 4
24457 // CHECK-NEXT:    [[TMP5268:%.*]] = bitcast float [[TMP5266]] to i32
24458 // CHECK-NEXT:    [[TMP5269:%.*]] = bitcast float [[TMP5267]] to i32
24459 // CHECK-NEXT:    [[TMP5270:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5268]], i32 [[TMP5269]] seq_cst seq_cst, align 4
24460 // CHECK-NEXT:    [[TMP5271:%.*]] = extractvalue { i32, i1 } [[TMP5270]], 0
24461 // CHECK-NEXT:    [[TMP5272:%.*]] = bitcast i32 [[TMP5271]] to float
24462 // CHECK-NEXT:    [[TMP5273:%.*]] = extractvalue { i32, i1 } [[TMP5270]], 1
24463 // CHECK-NEXT:    br i1 [[TMP5273]], label [[FX_ATOMIC_EXIT499:%.*]], label [[FX_ATOMIC_CONT500:%.*]]
24464 // CHECK:       fx.atomic.cont500:
24465 // CHECK-NEXT:    store float [[TMP5272]], ptr [[FV]], align 4
24466 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT499]]
24467 // CHECK:       fx.atomic.exit499:
24468 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24469 // CHECK-NEXT:    [[TMP5274:%.*]] = load float, ptr [[FE]], align 4
24470 // CHECK-NEXT:    [[TMP5275:%.*]] = load float, ptr [[FD]], align 4
24471 // CHECK-NEXT:    [[TMP5276:%.*]] = bitcast float [[TMP5274]] to i32
24472 // CHECK-NEXT:    [[TMP5277:%.*]] = bitcast float [[TMP5275]] to i32
24473 // CHECK-NEXT:    [[TMP5278:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5276]], i32 [[TMP5277]] seq_cst seq_cst, align 4
24474 // CHECK-NEXT:    [[TMP5279:%.*]] = extractvalue { i32, i1 } [[TMP5278]], 0
24475 // CHECK-NEXT:    [[TMP5280:%.*]] = bitcast i32 [[TMP5279]] to float
24476 // CHECK-NEXT:    [[TMP5281:%.*]] = extractvalue { i32, i1 } [[TMP5278]], 1
24477 // CHECK-NEXT:    br i1 [[TMP5281]], label [[FX_ATOMIC_EXIT501:%.*]], label [[FX_ATOMIC_CONT502:%.*]]
24478 // CHECK:       fx.atomic.cont502:
24479 // CHECK-NEXT:    store float [[TMP5280]], ptr [[FV]], align 4
24480 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT501]]
24481 // CHECK:       fx.atomic.exit501:
24482 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24483 // CHECK-NEXT:    [[TMP5282:%.*]] = load float, ptr [[FE]], align 4
24484 // CHECK-NEXT:    [[TMP5283:%.*]] = load float, ptr [[FD]], align 4
24485 // CHECK-NEXT:    [[TMP5284:%.*]] = bitcast float [[TMP5282]] to i32
24486 // CHECK-NEXT:    [[TMP5285:%.*]] = bitcast float [[TMP5283]] to i32
24487 // CHECK-NEXT:    [[TMP5286:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5284]], i32 [[TMP5285]] seq_cst seq_cst, align 4
24488 // CHECK-NEXT:    [[TMP5287:%.*]] = extractvalue { i32, i1 } [[TMP5286]], 1
24489 // CHECK-NEXT:    [[TMP5288:%.*]] = sext i1 [[TMP5287]] to i32
24490 // CHECK-NEXT:    store i32 [[TMP5288]], ptr [[IR]], align 4
24491 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24492 // CHECK-NEXT:    [[TMP5289:%.*]] = load float, ptr [[FE]], align 4
24493 // CHECK-NEXT:    [[TMP5290:%.*]] = load float, ptr [[FD]], align 4
24494 // CHECK-NEXT:    [[TMP5291:%.*]] = bitcast float [[TMP5289]] to i32
24495 // CHECK-NEXT:    [[TMP5292:%.*]] = bitcast float [[TMP5290]] to i32
24496 // CHECK-NEXT:    [[TMP5293:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5291]], i32 [[TMP5292]] seq_cst seq_cst, align 4
24497 // CHECK-NEXT:    [[TMP5294:%.*]] = extractvalue { i32, i1 } [[TMP5293]], 1
24498 // CHECK-NEXT:    [[TMP5295:%.*]] = sext i1 [[TMP5294]] to i32
24499 // CHECK-NEXT:    store i32 [[TMP5295]], ptr [[IR]], align 4
24500 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24501 // CHECK-NEXT:    [[TMP5296:%.*]] = load float, ptr [[FE]], align 4
24502 // CHECK-NEXT:    [[TMP5297:%.*]] = load float, ptr [[FD]], align 4
24503 // CHECK-NEXT:    [[TMP5298:%.*]] = bitcast float [[TMP5296]] to i32
24504 // CHECK-NEXT:    [[TMP5299:%.*]] = bitcast float [[TMP5297]] to i32
24505 // CHECK-NEXT:    [[TMP5300:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5298]], i32 [[TMP5299]] seq_cst seq_cst, align 4
24506 // CHECK-NEXT:    [[TMP5301:%.*]] = extractvalue { i32, i1 } [[TMP5300]], 0
24507 // CHECK-NEXT:    [[TMP5302:%.*]] = bitcast i32 [[TMP5301]] to float
24508 // CHECK-NEXT:    [[TMP5303:%.*]] = extractvalue { i32, i1 } [[TMP5300]], 1
24509 // CHECK-NEXT:    br i1 [[TMP5303]], label [[FX_ATOMIC_EXIT503:%.*]], label [[FX_ATOMIC_CONT504:%.*]]
24510 // CHECK:       fx.atomic.cont504:
24511 // CHECK-NEXT:    store float [[TMP5302]], ptr [[FV]], align 4
24512 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT503]]
24513 // CHECK:       fx.atomic.exit503:
24514 // CHECK-NEXT:    [[TMP5304:%.*]] = extractvalue { i32, i1 } [[TMP5300]], 1
24515 // CHECK-NEXT:    [[TMP5305:%.*]] = sext i1 [[TMP5304]] to i32
24516 // CHECK-NEXT:    store i32 [[TMP5305]], ptr [[IR]], align 4
24517 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24518 // CHECK-NEXT:    [[TMP5306:%.*]] = load float, ptr [[FE]], align 4
24519 // CHECK-NEXT:    [[TMP5307:%.*]] = load float, ptr [[FD]], align 4
24520 // CHECK-NEXT:    [[TMP5308:%.*]] = bitcast float [[TMP5306]] to i32
24521 // CHECK-NEXT:    [[TMP5309:%.*]] = bitcast float [[TMP5307]] to i32
24522 // CHECK-NEXT:    [[TMP5310:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5308]], i32 [[TMP5309]] seq_cst seq_cst, align 4
24523 // CHECK-NEXT:    [[TMP5311:%.*]] = extractvalue { i32, i1 } [[TMP5310]], 0
24524 // CHECK-NEXT:    [[TMP5312:%.*]] = bitcast i32 [[TMP5311]] to float
24525 // CHECK-NEXT:    [[TMP5313:%.*]] = extractvalue { i32, i1 } [[TMP5310]], 1
24526 // CHECK-NEXT:    br i1 [[TMP5313]], label [[FX_ATOMIC_EXIT505:%.*]], label [[FX_ATOMIC_CONT506:%.*]]
24527 // CHECK:       fx.atomic.cont506:
24528 // CHECK-NEXT:    store float [[TMP5312]], ptr [[FV]], align 4
24529 // CHECK-NEXT:    br label [[FX_ATOMIC_EXIT505]]
24530 // CHECK:       fx.atomic.exit505:
24531 // CHECK-NEXT:    [[TMP5314:%.*]] = extractvalue { i32, i1 } [[TMP5310]], 1
24532 // CHECK-NEXT:    [[TMP5315:%.*]] = sext i1 [[TMP5314]] to i32
24533 // CHECK-NEXT:    store i32 [[TMP5315]], ptr [[IR]], align 4
24534 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24535 // CHECK-NEXT:    [[TMP5316:%.*]] = load double, ptr [[DE]], align 8
24536 // CHECK-NEXT:    [[TMP5317:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5316]] monotonic, align 8
24537 // CHECK-NEXT:    store double [[TMP5317]], ptr [[DV]], align 8
24538 // CHECK-NEXT:    [[TMP5318:%.*]] = load double, ptr [[DE]], align 8
24539 // CHECK-NEXT:    [[TMP5319:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5318]] monotonic, align 8
24540 // CHECK-NEXT:    store double [[TMP5319]], ptr [[DV]], align 8
24541 // CHECK-NEXT:    [[TMP5320:%.*]] = load double, ptr [[DE]], align 8
24542 // CHECK-NEXT:    [[TMP5321:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5320]] monotonic, align 8
24543 // CHECK-NEXT:    store double [[TMP5321]], ptr [[DV]], align 8
24544 // CHECK-NEXT:    [[TMP5322:%.*]] = load double, ptr [[DE]], align 8
24545 // CHECK-NEXT:    [[TMP5323:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5322]] monotonic, align 8
24546 // CHECK-NEXT:    store double [[TMP5323]], ptr [[DV]], align 8
24547 // CHECK-NEXT:    [[TMP5324:%.*]] = load double, ptr [[DE]], align 8
24548 // CHECK-NEXT:    [[TMP5325:%.*]] = load double, ptr [[DD]], align 8
24549 // CHECK-NEXT:    [[TMP5326:%.*]] = bitcast double [[TMP5324]] to i64
24550 // CHECK-NEXT:    [[TMP5327:%.*]] = bitcast double [[TMP5325]] to i64
24551 // CHECK-NEXT:    [[TMP5328:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5326]], i64 [[TMP5327]] monotonic monotonic, align 8
24552 // CHECK-NEXT:    [[TMP5329:%.*]] = extractvalue { i64, i1 } [[TMP5328]], 0
24553 // CHECK-NEXT:    [[TMP5330:%.*]] = bitcast i64 [[TMP5329]] to double
24554 // CHECK-NEXT:    store double [[TMP5330]], ptr [[DV]], align 8
24555 // CHECK-NEXT:    [[TMP5331:%.*]] = load double, ptr [[DE]], align 8
24556 // CHECK-NEXT:    [[TMP5332:%.*]] = load double, ptr [[DD]], align 8
24557 // CHECK-NEXT:    [[TMP5333:%.*]] = bitcast double [[TMP5331]] to i64
24558 // CHECK-NEXT:    [[TMP5334:%.*]] = bitcast double [[TMP5332]] to i64
24559 // CHECK-NEXT:    [[TMP5335:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5333]], i64 [[TMP5334]] monotonic monotonic, align 8
24560 // CHECK-NEXT:    [[TMP5336:%.*]] = extractvalue { i64, i1 } [[TMP5335]], 0
24561 // CHECK-NEXT:    [[TMP5337:%.*]] = bitcast i64 [[TMP5336]] to double
24562 // CHECK-NEXT:    store double [[TMP5337]], ptr [[DV]], align 8
24563 // CHECK-NEXT:    [[TMP5338:%.*]] = load double, ptr [[DE]], align 8
24564 // CHECK-NEXT:    [[TMP5339:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5338]] monotonic, align 8
24565 // CHECK-NEXT:    [[TMP5340:%.*]] = fcmp ogt double [[TMP5339]], [[TMP5338]]
24566 // CHECK-NEXT:    [[TMP5341:%.*]] = select i1 [[TMP5340]], double [[TMP5338]], double [[TMP5339]]
24567 // CHECK-NEXT:    store double [[TMP5341]], ptr [[DV]], align 8
24568 // CHECK-NEXT:    [[TMP5342:%.*]] = load double, ptr [[DE]], align 8
24569 // CHECK-NEXT:    [[TMP5343:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5342]] monotonic, align 8
24570 // CHECK-NEXT:    [[TMP5344:%.*]] = fcmp olt double [[TMP5343]], [[TMP5342]]
24571 // CHECK-NEXT:    [[TMP5345:%.*]] = select i1 [[TMP5344]], double [[TMP5342]], double [[TMP5343]]
24572 // CHECK-NEXT:    store double [[TMP5345]], ptr [[DV]], align 8
24573 // CHECK-NEXT:    [[TMP5346:%.*]] = load double, ptr [[DE]], align 8
24574 // CHECK-NEXT:    [[TMP5347:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5346]] monotonic, align 8
24575 // CHECK-NEXT:    [[TMP5348:%.*]] = fcmp olt double [[TMP5347]], [[TMP5346]]
24576 // CHECK-NEXT:    [[TMP5349:%.*]] = select i1 [[TMP5348]], double [[TMP5346]], double [[TMP5347]]
24577 // CHECK-NEXT:    store double [[TMP5349]], ptr [[DV]], align 8
24578 // CHECK-NEXT:    [[TMP5350:%.*]] = load double, ptr [[DE]], align 8
24579 // CHECK-NEXT:    [[TMP5351:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5350]] monotonic, align 8
24580 // CHECK-NEXT:    [[TMP5352:%.*]] = fcmp ogt double [[TMP5351]], [[TMP5350]]
24581 // CHECK-NEXT:    [[TMP5353:%.*]] = select i1 [[TMP5352]], double [[TMP5350]], double [[TMP5351]]
24582 // CHECK-NEXT:    store double [[TMP5353]], ptr [[DV]], align 8
24583 // CHECK-NEXT:    [[TMP5354:%.*]] = load double, ptr [[DE]], align 8
24584 // CHECK-NEXT:    [[TMP5355:%.*]] = load double, ptr [[DD]], align 8
24585 // CHECK-NEXT:    [[TMP5356:%.*]] = bitcast double [[TMP5354]] to i64
24586 // CHECK-NEXT:    [[TMP5357:%.*]] = bitcast double [[TMP5355]] to i64
24587 // CHECK-NEXT:    [[TMP5358:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5356]], i64 [[TMP5357]] monotonic monotonic, align 8
24588 // CHECK-NEXT:    [[TMP5359:%.*]] = extractvalue { i64, i1 } [[TMP5358]], 0
24589 // CHECK-NEXT:    [[TMP5360:%.*]] = bitcast i64 [[TMP5359]] to double
24590 // CHECK-NEXT:    [[TMP5361:%.*]] = extractvalue { i64, i1 } [[TMP5358]], 1
24591 // CHECK-NEXT:    [[TMP5362:%.*]] = select i1 [[TMP5361]], double [[TMP5354]], double [[TMP5360]]
24592 // CHECK-NEXT:    store double [[TMP5362]], ptr [[DV]], align 8
24593 // CHECK-NEXT:    [[TMP5363:%.*]] = load double, ptr [[DE]], align 8
24594 // CHECK-NEXT:    [[TMP5364:%.*]] = load double, ptr [[DD]], align 8
24595 // CHECK-NEXT:    [[TMP5365:%.*]] = bitcast double [[TMP5363]] to i64
24596 // CHECK-NEXT:    [[TMP5366:%.*]] = bitcast double [[TMP5364]] to i64
24597 // CHECK-NEXT:    [[TMP5367:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5365]], i64 [[TMP5366]] monotonic monotonic, align 8
24598 // CHECK-NEXT:    [[TMP5368:%.*]] = extractvalue { i64, i1 } [[TMP5367]], 0
24599 // CHECK-NEXT:    [[TMP5369:%.*]] = bitcast i64 [[TMP5368]] to double
24600 // CHECK-NEXT:    [[TMP5370:%.*]] = extractvalue { i64, i1 } [[TMP5367]], 1
24601 // CHECK-NEXT:    [[TMP5371:%.*]] = select i1 [[TMP5370]], double [[TMP5363]], double [[TMP5369]]
24602 // CHECK-NEXT:    store double [[TMP5371]], ptr [[DV]], align 8
24603 // CHECK-NEXT:    [[TMP5372:%.*]] = load double, ptr [[DE]], align 8
24604 // CHECK-NEXT:    [[TMP5373:%.*]] = load double, ptr [[DD]], align 8
24605 // CHECK-NEXT:    [[TMP5374:%.*]] = bitcast double [[TMP5372]] to i64
24606 // CHECK-NEXT:    [[TMP5375:%.*]] = bitcast double [[TMP5373]] to i64
24607 // CHECK-NEXT:    [[TMP5376:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5374]], i64 [[TMP5375]] monotonic monotonic, align 8
24608 // CHECK-NEXT:    [[TMP5377:%.*]] = extractvalue { i64, i1 } [[TMP5376]], 0
24609 // CHECK-NEXT:    [[TMP5378:%.*]] = bitcast i64 [[TMP5377]] to double
24610 // CHECK-NEXT:    [[TMP5379:%.*]] = extractvalue { i64, i1 } [[TMP5376]], 1
24611 // CHECK-NEXT:    br i1 [[TMP5379]], label [[DX_ATOMIC_EXIT:%.*]], label [[DX_ATOMIC_CONT:%.*]]
24612 // CHECK:       dx.atomic.cont:
24613 // CHECK-NEXT:    store double [[TMP5378]], ptr [[DV]], align 8
24614 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT]]
24615 // CHECK:       dx.atomic.exit:
24616 // CHECK-NEXT:    [[TMP5380:%.*]] = load double, ptr [[DE]], align 8
24617 // CHECK-NEXT:    [[TMP5381:%.*]] = load double, ptr [[DD]], align 8
24618 // CHECK-NEXT:    [[TMP5382:%.*]] = bitcast double [[TMP5380]] to i64
24619 // CHECK-NEXT:    [[TMP5383:%.*]] = bitcast double [[TMP5381]] to i64
24620 // CHECK-NEXT:    [[TMP5384:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5382]], i64 [[TMP5383]] monotonic monotonic, align 8
24621 // CHECK-NEXT:    [[TMP5385:%.*]] = extractvalue { i64, i1 } [[TMP5384]], 0
24622 // CHECK-NEXT:    [[TMP5386:%.*]] = bitcast i64 [[TMP5385]] to double
24623 // CHECK-NEXT:    [[TMP5387:%.*]] = extractvalue { i64, i1 } [[TMP5384]], 1
24624 // CHECK-NEXT:    br i1 [[TMP5387]], label [[DX_ATOMIC_EXIT507:%.*]], label [[DX_ATOMIC_CONT508:%.*]]
24625 // CHECK:       dx.atomic.cont508:
24626 // CHECK-NEXT:    store double [[TMP5386]], ptr [[DV]], align 8
24627 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT507]]
24628 // CHECK:       dx.atomic.exit507:
24629 // CHECK-NEXT:    [[TMP5388:%.*]] = load double, ptr [[DE]], align 8
24630 // CHECK-NEXT:    [[TMP5389:%.*]] = load double, ptr [[DD]], align 8
24631 // CHECK-NEXT:    [[TMP5390:%.*]] = bitcast double [[TMP5388]] to i64
24632 // CHECK-NEXT:    [[TMP5391:%.*]] = bitcast double [[TMP5389]] to i64
24633 // CHECK-NEXT:    [[TMP5392:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5390]], i64 [[TMP5391]] monotonic monotonic, align 8
24634 // CHECK-NEXT:    [[TMP5393:%.*]] = extractvalue { i64, i1 } [[TMP5392]], 1
24635 // CHECK-NEXT:    [[TMP5394:%.*]] = sext i1 [[TMP5393]] to i32
24636 // CHECK-NEXT:    store i32 [[TMP5394]], ptr [[IR]], align 4
24637 // CHECK-NEXT:    [[TMP5395:%.*]] = load double, ptr [[DE]], align 8
24638 // CHECK-NEXT:    [[TMP5396:%.*]] = load double, ptr [[DD]], align 8
24639 // CHECK-NEXT:    [[TMP5397:%.*]] = bitcast double [[TMP5395]] to i64
24640 // CHECK-NEXT:    [[TMP5398:%.*]] = bitcast double [[TMP5396]] to i64
24641 // CHECK-NEXT:    [[TMP5399:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5397]], i64 [[TMP5398]] monotonic monotonic, align 8
24642 // CHECK-NEXT:    [[TMP5400:%.*]] = extractvalue { i64, i1 } [[TMP5399]], 1
24643 // CHECK-NEXT:    [[TMP5401:%.*]] = sext i1 [[TMP5400]] to i32
24644 // CHECK-NEXT:    store i32 [[TMP5401]], ptr [[IR]], align 4
24645 // CHECK-NEXT:    [[TMP5402:%.*]] = load double, ptr [[DE]], align 8
24646 // CHECK-NEXT:    [[TMP5403:%.*]] = load double, ptr [[DD]], align 8
24647 // CHECK-NEXT:    [[TMP5404:%.*]] = bitcast double [[TMP5402]] to i64
24648 // CHECK-NEXT:    [[TMP5405:%.*]] = bitcast double [[TMP5403]] to i64
24649 // CHECK-NEXT:    [[TMP5406:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5404]], i64 [[TMP5405]] monotonic monotonic, align 8
24650 // CHECK-NEXT:    [[TMP5407:%.*]] = extractvalue { i64, i1 } [[TMP5406]], 0
24651 // CHECK-NEXT:    [[TMP5408:%.*]] = bitcast i64 [[TMP5407]] to double
24652 // CHECK-NEXT:    [[TMP5409:%.*]] = extractvalue { i64, i1 } [[TMP5406]], 1
24653 // CHECK-NEXT:    br i1 [[TMP5409]], label [[DX_ATOMIC_EXIT509:%.*]], label [[DX_ATOMIC_CONT510:%.*]]
24654 // CHECK:       dx.atomic.cont510:
24655 // CHECK-NEXT:    store double [[TMP5408]], ptr [[DV]], align 8
24656 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT509]]
24657 // CHECK:       dx.atomic.exit509:
24658 // CHECK-NEXT:    [[TMP5410:%.*]] = extractvalue { i64, i1 } [[TMP5406]], 1
24659 // CHECK-NEXT:    [[TMP5411:%.*]] = sext i1 [[TMP5410]] to i32
24660 // CHECK-NEXT:    store i32 [[TMP5411]], ptr [[IR]], align 4
24661 // CHECK-NEXT:    [[TMP5412:%.*]] = load double, ptr [[DE]], align 8
24662 // CHECK-NEXT:    [[TMP5413:%.*]] = load double, ptr [[DD]], align 8
24663 // CHECK-NEXT:    [[TMP5414:%.*]] = bitcast double [[TMP5412]] to i64
24664 // CHECK-NEXT:    [[TMP5415:%.*]] = bitcast double [[TMP5413]] to i64
24665 // CHECK-NEXT:    [[TMP5416:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5414]], i64 [[TMP5415]] monotonic monotonic, align 8
24666 // CHECK-NEXT:    [[TMP5417:%.*]] = extractvalue { i64, i1 } [[TMP5416]], 0
24667 // CHECK-NEXT:    [[TMP5418:%.*]] = bitcast i64 [[TMP5417]] to double
24668 // CHECK-NEXT:    [[TMP5419:%.*]] = extractvalue { i64, i1 } [[TMP5416]], 1
24669 // CHECK-NEXT:    br i1 [[TMP5419]], label [[DX_ATOMIC_EXIT511:%.*]], label [[DX_ATOMIC_CONT512:%.*]]
24670 // CHECK:       dx.atomic.cont512:
24671 // CHECK-NEXT:    store double [[TMP5418]], ptr [[DV]], align 8
24672 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT511]]
24673 // CHECK:       dx.atomic.exit511:
24674 // CHECK-NEXT:    [[TMP5420:%.*]] = extractvalue { i64, i1 } [[TMP5416]], 1
24675 // CHECK-NEXT:    [[TMP5421:%.*]] = sext i1 [[TMP5420]] to i32
24676 // CHECK-NEXT:    store i32 [[TMP5421]], ptr [[IR]], align 4
24677 // CHECK-NEXT:    [[TMP5422:%.*]] = load double, ptr [[DE]], align 8
24678 // CHECK-NEXT:    [[TMP5423:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5422]] acq_rel, align 8
24679 // CHECK-NEXT:    store double [[TMP5423]], ptr [[DV]], align 8
24680 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24681 // CHECK-NEXT:    [[TMP5424:%.*]] = load double, ptr [[DE]], align 8
24682 // CHECK-NEXT:    [[TMP5425:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5424]] acq_rel, align 8
24683 // CHECK-NEXT:    store double [[TMP5425]], ptr [[DV]], align 8
24684 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24685 // CHECK-NEXT:    [[TMP5426:%.*]] = load double, ptr [[DE]], align 8
24686 // CHECK-NEXT:    [[TMP5427:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5426]] acq_rel, align 8
24687 // CHECK-NEXT:    store double [[TMP5427]], ptr [[DV]], align 8
24688 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24689 // CHECK-NEXT:    [[TMP5428:%.*]] = load double, ptr [[DE]], align 8
24690 // CHECK-NEXT:    [[TMP5429:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5428]] acq_rel, align 8
24691 // CHECK-NEXT:    store double [[TMP5429]], ptr [[DV]], align 8
24692 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24693 // CHECK-NEXT:    [[TMP5430:%.*]] = load double, ptr [[DE]], align 8
24694 // CHECK-NEXT:    [[TMP5431:%.*]] = load double, ptr [[DD]], align 8
24695 // CHECK-NEXT:    [[TMP5432:%.*]] = bitcast double [[TMP5430]] to i64
24696 // CHECK-NEXT:    [[TMP5433:%.*]] = bitcast double [[TMP5431]] to i64
24697 // CHECK-NEXT:    [[TMP5434:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5432]], i64 [[TMP5433]] acq_rel acquire, align 8
24698 // CHECK-NEXT:    [[TMP5435:%.*]] = extractvalue { i64, i1 } [[TMP5434]], 0
24699 // CHECK-NEXT:    [[TMP5436:%.*]] = bitcast i64 [[TMP5435]] to double
24700 // CHECK-NEXT:    store double [[TMP5436]], ptr [[DV]], align 8
24701 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24702 // CHECK-NEXT:    [[TMP5437:%.*]] = load double, ptr [[DE]], align 8
24703 // CHECK-NEXT:    [[TMP5438:%.*]] = load double, ptr [[DD]], align 8
24704 // CHECK-NEXT:    [[TMP5439:%.*]] = bitcast double [[TMP5437]] to i64
24705 // CHECK-NEXT:    [[TMP5440:%.*]] = bitcast double [[TMP5438]] to i64
24706 // CHECK-NEXT:    [[TMP5441:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5439]], i64 [[TMP5440]] acq_rel acquire, align 8
24707 // CHECK-NEXT:    [[TMP5442:%.*]] = extractvalue { i64, i1 } [[TMP5441]], 0
24708 // CHECK-NEXT:    [[TMP5443:%.*]] = bitcast i64 [[TMP5442]] to double
24709 // CHECK-NEXT:    store double [[TMP5443]], ptr [[DV]], align 8
24710 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24711 // CHECK-NEXT:    [[TMP5444:%.*]] = load double, ptr [[DE]], align 8
24712 // CHECK-NEXT:    [[TMP5445:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5444]] acq_rel, align 8
24713 // CHECK-NEXT:    [[TMP5446:%.*]] = fcmp ogt double [[TMP5445]], [[TMP5444]]
24714 // CHECK-NEXT:    [[TMP5447:%.*]] = select i1 [[TMP5446]], double [[TMP5444]], double [[TMP5445]]
24715 // CHECK-NEXT:    store double [[TMP5447]], ptr [[DV]], align 8
24716 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24717 // CHECK-NEXT:    [[TMP5448:%.*]] = load double, ptr [[DE]], align 8
24718 // CHECK-NEXT:    [[TMP5449:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5448]] acq_rel, align 8
24719 // CHECK-NEXT:    [[TMP5450:%.*]] = fcmp olt double [[TMP5449]], [[TMP5448]]
24720 // CHECK-NEXT:    [[TMP5451:%.*]] = select i1 [[TMP5450]], double [[TMP5448]], double [[TMP5449]]
24721 // CHECK-NEXT:    store double [[TMP5451]], ptr [[DV]], align 8
24722 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24723 // CHECK-NEXT:    [[TMP5452:%.*]] = load double, ptr [[DE]], align 8
24724 // CHECK-NEXT:    [[TMP5453:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5452]] acq_rel, align 8
24725 // CHECK-NEXT:    [[TMP5454:%.*]] = fcmp olt double [[TMP5453]], [[TMP5452]]
24726 // CHECK-NEXT:    [[TMP5455:%.*]] = select i1 [[TMP5454]], double [[TMP5452]], double [[TMP5453]]
24727 // CHECK-NEXT:    store double [[TMP5455]], ptr [[DV]], align 8
24728 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24729 // CHECK-NEXT:    [[TMP5456:%.*]] = load double, ptr [[DE]], align 8
24730 // CHECK-NEXT:    [[TMP5457:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5456]] acq_rel, align 8
24731 // CHECK-NEXT:    [[TMP5458:%.*]] = fcmp ogt double [[TMP5457]], [[TMP5456]]
24732 // CHECK-NEXT:    [[TMP5459:%.*]] = select i1 [[TMP5458]], double [[TMP5456]], double [[TMP5457]]
24733 // CHECK-NEXT:    store double [[TMP5459]], ptr [[DV]], align 8
24734 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24735 // CHECK-NEXT:    [[TMP5460:%.*]] = load double, ptr [[DE]], align 8
24736 // CHECK-NEXT:    [[TMP5461:%.*]] = load double, ptr [[DD]], align 8
24737 // CHECK-NEXT:    [[TMP5462:%.*]] = bitcast double [[TMP5460]] to i64
24738 // CHECK-NEXT:    [[TMP5463:%.*]] = bitcast double [[TMP5461]] to i64
24739 // CHECK-NEXT:    [[TMP5464:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5462]], i64 [[TMP5463]] acq_rel acquire, align 8
24740 // CHECK-NEXT:    [[TMP5465:%.*]] = extractvalue { i64, i1 } [[TMP5464]], 0
24741 // CHECK-NEXT:    [[TMP5466:%.*]] = bitcast i64 [[TMP5465]] to double
24742 // CHECK-NEXT:    [[TMP5467:%.*]] = extractvalue { i64, i1 } [[TMP5464]], 1
24743 // CHECK-NEXT:    [[TMP5468:%.*]] = select i1 [[TMP5467]], double [[TMP5460]], double [[TMP5466]]
24744 // CHECK-NEXT:    store double [[TMP5468]], ptr [[DV]], align 8
24745 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24746 // CHECK-NEXT:    [[TMP5469:%.*]] = load double, ptr [[DE]], align 8
24747 // CHECK-NEXT:    [[TMP5470:%.*]] = load double, ptr [[DD]], align 8
24748 // CHECK-NEXT:    [[TMP5471:%.*]] = bitcast double [[TMP5469]] to i64
24749 // CHECK-NEXT:    [[TMP5472:%.*]] = bitcast double [[TMP5470]] to i64
24750 // CHECK-NEXT:    [[TMP5473:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5471]], i64 [[TMP5472]] acq_rel acquire, align 8
24751 // CHECK-NEXT:    [[TMP5474:%.*]] = extractvalue { i64, i1 } [[TMP5473]], 0
24752 // CHECK-NEXT:    [[TMP5475:%.*]] = bitcast i64 [[TMP5474]] to double
24753 // CHECK-NEXT:    [[TMP5476:%.*]] = extractvalue { i64, i1 } [[TMP5473]], 1
24754 // CHECK-NEXT:    [[TMP5477:%.*]] = select i1 [[TMP5476]], double [[TMP5469]], double [[TMP5475]]
24755 // CHECK-NEXT:    store double [[TMP5477]], ptr [[DV]], align 8
24756 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24757 // CHECK-NEXT:    [[TMP5478:%.*]] = load double, ptr [[DE]], align 8
24758 // CHECK-NEXT:    [[TMP5479:%.*]] = load double, ptr [[DD]], align 8
24759 // CHECK-NEXT:    [[TMP5480:%.*]] = bitcast double [[TMP5478]] to i64
24760 // CHECK-NEXT:    [[TMP5481:%.*]] = bitcast double [[TMP5479]] to i64
24761 // CHECK-NEXT:    [[TMP5482:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5480]], i64 [[TMP5481]] acq_rel acquire, align 8
24762 // CHECK-NEXT:    [[TMP5483:%.*]] = extractvalue { i64, i1 } [[TMP5482]], 0
24763 // CHECK-NEXT:    [[TMP5484:%.*]] = bitcast i64 [[TMP5483]] to double
24764 // CHECK-NEXT:    [[TMP5485:%.*]] = extractvalue { i64, i1 } [[TMP5482]], 1
24765 // CHECK-NEXT:    br i1 [[TMP5485]], label [[DX_ATOMIC_EXIT513:%.*]], label [[DX_ATOMIC_CONT514:%.*]]
24766 // CHECK:       dx.atomic.cont514:
24767 // CHECK-NEXT:    store double [[TMP5484]], ptr [[DV]], align 8
24768 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT513]]
24769 // CHECK:       dx.atomic.exit513:
24770 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24771 // CHECK-NEXT:    [[TMP5486:%.*]] = load double, ptr [[DE]], align 8
24772 // CHECK-NEXT:    [[TMP5487:%.*]] = load double, ptr [[DD]], align 8
24773 // CHECK-NEXT:    [[TMP5488:%.*]] = bitcast double [[TMP5486]] to i64
24774 // CHECK-NEXT:    [[TMP5489:%.*]] = bitcast double [[TMP5487]] to i64
24775 // CHECK-NEXT:    [[TMP5490:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5488]], i64 [[TMP5489]] acq_rel acquire, align 8
24776 // CHECK-NEXT:    [[TMP5491:%.*]] = extractvalue { i64, i1 } [[TMP5490]], 0
24777 // CHECK-NEXT:    [[TMP5492:%.*]] = bitcast i64 [[TMP5491]] to double
24778 // CHECK-NEXT:    [[TMP5493:%.*]] = extractvalue { i64, i1 } [[TMP5490]], 1
24779 // CHECK-NEXT:    br i1 [[TMP5493]], label [[DX_ATOMIC_EXIT515:%.*]], label [[DX_ATOMIC_CONT516:%.*]]
24780 // CHECK:       dx.atomic.cont516:
24781 // CHECK-NEXT:    store double [[TMP5492]], ptr [[DV]], align 8
24782 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT515]]
24783 // CHECK:       dx.atomic.exit515:
24784 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24785 // CHECK-NEXT:    [[TMP5494:%.*]] = load double, ptr [[DE]], align 8
24786 // CHECK-NEXT:    [[TMP5495:%.*]] = load double, ptr [[DD]], align 8
24787 // CHECK-NEXT:    [[TMP5496:%.*]] = bitcast double [[TMP5494]] to i64
24788 // CHECK-NEXT:    [[TMP5497:%.*]] = bitcast double [[TMP5495]] to i64
24789 // CHECK-NEXT:    [[TMP5498:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5496]], i64 [[TMP5497]] acq_rel acquire, align 8
24790 // CHECK-NEXT:    [[TMP5499:%.*]] = extractvalue { i64, i1 } [[TMP5498]], 1
24791 // CHECK-NEXT:    [[TMP5500:%.*]] = sext i1 [[TMP5499]] to i32
24792 // CHECK-NEXT:    store i32 [[TMP5500]], ptr [[IR]], align 4
24793 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24794 // CHECK-NEXT:    [[TMP5501:%.*]] = load double, ptr [[DE]], align 8
24795 // CHECK-NEXT:    [[TMP5502:%.*]] = load double, ptr [[DD]], align 8
24796 // CHECK-NEXT:    [[TMP5503:%.*]] = bitcast double [[TMP5501]] to i64
24797 // CHECK-NEXT:    [[TMP5504:%.*]] = bitcast double [[TMP5502]] to i64
24798 // CHECK-NEXT:    [[TMP5505:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5503]], i64 [[TMP5504]] acq_rel acquire, align 8
24799 // CHECK-NEXT:    [[TMP5506:%.*]] = extractvalue { i64, i1 } [[TMP5505]], 1
24800 // CHECK-NEXT:    [[TMP5507:%.*]] = sext i1 [[TMP5506]] to i32
24801 // CHECK-NEXT:    store i32 [[TMP5507]], ptr [[IR]], align 4
24802 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24803 // CHECK-NEXT:    [[TMP5508:%.*]] = load double, ptr [[DE]], align 8
24804 // CHECK-NEXT:    [[TMP5509:%.*]] = load double, ptr [[DD]], align 8
24805 // CHECK-NEXT:    [[TMP5510:%.*]] = bitcast double [[TMP5508]] to i64
24806 // CHECK-NEXT:    [[TMP5511:%.*]] = bitcast double [[TMP5509]] to i64
24807 // CHECK-NEXT:    [[TMP5512:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5510]], i64 [[TMP5511]] acq_rel acquire, align 8
24808 // CHECK-NEXT:    [[TMP5513:%.*]] = extractvalue { i64, i1 } [[TMP5512]], 0
24809 // CHECK-NEXT:    [[TMP5514:%.*]] = bitcast i64 [[TMP5513]] to double
24810 // CHECK-NEXT:    [[TMP5515:%.*]] = extractvalue { i64, i1 } [[TMP5512]], 1
24811 // CHECK-NEXT:    br i1 [[TMP5515]], label [[DX_ATOMIC_EXIT517:%.*]], label [[DX_ATOMIC_CONT518:%.*]]
24812 // CHECK:       dx.atomic.cont518:
24813 // CHECK-NEXT:    store double [[TMP5514]], ptr [[DV]], align 8
24814 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT517]]
24815 // CHECK:       dx.atomic.exit517:
24816 // CHECK-NEXT:    [[TMP5516:%.*]] = extractvalue { i64, i1 } [[TMP5512]], 1
24817 // CHECK-NEXT:    [[TMP5517:%.*]] = sext i1 [[TMP5516]] to i32
24818 // CHECK-NEXT:    store i32 [[TMP5517]], ptr [[IR]], align 4
24819 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24820 // CHECK-NEXT:    [[TMP5518:%.*]] = load double, ptr [[DE]], align 8
24821 // CHECK-NEXT:    [[TMP5519:%.*]] = load double, ptr [[DD]], align 8
24822 // CHECK-NEXT:    [[TMP5520:%.*]] = bitcast double [[TMP5518]] to i64
24823 // CHECK-NEXT:    [[TMP5521:%.*]] = bitcast double [[TMP5519]] to i64
24824 // CHECK-NEXT:    [[TMP5522:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5520]], i64 [[TMP5521]] acq_rel acquire, align 8
24825 // CHECK-NEXT:    [[TMP5523:%.*]] = extractvalue { i64, i1 } [[TMP5522]], 0
24826 // CHECK-NEXT:    [[TMP5524:%.*]] = bitcast i64 [[TMP5523]] to double
24827 // CHECK-NEXT:    [[TMP5525:%.*]] = extractvalue { i64, i1 } [[TMP5522]], 1
24828 // CHECK-NEXT:    br i1 [[TMP5525]], label [[DX_ATOMIC_EXIT519:%.*]], label [[DX_ATOMIC_CONT520:%.*]]
24829 // CHECK:       dx.atomic.cont520:
24830 // CHECK-NEXT:    store double [[TMP5524]], ptr [[DV]], align 8
24831 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT519]]
24832 // CHECK:       dx.atomic.exit519:
24833 // CHECK-NEXT:    [[TMP5526:%.*]] = extractvalue { i64, i1 } [[TMP5522]], 1
24834 // CHECK-NEXT:    [[TMP5527:%.*]] = sext i1 [[TMP5526]] to i32
24835 // CHECK-NEXT:    store i32 [[TMP5527]], ptr [[IR]], align 4
24836 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
24837 // CHECK-NEXT:    [[TMP5528:%.*]] = load double, ptr [[DE]], align 8
24838 // CHECK-NEXT:    [[TMP5529:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5528]] acquire, align 8
24839 // CHECK-NEXT:    store double [[TMP5529]], ptr [[DV]], align 8
24840 // CHECK-NEXT:    [[TMP5530:%.*]] = load double, ptr [[DE]], align 8
24841 // CHECK-NEXT:    [[TMP5531:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5530]] acquire, align 8
24842 // CHECK-NEXT:    store double [[TMP5531]], ptr [[DV]], align 8
24843 // CHECK-NEXT:    [[TMP5532:%.*]] = load double, ptr [[DE]], align 8
24844 // CHECK-NEXT:    [[TMP5533:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5532]] acquire, align 8
24845 // CHECK-NEXT:    store double [[TMP5533]], ptr [[DV]], align 8
24846 // CHECK-NEXT:    [[TMP5534:%.*]] = load double, ptr [[DE]], align 8
24847 // CHECK-NEXT:    [[TMP5535:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5534]] acquire, align 8
24848 // CHECK-NEXT:    store double [[TMP5535]], ptr [[DV]], align 8
24849 // CHECK-NEXT:    [[TMP5536:%.*]] = load double, ptr [[DE]], align 8
24850 // CHECK-NEXT:    [[TMP5537:%.*]] = load double, ptr [[DD]], align 8
24851 // CHECK-NEXT:    [[TMP5538:%.*]] = bitcast double [[TMP5536]] to i64
24852 // CHECK-NEXT:    [[TMP5539:%.*]] = bitcast double [[TMP5537]] to i64
24853 // CHECK-NEXT:    [[TMP5540:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5538]], i64 [[TMP5539]] acquire acquire, align 8
24854 // CHECK-NEXT:    [[TMP5541:%.*]] = extractvalue { i64, i1 } [[TMP5540]], 0
24855 // CHECK-NEXT:    [[TMP5542:%.*]] = bitcast i64 [[TMP5541]] to double
24856 // CHECK-NEXT:    store double [[TMP5542]], ptr [[DV]], align 8
24857 // CHECK-NEXT:    [[TMP5543:%.*]] = load double, ptr [[DE]], align 8
24858 // CHECK-NEXT:    [[TMP5544:%.*]] = load double, ptr [[DD]], align 8
24859 // CHECK-NEXT:    [[TMP5545:%.*]] = bitcast double [[TMP5543]] to i64
24860 // CHECK-NEXT:    [[TMP5546:%.*]] = bitcast double [[TMP5544]] to i64
24861 // CHECK-NEXT:    [[TMP5547:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5545]], i64 [[TMP5546]] acquire acquire, align 8
24862 // CHECK-NEXT:    [[TMP5548:%.*]] = extractvalue { i64, i1 } [[TMP5547]], 0
24863 // CHECK-NEXT:    [[TMP5549:%.*]] = bitcast i64 [[TMP5548]] to double
24864 // CHECK-NEXT:    store double [[TMP5549]], ptr [[DV]], align 8
24865 // CHECK-NEXT:    [[TMP5550:%.*]] = load double, ptr [[DE]], align 8
24866 // CHECK-NEXT:    [[TMP5551:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5550]] acquire, align 8
24867 // CHECK-NEXT:    [[TMP5552:%.*]] = fcmp ogt double [[TMP5551]], [[TMP5550]]
24868 // CHECK-NEXT:    [[TMP5553:%.*]] = select i1 [[TMP5552]], double [[TMP5550]], double [[TMP5551]]
24869 // CHECK-NEXT:    store double [[TMP5553]], ptr [[DV]], align 8
24870 // CHECK-NEXT:    [[TMP5554:%.*]] = load double, ptr [[DE]], align 8
24871 // CHECK-NEXT:    [[TMP5555:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5554]] acquire, align 8
24872 // CHECK-NEXT:    [[TMP5556:%.*]] = fcmp olt double [[TMP5555]], [[TMP5554]]
24873 // CHECK-NEXT:    [[TMP5557:%.*]] = select i1 [[TMP5556]], double [[TMP5554]], double [[TMP5555]]
24874 // CHECK-NEXT:    store double [[TMP5557]], ptr [[DV]], align 8
24875 // CHECK-NEXT:    [[TMP5558:%.*]] = load double, ptr [[DE]], align 8
24876 // CHECK-NEXT:    [[TMP5559:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5558]] acquire, align 8
24877 // CHECK-NEXT:    [[TMP5560:%.*]] = fcmp olt double [[TMP5559]], [[TMP5558]]
24878 // CHECK-NEXT:    [[TMP5561:%.*]] = select i1 [[TMP5560]], double [[TMP5558]], double [[TMP5559]]
24879 // CHECK-NEXT:    store double [[TMP5561]], ptr [[DV]], align 8
24880 // CHECK-NEXT:    [[TMP5562:%.*]] = load double, ptr [[DE]], align 8
24881 // CHECK-NEXT:    [[TMP5563:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5562]] acquire, align 8
24882 // CHECK-NEXT:    [[TMP5564:%.*]] = fcmp ogt double [[TMP5563]], [[TMP5562]]
24883 // CHECK-NEXT:    [[TMP5565:%.*]] = select i1 [[TMP5564]], double [[TMP5562]], double [[TMP5563]]
24884 // CHECK-NEXT:    store double [[TMP5565]], ptr [[DV]], align 8
24885 // CHECK-NEXT:    [[TMP5566:%.*]] = load double, ptr [[DE]], align 8
24886 // CHECK-NEXT:    [[TMP5567:%.*]] = load double, ptr [[DD]], align 8
24887 // CHECK-NEXT:    [[TMP5568:%.*]] = bitcast double [[TMP5566]] to i64
24888 // CHECK-NEXT:    [[TMP5569:%.*]] = bitcast double [[TMP5567]] to i64
24889 // CHECK-NEXT:    [[TMP5570:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5568]], i64 [[TMP5569]] acquire acquire, align 8
24890 // CHECK-NEXT:    [[TMP5571:%.*]] = extractvalue { i64, i1 } [[TMP5570]], 0
24891 // CHECK-NEXT:    [[TMP5572:%.*]] = bitcast i64 [[TMP5571]] to double
24892 // CHECK-NEXT:    [[TMP5573:%.*]] = extractvalue { i64, i1 } [[TMP5570]], 1
24893 // CHECK-NEXT:    [[TMP5574:%.*]] = select i1 [[TMP5573]], double [[TMP5566]], double [[TMP5572]]
24894 // CHECK-NEXT:    store double [[TMP5574]], ptr [[DV]], align 8
24895 // CHECK-NEXT:    [[TMP5575:%.*]] = load double, ptr [[DE]], align 8
24896 // CHECK-NEXT:    [[TMP5576:%.*]] = load double, ptr [[DD]], align 8
24897 // CHECK-NEXT:    [[TMP5577:%.*]] = bitcast double [[TMP5575]] to i64
24898 // CHECK-NEXT:    [[TMP5578:%.*]] = bitcast double [[TMP5576]] to i64
24899 // CHECK-NEXT:    [[TMP5579:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5577]], i64 [[TMP5578]] acquire acquire, align 8
24900 // CHECK-NEXT:    [[TMP5580:%.*]] = extractvalue { i64, i1 } [[TMP5579]], 0
24901 // CHECK-NEXT:    [[TMP5581:%.*]] = bitcast i64 [[TMP5580]] to double
24902 // CHECK-NEXT:    [[TMP5582:%.*]] = extractvalue { i64, i1 } [[TMP5579]], 1
24903 // CHECK-NEXT:    [[TMP5583:%.*]] = select i1 [[TMP5582]], double [[TMP5575]], double [[TMP5581]]
24904 // CHECK-NEXT:    store double [[TMP5583]], ptr [[DV]], align 8
24905 // CHECK-NEXT:    [[TMP5584:%.*]] = load double, ptr [[DE]], align 8
24906 // CHECK-NEXT:    [[TMP5585:%.*]] = load double, ptr [[DD]], align 8
24907 // CHECK-NEXT:    [[TMP5586:%.*]] = bitcast double [[TMP5584]] to i64
24908 // CHECK-NEXT:    [[TMP5587:%.*]] = bitcast double [[TMP5585]] to i64
24909 // CHECK-NEXT:    [[TMP5588:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5586]], i64 [[TMP5587]] acquire acquire, align 8
24910 // CHECK-NEXT:    [[TMP5589:%.*]] = extractvalue { i64, i1 } [[TMP5588]], 0
24911 // CHECK-NEXT:    [[TMP5590:%.*]] = bitcast i64 [[TMP5589]] to double
24912 // CHECK-NEXT:    [[TMP5591:%.*]] = extractvalue { i64, i1 } [[TMP5588]], 1
24913 // CHECK-NEXT:    br i1 [[TMP5591]], label [[DX_ATOMIC_EXIT521:%.*]], label [[DX_ATOMIC_CONT522:%.*]]
24914 // CHECK:       dx.atomic.cont522:
24915 // CHECK-NEXT:    store double [[TMP5590]], ptr [[DV]], align 8
24916 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT521]]
24917 // CHECK:       dx.atomic.exit521:
24918 // CHECK-NEXT:    [[TMP5592:%.*]] = load double, ptr [[DE]], align 8
24919 // CHECK-NEXT:    [[TMP5593:%.*]] = load double, ptr [[DD]], align 8
24920 // CHECK-NEXT:    [[TMP5594:%.*]] = bitcast double [[TMP5592]] to i64
24921 // CHECK-NEXT:    [[TMP5595:%.*]] = bitcast double [[TMP5593]] to i64
24922 // CHECK-NEXT:    [[TMP5596:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5594]], i64 [[TMP5595]] acquire acquire, align 8
24923 // CHECK-NEXT:    [[TMP5597:%.*]] = extractvalue { i64, i1 } [[TMP5596]], 0
24924 // CHECK-NEXT:    [[TMP5598:%.*]] = bitcast i64 [[TMP5597]] to double
24925 // CHECK-NEXT:    [[TMP5599:%.*]] = extractvalue { i64, i1 } [[TMP5596]], 1
24926 // CHECK-NEXT:    br i1 [[TMP5599]], label [[DX_ATOMIC_EXIT523:%.*]], label [[DX_ATOMIC_CONT524:%.*]]
24927 // CHECK:       dx.atomic.cont524:
24928 // CHECK-NEXT:    store double [[TMP5598]], ptr [[DV]], align 8
24929 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT523]]
24930 // CHECK:       dx.atomic.exit523:
24931 // CHECK-NEXT:    [[TMP5600:%.*]] = load double, ptr [[DE]], align 8
24932 // CHECK-NEXT:    [[TMP5601:%.*]] = load double, ptr [[DD]], align 8
24933 // CHECK-NEXT:    [[TMP5602:%.*]] = bitcast double [[TMP5600]] to i64
24934 // CHECK-NEXT:    [[TMP5603:%.*]] = bitcast double [[TMP5601]] to i64
24935 // CHECK-NEXT:    [[TMP5604:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5602]], i64 [[TMP5603]] acquire acquire, align 8
24936 // CHECK-NEXT:    [[TMP5605:%.*]] = extractvalue { i64, i1 } [[TMP5604]], 1
24937 // CHECK-NEXT:    [[TMP5606:%.*]] = sext i1 [[TMP5605]] to i32
24938 // CHECK-NEXT:    store i32 [[TMP5606]], ptr [[IR]], align 4
24939 // CHECK-NEXT:    [[TMP5607:%.*]] = load double, ptr [[DE]], align 8
24940 // CHECK-NEXT:    [[TMP5608:%.*]] = load double, ptr [[DD]], align 8
24941 // CHECK-NEXT:    [[TMP5609:%.*]] = bitcast double [[TMP5607]] to i64
24942 // CHECK-NEXT:    [[TMP5610:%.*]] = bitcast double [[TMP5608]] to i64
24943 // CHECK-NEXT:    [[TMP5611:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5609]], i64 [[TMP5610]] acquire acquire, align 8
24944 // CHECK-NEXT:    [[TMP5612:%.*]] = extractvalue { i64, i1 } [[TMP5611]], 1
24945 // CHECK-NEXT:    [[TMP5613:%.*]] = sext i1 [[TMP5612]] to i32
24946 // CHECK-NEXT:    store i32 [[TMP5613]], ptr [[IR]], align 4
24947 // CHECK-NEXT:    [[TMP5614:%.*]] = load double, ptr [[DE]], align 8
24948 // CHECK-NEXT:    [[TMP5615:%.*]] = load double, ptr [[DD]], align 8
24949 // CHECK-NEXT:    [[TMP5616:%.*]] = bitcast double [[TMP5614]] to i64
24950 // CHECK-NEXT:    [[TMP5617:%.*]] = bitcast double [[TMP5615]] to i64
24951 // CHECK-NEXT:    [[TMP5618:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5616]], i64 [[TMP5617]] acquire acquire, align 8
24952 // CHECK-NEXT:    [[TMP5619:%.*]] = extractvalue { i64, i1 } [[TMP5618]], 0
24953 // CHECK-NEXT:    [[TMP5620:%.*]] = bitcast i64 [[TMP5619]] to double
24954 // CHECK-NEXT:    [[TMP5621:%.*]] = extractvalue { i64, i1 } [[TMP5618]], 1
24955 // CHECK-NEXT:    br i1 [[TMP5621]], label [[DX_ATOMIC_EXIT525:%.*]], label [[DX_ATOMIC_CONT526:%.*]]
24956 // CHECK:       dx.atomic.cont526:
24957 // CHECK-NEXT:    store double [[TMP5620]], ptr [[DV]], align 8
24958 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT525]]
24959 // CHECK:       dx.atomic.exit525:
24960 // CHECK-NEXT:    [[TMP5622:%.*]] = extractvalue { i64, i1 } [[TMP5618]], 1
24961 // CHECK-NEXT:    [[TMP5623:%.*]] = sext i1 [[TMP5622]] to i32
24962 // CHECK-NEXT:    store i32 [[TMP5623]], ptr [[IR]], align 4
24963 // CHECK-NEXT:    [[TMP5624:%.*]] = load double, ptr [[DE]], align 8
24964 // CHECK-NEXT:    [[TMP5625:%.*]] = load double, ptr [[DD]], align 8
24965 // CHECK-NEXT:    [[TMP5626:%.*]] = bitcast double [[TMP5624]] to i64
24966 // CHECK-NEXT:    [[TMP5627:%.*]] = bitcast double [[TMP5625]] to i64
24967 // CHECK-NEXT:    [[TMP5628:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5626]], i64 [[TMP5627]] acquire acquire, align 8
24968 // CHECK-NEXT:    [[TMP5629:%.*]] = extractvalue { i64, i1 } [[TMP5628]], 0
24969 // CHECK-NEXT:    [[TMP5630:%.*]] = bitcast i64 [[TMP5629]] to double
24970 // CHECK-NEXT:    [[TMP5631:%.*]] = extractvalue { i64, i1 } [[TMP5628]], 1
24971 // CHECK-NEXT:    br i1 [[TMP5631]], label [[DX_ATOMIC_EXIT527:%.*]], label [[DX_ATOMIC_CONT528:%.*]]
24972 // CHECK:       dx.atomic.cont528:
24973 // CHECK-NEXT:    store double [[TMP5630]], ptr [[DV]], align 8
24974 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT527]]
24975 // CHECK:       dx.atomic.exit527:
24976 // CHECK-NEXT:    [[TMP5632:%.*]] = extractvalue { i64, i1 } [[TMP5628]], 1
24977 // CHECK-NEXT:    [[TMP5633:%.*]] = sext i1 [[TMP5632]] to i32
24978 // CHECK-NEXT:    store i32 [[TMP5633]], ptr [[IR]], align 4
24979 // CHECK-NEXT:    [[TMP5634:%.*]] = load double, ptr [[DE]], align 8
24980 // CHECK-NEXT:    [[TMP5635:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5634]] monotonic, align 8
24981 // CHECK-NEXT:    store double [[TMP5635]], ptr [[DV]], align 8
24982 // CHECK-NEXT:    [[TMP5636:%.*]] = load double, ptr [[DE]], align 8
24983 // CHECK-NEXT:    [[TMP5637:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5636]] monotonic, align 8
24984 // CHECK-NEXT:    store double [[TMP5637]], ptr [[DV]], align 8
24985 // CHECK-NEXT:    [[TMP5638:%.*]] = load double, ptr [[DE]], align 8
24986 // CHECK-NEXT:    [[TMP5639:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5638]] monotonic, align 8
24987 // CHECK-NEXT:    store double [[TMP5639]], ptr [[DV]], align 8
24988 // CHECK-NEXT:    [[TMP5640:%.*]] = load double, ptr [[DE]], align 8
24989 // CHECK-NEXT:    [[TMP5641:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5640]] monotonic, align 8
24990 // CHECK-NEXT:    store double [[TMP5641]], ptr [[DV]], align 8
24991 // CHECK-NEXT:    [[TMP5642:%.*]] = load double, ptr [[DE]], align 8
24992 // CHECK-NEXT:    [[TMP5643:%.*]] = load double, ptr [[DD]], align 8
24993 // CHECK-NEXT:    [[TMP5644:%.*]] = bitcast double [[TMP5642]] to i64
24994 // CHECK-NEXT:    [[TMP5645:%.*]] = bitcast double [[TMP5643]] to i64
24995 // CHECK-NEXT:    [[TMP5646:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5644]], i64 [[TMP5645]] monotonic monotonic, align 8
24996 // CHECK-NEXT:    [[TMP5647:%.*]] = extractvalue { i64, i1 } [[TMP5646]], 0
24997 // CHECK-NEXT:    [[TMP5648:%.*]] = bitcast i64 [[TMP5647]] to double
24998 // CHECK-NEXT:    store double [[TMP5648]], ptr [[DV]], align 8
24999 // CHECK-NEXT:    [[TMP5649:%.*]] = load double, ptr [[DE]], align 8
25000 // CHECK-NEXT:    [[TMP5650:%.*]] = load double, ptr [[DD]], align 8
25001 // CHECK-NEXT:    [[TMP5651:%.*]] = bitcast double [[TMP5649]] to i64
25002 // CHECK-NEXT:    [[TMP5652:%.*]] = bitcast double [[TMP5650]] to i64
25003 // CHECK-NEXT:    [[TMP5653:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5651]], i64 [[TMP5652]] monotonic monotonic, align 8
25004 // CHECK-NEXT:    [[TMP5654:%.*]] = extractvalue { i64, i1 } [[TMP5653]], 0
25005 // CHECK-NEXT:    [[TMP5655:%.*]] = bitcast i64 [[TMP5654]] to double
25006 // CHECK-NEXT:    store double [[TMP5655]], ptr [[DV]], align 8
25007 // CHECK-NEXT:    [[TMP5656:%.*]] = load double, ptr [[DE]], align 8
25008 // CHECK-NEXT:    [[TMP5657:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5656]] monotonic, align 8
25009 // CHECK-NEXT:    [[TMP5658:%.*]] = fcmp ogt double [[TMP5657]], [[TMP5656]]
25010 // CHECK-NEXT:    [[TMP5659:%.*]] = select i1 [[TMP5658]], double [[TMP5656]], double [[TMP5657]]
25011 // CHECK-NEXT:    store double [[TMP5659]], ptr [[DV]], align 8
25012 // CHECK-NEXT:    [[TMP5660:%.*]] = load double, ptr [[DE]], align 8
25013 // CHECK-NEXT:    [[TMP5661:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5660]] monotonic, align 8
25014 // CHECK-NEXT:    [[TMP5662:%.*]] = fcmp olt double [[TMP5661]], [[TMP5660]]
25015 // CHECK-NEXT:    [[TMP5663:%.*]] = select i1 [[TMP5662]], double [[TMP5660]], double [[TMP5661]]
25016 // CHECK-NEXT:    store double [[TMP5663]], ptr [[DV]], align 8
25017 // CHECK-NEXT:    [[TMP5664:%.*]] = load double, ptr [[DE]], align 8
25018 // CHECK-NEXT:    [[TMP5665:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5664]] monotonic, align 8
25019 // CHECK-NEXT:    [[TMP5666:%.*]] = fcmp olt double [[TMP5665]], [[TMP5664]]
25020 // CHECK-NEXT:    [[TMP5667:%.*]] = select i1 [[TMP5666]], double [[TMP5664]], double [[TMP5665]]
25021 // CHECK-NEXT:    store double [[TMP5667]], ptr [[DV]], align 8
25022 // CHECK-NEXT:    [[TMP5668:%.*]] = load double, ptr [[DE]], align 8
25023 // CHECK-NEXT:    [[TMP5669:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5668]] monotonic, align 8
25024 // CHECK-NEXT:    [[TMP5670:%.*]] = fcmp ogt double [[TMP5669]], [[TMP5668]]
25025 // CHECK-NEXT:    [[TMP5671:%.*]] = select i1 [[TMP5670]], double [[TMP5668]], double [[TMP5669]]
25026 // CHECK-NEXT:    store double [[TMP5671]], ptr [[DV]], align 8
25027 // CHECK-NEXT:    [[TMP5672:%.*]] = load double, ptr [[DE]], align 8
25028 // CHECK-NEXT:    [[TMP5673:%.*]] = load double, ptr [[DD]], align 8
25029 // CHECK-NEXT:    [[TMP5674:%.*]] = bitcast double [[TMP5672]] to i64
25030 // CHECK-NEXT:    [[TMP5675:%.*]] = bitcast double [[TMP5673]] to i64
25031 // CHECK-NEXT:    [[TMP5676:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5674]], i64 [[TMP5675]] monotonic monotonic, align 8
25032 // CHECK-NEXT:    [[TMP5677:%.*]] = extractvalue { i64, i1 } [[TMP5676]], 0
25033 // CHECK-NEXT:    [[TMP5678:%.*]] = bitcast i64 [[TMP5677]] to double
25034 // CHECK-NEXT:    [[TMP5679:%.*]] = extractvalue { i64, i1 } [[TMP5676]], 1
25035 // CHECK-NEXT:    [[TMP5680:%.*]] = select i1 [[TMP5679]], double [[TMP5672]], double [[TMP5678]]
25036 // CHECK-NEXT:    store double [[TMP5680]], ptr [[DV]], align 8
25037 // CHECK-NEXT:    [[TMP5681:%.*]] = load double, ptr [[DE]], align 8
25038 // CHECK-NEXT:    [[TMP5682:%.*]] = load double, ptr [[DD]], align 8
25039 // CHECK-NEXT:    [[TMP5683:%.*]] = bitcast double [[TMP5681]] to i64
25040 // CHECK-NEXT:    [[TMP5684:%.*]] = bitcast double [[TMP5682]] to i64
25041 // CHECK-NEXT:    [[TMP5685:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5683]], i64 [[TMP5684]] monotonic monotonic, align 8
25042 // CHECK-NEXT:    [[TMP5686:%.*]] = extractvalue { i64, i1 } [[TMP5685]], 0
25043 // CHECK-NEXT:    [[TMP5687:%.*]] = bitcast i64 [[TMP5686]] to double
25044 // CHECK-NEXT:    [[TMP5688:%.*]] = extractvalue { i64, i1 } [[TMP5685]], 1
25045 // CHECK-NEXT:    [[TMP5689:%.*]] = select i1 [[TMP5688]], double [[TMP5681]], double [[TMP5687]]
25046 // CHECK-NEXT:    store double [[TMP5689]], ptr [[DV]], align 8
25047 // CHECK-NEXT:    [[TMP5690:%.*]] = load double, ptr [[DE]], align 8
25048 // CHECK-NEXT:    [[TMP5691:%.*]] = load double, ptr [[DD]], align 8
25049 // CHECK-NEXT:    [[TMP5692:%.*]] = bitcast double [[TMP5690]] to i64
25050 // CHECK-NEXT:    [[TMP5693:%.*]] = bitcast double [[TMP5691]] to i64
25051 // CHECK-NEXT:    [[TMP5694:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5692]], i64 [[TMP5693]] monotonic monotonic, align 8
25052 // CHECK-NEXT:    [[TMP5695:%.*]] = extractvalue { i64, i1 } [[TMP5694]], 0
25053 // CHECK-NEXT:    [[TMP5696:%.*]] = bitcast i64 [[TMP5695]] to double
25054 // CHECK-NEXT:    [[TMP5697:%.*]] = extractvalue { i64, i1 } [[TMP5694]], 1
25055 // CHECK-NEXT:    br i1 [[TMP5697]], label [[DX_ATOMIC_EXIT529:%.*]], label [[DX_ATOMIC_CONT530:%.*]]
25056 // CHECK:       dx.atomic.cont530:
25057 // CHECK-NEXT:    store double [[TMP5696]], ptr [[DV]], align 8
25058 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT529]]
25059 // CHECK:       dx.atomic.exit529:
25060 // CHECK-NEXT:    [[TMP5698:%.*]] = load double, ptr [[DE]], align 8
25061 // CHECK-NEXT:    [[TMP5699:%.*]] = load double, ptr [[DD]], align 8
25062 // CHECK-NEXT:    [[TMP5700:%.*]] = bitcast double [[TMP5698]] to i64
25063 // CHECK-NEXT:    [[TMP5701:%.*]] = bitcast double [[TMP5699]] to i64
25064 // CHECK-NEXT:    [[TMP5702:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5700]], i64 [[TMP5701]] monotonic monotonic, align 8
25065 // CHECK-NEXT:    [[TMP5703:%.*]] = extractvalue { i64, i1 } [[TMP5702]], 0
25066 // CHECK-NEXT:    [[TMP5704:%.*]] = bitcast i64 [[TMP5703]] to double
25067 // CHECK-NEXT:    [[TMP5705:%.*]] = extractvalue { i64, i1 } [[TMP5702]], 1
25068 // CHECK-NEXT:    br i1 [[TMP5705]], label [[DX_ATOMIC_EXIT531:%.*]], label [[DX_ATOMIC_CONT532:%.*]]
25069 // CHECK:       dx.atomic.cont532:
25070 // CHECK-NEXT:    store double [[TMP5704]], ptr [[DV]], align 8
25071 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT531]]
25072 // CHECK:       dx.atomic.exit531:
25073 // CHECK-NEXT:    [[TMP5706:%.*]] = load double, ptr [[DE]], align 8
25074 // CHECK-NEXT:    [[TMP5707:%.*]] = load double, ptr [[DD]], align 8
25075 // CHECK-NEXT:    [[TMP5708:%.*]] = bitcast double [[TMP5706]] to i64
25076 // CHECK-NEXT:    [[TMP5709:%.*]] = bitcast double [[TMP5707]] to i64
25077 // CHECK-NEXT:    [[TMP5710:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5708]], i64 [[TMP5709]] monotonic monotonic, align 8
25078 // CHECK-NEXT:    [[TMP5711:%.*]] = extractvalue { i64, i1 } [[TMP5710]], 1
25079 // CHECK-NEXT:    [[TMP5712:%.*]] = sext i1 [[TMP5711]] to i32
25080 // CHECK-NEXT:    store i32 [[TMP5712]], ptr [[IR]], align 4
25081 // CHECK-NEXT:    [[TMP5713:%.*]] = load double, ptr [[DE]], align 8
25082 // CHECK-NEXT:    [[TMP5714:%.*]] = load double, ptr [[DD]], align 8
25083 // CHECK-NEXT:    [[TMP5715:%.*]] = bitcast double [[TMP5713]] to i64
25084 // CHECK-NEXT:    [[TMP5716:%.*]] = bitcast double [[TMP5714]] to i64
25085 // CHECK-NEXT:    [[TMP5717:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5715]], i64 [[TMP5716]] monotonic monotonic, align 8
25086 // CHECK-NEXT:    [[TMP5718:%.*]] = extractvalue { i64, i1 } [[TMP5717]], 1
25087 // CHECK-NEXT:    [[TMP5719:%.*]] = sext i1 [[TMP5718]] to i32
25088 // CHECK-NEXT:    store i32 [[TMP5719]], ptr [[IR]], align 4
25089 // CHECK-NEXT:    [[TMP5720:%.*]] = load double, ptr [[DE]], align 8
25090 // CHECK-NEXT:    [[TMP5721:%.*]] = load double, ptr [[DD]], align 8
25091 // CHECK-NEXT:    [[TMP5722:%.*]] = bitcast double [[TMP5720]] to i64
25092 // CHECK-NEXT:    [[TMP5723:%.*]] = bitcast double [[TMP5721]] to i64
25093 // CHECK-NEXT:    [[TMP5724:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5722]], i64 [[TMP5723]] monotonic monotonic, align 8
25094 // CHECK-NEXT:    [[TMP5725:%.*]] = extractvalue { i64, i1 } [[TMP5724]], 0
25095 // CHECK-NEXT:    [[TMP5726:%.*]] = bitcast i64 [[TMP5725]] to double
25096 // CHECK-NEXT:    [[TMP5727:%.*]] = extractvalue { i64, i1 } [[TMP5724]], 1
25097 // CHECK-NEXT:    br i1 [[TMP5727]], label [[DX_ATOMIC_EXIT533:%.*]], label [[DX_ATOMIC_CONT534:%.*]]
25098 // CHECK:       dx.atomic.cont534:
25099 // CHECK-NEXT:    store double [[TMP5726]], ptr [[DV]], align 8
25100 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT533]]
25101 // CHECK:       dx.atomic.exit533:
25102 // CHECK-NEXT:    [[TMP5728:%.*]] = extractvalue { i64, i1 } [[TMP5724]], 1
25103 // CHECK-NEXT:    [[TMP5729:%.*]] = sext i1 [[TMP5728]] to i32
25104 // CHECK-NEXT:    store i32 [[TMP5729]], ptr [[IR]], align 4
25105 // CHECK-NEXT:    [[TMP5730:%.*]] = load double, ptr [[DE]], align 8
25106 // CHECK-NEXT:    [[TMP5731:%.*]] = load double, ptr [[DD]], align 8
25107 // CHECK-NEXT:    [[TMP5732:%.*]] = bitcast double [[TMP5730]] to i64
25108 // CHECK-NEXT:    [[TMP5733:%.*]] = bitcast double [[TMP5731]] to i64
25109 // CHECK-NEXT:    [[TMP5734:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5732]], i64 [[TMP5733]] monotonic monotonic, align 8
25110 // CHECK-NEXT:    [[TMP5735:%.*]] = extractvalue { i64, i1 } [[TMP5734]], 0
25111 // CHECK-NEXT:    [[TMP5736:%.*]] = bitcast i64 [[TMP5735]] to double
25112 // CHECK-NEXT:    [[TMP5737:%.*]] = extractvalue { i64, i1 } [[TMP5734]], 1
25113 // CHECK-NEXT:    br i1 [[TMP5737]], label [[DX_ATOMIC_EXIT535:%.*]], label [[DX_ATOMIC_CONT536:%.*]]
25114 // CHECK:       dx.atomic.cont536:
25115 // CHECK-NEXT:    store double [[TMP5736]], ptr [[DV]], align 8
25116 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT535]]
25117 // CHECK:       dx.atomic.exit535:
25118 // CHECK-NEXT:    [[TMP5738:%.*]] = extractvalue { i64, i1 } [[TMP5734]], 1
25119 // CHECK-NEXT:    [[TMP5739:%.*]] = sext i1 [[TMP5738]] to i32
25120 // CHECK-NEXT:    store i32 [[TMP5739]], ptr [[IR]], align 4
25121 // CHECK-NEXT:    [[TMP5740:%.*]] = load double, ptr [[DE]], align 8
25122 // CHECK-NEXT:    [[TMP5741:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5740]] release, align 8
25123 // CHECK-NEXT:    store double [[TMP5741]], ptr [[DV]], align 8
25124 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25125 // CHECK-NEXT:    [[TMP5742:%.*]] = load double, ptr [[DE]], align 8
25126 // CHECK-NEXT:    [[TMP5743:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5742]] release, align 8
25127 // CHECK-NEXT:    store double [[TMP5743]], ptr [[DV]], align 8
25128 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25129 // CHECK-NEXT:    [[TMP5744:%.*]] = load double, ptr [[DE]], align 8
25130 // CHECK-NEXT:    [[TMP5745:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5744]] release, align 8
25131 // CHECK-NEXT:    store double [[TMP5745]], ptr [[DV]], align 8
25132 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25133 // CHECK-NEXT:    [[TMP5746:%.*]] = load double, ptr [[DE]], align 8
25134 // CHECK-NEXT:    [[TMP5747:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5746]] release, align 8
25135 // CHECK-NEXT:    store double [[TMP5747]], ptr [[DV]], align 8
25136 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25137 // CHECK-NEXT:    [[TMP5748:%.*]] = load double, ptr [[DE]], align 8
25138 // CHECK-NEXT:    [[TMP5749:%.*]] = load double, ptr [[DD]], align 8
25139 // CHECK-NEXT:    [[TMP5750:%.*]] = bitcast double [[TMP5748]] to i64
25140 // CHECK-NEXT:    [[TMP5751:%.*]] = bitcast double [[TMP5749]] to i64
25141 // CHECK-NEXT:    [[TMP5752:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5750]], i64 [[TMP5751]] release monotonic, align 8
25142 // CHECK-NEXT:    [[TMP5753:%.*]] = extractvalue { i64, i1 } [[TMP5752]], 0
25143 // CHECK-NEXT:    [[TMP5754:%.*]] = bitcast i64 [[TMP5753]] to double
25144 // CHECK-NEXT:    store double [[TMP5754]], ptr [[DV]], align 8
25145 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25146 // CHECK-NEXT:    [[TMP5755:%.*]] = load double, ptr [[DE]], align 8
25147 // CHECK-NEXT:    [[TMP5756:%.*]] = load double, ptr [[DD]], align 8
25148 // CHECK-NEXT:    [[TMP5757:%.*]] = bitcast double [[TMP5755]] to i64
25149 // CHECK-NEXT:    [[TMP5758:%.*]] = bitcast double [[TMP5756]] to i64
25150 // CHECK-NEXT:    [[TMP5759:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5757]], i64 [[TMP5758]] release monotonic, align 8
25151 // CHECK-NEXT:    [[TMP5760:%.*]] = extractvalue { i64, i1 } [[TMP5759]], 0
25152 // CHECK-NEXT:    [[TMP5761:%.*]] = bitcast i64 [[TMP5760]] to double
25153 // CHECK-NEXT:    store double [[TMP5761]], ptr [[DV]], align 8
25154 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25155 // CHECK-NEXT:    [[TMP5762:%.*]] = load double, ptr [[DE]], align 8
25156 // CHECK-NEXT:    [[TMP5763:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5762]] release, align 8
25157 // CHECK-NEXT:    [[TMP5764:%.*]] = fcmp ogt double [[TMP5763]], [[TMP5762]]
25158 // CHECK-NEXT:    [[TMP5765:%.*]] = select i1 [[TMP5764]], double [[TMP5762]], double [[TMP5763]]
25159 // CHECK-NEXT:    store double [[TMP5765]], ptr [[DV]], align 8
25160 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25161 // CHECK-NEXT:    [[TMP5766:%.*]] = load double, ptr [[DE]], align 8
25162 // CHECK-NEXT:    [[TMP5767:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5766]] release, align 8
25163 // CHECK-NEXT:    [[TMP5768:%.*]] = fcmp olt double [[TMP5767]], [[TMP5766]]
25164 // CHECK-NEXT:    [[TMP5769:%.*]] = select i1 [[TMP5768]], double [[TMP5766]], double [[TMP5767]]
25165 // CHECK-NEXT:    store double [[TMP5769]], ptr [[DV]], align 8
25166 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25167 // CHECK-NEXT:    [[TMP5770:%.*]] = load double, ptr [[DE]], align 8
25168 // CHECK-NEXT:    [[TMP5771:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5770]] release, align 8
25169 // CHECK-NEXT:    [[TMP5772:%.*]] = fcmp olt double [[TMP5771]], [[TMP5770]]
25170 // CHECK-NEXT:    [[TMP5773:%.*]] = select i1 [[TMP5772]], double [[TMP5770]], double [[TMP5771]]
25171 // CHECK-NEXT:    store double [[TMP5773]], ptr [[DV]], align 8
25172 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25173 // CHECK-NEXT:    [[TMP5774:%.*]] = load double, ptr [[DE]], align 8
25174 // CHECK-NEXT:    [[TMP5775:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5774]] release, align 8
25175 // CHECK-NEXT:    [[TMP5776:%.*]] = fcmp ogt double [[TMP5775]], [[TMP5774]]
25176 // CHECK-NEXT:    [[TMP5777:%.*]] = select i1 [[TMP5776]], double [[TMP5774]], double [[TMP5775]]
25177 // CHECK-NEXT:    store double [[TMP5777]], ptr [[DV]], align 8
25178 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25179 // CHECK-NEXT:    [[TMP5778:%.*]] = load double, ptr [[DE]], align 8
25180 // CHECK-NEXT:    [[TMP5779:%.*]] = load double, ptr [[DD]], align 8
25181 // CHECK-NEXT:    [[TMP5780:%.*]] = bitcast double [[TMP5778]] to i64
25182 // CHECK-NEXT:    [[TMP5781:%.*]] = bitcast double [[TMP5779]] to i64
25183 // CHECK-NEXT:    [[TMP5782:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5780]], i64 [[TMP5781]] release monotonic, align 8
25184 // CHECK-NEXT:    [[TMP5783:%.*]] = extractvalue { i64, i1 } [[TMP5782]], 0
25185 // CHECK-NEXT:    [[TMP5784:%.*]] = bitcast i64 [[TMP5783]] to double
25186 // CHECK-NEXT:    [[TMP5785:%.*]] = extractvalue { i64, i1 } [[TMP5782]], 1
25187 // CHECK-NEXT:    [[TMP5786:%.*]] = select i1 [[TMP5785]], double [[TMP5778]], double [[TMP5784]]
25188 // CHECK-NEXT:    store double [[TMP5786]], ptr [[DV]], align 8
25189 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25190 // CHECK-NEXT:    [[TMP5787:%.*]] = load double, ptr [[DE]], align 8
25191 // CHECK-NEXT:    [[TMP5788:%.*]] = load double, ptr [[DD]], align 8
25192 // CHECK-NEXT:    [[TMP5789:%.*]] = bitcast double [[TMP5787]] to i64
25193 // CHECK-NEXT:    [[TMP5790:%.*]] = bitcast double [[TMP5788]] to i64
25194 // CHECK-NEXT:    [[TMP5791:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5789]], i64 [[TMP5790]] release monotonic, align 8
25195 // CHECK-NEXT:    [[TMP5792:%.*]] = extractvalue { i64, i1 } [[TMP5791]], 0
25196 // CHECK-NEXT:    [[TMP5793:%.*]] = bitcast i64 [[TMP5792]] to double
25197 // CHECK-NEXT:    [[TMP5794:%.*]] = extractvalue { i64, i1 } [[TMP5791]], 1
25198 // CHECK-NEXT:    [[TMP5795:%.*]] = select i1 [[TMP5794]], double [[TMP5787]], double [[TMP5793]]
25199 // CHECK-NEXT:    store double [[TMP5795]], ptr [[DV]], align 8
25200 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25201 // CHECK-NEXT:    [[TMP5796:%.*]] = load double, ptr [[DE]], align 8
25202 // CHECK-NEXT:    [[TMP5797:%.*]] = load double, ptr [[DD]], align 8
25203 // CHECK-NEXT:    [[TMP5798:%.*]] = bitcast double [[TMP5796]] to i64
25204 // CHECK-NEXT:    [[TMP5799:%.*]] = bitcast double [[TMP5797]] to i64
25205 // CHECK-NEXT:    [[TMP5800:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5798]], i64 [[TMP5799]] release monotonic, align 8
25206 // CHECK-NEXT:    [[TMP5801:%.*]] = extractvalue { i64, i1 } [[TMP5800]], 0
25207 // CHECK-NEXT:    [[TMP5802:%.*]] = bitcast i64 [[TMP5801]] to double
25208 // CHECK-NEXT:    [[TMP5803:%.*]] = extractvalue { i64, i1 } [[TMP5800]], 1
25209 // CHECK-NEXT:    br i1 [[TMP5803]], label [[DX_ATOMIC_EXIT537:%.*]], label [[DX_ATOMIC_CONT538:%.*]]
25210 // CHECK:       dx.atomic.cont538:
25211 // CHECK-NEXT:    store double [[TMP5802]], ptr [[DV]], align 8
25212 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT537]]
25213 // CHECK:       dx.atomic.exit537:
25214 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25215 // CHECK-NEXT:    [[TMP5804:%.*]] = load double, ptr [[DE]], align 8
25216 // CHECK-NEXT:    [[TMP5805:%.*]] = load double, ptr [[DD]], align 8
25217 // CHECK-NEXT:    [[TMP5806:%.*]] = bitcast double [[TMP5804]] to i64
25218 // CHECK-NEXT:    [[TMP5807:%.*]] = bitcast double [[TMP5805]] to i64
25219 // CHECK-NEXT:    [[TMP5808:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5806]], i64 [[TMP5807]] release monotonic, align 8
25220 // CHECK-NEXT:    [[TMP5809:%.*]] = extractvalue { i64, i1 } [[TMP5808]], 0
25221 // CHECK-NEXT:    [[TMP5810:%.*]] = bitcast i64 [[TMP5809]] to double
25222 // CHECK-NEXT:    [[TMP5811:%.*]] = extractvalue { i64, i1 } [[TMP5808]], 1
25223 // CHECK-NEXT:    br i1 [[TMP5811]], label [[DX_ATOMIC_EXIT539:%.*]], label [[DX_ATOMIC_CONT540:%.*]]
25224 // CHECK:       dx.atomic.cont540:
25225 // CHECK-NEXT:    store double [[TMP5810]], ptr [[DV]], align 8
25226 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT539]]
25227 // CHECK:       dx.atomic.exit539:
25228 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25229 // CHECK-NEXT:    [[TMP5812:%.*]] = load double, ptr [[DE]], align 8
25230 // CHECK-NEXT:    [[TMP5813:%.*]] = load double, ptr [[DD]], align 8
25231 // CHECK-NEXT:    [[TMP5814:%.*]] = bitcast double [[TMP5812]] to i64
25232 // CHECK-NEXT:    [[TMP5815:%.*]] = bitcast double [[TMP5813]] to i64
25233 // CHECK-NEXT:    [[TMP5816:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5814]], i64 [[TMP5815]] release monotonic, align 8
25234 // CHECK-NEXT:    [[TMP5817:%.*]] = extractvalue { i64, i1 } [[TMP5816]], 1
25235 // CHECK-NEXT:    [[TMP5818:%.*]] = sext i1 [[TMP5817]] to i32
25236 // CHECK-NEXT:    store i32 [[TMP5818]], ptr [[IR]], align 4
25237 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25238 // CHECK-NEXT:    [[TMP5819:%.*]] = load double, ptr [[DE]], align 8
25239 // CHECK-NEXT:    [[TMP5820:%.*]] = load double, ptr [[DD]], align 8
25240 // CHECK-NEXT:    [[TMP5821:%.*]] = bitcast double [[TMP5819]] to i64
25241 // CHECK-NEXT:    [[TMP5822:%.*]] = bitcast double [[TMP5820]] to i64
25242 // CHECK-NEXT:    [[TMP5823:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5821]], i64 [[TMP5822]] release monotonic, align 8
25243 // CHECK-NEXT:    [[TMP5824:%.*]] = extractvalue { i64, i1 } [[TMP5823]], 1
25244 // CHECK-NEXT:    [[TMP5825:%.*]] = sext i1 [[TMP5824]] to i32
25245 // CHECK-NEXT:    store i32 [[TMP5825]], ptr [[IR]], align 4
25246 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25247 // CHECK-NEXT:    [[TMP5826:%.*]] = load double, ptr [[DE]], align 8
25248 // CHECK-NEXT:    [[TMP5827:%.*]] = load double, ptr [[DD]], align 8
25249 // CHECK-NEXT:    [[TMP5828:%.*]] = bitcast double [[TMP5826]] to i64
25250 // CHECK-NEXT:    [[TMP5829:%.*]] = bitcast double [[TMP5827]] to i64
25251 // CHECK-NEXT:    [[TMP5830:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5828]], i64 [[TMP5829]] release monotonic, align 8
25252 // CHECK-NEXT:    [[TMP5831:%.*]] = extractvalue { i64, i1 } [[TMP5830]], 0
25253 // CHECK-NEXT:    [[TMP5832:%.*]] = bitcast i64 [[TMP5831]] to double
25254 // CHECK-NEXT:    [[TMP5833:%.*]] = extractvalue { i64, i1 } [[TMP5830]], 1
25255 // CHECK-NEXT:    br i1 [[TMP5833]], label [[DX_ATOMIC_EXIT541:%.*]], label [[DX_ATOMIC_CONT542:%.*]]
25256 // CHECK:       dx.atomic.cont542:
25257 // CHECK-NEXT:    store double [[TMP5832]], ptr [[DV]], align 8
25258 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT541]]
25259 // CHECK:       dx.atomic.exit541:
25260 // CHECK-NEXT:    [[TMP5834:%.*]] = extractvalue { i64, i1 } [[TMP5830]], 1
25261 // CHECK-NEXT:    [[TMP5835:%.*]] = sext i1 [[TMP5834]] to i32
25262 // CHECK-NEXT:    store i32 [[TMP5835]], ptr [[IR]], align 4
25263 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25264 // CHECK-NEXT:    [[TMP5836:%.*]] = load double, ptr [[DE]], align 8
25265 // CHECK-NEXT:    [[TMP5837:%.*]] = load double, ptr [[DD]], align 8
25266 // CHECK-NEXT:    [[TMP5838:%.*]] = bitcast double [[TMP5836]] to i64
25267 // CHECK-NEXT:    [[TMP5839:%.*]] = bitcast double [[TMP5837]] to i64
25268 // CHECK-NEXT:    [[TMP5840:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5838]], i64 [[TMP5839]] release monotonic, align 8
25269 // CHECK-NEXT:    [[TMP5841:%.*]] = extractvalue { i64, i1 } [[TMP5840]], 0
25270 // CHECK-NEXT:    [[TMP5842:%.*]] = bitcast i64 [[TMP5841]] to double
25271 // CHECK-NEXT:    [[TMP5843:%.*]] = extractvalue { i64, i1 } [[TMP5840]], 1
25272 // CHECK-NEXT:    br i1 [[TMP5843]], label [[DX_ATOMIC_EXIT543:%.*]], label [[DX_ATOMIC_CONT544:%.*]]
25273 // CHECK:       dx.atomic.cont544:
25274 // CHECK-NEXT:    store double [[TMP5842]], ptr [[DV]], align 8
25275 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT543]]
25276 // CHECK:       dx.atomic.exit543:
25277 // CHECK-NEXT:    [[TMP5844:%.*]] = extractvalue { i64, i1 } [[TMP5840]], 1
25278 // CHECK-NEXT:    [[TMP5845:%.*]] = sext i1 [[TMP5844]] to i32
25279 // CHECK-NEXT:    store i32 [[TMP5845]], ptr [[IR]], align 4
25280 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25281 // CHECK-NEXT:    [[TMP5846:%.*]] = load double, ptr [[DE]], align 8
25282 // CHECK-NEXT:    [[TMP5847:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5846]] seq_cst, align 8
25283 // CHECK-NEXT:    store double [[TMP5847]], ptr [[DV]], align 8
25284 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25285 // CHECK-NEXT:    [[TMP5848:%.*]] = load double, ptr [[DE]], align 8
25286 // CHECK-NEXT:    [[TMP5849:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5848]] seq_cst, align 8
25287 // CHECK-NEXT:    store double [[TMP5849]], ptr [[DV]], align 8
25288 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25289 // CHECK-NEXT:    [[TMP5850:%.*]] = load double, ptr [[DE]], align 8
25290 // CHECK-NEXT:    [[TMP5851:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5850]] seq_cst, align 8
25291 // CHECK-NEXT:    store double [[TMP5851]], ptr [[DV]], align 8
25292 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25293 // CHECK-NEXT:    [[TMP5852:%.*]] = load double, ptr [[DE]], align 8
25294 // CHECK-NEXT:    [[TMP5853:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5852]] seq_cst, align 8
25295 // CHECK-NEXT:    store double [[TMP5853]], ptr [[DV]], align 8
25296 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25297 // CHECK-NEXT:    [[TMP5854:%.*]] = load double, ptr [[DE]], align 8
25298 // CHECK-NEXT:    [[TMP5855:%.*]] = load double, ptr [[DD]], align 8
25299 // CHECK-NEXT:    [[TMP5856:%.*]] = bitcast double [[TMP5854]] to i64
25300 // CHECK-NEXT:    [[TMP5857:%.*]] = bitcast double [[TMP5855]] to i64
25301 // CHECK-NEXT:    [[TMP5858:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5856]], i64 [[TMP5857]] seq_cst seq_cst, align 8
25302 // CHECK-NEXT:    [[TMP5859:%.*]] = extractvalue { i64, i1 } [[TMP5858]], 0
25303 // CHECK-NEXT:    [[TMP5860:%.*]] = bitcast i64 [[TMP5859]] to double
25304 // CHECK-NEXT:    store double [[TMP5860]], ptr [[DV]], align 8
25305 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25306 // CHECK-NEXT:    [[TMP5861:%.*]] = load double, ptr [[DE]], align 8
25307 // CHECK-NEXT:    [[TMP5862:%.*]] = load double, ptr [[DD]], align 8
25308 // CHECK-NEXT:    [[TMP5863:%.*]] = bitcast double [[TMP5861]] to i64
25309 // CHECK-NEXT:    [[TMP5864:%.*]] = bitcast double [[TMP5862]] to i64
25310 // CHECK-NEXT:    [[TMP5865:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5863]], i64 [[TMP5864]] seq_cst seq_cst, align 8
25311 // CHECK-NEXT:    [[TMP5866:%.*]] = extractvalue { i64, i1 } [[TMP5865]], 0
25312 // CHECK-NEXT:    [[TMP5867:%.*]] = bitcast i64 [[TMP5866]] to double
25313 // CHECK-NEXT:    store double [[TMP5867]], ptr [[DV]], align 8
25314 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25315 // CHECK-NEXT:    [[TMP5868:%.*]] = load double, ptr [[DE]], align 8
25316 // CHECK-NEXT:    [[TMP5869:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5868]] seq_cst, align 8
25317 // CHECK-NEXT:    [[TMP5870:%.*]] = fcmp ogt double [[TMP5869]], [[TMP5868]]
25318 // CHECK-NEXT:    [[TMP5871:%.*]] = select i1 [[TMP5870]], double [[TMP5868]], double [[TMP5869]]
25319 // CHECK-NEXT:    store double [[TMP5871]], ptr [[DV]], align 8
25320 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25321 // CHECK-NEXT:    [[TMP5872:%.*]] = load double, ptr [[DE]], align 8
25322 // CHECK-NEXT:    [[TMP5873:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5872]] seq_cst, align 8
25323 // CHECK-NEXT:    [[TMP5874:%.*]] = fcmp olt double [[TMP5873]], [[TMP5872]]
25324 // CHECK-NEXT:    [[TMP5875:%.*]] = select i1 [[TMP5874]], double [[TMP5872]], double [[TMP5873]]
25325 // CHECK-NEXT:    store double [[TMP5875]], ptr [[DV]], align 8
25326 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25327 // CHECK-NEXT:    [[TMP5876:%.*]] = load double, ptr [[DE]], align 8
25328 // CHECK-NEXT:    [[TMP5877:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5876]] seq_cst, align 8
25329 // CHECK-NEXT:    [[TMP5878:%.*]] = fcmp olt double [[TMP5877]], [[TMP5876]]
25330 // CHECK-NEXT:    [[TMP5879:%.*]] = select i1 [[TMP5878]], double [[TMP5876]], double [[TMP5877]]
25331 // CHECK-NEXT:    store double [[TMP5879]], ptr [[DV]], align 8
25332 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25333 // CHECK-NEXT:    [[TMP5880:%.*]] = load double, ptr [[DE]], align 8
25334 // CHECK-NEXT:    [[TMP5881:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5880]] seq_cst, align 8
25335 // CHECK-NEXT:    [[TMP5882:%.*]] = fcmp ogt double [[TMP5881]], [[TMP5880]]
25336 // CHECK-NEXT:    [[TMP5883:%.*]] = select i1 [[TMP5882]], double [[TMP5880]], double [[TMP5881]]
25337 // CHECK-NEXT:    store double [[TMP5883]], ptr [[DV]], align 8
25338 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25339 // CHECK-NEXT:    [[TMP5884:%.*]] = load double, ptr [[DE]], align 8
25340 // CHECK-NEXT:    [[TMP5885:%.*]] = load double, ptr [[DD]], align 8
25341 // CHECK-NEXT:    [[TMP5886:%.*]] = bitcast double [[TMP5884]] to i64
25342 // CHECK-NEXT:    [[TMP5887:%.*]] = bitcast double [[TMP5885]] to i64
25343 // CHECK-NEXT:    [[TMP5888:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5886]], i64 [[TMP5887]] seq_cst seq_cst, align 8
25344 // CHECK-NEXT:    [[TMP5889:%.*]] = extractvalue { i64, i1 } [[TMP5888]], 0
25345 // CHECK-NEXT:    [[TMP5890:%.*]] = bitcast i64 [[TMP5889]] to double
25346 // CHECK-NEXT:    [[TMP5891:%.*]] = extractvalue { i64, i1 } [[TMP5888]], 1
25347 // CHECK-NEXT:    [[TMP5892:%.*]] = select i1 [[TMP5891]], double [[TMP5884]], double [[TMP5890]]
25348 // CHECK-NEXT:    store double [[TMP5892]], ptr [[DV]], align 8
25349 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25350 // CHECK-NEXT:    [[TMP5893:%.*]] = load double, ptr [[DE]], align 8
25351 // CHECK-NEXT:    [[TMP5894:%.*]] = load double, ptr [[DD]], align 8
25352 // CHECK-NEXT:    [[TMP5895:%.*]] = bitcast double [[TMP5893]] to i64
25353 // CHECK-NEXT:    [[TMP5896:%.*]] = bitcast double [[TMP5894]] to i64
25354 // CHECK-NEXT:    [[TMP5897:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5895]], i64 [[TMP5896]] seq_cst seq_cst, align 8
25355 // CHECK-NEXT:    [[TMP5898:%.*]] = extractvalue { i64, i1 } [[TMP5897]], 0
25356 // CHECK-NEXT:    [[TMP5899:%.*]] = bitcast i64 [[TMP5898]] to double
25357 // CHECK-NEXT:    [[TMP5900:%.*]] = extractvalue { i64, i1 } [[TMP5897]], 1
25358 // CHECK-NEXT:    [[TMP5901:%.*]] = select i1 [[TMP5900]], double [[TMP5893]], double [[TMP5899]]
25359 // CHECK-NEXT:    store double [[TMP5901]], ptr [[DV]], align 8
25360 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25361 // CHECK-NEXT:    [[TMP5902:%.*]] = load double, ptr [[DE]], align 8
25362 // CHECK-NEXT:    [[TMP5903:%.*]] = load double, ptr [[DD]], align 8
25363 // CHECK-NEXT:    [[TMP5904:%.*]] = bitcast double [[TMP5902]] to i64
25364 // CHECK-NEXT:    [[TMP5905:%.*]] = bitcast double [[TMP5903]] to i64
25365 // CHECK-NEXT:    [[TMP5906:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5904]], i64 [[TMP5905]] seq_cst seq_cst, align 8
25366 // CHECK-NEXT:    [[TMP5907:%.*]] = extractvalue { i64, i1 } [[TMP5906]], 0
25367 // CHECK-NEXT:    [[TMP5908:%.*]] = bitcast i64 [[TMP5907]] to double
25368 // CHECK-NEXT:    [[TMP5909:%.*]] = extractvalue { i64, i1 } [[TMP5906]], 1
25369 // CHECK-NEXT:    br i1 [[TMP5909]], label [[DX_ATOMIC_EXIT545:%.*]], label [[DX_ATOMIC_CONT546:%.*]]
25370 // CHECK:       dx.atomic.cont546:
25371 // CHECK-NEXT:    store double [[TMP5908]], ptr [[DV]], align 8
25372 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT545]]
25373 // CHECK:       dx.atomic.exit545:
25374 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25375 // CHECK-NEXT:    [[TMP5910:%.*]] = load double, ptr [[DE]], align 8
25376 // CHECK-NEXT:    [[TMP5911:%.*]] = load double, ptr [[DD]], align 8
25377 // CHECK-NEXT:    [[TMP5912:%.*]] = bitcast double [[TMP5910]] to i64
25378 // CHECK-NEXT:    [[TMP5913:%.*]] = bitcast double [[TMP5911]] to i64
25379 // CHECK-NEXT:    [[TMP5914:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5912]], i64 [[TMP5913]] seq_cst seq_cst, align 8
25380 // CHECK-NEXT:    [[TMP5915:%.*]] = extractvalue { i64, i1 } [[TMP5914]], 0
25381 // CHECK-NEXT:    [[TMP5916:%.*]] = bitcast i64 [[TMP5915]] to double
25382 // CHECK-NEXT:    [[TMP5917:%.*]] = extractvalue { i64, i1 } [[TMP5914]], 1
25383 // CHECK-NEXT:    br i1 [[TMP5917]], label [[DX_ATOMIC_EXIT547:%.*]], label [[DX_ATOMIC_CONT548:%.*]]
25384 // CHECK:       dx.atomic.cont548:
25385 // CHECK-NEXT:    store double [[TMP5916]], ptr [[DV]], align 8
25386 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT547]]
25387 // CHECK:       dx.atomic.exit547:
25388 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25389 // CHECK-NEXT:    [[TMP5918:%.*]] = load double, ptr [[DE]], align 8
25390 // CHECK-NEXT:    [[TMP5919:%.*]] = load double, ptr [[DD]], align 8
25391 // CHECK-NEXT:    [[TMP5920:%.*]] = bitcast double [[TMP5918]] to i64
25392 // CHECK-NEXT:    [[TMP5921:%.*]] = bitcast double [[TMP5919]] to i64
25393 // CHECK-NEXT:    [[TMP5922:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5920]], i64 [[TMP5921]] seq_cst seq_cst, align 8
25394 // CHECK-NEXT:    [[TMP5923:%.*]] = extractvalue { i64, i1 } [[TMP5922]], 1
25395 // CHECK-NEXT:    [[TMP5924:%.*]] = sext i1 [[TMP5923]] to i32
25396 // CHECK-NEXT:    store i32 [[TMP5924]], ptr [[IR]], align 4
25397 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25398 // CHECK-NEXT:    [[TMP5925:%.*]] = load double, ptr [[DE]], align 8
25399 // CHECK-NEXT:    [[TMP5926:%.*]] = load double, ptr [[DD]], align 8
25400 // CHECK-NEXT:    [[TMP5927:%.*]] = bitcast double [[TMP5925]] to i64
25401 // CHECK-NEXT:    [[TMP5928:%.*]] = bitcast double [[TMP5926]] to i64
25402 // CHECK-NEXT:    [[TMP5929:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5927]], i64 [[TMP5928]] seq_cst seq_cst, align 8
25403 // CHECK-NEXT:    [[TMP5930:%.*]] = extractvalue { i64, i1 } [[TMP5929]], 1
25404 // CHECK-NEXT:    [[TMP5931:%.*]] = sext i1 [[TMP5930]] to i32
25405 // CHECK-NEXT:    store i32 [[TMP5931]], ptr [[IR]], align 4
25406 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25407 // CHECK-NEXT:    [[TMP5932:%.*]] = load double, ptr [[DE]], align 8
25408 // CHECK-NEXT:    [[TMP5933:%.*]] = load double, ptr [[DD]], align 8
25409 // CHECK-NEXT:    [[TMP5934:%.*]] = bitcast double [[TMP5932]] to i64
25410 // CHECK-NEXT:    [[TMP5935:%.*]] = bitcast double [[TMP5933]] to i64
25411 // CHECK-NEXT:    [[TMP5936:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5934]], i64 [[TMP5935]] seq_cst seq_cst, align 8
25412 // CHECK-NEXT:    [[TMP5937:%.*]] = extractvalue { i64, i1 } [[TMP5936]], 0
25413 // CHECK-NEXT:    [[TMP5938:%.*]] = bitcast i64 [[TMP5937]] to double
25414 // CHECK-NEXT:    [[TMP5939:%.*]] = extractvalue { i64, i1 } [[TMP5936]], 1
25415 // CHECK-NEXT:    br i1 [[TMP5939]], label [[DX_ATOMIC_EXIT549:%.*]], label [[DX_ATOMIC_CONT550:%.*]]
25416 // CHECK:       dx.atomic.cont550:
25417 // CHECK-NEXT:    store double [[TMP5938]], ptr [[DV]], align 8
25418 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT549]]
25419 // CHECK:       dx.atomic.exit549:
25420 // CHECK-NEXT:    [[TMP5940:%.*]] = extractvalue { i64, i1 } [[TMP5936]], 1
25421 // CHECK-NEXT:    [[TMP5941:%.*]] = sext i1 [[TMP5940]] to i32
25422 // CHECK-NEXT:    store i32 [[TMP5941]], ptr [[IR]], align 4
25423 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25424 // CHECK-NEXT:    [[TMP5942:%.*]] = load double, ptr [[DE]], align 8
25425 // CHECK-NEXT:    [[TMP5943:%.*]] = load double, ptr [[DD]], align 8
25426 // CHECK-NEXT:    [[TMP5944:%.*]] = bitcast double [[TMP5942]] to i64
25427 // CHECK-NEXT:    [[TMP5945:%.*]] = bitcast double [[TMP5943]] to i64
25428 // CHECK-NEXT:    [[TMP5946:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5944]], i64 [[TMP5945]] seq_cst seq_cst, align 8
25429 // CHECK-NEXT:    [[TMP5947:%.*]] = extractvalue { i64, i1 } [[TMP5946]], 0
25430 // CHECK-NEXT:    [[TMP5948:%.*]] = bitcast i64 [[TMP5947]] to double
25431 // CHECK-NEXT:    [[TMP5949:%.*]] = extractvalue { i64, i1 } [[TMP5946]], 1
25432 // CHECK-NEXT:    br i1 [[TMP5949]], label [[DX_ATOMIC_EXIT551:%.*]], label [[DX_ATOMIC_CONT552:%.*]]
25433 // CHECK:       dx.atomic.cont552:
25434 // CHECK-NEXT:    store double [[TMP5948]], ptr [[DV]], align 8
25435 // CHECK-NEXT:    br label [[DX_ATOMIC_EXIT551]]
25436 // CHECK:       dx.atomic.exit551:
25437 // CHECK-NEXT:    [[TMP5950:%.*]] = extractvalue { i64, i1 } [[TMP5946]], 1
25438 // CHECK-NEXT:    [[TMP5951:%.*]] = sext i1 [[TMP5950]] to i32
25439 // CHECK-NEXT:    store i32 [[TMP5951]], ptr [[IR]], align 4
25440 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25441 // CHECK-NEXT:    ret void
25442 //
25443 //
25444 // CHECK-LABEL: @cxevd(
25445 // CHECK-NEXT:  entry:
25446 // CHECK-NEXT:    [[CX:%.*]] = alloca i8, align 1
25447 // CHECK-NEXT:    [[CV:%.*]] = alloca i8, align 1
25448 // CHECK-NEXT:    [[CE:%.*]] = alloca i8, align 1
25449 // CHECK-NEXT:    [[CD:%.*]] = alloca i8, align 1
25450 // CHECK-NEXT:    [[TMP0:%.*]] = load i8, ptr [[CE]], align 1
25451 // CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP0]] monotonic, align 1
25452 // CHECK-NEXT:    store i8 [[TMP1]], ptr [[CV]], align 1
25453 // CHECK-NEXT:    [[TMP2:%.*]] = load i8, ptr [[CE]], align 1
25454 // CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP2]] monotonic, align 1
25455 // CHECK-NEXT:    store i8 [[TMP3]], ptr [[CV]], align 1
25456 // CHECK-NEXT:    [[TMP4:%.*]] = load i8, ptr [[CE]], align 1
25457 // CHECK-NEXT:    [[TMP5:%.*]] = load i8, ptr [[CD]], align 1
25458 // CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP4]], i8 [[TMP5]] monotonic monotonic, align 1
25459 // CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i8, i1 } [[TMP6]], 0
25460 // CHECK-NEXT:    store i8 [[TMP7]], ptr [[CV]], align 1
25461 // CHECK-NEXT:    [[TMP8:%.*]] = load i8, ptr [[CE]], align 1
25462 // CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP8]] monotonic, align 1
25463 // CHECK-NEXT:    [[TMP10:%.*]] = icmp slt i8 [[TMP9]], [[TMP8]]
25464 // CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i8 [[TMP8]], i8 [[TMP9]]
25465 // CHECK-NEXT:    store i8 [[TMP11]], ptr [[CV]], align 1
25466 // CHECK-NEXT:    [[TMP12:%.*]] = load i8, ptr [[CE]], align 1
25467 // CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP12]] monotonic, align 1
25468 // CHECK-NEXT:    [[TMP14:%.*]] = icmp sgt i8 [[TMP13]], [[TMP12]]
25469 // CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i8 [[TMP12]], i8 [[TMP13]]
25470 // CHECK-NEXT:    store i8 [[TMP15]], ptr [[CV]], align 1
25471 // CHECK-NEXT:    [[TMP16:%.*]] = load i8, ptr [[CE]], align 1
25472 // CHECK-NEXT:    [[TMP17:%.*]] = load i8, ptr [[CD]], align 1
25473 // CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP16]], i8 [[TMP17]] monotonic monotonic, align 1
25474 // CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i8, i1 } [[TMP18]], 0
25475 // CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i8, i1 } [[TMP18]], 1
25476 // CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i8 [[TMP16]], i8 [[TMP19]]
25477 // CHECK-NEXT:    store i8 [[TMP21]], ptr [[CV]], align 1
25478 // CHECK-NEXT:    [[TMP22:%.*]] = load i8, ptr [[CE]], align 1
25479 // CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP22]] acq_rel, align 1
25480 // CHECK-NEXT:    store i8 [[TMP23]], ptr [[CV]], align 1
25481 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25482 // CHECK-NEXT:    [[TMP24:%.*]] = load i8, ptr [[CE]], align 1
25483 // CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP24]] acq_rel, align 1
25484 // CHECK-NEXT:    store i8 [[TMP25]], ptr [[CV]], align 1
25485 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25486 // CHECK-NEXT:    [[TMP26:%.*]] = load i8, ptr [[CE]], align 1
25487 // CHECK-NEXT:    [[TMP27:%.*]] = load i8, ptr [[CD]], align 1
25488 // CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP26]], i8 [[TMP27]] acq_rel acquire, align 1
25489 // CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i8, i1 } [[TMP28]], 0
25490 // CHECK-NEXT:    store i8 [[TMP29]], ptr [[CV]], align 1
25491 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25492 // CHECK-NEXT:    [[TMP30:%.*]] = load i8, ptr [[CE]], align 1
25493 // CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP30]] acq_rel, align 1
25494 // CHECK-NEXT:    [[TMP32:%.*]] = icmp slt i8 [[TMP31]], [[TMP30]]
25495 // CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i8 [[TMP30]], i8 [[TMP31]]
25496 // CHECK-NEXT:    store i8 [[TMP33]], ptr [[CV]], align 1
25497 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25498 // CHECK-NEXT:    [[TMP34:%.*]] = load i8, ptr [[CE]], align 1
25499 // CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP34]] acq_rel, align 1
25500 // CHECK-NEXT:    [[TMP36:%.*]] = icmp sgt i8 [[TMP35]], [[TMP34]]
25501 // CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i8 [[TMP34]], i8 [[TMP35]]
25502 // CHECK-NEXT:    store i8 [[TMP37]], ptr [[CV]], align 1
25503 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25504 // CHECK-NEXT:    [[TMP38:%.*]] = load i8, ptr [[CE]], align 1
25505 // CHECK-NEXT:    [[TMP39:%.*]] = load i8, ptr [[CD]], align 1
25506 // CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP38]], i8 [[TMP39]] acq_rel acquire, align 1
25507 // CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i8, i1 } [[TMP40]], 0
25508 // CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i8, i1 } [[TMP40]], 1
25509 // CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i8 [[TMP38]], i8 [[TMP41]]
25510 // CHECK-NEXT:    store i8 [[TMP43]], ptr [[CV]], align 1
25511 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25512 // CHECK-NEXT:    [[TMP44:%.*]] = load i8, ptr [[CE]], align 1
25513 // CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP44]] acquire, align 1
25514 // CHECK-NEXT:    store i8 [[TMP45]], ptr [[CV]], align 1
25515 // CHECK-NEXT:    [[TMP46:%.*]] = load i8, ptr [[CE]], align 1
25516 // CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP46]] acquire, align 1
25517 // CHECK-NEXT:    store i8 [[TMP47]], ptr [[CV]], align 1
25518 // CHECK-NEXT:    [[TMP48:%.*]] = load i8, ptr [[CE]], align 1
25519 // CHECK-NEXT:    [[TMP49:%.*]] = load i8, ptr [[CD]], align 1
25520 // CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP48]], i8 [[TMP49]] acquire acquire, align 1
25521 // CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i8, i1 } [[TMP50]], 0
25522 // CHECK-NEXT:    store i8 [[TMP51]], ptr [[CV]], align 1
25523 // CHECK-NEXT:    [[TMP52:%.*]] = load i8, ptr [[CE]], align 1
25524 // CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP52]] acquire, align 1
25525 // CHECK-NEXT:    [[TMP54:%.*]] = icmp slt i8 [[TMP53]], [[TMP52]]
25526 // CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i8 [[TMP52]], i8 [[TMP53]]
25527 // CHECK-NEXT:    store i8 [[TMP55]], ptr [[CV]], align 1
25528 // CHECK-NEXT:    [[TMP56:%.*]] = load i8, ptr [[CE]], align 1
25529 // CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP56]] acquire, align 1
25530 // CHECK-NEXT:    [[TMP58:%.*]] = icmp sgt i8 [[TMP57]], [[TMP56]]
25531 // CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i8 [[TMP56]], i8 [[TMP57]]
25532 // CHECK-NEXT:    store i8 [[TMP59]], ptr [[CV]], align 1
25533 // CHECK-NEXT:    [[TMP60:%.*]] = load i8, ptr [[CE]], align 1
25534 // CHECK-NEXT:    [[TMP61:%.*]] = load i8, ptr [[CD]], align 1
25535 // CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP60]], i8 [[TMP61]] acquire acquire, align 1
25536 // CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i8, i1 } [[TMP62]], 0
25537 // CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i8, i1 } [[TMP62]], 1
25538 // CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i8 [[TMP60]], i8 [[TMP63]]
25539 // CHECK-NEXT:    store i8 [[TMP65]], ptr [[CV]], align 1
25540 // CHECK-NEXT:    [[TMP66:%.*]] = load i8, ptr [[CE]], align 1
25541 // CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP66]] monotonic, align 1
25542 // CHECK-NEXT:    store i8 [[TMP67]], ptr [[CV]], align 1
25543 // CHECK-NEXT:    [[TMP68:%.*]] = load i8, ptr [[CE]], align 1
25544 // CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP68]] monotonic, align 1
25545 // CHECK-NEXT:    store i8 [[TMP69]], ptr [[CV]], align 1
25546 // CHECK-NEXT:    [[TMP70:%.*]] = load i8, ptr [[CE]], align 1
25547 // CHECK-NEXT:    [[TMP71:%.*]] = load i8, ptr [[CD]], align 1
25548 // CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP70]], i8 [[TMP71]] monotonic monotonic, align 1
25549 // CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i8, i1 } [[TMP72]], 0
25550 // CHECK-NEXT:    store i8 [[TMP73]], ptr [[CV]], align 1
25551 // CHECK-NEXT:    [[TMP74:%.*]] = load i8, ptr [[CE]], align 1
25552 // CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP74]] monotonic, align 1
25553 // CHECK-NEXT:    [[TMP76:%.*]] = icmp slt i8 [[TMP75]], [[TMP74]]
25554 // CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i8 [[TMP74]], i8 [[TMP75]]
25555 // CHECK-NEXT:    store i8 [[TMP77]], ptr [[CV]], align 1
25556 // CHECK-NEXT:    [[TMP78:%.*]] = load i8, ptr [[CE]], align 1
25557 // CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP78]] monotonic, align 1
25558 // CHECK-NEXT:    [[TMP80:%.*]] = icmp sgt i8 [[TMP79]], [[TMP78]]
25559 // CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i8 [[TMP78]], i8 [[TMP79]]
25560 // CHECK-NEXT:    store i8 [[TMP81]], ptr [[CV]], align 1
25561 // CHECK-NEXT:    [[TMP82:%.*]] = load i8, ptr [[CE]], align 1
25562 // CHECK-NEXT:    [[TMP83:%.*]] = load i8, ptr [[CD]], align 1
25563 // CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP82]], i8 [[TMP83]] monotonic monotonic, align 1
25564 // CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i8, i1 } [[TMP84]], 0
25565 // CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i8, i1 } [[TMP84]], 1
25566 // CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i8 [[TMP82]], i8 [[TMP85]]
25567 // CHECK-NEXT:    store i8 [[TMP87]], ptr [[CV]], align 1
25568 // CHECK-NEXT:    [[TMP88:%.*]] = load i8, ptr [[CE]], align 1
25569 // CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP88]] release, align 1
25570 // CHECK-NEXT:    store i8 [[TMP89]], ptr [[CV]], align 1
25571 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25572 // CHECK-NEXT:    [[TMP90:%.*]] = load i8, ptr [[CE]], align 1
25573 // CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP90]] release, align 1
25574 // CHECK-NEXT:    store i8 [[TMP91]], ptr [[CV]], align 1
25575 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25576 // CHECK-NEXT:    [[TMP92:%.*]] = load i8, ptr [[CE]], align 1
25577 // CHECK-NEXT:    [[TMP93:%.*]] = load i8, ptr [[CD]], align 1
25578 // CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP92]], i8 [[TMP93]] release monotonic, align 1
25579 // CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i8, i1 } [[TMP94]], 0
25580 // CHECK-NEXT:    store i8 [[TMP95]], ptr [[CV]], align 1
25581 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25582 // CHECK-NEXT:    [[TMP96:%.*]] = load i8, ptr [[CE]], align 1
25583 // CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP96]] release, align 1
25584 // CHECK-NEXT:    [[TMP98:%.*]] = icmp slt i8 [[TMP97]], [[TMP96]]
25585 // CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i8 [[TMP96]], i8 [[TMP97]]
25586 // CHECK-NEXT:    store i8 [[TMP99]], ptr [[CV]], align 1
25587 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25588 // CHECK-NEXT:    [[TMP100:%.*]] = load i8, ptr [[CE]], align 1
25589 // CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP100]] release, align 1
25590 // CHECK-NEXT:    [[TMP102:%.*]] = icmp sgt i8 [[TMP101]], [[TMP100]]
25591 // CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i8 [[TMP100]], i8 [[TMP101]]
25592 // CHECK-NEXT:    store i8 [[TMP103]], ptr [[CV]], align 1
25593 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25594 // CHECK-NEXT:    [[TMP104:%.*]] = load i8, ptr [[CE]], align 1
25595 // CHECK-NEXT:    [[TMP105:%.*]] = load i8, ptr [[CD]], align 1
25596 // CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP104]], i8 [[TMP105]] release monotonic, align 1
25597 // CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i8, i1 } [[TMP106]], 0
25598 // CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i8, i1 } [[TMP106]], 1
25599 // CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i8 [[TMP104]], i8 [[TMP107]]
25600 // CHECK-NEXT:    store i8 [[TMP109]], ptr [[CV]], align 1
25601 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25602 // CHECK-NEXT:    [[TMP110:%.*]] = load i8, ptr [[CE]], align 1
25603 // CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP110]] seq_cst, align 1
25604 // CHECK-NEXT:    store i8 [[TMP111]], ptr [[CV]], align 1
25605 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25606 // CHECK-NEXT:    [[TMP112:%.*]] = load i8, ptr [[CE]], align 1
25607 // CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP112]] seq_cst, align 1
25608 // CHECK-NEXT:    store i8 [[TMP113]], ptr [[CV]], align 1
25609 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25610 // CHECK-NEXT:    [[TMP114:%.*]] = load i8, ptr [[CE]], align 1
25611 // CHECK-NEXT:    [[TMP115:%.*]] = load i8, ptr [[CD]], align 1
25612 // CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP114]], i8 [[TMP115]] seq_cst seq_cst, align 1
25613 // CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i8, i1 } [[TMP116]], 0
25614 // CHECK-NEXT:    store i8 [[TMP117]], ptr [[CV]], align 1
25615 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25616 // CHECK-NEXT:    [[TMP118:%.*]] = load i8, ptr [[CE]], align 1
25617 // CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP118]] seq_cst, align 1
25618 // CHECK-NEXT:    [[TMP120:%.*]] = icmp slt i8 [[TMP119]], [[TMP118]]
25619 // CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i8 [[TMP118]], i8 [[TMP119]]
25620 // CHECK-NEXT:    store i8 [[TMP121]], ptr [[CV]], align 1
25621 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25622 // CHECK-NEXT:    [[TMP122:%.*]] = load i8, ptr [[CE]], align 1
25623 // CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP122]] seq_cst, align 1
25624 // CHECK-NEXT:    [[TMP124:%.*]] = icmp sgt i8 [[TMP123]], [[TMP122]]
25625 // CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i8 [[TMP122]], i8 [[TMP123]]
25626 // CHECK-NEXT:    store i8 [[TMP125]], ptr [[CV]], align 1
25627 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25628 // CHECK-NEXT:    [[TMP126:%.*]] = load i8, ptr [[CE]], align 1
25629 // CHECK-NEXT:    [[TMP127:%.*]] = load i8, ptr [[CD]], align 1
25630 // CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP126]], i8 [[TMP127]] seq_cst seq_cst, align 1
25631 // CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i8, i1 } [[TMP128]], 0
25632 // CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i8, i1 } [[TMP128]], 1
25633 // CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i8 [[TMP126]], i8 [[TMP129]]
25634 // CHECK-NEXT:    store i8 [[TMP131]], ptr [[CV]], align 1
25635 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25636 // CHECK-NEXT:    [[TMP132:%.*]] = load i8, ptr [[CV]], align 1
25637 // CHECK-NEXT:    ret i8 [[TMP132]]
25638 //
25639 //
25640 // CHECK-LABEL: @ucxevd(
25641 // CHECK-NEXT:  entry:
25642 // CHECK-NEXT:    [[UCX:%.*]] = alloca i8, align 1
25643 // CHECK-NEXT:    [[UCV:%.*]] = alloca i8, align 1
25644 // CHECK-NEXT:    [[UCE:%.*]] = alloca i8, align 1
25645 // CHECK-NEXT:    [[UCD:%.*]] = alloca i8, align 1
25646 // CHECK-NEXT:    [[TMP0:%.*]] = load i8, ptr [[UCE]], align 1
25647 // CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP0]] monotonic, align 1
25648 // CHECK-NEXT:    store i8 [[TMP1]], ptr [[UCV]], align 1
25649 // CHECK-NEXT:    [[TMP2:%.*]] = load i8, ptr [[UCE]], align 1
25650 // CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP2]] monotonic, align 1
25651 // CHECK-NEXT:    store i8 [[TMP3]], ptr [[UCV]], align 1
25652 // CHECK-NEXT:    [[TMP4:%.*]] = load i8, ptr [[UCE]], align 1
25653 // CHECK-NEXT:    [[TMP5:%.*]] = load i8, ptr [[UCD]], align 1
25654 // CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP4]], i8 [[TMP5]] monotonic monotonic, align 1
25655 // CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i8, i1 } [[TMP6]], 0
25656 // CHECK-NEXT:    store i8 [[TMP7]], ptr [[UCV]], align 1
25657 // CHECK-NEXT:    [[TMP8:%.*]] = load i8, ptr [[UCE]], align 1
25658 // CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP8]] monotonic, align 1
25659 // CHECK-NEXT:    [[TMP10:%.*]] = icmp ult i8 [[TMP9]], [[TMP8]]
25660 // CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i8 [[TMP8]], i8 [[TMP9]]
25661 // CHECK-NEXT:    store i8 [[TMP11]], ptr [[UCV]], align 1
25662 // CHECK-NEXT:    [[TMP12:%.*]] = load i8, ptr [[UCE]], align 1
25663 // CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP12]] monotonic, align 1
25664 // CHECK-NEXT:    [[TMP14:%.*]] = icmp ugt i8 [[TMP13]], [[TMP12]]
25665 // CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i8 [[TMP12]], i8 [[TMP13]]
25666 // CHECK-NEXT:    store i8 [[TMP15]], ptr [[UCV]], align 1
25667 // CHECK-NEXT:    [[TMP16:%.*]] = load i8, ptr [[UCE]], align 1
25668 // CHECK-NEXT:    [[TMP17:%.*]] = load i8, ptr [[UCD]], align 1
25669 // CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP16]], i8 [[TMP17]] monotonic monotonic, align 1
25670 // CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i8, i1 } [[TMP18]], 0
25671 // CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i8, i1 } [[TMP18]], 1
25672 // CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i8 [[TMP16]], i8 [[TMP19]]
25673 // CHECK-NEXT:    store i8 [[TMP21]], ptr [[UCV]], align 1
25674 // CHECK-NEXT:    [[TMP22:%.*]] = load i8, ptr [[UCE]], align 1
25675 // CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP22]] acq_rel, align 1
25676 // CHECK-NEXT:    store i8 [[TMP23]], ptr [[UCV]], align 1
25677 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25678 // CHECK-NEXT:    [[TMP24:%.*]] = load i8, ptr [[UCE]], align 1
25679 // CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP24]] acq_rel, align 1
25680 // CHECK-NEXT:    store i8 [[TMP25]], ptr [[UCV]], align 1
25681 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25682 // CHECK-NEXT:    [[TMP26:%.*]] = load i8, ptr [[UCE]], align 1
25683 // CHECK-NEXT:    [[TMP27:%.*]] = load i8, ptr [[UCD]], align 1
25684 // CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP26]], i8 [[TMP27]] acq_rel acquire, align 1
25685 // CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i8, i1 } [[TMP28]], 0
25686 // CHECK-NEXT:    store i8 [[TMP29]], ptr [[UCV]], align 1
25687 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25688 // CHECK-NEXT:    [[TMP30:%.*]] = load i8, ptr [[UCE]], align 1
25689 // CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP30]] acq_rel, align 1
25690 // CHECK-NEXT:    [[TMP32:%.*]] = icmp ult i8 [[TMP31]], [[TMP30]]
25691 // CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i8 [[TMP30]], i8 [[TMP31]]
25692 // CHECK-NEXT:    store i8 [[TMP33]], ptr [[UCV]], align 1
25693 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25694 // CHECK-NEXT:    [[TMP34:%.*]] = load i8, ptr [[UCE]], align 1
25695 // CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP34]] acq_rel, align 1
25696 // CHECK-NEXT:    [[TMP36:%.*]] = icmp ugt i8 [[TMP35]], [[TMP34]]
25697 // CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i8 [[TMP34]], i8 [[TMP35]]
25698 // CHECK-NEXT:    store i8 [[TMP37]], ptr [[UCV]], align 1
25699 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25700 // CHECK-NEXT:    [[TMP38:%.*]] = load i8, ptr [[UCE]], align 1
25701 // CHECK-NEXT:    [[TMP39:%.*]] = load i8, ptr [[UCD]], align 1
25702 // CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP38]], i8 [[TMP39]] acq_rel acquire, align 1
25703 // CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i8, i1 } [[TMP40]], 0
25704 // CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i8, i1 } [[TMP40]], 1
25705 // CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i8 [[TMP38]], i8 [[TMP41]]
25706 // CHECK-NEXT:    store i8 [[TMP43]], ptr [[UCV]], align 1
25707 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25708 // CHECK-NEXT:    [[TMP44:%.*]] = load i8, ptr [[UCE]], align 1
25709 // CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP44]] acquire, align 1
25710 // CHECK-NEXT:    store i8 [[TMP45]], ptr [[UCV]], align 1
25711 // CHECK-NEXT:    [[TMP46:%.*]] = load i8, ptr [[UCE]], align 1
25712 // CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP46]] acquire, align 1
25713 // CHECK-NEXT:    store i8 [[TMP47]], ptr [[UCV]], align 1
25714 // CHECK-NEXT:    [[TMP48:%.*]] = load i8, ptr [[UCE]], align 1
25715 // CHECK-NEXT:    [[TMP49:%.*]] = load i8, ptr [[UCD]], align 1
25716 // CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP48]], i8 [[TMP49]] acquire acquire, align 1
25717 // CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i8, i1 } [[TMP50]], 0
25718 // CHECK-NEXT:    store i8 [[TMP51]], ptr [[UCV]], align 1
25719 // CHECK-NEXT:    [[TMP52:%.*]] = load i8, ptr [[UCE]], align 1
25720 // CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP52]] acquire, align 1
25721 // CHECK-NEXT:    [[TMP54:%.*]] = icmp ult i8 [[TMP53]], [[TMP52]]
25722 // CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i8 [[TMP52]], i8 [[TMP53]]
25723 // CHECK-NEXT:    store i8 [[TMP55]], ptr [[UCV]], align 1
25724 // CHECK-NEXT:    [[TMP56:%.*]] = load i8, ptr [[UCE]], align 1
25725 // CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP56]] acquire, align 1
25726 // CHECK-NEXT:    [[TMP58:%.*]] = icmp ugt i8 [[TMP57]], [[TMP56]]
25727 // CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i8 [[TMP56]], i8 [[TMP57]]
25728 // CHECK-NEXT:    store i8 [[TMP59]], ptr [[UCV]], align 1
25729 // CHECK-NEXT:    [[TMP60:%.*]] = load i8, ptr [[UCE]], align 1
25730 // CHECK-NEXT:    [[TMP61:%.*]] = load i8, ptr [[UCD]], align 1
25731 // CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP60]], i8 [[TMP61]] acquire acquire, align 1
25732 // CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i8, i1 } [[TMP62]], 0
25733 // CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i8, i1 } [[TMP62]], 1
25734 // CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i8 [[TMP60]], i8 [[TMP63]]
25735 // CHECK-NEXT:    store i8 [[TMP65]], ptr [[UCV]], align 1
25736 // CHECK-NEXT:    [[TMP66:%.*]] = load i8, ptr [[UCE]], align 1
25737 // CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP66]] monotonic, align 1
25738 // CHECK-NEXT:    store i8 [[TMP67]], ptr [[UCV]], align 1
25739 // CHECK-NEXT:    [[TMP68:%.*]] = load i8, ptr [[UCE]], align 1
25740 // CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP68]] monotonic, align 1
25741 // CHECK-NEXT:    store i8 [[TMP69]], ptr [[UCV]], align 1
25742 // CHECK-NEXT:    [[TMP70:%.*]] = load i8, ptr [[UCE]], align 1
25743 // CHECK-NEXT:    [[TMP71:%.*]] = load i8, ptr [[UCD]], align 1
25744 // CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP70]], i8 [[TMP71]] monotonic monotonic, align 1
25745 // CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i8, i1 } [[TMP72]], 0
25746 // CHECK-NEXT:    store i8 [[TMP73]], ptr [[UCV]], align 1
25747 // CHECK-NEXT:    [[TMP74:%.*]] = load i8, ptr [[UCE]], align 1
25748 // CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP74]] monotonic, align 1
25749 // CHECK-NEXT:    [[TMP76:%.*]] = icmp ult i8 [[TMP75]], [[TMP74]]
25750 // CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i8 [[TMP74]], i8 [[TMP75]]
25751 // CHECK-NEXT:    store i8 [[TMP77]], ptr [[UCV]], align 1
25752 // CHECK-NEXT:    [[TMP78:%.*]] = load i8, ptr [[UCE]], align 1
25753 // CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP78]] monotonic, align 1
25754 // CHECK-NEXT:    [[TMP80:%.*]] = icmp ugt i8 [[TMP79]], [[TMP78]]
25755 // CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i8 [[TMP78]], i8 [[TMP79]]
25756 // CHECK-NEXT:    store i8 [[TMP81]], ptr [[UCV]], align 1
25757 // CHECK-NEXT:    [[TMP82:%.*]] = load i8, ptr [[UCE]], align 1
25758 // CHECK-NEXT:    [[TMP83:%.*]] = load i8, ptr [[UCD]], align 1
25759 // CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP82]], i8 [[TMP83]] monotonic monotonic, align 1
25760 // CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i8, i1 } [[TMP84]], 0
25761 // CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i8, i1 } [[TMP84]], 1
25762 // CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i8 [[TMP82]], i8 [[TMP85]]
25763 // CHECK-NEXT:    store i8 [[TMP87]], ptr [[UCV]], align 1
25764 // CHECK-NEXT:    [[TMP88:%.*]] = load i8, ptr [[UCE]], align 1
25765 // CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP88]] release, align 1
25766 // CHECK-NEXT:    store i8 [[TMP89]], ptr [[UCV]], align 1
25767 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25768 // CHECK-NEXT:    [[TMP90:%.*]] = load i8, ptr [[UCE]], align 1
25769 // CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP90]] release, align 1
25770 // CHECK-NEXT:    store i8 [[TMP91]], ptr [[UCV]], align 1
25771 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25772 // CHECK-NEXT:    [[TMP92:%.*]] = load i8, ptr [[UCE]], align 1
25773 // CHECK-NEXT:    [[TMP93:%.*]] = load i8, ptr [[UCD]], align 1
25774 // CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP92]], i8 [[TMP93]] release monotonic, align 1
25775 // CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i8, i1 } [[TMP94]], 0
25776 // CHECK-NEXT:    store i8 [[TMP95]], ptr [[UCV]], align 1
25777 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25778 // CHECK-NEXT:    [[TMP96:%.*]] = load i8, ptr [[UCE]], align 1
25779 // CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP96]] release, align 1
25780 // CHECK-NEXT:    [[TMP98:%.*]] = icmp ult i8 [[TMP97]], [[TMP96]]
25781 // CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i8 [[TMP96]], i8 [[TMP97]]
25782 // CHECK-NEXT:    store i8 [[TMP99]], ptr [[UCV]], align 1
25783 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25784 // CHECK-NEXT:    [[TMP100:%.*]] = load i8, ptr [[UCE]], align 1
25785 // CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP100]] release, align 1
25786 // CHECK-NEXT:    [[TMP102:%.*]] = icmp ugt i8 [[TMP101]], [[TMP100]]
25787 // CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i8 [[TMP100]], i8 [[TMP101]]
25788 // CHECK-NEXT:    store i8 [[TMP103]], ptr [[UCV]], align 1
25789 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25790 // CHECK-NEXT:    [[TMP104:%.*]] = load i8, ptr [[UCE]], align 1
25791 // CHECK-NEXT:    [[TMP105:%.*]] = load i8, ptr [[UCD]], align 1
25792 // CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP104]], i8 [[TMP105]] release monotonic, align 1
25793 // CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i8, i1 } [[TMP106]], 0
25794 // CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i8, i1 } [[TMP106]], 1
25795 // CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i8 [[TMP104]], i8 [[TMP107]]
25796 // CHECK-NEXT:    store i8 [[TMP109]], ptr [[UCV]], align 1
25797 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25798 // CHECK-NEXT:    [[TMP110:%.*]] = load i8, ptr [[UCE]], align 1
25799 // CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP110]] seq_cst, align 1
25800 // CHECK-NEXT:    store i8 [[TMP111]], ptr [[UCV]], align 1
25801 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25802 // CHECK-NEXT:    [[TMP112:%.*]] = load i8, ptr [[UCE]], align 1
25803 // CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP112]] seq_cst, align 1
25804 // CHECK-NEXT:    store i8 [[TMP113]], ptr [[UCV]], align 1
25805 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25806 // CHECK-NEXT:    [[TMP114:%.*]] = load i8, ptr [[UCE]], align 1
25807 // CHECK-NEXT:    [[TMP115:%.*]] = load i8, ptr [[UCD]], align 1
25808 // CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP114]], i8 [[TMP115]] seq_cst seq_cst, align 1
25809 // CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i8, i1 } [[TMP116]], 0
25810 // CHECK-NEXT:    store i8 [[TMP117]], ptr [[UCV]], align 1
25811 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25812 // CHECK-NEXT:    [[TMP118:%.*]] = load i8, ptr [[UCE]], align 1
25813 // CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP118]] seq_cst, align 1
25814 // CHECK-NEXT:    [[TMP120:%.*]] = icmp ult i8 [[TMP119]], [[TMP118]]
25815 // CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i8 [[TMP118]], i8 [[TMP119]]
25816 // CHECK-NEXT:    store i8 [[TMP121]], ptr [[UCV]], align 1
25817 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25818 // CHECK-NEXT:    [[TMP122:%.*]] = load i8, ptr [[UCE]], align 1
25819 // CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP122]] seq_cst, align 1
25820 // CHECK-NEXT:    [[TMP124:%.*]] = icmp ugt i8 [[TMP123]], [[TMP122]]
25821 // CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i8 [[TMP122]], i8 [[TMP123]]
25822 // CHECK-NEXT:    store i8 [[TMP125]], ptr [[UCV]], align 1
25823 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25824 // CHECK-NEXT:    [[TMP126:%.*]] = load i8, ptr [[UCE]], align 1
25825 // CHECK-NEXT:    [[TMP127:%.*]] = load i8, ptr [[UCD]], align 1
25826 // CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP126]], i8 [[TMP127]] seq_cst seq_cst, align 1
25827 // CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i8, i1 } [[TMP128]], 0
25828 // CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i8, i1 } [[TMP128]], 1
25829 // CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i8 [[TMP126]], i8 [[TMP129]]
25830 // CHECK-NEXT:    store i8 [[TMP131]], ptr [[UCV]], align 1
25831 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25832 // CHECK-NEXT:    [[TMP132:%.*]] = load i8, ptr [[UCV]], align 1
25833 // CHECK-NEXT:    ret i8 [[TMP132]]
25834 //
25835 //
25836 // CHECK-LABEL: @sxevd(
25837 // CHECK-NEXT:  entry:
25838 // CHECK-NEXT:    [[SX:%.*]] = alloca i16, align 2
25839 // CHECK-NEXT:    [[SV:%.*]] = alloca i16, align 2
25840 // CHECK-NEXT:    [[SE:%.*]] = alloca i16, align 2
25841 // CHECK-NEXT:    [[SD:%.*]] = alloca i16, align 2
25842 // CHECK-NEXT:    [[TMP0:%.*]] = load i16, ptr [[SE]], align 2
25843 // CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP0]] monotonic, align 2
25844 // CHECK-NEXT:    store i16 [[TMP1]], ptr [[SV]], align 2
25845 // CHECK-NEXT:    [[TMP2:%.*]] = load i16, ptr [[SE]], align 2
25846 // CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP2]] monotonic, align 2
25847 // CHECK-NEXT:    store i16 [[TMP3]], ptr [[SV]], align 2
25848 // CHECK-NEXT:    [[TMP4:%.*]] = load i16, ptr [[SE]], align 2
25849 // CHECK-NEXT:    [[TMP5:%.*]] = load i16, ptr [[SD]], align 2
25850 // CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP4]], i16 [[TMP5]] monotonic monotonic, align 2
25851 // CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i16, i1 } [[TMP6]], 0
25852 // CHECK-NEXT:    store i16 [[TMP7]], ptr [[SV]], align 2
25853 // CHECK-NEXT:    [[TMP8:%.*]] = load i16, ptr [[SE]], align 2
25854 // CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP8]] monotonic, align 2
25855 // CHECK-NEXT:    [[TMP10:%.*]] = icmp slt i16 [[TMP9]], [[TMP8]]
25856 // CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i16 [[TMP8]], i16 [[TMP9]]
25857 // CHECK-NEXT:    store i16 [[TMP11]], ptr [[SV]], align 2
25858 // CHECK-NEXT:    [[TMP12:%.*]] = load i16, ptr [[SE]], align 2
25859 // CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP12]] monotonic, align 2
25860 // CHECK-NEXT:    [[TMP14:%.*]] = icmp sgt i16 [[TMP13]], [[TMP12]]
25861 // CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i16 [[TMP12]], i16 [[TMP13]]
25862 // CHECK-NEXT:    store i16 [[TMP15]], ptr [[SV]], align 2
25863 // CHECK-NEXT:    [[TMP16:%.*]] = load i16, ptr [[SE]], align 2
25864 // CHECK-NEXT:    [[TMP17:%.*]] = load i16, ptr [[SD]], align 2
25865 // CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP16]], i16 [[TMP17]] monotonic monotonic, align 2
25866 // CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i16, i1 } [[TMP18]], 0
25867 // CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i16, i1 } [[TMP18]], 1
25868 // CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i16 [[TMP16]], i16 [[TMP19]]
25869 // CHECK-NEXT:    store i16 [[TMP21]], ptr [[SV]], align 2
25870 // CHECK-NEXT:    [[TMP22:%.*]] = load i16, ptr [[SE]], align 2
25871 // CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP22]] acq_rel, align 2
25872 // CHECK-NEXT:    store i16 [[TMP23]], ptr [[SV]], align 2
25873 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25874 // CHECK-NEXT:    [[TMP24:%.*]] = load i16, ptr [[SE]], align 2
25875 // CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP24]] acq_rel, align 2
25876 // CHECK-NEXT:    store i16 [[TMP25]], ptr [[SV]], align 2
25877 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25878 // CHECK-NEXT:    [[TMP26:%.*]] = load i16, ptr [[SE]], align 2
25879 // CHECK-NEXT:    [[TMP27:%.*]] = load i16, ptr [[SD]], align 2
25880 // CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP26]], i16 [[TMP27]] acq_rel acquire, align 2
25881 // CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i16, i1 } [[TMP28]], 0
25882 // CHECK-NEXT:    store i16 [[TMP29]], ptr [[SV]], align 2
25883 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25884 // CHECK-NEXT:    [[TMP30:%.*]] = load i16, ptr [[SE]], align 2
25885 // CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP30]] acq_rel, align 2
25886 // CHECK-NEXT:    [[TMP32:%.*]] = icmp slt i16 [[TMP31]], [[TMP30]]
25887 // CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i16 [[TMP30]], i16 [[TMP31]]
25888 // CHECK-NEXT:    store i16 [[TMP33]], ptr [[SV]], align 2
25889 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25890 // CHECK-NEXT:    [[TMP34:%.*]] = load i16, ptr [[SE]], align 2
25891 // CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP34]] acq_rel, align 2
25892 // CHECK-NEXT:    [[TMP36:%.*]] = icmp sgt i16 [[TMP35]], [[TMP34]]
25893 // CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i16 [[TMP34]], i16 [[TMP35]]
25894 // CHECK-NEXT:    store i16 [[TMP37]], ptr [[SV]], align 2
25895 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25896 // CHECK-NEXT:    [[TMP38:%.*]] = load i16, ptr [[SE]], align 2
25897 // CHECK-NEXT:    [[TMP39:%.*]] = load i16, ptr [[SD]], align 2
25898 // CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP38]], i16 [[TMP39]] acq_rel acquire, align 2
25899 // CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i16, i1 } [[TMP40]], 0
25900 // CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i16, i1 } [[TMP40]], 1
25901 // CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i16 [[TMP38]], i16 [[TMP41]]
25902 // CHECK-NEXT:    store i16 [[TMP43]], ptr [[SV]], align 2
25903 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25904 // CHECK-NEXT:    [[TMP44:%.*]] = load i16, ptr [[SE]], align 2
25905 // CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP44]] acquire, align 2
25906 // CHECK-NEXT:    store i16 [[TMP45]], ptr [[SV]], align 2
25907 // CHECK-NEXT:    [[TMP46:%.*]] = load i16, ptr [[SE]], align 2
25908 // CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP46]] acquire, align 2
25909 // CHECK-NEXT:    store i16 [[TMP47]], ptr [[SV]], align 2
25910 // CHECK-NEXT:    [[TMP48:%.*]] = load i16, ptr [[SE]], align 2
25911 // CHECK-NEXT:    [[TMP49:%.*]] = load i16, ptr [[SD]], align 2
25912 // CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP48]], i16 [[TMP49]] acquire acquire, align 2
25913 // CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i16, i1 } [[TMP50]], 0
25914 // CHECK-NEXT:    store i16 [[TMP51]], ptr [[SV]], align 2
25915 // CHECK-NEXT:    [[TMP52:%.*]] = load i16, ptr [[SE]], align 2
25916 // CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP52]] acquire, align 2
25917 // CHECK-NEXT:    [[TMP54:%.*]] = icmp slt i16 [[TMP53]], [[TMP52]]
25918 // CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i16 [[TMP52]], i16 [[TMP53]]
25919 // CHECK-NEXT:    store i16 [[TMP55]], ptr [[SV]], align 2
25920 // CHECK-NEXT:    [[TMP56:%.*]] = load i16, ptr [[SE]], align 2
25921 // CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP56]] acquire, align 2
25922 // CHECK-NEXT:    [[TMP58:%.*]] = icmp sgt i16 [[TMP57]], [[TMP56]]
25923 // CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i16 [[TMP56]], i16 [[TMP57]]
25924 // CHECK-NEXT:    store i16 [[TMP59]], ptr [[SV]], align 2
25925 // CHECK-NEXT:    [[TMP60:%.*]] = load i16, ptr [[SE]], align 2
25926 // CHECK-NEXT:    [[TMP61:%.*]] = load i16, ptr [[SD]], align 2
25927 // CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP60]], i16 [[TMP61]] acquire acquire, align 2
25928 // CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i16, i1 } [[TMP62]], 0
25929 // CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i16, i1 } [[TMP62]], 1
25930 // CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i16 [[TMP60]], i16 [[TMP63]]
25931 // CHECK-NEXT:    store i16 [[TMP65]], ptr [[SV]], align 2
25932 // CHECK-NEXT:    [[TMP66:%.*]] = load i16, ptr [[SE]], align 2
25933 // CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP66]] monotonic, align 2
25934 // CHECK-NEXT:    store i16 [[TMP67]], ptr [[SV]], align 2
25935 // CHECK-NEXT:    [[TMP68:%.*]] = load i16, ptr [[SE]], align 2
25936 // CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP68]] monotonic, align 2
25937 // CHECK-NEXT:    store i16 [[TMP69]], ptr [[SV]], align 2
25938 // CHECK-NEXT:    [[TMP70:%.*]] = load i16, ptr [[SE]], align 2
25939 // CHECK-NEXT:    [[TMP71:%.*]] = load i16, ptr [[SD]], align 2
25940 // CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP70]], i16 [[TMP71]] monotonic monotonic, align 2
25941 // CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i16, i1 } [[TMP72]], 0
25942 // CHECK-NEXT:    store i16 [[TMP73]], ptr [[SV]], align 2
25943 // CHECK-NEXT:    [[TMP74:%.*]] = load i16, ptr [[SE]], align 2
25944 // CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP74]] monotonic, align 2
25945 // CHECK-NEXT:    [[TMP76:%.*]] = icmp slt i16 [[TMP75]], [[TMP74]]
25946 // CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i16 [[TMP74]], i16 [[TMP75]]
25947 // CHECK-NEXT:    store i16 [[TMP77]], ptr [[SV]], align 2
25948 // CHECK-NEXT:    [[TMP78:%.*]] = load i16, ptr [[SE]], align 2
25949 // CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP78]] monotonic, align 2
25950 // CHECK-NEXT:    [[TMP80:%.*]] = icmp sgt i16 [[TMP79]], [[TMP78]]
25951 // CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i16 [[TMP78]], i16 [[TMP79]]
25952 // CHECK-NEXT:    store i16 [[TMP81]], ptr [[SV]], align 2
25953 // CHECK-NEXT:    [[TMP82:%.*]] = load i16, ptr [[SE]], align 2
25954 // CHECK-NEXT:    [[TMP83:%.*]] = load i16, ptr [[SD]], align 2
25955 // CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP82]], i16 [[TMP83]] monotonic monotonic, align 2
25956 // CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i16, i1 } [[TMP84]], 0
25957 // CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i16, i1 } [[TMP84]], 1
25958 // CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i16 [[TMP82]], i16 [[TMP85]]
25959 // CHECK-NEXT:    store i16 [[TMP87]], ptr [[SV]], align 2
25960 // CHECK-NEXT:    [[TMP88:%.*]] = load i16, ptr [[SE]], align 2
25961 // CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP88]] release, align 2
25962 // CHECK-NEXT:    store i16 [[TMP89]], ptr [[SV]], align 2
25963 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25964 // CHECK-NEXT:    [[TMP90:%.*]] = load i16, ptr [[SE]], align 2
25965 // CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP90]] release, align 2
25966 // CHECK-NEXT:    store i16 [[TMP91]], ptr [[SV]], align 2
25967 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25968 // CHECK-NEXT:    [[TMP92:%.*]] = load i16, ptr [[SE]], align 2
25969 // CHECK-NEXT:    [[TMP93:%.*]] = load i16, ptr [[SD]], align 2
25970 // CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP92]], i16 [[TMP93]] release monotonic, align 2
25971 // CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i16, i1 } [[TMP94]], 0
25972 // CHECK-NEXT:    store i16 [[TMP95]], ptr [[SV]], align 2
25973 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25974 // CHECK-NEXT:    [[TMP96:%.*]] = load i16, ptr [[SE]], align 2
25975 // CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP96]] release, align 2
25976 // CHECK-NEXT:    [[TMP98:%.*]] = icmp slt i16 [[TMP97]], [[TMP96]]
25977 // CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i16 [[TMP96]], i16 [[TMP97]]
25978 // CHECK-NEXT:    store i16 [[TMP99]], ptr [[SV]], align 2
25979 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25980 // CHECK-NEXT:    [[TMP100:%.*]] = load i16, ptr [[SE]], align 2
25981 // CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP100]] release, align 2
25982 // CHECK-NEXT:    [[TMP102:%.*]] = icmp sgt i16 [[TMP101]], [[TMP100]]
25983 // CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i16 [[TMP100]], i16 [[TMP101]]
25984 // CHECK-NEXT:    store i16 [[TMP103]], ptr [[SV]], align 2
25985 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25986 // CHECK-NEXT:    [[TMP104:%.*]] = load i16, ptr [[SE]], align 2
25987 // CHECK-NEXT:    [[TMP105:%.*]] = load i16, ptr [[SD]], align 2
25988 // CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP104]], i16 [[TMP105]] release monotonic, align 2
25989 // CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i16, i1 } [[TMP106]], 0
25990 // CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i16, i1 } [[TMP106]], 1
25991 // CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i16 [[TMP104]], i16 [[TMP107]]
25992 // CHECK-NEXT:    store i16 [[TMP109]], ptr [[SV]], align 2
25993 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25994 // CHECK-NEXT:    [[TMP110:%.*]] = load i16, ptr [[SE]], align 2
25995 // CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP110]] seq_cst, align 2
25996 // CHECK-NEXT:    store i16 [[TMP111]], ptr [[SV]], align 2
25997 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
25998 // CHECK-NEXT:    [[TMP112:%.*]] = load i16, ptr [[SE]], align 2
25999 // CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP112]] seq_cst, align 2
26000 // CHECK-NEXT:    store i16 [[TMP113]], ptr [[SV]], align 2
26001 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26002 // CHECK-NEXT:    [[TMP114:%.*]] = load i16, ptr [[SE]], align 2
26003 // CHECK-NEXT:    [[TMP115:%.*]] = load i16, ptr [[SD]], align 2
26004 // CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP114]], i16 [[TMP115]] seq_cst seq_cst, align 2
26005 // CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i16, i1 } [[TMP116]], 0
26006 // CHECK-NEXT:    store i16 [[TMP117]], ptr [[SV]], align 2
26007 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26008 // CHECK-NEXT:    [[TMP118:%.*]] = load i16, ptr [[SE]], align 2
26009 // CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP118]] seq_cst, align 2
26010 // CHECK-NEXT:    [[TMP120:%.*]] = icmp slt i16 [[TMP119]], [[TMP118]]
26011 // CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i16 [[TMP118]], i16 [[TMP119]]
26012 // CHECK-NEXT:    store i16 [[TMP121]], ptr [[SV]], align 2
26013 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26014 // CHECK-NEXT:    [[TMP122:%.*]] = load i16, ptr [[SE]], align 2
26015 // CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP122]] seq_cst, align 2
26016 // CHECK-NEXT:    [[TMP124:%.*]] = icmp sgt i16 [[TMP123]], [[TMP122]]
26017 // CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i16 [[TMP122]], i16 [[TMP123]]
26018 // CHECK-NEXT:    store i16 [[TMP125]], ptr [[SV]], align 2
26019 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26020 // CHECK-NEXT:    [[TMP126:%.*]] = load i16, ptr [[SE]], align 2
26021 // CHECK-NEXT:    [[TMP127:%.*]] = load i16, ptr [[SD]], align 2
26022 // CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP126]], i16 [[TMP127]] seq_cst seq_cst, align 2
26023 // CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i16, i1 } [[TMP128]], 0
26024 // CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i16, i1 } [[TMP128]], 1
26025 // CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i16 [[TMP126]], i16 [[TMP129]]
26026 // CHECK-NEXT:    store i16 [[TMP131]], ptr [[SV]], align 2
26027 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26028 // CHECK-NEXT:    [[TMP132:%.*]] = load i16, ptr [[SV]], align 2
26029 // CHECK-NEXT:    ret i16 [[TMP132]]
26030 //
26031 //
26032 // CHECK-LABEL: @usxevd(
26033 // CHECK-NEXT:  entry:
26034 // CHECK-NEXT:    [[USX:%.*]] = alloca i16, align 2
26035 // CHECK-NEXT:    [[USV:%.*]] = alloca i16, align 2
26036 // CHECK-NEXT:    [[USE:%.*]] = alloca i16, align 2
26037 // CHECK-NEXT:    [[USD:%.*]] = alloca i16, align 2
26038 // CHECK-NEXT:    [[TMP0:%.*]] = load i16, ptr [[USE]], align 2
26039 // CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP0]] monotonic, align 2
26040 // CHECK-NEXT:    store i16 [[TMP1]], ptr [[USV]], align 2
26041 // CHECK-NEXT:    [[TMP2:%.*]] = load i16, ptr [[USE]], align 2
26042 // CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP2]] monotonic, align 2
26043 // CHECK-NEXT:    store i16 [[TMP3]], ptr [[USV]], align 2
26044 // CHECK-NEXT:    [[TMP4:%.*]] = load i16, ptr [[USE]], align 2
26045 // CHECK-NEXT:    [[TMP5:%.*]] = load i16, ptr [[USD]], align 2
26046 // CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP4]], i16 [[TMP5]] monotonic monotonic, align 2
26047 // CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i16, i1 } [[TMP6]], 0
26048 // CHECK-NEXT:    store i16 [[TMP7]], ptr [[USV]], align 2
26049 // CHECK-NEXT:    [[TMP8:%.*]] = load i16, ptr [[USE]], align 2
26050 // CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP8]] monotonic, align 2
26051 // CHECK-NEXT:    [[TMP10:%.*]] = icmp ult i16 [[TMP9]], [[TMP8]]
26052 // CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i16 [[TMP8]], i16 [[TMP9]]
26053 // CHECK-NEXT:    store i16 [[TMP11]], ptr [[USV]], align 2
26054 // CHECK-NEXT:    [[TMP12:%.*]] = load i16, ptr [[USE]], align 2
26055 // CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP12]] monotonic, align 2
26056 // CHECK-NEXT:    [[TMP14:%.*]] = icmp ugt i16 [[TMP13]], [[TMP12]]
26057 // CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i16 [[TMP12]], i16 [[TMP13]]
26058 // CHECK-NEXT:    store i16 [[TMP15]], ptr [[USV]], align 2
26059 // CHECK-NEXT:    [[TMP16:%.*]] = load i16, ptr [[USE]], align 2
26060 // CHECK-NEXT:    [[TMP17:%.*]] = load i16, ptr [[USD]], align 2
26061 // CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP16]], i16 [[TMP17]] monotonic monotonic, align 2
26062 // CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i16, i1 } [[TMP18]], 0
26063 // CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i16, i1 } [[TMP18]], 1
26064 // CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i16 [[TMP16]], i16 [[TMP19]]
26065 // CHECK-NEXT:    store i16 [[TMP21]], ptr [[USV]], align 2
26066 // CHECK-NEXT:    [[TMP22:%.*]] = load i16, ptr [[USE]], align 2
26067 // CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP22]] acq_rel, align 2
26068 // CHECK-NEXT:    store i16 [[TMP23]], ptr [[USV]], align 2
26069 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26070 // CHECK-NEXT:    [[TMP24:%.*]] = load i16, ptr [[USE]], align 2
26071 // CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP24]] acq_rel, align 2
26072 // CHECK-NEXT:    store i16 [[TMP25]], ptr [[USV]], align 2
26073 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26074 // CHECK-NEXT:    [[TMP26:%.*]] = load i16, ptr [[USE]], align 2
26075 // CHECK-NEXT:    [[TMP27:%.*]] = load i16, ptr [[USD]], align 2
26076 // CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP26]], i16 [[TMP27]] acq_rel acquire, align 2
26077 // CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i16, i1 } [[TMP28]], 0
26078 // CHECK-NEXT:    store i16 [[TMP29]], ptr [[USV]], align 2
26079 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26080 // CHECK-NEXT:    [[TMP30:%.*]] = load i16, ptr [[USE]], align 2
26081 // CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP30]] acq_rel, align 2
26082 // CHECK-NEXT:    [[TMP32:%.*]] = icmp ult i16 [[TMP31]], [[TMP30]]
26083 // CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i16 [[TMP30]], i16 [[TMP31]]
26084 // CHECK-NEXT:    store i16 [[TMP33]], ptr [[USV]], align 2
26085 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26086 // CHECK-NEXT:    [[TMP34:%.*]] = load i16, ptr [[USE]], align 2
26087 // CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP34]] acq_rel, align 2
26088 // CHECK-NEXT:    [[TMP36:%.*]] = icmp ugt i16 [[TMP35]], [[TMP34]]
26089 // CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i16 [[TMP34]], i16 [[TMP35]]
26090 // CHECK-NEXT:    store i16 [[TMP37]], ptr [[USV]], align 2
26091 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26092 // CHECK-NEXT:    [[TMP38:%.*]] = load i16, ptr [[USE]], align 2
26093 // CHECK-NEXT:    [[TMP39:%.*]] = load i16, ptr [[USD]], align 2
26094 // CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP38]], i16 [[TMP39]] acq_rel acquire, align 2
26095 // CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i16, i1 } [[TMP40]], 0
26096 // CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i16, i1 } [[TMP40]], 1
26097 // CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i16 [[TMP38]], i16 [[TMP41]]
26098 // CHECK-NEXT:    store i16 [[TMP43]], ptr [[USV]], align 2
26099 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26100 // CHECK-NEXT:    [[TMP44:%.*]] = load i16, ptr [[USE]], align 2
26101 // CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP44]] acquire, align 2
26102 // CHECK-NEXT:    store i16 [[TMP45]], ptr [[USV]], align 2
26103 // CHECK-NEXT:    [[TMP46:%.*]] = load i16, ptr [[USE]], align 2
26104 // CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP46]] acquire, align 2
26105 // CHECK-NEXT:    store i16 [[TMP47]], ptr [[USV]], align 2
26106 // CHECK-NEXT:    [[TMP48:%.*]] = load i16, ptr [[USE]], align 2
26107 // CHECK-NEXT:    [[TMP49:%.*]] = load i16, ptr [[USD]], align 2
26108 // CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP48]], i16 [[TMP49]] acquire acquire, align 2
26109 // CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i16, i1 } [[TMP50]], 0
26110 // CHECK-NEXT:    store i16 [[TMP51]], ptr [[USV]], align 2
26111 // CHECK-NEXT:    [[TMP52:%.*]] = load i16, ptr [[USE]], align 2
26112 // CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP52]] acquire, align 2
26113 // CHECK-NEXT:    [[TMP54:%.*]] = icmp ult i16 [[TMP53]], [[TMP52]]
26114 // CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i16 [[TMP52]], i16 [[TMP53]]
26115 // CHECK-NEXT:    store i16 [[TMP55]], ptr [[USV]], align 2
26116 // CHECK-NEXT:    [[TMP56:%.*]] = load i16, ptr [[USE]], align 2
26117 // CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP56]] acquire, align 2
26118 // CHECK-NEXT:    [[TMP58:%.*]] = icmp ugt i16 [[TMP57]], [[TMP56]]
26119 // CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i16 [[TMP56]], i16 [[TMP57]]
26120 // CHECK-NEXT:    store i16 [[TMP59]], ptr [[USV]], align 2
26121 // CHECK-NEXT:    [[TMP60:%.*]] = load i16, ptr [[USE]], align 2
26122 // CHECK-NEXT:    [[TMP61:%.*]] = load i16, ptr [[USD]], align 2
26123 // CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP60]], i16 [[TMP61]] acquire acquire, align 2
26124 // CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i16, i1 } [[TMP62]], 0
26125 // CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i16, i1 } [[TMP62]], 1
26126 // CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i16 [[TMP60]], i16 [[TMP63]]
26127 // CHECK-NEXT:    store i16 [[TMP65]], ptr [[USV]], align 2
26128 // CHECK-NEXT:    [[TMP66:%.*]] = load i16, ptr [[USE]], align 2
26129 // CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP66]] monotonic, align 2
26130 // CHECK-NEXT:    store i16 [[TMP67]], ptr [[USV]], align 2
26131 // CHECK-NEXT:    [[TMP68:%.*]] = load i16, ptr [[USE]], align 2
26132 // CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP68]] monotonic, align 2
26133 // CHECK-NEXT:    store i16 [[TMP69]], ptr [[USV]], align 2
26134 // CHECK-NEXT:    [[TMP70:%.*]] = load i16, ptr [[USE]], align 2
26135 // CHECK-NEXT:    [[TMP71:%.*]] = load i16, ptr [[USD]], align 2
26136 // CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP70]], i16 [[TMP71]] monotonic monotonic, align 2
26137 // CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i16, i1 } [[TMP72]], 0
26138 // CHECK-NEXT:    store i16 [[TMP73]], ptr [[USV]], align 2
26139 // CHECK-NEXT:    [[TMP74:%.*]] = load i16, ptr [[USE]], align 2
26140 // CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP74]] monotonic, align 2
26141 // CHECK-NEXT:    [[TMP76:%.*]] = icmp ult i16 [[TMP75]], [[TMP74]]
26142 // CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i16 [[TMP74]], i16 [[TMP75]]
26143 // CHECK-NEXT:    store i16 [[TMP77]], ptr [[USV]], align 2
26144 // CHECK-NEXT:    [[TMP78:%.*]] = load i16, ptr [[USE]], align 2
26145 // CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP78]] monotonic, align 2
26146 // CHECK-NEXT:    [[TMP80:%.*]] = icmp ugt i16 [[TMP79]], [[TMP78]]
26147 // CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i16 [[TMP78]], i16 [[TMP79]]
26148 // CHECK-NEXT:    store i16 [[TMP81]], ptr [[USV]], align 2
26149 // CHECK-NEXT:    [[TMP82:%.*]] = load i16, ptr [[USE]], align 2
26150 // CHECK-NEXT:    [[TMP83:%.*]] = load i16, ptr [[USD]], align 2
26151 // CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP82]], i16 [[TMP83]] monotonic monotonic, align 2
26152 // CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i16, i1 } [[TMP84]], 0
26153 // CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i16, i1 } [[TMP84]], 1
26154 // CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i16 [[TMP82]], i16 [[TMP85]]
26155 // CHECK-NEXT:    store i16 [[TMP87]], ptr [[USV]], align 2
26156 // CHECK-NEXT:    [[TMP88:%.*]] = load i16, ptr [[USE]], align 2
26157 // CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP88]] release, align 2
26158 // CHECK-NEXT:    store i16 [[TMP89]], ptr [[USV]], align 2
26159 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26160 // CHECK-NEXT:    [[TMP90:%.*]] = load i16, ptr [[USE]], align 2
26161 // CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP90]] release, align 2
26162 // CHECK-NEXT:    store i16 [[TMP91]], ptr [[USV]], align 2
26163 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26164 // CHECK-NEXT:    [[TMP92:%.*]] = load i16, ptr [[USE]], align 2
26165 // CHECK-NEXT:    [[TMP93:%.*]] = load i16, ptr [[USD]], align 2
26166 // CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP92]], i16 [[TMP93]] release monotonic, align 2
26167 // CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i16, i1 } [[TMP94]], 0
26168 // CHECK-NEXT:    store i16 [[TMP95]], ptr [[USV]], align 2
26169 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26170 // CHECK-NEXT:    [[TMP96:%.*]] = load i16, ptr [[USE]], align 2
26171 // CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP96]] release, align 2
26172 // CHECK-NEXT:    [[TMP98:%.*]] = icmp ult i16 [[TMP97]], [[TMP96]]
26173 // CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i16 [[TMP96]], i16 [[TMP97]]
26174 // CHECK-NEXT:    store i16 [[TMP99]], ptr [[USV]], align 2
26175 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26176 // CHECK-NEXT:    [[TMP100:%.*]] = load i16, ptr [[USE]], align 2
26177 // CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP100]] release, align 2
26178 // CHECK-NEXT:    [[TMP102:%.*]] = icmp ugt i16 [[TMP101]], [[TMP100]]
26179 // CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i16 [[TMP100]], i16 [[TMP101]]
26180 // CHECK-NEXT:    store i16 [[TMP103]], ptr [[USV]], align 2
26181 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26182 // CHECK-NEXT:    [[TMP104:%.*]] = load i16, ptr [[USE]], align 2
26183 // CHECK-NEXT:    [[TMP105:%.*]] = load i16, ptr [[USD]], align 2
26184 // CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP104]], i16 [[TMP105]] release monotonic, align 2
26185 // CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i16, i1 } [[TMP106]], 0
26186 // CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i16, i1 } [[TMP106]], 1
26187 // CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i16 [[TMP104]], i16 [[TMP107]]
26188 // CHECK-NEXT:    store i16 [[TMP109]], ptr [[USV]], align 2
26189 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26190 // CHECK-NEXT:    [[TMP110:%.*]] = load i16, ptr [[USE]], align 2
26191 // CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP110]] seq_cst, align 2
26192 // CHECK-NEXT:    store i16 [[TMP111]], ptr [[USV]], align 2
26193 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26194 // CHECK-NEXT:    [[TMP112:%.*]] = load i16, ptr [[USE]], align 2
26195 // CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP112]] seq_cst, align 2
26196 // CHECK-NEXT:    store i16 [[TMP113]], ptr [[USV]], align 2
26197 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26198 // CHECK-NEXT:    [[TMP114:%.*]] = load i16, ptr [[USE]], align 2
26199 // CHECK-NEXT:    [[TMP115:%.*]] = load i16, ptr [[USD]], align 2
26200 // CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP114]], i16 [[TMP115]] seq_cst seq_cst, align 2
26201 // CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i16, i1 } [[TMP116]], 0
26202 // CHECK-NEXT:    store i16 [[TMP117]], ptr [[USV]], align 2
26203 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26204 // CHECK-NEXT:    [[TMP118:%.*]] = load i16, ptr [[USE]], align 2
26205 // CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP118]] seq_cst, align 2
26206 // CHECK-NEXT:    [[TMP120:%.*]] = icmp ult i16 [[TMP119]], [[TMP118]]
26207 // CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i16 [[TMP118]], i16 [[TMP119]]
26208 // CHECK-NEXT:    store i16 [[TMP121]], ptr [[USV]], align 2
26209 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26210 // CHECK-NEXT:    [[TMP122:%.*]] = load i16, ptr [[USE]], align 2
26211 // CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP122]] seq_cst, align 2
26212 // CHECK-NEXT:    [[TMP124:%.*]] = icmp ugt i16 [[TMP123]], [[TMP122]]
26213 // CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i16 [[TMP122]], i16 [[TMP123]]
26214 // CHECK-NEXT:    store i16 [[TMP125]], ptr [[USV]], align 2
26215 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26216 // CHECK-NEXT:    [[TMP126:%.*]] = load i16, ptr [[USE]], align 2
26217 // CHECK-NEXT:    [[TMP127:%.*]] = load i16, ptr [[USD]], align 2
26218 // CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP126]], i16 [[TMP127]] seq_cst seq_cst, align 2
26219 // CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i16, i1 } [[TMP128]], 0
26220 // CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i16, i1 } [[TMP128]], 1
26221 // CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i16 [[TMP126]], i16 [[TMP129]]
26222 // CHECK-NEXT:    store i16 [[TMP131]], ptr [[USV]], align 2
26223 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26224 // CHECK-NEXT:    [[TMP132:%.*]] = load i16, ptr [[USV]], align 2
26225 // CHECK-NEXT:    ret i16 [[TMP132]]
26226 //
26227 //
26228 // CHECK-LABEL: @ixevd(
26229 // CHECK-NEXT:  entry:
26230 // CHECK-NEXT:    [[IX:%.*]] = alloca i32, align 4
26231 // CHECK-NEXT:    [[IV:%.*]] = alloca i32, align 4
26232 // CHECK-NEXT:    [[IE:%.*]] = alloca i32, align 4
26233 // CHECK-NEXT:    [[ID:%.*]] = alloca i32, align 4
26234 // CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[IE]], align 4
26235 // CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP0]] monotonic, align 4
26236 // CHECK-NEXT:    store i32 [[TMP1]], ptr [[IV]], align 4
26237 // CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[IE]], align 4
26238 // CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2]] monotonic, align 4
26239 // CHECK-NEXT:    store i32 [[TMP3]], ptr [[IV]], align 4
26240 // CHECK-NEXT:    [[TMP4:%.*]] = load i32, ptr [[IE]], align 4
26241 // CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[ID]], align 4
26242 // CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP4]], i32 [[TMP5]] monotonic monotonic, align 4
26243 // CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0
26244 // CHECK-NEXT:    store i32 [[TMP7]], ptr [[IV]], align 4
26245 // CHECK-NEXT:    [[TMP8:%.*]] = load i32, ptr [[IE]], align 4
26246 // CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP8]] monotonic, align 4
26247 // CHECK-NEXT:    [[TMP10:%.*]] = icmp slt i32 [[TMP9]], [[TMP8]]
26248 // CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i32 [[TMP8]], i32 [[TMP9]]
26249 // CHECK-NEXT:    store i32 [[TMP11]], ptr [[IV]], align 4
26250 // CHECK-NEXT:    [[TMP12:%.*]] = load i32, ptr [[IE]], align 4
26251 // CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP12]] monotonic, align 4
26252 // CHECK-NEXT:    [[TMP14:%.*]] = icmp sgt i32 [[TMP13]], [[TMP12]]
26253 // CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[TMP12]], i32 [[TMP13]]
26254 // CHECK-NEXT:    store i32 [[TMP15]], ptr [[IV]], align 4
26255 // CHECK-NEXT:    [[TMP16:%.*]] = load i32, ptr [[IE]], align 4
26256 // CHECK-NEXT:    [[TMP17:%.*]] = load i32, ptr [[ID]], align 4
26257 // CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP16]], i32 [[TMP17]] monotonic monotonic, align 4
26258 // CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i32, i1 } [[TMP18]], 0
26259 // CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i32, i1 } [[TMP18]], 1
26260 // CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i32 [[TMP16]], i32 [[TMP19]]
26261 // CHECK-NEXT:    store i32 [[TMP21]], ptr [[IV]], align 4
26262 // CHECK-NEXT:    [[TMP22:%.*]] = load i32, ptr [[IE]], align 4
26263 // CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP22]] acq_rel, align 4
26264 // CHECK-NEXT:    store i32 [[TMP23]], ptr [[IV]], align 4
26265 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26266 // CHECK-NEXT:    [[TMP24:%.*]] = load i32, ptr [[IE]], align 4
26267 // CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP24]] acq_rel, align 4
26268 // CHECK-NEXT:    store i32 [[TMP25]], ptr [[IV]], align 4
26269 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26270 // CHECK-NEXT:    [[TMP26:%.*]] = load i32, ptr [[IE]], align 4
26271 // CHECK-NEXT:    [[TMP27:%.*]] = load i32, ptr [[ID]], align 4
26272 // CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP26]], i32 [[TMP27]] acq_rel acquire, align 4
26273 // CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i32, i1 } [[TMP28]], 0
26274 // CHECK-NEXT:    store i32 [[TMP29]], ptr [[IV]], align 4
26275 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26276 // CHECK-NEXT:    [[TMP30:%.*]] = load i32, ptr [[IE]], align 4
26277 // CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP30]] acq_rel, align 4
26278 // CHECK-NEXT:    [[TMP32:%.*]] = icmp slt i32 [[TMP31]], [[TMP30]]
26279 // CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i32 [[TMP30]], i32 [[TMP31]]
26280 // CHECK-NEXT:    store i32 [[TMP33]], ptr [[IV]], align 4
26281 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26282 // CHECK-NEXT:    [[TMP34:%.*]] = load i32, ptr [[IE]], align 4
26283 // CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP34]] acq_rel, align 4
26284 // CHECK-NEXT:    [[TMP36:%.*]] = icmp sgt i32 [[TMP35]], [[TMP34]]
26285 // CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i32 [[TMP34]], i32 [[TMP35]]
26286 // CHECK-NEXT:    store i32 [[TMP37]], ptr [[IV]], align 4
26287 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26288 // CHECK-NEXT:    [[TMP38:%.*]] = load i32, ptr [[IE]], align 4
26289 // CHECK-NEXT:    [[TMP39:%.*]] = load i32, ptr [[ID]], align 4
26290 // CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP38]], i32 [[TMP39]] acq_rel acquire, align 4
26291 // CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i32, i1 } [[TMP40]], 0
26292 // CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i32, i1 } [[TMP40]], 1
26293 // CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP38]], i32 [[TMP41]]
26294 // CHECK-NEXT:    store i32 [[TMP43]], ptr [[IV]], align 4
26295 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26296 // CHECK-NEXT:    [[TMP44:%.*]] = load i32, ptr [[IE]], align 4
26297 // CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP44]] acquire, align 4
26298 // CHECK-NEXT:    store i32 [[TMP45]], ptr [[IV]], align 4
26299 // CHECK-NEXT:    [[TMP46:%.*]] = load i32, ptr [[IE]], align 4
26300 // CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP46]] acquire, align 4
26301 // CHECK-NEXT:    store i32 [[TMP47]], ptr [[IV]], align 4
26302 // CHECK-NEXT:    [[TMP48:%.*]] = load i32, ptr [[IE]], align 4
26303 // CHECK-NEXT:    [[TMP49:%.*]] = load i32, ptr [[ID]], align 4
26304 // CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP48]], i32 [[TMP49]] acquire acquire, align 4
26305 // CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i32, i1 } [[TMP50]], 0
26306 // CHECK-NEXT:    store i32 [[TMP51]], ptr [[IV]], align 4
26307 // CHECK-NEXT:    [[TMP52:%.*]] = load i32, ptr [[IE]], align 4
26308 // CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP52]] acquire, align 4
26309 // CHECK-NEXT:    [[TMP54:%.*]] = icmp slt i32 [[TMP53]], [[TMP52]]
26310 // CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i32 [[TMP52]], i32 [[TMP53]]
26311 // CHECK-NEXT:    store i32 [[TMP55]], ptr [[IV]], align 4
26312 // CHECK-NEXT:    [[TMP56:%.*]] = load i32, ptr [[IE]], align 4
26313 // CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP56]] acquire, align 4
26314 // CHECK-NEXT:    [[TMP58:%.*]] = icmp sgt i32 [[TMP57]], [[TMP56]]
26315 // CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i32 [[TMP56]], i32 [[TMP57]]
26316 // CHECK-NEXT:    store i32 [[TMP59]], ptr [[IV]], align 4
26317 // CHECK-NEXT:    [[TMP60:%.*]] = load i32, ptr [[IE]], align 4
26318 // CHECK-NEXT:    [[TMP61:%.*]] = load i32, ptr [[ID]], align 4
26319 // CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP60]], i32 [[TMP61]] acquire acquire, align 4
26320 // CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i32, i1 } [[TMP62]], 0
26321 // CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i32, i1 } [[TMP62]], 1
26322 // CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i32 [[TMP60]], i32 [[TMP63]]
26323 // CHECK-NEXT:    store i32 [[TMP65]], ptr [[IV]], align 4
26324 // CHECK-NEXT:    [[TMP66:%.*]] = load i32, ptr [[IE]], align 4
26325 // CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP66]] monotonic, align 4
26326 // CHECK-NEXT:    store i32 [[TMP67]], ptr [[IV]], align 4
26327 // CHECK-NEXT:    [[TMP68:%.*]] = load i32, ptr [[IE]], align 4
26328 // CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP68]] monotonic, align 4
26329 // CHECK-NEXT:    store i32 [[TMP69]], ptr [[IV]], align 4
26330 // CHECK-NEXT:    [[TMP70:%.*]] = load i32, ptr [[IE]], align 4
26331 // CHECK-NEXT:    [[TMP71:%.*]] = load i32, ptr [[ID]], align 4
26332 // CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP70]], i32 [[TMP71]] monotonic monotonic, align 4
26333 // CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i32, i1 } [[TMP72]], 0
26334 // CHECK-NEXT:    store i32 [[TMP73]], ptr [[IV]], align 4
26335 // CHECK-NEXT:    [[TMP74:%.*]] = load i32, ptr [[IE]], align 4
26336 // CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP74]] monotonic, align 4
26337 // CHECK-NEXT:    [[TMP76:%.*]] = icmp slt i32 [[TMP75]], [[TMP74]]
26338 // CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i32 [[TMP74]], i32 [[TMP75]]
26339 // CHECK-NEXT:    store i32 [[TMP77]], ptr [[IV]], align 4
26340 // CHECK-NEXT:    [[TMP78:%.*]] = load i32, ptr [[IE]], align 4
26341 // CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP78]] monotonic, align 4
26342 // CHECK-NEXT:    [[TMP80:%.*]] = icmp sgt i32 [[TMP79]], [[TMP78]]
26343 // CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i32 [[TMP78]], i32 [[TMP79]]
26344 // CHECK-NEXT:    store i32 [[TMP81]], ptr [[IV]], align 4
26345 // CHECK-NEXT:    [[TMP82:%.*]] = load i32, ptr [[IE]], align 4
26346 // CHECK-NEXT:    [[TMP83:%.*]] = load i32, ptr [[ID]], align 4
26347 // CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP82]], i32 [[TMP83]] monotonic monotonic, align 4
26348 // CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i32, i1 } [[TMP84]], 0
26349 // CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i32, i1 } [[TMP84]], 1
26350 // CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i32 [[TMP82]], i32 [[TMP85]]
26351 // CHECK-NEXT:    store i32 [[TMP87]], ptr [[IV]], align 4
26352 // CHECK-NEXT:    [[TMP88:%.*]] = load i32, ptr [[IE]], align 4
26353 // CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP88]] release, align 4
26354 // CHECK-NEXT:    store i32 [[TMP89]], ptr [[IV]], align 4
26355 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26356 // CHECK-NEXT:    [[TMP90:%.*]] = load i32, ptr [[IE]], align 4
26357 // CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP90]] release, align 4
26358 // CHECK-NEXT:    store i32 [[TMP91]], ptr [[IV]], align 4
26359 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26360 // CHECK-NEXT:    [[TMP92:%.*]] = load i32, ptr [[IE]], align 4
26361 // CHECK-NEXT:    [[TMP93:%.*]] = load i32, ptr [[ID]], align 4
26362 // CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP92]], i32 [[TMP93]] release monotonic, align 4
26363 // CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i32, i1 } [[TMP94]], 0
26364 // CHECK-NEXT:    store i32 [[TMP95]], ptr [[IV]], align 4
26365 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26366 // CHECK-NEXT:    [[TMP96:%.*]] = load i32, ptr [[IE]], align 4
26367 // CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP96]] release, align 4
26368 // CHECK-NEXT:    [[TMP98:%.*]] = icmp slt i32 [[TMP97]], [[TMP96]]
26369 // CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i32 [[TMP96]], i32 [[TMP97]]
26370 // CHECK-NEXT:    store i32 [[TMP99]], ptr [[IV]], align 4
26371 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26372 // CHECK-NEXT:    [[TMP100:%.*]] = load i32, ptr [[IE]], align 4
26373 // CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP100]] release, align 4
26374 // CHECK-NEXT:    [[TMP102:%.*]] = icmp sgt i32 [[TMP101]], [[TMP100]]
26375 // CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i32 [[TMP100]], i32 [[TMP101]]
26376 // CHECK-NEXT:    store i32 [[TMP103]], ptr [[IV]], align 4
26377 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26378 // CHECK-NEXT:    [[TMP104:%.*]] = load i32, ptr [[IE]], align 4
26379 // CHECK-NEXT:    [[TMP105:%.*]] = load i32, ptr [[ID]], align 4
26380 // CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP104]], i32 [[TMP105]] release monotonic, align 4
26381 // CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i32, i1 } [[TMP106]], 0
26382 // CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i32, i1 } [[TMP106]], 1
26383 // CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i32 [[TMP104]], i32 [[TMP107]]
26384 // CHECK-NEXT:    store i32 [[TMP109]], ptr [[IV]], align 4
26385 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26386 // CHECK-NEXT:    [[TMP110:%.*]] = load i32, ptr [[IE]], align 4
26387 // CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP110]] seq_cst, align 4
26388 // CHECK-NEXT:    store i32 [[TMP111]], ptr [[IV]], align 4
26389 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26390 // CHECK-NEXT:    [[TMP112:%.*]] = load i32, ptr [[IE]], align 4
26391 // CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP112]] seq_cst, align 4
26392 // CHECK-NEXT:    store i32 [[TMP113]], ptr [[IV]], align 4
26393 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26394 // CHECK-NEXT:    [[TMP114:%.*]] = load i32, ptr [[IE]], align 4
26395 // CHECK-NEXT:    [[TMP115:%.*]] = load i32, ptr [[ID]], align 4
26396 // CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP114]], i32 [[TMP115]] seq_cst seq_cst, align 4
26397 // CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i32, i1 } [[TMP116]], 0
26398 // CHECK-NEXT:    store i32 [[TMP117]], ptr [[IV]], align 4
26399 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26400 // CHECK-NEXT:    [[TMP118:%.*]] = load i32, ptr [[IE]], align 4
26401 // CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP118]] seq_cst, align 4
26402 // CHECK-NEXT:    [[TMP120:%.*]] = icmp slt i32 [[TMP119]], [[TMP118]]
26403 // CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i32 [[TMP118]], i32 [[TMP119]]
26404 // CHECK-NEXT:    store i32 [[TMP121]], ptr [[IV]], align 4
26405 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26406 // CHECK-NEXT:    [[TMP122:%.*]] = load i32, ptr [[IE]], align 4
26407 // CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP122]] seq_cst, align 4
26408 // CHECK-NEXT:    [[TMP124:%.*]] = icmp sgt i32 [[TMP123]], [[TMP122]]
26409 // CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i32 [[TMP122]], i32 [[TMP123]]
26410 // CHECK-NEXT:    store i32 [[TMP125]], ptr [[IV]], align 4
26411 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26412 // CHECK-NEXT:    [[TMP126:%.*]] = load i32, ptr [[IE]], align 4
26413 // CHECK-NEXT:    [[TMP127:%.*]] = load i32, ptr [[ID]], align 4
26414 // CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP126]], i32 [[TMP127]] seq_cst seq_cst, align 4
26415 // CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i32, i1 } [[TMP128]], 0
26416 // CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i32, i1 } [[TMP128]], 1
26417 // CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i32 [[TMP126]], i32 [[TMP129]]
26418 // CHECK-NEXT:    store i32 [[TMP131]], ptr [[IV]], align 4
26419 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26420 // CHECK-NEXT:    [[TMP132:%.*]] = load i32, ptr [[IV]], align 4
26421 // CHECK-NEXT:    ret i32 [[TMP132]]
26422 //
26423 //
26424 // CHECK-LABEL: @uixevd(
26425 // CHECK-NEXT:  entry:
26426 // CHECK-NEXT:    [[UIX:%.*]] = alloca i32, align 4
26427 // CHECK-NEXT:    [[UIV:%.*]] = alloca i32, align 4
26428 // CHECK-NEXT:    [[UIE:%.*]] = alloca i32, align 4
26429 // CHECK-NEXT:    [[UID:%.*]] = alloca i32, align 4
26430 // CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[UIE]], align 4
26431 // CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP0]] monotonic, align 4
26432 // CHECK-NEXT:    store i32 [[TMP1]], ptr [[UIV]], align 4
26433 // CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[UIE]], align 4
26434 // CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2]] monotonic, align 4
26435 // CHECK-NEXT:    store i32 [[TMP3]], ptr [[UIV]], align 4
26436 // CHECK-NEXT:    [[TMP4:%.*]] = load i32, ptr [[UIE]], align 4
26437 // CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[UID]], align 4
26438 // CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP4]], i32 [[TMP5]] monotonic monotonic, align 4
26439 // CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0
26440 // CHECK-NEXT:    store i32 [[TMP7]], ptr [[UIV]], align 4
26441 // CHECK-NEXT:    [[TMP8:%.*]] = load i32, ptr [[UIE]], align 4
26442 // CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP8]] monotonic, align 4
26443 // CHECK-NEXT:    [[TMP10:%.*]] = icmp ult i32 [[TMP9]], [[TMP8]]
26444 // CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i32 [[TMP8]], i32 [[TMP9]]
26445 // CHECK-NEXT:    store i32 [[TMP11]], ptr [[UIV]], align 4
26446 // CHECK-NEXT:    [[TMP12:%.*]] = load i32, ptr [[UIE]], align 4
26447 // CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP12]] monotonic, align 4
26448 // CHECK-NEXT:    [[TMP14:%.*]] = icmp ugt i32 [[TMP13]], [[TMP12]]
26449 // CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[TMP12]], i32 [[TMP13]]
26450 // CHECK-NEXT:    store i32 [[TMP15]], ptr [[UIV]], align 4
26451 // CHECK-NEXT:    [[TMP16:%.*]] = load i32, ptr [[UIE]], align 4
26452 // CHECK-NEXT:    [[TMP17:%.*]] = load i32, ptr [[UID]], align 4
26453 // CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP16]], i32 [[TMP17]] monotonic monotonic, align 4
26454 // CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i32, i1 } [[TMP18]], 0
26455 // CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i32, i1 } [[TMP18]], 1
26456 // CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i32 [[TMP16]], i32 [[TMP19]]
26457 // CHECK-NEXT:    store i32 [[TMP21]], ptr [[UIV]], align 4
26458 // CHECK-NEXT:    [[TMP22:%.*]] = load i32, ptr [[UIE]], align 4
26459 // CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP22]] acq_rel, align 4
26460 // CHECK-NEXT:    store i32 [[TMP23]], ptr [[UIV]], align 4
26461 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26462 // CHECK-NEXT:    [[TMP24:%.*]] = load i32, ptr [[UIE]], align 4
26463 // CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP24]] acq_rel, align 4
26464 // CHECK-NEXT:    store i32 [[TMP25]], ptr [[UIV]], align 4
26465 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26466 // CHECK-NEXT:    [[TMP26:%.*]] = load i32, ptr [[UIE]], align 4
26467 // CHECK-NEXT:    [[TMP27:%.*]] = load i32, ptr [[UID]], align 4
26468 // CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP26]], i32 [[TMP27]] acq_rel acquire, align 4
26469 // CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i32, i1 } [[TMP28]], 0
26470 // CHECK-NEXT:    store i32 [[TMP29]], ptr [[UIV]], align 4
26471 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26472 // CHECK-NEXT:    [[TMP30:%.*]] = load i32, ptr [[UIE]], align 4
26473 // CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP30]] acq_rel, align 4
26474 // CHECK-NEXT:    [[TMP32:%.*]] = icmp ult i32 [[TMP31]], [[TMP30]]
26475 // CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i32 [[TMP30]], i32 [[TMP31]]
26476 // CHECK-NEXT:    store i32 [[TMP33]], ptr [[UIV]], align 4
26477 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26478 // CHECK-NEXT:    [[TMP34:%.*]] = load i32, ptr [[UIE]], align 4
26479 // CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP34]] acq_rel, align 4
26480 // CHECK-NEXT:    [[TMP36:%.*]] = icmp ugt i32 [[TMP35]], [[TMP34]]
26481 // CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i32 [[TMP34]], i32 [[TMP35]]
26482 // CHECK-NEXT:    store i32 [[TMP37]], ptr [[UIV]], align 4
26483 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26484 // CHECK-NEXT:    [[TMP38:%.*]] = load i32, ptr [[UIE]], align 4
26485 // CHECK-NEXT:    [[TMP39:%.*]] = load i32, ptr [[UID]], align 4
26486 // CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP38]], i32 [[TMP39]] acq_rel acquire, align 4
26487 // CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i32, i1 } [[TMP40]], 0
26488 // CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i32, i1 } [[TMP40]], 1
26489 // CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP38]], i32 [[TMP41]]
26490 // CHECK-NEXT:    store i32 [[TMP43]], ptr [[UIV]], align 4
26491 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26492 // CHECK-NEXT:    [[TMP44:%.*]] = load i32, ptr [[UIE]], align 4
26493 // CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP44]] acquire, align 4
26494 // CHECK-NEXT:    store i32 [[TMP45]], ptr [[UIV]], align 4
26495 // CHECK-NEXT:    [[TMP46:%.*]] = load i32, ptr [[UIE]], align 4
26496 // CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP46]] acquire, align 4
26497 // CHECK-NEXT:    store i32 [[TMP47]], ptr [[UIV]], align 4
26498 // CHECK-NEXT:    [[TMP48:%.*]] = load i32, ptr [[UIE]], align 4
26499 // CHECK-NEXT:    [[TMP49:%.*]] = load i32, ptr [[UID]], align 4
26500 // CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP48]], i32 [[TMP49]] acquire acquire, align 4
26501 // CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i32, i1 } [[TMP50]], 0
26502 // CHECK-NEXT:    store i32 [[TMP51]], ptr [[UIV]], align 4
26503 // CHECK-NEXT:    [[TMP52:%.*]] = load i32, ptr [[UIE]], align 4
26504 // CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP52]] acquire, align 4
26505 // CHECK-NEXT:    [[TMP54:%.*]] = icmp ult i32 [[TMP53]], [[TMP52]]
26506 // CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i32 [[TMP52]], i32 [[TMP53]]
26507 // CHECK-NEXT:    store i32 [[TMP55]], ptr [[UIV]], align 4
26508 // CHECK-NEXT:    [[TMP56:%.*]] = load i32, ptr [[UIE]], align 4
26509 // CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP56]] acquire, align 4
26510 // CHECK-NEXT:    [[TMP58:%.*]] = icmp ugt i32 [[TMP57]], [[TMP56]]
26511 // CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i32 [[TMP56]], i32 [[TMP57]]
26512 // CHECK-NEXT:    store i32 [[TMP59]], ptr [[UIV]], align 4
26513 // CHECK-NEXT:    [[TMP60:%.*]] = load i32, ptr [[UIE]], align 4
26514 // CHECK-NEXT:    [[TMP61:%.*]] = load i32, ptr [[UID]], align 4
26515 // CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP60]], i32 [[TMP61]] acquire acquire, align 4
26516 // CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i32, i1 } [[TMP62]], 0
26517 // CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i32, i1 } [[TMP62]], 1
26518 // CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i32 [[TMP60]], i32 [[TMP63]]
26519 // CHECK-NEXT:    store i32 [[TMP65]], ptr [[UIV]], align 4
26520 // CHECK-NEXT:    [[TMP66:%.*]] = load i32, ptr [[UIE]], align 4
26521 // CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP66]] monotonic, align 4
26522 // CHECK-NEXT:    store i32 [[TMP67]], ptr [[UIV]], align 4
26523 // CHECK-NEXT:    [[TMP68:%.*]] = load i32, ptr [[UIE]], align 4
26524 // CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP68]] monotonic, align 4
26525 // CHECK-NEXT:    store i32 [[TMP69]], ptr [[UIV]], align 4
26526 // CHECK-NEXT:    [[TMP70:%.*]] = load i32, ptr [[UIE]], align 4
26527 // CHECK-NEXT:    [[TMP71:%.*]] = load i32, ptr [[UID]], align 4
26528 // CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP70]], i32 [[TMP71]] monotonic monotonic, align 4
26529 // CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i32, i1 } [[TMP72]], 0
26530 // CHECK-NEXT:    store i32 [[TMP73]], ptr [[UIV]], align 4
26531 // CHECK-NEXT:    [[TMP74:%.*]] = load i32, ptr [[UIE]], align 4
26532 // CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP74]] monotonic, align 4
26533 // CHECK-NEXT:    [[TMP76:%.*]] = icmp ult i32 [[TMP75]], [[TMP74]]
26534 // CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i32 [[TMP74]], i32 [[TMP75]]
26535 // CHECK-NEXT:    store i32 [[TMP77]], ptr [[UIV]], align 4
26536 // CHECK-NEXT:    [[TMP78:%.*]] = load i32, ptr [[UIE]], align 4
26537 // CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP78]] monotonic, align 4
26538 // CHECK-NEXT:    [[TMP80:%.*]] = icmp ugt i32 [[TMP79]], [[TMP78]]
26539 // CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i32 [[TMP78]], i32 [[TMP79]]
26540 // CHECK-NEXT:    store i32 [[TMP81]], ptr [[UIV]], align 4
26541 // CHECK-NEXT:    [[TMP82:%.*]] = load i32, ptr [[UIE]], align 4
26542 // CHECK-NEXT:    [[TMP83:%.*]] = load i32, ptr [[UID]], align 4
26543 // CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP82]], i32 [[TMP83]] monotonic monotonic, align 4
26544 // CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i32, i1 } [[TMP84]], 0
26545 // CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i32, i1 } [[TMP84]], 1
26546 // CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i32 [[TMP82]], i32 [[TMP85]]
26547 // CHECK-NEXT:    store i32 [[TMP87]], ptr [[UIV]], align 4
26548 // CHECK-NEXT:    [[TMP88:%.*]] = load i32, ptr [[UIE]], align 4
26549 // CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP88]] release, align 4
26550 // CHECK-NEXT:    store i32 [[TMP89]], ptr [[UIV]], align 4
26551 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26552 // CHECK-NEXT:    [[TMP90:%.*]] = load i32, ptr [[UIE]], align 4
26553 // CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP90]] release, align 4
26554 // CHECK-NEXT:    store i32 [[TMP91]], ptr [[UIV]], align 4
26555 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26556 // CHECK-NEXT:    [[TMP92:%.*]] = load i32, ptr [[UIE]], align 4
26557 // CHECK-NEXT:    [[TMP93:%.*]] = load i32, ptr [[UID]], align 4
26558 // CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP92]], i32 [[TMP93]] release monotonic, align 4
26559 // CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i32, i1 } [[TMP94]], 0
26560 // CHECK-NEXT:    store i32 [[TMP95]], ptr [[UIV]], align 4
26561 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26562 // CHECK-NEXT:    [[TMP96:%.*]] = load i32, ptr [[UIE]], align 4
26563 // CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP96]] release, align 4
26564 // CHECK-NEXT:    [[TMP98:%.*]] = icmp ult i32 [[TMP97]], [[TMP96]]
26565 // CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i32 [[TMP96]], i32 [[TMP97]]
26566 // CHECK-NEXT:    store i32 [[TMP99]], ptr [[UIV]], align 4
26567 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26568 // CHECK-NEXT:    [[TMP100:%.*]] = load i32, ptr [[UIE]], align 4
26569 // CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP100]] release, align 4
26570 // CHECK-NEXT:    [[TMP102:%.*]] = icmp ugt i32 [[TMP101]], [[TMP100]]
26571 // CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i32 [[TMP100]], i32 [[TMP101]]
26572 // CHECK-NEXT:    store i32 [[TMP103]], ptr [[UIV]], align 4
26573 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26574 // CHECK-NEXT:    [[TMP104:%.*]] = load i32, ptr [[UIE]], align 4
26575 // CHECK-NEXT:    [[TMP105:%.*]] = load i32, ptr [[UID]], align 4
26576 // CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP104]], i32 [[TMP105]] release monotonic, align 4
26577 // CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i32, i1 } [[TMP106]], 0
26578 // CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i32, i1 } [[TMP106]], 1
26579 // CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i32 [[TMP104]], i32 [[TMP107]]
26580 // CHECK-NEXT:    store i32 [[TMP109]], ptr [[UIV]], align 4
26581 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26582 // CHECK-NEXT:    [[TMP110:%.*]] = load i32, ptr [[UIE]], align 4
26583 // CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP110]] seq_cst, align 4
26584 // CHECK-NEXT:    store i32 [[TMP111]], ptr [[UIV]], align 4
26585 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26586 // CHECK-NEXT:    [[TMP112:%.*]] = load i32, ptr [[UIE]], align 4
26587 // CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP112]] seq_cst, align 4
26588 // CHECK-NEXT:    store i32 [[TMP113]], ptr [[UIV]], align 4
26589 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26590 // CHECK-NEXT:    [[TMP114:%.*]] = load i32, ptr [[UIE]], align 4
26591 // CHECK-NEXT:    [[TMP115:%.*]] = load i32, ptr [[UID]], align 4
26592 // CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP114]], i32 [[TMP115]] seq_cst seq_cst, align 4
26593 // CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i32, i1 } [[TMP116]], 0
26594 // CHECK-NEXT:    store i32 [[TMP117]], ptr [[UIV]], align 4
26595 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26596 // CHECK-NEXT:    [[TMP118:%.*]] = load i32, ptr [[UIE]], align 4
26597 // CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP118]] seq_cst, align 4
26598 // CHECK-NEXT:    [[TMP120:%.*]] = icmp ult i32 [[TMP119]], [[TMP118]]
26599 // CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i32 [[TMP118]], i32 [[TMP119]]
26600 // CHECK-NEXT:    store i32 [[TMP121]], ptr [[UIV]], align 4
26601 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26602 // CHECK-NEXT:    [[TMP122:%.*]] = load i32, ptr [[UIE]], align 4
26603 // CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP122]] seq_cst, align 4
26604 // CHECK-NEXT:    [[TMP124:%.*]] = icmp ugt i32 [[TMP123]], [[TMP122]]
26605 // CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i32 [[TMP122]], i32 [[TMP123]]
26606 // CHECK-NEXT:    store i32 [[TMP125]], ptr [[UIV]], align 4
26607 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26608 // CHECK-NEXT:    [[TMP126:%.*]] = load i32, ptr [[UIE]], align 4
26609 // CHECK-NEXT:    [[TMP127:%.*]] = load i32, ptr [[UID]], align 4
26610 // CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP126]], i32 [[TMP127]] seq_cst seq_cst, align 4
26611 // CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i32, i1 } [[TMP128]], 0
26612 // CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i32, i1 } [[TMP128]], 1
26613 // CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i32 [[TMP126]], i32 [[TMP129]]
26614 // CHECK-NEXT:    store i32 [[TMP131]], ptr [[UIV]], align 4
26615 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26616 // CHECK-NEXT:    [[TMP132:%.*]] = load i32, ptr [[UIV]], align 4
26617 // CHECK-NEXT:    ret i32 [[TMP132]]
26618 //
26619 //
26620 // CHECK-LABEL: @lxevd(
26621 // CHECK-NEXT:  entry:
26622 // CHECK-NEXT:    [[LX:%.*]] = alloca i64, align 8
26623 // CHECK-NEXT:    [[LV:%.*]] = alloca i64, align 8
26624 // CHECK-NEXT:    [[LE:%.*]] = alloca i64, align 8
26625 // CHECK-NEXT:    [[LD:%.*]] = alloca i64, align 8
26626 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr [[LE]], align 8
26627 // CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP0]] monotonic, align 8
26628 // CHECK-NEXT:    store i64 [[TMP1]], ptr [[LV]], align 8
26629 // CHECK-NEXT:    [[TMP2:%.*]] = load i64, ptr [[LE]], align 8
26630 // CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2]] monotonic, align 8
26631 // CHECK-NEXT:    store i64 [[TMP3]], ptr [[LV]], align 8
26632 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr [[LE]], align 8
26633 // CHECK-NEXT:    [[TMP5:%.*]] = load i64, ptr [[LD]], align 8
26634 // CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP4]], i64 [[TMP5]] monotonic monotonic, align 8
26635 // CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
26636 // CHECK-NEXT:    store i64 [[TMP7]], ptr [[LV]], align 8
26637 // CHECK-NEXT:    [[TMP8:%.*]] = load i64, ptr [[LE]], align 8
26638 // CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP8]] monotonic, align 8
26639 // CHECK-NEXT:    [[TMP10:%.*]] = icmp slt i64 [[TMP9]], [[TMP8]]
26640 // CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP8]], i64 [[TMP9]]
26641 // CHECK-NEXT:    store i64 [[TMP11]], ptr [[LV]], align 8
26642 // CHECK-NEXT:    [[TMP12:%.*]] = load i64, ptr [[LE]], align 8
26643 // CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP12]] monotonic, align 8
26644 // CHECK-NEXT:    [[TMP14:%.*]] = icmp sgt i64 [[TMP13]], [[TMP12]]
26645 // CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP12]], i64 [[TMP13]]
26646 // CHECK-NEXT:    store i64 [[TMP15]], ptr [[LV]], align 8
26647 // CHECK-NEXT:    [[TMP16:%.*]] = load i64, ptr [[LE]], align 8
26648 // CHECK-NEXT:    [[TMP17:%.*]] = load i64, ptr [[LD]], align 8
26649 // CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP16]], i64 [[TMP17]] monotonic monotonic, align 8
26650 // CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i64, i1 } [[TMP18]], 0
26651 // CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i64, i1 } [[TMP18]], 1
26652 // CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[TMP16]], i64 [[TMP19]]
26653 // CHECK-NEXT:    store i64 [[TMP21]], ptr [[LV]], align 8
26654 // CHECK-NEXT:    [[TMP22:%.*]] = load i64, ptr [[LE]], align 8
26655 // CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP22]] acq_rel, align 8
26656 // CHECK-NEXT:    store i64 [[TMP23]], ptr [[LV]], align 8
26657 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26658 // CHECK-NEXT:    [[TMP24:%.*]] = load i64, ptr [[LE]], align 8
26659 // CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP24]] acq_rel, align 8
26660 // CHECK-NEXT:    store i64 [[TMP25]], ptr [[LV]], align 8
26661 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26662 // CHECK-NEXT:    [[TMP26:%.*]] = load i64, ptr [[LE]], align 8
26663 // CHECK-NEXT:    [[TMP27:%.*]] = load i64, ptr [[LD]], align 8
26664 // CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP26]], i64 [[TMP27]] acq_rel acquire, align 8
26665 // CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i64, i1 } [[TMP28]], 0
26666 // CHECK-NEXT:    store i64 [[TMP29]], ptr [[LV]], align 8
26667 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26668 // CHECK-NEXT:    [[TMP30:%.*]] = load i64, ptr [[LE]], align 8
26669 // CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP30]] acq_rel, align 8
26670 // CHECK-NEXT:    [[TMP32:%.*]] = icmp slt i64 [[TMP31]], [[TMP30]]
26671 // CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i64 [[TMP30]], i64 [[TMP31]]
26672 // CHECK-NEXT:    store i64 [[TMP33]], ptr [[LV]], align 8
26673 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26674 // CHECK-NEXT:    [[TMP34:%.*]] = load i64, ptr [[LE]], align 8
26675 // CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP34]] acq_rel, align 8
26676 // CHECK-NEXT:    [[TMP36:%.*]] = icmp sgt i64 [[TMP35]], [[TMP34]]
26677 // CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i64 [[TMP34]], i64 [[TMP35]]
26678 // CHECK-NEXT:    store i64 [[TMP37]], ptr [[LV]], align 8
26679 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26680 // CHECK-NEXT:    [[TMP38:%.*]] = load i64, ptr [[LE]], align 8
26681 // CHECK-NEXT:    [[TMP39:%.*]] = load i64, ptr [[LD]], align 8
26682 // CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP38]], i64 [[TMP39]] acq_rel acquire, align 8
26683 // CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i64, i1 } [[TMP40]], 0
26684 // CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i64, i1 } [[TMP40]], 1
26685 // CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i64 [[TMP38]], i64 [[TMP41]]
26686 // CHECK-NEXT:    store i64 [[TMP43]], ptr [[LV]], align 8
26687 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26688 // CHECK-NEXT:    [[TMP44:%.*]] = load i64, ptr [[LE]], align 8
26689 // CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP44]] acquire, align 8
26690 // CHECK-NEXT:    store i64 [[TMP45]], ptr [[LV]], align 8
26691 // CHECK-NEXT:    [[TMP46:%.*]] = load i64, ptr [[LE]], align 8
26692 // CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP46]] acquire, align 8
26693 // CHECK-NEXT:    store i64 [[TMP47]], ptr [[LV]], align 8
26694 // CHECK-NEXT:    [[TMP48:%.*]] = load i64, ptr [[LE]], align 8
26695 // CHECK-NEXT:    [[TMP49:%.*]] = load i64, ptr [[LD]], align 8
26696 // CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP48]], i64 [[TMP49]] acquire acquire, align 8
26697 // CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i64, i1 } [[TMP50]], 0
26698 // CHECK-NEXT:    store i64 [[TMP51]], ptr [[LV]], align 8
26699 // CHECK-NEXT:    [[TMP52:%.*]] = load i64, ptr [[LE]], align 8
26700 // CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP52]] acquire, align 8
26701 // CHECK-NEXT:    [[TMP54:%.*]] = icmp slt i64 [[TMP53]], [[TMP52]]
26702 // CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i64 [[TMP52]], i64 [[TMP53]]
26703 // CHECK-NEXT:    store i64 [[TMP55]], ptr [[LV]], align 8
26704 // CHECK-NEXT:    [[TMP56:%.*]] = load i64, ptr [[LE]], align 8
26705 // CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP56]] acquire, align 8
26706 // CHECK-NEXT:    [[TMP58:%.*]] = icmp sgt i64 [[TMP57]], [[TMP56]]
26707 // CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i64 [[TMP56]], i64 [[TMP57]]
26708 // CHECK-NEXT:    store i64 [[TMP59]], ptr [[LV]], align 8
26709 // CHECK-NEXT:    [[TMP60:%.*]] = load i64, ptr [[LE]], align 8
26710 // CHECK-NEXT:    [[TMP61:%.*]] = load i64, ptr [[LD]], align 8
26711 // CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP60]], i64 [[TMP61]] acquire acquire, align 8
26712 // CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i64, i1 } [[TMP62]], 0
26713 // CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i64, i1 } [[TMP62]], 1
26714 // CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i64 [[TMP60]], i64 [[TMP63]]
26715 // CHECK-NEXT:    store i64 [[TMP65]], ptr [[LV]], align 8
26716 // CHECK-NEXT:    [[TMP66:%.*]] = load i64, ptr [[LE]], align 8
26717 // CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP66]] monotonic, align 8
26718 // CHECK-NEXT:    store i64 [[TMP67]], ptr [[LV]], align 8
26719 // CHECK-NEXT:    [[TMP68:%.*]] = load i64, ptr [[LE]], align 8
26720 // CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP68]] monotonic, align 8
26721 // CHECK-NEXT:    store i64 [[TMP69]], ptr [[LV]], align 8
26722 // CHECK-NEXT:    [[TMP70:%.*]] = load i64, ptr [[LE]], align 8
26723 // CHECK-NEXT:    [[TMP71:%.*]] = load i64, ptr [[LD]], align 8
26724 // CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP70]], i64 [[TMP71]] monotonic monotonic, align 8
26725 // CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i64, i1 } [[TMP72]], 0
26726 // CHECK-NEXT:    store i64 [[TMP73]], ptr [[LV]], align 8
26727 // CHECK-NEXT:    [[TMP74:%.*]] = load i64, ptr [[LE]], align 8
26728 // CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP74]] monotonic, align 8
26729 // CHECK-NEXT:    [[TMP76:%.*]] = icmp slt i64 [[TMP75]], [[TMP74]]
26730 // CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i64 [[TMP74]], i64 [[TMP75]]
26731 // CHECK-NEXT:    store i64 [[TMP77]], ptr [[LV]], align 8
26732 // CHECK-NEXT:    [[TMP78:%.*]] = load i64, ptr [[LE]], align 8
26733 // CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP78]] monotonic, align 8
26734 // CHECK-NEXT:    [[TMP80:%.*]] = icmp sgt i64 [[TMP79]], [[TMP78]]
26735 // CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i64 [[TMP78]], i64 [[TMP79]]
26736 // CHECK-NEXT:    store i64 [[TMP81]], ptr [[LV]], align 8
26737 // CHECK-NEXT:    [[TMP82:%.*]] = load i64, ptr [[LE]], align 8
26738 // CHECK-NEXT:    [[TMP83:%.*]] = load i64, ptr [[LD]], align 8
26739 // CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP82]], i64 [[TMP83]] monotonic monotonic, align 8
26740 // CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i64, i1 } [[TMP84]], 0
26741 // CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i64, i1 } [[TMP84]], 1
26742 // CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i64 [[TMP82]], i64 [[TMP85]]
26743 // CHECK-NEXT:    store i64 [[TMP87]], ptr [[LV]], align 8
26744 // CHECK-NEXT:    [[TMP88:%.*]] = load i64, ptr [[LE]], align 8
26745 // CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP88]] release, align 8
26746 // CHECK-NEXT:    store i64 [[TMP89]], ptr [[LV]], align 8
26747 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26748 // CHECK-NEXT:    [[TMP90:%.*]] = load i64, ptr [[LE]], align 8
26749 // CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP90]] release, align 8
26750 // CHECK-NEXT:    store i64 [[TMP91]], ptr [[LV]], align 8
26751 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26752 // CHECK-NEXT:    [[TMP92:%.*]] = load i64, ptr [[LE]], align 8
26753 // CHECK-NEXT:    [[TMP93:%.*]] = load i64, ptr [[LD]], align 8
26754 // CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP92]], i64 [[TMP93]] release monotonic, align 8
26755 // CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i64, i1 } [[TMP94]], 0
26756 // CHECK-NEXT:    store i64 [[TMP95]], ptr [[LV]], align 8
26757 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26758 // CHECK-NEXT:    [[TMP96:%.*]] = load i64, ptr [[LE]], align 8
26759 // CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP96]] release, align 8
26760 // CHECK-NEXT:    [[TMP98:%.*]] = icmp slt i64 [[TMP97]], [[TMP96]]
26761 // CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i64 [[TMP96]], i64 [[TMP97]]
26762 // CHECK-NEXT:    store i64 [[TMP99]], ptr [[LV]], align 8
26763 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26764 // CHECK-NEXT:    [[TMP100:%.*]] = load i64, ptr [[LE]], align 8
26765 // CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP100]] release, align 8
26766 // CHECK-NEXT:    [[TMP102:%.*]] = icmp sgt i64 [[TMP101]], [[TMP100]]
26767 // CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i64 [[TMP100]], i64 [[TMP101]]
26768 // CHECK-NEXT:    store i64 [[TMP103]], ptr [[LV]], align 8
26769 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26770 // CHECK-NEXT:    [[TMP104:%.*]] = load i64, ptr [[LE]], align 8
26771 // CHECK-NEXT:    [[TMP105:%.*]] = load i64, ptr [[LD]], align 8
26772 // CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP104]], i64 [[TMP105]] release monotonic, align 8
26773 // CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i64, i1 } [[TMP106]], 0
26774 // CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP106]], 1
26775 // CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i64 [[TMP104]], i64 [[TMP107]]
26776 // CHECK-NEXT:    store i64 [[TMP109]], ptr [[LV]], align 8
26777 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26778 // CHECK-NEXT:    [[TMP110:%.*]] = load i64, ptr [[LE]], align 8
26779 // CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP110]] seq_cst, align 8
26780 // CHECK-NEXT:    store i64 [[TMP111]], ptr [[LV]], align 8
26781 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26782 // CHECK-NEXT:    [[TMP112:%.*]] = load i64, ptr [[LE]], align 8
26783 // CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP112]] seq_cst, align 8
26784 // CHECK-NEXT:    store i64 [[TMP113]], ptr [[LV]], align 8
26785 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26786 // CHECK-NEXT:    [[TMP114:%.*]] = load i64, ptr [[LE]], align 8
26787 // CHECK-NEXT:    [[TMP115:%.*]] = load i64, ptr [[LD]], align 8
26788 // CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP114]], i64 [[TMP115]] seq_cst seq_cst, align 8
26789 // CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i64, i1 } [[TMP116]], 0
26790 // CHECK-NEXT:    store i64 [[TMP117]], ptr [[LV]], align 8
26791 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26792 // CHECK-NEXT:    [[TMP118:%.*]] = load i64, ptr [[LE]], align 8
26793 // CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP118]] seq_cst, align 8
26794 // CHECK-NEXT:    [[TMP120:%.*]] = icmp slt i64 [[TMP119]], [[TMP118]]
26795 // CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i64 [[TMP118]], i64 [[TMP119]]
26796 // CHECK-NEXT:    store i64 [[TMP121]], ptr [[LV]], align 8
26797 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26798 // CHECK-NEXT:    [[TMP122:%.*]] = load i64, ptr [[LE]], align 8
26799 // CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP122]] seq_cst, align 8
26800 // CHECK-NEXT:    [[TMP124:%.*]] = icmp sgt i64 [[TMP123]], [[TMP122]]
26801 // CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i64 [[TMP122]], i64 [[TMP123]]
26802 // CHECK-NEXT:    store i64 [[TMP125]], ptr [[LV]], align 8
26803 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26804 // CHECK-NEXT:    [[TMP126:%.*]] = load i64, ptr [[LE]], align 8
26805 // CHECK-NEXT:    [[TMP127:%.*]] = load i64, ptr [[LD]], align 8
26806 // CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP126]], i64 [[TMP127]] seq_cst seq_cst, align 8
26807 // CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i64, i1 } [[TMP128]], 0
26808 // CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i64, i1 } [[TMP128]], 1
26809 // CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i64 [[TMP126]], i64 [[TMP129]]
26810 // CHECK-NEXT:    store i64 [[TMP131]], ptr [[LV]], align 8
26811 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26812 // CHECK-NEXT:    [[TMP132:%.*]] = load i64, ptr [[LV]], align 8
26813 // CHECK-NEXT:    ret i64 [[TMP132]]
26814 //
26815 //
26816 // CHECK-LABEL: @ulxevd(
26817 // CHECK-NEXT:  entry:
26818 // CHECK-NEXT:    [[ULX:%.*]] = alloca i64, align 8
26819 // CHECK-NEXT:    [[ULV:%.*]] = alloca i64, align 8
26820 // CHECK-NEXT:    [[ULE:%.*]] = alloca i64, align 8
26821 // CHECK-NEXT:    [[ULD:%.*]] = alloca i64, align 8
26822 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr [[ULE]], align 8
26823 // CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP0]] monotonic, align 8
26824 // CHECK-NEXT:    store i64 [[TMP1]], ptr [[ULV]], align 8
26825 // CHECK-NEXT:    [[TMP2:%.*]] = load i64, ptr [[ULE]], align 8
26826 // CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2]] monotonic, align 8
26827 // CHECK-NEXT:    store i64 [[TMP3]], ptr [[ULV]], align 8
26828 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr [[ULE]], align 8
26829 // CHECK-NEXT:    [[TMP5:%.*]] = load i64, ptr [[ULD]], align 8
26830 // CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP4]], i64 [[TMP5]] monotonic monotonic, align 8
26831 // CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
26832 // CHECK-NEXT:    store i64 [[TMP7]], ptr [[ULV]], align 8
26833 // CHECK-NEXT:    [[TMP8:%.*]] = load i64, ptr [[ULE]], align 8
26834 // CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP8]] monotonic, align 8
26835 // CHECK-NEXT:    [[TMP10:%.*]] = icmp ult i64 [[TMP9]], [[TMP8]]
26836 // CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP8]], i64 [[TMP9]]
26837 // CHECK-NEXT:    store i64 [[TMP11]], ptr [[ULV]], align 8
26838 // CHECK-NEXT:    [[TMP12:%.*]] = load i64, ptr [[ULE]], align 8
26839 // CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP12]] monotonic, align 8
26840 // CHECK-NEXT:    [[TMP14:%.*]] = icmp ugt i64 [[TMP13]], [[TMP12]]
26841 // CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP12]], i64 [[TMP13]]
26842 // CHECK-NEXT:    store i64 [[TMP15]], ptr [[ULV]], align 8
26843 // CHECK-NEXT:    [[TMP16:%.*]] = load i64, ptr [[ULE]], align 8
26844 // CHECK-NEXT:    [[TMP17:%.*]] = load i64, ptr [[ULD]], align 8
26845 // CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP16]], i64 [[TMP17]] monotonic monotonic, align 8
26846 // CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i64, i1 } [[TMP18]], 0
26847 // CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i64, i1 } [[TMP18]], 1
26848 // CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[TMP16]], i64 [[TMP19]]
26849 // CHECK-NEXT:    store i64 [[TMP21]], ptr [[ULV]], align 8
26850 // CHECK-NEXT:    [[TMP22:%.*]] = load i64, ptr [[ULE]], align 8
26851 // CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP22]] acq_rel, align 8
26852 // CHECK-NEXT:    store i64 [[TMP23]], ptr [[ULV]], align 8
26853 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26854 // CHECK-NEXT:    [[TMP24:%.*]] = load i64, ptr [[ULE]], align 8
26855 // CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP24]] acq_rel, align 8
26856 // CHECK-NEXT:    store i64 [[TMP25]], ptr [[ULV]], align 8
26857 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26858 // CHECK-NEXT:    [[TMP26:%.*]] = load i64, ptr [[ULE]], align 8
26859 // CHECK-NEXT:    [[TMP27:%.*]] = load i64, ptr [[ULD]], align 8
26860 // CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP26]], i64 [[TMP27]] acq_rel acquire, align 8
26861 // CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i64, i1 } [[TMP28]], 0
26862 // CHECK-NEXT:    store i64 [[TMP29]], ptr [[ULV]], align 8
26863 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26864 // CHECK-NEXT:    [[TMP30:%.*]] = load i64, ptr [[ULE]], align 8
26865 // CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP30]] acq_rel, align 8
26866 // CHECK-NEXT:    [[TMP32:%.*]] = icmp ult i64 [[TMP31]], [[TMP30]]
26867 // CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i64 [[TMP30]], i64 [[TMP31]]
26868 // CHECK-NEXT:    store i64 [[TMP33]], ptr [[ULV]], align 8
26869 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26870 // CHECK-NEXT:    [[TMP34:%.*]] = load i64, ptr [[ULE]], align 8
26871 // CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP34]] acq_rel, align 8
26872 // CHECK-NEXT:    [[TMP36:%.*]] = icmp ugt i64 [[TMP35]], [[TMP34]]
26873 // CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i64 [[TMP34]], i64 [[TMP35]]
26874 // CHECK-NEXT:    store i64 [[TMP37]], ptr [[ULV]], align 8
26875 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26876 // CHECK-NEXT:    [[TMP38:%.*]] = load i64, ptr [[ULE]], align 8
26877 // CHECK-NEXT:    [[TMP39:%.*]] = load i64, ptr [[ULD]], align 8
26878 // CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP38]], i64 [[TMP39]] acq_rel acquire, align 8
26879 // CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i64, i1 } [[TMP40]], 0
26880 // CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i64, i1 } [[TMP40]], 1
26881 // CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i64 [[TMP38]], i64 [[TMP41]]
26882 // CHECK-NEXT:    store i64 [[TMP43]], ptr [[ULV]], align 8
26883 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26884 // CHECK-NEXT:    [[TMP44:%.*]] = load i64, ptr [[ULE]], align 8
26885 // CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP44]] acquire, align 8
26886 // CHECK-NEXT:    store i64 [[TMP45]], ptr [[ULV]], align 8
26887 // CHECK-NEXT:    [[TMP46:%.*]] = load i64, ptr [[ULE]], align 8
26888 // CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP46]] acquire, align 8
26889 // CHECK-NEXT:    store i64 [[TMP47]], ptr [[ULV]], align 8
26890 // CHECK-NEXT:    [[TMP48:%.*]] = load i64, ptr [[ULE]], align 8
26891 // CHECK-NEXT:    [[TMP49:%.*]] = load i64, ptr [[ULD]], align 8
26892 // CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP48]], i64 [[TMP49]] acquire acquire, align 8
26893 // CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i64, i1 } [[TMP50]], 0
26894 // CHECK-NEXT:    store i64 [[TMP51]], ptr [[ULV]], align 8
26895 // CHECK-NEXT:    [[TMP52:%.*]] = load i64, ptr [[ULE]], align 8
26896 // CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP52]] acquire, align 8
26897 // CHECK-NEXT:    [[TMP54:%.*]] = icmp ult i64 [[TMP53]], [[TMP52]]
26898 // CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i64 [[TMP52]], i64 [[TMP53]]
26899 // CHECK-NEXT:    store i64 [[TMP55]], ptr [[ULV]], align 8
26900 // CHECK-NEXT:    [[TMP56:%.*]] = load i64, ptr [[ULE]], align 8
26901 // CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP56]] acquire, align 8
26902 // CHECK-NEXT:    [[TMP58:%.*]] = icmp ugt i64 [[TMP57]], [[TMP56]]
26903 // CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i64 [[TMP56]], i64 [[TMP57]]
26904 // CHECK-NEXT:    store i64 [[TMP59]], ptr [[ULV]], align 8
26905 // CHECK-NEXT:    [[TMP60:%.*]] = load i64, ptr [[ULE]], align 8
26906 // CHECK-NEXT:    [[TMP61:%.*]] = load i64, ptr [[ULD]], align 8
26907 // CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP60]], i64 [[TMP61]] acquire acquire, align 8
26908 // CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i64, i1 } [[TMP62]], 0
26909 // CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i64, i1 } [[TMP62]], 1
26910 // CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i64 [[TMP60]], i64 [[TMP63]]
26911 // CHECK-NEXT:    store i64 [[TMP65]], ptr [[ULV]], align 8
26912 // CHECK-NEXT:    [[TMP66:%.*]] = load i64, ptr [[ULE]], align 8
26913 // CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP66]] monotonic, align 8
26914 // CHECK-NEXT:    store i64 [[TMP67]], ptr [[ULV]], align 8
26915 // CHECK-NEXT:    [[TMP68:%.*]] = load i64, ptr [[ULE]], align 8
26916 // CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP68]] monotonic, align 8
26917 // CHECK-NEXT:    store i64 [[TMP69]], ptr [[ULV]], align 8
26918 // CHECK-NEXT:    [[TMP70:%.*]] = load i64, ptr [[ULE]], align 8
26919 // CHECK-NEXT:    [[TMP71:%.*]] = load i64, ptr [[ULD]], align 8
26920 // CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP70]], i64 [[TMP71]] monotonic monotonic, align 8
26921 // CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i64, i1 } [[TMP72]], 0
26922 // CHECK-NEXT:    store i64 [[TMP73]], ptr [[ULV]], align 8
26923 // CHECK-NEXT:    [[TMP74:%.*]] = load i64, ptr [[ULE]], align 8
26924 // CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP74]] monotonic, align 8
26925 // CHECK-NEXT:    [[TMP76:%.*]] = icmp ult i64 [[TMP75]], [[TMP74]]
26926 // CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i64 [[TMP74]], i64 [[TMP75]]
26927 // CHECK-NEXT:    store i64 [[TMP77]], ptr [[ULV]], align 8
26928 // CHECK-NEXT:    [[TMP78:%.*]] = load i64, ptr [[ULE]], align 8
26929 // CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP78]] monotonic, align 8
26930 // CHECK-NEXT:    [[TMP80:%.*]] = icmp ugt i64 [[TMP79]], [[TMP78]]
26931 // CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i64 [[TMP78]], i64 [[TMP79]]
26932 // CHECK-NEXT:    store i64 [[TMP81]], ptr [[ULV]], align 8
26933 // CHECK-NEXT:    [[TMP82:%.*]] = load i64, ptr [[ULE]], align 8
26934 // CHECK-NEXT:    [[TMP83:%.*]] = load i64, ptr [[ULD]], align 8
26935 // CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP82]], i64 [[TMP83]] monotonic monotonic, align 8
26936 // CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i64, i1 } [[TMP84]], 0
26937 // CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i64, i1 } [[TMP84]], 1
26938 // CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i64 [[TMP82]], i64 [[TMP85]]
26939 // CHECK-NEXT:    store i64 [[TMP87]], ptr [[ULV]], align 8
26940 // CHECK-NEXT:    [[TMP88:%.*]] = load i64, ptr [[ULE]], align 8
26941 // CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP88]] release, align 8
26942 // CHECK-NEXT:    store i64 [[TMP89]], ptr [[ULV]], align 8
26943 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26944 // CHECK-NEXT:    [[TMP90:%.*]] = load i64, ptr [[ULE]], align 8
26945 // CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP90]] release, align 8
26946 // CHECK-NEXT:    store i64 [[TMP91]], ptr [[ULV]], align 8
26947 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26948 // CHECK-NEXT:    [[TMP92:%.*]] = load i64, ptr [[ULE]], align 8
26949 // CHECK-NEXT:    [[TMP93:%.*]] = load i64, ptr [[ULD]], align 8
26950 // CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP92]], i64 [[TMP93]] release monotonic, align 8
26951 // CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i64, i1 } [[TMP94]], 0
26952 // CHECK-NEXT:    store i64 [[TMP95]], ptr [[ULV]], align 8
26953 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26954 // CHECK-NEXT:    [[TMP96:%.*]] = load i64, ptr [[ULE]], align 8
26955 // CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP96]] release, align 8
26956 // CHECK-NEXT:    [[TMP98:%.*]] = icmp ult i64 [[TMP97]], [[TMP96]]
26957 // CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i64 [[TMP96]], i64 [[TMP97]]
26958 // CHECK-NEXT:    store i64 [[TMP99]], ptr [[ULV]], align 8
26959 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26960 // CHECK-NEXT:    [[TMP100:%.*]] = load i64, ptr [[ULE]], align 8
26961 // CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP100]] release, align 8
26962 // CHECK-NEXT:    [[TMP102:%.*]] = icmp ugt i64 [[TMP101]], [[TMP100]]
26963 // CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i64 [[TMP100]], i64 [[TMP101]]
26964 // CHECK-NEXT:    store i64 [[TMP103]], ptr [[ULV]], align 8
26965 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26966 // CHECK-NEXT:    [[TMP104:%.*]] = load i64, ptr [[ULE]], align 8
26967 // CHECK-NEXT:    [[TMP105:%.*]] = load i64, ptr [[ULD]], align 8
26968 // CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP104]], i64 [[TMP105]] release monotonic, align 8
26969 // CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i64, i1 } [[TMP106]], 0
26970 // CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP106]], 1
26971 // CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i64 [[TMP104]], i64 [[TMP107]]
26972 // CHECK-NEXT:    store i64 [[TMP109]], ptr [[ULV]], align 8
26973 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26974 // CHECK-NEXT:    [[TMP110:%.*]] = load i64, ptr [[ULE]], align 8
26975 // CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP110]] seq_cst, align 8
26976 // CHECK-NEXT:    store i64 [[TMP111]], ptr [[ULV]], align 8
26977 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26978 // CHECK-NEXT:    [[TMP112:%.*]] = load i64, ptr [[ULE]], align 8
26979 // CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP112]] seq_cst, align 8
26980 // CHECK-NEXT:    store i64 [[TMP113]], ptr [[ULV]], align 8
26981 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26982 // CHECK-NEXT:    [[TMP114:%.*]] = load i64, ptr [[ULE]], align 8
26983 // CHECK-NEXT:    [[TMP115:%.*]] = load i64, ptr [[ULD]], align 8
26984 // CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP114]], i64 [[TMP115]] seq_cst seq_cst, align 8
26985 // CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i64, i1 } [[TMP116]], 0
26986 // CHECK-NEXT:    store i64 [[TMP117]], ptr [[ULV]], align 8
26987 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26988 // CHECK-NEXT:    [[TMP118:%.*]] = load i64, ptr [[ULE]], align 8
26989 // CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP118]] seq_cst, align 8
26990 // CHECK-NEXT:    [[TMP120:%.*]] = icmp ult i64 [[TMP119]], [[TMP118]]
26991 // CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i64 [[TMP118]], i64 [[TMP119]]
26992 // CHECK-NEXT:    store i64 [[TMP121]], ptr [[ULV]], align 8
26993 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
26994 // CHECK-NEXT:    [[TMP122:%.*]] = load i64, ptr [[ULE]], align 8
26995 // CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP122]] seq_cst, align 8
26996 // CHECK-NEXT:    [[TMP124:%.*]] = icmp ugt i64 [[TMP123]], [[TMP122]]
26997 // CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i64 [[TMP122]], i64 [[TMP123]]
26998 // CHECK-NEXT:    store i64 [[TMP125]], ptr [[ULV]], align 8
26999 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27000 // CHECK-NEXT:    [[TMP126:%.*]] = load i64, ptr [[ULE]], align 8
27001 // CHECK-NEXT:    [[TMP127:%.*]] = load i64, ptr [[ULD]], align 8
27002 // CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP126]], i64 [[TMP127]] seq_cst seq_cst, align 8
27003 // CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i64, i1 } [[TMP128]], 0
27004 // CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i64, i1 } [[TMP128]], 1
27005 // CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i64 [[TMP126]], i64 [[TMP129]]
27006 // CHECK-NEXT:    store i64 [[TMP131]], ptr [[ULV]], align 8
27007 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27008 // CHECK-NEXT:    [[TMP132:%.*]] = load i64, ptr [[ULV]], align 8
27009 // CHECK-NEXT:    ret i64 [[TMP132]]
27010 //
27011 //
27012 // CHECK-LABEL: @llxevd(
27013 // CHECK-NEXT:  entry:
27014 // CHECK-NEXT:    [[LLX:%.*]] = alloca i64, align 8
27015 // CHECK-NEXT:    [[LLV:%.*]] = alloca i64, align 8
27016 // CHECK-NEXT:    [[LLE:%.*]] = alloca i64, align 8
27017 // CHECK-NEXT:    [[LLD:%.*]] = alloca i64, align 8
27018 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr [[LLE]], align 8
27019 // CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP0]] monotonic, align 8
27020 // CHECK-NEXT:    store i64 [[TMP1]], ptr [[LLV]], align 8
27021 // CHECK-NEXT:    [[TMP2:%.*]] = load i64, ptr [[LLE]], align 8
27022 // CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2]] monotonic, align 8
27023 // CHECK-NEXT:    store i64 [[TMP3]], ptr [[LLV]], align 8
27024 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr [[LLE]], align 8
27025 // CHECK-NEXT:    [[TMP5:%.*]] = load i64, ptr [[LLD]], align 8
27026 // CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4]], i64 [[TMP5]] monotonic monotonic, align 8
27027 // CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
27028 // CHECK-NEXT:    store i64 [[TMP7]], ptr [[LLV]], align 8
27029 // CHECK-NEXT:    [[TMP8:%.*]] = load i64, ptr [[LLE]], align 8
27030 // CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP8]] monotonic, align 8
27031 // CHECK-NEXT:    [[TMP10:%.*]] = icmp slt i64 [[TMP9]], [[TMP8]]
27032 // CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP8]], i64 [[TMP9]]
27033 // CHECK-NEXT:    store i64 [[TMP11]], ptr [[LLV]], align 8
27034 // CHECK-NEXT:    [[TMP12:%.*]] = load i64, ptr [[LLE]], align 8
27035 // CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP12]] monotonic, align 8
27036 // CHECK-NEXT:    [[TMP14:%.*]] = icmp sgt i64 [[TMP13]], [[TMP12]]
27037 // CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP12]], i64 [[TMP13]]
27038 // CHECK-NEXT:    store i64 [[TMP15]], ptr [[LLV]], align 8
27039 // CHECK-NEXT:    [[TMP16:%.*]] = load i64, ptr [[LLE]], align 8
27040 // CHECK-NEXT:    [[TMP17:%.*]] = load i64, ptr [[LLD]], align 8
27041 // CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP16]], i64 [[TMP17]] monotonic monotonic, align 8
27042 // CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i64, i1 } [[TMP18]], 0
27043 // CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i64, i1 } [[TMP18]], 1
27044 // CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[TMP16]], i64 [[TMP19]]
27045 // CHECK-NEXT:    store i64 [[TMP21]], ptr [[LLV]], align 8
27046 // CHECK-NEXT:    [[TMP22:%.*]] = load i64, ptr [[LLE]], align 8
27047 // CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP22]] acq_rel, align 8
27048 // CHECK-NEXT:    store i64 [[TMP23]], ptr [[LLV]], align 8
27049 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27050 // CHECK-NEXT:    [[TMP24:%.*]] = load i64, ptr [[LLE]], align 8
27051 // CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP24]] acq_rel, align 8
27052 // CHECK-NEXT:    store i64 [[TMP25]], ptr [[LLV]], align 8
27053 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27054 // CHECK-NEXT:    [[TMP26:%.*]] = load i64, ptr [[LLE]], align 8
27055 // CHECK-NEXT:    [[TMP27:%.*]] = load i64, ptr [[LLD]], align 8
27056 // CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP26]], i64 [[TMP27]] acq_rel acquire, align 8
27057 // CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i64, i1 } [[TMP28]], 0
27058 // CHECK-NEXT:    store i64 [[TMP29]], ptr [[LLV]], align 8
27059 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27060 // CHECK-NEXT:    [[TMP30:%.*]] = load i64, ptr [[LLE]], align 8
27061 // CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP30]] acq_rel, align 8
27062 // CHECK-NEXT:    [[TMP32:%.*]] = icmp slt i64 [[TMP31]], [[TMP30]]
27063 // CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i64 [[TMP30]], i64 [[TMP31]]
27064 // CHECK-NEXT:    store i64 [[TMP33]], ptr [[LLV]], align 8
27065 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27066 // CHECK-NEXT:    [[TMP34:%.*]] = load i64, ptr [[LLE]], align 8
27067 // CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP34]] acq_rel, align 8
27068 // CHECK-NEXT:    [[TMP36:%.*]] = icmp sgt i64 [[TMP35]], [[TMP34]]
27069 // CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i64 [[TMP34]], i64 [[TMP35]]
27070 // CHECK-NEXT:    store i64 [[TMP37]], ptr [[LLV]], align 8
27071 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27072 // CHECK-NEXT:    [[TMP38:%.*]] = load i64, ptr [[LLE]], align 8
27073 // CHECK-NEXT:    [[TMP39:%.*]] = load i64, ptr [[LLD]], align 8
27074 // CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP38]], i64 [[TMP39]] acq_rel acquire, align 8
27075 // CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i64, i1 } [[TMP40]], 0
27076 // CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i64, i1 } [[TMP40]], 1
27077 // CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i64 [[TMP38]], i64 [[TMP41]]
27078 // CHECK-NEXT:    store i64 [[TMP43]], ptr [[LLV]], align 8
27079 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27080 // CHECK-NEXT:    [[TMP44:%.*]] = load i64, ptr [[LLE]], align 8
27081 // CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP44]] acquire, align 8
27082 // CHECK-NEXT:    store i64 [[TMP45]], ptr [[LLV]], align 8
27083 // CHECK-NEXT:    [[TMP46:%.*]] = load i64, ptr [[LLE]], align 8
27084 // CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP46]] acquire, align 8
27085 // CHECK-NEXT:    store i64 [[TMP47]], ptr [[LLV]], align 8
27086 // CHECK-NEXT:    [[TMP48:%.*]] = load i64, ptr [[LLE]], align 8
27087 // CHECK-NEXT:    [[TMP49:%.*]] = load i64, ptr [[LLD]], align 8
27088 // CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP48]], i64 [[TMP49]] acquire acquire, align 8
27089 // CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i64, i1 } [[TMP50]], 0
27090 // CHECK-NEXT:    store i64 [[TMP51]], ptr [[LLV]], align 8
27091 // CHECK-NEXT:    [[TMP52:%.*]] = load i64, ptr [[LLE]], align 8
27092 // CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP52]] acquire, align 8
27093 // CHECK-NEXT:    [[TMP54:%.*]] = icmp slt i64 [[TMP53]], [[TMP52]]
27094 // CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i64 [[TMP52]], i64 [[TMP53]]
27095 // CHECK-NEXT:    store i64 [[TMP55]], ptr [[LLV]], align 8
27096 // CHECK-NEXT:    [[TMP56:%.*]] = load i64, ptr [[LLE]], align 8
27097 // CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP56]] acquire, align 8
27098 // CHECK-NEXT:    [[TMP58:%.*]] = icmp sgt i64 [[TMP57]], [[TMP56]]
27099 // CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i64 [[TMP56]], i64 [[TMP57]]
27100 // CHECK-NEXT:    store i64 [[TMP59]], ptr [[LLV]], align 8
27101 // CHECK-NEXT:    [[TMP60:%.*]] = load i64, ptr [[LLE]], align 8
27102 // CHECK-NEXT:    [[TMP61:%.*]] = load i64, ptr [[LLD]], align 8
27103 // CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP60]], i64 [[TMP61]] acquire acquire, align 8
27104 // CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i64, i1 } [[TMP62]], 0
27105 // CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i64, i1 } [[TMP62]], 1
27106 // CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i64 [[TMP60]], i64 [[TMP63]]
27107 // CHECK-NEXT:    store i64 [[TMP65]], ptr [[LLV]], align 8
27108 // CHECK-NEXT:    [[TMP66:%.*]] = load i64, ptr [[LLE]], align 8
27109 // CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP66]] monotonic, align 8
27110 // CHECK-NEXT:    store i64 [[TMP67]], ptr [[LLV]], align 8
27111 // CHECK-NEXT:    [[TMP68:%.*]] = load i64, ptr [[LLE]], align 8
27112 // CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP68]] monotonic, align 8
27113 // CHECK-NEXT:    store i64 [[TMP69]], ptr [[LLV]], align 8
27114 // CHECK-NEXT:    [[TMP70:%.*]] = load i64, ptr [[LLE]], align 8
27115 // CHECK-NEXT:    [[TMP71:%.*]] = load i64, ptr [[LLD]], align 8
27116 // CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP70]], i64 [[TMP71]] monotonic monotonic, align 8
27117 // CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i64, i1 } [[TMP72]], 0
27118 // CHECK-NEXT:    store i64 [[TMP73]], ptr [[LLV]], align 8
27119 // CHECK-NEXT:    [[TMP74:%.*]] = load i64, ptr [[LLE]], align 8
27120 // CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP74]] monotonic, align 8
27121 // CHECK-NEXT:    [[TMP76:%.*]] = icmp slt i64 [[TMP75]], [[TMP74]]
27122 // CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i64 [[TMP74]], i64 [[TMP75]]
27123 // CHECK-NEXT:    store i64 [[TMP77]], ptr [[LLV]], align 8
27124 // CHECK-NEXT:    [[TMP78:%.*]] = load i64, ptr [[LLE]], align 8
27125 // CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP78]] monotonic, align 8
27126 // CHECK-NEXT:    [[TMP80:%.*]] = icmp sgt i64 [[TMP79]], [[TMP78]]
27127 // CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i64 [[TMP78]], i64 [[TMP79]]
27128 // CHECK-NEXT:    store i64 [[TMP81]], ptr [[LLV]], align 8
27129 // CHECK-NEXT:    [[TMP82:%.*]] = load i64, ptr [[LLE]], align 8
27130 // CHECK-NEXT:    [[TMP83:%.*]] = load i64, ptr [[LLD]], align 8
27131 // CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP82]], i64 [[TMP83]] monotonic monotonic, align 8
27132 // CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i64, i1 } [[TMP84]], 0
27133 // CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i64, i1 } [[TMP84]], 1
27134 // CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i64 [[TMP82]], i64 [[TMP85]]
27135 // CHECK-NEXT:    store i64 [[TMP87]], ptr [[LLV]], align 8
27136 // CHECK-NEXT:    [[TMP88:%.*]] = load i64, ptr [[LLE]], align 8
27137 // CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP88]] release, align 8
27138 // CHECK-NEXT:    store i64 [[TMP89]], ptr [[LLV]], align 8
27139 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27140 // CHECK-NEXT:    [[TMP90:%.*]] = load i64, ptr [[LLE]], align 8
27141 // CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP90]] release, align 8
27142 // CHECK-NEXT:    store i64 [[TMP91]], ptr [[LLV]], align 8
27143 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27144 // CHECK-NEXT:    [[TMP92:%.*]] = load i64, ptr [[LLE]], align 8
27145 // CHECK-NEXT:    [[TMP93:%.*]] = load i64, ptr [[LLD]], align 8
27146 // CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP92]], i64 [[TMP93]] release monotonic, align 8
27147 // CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i64, i1 } [[TMP94]], 0
27148 // CHECK-NEXT:    store i64 [[TMP95]], ptr [[LLV]], align 8
27149 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27150 // CHECK-NEXT:    [[TMP96:%.*]] = load i64, ptr [[LLE]], align 8
27151 // CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP96]] release, align 8
27152 // CHECK-NEXT:    [[TMP98:%.*]] = icmp slt i64 [[TMP97]], [[TMP96]]
27153 // CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i64 [[TMP96]], i64 [[TMP97]]
27154 // CHECK-NEXT:    store i64 [[TMP99]], ptr [[LLV]], align 8
27155 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27156 // CHECK-NEXT:    [[TMP100:%.*]] = load i64, ptr [[LLE]], align 8
27157 // CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP100]] release, align 8
27158 // CHECK-NEXT:    [[TMP102:%.*]] = icmp sgt i64 [[TMP101]], [[TMP100]]
27159 // CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i64 [[TMP100]], i64 [[TMP101]]
27160 // CHECK-NEXT:    store i64 [[TMP103]], ptr [[LLV]], align 8
27161 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27162 // CHECK-NEXT:    [[TMP104:%.*]] = load i64, ptr [[LLE]], align 8
27163 // CHECK-NEXT:    [[TMP105:%.*]] = load i64, ptr [[LLD]], align 8
27164 // CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP104]], i64 [[TMP105]] release monotonic, align 8
27165 // CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i64, i1 } [[TMP106]], 0
27166 // CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP106]], 1
27167 // CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i64 [[TMP104]], i64 [[TMP107]]
27168 // CHECK-NEXT:    store i64 [[TMP109]], ptr [[LLV]], align 8
27169 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27170 // CHECK-NEXT:    [[TMP110:%.*]] = load i64, ptr [[LLE]], align 8
27171 // CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP110]] seq_cst, align 8
27172 // CHECK-NEXT:    store i64 [[TMP111]], ptr [[LLV]], align 8
27173 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27174 // CHECK-NEXT:    [[TMP112:%.*]] = load i64, ptr [[LLE]], align 8
27175 // CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP112]] seq_cst, align 8
27176 // CHECK-NEXT:    store i64 [[TMP113]], ptr [[LLV]], align 8
27177 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27178 // CHECK-NEXT:    [[TMP114:%.*]] = load i64, ptr [[LLE]], align 8
27179 // CHECK-NEXT:    [[TMP115:%.*]] = load i64, ptr [[LLD]], align 8
27180 // CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP114]], i64 [[TMP115]] seq_cst seq_cst, align 8
27181 // CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i64, i1 } [[TMP116]], 0
27182 // CHECK-NEXT:    store i64 [[TMP117]], ptr [[LLV]], align 8
27183 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27184 // CHECK-NEXT:    [[TMP118:%.*]] = load i64, ptr [[LLE]], align 8
27185 // CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP118]] seq_cst, align 8
27186 // CHECK-NEXT:    [[TMP120:%.*]] = icmp slt i64 [[TMP119]], [[TMP118]]
27187 // CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i64 [[TMP118]], i64 [[TMP119]]
27188 // CHECK-NEXT:    store i64 [[TMP121]], ptr [[LLV]], align 8
27189 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27190 // CHECK-NEXT:    [[TMP122:%.*]] = load i64, ptr [[LLE]], align 8
27191 // CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP122]] seq_cst, align 8
27192 // CHECK-NEXT:    [[TMP124:%.*]] = icmp sgt i64 [[TMP123]], [[TMP122]]
27193 // CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i64 [[TMP122]], i64 [[TMP123]]
27194 // CHECK-NEXT:    store i64 [[TMP125]], ptr [[LLV]], align 8
27195 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27196 // CHECK-NEXT:    [[TMP126:%.*]] = load i64, ptr [[LLE]], align 8
27197 // CHECK-NEXT:    [[TMP127:%.*]] = load i64, ptr [[LLD]], align 8
27198 // CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP126]], i64 [[TMP127]] seq_cst seq_cst, align 8
27199 // CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i64, i1 } [[TMP128]], 0
27200 // CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i64, i1 } [[TMP128]], 1
27201 // CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i64 [[TMP126]], i64 [[TMP129]]
27202 // CHECK-NEXT:    store i64 [[TMP131]], ptr [[LLV]], align 8
27203 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27204 // CHECK-NEXT:    [[TMP132:%.*]] = load i64, ptr [[LLV]], align 8
27205 // CHECK-NEXT:    ret i64 [[TMP132]]
27206 //
27207 //
27208 // CHECK-LABEL: @ullxevd(
27209 // CHECK-NEXT:  entry:
27210 // CHECK-NEXT:    [[ULLX:%.*]] = alloca i64, align 8
27211 // CHECK-NEXT:    [[ULLV:%.*]] = alloca i64, align 8
27212 // CHECK-NEXT:    [[ULLE:%.*]] = alloca i64, align 8
27213 // CHECK-NEXT:    [[ULLD:%.*]] = alloca i64, align 8
27214 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr [[ULLE]], align 8
27215 // CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP0]] monotonic, align 8
27216 // CHECK-NEXT:    store i64 [[TMP1]], ptr [[ULLV]], align 8
27217 // CHECK-NEXT:    [[TMP2:%.*]] = load i64, ptr [[ULLE]], align 8
27218 // CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2]] monotonic, align 8
27219 // CHECK-NEXT:    store i64 [[TMP3]], ptr [[ULLV]], align 8
27220 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr [[ULLE]], align 8
27221 // CHECK-NEXT:    [[TMP5:%.*]] = load i64, ptr [[ULLD]], align 8
27222 // CHECK-NEXT:    [[TMP6:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4]], i64 [[TMP5]] monotonic monotonic, align 8
27223 // CHECK-NEXT:    [[TMP7:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
27224 // CHECK-NEXT:    store i64 [[TMP7]], ptr [[ULLV]], align 8
27225 // CHECK-NEXT:    [[TMP8:%.*]] = load i64, ptr [[ULLE]], align 8
27226 // CHECK-NEXT:    [[TMP9:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP8]] monotonic, align 8
27227 // CHECK-NEXT:    [[TMP10:%.*]] = icmp ult i64 [[TMP9]], [[TMP8]]
27228 // CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP8]], i64 [[TMP9]]
27229 // CHECK-NEXT:    store i64 [[TMP11]], ptr [[ULLV]], align 8
27230 // CHECK-NEXT:    [[TMP12:%.*]] = load i64, ptr [[ULLE]], align 8
27231 // CHECK-NEXT:    [[TMP13:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP12]] monotonic, align 8
27232 // CHECK-NEXT:    [[TMP14:%.*]] = icmp ugt i64 [[TMP13]], [[TMP12]]
27233 // CHECK-NEXT:    [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP12]], i64 [[TMP13]]
27234 // CHECK-NEXT:    store i64 [[TMP15]], ptr [[ULLV]], align 8
27235 // CHECK-NEXT:    [[TMP16:%.*]] = load i64, ptr [[ULLE]], align 8
27236 // CHECK-NEXT:    [[TMP17:%.*]] = load i64, ptr [[ULLD]], align 8
27237 // CHECK-NEXT:    [[TMP18:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP16]], i64 [[TMP17]] monotonic monotonic, align 8
27238 // CHECK-NEXT:    [[TMP19:%.*]] = extractvalue { i64, i1 } [[TMP18]], 0
27239 // CHECK-NEXT:    [[TMP20:%.*]] = extractvalue { i64, i1 } [[TMP18]], 1
27240 // CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[TMP16]], i64 [[TMP19]]
27241 // CHECK-NEXT:    store i64 [[TMP21]], ptr [[ULLV]], align 8
27242 // CHECK-NEXT:    [[TMP22:%.*]] = load i64, ptr [[ULLE]], align 8
27243 // CHECK-NEXT:    [[TMP23:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP22]] acq_rel, align 8
27244 // CHECK-NEXT:    store i64 [[TMP23]], ptr [[ULLV]], align 8
27245 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27246 // CHECK-NEXT:    [[TMP24:%.*]] = load i64, ptr [[ULLE]], align 8
27247 // CHECK-NEXT:    [[TMP25:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP24]] acq_rel, align 8
27248 // CHECK-NEXT:    store i64 [[TMP25]], ptr [[ULLV]], align 8
27249 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27250 // CHECK-NEXT:    [[TMP26:%.*]] = load i64, ptr [[ULLE]], align 8
27251 // CHECK-NEXT:    [[TMP27:%.*]] = load i64, ptr [[ULLD]], align 8
27252 // CHECK-NEXT:    [[TMP28:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP26]], i64 [[TMP27]] acq_rel acquire, align 8
27253 // CHECK-NEXT:    [[TMP29:%.*]] = extractvalue { i64, i1 } [[TMP28]], 0
27254 // CHECK-NEXT:    store i64 [[TMP29]], ptr [[ULLV]], align 8
27255 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27256 // CHECK-NEXT:    [[TMP30:%.*]] = load i64, ptr [[ULLE]], align 8
27257 // CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP30]] acq_rel, align 8
27258 // CHECK-NEXT:    [[TMP32:%.*]] = icmp ult i64 [[TMP31]], [[TMP30]]
27259 // CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i64 [[TMP30]], i64 [[TMP31]]
27260 // CHECK-NEXT:    store i64 [[TMP33]], ptr [[ULLV]], align 8
27261 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27262 // CHECK-NEXT:    [[TMP34:%.*]] = load i64, ptr [[ULLE]], align 8
27263 // CHECK-NEXT:    [[TMP35:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP34]] acq_rel, align 8
27264 // CHECK-NEXT:    [[TMP36:%.*]] = icmp ugt i64 [[TMP35]], [[TMP34]]
27265 // CHECK-NEXT:    [[TMP37:%.*]] = select i1 [[TMP36]], i64 [[TMP34]], i64 [[TMP35]]
27266 // CHECK-NEXT:    store i64 [[TMP37]], ptr [[ULLV]], align 8
27267 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27268 // CHECK-NEXT:    [[TMP38:%.*]] = load i64, ptr [[ULLE]], align 8
27269 // CHECK-NEXT:    [[TMP39:%.*]] = load i64, ptr [[ULLD]], align 8
27270 // CHECK-NEXT:    [[TMP40:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP38]], i64 [[TMP39]] acq_rel acquire, align 8
27271 // CHECK-NEXT:    [[TMP41:%.*]] = extractvalue { i64, i1 } [[TMP40]], 0
27272 // CHECK-NEXT:    [[TMP42:%.*]] = extractvalue { i64, i1 } [[TMP40]], 1
27273 // CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i64 [[TMP38]], i64 [[TMP41]]
27274 // CHECK-NEXT:    store i64 [[TMP43]], ptr [[ULLV]], align 8
27275 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27276 // CHECK-NEXT:    [[TMP44:%.*]] = load i64, ptr [[ULLE]], align 8
27277 // CHECK-NEXT:    [[TMP45:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP44]] acquire, align 8
27278 // CHECK-NEXT:    store i64 [[TMP45]], ptr [[ULLV]], align 8
27279 // CHECK-NEXT:    [[TMP46:%.*]] = load i64, ptr [[ULLE]], align 8
27280 // CHECK-NEXT:    [[TMP47:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP46]] acquire, align 8
27281 // CHECK-NEXT:    store i64 [[TMP47]], ptr [[ULLV]], align 8
27282 // CHECK-NEXT:    [[TMP48:%.*]] = load i64, ptr [[ULLE]], align 8
27283 // CHECK-NEXT:    [[TMP49:%.*]] = load i64, ptr [[ULLD]], align 8
27284 // CHECK-NEXT:    [[TMP50:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP48]], i64 [[TMP49]] acquire acquire, align 8
27285 // CHECK-NEXT:    [[TMP51:%.*]] = extractvalue { i64, i1 } [[TMP50]], 0
27286 // CHECK-NEXT:    store i64 [[TMP51]], ptr [[ULLV]], align 8
27287 // CHECK-NEXT:    [[TMP52:%.*]] = load i64, ptr [[ULLE]], align 8
27288 // CHECK-NEXT:    [[TMP53:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP52]] acquire, align 8
27289 // CHECK-NEXT:    [[TMP54:%.*]] = icmp ult i64 [[TMP53]], [[TMP52]]
27290 // CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], i64 [[TMP52]], i64 [[TMP53]]
27291 // CHECK-NEXT:    store i64 [[TMP55]], ptr [[ULLV]], align 8
27292 // CHECK-NEXT:    [[TMP56:%.*]] = load i64, ptr [[ULLE]], align 8
27293 // CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP56]] acquire, align 8
27294 // CHECK-NEXT:    [[TMP58:%.*]] = icmp ugt i64 [[TMP57]], [[TMP56]]
27295 // CHECK-NEXT:    [[TMP59:%.*]] = select i1 [[TMP58]], i64 [[TMP56]], i64 [[TMP57]]
27296 // CHECK-NEXT:    store i64 [[TMP59]], ptr [[ULLV]], align 8
27297 // CHECK-NEXT:    [[TMP60:%.*]] = load i64, ptr [[ULLE]], align 8
27298 // CHECK-NEXT:    [[TMP61:%.*]] = load i64, ptr [[ULLD]], align 8
27299 // CHECK-NEXT:    [[TMP62:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP60]], i64 [[TMP61]] acquire acquire, align 8
27300 // CHECK-NEXT:    [[TMP63:%.*]] = extractvalue { i64, i1 } [[TMP62]], 0
27301 // CHECK-NEXT:    [[TMP64:%.*]] = extractvalue { i64, i1 } [[TMP62]], 1
27302 // CHECK-NEXT:    [[TMP65:%.*]] = select i1 [[TMP64]], i64 [[TMP60]], i64 [[TMP63]]
27303 // CHECK-NEXT:    store i64 [[TMP65]], ptr [[ULLV]], align 8
27304 // CHECK-NEXT:    [[TMP66:%.*]] = load i64, ptr [[ULLE]], align 8
27305 // CHECK-NEXT:    [[TMP67:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP66]] monotonic, align 8
27306 // CHECK-NEXT:    store i64 [[TMP67]], ptr [[ULLV]], align 8
27307 // CHECK-NEXT:    [[TMP68:%.*]] = load i64, ptr [[ULLE]], align 8
27308 // CHECK-NEXT:    [[TMP69:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP68]] monotonic, align 8
27309 // CHECK-NEXT:    store i64 [[TMP69]], ptr [[ULLV]], align 8
27310 // CHECK-NEXT:    [[TMP70:%.*]] = load i64, ptr [[ULLE]], align 8
27311 // CHECK-NEXT:    [[TMP71:%.*]] = load i64, ptr [[ULLD]], align 8
27312 // CHECK-NEXT:    [[TMP72:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP70]], i64 [[TMP71]] monotonic monotonic, align 8
27313 // CHECK-NEXT:    [[TMP73:%.*]] = extractvalue { i64, i1 } [[TMP72]], 0
27314 // CHECK-NEXT:    store i64 [[TMP73]], ptr [[ULLV]], align 8
27315 // CHECK-NEXT:    [[TMP74:%.*]] = load i64, ptr [[ULLE]], align 8
27316 // CHECK-NEXT:    [[TMP75:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP74]] monotonic, align 8
27317 // CHECK-NEXT:    [[TMP76:%.*]] = icmp ult i64 [[TMP75]], [[TMP74]]
27318 // CHECK-NEXT:    [[TMP77:%.*]] = select i1 [[TMP76]], i64 [[TMP74]], i64 [[TMP75]]
27319 // CHECK-NEXT:    store i64 [[TMP77]], ptr [[ULLV]], align 8
27320 // CHECK-NEXT:    [[TMP78:%.*]] = load i64, ptr [[ULLE]], align 8
27321 // CHECK-NEXT:    [[TMP79:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP78]] monotonic, align 8
27322 // CHECK-NEXT:    [[TMP80:%.*]] = icmp ugt i64 [[TMP79]], [[TMP78]]
27323 // CHECK-NEXT:    [[TMP81:%.*]] = select i1 [[TMP80]], i64 [[TMP78]], i64 [[TMP79]]
27324 // CHECK-NEXT:    store i64 [[TMP81]], ptr [[ULLV]], align 8
27325 // CHECK-NEXT:    [[TMP82:%.*]] = load i64, ptr [[ULLE]], align 8
27326 // CHECK-NEXT:    [[TMP83:%.*]] = load i64, ptr [[ULLD]], align 8
27327 // CHECK-NEXT:    [[TMP84:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP82]], i64 [[TMP83]] monotonic monotonic, align 8
27328 // CHECK-NEXT:    [[TMP85:%.*]] = extractvalue { i64, i1 } [[TMP84]], 0
27329 // CHECK-NEXT:    [[TMP86:%.*]] = extractvalue { i64, i1 } [[TMP84]], 1
27330 // CHECK-NEXT:    [[TMP87:%.*]] = select i1 [[TMP86]], i64 [[TMP82]], i64 [[TMP85]]
27331 // CHECK-NEXT:    store i64 [[TMP87]], ptr [[ULLV]], align 8
27332 // CHECK-NEXT:    [[TMP88:%.*]] = load i64, ptr [[ULLE]], align 8
27333 // CHECK-NEXT:    [[TMP89:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP88]] release, align 8
27334 // CHECK-NEXT:    store i64 [[TMP89]], ptr [[ULLV]], align 8
27335 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27336 // CHECK-NEXT:    [[TMP90:%.*]] = load i64, ptr [[ULLE]], align 8
27337 // CHECK-NEXT:    [[TMP91:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP90]] release, align 8
27338 // CHECK-NEXT:    store i64 [[TMP91]], ptr [[ULLV]], align 8
27339 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27340 // CHECK-NEXT:    [[TMP92:%.*]] = load i64, ptr [[ULLE]], align 8
27341 // CHECK-NEXT:    [[TMP93:%.*]] = load i64, ptr [[ULLD]], align 8
27342 // CHECK-NEXT:    [[TMP94:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP92]], i64 [[TMP93]] release monotonic, align 8
27343 // CHECK-NEXT:    [[TMP95:%.*]] = extractvalue { i64, i1 } [[TMP94]], 0
27344 // CHECK-NEXT:    store i64 [[TMP95]], ptr [[ULLV]], align 8
27345 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27346 // CHECK-NEXT:    [[TMP96:%.*]] = load i64, ptr [[ULLE]], align 8
27347 // CHECK-NEXT:    [[TMP97:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP96]] release, align 8
27348 // CHECK-NEXT:    [[TMP98:%.*]] = icmp ult i64 [[TMP97]], [[TMP96]]
27349 // CHECK-NEXT:    [[TMP99:%.*]] = select i1 [[TMP98]], i64 [[TMP96]], i64 [[TMP97]]
27350 // CHECK-NEXT:    store i64 [[TMP99]], ptr [[ULLV]], align 8
27351 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27352 // CHECK-NEXT:    [[TMP100:%.*]] = load i64, ptr [[ULLE]], align 8
27353 // CHECK-NEXT:    [[TMP101:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP100]] release, align 8
27354 // CHECK-NEXT:    [[TMP102:%.*]] = icmp ugt i64 [[TMP101]], [[TMP100]]
27355 // CHECK-NEXT:    [[TMP103:%.*]] = select i1 [[TMP102]], i64 [[TMP100]], i64 [[TMP101]]
27356 // CHECK-NEXT:    store i64 [[TMP103]], ptr [[ULLV]], align 8
27357 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27358 // CHECK-NEXT:    [[TMP104:%.*]] = load i64, ptr [[ULLE]], align 8
27359 // CHECK-NEXT:    [[TMP105:%.*]] = load i64, ptr [[ULLD]], align 8
27360 // CHECK-NEXT:    [[TMP106:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP104]], i64 [[TMP105]] release monotonic, align 8
27361 // CHECK-NEXT:    [[TMP107:%.*]] = extractvalue { i64, i1 } [[TMP106]], 0
27362 // CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP106]], 1
27363 // CHECK-NEXT:    [[TMP109:%.*]] = select i1 [[TMP108]], i64 [[TMP104]], i64 [[TMP107]]
27364 // CHECK-NEXT:    store i64 [[TMP109]], ptr [[ULLV]], align 8
27365 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27366 // CHECK-NEXT:    [[TMP110:%.*]] = load i64, ptr [[ULLE]], align 8
27367 // CHECK-NEXT:    [[TMP111:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP110]] seq_cst, align 8
27368 // CHECK-NEXT:    store i64 [[TMP111]], ptr [[ULLV]], align 8
27369 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27370 // CHECK-NEXT:    [[TMP112:%.*]] = load i64, ptr [[ULLE]], align 8
27371 // CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP112]] seq_cst, align 8
27372 // CHECK-NEXT:    store i64 [[TMP113]], ptr [[ULLV]], align 8
27373 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27374 // CHECK-NEXT:    [[TMP114:%.*]] = load i64, ptr [[ULLE]], align 8
27375 // CHECK-NEXT:    [[TMP115:%.*]] = load i64, ptr [[ULLD]], align 8
27376 // CHECK-NEXT:    [[TMP116:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP114]], i64 [[TMP115]] seq_cst seq_cst, align 8
27377 // CHECK-NEXT:    [[TMP117:%.*]] = extractvalue { i64, i1 } [[TMP116]], 0
27378 // CHECK-NEXT:    store i64 [[TMP117]], ptr [[ULLV]], align 8
27379 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27380 // CHECK-NEXT:    [[TMP118:%.*]] = load i64, ptr [[ULLE]], align 8
27381 // CHECK-NEXT:    [[TMP119:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP118]] seq_cst, align 8
27382 // CHECK-NEXT:    [[TMP120:%.*]] = icmp ult i64 [[TMP119]], [[TMP118]]
27383 // CHECK-NEXT:    [[TMP121:%.*]] = select i1 [[TMP120]], i64 [[TMP118]], i64 [[TMP119]]
27384 // CHECK-NEXT:    store i64 [[TMP121]], ptr [[ULLV]], align 8
27385 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27386 // CHECK-NEXT:    [[TMP122:%.*]] = load i64, ptr [[ULLE]], align 8
27387 // CHECK-NEXT:    [[TMP123:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP122]] seq_cst, align 8
27388 // CHECK-NEXT:    [[TMP124:%.*]] = icmp ugt i64 [[TMP123]], [[TMP122]]
27389 // CHECK-NEXT:    [[TMP125:%.*]] = select i1 [[TMP124]], i64 [[TMP122]], i64 [[TMP123]]
27390 // CHECK-NEXT:    store i64 [[TMP125]], ptr [[ULLV]], align 8
27391 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27392 // CHECK-NEXT:    [[TMP126:%.*]] = load i64, ptr [[ULLE]], align 8
27393 // CHECK-NEXT:    [[TMP127:%.*]] = load i64, ptr [[ULLD]], align 8
27394 // CHECK-NEXT:    [[TMP128:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP126]], i64 [[TMP127]] seq_cst seq_cst, align 8
27395 // CHECK-NEXT:    [[TMP129:%.*]] = extractvalue { i64, i1 } [[TMP128]], 0
27396 // CHECK-NEXT:    [[TMP130:%.*]] = extractvalue { i64, i1 } [[TMP128]], 1
27397 // CHECK-NEXT:    [[TMP131:%.*]] = select i1 [[TMP130]], i64 [[TMP126]], i64 [[TMP129]]
27398 // CHECK-NEXT:    store i64 [[TMP131]], ptr [[ULLV]], align 8
27399 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27400 // CHECK-NEXT:    [[TMP132:%.*]] = load i64, ptr [[ULLV]], align 8
27401 // CHECK-NEXT:    ret i64 [[TMP132]]
27402 //
27403 //
27404 // CHECK-LABEL: @fxevd(
27405 // CHECK-NEXT:  entry:
27406 // CHECK-NEXT:    [[FX:%.*]] = alloca float, align 4
27407 // CHECK-NEXT:    [[FV:%.*]] = alloca float, align 4
27408 // CHECK-NEXT:    [[FE:%.*]] = alloca float, align 4
27409 // CHECK-NEXT:    [[FD:%.*]] = alloca float, align 4
27410 // CHECK-NEXT:    [[TMP0:%.*]] = load float, ptr [[FE]], align 4
27411 // CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP0]] monotonic, align 4
27412 // CHECK-NEXT:    store float [[TMP1]], ptr [[FV]], align 4
27413 // CHECK-NEXT:    [[TMP2:%.*]] = load float, ptr [[FE]], align 4
27414 // CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP2]] monotonic, align 4
27415 // CHECK-NEXT:    store float [[TMP3]], ptr [[FV]], align 4
27416 // CHECK-NEXT:    [[TMP4:%.*]] = load float, ptr [[FE]], align 4
27417 // CHECK-NEXT:    [[TMP5:%.*]] = load float, ptr [[FD]], align 4
27418 // CHECK-NEXT:    [[TMP6:%.*]] = bitcast float [[TMP4]] to i32
27419 // CHECK-NEXT:    [[TMP7:%.*]] = bitcast float [[TMP5]] to i32
27420 // CHECK-NEXT:    [[TMP8:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP6]], i32 [[TMP7]] monotonic monotonic, align 4
27421 // CHECK-NEXT:    [[TMP9:%.*]] = extractvalue { i32, i1 } [[TMP8]], 0
27422 // CHECK-NEXT:    [[TMP10:%.*]] = bitcast i32 [[TMP9]] to float
27423 // CHECK-NEXT:    store float [[TMP10]], ptr [[FV]], align 4
27424 // CHECK-NEXT:    [[TMP11:%.*]] = load float, ptr [[FE]], align 4
27425 // CHECK-NEXT:    [[TMP12:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP11]] monotonic, align 4
27426 // CHECK-NEXT:    [[TMP13:%.*]] = fcmp olt float [[TMP12]], [[TMP11]]
27427 // CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], float [[TMP11]], float [[TMP12]]
27428 // CHECK-NEXT:    store float [[TMP14]], ptr [[FV]], align 4
27429 // CHECK-NEXT:    [[TMP15:%.*]] = load float, ptr [[FE]], align 4
27430 // CHECK-NEXT:    [[TMP16:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP15]] monotonic, align 4
27431 // CHECK-NEXT:    [[TMP17:%.*]] = fcmp ogt float [[TMP16]], [[TMP15]]
27432 // CHECK-NEXT:    [[TMP18:%.*]] = select i1 [[TMP17]], float [[TMP15]], float [[TMP16]]
27433 // CHECK-NEXT:    store float [[TMP18]], ptr [[FV]], align 4
27434 // CHECK-NEXT:    [[TMP19:%.*]] = load float, ptr [[FE]], align 4
27435 // CHECK-NEXT:    [[TMP20:%.*]] = load float, ptr [[FD]], align 4
27436 // CHECK-NEXT:    [[TMP21:%.*]] = bitcast float [[TMP19]] to i32
27437 // CHECK-NEXT:    [[TMP22:%.*]] = bitcast float [[TMP20]] to i32
27438 // CHECK-NEXT:    [[TMP23:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP21]], i32 [[TMP22]] monotonic monotonic, align 4
27439 // CHECK-NEXT:    [[TMP24:%.*]] = extractvalue { i32, i1 } [[TMP23]], 0
27440 // CHECK-NEXT:    [[TMP25:%.*]] = bitcast i32 [[TMP24]] to float
27441 // CHECK-NEXT:    [[TMP26:%.*]] = extractvalue { i32, i1 } [[TMP23]], 1
27442 // CHECK-NEXT:    [[TMP27:%.*]] = select i1 [[TMP26]], float [[TMP19]], float [[TMP25]]
27443 // CHECK-NEXT:    store float [[TMP27]], ptr [[FV]], align 4
27444 // CHECK-NEXT:    [[TMP28:%.*]] = load float, ptr [[FE]], align 4
27445 // CHECK-NEXT:    [[TMP29:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP28]] acq_rel, align 4
27446 // CHECK-NEXT:    store float [[TMP29]], ptr [[FV]], align 4
27447 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27448 // CHECK-NEXT:    [[TMP30:%.*]] = load float, ptr [[FE]], align 4
27449 // CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP30]] acq_rel, align 4
27450 // CHECK-NEXT:    store float [[TMP31]], ptr [[FV]], align 4
27451 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27452 // CHECK-NEXT:    [[TMP32:%.*]] = load float, ptr [[FE]], align 4
27453 // CHECK-NEXT:    [[TMP33:%.*]] = load float, ptr [[FD]], align 4
27454 // CHECK-NEXT:    [[TMP34:%.*]] = bitcast float [[TMP32]] to i32
27455 // CHECK-NEXT:    [[TMP35:%.*]] = bitcast float [[TMP33]] to i32
27456 // CHECK-NEXT:    [[TMP36:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP34]], i32 [[TMP35]] acq_rel acquire, align 4
27457 // CHECK-NEXT:    [[TMP37:%.*]] = extractvalue { i32, i1 } [[TMP36]], 0
27458 // CHECK-NEXT:    [[TMP38:%.*]] = bitcast i32 [[TMP37]] to float
27459 // CHECK-NEXT:    store float [[TMP38]], ptr [[FV]], align 4
27460 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27461 // CHECK-NEXT:    [[TMP39:%.*]] = load float, ptr [[FE]], align 4
27462 // CHECK-NEXT:    [[TMP40:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP39]] acq_rel, align 4
27463 // CHECK-NEXT:    [[TMP41:%.*]] = fcmp olt float [[TMP40]], [[TMP39]]
27464 // CHECK-NEXT:    [[TMP42:%.*]] = select i1 [[TMP41]], float [[TMP39]], float [[TMP40]]
27465 // CHECK-NEXT:    store float [[TMP42]], ptr [[FV]], align 4
27466 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27467 // CHECK-NEXT:    [[TMP43:%.*]] = load float, ptr [[FE]], align 4
27468 // CHECK-NEXT:    [[TMP44:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP43]] acq_rel, align 4
27469 // CHECK-NEXT:    [[TMP45:%.*]] = fcmp ogt float [[TMP44]], [[TMP43]]
27470 // CHECK-NEXT:    [[TMP46:%.*]] = select i1 [[TMP45]], float [[TMP43]], float [[TMP44]]
27471 // CHECK-NEXT:    store float [[TMP46]], ptr [[FV]], align 4
27472 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27473 // CHECK-NEXT:    [[TMP47:%.*]] = load float, ptr [[FE]], align 4
27474 // CHECK-NEXT:    [[TMP48:%.*]] = load float, ptr [[FD]], align 4
27475 // CHECK-NEXT:    [[TMP49:%.*]] = bitcast float [[TMP47]] to i32
27476 // CHECK-NEXT:    [[TMP50:%.*]] = bitcast float [[TMP48]] to i32
27477 // CHECK-NEXT:    [[TMP51:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP49]], i32 [[TMP50]] acq_rel acquire, align 4
27478 // CHECK-NEXT:    [[TMP52:%.*]] = extractvalue { i32, i1 } [[TMP51]], 0
27479 // CHECK-NEXT:    [[TMP53:%.*]] = bitcast i32 [[TMP52]] to float
27480 // CHECK-NEXT:    [[TMP54:%.*]] = extractvalue { i32, i1 } [[TMP51]], 1
27481 // CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], float [[TMP47]], float [[TMP53]]
27482 // CHECK-NEXT:    store float [[TMP55]], ptr [[FV]], align 4
27483 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27484 // CHECK-NEXT:    [[TMP56:%.*]] = load float, ptr [[FE]], align 4
27485 // CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP56]] acquire, align 4
27486 // CHECK-NEXT:    store float [[TMP57]], ptr [[FV]], align 4
27487 // CHECK-NEXT:    [[TMP58:%.*]] = load float, ptr [[FE]], align 4
27488 // CHECK-NEXT:    [[TMP59:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP58]] acquire, align 4
27489 // CHECK-NEXT:    store float [[TMP59]], ptr [[FV]], align 4
27490 // CHECK-NEXT:    [[TMP60:%.*]] = load float, ptr [[FE]], align 4
27491 // CHECK-NEXT:    [[TMP61:%.*]] = load float, ptr [[FD]], align 4
27492 // CHECK-NEXT:    [[TMP62:%.*]] = bitcast float [[TMP60]] to i32
27493 // CHECK-NEXT:    [[TMP63:%.*]] = bitcast float [[TMP61]] to i32
27494 // CHECK-NEXT:    [[TMP64:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP62]], i32 [[TMP63]] acquire acquire, align 4
27495 // CHECK-NEXT:    [[TMP65:%.*]] = extractvalue { i32, i1 } [[TMP64]], 0
27496 // CHECK-NEXT:    [[TMP66:%.*]] = bitcast i32 [[TMP65]] to float
27497 // CHECK-NEXT:    store float [[TMP66]], ptr [[FV]], align 4
27498 // CHECK-NEXT:    [[TMP67:%.*]] = load float, ptr [[FE]], align 4
27499 // CHECK-NEXT:    [[TMP68:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP67]] acquire, align 4
27500 // CHECK-NEXT:    [[TMP69:%.*]] = fcmp olt float [[TMP68]], [[TMP67]]
27501 // CHECK-NEXT:    [[TMP70:%.*]] = select i1 [[TMP69]], float [[TMP67]], float [[TMP68]]
27502 // CHECK-NEXT:    store float [[TMP70]], ptr [[FV]], align 4
27503 // CHECK-NEXT:    [[TMP71:%.*]] = load float, ptr [[FE]], align 4
27504 // CHECK-NEXT:    [[TMP72:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP71]] acquire, align 4
27505 // CHECK-NEXT:    [[TMP73:%.*]] = fcmp ogt float [[TMP72]], [[TMP71]]
27506 // CHECK-NEXT:    [[TMP74:%.*]] = select i1 [[TMP73]], float [[TMP71]], float [[TMP72]]
27507 // CHECK-NEXT:    store float [[TMP74]], ptr [[FV]], align 4
27508 // CHECK-NEXT:    [[TMP75:%.*]] = load float, ptr [[FE]], align 4
27509 // CHECK-NEXT:    [[TMP76:%.*]] = load float, ptr [[FD]], align 4
27510 // CHECK-NEXT:    [[TMP77:%.*]] = bitcast float [[TMP75]] to i32
27511 // CHECK-NEXT:    [[TMP78:%.*]] = bitcast float [[TMP76]] to i32
27512 // CHECK-NEXT:    [[TMP79:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP77]], i32 [[TMP78]] acquire acquire, align 4
27513 // CHECK-NEXT:    [[TMP80:%.*]] = extractvalue { i32, i1 } [[TMP79]], 0
27514 // CHECK-NEXT:    [[TMP81:%.*]] = bitcast i32 [[TMP80]] to float
27515 // CHECK-NEXT:    [[TMP82:%.*]] = extractvalue { i32, i1 } [[TMP79]], 1
27516 // CHECK-NEXT:    [[TMP83:%.*]] = select i1 [[TMP82]], float [[TMP75]], float [[TMP81]]
27517 // CHECK-NEXT:    store float [[TMP83]], ptr [[FV]], align 4
27518 // CHECK-NEXT:    [[TMP84:%.*]] = load float, ptr [[FE]], align 4
27519 // CHECK-NEXT:    [[TMP85:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP84]] monotonic, align 4
27520 // CHECK-NEXT:    store float [[TMP85]], ptr [[FV]], align 4
27521 // CHECK-NEXT:    [[TMP86:%.*]] = load float, ptr [[FE]], align 4
27522 // CHECK-NEXT:    [[TMP87:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP86]] monotonic, align 4
27523 // CHECK-NEXT:    store float [[TMP87]], ptr [[FV]], align 4
27524 // CHECK-NEXT:    [[TMP88:%.*]] = load float, ptr [[FE]], align 4
27525 // CHECK-NEXT:    [[TMP89:%.*]] = load float, ptr [[FD]], align 4
27526 // CHECK-NEXT:    [[TMP90:%.*]] = bitcast float [[TMP88]] to i32
27527 // CHECK-NEXT:    [[TMP91:%.*]] = bitcast float [[TMP89]] to i32
27528 // CHECK-NEXT:    [[TMP92:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP90]], i32 [[TMP91]] monotonic monotonic, align 4
27529 // CHECK-NEXT:    [[TMP93:%.*]] = extractvalue { i32, i1 } [[TMP92]], 0
27530 // CHECK-NEXT:    [[TMP94:%.*]] = bitcast i32 [[TMP93]] to float
27531 // CHECK-NEXT:    store float [[TMP94]], ptr [[FV]], align 4
27532 // CHECK-NEXT:    [[TMP95:%.*]] = load float, ptr [[FE]], align 4
27533 // CHECK-NEXT:    [[TMP96:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP95]] monotonic, align 4
27534 // CHECK-NEXT:    [[TMP97:%.*]] = fcmp olt float [[TMP96]], [[TMP95]]
27535 // CHECK-NEXT:    [[TMP98:%.*]] = select i1 [[TMP97]], float [[TMP95]], float [[TMP96]]
27536 // CHECK-NEXT:    store float [[TMP98]], ptr [[FV]], align 4
27537 // CHECK-NEXT:    [[TMP99:%.*]] = load float, ptr [[FE]], align 4
27538 // CHECK-NEXT:    [[TMP100:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP99]] monotonic, align 4
27539 // CHECK-NEXT:    [[TMP101:%.*]] = fcmp ogt float [[TMP100]], [[TMP99]]
27540 // CHECK-NEXT:    [[TMP102:%.*]] = select i1 [[TMP101]], float [[TMP99]], float [[TMP100]]
27541 // CHECK-NEXT:    store float [[TMP102]], ptr [[FV]], align 4
27542 // CHECK-NEXT:    [[TMP103:%.*]] = load float, ptr [[FE]], align 4
27543 // CHECK-NEXT:    [[TMP104:%.*]] = load float, ptr [[FD]], align 4
27544 // CHECK-NEXT:    [[TMP105:%.*]] = bitcast float [[TMP103]] to i32
27545 // CHECK-NEXT:    [[TMP106:%.*]] = bitcast float [[TMP104]] to i32
27546 // CHECK-NEXT:    [[TMP107:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP105]], i32 [[TMP106]] monotonic monotonic, align 4
27547 // CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i32, i1 } [[TMP107]], 0
27548 // CHECK-NEXT:    [[TMP109:%.*]] = bitcast i32 [[TMP108]] to float
27549 // CHECK-NEXT:    [[TMP110:%.*]] = extractvalue { i32, i1 } [[TMP107]], 1
27550 // CHECK-NEXT:    [[TMP111:%.*]] = select i1 [[TMP110]], float [[TMP103]], float [[TMP109]]
27551 // CHECK-NEXT:    store float [[TMP111]], ptr [[FV]], align 4
27552 // CHECK-NEXT:    [[TMP112:%.*]] = load float, ptr [[FE]], align 4
27553 // CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP112]] release, align 4
27554 // CHECK-NEXT:    store float [[TMP113]], ptr [[FV]], align 4
27555 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27556 // CHECK-NEXT:    [[TMP114:%.*]] = load float, ptr [[FE]], align 4
27557 // CHECK-NEXT:    [[TMP115:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP114]] release, align 4
27558 // CHECK-NEXT:    store float [[TMP115]], ptr [[FV]], align 4
27559 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27560 // CHECK-NEXT:    [[TMP116:%.*]] = load float, ptr [[FE]], align 4
27561 // CHECK-NEXT:    [[TMP117:%.*]] = load float, ptr [[FD]], align 4
27562 // CHECK-NEXT:    [[TMP118:%.*]] = bitcast float [[TMP116]] to i32
27563 // CHECK-NEXT:    [[TMP119:%.*]] = bitcast float [[TMP117]] to i32
27564 // CHECK-NEXT:    [[TMP120:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP118]], i32 [[TMP119]] release monotonic, align 4
27565 // CHECK-NEXT:    [[TMP121:%.*]] = extractvalue { i32, i1 } [[TMP120]], 0
27566 // CHECK-NEXT:    [[TMP122:%.*]] = bitcast i32 [[TMP121]] to float
27567 // CHECK-NEXT:    store float [[TMP122]], ptr [[FV]], align 4
27568 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27569 // CHECK-NEXT:    [[TMP123:%.*]] = load float, ptr [[FE]], align 4
27570 // CHECK-NEXT:    [[TMP124:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP123]] release, align 4
27571 // CHECK-NEXT:    [[TMP125:%.*]] = fcmp olt float [[TMP124]], [[TMP123]]
27572 // CHECK-NEXT:    [[TMP126:%.*]] = select i1 [[TMP125]], float [[TMP123]], float [[TMP124]]
27573 // CHECK-NEXT:    store float [[TMP126]], ptr [[FV]], align 4
27574 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27575 // CHECK-NEXT:    [[TMP127:%.*]] = load float, ptr [[FE]], align 4
27576 // CHECK-NEXT:    [[TMP128:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP127]] release, align 4
27577 // CHECK-NEXT:    [[TMP129:%.*]] = fcmp ogt float [[TMP128]], [[TMP127]]
27578 // CHECK-NEXT:    [[TMP130:%.*]] = select i1 [[TMP129]], float [[TMP127]], float [[TMP128]]
27579 // CHECK-NEXT:    store float [[TMP130]], ptr [[FV]], align 4
27580 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27581 // CHECK-NEXT:    [[TMP131:%.*]] = load float, ptr [[FE]], align 4
27582 // CHECK-NEXT:    [[TMP132:%.*]] = load float, ptr [[FD]], align 4
27583 // CHECK-NEXT:    [[TMP133:%.*]] = bitcast float [[TMP131]] to i32
27584 // CHECK-NEXT:    [[TMP134:%.*]] = bitcast float [[TMP132]] to i32
27585 // CHECK-NEXT:    [[TMP135:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP133]], i32 [[TMP134]] release monotonic, align 4
27586 // CHECK-NEXT:    [[TMP136:%.*]] = extractvalue { i32, i1 } [[TMP135]], 0
27587 // CHECK-NEXT:    [[TMP137:%.*]] = bitcast i32 [[TMP136]] to float
27588 // CHECK-NEXT:    [[TMP138:%.*]] = extractvalue { i32, i1 } [[TMP135]], 1
27589 // CHECK-NEXT:    [[TMP139:%.*]] = select i1 [[TMP138]], float [[TMP131]], float [[TMP137]]
27590 // CHECK-NEXT:    store float [[TMP139]], ptr [[FV]], align 4
27591 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27592 // CHECK-NEXT:    [[TMP140:%.*]] = load float, ptr [[FE]], align 4
27593 // CHECK-NEXT:    [[TMP141:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP140]] seq_cst, align 4
27594 // CHECK-NEXT:    store float [[TMP141]], ptr [[FV]], align 4
27595 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27596 // CHECK-NEXT:    [[TMP142:%.*]] = load float, ptr [[FE]], align 4
27597 // CHECK-NEXT:    [[TMP143:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP142]] seq_cst, align 4
27598 // CHECK-NEXT:    store float [[TMP143]], ptr [[FV]], align 4
27599 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27600 // CHECK-NEXT:    [[TMP144:%.*]] = load float, ptr [[FE]], align 4
27601 // CHECK-NEXT:    [[TMP145:%.*]] = load float, ptr [[FD]], align 4
27602 // CHECK-NEXT:    [[TMP146:%.*]] = bitcast float [[TMP144]] to i32
27603 // CHECK-NEXT:    [[TMP147:%.*]] = bitcast float [[TMP145]] to i32
27604 // CHECK-NEXT:    [[TMP148:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP146]], i32 [[TMP147]] seq_cst seq_cst, align 4
27605 // CHECK-NEXT:    [[TMP149:%.*]] = extractvalue { i32, i1 } [[TMP148]], 0
27606 // CHECK-NEXT:    [[TMP150:%.*]] = bitcast i32 [[TMP149]] to float
27607 // CHECK-NEXT:    store float [[TMP150]], ptr [[FV]], align 4
27608 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27609 // CHECK-NEXT:    [[TMP151:%.*]] = load float, ptr [[FE]], align 4
27610 // CHECK-NEXT:    [[TMP152:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP151]] seq_cst, align 4
27611 // CHECK-NEXT:    [[TMP153:%.*]] = fcmp olt float [[TMP152]], [[TMP151]]
27612 // CHECK-NEXT:    [[TMP154:%.*]] = select i1 [[TMP153]], float [[TMP151]], float [[TMP152]]
27613 // CHECK-NEXT:    store float [[TMP154]], ptr [[FV]], align 4
27614 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27615 // CHECK-NEXT:    [[TMP155:%.*]] = load float, ptr [[FE]], align 4
27616 // CHECK-NEXT:    [[TMP156:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP155]] seq_cst, align 4
27617 // CHECK-NEXT:    [[TMP157:%.*]] = fcmp ogt float [[TMP156]], [[TMP155]]
27618 // CHECK-NEXT:    [[TMP158:%.*]] = select i1 [[TMP157]], float [[TMP155]], float [[TMP156]]
27619 // CHECK-NEXT:    store float [[TMP158]], ptr [[FV]], align 4
27620 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27621 // CHECK-NEXT:    [[TMP159:%.*]] = load float, ptr [[FE]], align 4
27622 // CHECK-NEXT:    [[TMP160:%.*]] = load float, ptr [[FD]], align 4
27623 // CHECK-NEXT:    [[TMP161:%.*]] = bitcast float [[TMP159]] to i32
27624 // CHECK-NEXT:    [[TMP162:%.*]] = bitcast float [[TMP160]] to i32
27625 // CHECK-NEXT:    [[TMP163:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP161]], i32 [[TMP162]] seq_cst seq_cst, align 4
27626 // CHECK-NEXT:    [[TMP164:%.*]] = extractvalue { i32, i1 } [[TMP163]], 0
27627 // CHECK-NEXT:    [[TMP165:%.*]] = bitcast i32 [[TMP164]] to float
27628 // CHECK-NEXT:    [[TMP166:%.*]] = extractvalue { i32, i1 } [[TMP163]], 1
27629 // CHECK-NEXT:    [[TMP167:%.*]] = select i1 [[TMP166]], float [[TMP159]], float [[TMP165]]
27630 // CHECK-NEXT:    store float [[TMP167]], ptr [[FV]], align 4
27631 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27632 // CHECK-NEXT:    [[TMP168:%.*]] = load float, ptr [[FV]], align 4
27633 // CHECK-NEXT:    ret float [[TMP168]]
27634 //
27635 //
27636 // CHECK-LABEL: @dxevd(
27637 // CHECK-NEXT:  entry:
27638 // CHECK-NEXT:    [[DX:%.*]] = alloca double, align 8
27639 // CHECK-NEXT:    [[DV:%.*]] = alloca double, align 8
27640 // CHECK-NEXT:    [[DE:%.*]] = alloca double, align 8
27641 // CHECK-NEXT:    [[DD:%.*]] = alloca double, align 8
27642 // CHECK-NEXT:    [[TMP0:%.*]] = load double, ptr [[DE]], align 8
27643 // CHECK-NEXT:    [[TMP1:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP0]] monotonic, align 8
27644 // CHECK-NEXT:    store double [[TMP1]], ptr [[DV]], align 8
27645 // CHECK-NEXT:    [[TMP2:%.*]] = load double, ptr [[DE]], align 8
27646 // CHECK-NEXT:    [[TMP3:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP2]] monotonic, align 8
27647 // CHECK-NEXT:    store double [[TMP3]], ptr [[DV]], align 8
27648 // CHECK-NEXT:    [[TMP4:%.*]] = load double, ptr [[DE]], align 8
27649 // CHECK-NEXT:    [[TMP5:%.*]] = load double, ptr [[DD]], align 8
27650 // CHECK-NEXT:    [[TMP6:%.*]] = bitcast double [[TMP4]] to i64
27651 // CHECK-NEXT:    [[TMP7:%.*]] = bitcast double [[TMP5]] to i64
27652 // CHECK-NEXT:    [[TMP8:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP6]], i64 [[TMP7]] monotonic monotonic, align 8
27653 // CHECK-NEXT:    [[TMP9:%.*]] = extractvalue { i64, i1 } [[TMP8]], 0
27654 // CHECK-NEXT:    [[TMP10:%.*]] = bitcast i64 [[TMP9]] to double
27655 // CHECK-NEXT:    store double [[TMP10]], ptr [[DV]], align 8
27656 // CHECK-NEXT:    [[TMP11:%.*]] = load double, ptr [[DE]], align 8
27657 // CHECK-NEXT:    [[TMP12:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP11]] monotonic, align 8
27658 // CHECK-NEXT:    [[TMP13:%.*]] = fcmp olt double [[TMP12]], [[TMP11]]
27659 // CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], double [[TMP11]], double [[TMP12]]
27660 // CHECK-NEXT:    store double [[TMP14]], ptr [[DV]], align 8
27661 // CHECK-NEXT:    [[TMP15:%.*]] = load double, ptr [[DE]], align 8
27662 // CHECK-NEXT:    [[TMP16:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP15]] monotonic, align 8
27663 // CHECK-NEXT:    [[TMP17:%.*]] = fcmp ogt double [[TMP16]], [[TMP15]]
27664 // CHECK-NEXT:    [[TMP18:%.*]] = select i1 [[TMP17]], double [[TMP15]], double [[TMP16]]
27665 // CHECK-NEXT:    store double [[TMP18]], ptr [[DV]], align 8
27666 // CHECK-NEXT:    [[TMP19:%.*]] = load double, ptr [[DE]], align 8
27667 // CHECK-NEXT:    [[TMP20:%.*]] = load double, ptr [[DD]], align 8
27668 // CHECK-NEXT:    [[TMP21:%.*]] = bitcast double [[TMP19]] to i64
27669 // CHECK-NEXT:    [[TMP22:%.*]] = bitcast double [[TMP20]] to i64
27670 // CHECK-NEXT:    [[TMP23:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP21]], i64 [[TMP22]] monotonic monotonic, align 8
27671 // CHECK-NEXT:    [[TMP24:%.*]] = extractvalue { i64, i1 } [[TMP23]], 0
27672 // CHECK-NEXT:    [[TMP25:%.*]] = bitcast i64 [[TMP24]] to double
27673 // CHECK-NEXT:    [[TMP26:%.*]] = extractvalue { i64, i1 } [[TMP23]], 1
27674 // CHECK-NEXT:    [[TMP27:%.*]] = select i1 [[TMP26]], double [[TMP19]], double [[TMP25]]
27675 // CHECK-NEXT:    store double [[TMP27]], ptr [[DV]], align 8
27676 // CHECK-NEXT:    [[TMP28:%.*]] = load double, ptr [[DE]], align 8
27677 // CHECK-NEXT:    [[TMP29:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP28]] acq_rel, align 8
27678 // CHECK-NEXT:    store double [[TMP29]], ptr [[DV]], align 8
27679 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27680 // CHECK-NEXT:    [[TMP30:%.*]] = load double, ptr [[DE]], align 8
27681 // CHECK-NEXT:    [[TMP31:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP30]] acq_rel, align 8
27682 // CHECK-NEXT:    store double [[TMP31]], ptr [[DV]], align 8
27683 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27684 // CHECK-NEXT:    [[TMP32:%.*]] = load double, ptr [[DE]], align 8
27685 // CHECK-NEXT:    [[TMP33:%.*]] = load double, ptr [[DD]], align 8
27686 // CHECK-NEXT:    [[TMP34:%.*]] = bitcast double [[TMP32]] to i64
27687 // CHECK-NEXT:    [[TMP35:%.*]] = bitcast double [[TMP33]] to i64
27688 // CHECK-NEXT:    [[TMP36:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP34]], i64 [[TMP35]] acq_rel acquire, align 8
27689 // CHECK-NEXT:    [[TMP37:%.*]] = extractvalue { i64, i1 } [[TMP36]], 0
27690 // CHECK-NEXT:    [[TMP38:%.*]] = bitcast i64 [[TMP37]] to double
27691 // CHECK-NEXT:    store double [[TMP38]], ptr [[DV]], align 8
27692 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27693 // CHECK-NEXT:    [[TMP39:%.*]] = load double, ptr [[DE]], align 8
27694 // CHECK-NEXT:    [[TMP40:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP39]] acq_rel, align 8
27695 // CHECK-NEXT:    [[TMP41:%.*]] = fcmp olt double [[TMP40]], [[TMP39]]
27696 // CHECK-NEXT:    [[TMP42:%.*]] = select i1 [[TMP41]], double [[TMP39]], double [[TMP40]]
27697 // CHECK-NEXT:    store double [[TMP42]], ptr [[DV]], align 8
27698 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27699 // CHECK-NEXT:    [[TMP43:%.*]] = load double, ptr [[DE]], align 8
27700 // CHECK-NEXT:    [[TMP44:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP43]] acq_rel, align 8
27701 // CHECK-NEXT:    [[TMP45:%.*]] = fcmp ogt double [[TMP44]], [[TMP43]]
27702 // CHECK-NEXT:    [[TMP46:%.*]] = select i1 [[TMP45]], double [[TMP43]], double [[TMP44]]
27703 // CHECK-NEXT:    store double [[TMP46]], ptr [[DV]], align 8
27704 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27705 // CHECK-NEXT:    [[TMP47:%.*]] = load double, ptr [[DE]], align 8
27706 // CHECK-NEXT:    [[TMP48:%.*]] = load double, ptr [[DD]], align 8
27707 // CHECK-NEXT:    [[TMP49:%.*]] = bitcast double [[TMP47]] to i64
27708 // CHECK-NEXT:    [[TMP50:%.*]] = bitcast double [[TMP48]] to i64
27709 // CHECK-NEXT:    [[TMP51:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP49]], i64 [[TMP50]] acq_rel acquire, align 8
27710 // CHECK-NEXT:    [[TMP52:%.*]] = extractvalue { i64, i1 } [[TMP51]], 0
27711 // CHECK-NEXT:    [[TMP53:%.*]] = bitcast i64 [[TMP52]] to double
27712 // CHECK-NEXT:    [[TMP54:%.*]] = extractvalue { i64, i1 } [[TMP51]], 1
27713 // CHECK-NEXT:    [[TMP55:%.*]] = select i1 [[TMP54]], double [[TMP47]], double [[TMP53]]
27714 // CHECK-NEXT:    store double [[TMP55]], ptr [[DV]], align 8
27715 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27716 // CHECK-NEXT:    [[TMP56:%.*]] = load double, ptr [[DE]], align 8
27717 // CHECK-NEXT:    [[TMP57:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP56]] acquire, align 8
27718 // CHECK-NEXT:    store double [[TMP57]], ptr [[DV]], align 8
27719 // CHECK-NEXT:    [[TMP58:%.*]] = load double, ptr [[DE]], align 8
27720 // CHECK-NEXT:    [[TMP59:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP58]] acquire, align 8
27721 // CHECK-NEXT:    store double [[TMP59]], ptr [[DV]], align 8
27722 // CHECK-NEXT:    [[TMP60:%.*]] = load double, ptr [[DE]], align 8
27723 // CHECK-NEXT:    [[TMP61:%.*]] = load double, ptr [[DD]], align 8
27724 // CHECK-NEXT:    [[TMP62:%.*]] = bitcast double [[TMP60]] to i64
27725 // CHECK-NEXT:    [[TMP63:%.*]] = bitcast double [[TMP61]] to i64
27726 // CHECK-NEXT:    [[TMP64:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP62]], i64 [[TMP63]] acquire acquire, align 8
27727 // CHECK-NEXT:    [[TMP65:%.*]] = extractvalue { i64, i1 } [[TMP64]], 0
27728 // CHECK-NEXT:    [[TMP66:%.*]] = bitcast i64 [[TMP65]] to double
27729 // CHECK-NEXT:    store double [[TMP66]], ptr [[DV]], align 8
27730 // CHECK-NEXT:    [[TMP67:%.*]] = load double, ptr [[DE]], align 8
27731 // CHECK-NEXT:    [[TMP68:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP67]] acquire, align 8
27732 // CHECK-NEXT:    [[TMP69:%.*]] = fcmp olt double [[TMP68]], [[TMP67]]
27733 // CHECK-NEXT:    [[TMP70:%.*]] = select i1 [[TMP69]], double [[TMP67]], double [[TMP68]]
27734 // CHECK-NEXT:    store double [[TMP70]], ptr [[DV]], align 8
27735 // CHECK-NEXT:    [[TMP71:%.*]] = load double, ptr [[DE]], align 8
27736 // CHECK-NEXT:    [[TMP72:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP71]] acquire, align 8
27737 // CHECK-NEXT:    [[TMP73:%.*]] = fcmp ogt double [[TMP72]], [[TMP71]]
27738 // CHECK-NEXT:    [[TMP74:%.*]] = select i1 [[TMP73]], double [[TMP71]], double [[TMP72]]
27739 // CHECK-NEXT:    store double [[TMP74]], ptr [[DV]], align 8
27740 // CHECK-NEXT:    [[TMP75:%.*]] = load double, ptr [[DE]], align 8
27741 // CHECK-NEXT:    [[TMP76:%.*]] = load double, ptr [[DD]], align 8
27742 // CHECK-NEXT:    [[TMP77:%.*]] = bitcast double [[TMP75]] to i64
27743 // CHECK-NEXT:    [[TMP78:%.*]] = bitcast double [[TMP76]] to i64
27744 // CHECK-NEXT:    [[TMP79:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP77]], i64 [[TMP78]] acquire acquire, align 8
27745 // CHECK-NEXT:    [[TMP80:%.*]] = extractvalue { i64, i1 } [[TMP79]], 0
27746 // CHECK-NEXT:    [[TMP81:%.*]] = bitcast i64 [[TMP80]] to double
27747 // CHECK-NEXT:    [[TMP82:%.*]] = extractvalue { i64, i1 } [[TMP79]], 1
27748 // CHECK-NEXT:    [[TMP83:%.*]] = select i1 [[TMP82]], double [[TMP75]], double [[TMP81]]
27749 // CHECK-NEXT:    store double [[TMP83]], ptr [[DV]], align 8
27750 // CHECK-NEXT:    [[TMP84:%.*]] = load double, ptr [[DE]], align 8
27751 // CHECK-NEXT:    [[TMP85:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP84]] monotonic, align 8
27752 // CHECK-NEXT:    store double [[TMP85]], ptr [[DV]], align 8
27753 // CHECK-NEXT:    [[TMP86:%.*]] = load double, ptr [[DE]], align 8
27754 // CHECK-NEXT:    [[TMP87:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP86]] monotonic, align 8
27755 // CHECK-NEXT:    store double [[TMP87]], ptr [[DV]], align 8
27756 // CHECK-NEXT:    [[TMP88:%.*]] = load double, ptr [[DE]], align 8
27757 // CHECK-NEXT:    [[TMP89:%.*]] = load double, ptr [[DD]], align 8
27758 // CHECK-NEXT:    [[TMP90:%.*]] = bitcast double [[TMP88]] to i64
27759 // CHECK-NEXT:    [[TMP91:%.*]] = bitcast double [[TMP89]] to i64
27760 // CHECK-NEXT:    [[TMP92:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP90]], i64 [[TMP91]] monotonic monotonic, align 8
27761 // CHECK-NEXT:    [[TMP93:%.*]] = extractvalue { i64, i1 } [[TMP92]], 0
27762 // CHECK-NEXT:    [[TMP94:%.*]] = bitcast i64 [[TMP93]] to double
27763 // CHECK-NEXT:    store double [[TMP94]], ptr [[DV]], align 8
27764 // CHECK-NEXT:    [[TMP95:%.*]] = load double, ptr [[DE]], align 8
27765 // CHECK-NEXT:    [[TMP96:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP95]] monotonic, align 8
27766 // CHECK-NEXT:    [[TMP97:%.*]] = fcmp olt double [[TMP96]], [[TMP95]]
27767 // CHECK-NEXT:    [[TMP98:%.*]] = select i1 [[TMP97]], double [[TMP95]], double [[TMP96]]
27768 // CHECK-NEXT:    store double [[TMP98]], ptr [[DV]], align 8
27769 // CHECK-NEXT:    [[TMP99:%.*]] = load double, ptr [[DE]], align 8
27770 // CHECK-NEXT:    [[TMP100:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP99]] monotonic, align 8
27771 // CHECK-NEXT:    [[TMP101:%.*]] = fcmp ogt double [[TMP100]], [[TMP99]]
27772 // CHECK-NEXT:    [[TMP102:%.*]] = select i1 [[TMP101]], double [[TMP99]], double [[TMP100]]
27773 // CHECK-NEXT:    store double [[TMP102]], ptr [[DV]], align 8
27774 // CHECK-NEXT:    [[TMP103:%.*]] = load double, ptr [[DE]], align 8
27775 // CHECK-NEXT:    [[TMP104:%.*]] = load double, ptr [[DD]], align 8
27776 // CHECK-NEXT:    [[TMP105:%.*]] = bitcast double [[TMP103]] to i64
27777 // CHECK-NEXT:    [[TMP106:%.*]] = bitcast double [[TMP104]] to i64
27778 // CHECK-NEXT:    [[TMP107:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP105]], i64 [[TMP106]] monotonic monotonic, align 8
27779 // CHECK-NEXT:    [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP107]], 0
27780 // CHECK-NEXT:    [[TMP109:%.*]] = bitcast i64 [[TMP108]] to double
27781 // CHECK-NEXT:    [[TMP110:%.*]] = extractvalue { i64, i1 } [[TMP107]], 1
27782 // CHECK-NEXT:    [[TMP111:%.*]] = select i1 [[TMP110]], double [[TMP103]], double [[TMP109]]
27783 // CHECK-NEXT:    store double [[TMP111]], ptr [[DV]], align 8
27784 // CHECK-NEXT:    [[TMP112:%.*]] = load double, ptr [[DE]], align 8
27785 // CHECK-NEXT:    [[TMP113:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP112]] release, align 8
27786 // CHECK-NEXT:    store double [[TMP113]], ptr [[DV]], align 8
27787 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27788 // CHECK-NEXT:    [[TMP114:%.*]] = load double, ptr [[DE]], align 8
27789 // CHECK-NEXT:    [[TMP115:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP114]] release, align 8
27790 // CHECK-NEXT:    store double [[TMP115]], ptr [[DV]], align 8
27791 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27792 // CHECK-NEXT:    [[TMP116:%.*]] = load double, ptr [[DE]], align 8
27793 // CHECK-NEXT:    [[TMP117:%.*]] = load double, ptr [[DD]], align 8
27794 // CHECK-NEXT:    [[TMP118:%.*]] = bitcast double [[TMP116]] to i64
27795 // CHECK-NEXT:    [[TMP119:%.*]] = bitcast double [[TMP117]] to i64
27796 // CHECK-NEXT:    [[TMP120:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP118]], i64 [[TMP119]] release monotonic, align 8
27797 // CHECK-NEXT:    [[TMP121:%.*]] = extractvalue { i64, i1 } [[TMP120]], 0
27798 // CHECK-NEXT:    [[TMP122:%.*]] = bitcast i64 [[TMP121]] to double
27799 // CHECK-NEXT:    store double [[TMP122]], ptr [[DV]], align 8
27800 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27801 // CHECK-NEXT:    [[TMP123:%.*]] = load double, ptr [[DE]], align 8
27802 // CHECK-NEXT:    [[TMP124:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP123]] release, align 8
27803 // CHECK-NEXT:    [[TMP125:%.*]] = fcmp olt double [[TMP124]], [[TMP123]]
27804 // CHECK-NEXT:    [[TMP126:%.*]] = select i1 [[TMP125]], double [[TMP123]], double [[TMP124]]
27805 // CHECK-NEXT:    store double [[TMP126]], ptr [[DV]], align 8
27806 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27807 // CHECK-NEXT:    [[TMP127:%.*]] = load double, ptr [[DE]], align 8
27808 // CHECK-NEXT:    [[TMP128:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP127]] release, align 8
27809 // CHECK-NEXT:    [[TMP129:%.*]] = fcmp ogt double [[TMP128]], [[TMP127]]
27810 // CHECK-NEXT:    [[TMP130:%.*]] = select i1 [[TMP129]], double [[TMP127]], double [[TMP128]]
27811 // CHECK-NEXT:    store double [[TMP130]], ptr [[DV]], align 8
27812 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27813 // CHECK-NEXT:    [[TMP131:%.*]] = load double, ptr [[DE]], align 8
27814 // CHECK-NEXT:    [[TMP132:%.*]] = load double, ptr [[DD]], align 8
27815 // CHECK-NEXT:    [[TMP133:%.*]] = bitcast double [[TMP131]] to i64
27816 // CHECK-NEXT:    [[TMP134:%.*]] = bitcast double [[TMP132]] to i64
27817 // CHECK-NEXT:    [[TMP135:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP133]], i64 [[TMP134]] release monotonic, align 8
27818 // CHECK-NEXT:    [[TMP136:%.*]] = extractvalue { i64, i1 } [[TMP135]], 0
27819 // CHECK-NEXT:    [[TMP137:%.*]] = bitcast i64 [[TMP136]] to double
27820 // CHECK-NEXT:    [[TMP138:%.*]] = extractvalue { i64, i1 } [[TMP135]], 1
27821 // CHECK-NEXT:    [[TMP139:%.*]] = select i1 [[TMP138]], double [[TMP131]], double [[TMP137]]
27822 // CHECK-NEXT:    store double [[TMP139]], ptr [[DV]], align 8
27823 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27824 // CHECK-NEXT:    [[TMP140:%.*]] = load double, ptr [[DE]], align 8
27825 // CHECK-NEXT:    [[TMP141:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP140]] seq_cst, align 8
27826 // CHECK-NEXT:    store double [[TMP141]], ptr [[DV]], align 8
27827 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27828 // CHECK-NEXT:    [[TMP142:%.*]] = load double, ptr [[DE]], align 8
27829 // CHECK-NEXT:    [[TMP143:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP142]] seq_cst, align 8
27830 // CHECK-NEXT:    store double [[TMP143]], ptr [[DV]], align 8
27831 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27832 // CHECK-NEXT:    [[TMP144:%.*]] = load double, ptr [[DE]], align 8
27833 // CHECK-NEXT:    [[TMP145:%.*]] = load double, ptr [[DD]], align 8
27834 // CHECK-NEXT:    [[TMP146:%.*]] = bitcast double [[TMP144]] to i64
27835 // CHECK-NEXT:    [[TMP147:%.*]] = bitcast double [[TMP145]] to i64
27836 // CHECK-NEXT:    [[TMP148:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP146]], i64 [[TMP147]] seq_cst seq_cst, align 8
27837 // CHECK-NEXT:    [[TMP149:%.*]] = extractvalue { i64, i1 } [[TMP148]], 0
27838 // CHECK-NEXT:    [[TMP150:%.*]] = bitcast i64 [[TMP149]] to double
27839 // CHECK-NEXT:    store double [[TMP150]], ptr [[DV]], align 8
27840 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27841 // CHECK-NEXT:    [[TMP151:%.*]] = load double, ptr [[DE]], align 8
27842 // CHECK-NEXT:    [[TMP152:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP151]] seq_cst, align 8
27843 // CHECK-NEXT:    [[TMP153:%.*]] = fcmp olt double [[TMP152]], [[TMP151]]
27844 // CHECK-NEXT:    [[TMP154:%.*]] = select i1 [[TMP153]], double [[TMP151]], double [[TMP152]]
27845 // CHECK-NEXT:    store double [[TMP154]], ptr [[DV]], align 8
27846 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27847 // CHECK-NEXT:    [[TMP155:%.*]] = load double, ptr [[DE]], align 8
27848 // CHECK-NEXT:    [[TMP156:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP155]] seq_cst, align 8
27849 // CHECK-NEXT:    [[TMP157:%.*]] = fcmp ogt double [[TMP156]], [[TMP155]]
27850 // CHECK-NEXT:    [[TMP158:%.*]] = select i1 [[TMP157]], double [[TMP155]], double [[TMP156]]
27851 // CHECK-NEXT:    store double [[TMP158]], ptr [[DV]], align 8
27852 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27853 // CHECK-NEXT:    [[TMP159:%.*]] = load double, ptr [[DE]], align 8
27854 // CHECK-NEXT:    [[TMP160:%.*]] = load double, ptr [[DD]], align 8
27855 // CHECK-NEXT:    [[TMP161:%.*]] = bitcast double [[TMP159]] to i64
27856 // CHECK-NEXT:    [[TMP162:%.*]] = bitcast double [[TMP160]] to i64
27857 // CHECK-NEXT:    [[TMP163:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP161]], i64 [[TMP162]] seq_cst seq_cst, align 8
27858 // CHECK-NEXT:    [[TMP164:%.*]] = extractvalue { i64, i1 } [[TMP163]], 0
27859 // CHECK-NEXT:    [[TMP165:%.*]] = bitcast i64 [[TMP164]] to double
27860 // CHECK-NEXT:    [[TMP166:%.*]] = extractvalue { i64, i1 } [[TMP163]], 1
27861 // CHECK-NEXT:    [[TMP167:%.*]] = select i1 [[TMP166]], double [[TMP159]], double [[TMP165]]
27862 // CHECK-NEXT:    store double [[TMP167]], ptr [[DV]], align 8
27863 // CHECK-NEXT:    call void @__kmpc_flush(ptr @[[GLOB1]])
27864 // CHECK-NEXT:    [[TMP168:%.*]] = load double, ptr [[DV]], align 8
27865 // CHECK-NEXT:    ret double [[TMP168]]
27866 //
27867 //
27868 // SIMD-ONLY0-LABEL: @foo(
27869 // SIMD-ONLY0-NEXT:  entry:
27870 // SIMD-ONLY0-NEXT:    [[CX:%.*]] = alloca i8, align 1
27871 // SIMD-ONLY0-NEXT:    [[CE:%.*]] = alloca i8, align 1
27872 // SIMD-ONLY0-NEXT:    [[CD:%.*]] = alloca i8, align 1
27873 // SIMD-ONLY0-NEXT:    [[UCX:%.*]] = alloca i8, align 1
27874 // SIMD-ONLY0-NEXT:    [[UCE:%.*]] = alloca i8, align 1
27875 // SIMD-ONLY0-NEXT:    [[UCD:%.*]] = alloca i8, align 1
27876 // SIMD-ONLY0-NEXT:    [[SX:%.*]] = alloca i16, align 2
27877 // SIMD-ONLY0-NEXT:    [[SE:%.*]] = alloca i16, align 2
27878 // SIMD-ONLY0-NEXT:    [[SD:%.*]] = alloca i16, align 2
27879 // SIMD-ONLY0-NEXT:    [[USX:%.*]] = alloca i16, align 2
27880 // SIMD-ONLY0-NEXT:    [[USE:%.*]] = alloca i16, align 2
27881 // SIMD-ONLY0-NEXT:    [[USD:%.*]] = alloca i16, align 2
27882 // SIMD-ONLY0-NEXT:    [[IX:%.*]] = alloca i32, align 4
27883 // SIMD-ONLY0-NEXT:    [[IE:%.*]] = alloca i32, align 4
27884 // SIMD-ONLY0-NEXT:    [[ID:%.*]] = alloca i32, align 4
27885 // SIMD-ONLY0-NEXT:    [[UIX:%.*]] = alloca i32, align 4
27886 // SIMD-ONLY0-NEXT:    [[UIE:%.*]] = alloca i32, align 4
27887 // SIMD-ONLY0-NEXT:    [[UID:%.*]] = alloca i32, align 4
27888 // SIMD-ONLY0-NEXT:    [[LX:%.*]] = alloca i64, align 8
27889 // SIMD-ONLY0-NEXT:    [[LE:%.*]] = alloca i64, align 8
27890 // SIMD-ONLY0-NEXT:    [[LD:%.*]] = alloca i64, align 8
27891 // SIMD-ONLY0-NEXT:    [[ULX:%.*]] = alloca i64, align 8
27892 // SIMD-ONLY0-NEXT:    [[ULE:%.*]] = alloca i64, align 8
27893 // SIMD-ONLY0-NEXT:    [[ULD:%.*]] = alloca i64, align 8
27894 // SIMD-ONLY0-NEXT:    [[LLX:%.*]] = alloca i64, align 8
27895 // SIMD-ONLY0-NEXT:    [[LLE:%.*]] = alloca i64, align 8
27896 // SIMD-ONLY0-NEXT:    [[LLD:%.*]] = alloca i64, align 8
27897 // SIMD-ONLY0-NEXT:    [[ULLX:%.*]] = alloca i64, align 8
27898 // SIMD-ONLY0-NEXT:    [[ULLE:%.*]] = alloca i64, align 8
27899 // SIMD-ONLY0-NEXT:    [[ULLD:%.*]] = alloca i64, align 8
27900 // SIMD-ONLY0-NEXT:    [[FX:%.*]] = alloca float, align 4
27901 // SIMD-ONLY0-NEXT:    [[FE:%.*]] = alloca float, align 4
27902 // SIMD-ONLY0-NEXT:    [[FD:%.*]] = alloca float, align 4
27903 // SIMD-ONLY0-NEXT:    [[DX:%.*]] = alloca double, align 8
27904 // SIMD-ONLY0-NEXT:    [[DE:%.*]] = alloca double, align 8
27905 // SIMD-ONLY0-NEXT:    [[DD:%.*]] = alloca double, align 8
27906 // SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = load i8, ptr [[CX]], align 1
27907 // SIMD-ONLY0-NEXT:    [[CONV:%.*]] = sext i8 [[TMP0]] to i32
27908 // SIMD-ONLY0-NEXT:    [[TMP1:%.*]] = load i8, ptr [[CE]], align 1
27909 // SIMD-ONLY0-NEXT:    [[CONV1:%.*]] = sext i8 [[TMP1]] to i32
27910 // SIMD-ONLY0-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[CONV]], [[CONV1]]
27911 // SIMD-ONLY0-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
27912 // SIMD-ONLY0:       cond.true:
27913 // SIMD-ONLY0-NEXT:    [[TMP2:%.*]] = load i8, ptr [[CE]], align 1
27914 // SIMD-ONLY0-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
27915 // SIMD-ONLY0-NEXT:    br label [[COND_END:%.*]]
27916 // SIMD-ONLY0:       cond.false:
27917 // SIMD-ONLY0-NEXT:    [[TMP3:%.*]] = load i8, ptr [[CX]], align 1
27918 // SIMD-ONLY0-NEXT:    [[CONV4:%.*]] = sext i8 [[TMP3]] to i32
27919 // SIMD-ONLY0-NEXT:    br label [[COND_END]]
27920 // SIMD-ONLY0:       cond.end:
27921 // SIMD-ONLY0-NEXT:    [[COND:%.*]] = phi i32 [ [[CONV3]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ]
27922 // SIMD-ONLY0-NEXT:    [[CONV5:%.*]] = trunc i32 [[COND]] to i8
27923 // SIMD-ONLY0-NEXT:    store i8 [[CONV5]], ptr [[CX]], align 1
27924 // SIMD-ONLY0-NEXT:    [[TMP4:%.*]] = load i8, ptr [[CX]], align 1
27925 // SIMD-ONLY0-NEXT:    [[CONV6:%.*]] = sext i8 [[TMP4]] to i32
27926 // SIMD-ONLY0-NEXT:    [[TMP5:%.*]] = load i8, ptr [[CE]], align 1
27927 // SIMD-ONLY0-NEXT:    [[CONV7:%.*]] = sext i8 [[TMP5]] to i32
27928 // SIMD-ONLY0-NEXT:    [[CMP8:%.*]] = icmp slt i32 [[CONV6]], [[CONV7]]
27929 // SIMD-ONLY0-NEXT:    br i1 [[CMP8]], label [[COND_TRUE10:%.*]], label [[COND_FALSE12:%.*]]
27930 // SIMD-ONLY0:       cond.true10:
27931 // SIMD-ONLY0-NEXT:    [[TMP6:%.*]] = load i8, ptr [[CE]], align 1
27932 // SIMD-ONLY0-NEXT:    [[CONV11:%.*]] = sext i8 [[TMP6]] to i32
27933 // SIMD-ONLY0-NEXT:    br label [[COND_END14:%.*]]
27934 // SIMD-ONLY0:       cond.false12:
27935 // SIMD-ONLY0-NEXT:    [[TMP7:%.*]] = load i8, ptr [[CX]], align 1
27936 // SIMD-ONLY0-NEXT:    [[CONV13:%.*]] = sext i8 [[TMP7]] to i32
27937 // SIMD-ONLY0-NEXT:    br label [[COND_END14]]
27938 // SIMD-ONLY0:       cond.end14:
27939 // SIMD-ONLY0-NEXT:    [[COND15:%.*]] = phi i32 [ [[CONV11]], [[COND_TRUE10]] ], [ [[CONV13]], [[COND_FALSE12]] ]
27940 // SIMD-ONLY0-NEXT:    [[CONV16:%.*]] = trunc i32 [[COND15]] to i8
27941 // SIMD-ONLY0-NEXT:    store i8 [[CONV16]], ptr [[CX]], align 1
27942 // SIMD-ONLY0-NEXT:    [[TMP8:%.*]] = load i8, ptr [[CE]], align 1
27943 // SIMD-ONLY0-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP8]] to i32
27944 // SIMD-ONLY0-NEXT:    [[TMP9:%.*]] = load i8, ptr [[CX]], align 1
27945 // SIMD-ONLY0-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP9]] to i32
27946 // SIMD-ONLY0-NEXT:    [[CMP19:%.*]] = icmp sgt i32 [[CONV17]], [[CONV18]]
27947 // SIMD-ONLY0-NEXT:    br i1 [[CMP19]], label [[COND_TRUE21:%.*]], label [[COND_FALSE23:%.*]]
27948 // SIMD-ONLY0:       cond.true21:
27949 // SIMD-ONLY0-NEXT:    [[TMP10:%.*]] = load i8, ptr [[CE]], align 1
27950 // SIMD-ONLY0-NEXT:    [[CONV22:%.*]] = sext i8 [[TMP10]] to i32
27951 // SIMD-ONLY0-NEXT:    br label [[COND_END25:%.*]]
27952 // SIMD-ONLY0:       cond.false23:
27953 // SIMD-ONLY0-NEXT:    [[TMP11:%.*]] = load i8, ptr [[CX]], align 1
27954 // SIMD-ONLY0-NEXT:    [[CONV24:%.*]] = sext i8 [[TMP11]] to i32
27955 // SIMD-ONLY0-NEXT:    br label [[COND_END25]]
27956 // SIMD-ONLY0:       cond.end25:
27957 // SIMD-ONLY0-NEXT:    [[COND26:%.*]] = phi i32 [ [[CONV22]], [[COND_TRUE21]] ], [ [[CONV24]], [[COND_FALSE23]] ]
27958 // SIMD-ONLY0-NEXT:    [[CONV27:%.*]] = trunc i32 [[COND26]] to i8
27959 // SIMD-ONLY0-NEXT:    store i8 [[CONV27]], ptr [[CX]], align 1
27960 // SIMD-ONLY0-NEXT:    [[TMP12:%.*]] = load i8, ptr [[CE]], align 1
27961 // SIMD-ONLY0-NEXT:    [[CONV28:%.*]] = sext i8 [[TMP12]] to i32
27962 // SIMD-ONLY0-NEXT:    [[TMP13:%.*]] = load i8, ptr [[CX]], align 1
27963 // SIMD-ONLY0-NEXT:    [[CONV29:%.*]] = sext i8 [[TMP13]] to i32
27964 // SIMD-ONLY0-NEXT:    [[CMP30:%.*]] = icmp slt i32 [[CONV28]], [[CONV29]]
27965 // SIMD-ONLY0-NEXT:    br i1 [[CMP30]], label [[COND_TRUE32:%.*]], label [[COND_FALSE34:%.*]]
27966 // SIMD-ONLY0:       cond.true32:
27967 // SIMD-ONLY0-NEXT:    [[TMP14:%.*]] = load i8, ptr [[CE]], align 1
27968 // SIMD-ONLY0-NEXT:    [[CONV33:%.*]] = sext i8 [[TMP14]] to i32
27969 // SIMD-ONLY0-NEXT:    br label [[COND_END36:%.*]]
27970 // SIMD-ONLY0:       cond.false34:
27971 // SIMD-ONLY0-NEXT:    [[TMP15:%.*]] = load i8, ptr [[CX]], align 1
27972 // SIMD-ONLY0-NEXT:    [[CONV35:%.*]] = sext i8 [[TMP15]] to i32
27973 // SIMD-ONLY0-NEXT:    br label [[COND_END36]]
27974 // SIMD-ONLY0:       cond.end36:
27975 // SIMD-ONLY0-NEXT:    [[COND37:%.*]] = phi i32 [ [[CONV33]], [[COND_TRUE32]] ], [ [[CONV35]], [[COND_FALSE34]] ]
27976 // SIMD-ONLY0-NEXT:    [[CONV38:%.*]] = trunc i32 [[COND37]] to i8
27977 // SIMD-ONLY0-NEXT:    store i8 [[CONV38]], ptr [[CX]], align 1
27978 // SIMD-ONLY0-NEXT:    [[TMP16:%.*]] = load i8, ptr [[CX]], align 1
27979 // SIMD-ONLY0-NEXT:    [[CONV39:%.*]] = sext i8 [[TMP16]] to i32
27980 // SIMD-ONLY0-NEXT:    [[TMP17:%.*]] = load i8, ptr [[CE]], align 1
27981 // SIMD-ONLY0-NEXT:    [[CONV40:%.*]] = sext i8 [[TMP17]] to i32
27982 // SIMD-ONLY0-NEXT:    [[CMP41:%.*]] = icmp sgt i32 [[CONV39]], [[CONV40]]
27983 // SIMD-ONLY0-NEXT:    br i1 [[CMP41]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
27984 // SIMD-ONLY0:       if.then:
27985 // SIMD-ONLY0-NEXT:    [[TMP18:%.*]] = load i8, ptr [[CE]], align 1
27986 // SIMD-ONLY0-NEXT:    store i8 [[TMP18]], ptr [[CX]], align 1
27987 // SIMD-ONLY0-NEXT:    br label [[IF_END]]
27988 // SIMD-ONLY0:       if.end:
27989 // SIMD-ONLY0-NEXT:    [[TMP19:%.*]] = load i8, ptr [[CX]], align 1
27990 // SIMD-ONLY0-NEXT:    [[CONV43:%.*]] = sext i8 [[TMP19]] to i32
27991 // SIMD-ONLY0-NEXT:    [[TMP20:%.*]] = load i8, ptr [[CE]], align 1
27992 // SIMD-ONLY0-NEXT:    [[CONV44:%.*]] = sext i8 [[TMP20]] to i32
27993 // SIMD-ONLY0-NEXT:    [[CMP45:%.*]] = icmp slt i32 [[CONV43]], [[CONV44]]
27994 // SIMD-ONLY0-NEXT:    br i1 [[CMP45]], label [[IF_THEN47:%.*]], label [[IF_END48:%.*]]
27995 // SIMD-ONLY0:       if.then47:
27996 // SIMD-ONLY0-NEXT:    [[TMP21:%.*]] = load i8, ptr [[CE]], align 1
27997 // SIMD-ONLY0-NEXT:    store i8 [[TMP21]], ptr [[CX]], align 1
27998 // SIMD-ONLY0-NEXT:    br label [[IF_END48]]
27999 // SIMD-ONLY0:       if.end48:
28000 // SIMD-ONLY0-NEXT:    [[TMP22:%.*]] = load i8, ptr [[CE]], align 1
28001 // SIMD-ONLY0-NEXT:    [[CONV49:%.*]] = sext i8 [[TMP22]] to i32
28002 // SIMD-ONLY0-NEXT:    [[TMP23:%.*]] = load i8, ptr [[CX]], align 1
28003 // SIMD-ONLY0-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP23]] to i32
28004 // SIMD-ONLY0-NEXT:    [[CMP51:%.*]] = icmp sgt i32 [[CONV49]], [[CONV50]]
28005 // SIMD-ONLY0-NEXT:    br i1 [[CMP51]], label [[IF_THEN53:%.*]], label [[IF_END54:%.*]]
28006 // SIMD-ONLY0:       if.then53:
28007 // SIMD-ONLY0-NEXT:    [[TMP24:%.*]] = load i8, ptr [[CE]], align 1
28008 // SIMD-ONLY0-NEXT:    store i8 [[TMP24]], ptr [[CX]], align 1
28009 // SIMD-ONLY0-NEXT:    br label [[IF_END54]]
28010 // SIMD-ONLY0:       if.end54:
28011 // SIMD-ONLY0-NEXT:    [[TMP25:%.*]] = load i8, ptr [[CE]], align 1
28012 // SIMD-ONLY0-NEXT:    [[CONV55:%.*]] = sext i8 [[TMP25]] to i32
28013 // SIMD-ONLY0-NEXT:    [[TMP26:%.*]] = load i8, ptr [[CX]], align 1
28014 // SIMD-ONLY0-NEXT:    [[CONV56:%.*]] = sext i8 [[TMP26]] to i32
28015 // SIMD-ONLY0-NEXT:    [[CMP57:%.*]] = icmp slt i32 [[CONV55]], [[CONV56]]
28016 // SIMD-ONLY0-NEXT:    br i1 [[CMP57]], label [[IF_THEN59:%.*]], label [[IF_END60:%.*]]
28017 // SIMD-ONLY0:       if.then59:
28018 // SIMD-ONLY0-NEXT:    [[TMP27:%.*]] = load i8, ptr [[CE]], align 1
28019 // SIMD-ONLY0-NEXT:    store i8 [[TMP27]], ptr [[CX]], align 1
28020 // SIMD-ONLY0-NEXT:    br label [[IF_END60]]
28021 // SIMD-ONLY0:       if.end60:
28022 // SIMD-ONLY0-NEXT:    [[TMP28:%.*]] = load i8, ptr [[CX]], align 1
28023 // SIMD-ONLY0-NEXT:    [[CONV61:%.*]] = sext i8 [[TMP28]] to i32
28024 // SIMD-ONLY0-NEXT:    [[TMP29:%.*]] = load i8, ptr [[CE]], align 1
28025 // SIMD-ONLY0-NEXT:    [[CONV62:%.*]] = sext i8 [[TMP29]] to i32
28026 // SIMD-ONLY0-NEXT:    [[CMP63:%.*]] = icmp eq i32 [[CONV61]], [[CONV62]]
28027 // SIMD-ONLY0-NEXT:    br i1 [[CMP63]], label [[COND_TRUE65:%.*]], label [[COND_FALSE67:%.*]]
28028 // SIMD-ONLY0:       cond.true65:
28029 // SIMD-ONLY0-NEXT:    [[TMP30:%.*]] = load i8, ptr [[CD]], align 1
28030 // SIMD-ONLY0-NEXT:    [[CONV66:%.*]] = sext i8 [[TMP30]] to i32
28031 // SIMD-ONLY0-NEXT:    br label [[COND_END69:%.*]]
28032 // SIMD-ONLY0:       cond.false67:
28033 // SIMD-ONLY0-NEXT:    [[TMP31:%.*]] = load i8, ptr [[CX]], align 1
28034 // SIMD-ONLY0-NEXT:    [[CONV68:%.*]] = sext i8 [[TMP31]] to i32
28035 // SIMD-ONLY0-NEXT:    br label [[COND_END69]]
28036 // SIMD-ONLY0:       cond.end69:
28037 // SIMD-ONLY0-NEXT:    [[COND70:%.*]] = phi i32 [ [[CONV66]], [[COND_TRUE65]] ], [ [[CONV68]], [[COND_FALSE67]] ]
28038 // SIMD-ONLY0-NEXT:    [[CONV71:%.*]] = trunc i32 [[COND70]] to i8
28039 // SIMD-ONLY0-NEXT:    store i8 [[CONV71]], ptr [[CX]], align 1
28040 // SIMD-ONLY0-NEXT:    [[TMP32:%.*]] = load i8, ptr [[CE]], align 1
28041 // SIMD-ONLY0-NEXT:    [[CONV72:%.*]] = sext i8 [[TMP32]] to i32
28042 // SIMD-ONLY0-NEXT:    [[TMP33:%.*]] = load i8, ptr [[CX]], align 1
28043 // SIMD-ONLY0-NEXT:    [[CONV73:%.*]] = sext i8 [[TMP33]] to i32
28044 // SIMD-ONLY0-NEXT:    [[CMP74:%.*]] = icmp eq i32 [[CONV72]], [[CONV73]]
28045 // SIMD-ONLY0-NEXT:    br i1 [[CMP74]], label [[COND_TRUE76:%.*]], label [[COND_FALSE78:%.*]]
28046 // SIMD-ONLY0:       cond.true76:
28047 // SIMD-ONLY0-NEXT:    [[TMP34:%.*]] = load i8, ptr [[CD]], align 1
28048 // SIMD-ONLY0-NEXT:    [[CONV77:%.*]] = sext i8 [[TMP34]] to i32
28049 // SIMD-ONLY0-NEXT:    br label [[COND_END80:%.*]]
28050 // SIMD-ONLY0:       cond.false78:
28051 // SIMD-ONLY0-NEXT:    [[TMP35:%.*]] = load i8, ptr [[CX]], align 1
28052 // SIMD-ONLY0-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP35]] to i32
28053 // SIMD-ONLY0-NEXT:    br label [[COND_END80]]
28054 // SIMD-ONLY0:       cond.end80:
28055 // SIMD-ONLY0-NEXT:    [[COND81:%.*]] = phi i32 [ [[CONV77]], [[COND_TRUE76]] ], [ [[CONV79]], [[COND_FALSE78]] ]
28056 // SIMD-ONLY0-NEXT:    [[CONV82:%.*]] = trunc i32 [[COND81]] to i8
28057 // SIMD-ONLY0-NEXT:    store i8 [[CONV82]], ptr [[CX]], align 1
28058 // SIMD-ONLY0-NEXT:    [[TMP36:%.*]] = load i8, ptr [[CX]], align 1
28059 // SIMD-ONLY0-NEXT:    [[CONV83:%.*]] = sext i8 [[TMP36]] to i32
28060 // SIMD-ONLY0-NEXT:    [[TMP37:%.*]] = load i8, ptr [[CE]], align 1
28061 // SIMD-ONLY0-NEXT:    [[CONV84:%.*]] = sext i8 [[TMP37]] to i32
28062 // SIMD-ONLY0-NEXT:    [[CMP85:%.*]] = icmp eq i32 [[CONV83]], [[CONV84]]
28063 // SIMD-ONLY0-NEXT:    br i1 [[CMP85]], label [[IF_THEN87:%.*]], label [[IF_END88:%.*]]
28064 // SIMD-ONLY0:       if.then87:
28065 // SIMD-ONLY0-NEXT:    [[TMP38:%.*]] = load i8, ptr [[CD]], align 1
28066 // SIMD-ONLY0-NEXT:    store i8 [[TMP38]], ptr [[CX]], align 1
28067 // SIMD-ONLY0-NEXT:    br label [[IF_END88]]
28068 // SIMD-ONLY0:       if.end88:
28069 // SIMD-ONLY0-NEXT:    [[TMP39:%.*]] = load i8, ptr [[CE]], align 1
28070 // SIMD-ONLY0-NEXT:    [[CONV89:%.*]] = sext i8 [[TMP39]] to i32
28071 // SIMD-ONLY0-NEXT:    [[TMP40:%.*]] = load i8, ptr [[CX]], align 1
28072 // SIMD-ONLY0-NEXT:    [[CONV90:%.*]] = sext i8 [[TMP40]] to i32
28073 // SIMD-ONLY0-NEXT:    [[CMP91:%.*]] = icmp eq i32 [[CONV89]], [[CONV90]]
28074 // SIMD-ONLY0-NEXT:    br i1 [[CMP91]], label [[IF_THEN93:%.*]], label [[IF_END94:%.*]]
28075 // SIMD-ONLY0:       if.then93:
28076 // SIMD-ONLY0-NEXT:    [[TMP41:%.*]] = load i8, ptr [[CD]], align 1
28077 // SIMD-ONLY0-NEXT:    store i8 [[TMP41]], ptr [[CX]], align 1
28078 // SIMD-ONLY0-NEXT:    br label [[IF_END94]]
28079 // SIMD-ONLY0:       if.end94:
28080 // SIMD-ONLY0-NEXT:    [[TMP42:%.*]] = load i8, ptr [[UCX]], align 1
28081 // SIMD-ONLY0-NEXT:    [[CONV95:%.*]] = zext i8 [[TMP42]] to i32
28082 // SIMD-ONLY0-NEXT:    [[TMP43:%.*]] = load i8, ptr [[UCE]], align 1
28083 // SIMD-ONLY0-NEXT:    [[CONV96:%.*]] = zext i8 [[TMP43]] to i32
28084 // SIMD-ONLY0-NEXT:    [[CMP97:%.*]] = icmp sgt i32 [[CONV95]], [[CONV96]]
28085 // SIMD-ONLY0-NEXT:    br i1 [[CMP97]], label [[COND_TRUE99:%.*]], label [[COND_FALSE101:%.*]]
28086 // SIMD-ONLY0:       cond.true99:
28087 // SIMD-ONLY0-NEXT:    [[TMP44:%.*]] = load i8, ptr [[UCE]], align 1
28088 // SIMD-ONLY0-NEXT:    [[CONV100:%.*]] = zext i8 [[TMP44]] to i32
28089 // SIMD-ONLY0-NEXT:    br label [[COND_END103:%.*]]
28090 // SIMD-ONLY0:       cond.false101:
28091 // SIMD-ONLY0-NEXT:    [[TMP45:%.*]] = load i8, ptr [[UCX]], align 1
28092 // SIMD-ONLY0-NEXT:    [[CONV102:%.*]] = zext i8 [[TMP45]] to i32
28093 // SIMD-ONLY0-NEXT:    br label [[COND_END103]]
28094 // SIMD-ONLY0:       cond.end103:
28095 // SIMD-ONLY0-NEXT:    [[COND104:%.*]] = phi i32 [ [[CONV100]], [[COND_TRUE99]] ], [ [[CONV102]], [[COND_FALSE101]] ]
28096 // SIMD-ONLY0-NEXT:    [[CONV105:%.*]] = trunc i32 [[COND104]] to i8
28097 // SIMD-ONLY0-NEXT:    store i8 [[CONV105]], ptr [[UCX]], align 1
28098 // SIMD-ONLY0-NEXT:    [[TMP46:%.*]] = load i8, ptr [[UCX]], align 1
28099 // SIMD-ONLY0-NEXT:    [[CONV106:%.*]] = zext i8 [[TMP46]] to i32
28100 // SIMD-ONLY0-NEXT:    [[TMP47:%.*]] = load i8, ptr [[UCE]], align 1
28101 // SIMD-ONLY0-NEXT:    [[CONV107:%.*]] = zext i8 [[TMP47]] to i32
28102 // SIMD-ONLY0-NEXT:    [[CMP108:%.*]] = icmp slt i32 [[CONV106]], [[CONV107]]
28103 // SIMD-ONLY0-NEXT:    br i1 [[CMP108]], label [[COND_TRUE110:%.*]], label [[COND_FALSE112:%.*]]
28104 // SIMD-ONLY0:       cond.true110:
28105 // SIMD-ONLY0-NEXT:    [[TMP48:%.*]] = load i8, ptr [[UCE]], align 1
28106 // SIMD-ONLY0-NEXT:    [[CONV111:%.*]] = zext i8 [[TMP48]] to i32
28107 // SIMD-ONLY0-NEXT:    br label [[COND_END114:%.*]]
28108 // SIMD-ONLY0:       cond.false112:
28109 // SIMD-ONLY0-NEXT:    [[TMP49:%.*]] = load i8, ptr [[UCX]], align 1
28110 // SIMD-ONLY0-NEXT:    [[CONV113:%.*]] = zext i8 [[TMP49]] to i32
28111 // SIMD-ONLY0-NEXT:    br label [[COND_END114]]
28112 // SIMD-ONLY0:       cond.end114:
28113 // SIMD-ONLY0-NEXT:    [[COND115:%.*]] = phi i32 [ [[CONV111]], [[COND_TRUE110]] ], [ [[CONV113]], [[COND_FALSE112]] ]
28114 // SIMD-ONLY0-NEXT:    [[CONV116:%.*]] = trunc i32 [[COND115]] to i8
28115 // SIMD-ONLY0-NEXT:    store i8 [[CONV116]], ptr [[UCX]], align 1
28116 // SIMD-ONLY0-NEXT:    [[TMP50:%.*]] = load i8, ptr [[UCE]], align 1
28117 // SIMD-ONLY0-NEXT:    [[CONV117:%.*]] = zext i8 [[TMP50]] to i32
28118 // SIMD-ONLY0-NEXT:    [[TMP51:%.*]] = load i8, ptr [[UCX]], align 1
28119 // SIMD-ONLY0-NEXT:    [[CONV118:%.*]] = zext i8 [[TMP51]] to i32
28120 // SIMD-ONLY0-NEXT:    [[CMP119:%.*]] = icmp sgt i32 [[CONV117]], [[CONV118]]
28121 // SIMD-ONLY0-NEXT:    br i1 [[CMP119]], label [[COND_TRUE121:%.*]], label [[COND_FALSE123:%.*]]
28122 // SIMD-ONLY0:       cond.true121:
28123 // SIMD-ONLY0-NEXT:    [[TMP52:%.*]] = load i8, ptr [[UCE]], align 1
28124 // SIMD-ONLY0-NEXT:    [[CONV122:%.*]] = zext i8 [[TMP52]] to i32
28125 // SIMD-ONLY0-NEXT:    br label [[COND_END125:%.*]]
28126 // SIMD-ONLY0:       cond.false123:
28127 // SIMD-ONLY0-NEXT:    [[TMP53:%.*]] = load i8, ptr [[UCX]], align 1
28128 // SIMD-ONLY0-NEXT:    [[CONV124:%.*]] = zext i8 [[TMP53]] to i32
28129 // SIMD-ONLY0-NEXT:    br label [[COND_END125]]
28130 // SIMD-ONLY0:       cond.end125:
28131 // SIMD-ONLY0-NEXT:    [[COND126:%.*]] = phi i32 [ [[CONV122]], [[COND_TRUE121]] ], [ [[CONV124]], [[COND_FALSE123]] ]
28132 // SIMD-ONLY0-NEXT:    [[CONV127:%.*]] = trunc i32 [[COND126]] to i8
28133 // SIMD-ONLY0-NEXT:    store i8 [[CONV127]], ptr [[UCX]], align 1
28134 // SIMD-ONLY0-NEXT:    [[TMP54:%.*]] = load i8, ptr [[UCE]], align 1
28135 // SIMD-ONLY0-NEXT:    [[CONV128:%.*]] = zext i8 [[TMP54]] to i32
28136 // SIMD-ONLY0-NEXT:    [[TMP55:%.*]] = load i8, ptr [[UCX]], align 1
28137 // SIMD-ONLY0-NEXT:    [[CONV129:%.*]] = zext i8 [[TMP55]] to i32
28138 // SIMD-ONLY0-NEXT:    [[CMP130:%.*]] = icmp slt i32 [[CONV128]], [[CONV129]]
28139 // SIMD-ONLY0-NEXT:    br i1 [[CMP130]], label [[COND_TRUE132:%.*]], label [[COND_FALSE134:%.*]]
28140 // SIMD-ONLY0:       cond.true132:
28141 // SIMD-ONLY0-NEXT:    [[TMP56:%.*]] = load i8, ptr [[UCE]], align 1
28142 // SIMD-ONLY0-NEXT:    [[CONV133:%.*]] = zext i8 [[TMP56]] to i32
28143 // SIMD-ONLY0-NEXT:    br label [[COND_END136:%.*]]
28144 // SIMD-ONLY0:       cond.false134:
28145 // SIMD-ONLY0-NEXT:    [[TMP57:%.*]] = load i8, ptr [[UCX]], align 1
28146 // SIMD-ONLY0-NEXT:    [[CONV135:%.*]] = zext i8 [[TMP57]] to i32
28147 // SIMD-ONLY0-NEXT:    br label [[COND_END136]]
28148 // SIMD-ONLY0:       cond.end136:
28149 // SIMD-ONLY0-NEXT:    [[COND137:%.*]] = phi i32 [ [[CONV133]], [[COND_TRUE132]] ], [ [[CONV135]], [[COND_FALSE134]] ]
28150 // SIMD-ONLY0-NEXT:    [[CONV138:%.*]] = trunc i32 [[COND137]] to i8
28151 // SIMD-ONLY0-NEXT:    store i8 [[CONV138]], ptr [[UCX]], align 1
28152 // SIMD-ONLY0-NEXT:    [[TMP58:%.*]] = load i8, ptr [[UCX]], align 1
28153 // SIMD-ONLY0-NEXT:    [[CONV139:%.*]] = zext i8 [[TMP58]] to i32
28154 // SIMD-ONLY0-NEXT:    [[TMP59:%.*]] = load i8, ptr [[UCE]], align 1
28155 // SIMD-ONLY0-NEXT:    [[CONV140:%.*]] = zext i8 [[TMP59]] to i32
28156 // SIMD-ONLY0-NEXT:    [[CMP141:%.*]] = icmp sgt i32 [[CONV139]], [[CONV140]]
28157 // SIMD-ONLY0-NEXT:    br i1 [[CMP141]], label [[IF_THEN143:%.*]], label [[IF_END144:%.*]]
28158 // SIMD-ONLY0:       if.then143:
28159 // SIMD-ONLY0-NEXT:    [[TMP60:%.*]] = load i8, ptr [[UCE]], align 1
28160 // SIMD-ONLY0-NEXT:    store i8 [[TMP60]], ptr [[UCX]], align 1
28161 // SIMD-ONLY0-NEXT:    br label [[IF_END144]]
28162 // SIMD-ONLY0:       if.end144:
28163 // SIMD-ONLY0-NEXT:    [[TMP61:%.*]] = load i8, ptr [[UCX]], align 1
28164 // SIMD-ONLY0-NEXT:    [[CONV145:%.*]] = zext i8 [[TMP61]] to i32
28165 // SIMD-ONLY0-NEXT:    [[TMP62:%.*]] = load i8, ptr [[UCE]], align 1
28166 // SIMD-ONLY0-NEXT:    [[CONV146:%.*]] = zext i8 [[TMP62]] to i32
28167 // SIMD-ONLY0-NEXT:    [[CMP147:%.*]] = icmp slt i32 [[CONV145]], [[CONV146]]
28168 // SIMD-ONLY0-NEXT:    br i1 [[CMP147]], label [[IF_THEN149:%.*]], label [[IF_END150:%.*]]
28169 // SIMD-ONLY0:       if.then149:
28170 // SIMD-ONLY0-NEXT:    [[TMP63:%.*]] = load i8, ptr [[UCE]], align 1
28171 // SIMD-ONLY0-NEXT:    store i8 [[TMP63]], ptr [[UCX]], align 1
28172 // SIMD-ONLY0-NEXT:    br label [[IF_END150]]
28173 // SIMD-ONLY0:       if.end150:
28174 // SIMD-ONLY0-NEXT:    [[TMP64:%.*]] = load i8, ptr [[UCE]], align 1
28175 // SIMD-ONLY0-NEXT:    [[CONV151:%.*]] = zext i8 [[TMP64]] to i32
28176 // SIMD-ONLY0-NEXT:    [[TMP65:%.*]] = load i8, ptr [[UCX]], align 1
28177 // SIMD-ONLY0-NEXT:    [[CONV152:%.*]] = zext i8 [[TMP65]] to i32
28178 // SIMD-ONLY0-NEXT:    [[CMP153:%.*]] = icmp sgt i32 [[CONV151]], [[CONV152]]
28179 // SIMD-ONLY0-NEXT:    br i1 [[CMP153]], label [[IF_THEN155:%.*]], label [[IF_END156:%.*]]
28180 // SIMD-ONLY0:       if.then155:
28181 // SIMD-ONLY0-NEXT:    [[TMP66:%.*]] = load i8, ptr [[UCE]], align 1
28182 // SIMD-ONLY0-NEXT:    store i8 [[TMP66]], ptr [[UCX]], align 1
28183 // SIMD-ONLY0-NEXT:    br label [[IF_END156]]
28184 // SIMD-ONLY0:       if.end156:
28185 // SIMD-ONLY0-NEXT:    [[TMP67:%.*]] = load i8, ptr [[UCE]], align 1
28186 // SIMD-ONLY0-NEXT:    [[CONV157:%.*]] = zext i8 [[TMP67]] to i32
28187 // SIMD-ONLY0-NEXT:    [[TMP68:%.*]] = load i8, ptr [[UCX]], align 1
28188 // SIMD-ONLY0-NEXT:    [[CONV158:%.*]] = zext i8 [[TMP68]] to i32
28189 // SIMD-ONLY0-NEXT:    [[CMP159:%.*]] = icmp slt i32 [[CONV157]], [[CONV158]]
28190 // SIMD-ONLY0-NEXT:    br i1 [[CMP159]], label [[IF_THEN161:%.*]], label [[IF_END162:%.*]]
28191 // SIMD-ONLY0:       if.then161:
28192 // SIMD-ONLY0-NEXT:    [[TMP69:%.*]] = load i8, ptr [[UCE]], align 1
28193 // SIMD-ONLY0-NEXT:    store i8 [[TMP69]], ptr [[UCX]], align 1
28194 // SIMD-ONLY0-NEXT:    br label [[IF_END162]]
28195 // SIMD-ONLY0:       if.end162:
28196 // SIMD-ONLY0-NEXT:    [[TMP70:%.*]] = load i8, ptr [[UCX]], align 1
28197 // SIMD-ONLY0-NEXT:    [[CONV163:%.*]] = zext i8 [[TMP70]] to i32
28198 // SIMD-ONLY0-NEXT:    [[TMP71:%.*]] = load i8, ptr [[UCE]], align 1
28199 // SIMD-ONLY0-NEXT:    [[CONV164:%.*]] = zext i8 [[TMP71]] to i32
28200 // SIMD-ONLY0-NEXT:    [[CMP165:%.*]] = icmp eq i32 [[CONV163]], [[CONV164]]
28201 // SIMD-ONLY0-NEXT:    br i1 [[CMP165]], label [[COND_TRUE167:%.*]], label [[COND_FALSE169:%.*]]
28202 // SIMD-ONLY0:       cond.true167:
28203 // SIMD-ONLY0-NEXT:    [[TMP72:%.*]] = load i8, ptr [[UCD]], align 1
28204 // SIMD-ONLY0-NEXT:    [[CONV168:%.*]] = zext i8 [[TMP72]] to i32
28205 // SIMD-ONLY0-NEXT:    br label [[COND_END171:%.*]]
28206 // SIMD-ONLY0:       cond.false169:
28207 // SIMD-ONLY0-NEXT:    [[TMP73:%.*]] = load i8, ptr [[UCX]], align 1
28208 // SIMD-ONLY0-NEXT:    [[CONV170:%.*]] = zext i8 [[TMP73]] to i32
28209 // SIMD-ONLY0-NEXT:    br label [[COND_END171]]
28210 // SIMD-ONLY0:       cond.end171:
28211 // SIMD-ONLY0-NEXT:    [[COND172:%.*]] = phi i32 [ [[CONV168]], [[COND_TRUE167]] ], [ [[CONV170]], [[COND_FALSE169]] ]
28212 // SIMD-ONLY0-NEXT:    [[CONV173:%.*]] = trunc i32 [[COND172]] to i8
28213 // SIMD-ONLY0-NEXT:    store i8 [[CONV173]], ptr [[UCX]], align 1
28214 // SIMD-ONLY0-NEXT:    [[TMP74:%.*]] = load i8, ptr [[UCE]], align 1
28215 // SIMD-ONLY0-NEXT:    [[CONV174:%.*]] = zext i8 [[TMP74]] to i32
28216 // SIMD-ONLY0-NEXT:    [[TMP75:%.*]] = load i8, ptr [[UCX]], align 1
28217 // SIMD-ONLY0-NEXT:    [[CONV175:%.*]] = zext i8 [[TMP75]] to i32
28218 // SIMD-ONLY0-NEXT:    [[CMP176:%.*]] = icmp eq i32 [[CONV174]], [[CONV175]]
28219 // SIMD-ONLY0-NEXT:    br i1 [[CMP176]], label [[COND_TRUE178:%.*]], label [[COND_FALSE180:%.*]]
28220 // SIMD-ONLY0:       cond.true178:
28221 // SIMD-ONLY0-NEXT:    [[TMP76:%.*]] = load i8, ptr [[UCD]], align 1
28222 // SIMD-ONLY0-NEXT:    [[CONV179:%.*]] = zext i8 [[TMP76]] to i32
28223 // SIMD-ONLY0-NEXT:    br label [[COND_END182:%.*]]
28224 // SIMD-ONLY0:       cond.false180:
28225 // SIMD-ONLY0-NEXT:    [[TMP77:%.*]] = load i8, ptr [[UCX]], align 1
28226 // SIMD-ONLY0-NEXT:    [[CONV181:%.*]] = zext i8 [[TMP77]] to i32
28227 // SIMD-ONLY0-NEXT:    br label [[COND_END182]]
28228 // SIMD-ONLY0:       cond.end182:
28229 // SIMD-ONLY0-NEXT:    [[COND183:%.*]] = phi i32 [ [[CONV179]], [[COND_TRUE178]] ], [ [[CONV181]], [[COND_FALSE180]] ]
28230 // SIMD-ONLY0-NEXT:    [[CONV184:%.*]] = trunc i32 [[COND183]] to i8
28231 // SIMD-ONLY0-NEXT:    store i8 [[CONV184]], ptr [[UCX]], align 1
28232 // SIMD-ONLY0-NEXT:    [[TMP78:%.*]] = load i8, ptr [[UCX]], align 1
28233 // SIMD-ONLY0-NEXT:    [[CONV185:%.*]] = zext i8 [[TMP78]] to i32
28234 // SIMD-ONLY0-NEXT:    [[TMP79:%.*]] = load i8, ptr [[UCE]], align 1
28235 // SIMD-ONLY0-NEXT:    [[CONV186:%.*]] = zext i8 [[TMP79]] to i32
28236 // SIMD-ONLY0-NEXT:    [[CMP187:%.*]] = icmp eq i32 [[CONV185]], [[CONV186]]
28237 // SIMD-ONLY0-NEXT:    br i1 [[CMP187]], label [[IF_THEN189:%.*]], label [[IF_END190:%.*]]
28238 // SIMD-ONLY0:       if.then189:
28239 // SIMD-ONLY0-NEXT:    [[TMP80:%.*]] = load i8, ptr [[UCD]], align 1
28240 // SIMD-ONLY0-NEXT:    store i8 [[TMP80]], ptr [[UCX]], align 1
28241 // SIMD-ONLY0-NEXT:    br label [[IF_END190]]
28242 // SIMD-ONLY0:       if.end190:
28243 // SIMD-ONLY0-NEXT:    [[TMP81:%.*]] = load i8, ptr [[UCE]], align 1
28244 // SIMD-ONLY0-NEXT:    [[CONV191:%.*]] = zext i8 [[TMP81]] to i32
28245 // SIMD-ONLY0-NEXT:    [[TMP82:%.*]] = load i8, ptr [[UCX]], align 1
28246 // SIMD-ONLY0-NEXT:    [[CONV192:%.*]] = zext i8 [[TMP82]] to i32
28247 // SIMD-ONLY0-NEXT:    [[CMP193:%.*]] = icmp eq i32 [[CONV191]], [[CONV192]]
28248 // SIMD-ONLY0-NEXT:    br i1 [[CMP193]], label [[IF_THEN195:%.*]], label [[IF_END196:%.*]]
28249 // SIMD-ONLY0:       if.then195:
28250 // SIMD-ONLY0-NEXT:    [[TMP83:%.*]] = load i8, ptr [[UCD]], align 1
28251 // SIMD-ONLY0-NEXT:    store i8 [[TMP83]], ptr [[UCX]], align 1
28252 // SIMD-ONLY0-NEXT:    br label [[IF_END196]]
28253 // SIMD-ONLY0:       if.end196:
28254 // SIMD-ONLY0-NEXT:    [[TMP84:%.*]] = load i8, ptr [[CX]], align 1
28255 // SIMD-ONLY0-NEXT:    [[CONV197:%.*]] = sext i8 [[TMP84]] to i32
28256 // SIMD-ONLY0-NEXT:    [[TMP85:%.*]] = load i8, ptr [[CE]], align 1
28257 // SIMD-ONLY0-NEXT:    [[CONV198:%.*]] = sext i8 [[TMP85]] to i32
28258 // SIMD-ONLY0-NEXT:    [[CMP199:%.*]] = icmp sgt i32 [[CONV197]], [[CONV198]]
28259 // SIMD-ONLY0-NEXT:    br i1 [[CMP199]], label [[COND_TRUE201:%.*]], label [[COND_FALSE203:%.*]]
28260 // SIMD-ONLY0:       cond.true201:
28261 // SIMD-ONLY0-NEXT:    [[TMP86:%.*]] = load i8, ptr [[CE]], align 1
28262 // SIMD-ONLY0-NEXT:    [[CONV202:%.*]] = sext i8 [[TMP86]] to i32
28263 // SIMD-ONLY0-NEXT:    br label [[COND_END205:%.*]]
28264 // SIMD-ONLY0:       cond.false203:
28265 // SIMD-ONLY0-NEXT:    [[TMP87:%.*]] = load i8, ptr [[CX]], align 1
28266 // SIMD-ONLY0-NEXT:    [[CONV204:%.*]] = sext i8 [[TMP87]] to i32
28267 // SIMD-ONLY0-NEXT:    br label [[COND_END205]]
28268 // SIMD-ONLY0:       cond.end205:
28269 // SIMD-ONLY0-NEXT:    [[COND206:%.*]] = phi i32 [ [[CONV202]], [[COND_TRUE201]] ], [ [[CONV204]], [[COND_FALSE203]] ]
28270 // SIMD-ONLY0-NEXT:    [[CONV207:%.*]] = trunc i32 [[COND206]] to i8
28271 // SIMD-ONLY0-NEXT:    store i8 [[CONV207]], ptr [[CX]], align 1
28272 // SIMD-ONLY0-NEXT:    [[TMP88:%.*]] = load i8, ptr [[CX]], align 1
28273 // SIMD-ONLY0-NEXT:    [[CONV208:%.*]] = sext i8 [[TMP88]] to i32
28274 // SIMD-ONLY0-NEXT:    [[TMP89:%.*]] = load i8, ptr [[CE]], align 1
28275 // SIMD-ONLY0-NEXT:    [[CONV209:%.*]] = sext i8 [[TMP89]] to i32
28276 // SIMD-ONLY0-NEXT:    [[CMP210:%.*]] = icmp slt i32 [[CONV208]], [[CONV209]]
28277 // SIMD-ONLY0-NEXT:    br i1 [[CMP210]], label [[COND_TRUE212:%.*]], label [[COND_FALSE214:%.*]]
28278 // SIMD-ONLY0:       cond.true212:
28279 // SIMD-ONLY0-NEXT:    [[TMP90:%.*]] = load i8, ptr [[CE]], align 1
28280 // SIMD-ONLY0-NEXT:    [[CONV213:%.*]] = sext i8 [[TMP90]] to i32
28281 // SIMD-ONLY0-NEXT:    br label [[COND_END216:%.*]]
28282 // SIMD-ONLY0:       cond.false214:
28283 // SIMD-ONLY0-NEXT:    [[TMP91:%.*]] = load i8, ptr [[CX]], align 1
28284 // SIMD-ONLY0-NEXT:    [[CONV215:%.*]] = sext i8 [[TMP91]] to i32
28285 // SIMD-ONLY0-NEXT:    br label [[COND_END216]]
28286 // SIMD-ONLY0:       cond.end216:
28287 // SIMD-ONLY0-NEXT:    [[COND217:%.*]] = phi i32 [ [[CONV213]], [[COND_TRUE212]] ], [ [[CONV215]], [[COND_FALSE214]] ]
28288 // SIMD-ONLY0-NEXT:    [[CONV218:%.*]] = trunc i32 [[COND217]] to i8
28289 // SIMD-ONLY0-NEXT:    store i8 [[CONV218]], ptr [[CX]], align 1
28290 // SIMD-ONLY0-NEXT:    [[TMP92:%.*]] = load i8, ptr [[CE]], align 1
28291 // SIMD-ONLY0-NEXT:    [[CONV219:%.*]] = sext i8 [[TMP92]] to i32
28292 // SIMD-ONLY0-NEXT:    [[TMP93:%.*]] = load i8, ptr [[CX]], align 1
28293 // SIMD-ONLY0-NEXT:    [[CONV220:%.*]] = sext i8 [[TMP93]] to i32
28294 // SIMD-ONLY0-NEXT:    [[CMP221:%.*]] = icmp sgt i32 [[CONV219]], [[CONV220]]
28295 // SIMD-ONLY0-NEXT:    br i1 [[CMP221]], label [[COND_TRUE223:%.*]], label [[COND_FALSE225:%.*]]
28296 // SIMD-ONLY0:       cond.true223:
28297 // SIMD-ONLY0-NEXT:    [[TMP94:%.*]] = load i8, ptr [[CE]], align 1
28298 // SIMD-ONLY0-NEXT:    [[CONV224:%.*]] = sext i8 [[TMP94]] to i32
28299 // SIMD-ONLY0-NEXT:    br label [[COND_END227:%.*]]
28300 // SIMD-ONLY0:       cond.false225:
28301 // SIMD-ONLY0-NEXT:    [[TMP95:%.*]] = load i8, ptr [[CX]], align 1
28302 // SIMD-ONLY0-NEXT:    [[CONV226:%.*]] = sext i8 [[TMP95]] to i32
28303 // SIMD-ONLY0-NEXT:    br label [[COND_END227]]
28304 // SIMD-ONLY0:       cond.end227:
28305 // SIMD-ONLY0-NEXT:    [[COND228:%.*]] = phi i32 [ [[CONV224]], [[COND_TRUE223]] ], [ [[CONV226]], [[COND_FALSE225]] ]
28306 // SIMD-ONLY0-NEXT:    [[CONV229:%.*]] = trunc i32 [[COND228]] to i8
28307 // SIMD-ONLY0-NEXT:    store i8 [[CONV229]], ptr [[CX]], align 1
28308 // SIMD-ONLY0-NEXT:    [[TMP96:%.*]] = load i8, ptr [[CE]], align 1
28309 // SIMD-ONLY0-NEXT:    [[CONV230:%.*]] = sext i8 [[TMP96]] to i32
28310 // SIMD-ONLY0-NEXT:    [[TMP97:%.*]] = load i8, ptr [[CX]], align 1
28311 // SIMD-ONLY0-NEXT:    [[CONV231:%.*]] = sext i8 [[TMP97]] to i32
28312 // SIMD-ONLY0-NEXT:    [[CMP232:%.*]] = icmp slt i32 [[CONV230]], [[CONV231]]
28313 // SIMD-ONLY0-NEXT:    br i1 [[CMP232]], label [[COND_TRUE234:%.*]], label [[COND_FALSE236:%.*]]
28314 // SIMD-ONLY0:       cond.true234:
28315 // SIMD-ONLY0-NEXT:    [[TMP98:%.*]] = load i8, ptr [[CE]], align 1
28316 // SIMD-ONLY0-NEXT:    [[CONV235:%.*]] = sext i8 [[TMP98]] to i32
28317 // SIMD-ONLY0-NEXT:    br label [[COND_END238:%.*]]
28318 // SIMD-ONLY0:       cond.false236:
28319 // SIMD-ONLY0-NEXT:    [[TMP99:%.*]] = load i8, ptr [[CX]], align 1
28320 // SIMD-ONLY0-NEXT:    [[CONV237:%.*]] = sext i8 [[TMP99]] to i32
28321 // SIMD-ONLY0-NEXT:    br label [[COND_END238]]
28322 // SIMD-ONLY0:       cond.end238:
28323 // SIMD-ONLY0-NEXT:    [[COND239:%.*]] = phi i32 [ [[CONV235]], [[COND_TRUE234]] ], [ [[CONV237]], [[COND_FALSE236]] ]
28324 // SIMD-ONLY0-NEXT:    [[CONV240:%.*]] = trunc i32 [[COND239]] to i8
28325 // SIMD-ONLY0-NEXT:    store i8 [[CONV240]], ptr [[CX]], align 1
28326 // SIMD-ONLY0-NEXT:    [[TMP100:%.*]] = load i8, ptr [[CX]], align 1
28327 // SIMD-ONLY0-NEXT:    [[CONV241:%.*]] = sext i8 [[TMP100]] to i32
28328 // SIMD-ONLY0-NEXT:    [[TMP101:%.*]] = load i8, ptr [[CE]], align 1
28329 // SIMD-ONLY0-NEXT:    [[CONV242:%.*]] = sext i8 [[TMP101]] to i32
28330 // SIMD-ONLY0-NEXT:    [[CMP243:%.*]] = icmp sgt i32 [[CONV241]], [[CONV242]]
28331 // SIMD-ONLY0-NEXT:    br i1 [[CMP243]], label [[IF_THEN245:%.*]], label [[IF_END246:%.*]]
28332 // SIMD-ONLY0:       if.then245:
28333 // SIMD-ONLY0-NEXT:    [[TMP102:%.*]] = load i8, ptr [[CE]], align 1
28334 // SIMD-ONLY0-NEXT:    store i8 [[TMP102]], ptr [[CX]], align 1
28335 // SIMD-ONLY0-NEXT:    br label [[IF_END246]]
28336 // SIMD-ONLY0:       if.end246:
28337 // SIMD-ONLY0-NEXT:    [[TMP103:%.*]] = load i8, ptr [[CX]], align 1
28338 // SIMD-ONLY0-NEXT:    [[CONV247:%.*]] = sext i8 [[TMP103]] to i32
28339 // SIMD-ONLY0-NEXT:    [[TMP104:%.*]] = load i8, ptr [[CE]], align 1
28340 // SIMD-ONLY0-NEXT:    [[CONV248:%.*]] = sext i8 [[TMP104]] to i32
28341 // SIMD-ONLY0-NEXT:    [[CMP249:%.*]] = icmp slt i32 [[CONV247]], [[CONV248]]
28342 // SIMD-ONLY0-NEXT:    br i1 [[CMP249]], label [[IF_THEN251:%.*]], label [[IF_END252:%.*]]
28343 // SIMD-ONLY0:       if.then251:
28344 // SIMD-ONLY0-NEXT:    [[TMP105:%.*]] = load i8, ptr [[CE]], align 1
28345 // SIMD-ONLY0-NEXT:    store i8 [[TMP105]], ptr [[CX]], align 1
28346 // SIMD-ONLY0-NEXT:    br label [[IF_END252]]
28347 // SIMD-ONLY0:       if.end252:
28348 // SIMD-ONLY0-NEXT:    [[TMP106:%.*]] = load i8, ptr [[CE]], align 1
28349 // SIMD-ONLY0-NEXT:    [[CONV253:%.*]] = sext i8 [[TMP106]] to i32
28350 // SIMD-ONLY0-NEXT:    [[TMP107:%.*]] = load i8, ptr [[CX]], align 1
28351 // SIMD-ONLY0-NEXT:    [[CONV254:%.*]] = sext i8 [[TMP107]] to i32
28352 // SIMD-ONLY0-NEXT:    [[CMP255:%.*]] = icmp sgt i32 [[CONV253]], [[CONV254]]
28353 // SIMD-ONLY0-NEXT:    br i1 [[CMP255]], label [[IF_THEN257:%.*]], label [[IF_END258:%.*]]
28354 // SIMD-ONLY0:       if.then257:
28355 // SIMD-ONLY0-NEXT:    [[TMP108:%.*]] = load i8, ptr [[CE]], align 1
28356 // SIMD-ONLY0-NEXT:    store i8 [[TMP108]], ptr [[CX]], align 1
28357 // SIMD-ONLY0-NEXT:    br label [[IF_END258]]
28358 // SIMD-ONLY0:       if.end258:
28359 // SIMD-ONLY0-NEXT:    [[TMP109:%.*]] = load i8, ptr [[CE]], align 1
28360 // SIMD-ONLY0-NEXT:    [[CONV259:%.*]] = sext i8 [[TMP109]] to i32
28361 // SIMD-ONLY0-NEXT:    [[TMP110:%.*]] = load i8, ptr [[CX]], align 1
28362 // SIMD-ONLY0-NEXT:    [[CONV260:%.*]] = sext i8 [[TMP110]] to i32
28363 // SIMD-ONLY0-NEXT:    [[CMP261:%.*]] = icmp slt i32 [[CONV259]], [[CONV260]]
28364 // SIMD-ONLY0-NEXT:    br i1 [[CMP261]], label [[IF_THEN263:%.*]], label [[IF_END264:%.*]]
28365 // SIMD-ONLY0:       if.then263:
28366 // SIMD-ONLY0-NEXT:    [[TMP111:%.*]] = load i8, ptr [[CE]], align 1
28367 // SIMD-ONLY0-NEXT:    store i8 [[TMP111]], ptr [[CX]], align 1
28368 // SIMD-ONLY0-NEXT:    br label [[IF_END264]]
28369 // SIMD-ONLY0:       if.end264:
28370 // SIMD-ONLY0-NEXT:    [[TMP112:%.*]] = load i8, ptr [[CX]], align 1
28371 // SIMD-ONLY0-NEXT:    [[CONV265:%.*]] = sext i8 [[TMP112]] to i32
28372 // SIMD-ONLY0-NEXT:    [[TMP113:%.*]] = load i8, ptr [[CE]], align 1
28373 // SIMD-ONLY0-NEXT:    [[CONV266:%.*]] = sext i8 [[TMP113]] to i32
28374 // SIMD-ONLY0-NEXT:    [[CMP267:%.*]] = icmp eq i32 [[CONV265]], [[CONV266]]
28375 // SIMD-ONLY0-NEXT:    br i1 [[CMP267]], label [[COND_TRUE269:%.*]], label [[COND_FALSE271:%.*]]
28376 // SIMD-ONLY0:       cond.true269:
28377 // SIMD-ONLY0-NEXT:    [[TMP114:%.*]] = load i8, ptr [[CD]], align 1
28378 // SIMD-ONLY0-NEXT:    [[CONV270:%.*]] = sext i8 [[TMP114]] to i32
28379 // SIMD-ONLY0-NEXT:    br label [[COND_END273:%.*]]
28380 // SIMD-ONLY0:       cond.false271:
28381 // SIMD-ONLY0-NEXT:    [[TMP115:%.*]] = load i8, ptr [[CX]], align 1
28382 // SIMD-ONLY0-NEXT:    [[CONV272:%.*]] = sext i8 [[TMP115]] to i32
28383 // SIMD-ONLY0-NEXT:    br label [[COND_END273]]
28384 // SIMD-ONLY0:       cond.end273:
28385 // SIMD-ONLY0-NEXT:    [[COND274:%.*]] = phi i32 [ [[CONV270]], [[COND_TRUE269]] ], [ [[CONV272]], [[COND_FALSE271]] ]
28386 // SIMD-ONLY0-NEXT:    [[CONV275:%.*]] = trunc i32 [[COND274]] to i8
28387 // SIMD-ONLY0-NEXT:    store i8 [[CONV275]], ptr [[CX]], align 1
28388 // SIMD-ONLY0-NEXT:    [[TMP116:%.*]] = load i8, ptr [[CE]], align 1
28389 // SIMD-ONLY0-NEXT:    [[CONV276:%.*]] = sext i8 [[TMP116]] to i32
28390 // SIMD-ONLY0-NEXT:    [[TMP117:%.*]] = load i8, ptr [[CX]], align 1
28391 // SIMD-ONLY0-NEXT:    [[CONV277:%.*]] = sext i8 [[TMP117]] to i32
28392 // SIMD-ONLY0-NEXT:    [[CMP278:%.*]] = icmp eq i32 [[CONV276]], [[CONV277]]
28393 // SIMD-ONLY0-NEXT:    br i1 [[CMP278]], label [[COND_TRUE280:%.*]], label [[COND_FALSE282:%.*]]
28394 // SIMD-ONLY0:       cond.true280:
28395 // SIMD-ONLY0-NEXT:    [[TMP118:%.*]] = load i8, ptr [[CD]], align 1
28396 // SIMD-ONLY0-NEXT:    [[CONV281:%.*]] = sext i8 [[TMP118]] to i32
28397 // SIMD-ONLY0-NEXT:    br label [[COND_END284:%.*]]
28398 // SIMD-ONLY0:       cond.false282:
28399 // SIMD-ONLY0-NEXT:    [[TMP119:%.*]] = load i8, ptr [[CX]], align 1
28400 // SIMD-ONLY0-NEXT:    [[CONV283:%.*]] = sext i8 [[TMP119]] to i32
28401 // SIMD-ONLY0-NEXT:    br label [[COND_END284]]
28402 // SIMD-ONLY0:       cond.end284:
28403 // SIMD-ONLY0-NEXT:    [[COND285:%.*]] = phi i32 [ [[CONV281]], [[COND_TRUE280]] ], [ [[CONV283]], [[COND_FALSE282]] ]
28404 // SIMD-ONLY0-NEXT:    [[CONV286:%.*]] = trunc i32 [[COND285]] to i8
28405 // SIMD-ONLY0-NEXT:    store i8 [[CONV286]], ptr [[CX]], align 1
28406 // SIMD-ONLY0-NEXT:    [[TMP120:%.*]] = load i8, ptr [[CX]], align 1
28407 // SIMD-ONLY0-NEXT:    [[CONV287:%.*]] = sext i8 [[TMP120]] to i32
28408 // SIMD-ONLY0-NEXT:    [[TMP121:%.*]] = load i8, ptr [[CE]], align 1
28409 // SIMD-ONLY0-NEXT:    [[CONV288:%.*]] = sext i8 [[TMP121]] to i32
28410 // SIMD-ONLY0-NEXT:    [[CMP289:%.*]] = icmp eq i32 [[CONV287]], [[CONV288]]
28411 // SIMD-ONLY0-NEXT:    br i1 [[CMP289]], label [[IF_THEN291:%.*]], label [[IF_END292:%.*]]
28412 // SIMD-ONLY0:       if.then291:
28413 // SIMD-ONLY0-NEXT:    [[TMP122:%.*]] = load i8, ptr [[CD]], align 1
28414 // SIMD-ONLY0-NEXT:    store i8 [[TMP122]], ptr [[CX]], align 1
28415 // SIMD-ONLY0-NEXT:    br label [[IF_END292]]
28416 // SIMD-ONLY0:       if.end292:
28417 // SIMD-ONLY0-NEXT:    [[TMP123:%.*]] = load i8, ptr [[CE]], align 1
28418 // SIMD-ONLY0-NEXT:    [[CONV293:%.*]] = sext i8 [[TMP123]] to i32
28419 // SIMD-ONLY0-NEXT:    [[TMP124:%.*]] = load i8, ptr [[CX]], align 1
28420 // SIMD-ONLY0-NEXT:    [[CONV294:%.*]] = sext i8 [[TMP124]] to i32
28421 // SIMD-ONLY0-NEXT:    [[CMP295:%.*]] = icmp eq i32 [[CONV293]], [[CONV294]]
28422 // SIMD-ONLY0-NEXT:    br i1 [[CMP295]], label [[IF_THEN297:%.*]], label [[IF_END298:%.*]]
28423 // SIMD-ONLY0:       if.then297:
28424 // SIMD-ONLY0-NEXT:    [[TMP125:%.*]] = load i8, ptr [[CD]], align 1
28425 // SIMD-ONLY0-NEXT:    store i8 [[TMP125]], ptr [[CX]], align 1
28426 // SIMD-ONLY0-NEXT:    br label [[IF_END298]]
28427 // SIMD-ONLY0:       if.end298:
28428 // SIMD-ONLY0-NEXT:    [[TMP126:%.*]] = load i8, ptr [[UCX]], align 1
28429 // SIMD-ONLY0-NEXT:    [[CONV299:%.*]] = zext i8 [[TMP126]] to i32
28430 // SIMD-ONLY0-NEXT:    [[TMP127:%.*]] = load i8, ptr [[UCE]], align 1
28431 // SIMD-ONLY0-NEXT:    [[CONV300:%.*]] = zext i8 [[TMP127]] to i32
28432 // SIMD-ONLY0-NEXT:    [[CMP301:%.*]] = icmp sgt i32 [[CONV299]], [[CONV300]]
28433 // SIMD-ONLY0-NEXT:    br i1 [[CMP301]], label [[COND_TRUE303:%.*]], label [[COND_FALSE305:%.*]]
28434 // SIMD-ONLY0:       cond.true303:
28435 // SIMD-ONLY0-NEXT:    [[TMP128:%.*]] = load i8, ptr [[UCE]], align 1
28436 // SIMD-ONLY0-NEXT:    [[CONV304:%.*]] = zext i8 [[TMP128]] to i32
28437 // SIMD-ONLY0-NEXT:    br label [[COND_END307:%.*]]
28438 // SIMD-ONLY0:       cond.false305:
28439 // SIMD-ONLY0-NEXT:    [[TMP129:%.*]] = load i8, ptr [[UCX]], align 1
28440 // SIMD-ONLY0-NEXT:    [[CONV306:%.*]] = zext i8 [[TMP129]] to i32
28441 // SIMD-ONLY0-NEXT:    br label [[COND_END307]]
28442 // SIMD-ONLY0:       cond.end307:
28443 // SIMD-ONLY0-NEXT:    [[COND308:%.*]] = phi i32 [ [[CONV304]], [[COND_TRUE303]] ], [ [[CONV306]], [[COND_FALSE305]] ]
28444 // SIMD-ONLY0-NEXT:    [[CONV309:%.*]] = trunc i32 [[COND308]] to i8
28445 // SIMD-ONLY0-NEXT:    store i8 [[CONV309]], ptr [[UCX]], align 1
28446 // SIMD-ONLY0-NEXT:    [[TMP130:%.*]] = load i8, ptr [[UCX]], align 1
28447 // SIMD-ONLY0-NEXT:    [[CONV310:%.*]] = zext i8 [[TMP130]] to i32
28448 // SIMD-ONLY0-NEXT:    [[TMP131:%.*]] = load i8, ptr [[UCE]], align 1
28449 // SIMD-ONLY0-NEXT:    [[CONV311:%.*]] = zext i8 [[TMP131]] to i32
28450 // SIMD-ONLY0-NEXT:    [[CMP312:%.*]] = icmp slt i32 [[CONV310]], [[CONV311]]
28451 // SIMD-ONLY0-NEXT:    br i1 [[CMP312]], label [[COND_TRUE314:%.*]], label [[COND_FALSE316:%.*]]
28452 // SIMD-ONLY0:       cond.true314:
28453 // SIMD-ONLY0-NEXT:    [[TMP132:%.*]] = load i8, ptr [[UCE]], align 1
28454 // SIMD-ONLY0-NEXT:    [[CONV315:%.*]] = zext i8 [[TMP132]] to i32
28455 // SIMD-ONLY0-NEXT:    br label [[COND_END318:%.*]]
28456 // SIMD-ONLY0:       cond.false316:
28457 // SIMD-ONLY0-NEXT:    [[TMP133:%.*]] = load i8, ptr [[UCX]], align 1
28458 // SIMD-ONLY0-NEXT:    [[CONV317:%.*]] = zext i8 [[TMP133]] to i32
28459 // SIMD-ONLY0-NEXT:    br label [[COND_END318]]
28460 // SIMD-ONLY0:       cond.end318:
28461 // SIMD-ONLY0-NEXT:    [[COND319:%.*]] = phi i32 [ [[CONV315]], [[COND_TRUE314]] ], [ [[CONV317]], [[COND_FALSE316]] ]
28462 // SIMD-ONLY0-NEXT:    [[CONV320:%.*]] = trunc i32 [[COND319]] to i8
28463 // SIMD-ONLY0-NEXT:    store i8 [[CONV320]], ptr [[UCX]], align 1
28464 // SIMD-ONLY0-NEXT:    [[TMP134:%.*]] = load i8, ptr [[UCE]], align 1
28465 // SIMD-ONLY0-NEXT:    [[CONV321:%.*]] = zext i8 [[TMP134]] to i32
28466 // SIMD-ONLY0-NEXT:    [[TMP135:%.*]] = load i8, ptr [[UCX]], align 1
28467 // SIMD-ONLY0-NEXT:    [[CONV322:%.*]] = zext i8 [[TMP135]] to i32
28468 // SIMD-ONLY0-NEXT:    [[CMP323:%.*]] = icmp sgt i32 [[CONV321]], [[CONV322]]
28469 // SIMD-ONLY0-NEXT:    br i1 [[CMP323]], label [[COND_TRUE325:%.*]], label [[COND_FALSE327:%.*]]
28470 // SIMD-ONLY0:       cond.true325:
28471 // SIMD-ONLY0-NEXT:    [[TMP136:%.*]] = load i8, ptr [[UCE]], align 1
28472 // SIMD-ONLY0-NEXT:    [[CONV326:%.*]] = zext i8 [[TMP136]] to i32
28473 // SIMD-ONLY0-NEXT:    br label [[COND_END329:%.*]]
28474 // SIMD-ONLY0:       cond.false327:
28475 // SIMD-ONLY0-NEXT:    [[TMP137:%.*]] = load i8, ptr [[UCX]], align 1
28476 // SIMD-ONLY0-NEXT:    [[CONV328:%.*]] = zext i8 [[TMP137]] to i32
28477 // SIMD-ONLY0-NEXT:    br label [[COND_END329]]
28478 // SIMD-ONLY0:       cond.end329:
28479 // SIMD-ONLY0-NEXT:    [[COND330:%.*]] = phi i32 [ [[CONV326]], [[COND_TRUE325]] ], [ [[CONV328]], [[COND_FALSE327]] ]
28480 // SIMD-ONLY0-NEXT:    [[CONV331:%.*]] = trunc i32 [[COND330]] to i8
28481 // SIMD-ONLY0-NEXT:    store i8 [[CONV331]], ptr [[UCX]], align 1
28482 // SIMD-ONLY0-NEXT:    [[TMP138:%.*]] = load i8, ptr [[UCE]], align 1
28483 // SIMD-ONLY0-NEXT:    [[CONV332:%.*]] = zext i8 [[TMP138]] to i32
28484 // SIMD-ONLY0-NEXT:    [[TMP139:%.*]] = load i8, ptr [[UCX]], align 1
28485 // SIMD-ONLY0-NEXT:    [[CONV333:%.*]] = zext i8 [[TMP139]] to i32
28486 // SIMD-ONLY0-NEXT:    [[CMP334:%.*]] = icmp slt i32 [[CONV332]], [[CONV333]]
28487 // SIMD-ONLY0-NEXT:    br i1 [[CMP334]], label [[COND_TRUE336:%.*]], label [[COND_FALSE338:%.*]]
28488 // SIMD-ONLY0:       cond.true336:
28489 // SIMD-ONLY0-NEXT:    [[TMP140:%.*]] = load i8, ptr [[UCE]], align 1
28490 // SIMD-ONLY0-NEXT:    [[CONV337:%.*]] = zext i8 [[TMP140]] to i32
28491 // SIMD-ONLY0-NEXT:    br label [[COND_END340:%.*]]
28492 // SIMD-ONLY0:       cond.false338:
28493 // SIMD-ONLY0-NEXT:    [[TMP141:%.*]] = load i8, ptr [[UCX]], align 1
28494 // SIMD-ONLY0-NEXT:    [[CONV339:%.*]] = zext i8 [[TMP141]] to i32
28495 // SIMD-ONLY0-NEXT:    br label [[COND_END340]]
28496 // SIMD-ONLY0:       cond.end340:
28497 // SIMD-ONLY0-NEXT:    [[COND341:%.*]] = phi i32 [ [[CONV337]], [[COND_TRUE336]] ], [ [[CONV339]], [[COND_FALSE338]] ]
28498 // SIMD-ONLY0-NEXT:    [[CONV342:%.*]] = trunc i32 [[COND341]] to i8
28499 // SIMD-ONLY0-NEXT:    store i8 [[CONV342]], ptr [[UCX]], align 1
28500 // SIMD-ONLY0-NEXT:    [[TMP142:%.*]] = load i8, ptr [[UCX]], align 1
28501 // SIMD-ONLY0-NEXT:    [[CONV343:%.*]] = zext i8 [[TMP142]] to i32
28502 // SIMD-ONLY0-NEXT:    [[TMP143:%.*]] = load i8, ptr [[UCE]], align 1
28503 // SIMD-ONLY0-NEXT:    [[CONV344:%.*]] = zext i8 [[TMP143]] to i32
28504 // SIMD-ONLY0-NEXT:    [[CMP345:%.*]] = icmp sgt i32 [[CONV343]], [[CONV344]]
28505 // SIMD-ONLY0-NEXT:    br i1 [[CMP345]], label [[IF_THEN347:%.*]], label [[IF_END348:%.*]]
28506 // SIMD-ONLY0:       if.then347:
28507 // SIMD-ONLY0-NEXT:    [[TMP144:%.*]] = load i8, ptr [[UCE]], align 1
28508 // SIMD-ONLY0-NEXT:    store i8 [[TMP144]], ptr [[UCX]], align 1
28509 // SIMD-ONLY0-NEXT:    br label [[IF_END348]]
28510 // SIMD-ONLY0:       if.end348:
28511 // SIMD-ONLY0-NEXT:    [[TMP145:%.*]] = load i8, ptr [[UCX]], align 1
28512 // SIMD-ONLY0-NEXT:    [[CONV349:%.*]] = zext i8 [[TMP145]] to i32
28513 // SIMD-ONLY0-NEXT:    [[TMP146:%.*]] = load i8, ptr [[UCE]], align 1
28514 // SIMD-ONLY0-NEXT:    [[CONV350:%.*]] = zext i8 [[TMP146]] to i32
28515 // SIMD-ONLY0-NEXT:    [[CMP351:%.*]] = icmp slt i32 [[CONV349]], [[CONV350]]
28516 // SIMD-ONLY0-NEXT:    br i1 [[CMP351]], label [[IF_THEN353:%.*]], label [[IF_END354:%.*]]
28517 // SIMD-ONLY0:       if.then353:
28518 // SIMD-ONLY0-NEXT:    [[TMP147:%.*]] = load i8, ptr [[UCE]], align 1
28519 // SIMD-ONLY0-NEXT:    store i8 [[TMP147]], ptr [[UCX]], align 1
28520 // SIMD-ONLY0-NEXT:    br label [[IF_END354]]
28521 // SIMD-ONLY0:       if.end354:
28522 // SIMD-ONLY0-NEXT:    [[TMP148:%.*]] = load i8, ptr [[UCE]], align 1
28523 // SIMD-ONLY0-NEXT:    [[CONV355:%.*]] = zext i8 [[TMP148]] to i32
28524 // SIMD-ONLY0-NEXT:    [[TMP149:%.*]] = load i8, ptr [[UCX]], align 1
28525 // SIMD-ONLY0-NEXT:    [[CONV356:%.*]] = zext i8 [[TMP149]] to i32
28526 // SIMD-ONLY0-NEXT:    [[CMP357:%.*]] = icmp sgt i32 [[CONV355]], [[CONV356]]
28527 // SIMD-ONLY0-NEXT:    br i1 [[CMP357]], label [[IF_THEN359:%.*]], label [[IF_END360:%.*]]
28528 // SIMD-ONLY0:       if.then359:
28529 // SIMD-ONLY0-NEXT:    [[TMP150:%.*]] = load i8, ptr [[UCE]], align 1
28530 // SIMD-ONLY0-NEXT:    store i8 [[TMP150]], ptr [[UCX]], align 1
28531 // SIMD-ONLY0-NEXT:    br label [[IF_END360]]
28532 // SIMD-ONLY0:       if.end360:
28533 // SIMD-ONLY0-NEXT:    [[TMP151:%.*]] = load i8, ptr [[UCE]], align 1
28534 // SIMD-ONLY0-NEXT:    [[CONV361:%.*]] = zext i8 [[TMP151]] to i32
28535 // SIMD-ONLY0-NEXT:    [[TMP152:%.*]] = load i8, ptr [[UCX]], align 1
28536 // SIMD-ONLY0-NEXT:    [[CONV362:%.*]] = zext i8 [[TMP152]] to i32
28537 // SIMD-ONLY0-NEXT:    [[CMP363:%.*]] = icmp slt i32 [[CONV361]], [[CONV362]]
28538 // SIMD-ONLY0-NEXT:    br i1 [[CMP363]], label [[IF_THEN365:%.*]], label [[IF_END366:%.*]]
28539 // SIMD-ONLY0:       if.then365:
28540 // SIMD-ONLY0-NEXT:    [[TMP153:%.*]] = load i8, ptr [[UCE]], align 1
28541 // SIMD-ONLY0-NEXT:    store i8 [[TMP153]], ptr [[UCX]], align 1
28542 // SIMD-ONLY0-NEXT:    br label [[IF_END366]]
28543 // SIMD-ONLY0:       if.end366:
28544 // SIMD-ONLY0-NEXT:    [[TMP154:%.*]] = load i8, ptr [[UCX]], align 1
28545 // SIMD-ONLY0-NEXT:    [[CONV367:%.*]] = zext i8 [[TMP154]] to i32
28546 // SIMD-ONLY0-NEXT:    [[TMP155:%.*]] = load i8, ptr [[UCE]], align 1
28547 // SIMD-ONLY0-NEXT:    [[CONV368:%.*]] = zext i8 [[TMP155]] to i32
28548 // SIMD-ONLY0-NEXT:    [[CMP369:%.*]] = icmp eq i32 [[CONV367]], [[CONV368]]
28549 // SIMD-ONLY0-NEXT:    br i1 [[CMP369]], label [[COND_TRUE371:%.*]], label [[COND_FALSE373:%.*]]
28550 // SIMD-ONLY0:       cond.true371:
28551 // SIMD-ONLY0-NEXT:    [[TMP156:%.*]] = load i8, ptr [[UCD]], align 1
28552 // SIMD-ONLY0-NEXT:    [[CONV372:%.*]] = zext i8 [[TMP156]] to i32
28553 // SIMD-ONLY0-NEXT:    br label [[COND_END375:%.*]]
28554 // SIMD-ONLY0:       cond.false373:
28555 // SIMD-ONLY0-NEXT:    [[TMP157:%.*]] = load i8, ptr [[UCX]], align 1
28556 // SIMD-ONLY0-NEXT:    [[CONV374:%.*]] = zext i8 [[TMP157]] to i32
28557 // SIMD-ONLY0-NEXT:    br label [[COND_END375]]
28558 // SIMD-ONLY0:       cond.end375:
28559 // SIMD-ONLY0-NEXT:    [[COND376:%.*]] = phi i32 [ [[CONV372]], [[COND_TRUE371]] ], [ [[CONV374]], [[COND_FALSE373]] ]
28560 // SIMD-ONLY0-NEXT:    [[CONV377:%.*]] = trunc i32 [[COND376]] to i8
28561 // SIMD-ONLY0-NEXT:    store i8 [[CONV377]], ptr [[UCX]], align 1
28562 // SIMD-ONLY0-NEXT:    [[TMP158:%.*]] = load i8, ptr [[UCE]], align 1
28563 // SIMD-ONLY0-NEXT:    [[CONV378:%.*]] = zext i8 [[TMP158]] to i32
28564 // SIMD-ONLY0-NEXT:    [[TMP159:%.*]] = load i8, ptr [[UCX]], align 1
28565 // SIMD-ONLY0-NEXT:    [[CONV379:%.*]] = zext i8 [[TMP159]] to i32
28566 // SIMD-ONLY0-NEXT:    [[CMP380:%.*]] = icmp eq i32 [[CONV378]], [[CONV379]]
28567 // SIMD-ONLY0-NEXT:    br i1 [[CMP380]], label [[COND_TRUE382:%.*]], label [[COND_FALSE384:%.*]]
28568 // SIMD-ONLY0:       cond.true382:
28569 // SIMD-ONLY0-NEXT:    [[TMP160:%.*]] = load i8, ptr [[UCD]], align 1
28570 // SIMD-ONLY0-NEXT:    [[CONV383:%.*]] = zext i8 [[TMP160]] to i32
28571 // SIMD-ONLY0-NEXT:    br label [[COND_END386:%.*]]
28572 // SIMD-ONLY0:       cond.false384:
28573 // SIMD-ONLY0-NEXT:    [[TMP161:%.*]] = load i8, ptr [[UCX]], align 1
28574 // SIMD-ONLY0-NEXT:    [[CONV385:%.*]] = zext i8 [[TMP161]] to i32
28575 // SIMD-ONLY0-NEXT:    br label [[COND_END386]]
28576 // SIMD-ONLY0:       cond.end386:
28577 // SIMD-ONLY0-NEXT:    [[COND387:%.*]] = phi i32 [ [[CONV383]], [[COND_TRUE382]] ], [ [[CONV385]], [[COND_FALSE384]] ]
28578 // SIMD-ONLY0-NEXT:    [[CONV388:%.*]] = trunc i32 [[COND387]] to i8
28579 // SIMD-ONLY0-NEXT:    store i8 [[CONV388]], ptr [[UCX]], align 1
28580 // SIMD-ONLY0-NEXT:    [[TMP162:%.*]] = load i8, ptr [[UCX]], align 1
28581 // SIMD-ONLY0-NEXT:    [[CONV389:%.*]] = zext i8 [[TMP162]] to i32
28582 // SIMD-ONLY0-NEXT:    [[TMP163:%.*]] = load i8, ptr [[UCE]], align 1
28583 // SIMD-ONLY0-NEXT:    [[CONV390:%.*]] = zext i8 [[TMP163]] to i32
28584 // SIMD-ONLY0-NEXT:    [[CMP391:%.*]] = icmp eq i32 [[CONV389]], [[CONV390]]
28585 // SIMD-ONLY0-NEXT:    br i1 [[CMP391]], label [[IF_THEN393:%.*]], label [[IF_END394:%.*]]
28586 // SIMD-ONLY0:       if.then393:
28587 // SIMD-ONLY0-NEXT:    [[TMP164:%.*]] = load i8, ptr [[UCD]], align 1
28588 // SIMD-ONLY0-NEXT:    store i8 [[TMP164]], ptr [[UCX]], align 1
28589 // SIMD-ONLY0-NEXT:    br label [[IF_END394]]
28590 // SIMD-ONLY0:       if.end394:
28591 // SIMD-ONLY0-NEXT:    [[TMP165:%.*]] = load i8, ptr [[UCE]], align 1
28592 // SIMD-ONLY0-NEXT:    [[CONV395:%.*]] = zext i8 [[TMP165]] to i32
28593 // SIMD-ONLY0-NEXT:    [[TMP166:%.*]] = load i8, ptr [[UCX]], align 1
28594 // SIMD-ONLY0-NEXT:    [[CONV396:%.*]] = zext i8 [[TMP166]] to i32
28595 // SIMD-ONLY0-NEXT:    [[CMP397:%.*]] = icmp eq i32 [[CONV395]], [[CONV396]]
28596 // SIMD-ONLY0-NEXT:    br i1 [[CMP397]], label [[IF_THEN399:%.*]], label [[IF_END400:%.*]]
28597 // SIMD-ONLY0:       if.then399:
28598 // SIMD-ONLY0-NEXT:    [[TMP167:%.*]] = load i8, ptr [[UCD]], align 1
28599 // SIMD-ONLY0-NEXT:    store i8 [[TMP167]], ptr [[UCX]], align 1
28600 // SIMD-ONLY0-NEXT:    br label [[IF_END400]]
28601 // SIMD-ONLY0:       if.end400:
28602 // SIMD-ONLY0-NEXT:    [[TMP168:%.*]] = load i8, ptr [[CX]], align 1
28603 // SIMD-ONLY0-NEXT:    [[CONV401:%.*]] = sext i8 [[TMP168]] to i32
28604 // SIMD-ONLY0-NEXT:    [[TMP169:%.*]] = load i8, ptr [[CE]], align 1
28605 // SIMD-ONLY0-NEXT:    [[CONV402:%.*]] = sext i8 [[TMP169]] to i32
28606 // SIMD-ONLY0-NEXT:    [[CMP403:%.*]] = icmp sgt i32 [[CONV401]], [[CONV402]]
28607 // SIMD-ONLY0-NEXT:    br i1 [[CMP403]], label [[COND_TRUE405:%.*]], label [[COND_FALSE407:%.*]]
28608 // SIMD-ONLY0:       cond.true405:
28609 // SIMD-ONLY0-NEXT:    [[TMP170:%.*]] = load i8, ptr [[CE]], align 1
28610 // SIMD-ONLY0-NEXT:    [[CONV406:%.*]] = sext i8 [[TMP170]] to i32
28611 // SIMD-ONLY0-NEXT:    br label [[COND_END409:%.*]]
28612 // SIMD-ONLY0:       cond.false407:
28613 // SIMD-ONLY0-NEXT:    [[TMP171:%.*]] = load i8, ptr [[CX]], align 1
28614 // SIMD-ONLY0-NEXT:    [[CONV408:%.*]] = sext i8 [[TMP171]] to i32
28615 // SIMD-ONLY0-NEXT:    br label [[COND_END409]]
28616 // SIMD-ONLY0:       cond.end409:
28617 // SIMD-ONLY0-NEXT:    [[COND410:%.*]] = phi i32 [ [[CONV406]], [[COND_TRUE405]] ], [ [[CONV408]], [[COND_FALSE407]] ]
28618 // SIMD-ONLY0-NEXT:    [[CONV411:%.*]] = trunc i32 [[COND410]] to i8
28619 // SIMD-ONLY0-NEXT:    store i8 [[CONV411]], ptr [[CX]], align 1
28620 // SIMD-ONLY0-NEXT:    [[TMP172:%.*]] = load i8, ptr [[CX]], align 1
28621 // SIMD-ONLY0-NEXT:    [[CONV412:%.*]] = sext i8 [[TMP172]] to i32
28622 // SIMD-ONLY0-NEXT:    [[TMP173:%.*]] = load i8, ptr [[CE]], align 1
28623 // SIMD-ONLY0-NEXT:    [[CONV413:%.*]] = sext i8 [[TMP173]] to i32
28624 // SIMD-ONLY0-NEXT:    [[CMP414:%.*]] = icmp slt i32 [[CONV412]], [[CONV413]]
28625 // SIMD-ONLY0-NEXT:    br i1 [[CMP414]], label [[COND_TRUE416:%.*]], label [[COND_FALSE418:%.*]]
28626 // SIMD-ONLY0:       cond.true416:
28627 // SIMD-ONLY0-NEXT:    [[TMP174:%.*]] = load i8, ptr [[CE]], align 1
28628 // SIMD-ONLY0-NEXT:    [[CONV417:%.*]] = sext i8 [[TMP174]] to i32
28629 // SIMD-ONLY0-NEXT:    br label [[COND_END420:%.*]]
28630 // SIMD-ONLY0:       cond.false418:
28631 // SIMD-ONLY0-NEXT:    [[TMP175:%.*]] = load i8, ptr [[CX]], align 1
28632 // SIMD-ONLY0-NEXT:    [[CONV419:%.*]] = sext i8 [[TMP175]] to i32
28633 // SIMD-ONLY0-NEXT:    br label [[COND_END420]]
28634 // SIMD-ONLY0:       cond.end420:
28635 // SIMD-ONLY0-NEXT:    [[COND421:%.*]] = phi i32 [ [[CONV417]], [[COND_TRUE416]] ], [ [[CONV419]], [[COND_FALSE418]] ]
28636 // SIMD-ONLY0-NEXT:    [[CONV422:%.*]] = trunc i32 [[COND421]] to i8
28637 // SIMD-ONLY0-NEXT:    store i8 [[CONV422]], ptr [[CX]], align 1
28638 // SIMD-ONLY0-NEXT:    [[TMP176:%.*]] = load i8, ptr [[CE]], align 1
28639 // SIMD-ONLY0-NEXT:    [[CONV423:%.*]] = sext i8 [[TMP176]] to i32
28640 // SIMD-ONLY0-NEXT:    [[TMP177:%.*]] = load i8, ptr [[CX]], align 1
28641 // SIMD-ONLY0-NEXT:    [[CONV424:%.*]] = sext i8 [[TMP177]] to i32
28642 // SIMD-ONLY0-NEXT:    [[CMP425:%.*]] = icmp sgt i32 [[CONV423]], [[CONV424]]
28643 // SIMD-ONLY0-NEXT:    br i1 [[CMP425]], label [[COND_TRUE427:%.*]], label [[COND_FALSE429:%.*]]
28644 // SIMD-ONLY0:       cond.true427:
28645 // SIMD-ONLY0-NEXT:    [[TMP178:%.*]] = load i8, ptr [[CE]], align 1
28646 // SIMD-ONLY0-NEXT:    [[CONV428:%.*]] = sext i8 [[TMP178]] to i32
28647 // SIMD-ONLY0-NEXT:    br label [[COND_END431:%.*]]
28648 // SIMD-ONLY0:       cond.false429:
28649 // SIMD-ONLY0-NEXT:    [[TMP179:%.*]] = load i8, ptr [[CX]], align 1
28650 // SIMD-ONLY0-NEXT:    [[CONV430:%.*]] = sext i8 [[TMP179]] to i32
28651 // SIMD-ONLY0-NEXT:    br label [[COND_END431]]
28652 // SIMD-ONLY0:       cond.end431:
28653 // SIMD-ONLY0-NEXT:    [[COND432:%.*]] = phi i32 [ [[CONV428]], [[COND_TRUE427]] ], [ [[CONV430]], [[COND_FALSE429]] ]
28654 // SIMD-ONLY0-NEXT:    [[CONV433:%.*]] = trunc i32 [[COND432]] to i8
28655 // SIMD-ONLY0-NEXT:    store i8 [[CONV433]], ptr [[CX]], align 1
28656 // SIMD-ONLY0-NEXT:    [[TMP180:%.*]] = load i8, ptr [[CE]], align 1
28657 // SIMD-ONLY0-NEXT:    [[CONV434:%.*]] = sext i8 [[TMP180]] to i32
28658 // SIMD-ONLY0-NEXT:    [[TMP181:%.*]] = load i8, ptr [[CX]], align 1
28659 // SIMD-ONLY0-NEXT:    [[CONV435:%.*]] = sext i8 [[TMP181]] to i32
28660 // SIMD-ONLY0-NEXT:    [[CMP436:%.*]] = icmp slt i32 [[CONV434]], [[CONV435]]
28661 // SIMD-ONLY0-NEXT:    br i1 [[CMP436]], label [[COND_TRUE438:%.*]], label [[COND_FALSE440:%.*]]
28662 // SIMD-ONLY0:       cond.true438:
28663 // SIMD-ONLY0-NEXT:    [[TMP182:%.*]] = load i8, ptr [[CE]], align 1
28664 // SIMD-ONLY0-NEXT:    [[CONV439:%.*]] = sext i8 [[TMP182]] to i32
28665 // SIMD-ONLY0-NEXT:    br label [[COND_END442:%.*]]
28666 // SIMD-ONLY0:       cond.false440:
28667 // SIMD-ONLY0-NEXT:    [[TMP183:%.*]] = load i8, ptr [[CX]], align 1
28668 // SIMD-ONLY0-NEXT:    [[CONV441:%.*]] = sext i8 [[TMP183]] to i32
28669 // SIMD-ONLY0-NEXT:    br label [[COND_END442]]
28670 // SIMD-ONLY0:       cond.end442:
28671 // SIMD-ONLY0-NEXT:    [[COND443:%.*]] = phi i32 [ [[CONV439]], [[COND_TRUE438]] ], [ [[CONV441]], [[COND_FALSE440]] ]
28672 // SIMD-ONLY0-NEXT:    [[CONV444:%.*]] = trunc i32 [[COND443]] to i8
28673 // SIMD-ONLY0-NEXT:    store i8 [[CONV444]], ptr [[CX]], align 1
28674 // SIMD-ONLY0-NEXT:    [[TMP184:%.*]] = load i8, ptr [[CX]], align 1
28675 // SIMD-ONLY0-NEXT:    [[CONV445:%.*]] = sext i8 [[TMP184]] to i32
28676 // SIMD-ONLY0-NEXT:    [[TMP185:%.*]] = load i8, ptr [[CE]], align 1
28677 // SIMD-ONLY0-NEXT:    [[CONV446:%.*]] = sext i8 [[TMP185]] to i32
28678 // SIMD-ONLY0-NEXT:    [[CMP447:%.*]] = icmp sgt i32 [[CONV445]], [[CONV446]]
28679 // SIMD-ONLY0-NEXT:    br i1 [[CMP447]], label [[IF_THEN449:%.*]], label [[IF_END450:%.*]]
28680 // SIMD-ONLY0:       if.then449:
28681 // SIMD-ONLY0-NEXT:    [[TMP186:%.*]] = load i8, ptr [[CE]], align 1
28682 // SIMD-ONLY0-NEXT:    store i8 [[TMP186]], ptr [[CX]], align 1
28683 // SIMD-ONLY0-NEXT:    br label [[IF_END450]]
28684 // SIMD-ONLY0:       if.end450:
28685 // SIMD-ONLY0-NEXT:    [[TMP187:%.*]] = load i8, ptr [[CX]], align 1
28686 // SIMD-ONLY0-NEXT:    [[CONV451:%.*]] = sext i8 [[TMP187]] to i32
28687 // SIMD-ONLY0-NEXT:    [[TMP188:%.*]] = load i8, ptr [[CE]], align 1
28688 // SIMD-ONLY0-NEXT:    [[CONV452:%.*]] = sext i8 [[TMP188]] to i32
28689 // SIMD-ONLY0-NEXT:    [[CMP453:%.*]] = icmp slt i32 [[CONV451]], [[CONV452]]
28690 // SIMD-ONLY0-NEXT:    br i1 [[CMP453]], label [[IF_THEN455:%.*]], label [[IF_END456:%.*]]
28691 // SIMD-ONLY0:       if.then455:
28692 // SIMD-ONLY0-NEXT:    [[TMP189:%.*]] = load i8, ptr [[CE]], align 1
28693 // SIMD-ONLY0-NEXT:    store i8 [[TMP189]], ptr [[CX]], align 1
28694 // SIMD-ONLY0-NEXT:    br label [[IF_END456]]
28695 // SIMD-ONLY0:       if.end456:
28696 // SIMD-ONLY0-NEXT:    [[TMP190:%.*]] = load i8, ptr [[CE]], align 1
28697 // SIMD-ONLY0-NEXT:    [[CONV457:%.*]] = sext i8 [[TMP190]] to i32
28698 // SIMD-ONLY0-NEXT:    [[TMP191:%.*]] = load i8, ptr [[CX]], align 1
28699 // SIMD-ONLY0-NEXT:    [[CONV458:%.*]] = sext i8 [[TMP191]] to i32
28700 // SIMD-ONLY0-NEXT:    [[CMP459:%.*]] = icmp sgt i32 [[CONV457]], [[CONV458]]
28701 // SIMD-ONLY0-NEXT:    br i1 [[CMP459]], label [[IF_THEN461:%.*]], label [[IF_END462:%.*]]
28702 // SIMD-ONLY0:       if.then461:
28703 // SIMD-ONLY0-NEXT:    [[TMP192:%.*]] = load i8, ptr [[CE]], align 1
28704 // SIMD-ONLY0-NEXT:    store i8 [[TMP192]], ptr [[CX]], align 1
28705 // SIMD-ONLY0-NEXT:    br label [[IF_END462]]
28706 // SIMD-ONLY0:       if.end462:
28707 // SIMD-ONLY0-NEXT:    [[TMP193:%.*]] = load i8, ptr [[CE]], align 1
28708 // SIMD-ONLY0-NEXT:    [[CONV463:%.*]] = sext i8 [[TMP193]] to i32
28709 // SIMD-ONLY0-NEXT:    [[TMP194:%.*]] = load i8, ptr [[CX]], align 1
28710 // SIMD-ONLY0-NEXT:    [[CONV464:%.*]] = sext i8 [[TMP194]] to i32
28711 // SIMD-ONLY0-NEXT:    [[CMP465:%.*]] = icmp slt i32 [[CONV463]], [[CONV464]]
28712 // SIMD-ONLY0-NEXT:    br i1 [[CMP465]], label [[IF_THEN467:%.*]], label [[IF_END468:%.*]]
28713 // SIMD-ONLY0:       if.then467:
28714 // SIMD-ONLY0-NEXT:    [[TMP195:%.*]] = load i8, ptr [[CE]], align 1
28715 // SIMD-ONLY0-NEXT:    store i8 [[TMP195]], ptr [[CX]], align 1
28716 // SIMD-ONLY0-NEXT:    br label [[IF_END468]]
28717 // SIMD-ONLY0:       if.end468:
28718 // SIMD-ONLY0-NEXT:    [[TMP196:%.*]] = load i8, ptr [[CX]], align 1
28719 // SIMD-ONLY0-NEXT:    [[CONV469:%.*]] = sext i8 [[TMP196]] to i32
28720 // SIMD-ONLY0-NEXT:    [[TMP197:%.*]] = load i8, ptr [[CE]], align 1
28721 // SIMD-ONLY0-NEXT:    [[CONV470:%.*]] = sext i8 [[TMP197]] to i32
28722 // SIMD-ONLY0-NEXT:    [[CMP471:%.*]] = icmp eq i32 [[CONV469]], [[CONV470]]
28723 // SIMD-ONLY0-NEXT:    br i1 [[CMP471]], label [[COND_TRUE473:%.*]], label [[COND_FALSE475:%.*]]
28724 // SIMD-ONLY0:       cond.true473:
28725 // SIMD-ONLY0-NEXT:    [[TMP198:%.*]] = load i8, ptr [[CD]], align 1
28726 // SIMD-ONLY0-NEXT:    [[CONV474:%.*]] = sext i8 [[TMP198]] to i32
28727 // SIMD-ONLY0-NEXT:    br label [[COND_END477:%.*]]
28728 // SIMD-ONLY0:       cond.false475:
28729 // SIMD-ONLY0-NEXT:    [[TMP199:%.*]] = load i8, ptr [[CX]], align 1
28730 // SIMD-ONLY0-NEXT:    [[CONV476:%.*]] = sext i8 [[TMP199]] to i32
28731 // SIMD-ONLY0-NEXT:    br label [[COND_END477]]
28732 // SIMD-ONLY0:       cond.end477:
28733 // SIMD-ONLY0-NEXT:    [[COND478:%.*]] = phi i32 [ [[CONV474]], [[COND_TRUE473]] ], [ [[CONV476]], [[COND_FALSE475]] ]
28734 // SIMD-ONLY0-NEXT:    [[CONV479:%.*]] = trunc i32 [[COND478]] to i8
28735 // SIMD-ONLY0-NEXT:    store i8 [[CONV479]], ptr [[CX]], align 1
28736 // SIMD-ONLY0-NEXT:    [[TMP200:%.*]] = load i8, ptr [[CE]], align 1
28737 // SIMD-ONLY0-NEXT:    [[CONV480:%.*]] = sext i8 [[TMP200]] to i32
28738 // SIMD-ONLY0-NEXT:    [[TMP201:%.*]] = load i8, ptr [[CX]], align 1
28739 // SIMD-ONLY0-NEXT:    [[CONV481:%.*]] = sext i8 [[TMP201]] to i32
28740 // SIMD-ONLY0-NEXT:    [[CMP482:%.*]] = icmp eq i32 [[CONV480]], [[CONV481]]
28741 // SIMD-ONLY0-NEXT:    br i1 [[CMP482]], label [[COND_TRUE484:%.*]], label [[COND_FALSE486:%.*]]
28742 // SIMD-ONLY0:       cond.true484:
28743 // SIMD-ONLY0-NEXT:    [[TMP202:%.*]] = load i8, ptr [[CD]], align 1
28744 // SIMD-ONLY0-NEXT:    [[CONV485:%.*]] = sext i8 [[TMP202]] to i32
28745 // SIMD-ONLY0-NEXT:    br label [[COND_END488:%.*]]
28746 // SIMD-ONLY0:       cond.false486:
28747 // SIMD-ONLY0-NEXT:    [[TMP203:%.*]] = load i8, ptr [[CX]], align 1
28748 // SIMD-ONLY0-NEXT:    [[CONV487:%.*]] = sext i8 [[TMP203]] to i32
28749 // SIMD-ONLY0-NEXT:    br label [[COND_END488]]
28750 // SIMD-ONLY0:       cond.end488:
28751 // SIMD-ONLY0-NEXT:    [[COND489:%.*]] = phi i32 [ [[CONV485]], [[COND_TRUE484]] ], [ [[CONV487]], [[COND_FALSE486]] ]
28752 // SIMD-ONLY0-NEXT:    [[CONV490:%.*]] = trunc i32 [[COND489]] to i8
28753 // SIMD-ONLY0-NEXT:    store i8 [[CONV490]], ptr [[CX]], align 1
28754 // SIMD-ONLY0-NEXT:    [[TMP204:%.*]] = load i8, ptr [[CX]], align 1
28755 // SIMD-ONLY0-NEXT:    [[CONV491:%.*]] = sext i8 [[TMP204]] to i32
28756 // SIMD-ONLY0-NEXT:    [[TMP205:%.*]] = load i8, ptr [[CE]], align 1
28757 // SIMD-ONLY0-NEXT:    [[CONV492:%.*]] = sext i8 [[TMP205]] to i32
28758 // SIMD-ONLY0-NEXT:    [[CMP493:%.*]] = icmp eq i32 [[CONV491]], [[CONV492]]
28759 // SIMD-ONLY0-NEXT:    br i1 [[CMP493]], label [[IF_THEN495:%.*]], label [[IF_END496:%.*]]
28760 // SIMD-ONLY0:       if.then495:
28761 // SIMD-ONLY0-NEXT:    [[TMP206:%.*]] = load i8, ptr [[CD]], align 1
28762 // SIMD-ONLY0-NEXT:    store i8 [[TMP206]], ptr [[CX]], align 1
28763 // SIMD-ONLY0-NEXT:    br label [[IF_END496]]
28764 // SIMD-ONLY0:       if.end496:
28765 // SIMD-ONLY0-NEXT:    [[TMP207:%.*]] = load i8, ptr [[CE]], align 1
28766 // SIMD-ONLY0-NEXT:    [[CONV497:%.*]] = sext i8 [[TMP207]] to i32
28767 // SIMD-ONLY0-NEXT:    [[TMP208:%.*]] = load i8, ptr [[CX]], align 1
28768 // SIMD-ONLY0-NEXT:    [[CONV498:%.*]] = sext i8 [[TMP208]] to i32
28769 // SIMD-ONLY0-NEXT:    [[CMP499:%.*]] = icmp eq i32 [[CONV497]], [[CONV498]]
28770 // SIMD-ONLY0-NEXT:    br i1 [[CMP499]], label [[IF_THEN501:%.*]], label [[IF_END502:%.*]]
28771 // SIMD-ONLY0:       if.then501:
28772 // SIMD-ONLY0-NEXT:    [[TMP209:%.*]] = load i8, ptr [[CD]], align 1
28773 // SIMD-ONLY0-NEXT:    store i8 [[TMP209]], ptr [[CX]], align 1
28774 // SIMD-ONLY0-NEXT:    br label [[IF_END502]]
28775 // SIMD-ONLY0:       if.end502:
28776 // SIMD-ONLY0-NEXT:    [[TMP210:%.*]] = load i8, ptr [[UCX]], align 1
28777 // SIMD-ONLY0-NEXT:    [[CONV503:%.*]] = zext i8 [[TMP210]] to i32
28778 // SIMD-ONLY0-NEXT:    [[TMP211:%.*]] = load i8, ptr [[UCE]], align 1
28779 // SIMD-ONLY0-NEXT:    [[CONV504:%.*]] = zext i8 [[TMP211]] to i32
28780 // SIMD-ONLY0-NEXT:    [[CMP505:%.*]] = icmp sgt i32 [[CONV503]], [[CONV504]]
28781 // SIMD-ONLY0-NEXT:    br i1 [[CMP505]], label [[COND_TRUE507:%.*]], label [[COND_FALSE509:%.*]]
28782 // SIMD-ONLY0:       cond.true507:
28783 // SIMD-ONLY0-NEXT:    [[TMP212:%.*]] = load i8, ptr [[UCE]], align 1
28784 // SIMD-ONLY0-NEXT:    [[CONV508:%.*]] = zext i8 [[TMP212]] to i32
28785 // SIMD-ONLY0-NEXT:    br label [[COND_END511:%.*]]
28786 // SIMD-ONLY0:       cond.false509:
28787 // SIMD-ONLY0-NEXT:    [[TMP213:%.*]] = load i8, ptr [[UCX]], align 1
28788 // SIMD-ONLY0-NEXT:    [[CONV510:%.*]] = zext i8 [[TMP213]] to i32
28789 // SIMD-ONLY0-NEXT:    br label [[COND_END511]]
28790 // SIMD-ONLY0:       cond.end511:
28791 // SIMD-ONLY0-NEXT:    [[COND512:%.*]] = phi i32 [ [[CONV508]], [[COND_TRUE507]] ], [ [[CONV510]], [[COND_FALSE509]] ]
28792 // SIMD-ONLY0-NEXT:    [[CONV513:%.*]] = trunc i32 [[COND512]] to i8
28793 // SIMD-ONLY0-NEXT:    store i8 [[CONV513]], ptr [[UCX]], align 1
28794 // SIMD-ONLY0-NEXT:    [[TMP214:%.*]] = load i8, ptr [[UCX]], align 1
28795 // SIMD-ONLY0-NEXT:    [[CONV514:%.*]] = zext i8 [[TMP214]] to i32
28796 // SIMD-ONLY0-NEXT:    [[TMP215:%.*]] = load i8, ptr [[UCE]], align 1
28797 // SIMD-ONLY0-NEXT:    [[CONV515:%.*]] = zext i8 [[TMP215]] to i32
28798 // SIMD-ONLY0-NEXT:    [[CMP516:%.*]] = icmp slt i32 [[CONV514]], [[CONV515]]
28799 // SIMD-ONLY0-NEXT:    br i1 [[CMP516]], label [[COND_TRUE518:%.*]], label [[COND_FALSE520:%.*]]
28800 // SIMD-ONLY0:       cond.true518:
28801 // SIMD-ONLY0-NEXT:    [[TMP216:%.*]] = load i8, ptr [[UCE]], align 1
28802 // SIMD-ONLY0-NEXT:    [[CONV519:%.*]] = zext i8 [[TMP216]] to i32
28803 // SIMD-ONLY0-NEXT:    br label [[COND_END522:%.*]]
28804 // SIMD-ONLY0:       cond.false520:
28805 // SIMD-ONLY0-NEXT:    [[TMP217:%.*]] = load i8, ptr [[UCX]], align 1
28806 // SIMD-ONLY0-NEXT:    [[CONV521:%.*]] = zext i8 [[TMP217]] to i32
28807 // SIMD-ONLY0-NEXT:    br label [[COND_END522]]
28808 // SIMD-ONLY0:       cond.end522:
28809 // SIMD-ONLY0-NEXT:    [[COND523:%.*]] = phi i32 [ [[CONV519]], [[COND_TRUE518]] ], [ [[CONV521]], [[COND_FALSE520]] ]
28810 // SIMD-ONLY0-NEXT:    [[CONV524:%.*]] = trunc i32 [[COND523]] to i8
28811 // SIMD-ONLY0-NEXT:    store i8 [[CONV524]], ptr [[UCX]], align 1
28812 // SIMD-ONLY0-NEXT:    [[TMP218:%.*]] = load i8, ptr [[UCE]], align 1
28813 // SIMD-ONLY0-NEXT:    [[CONV525:%.*]] = zext i8 [[TMP218]] to i32
28814 // SIMD-ONLY0-NEXT:    [[TMP219:%.*]] = load i8, ptr [[UCX]], align 1
28815 // SIMD-ONLY0-NEXT:    [[CONV526:%.*]] = zext i8 [[TMP219]] to i32
28816 // SIMD-ONLY0-NEXT:    [[CMP527:%.*]] = icmp sgt i32 [[CONV525]], [[CONV526]]
28817 // SIMD-ONLY0-NEXT:    br i1 [[CMP527]], label [[COND_TRUE529:%.*]], label [[COND_FALSE531:%.*]]
28818 // SIMD-ONLY0:       cond.true529:
28819 // SIMD-ONLY0-NEXT:    [[TMP220:%.*]] = load i8, ptr [[UCE]], align 1
28820 // SIMD-ONLY0-NEXT:    [[CONV530:%.*]] = zext i8 [[TMP220]] to i32
28821 // SIMD-ONLY0-NEXT:    br label [[COND_END533:%.*]]
28822 // SIMD-ONLY0:       cond.false531:
28823 // SIMD-ONLY0-NEXT:    [[TMP221:%.*]] = load i8, ptr [[UCX]], align 1
28824 // SIMD-ONLY0-NEXT:    [[CONV532:%.*]] = zext i8 [[TMP221]] to i32
28825 // SIMD-ONLY0-NEXT:    br label [[COND_END533]]
28826 // SIMD-ONLY0:       cond.end533:
28827 // SIMD-ONLY0-NEXT:    [[COND534:%.*]] = phi i32 [ [[CONV530]], [[COND_TRUE529]] ], [ [[CONV532]], [[COND_FALSE531]] ]
28828 // SIMD-ONLY0-NEXT:    [[CONV535:%.*]] = trunc i32 [[COND534]] to i8
28829 // SIMD-ONLY0-NEXT:    store i8 [[CONV535]], ptr [[UCX]], align 1
28830 // SIMD-ONLY0-NEXT:    [[TMP222:%.*]] = load i8, ptr [[UCE]], align 1
28831 // SIMD-ONLY0-NEXT:    [[CONV536:%.*]] = zext i8 [[TMP222]] to i32
28832 // SIMD-ONLY0-NEXT:    [[TMP223:%.*]] = load i8, ptr [[UCX]], align 1
28833 // SIMD-ONLY0-NEXT:    [[CONV537:%.*]] = zext i8 [[TMP223]] to i32
28834 // SIMD-ONLY0-NEXT:    [[CMP538:%.*]] = icmp slt i32 [[CONV536]], [[CONV537]]
28835 // SIMD-ONLY0-NEXT:    br i1 [[CMP538]], label [[COND_TRUE540:%.*]], label [[COND_FALSE542:%.*]]
28836 // SIMD-ONLY0:       cond.true540:
28837 // SIMD-ONLY0-NEXT:    [[TMP224:%.*]] = load i8, ptr [[UCE]], align 1
28838 // SIMD-ONLY0-NEXT:    [[CONV541:%.*]] = zext i8 [[TMP224]] to i32
28839 // SIMD-ONLY0-NEXT:    br label [[COND_END544:%.*]]
28840 // SIMD-ONLY0:       cond.false542:
28841 // SIMD-ONLY0-NEXT:    [[TMP225:%.*]] = load i8, ptr [[UCX]], align 1
28842 // SIMD-ONLY0-NEXT:    [[CONV543:%.*]] = zext i8 [[TMP225]] to i32
28843 // SIMD-ONLY0-NEXT:    br label [[COND_END544]]
28844 // SIMD-ONLY0:       cond.end544:
28845 // SIMD-ONLY0-NEXT:    [[COND545:%.*]] = phi i32 [ [[CONV541]], [[COND_TRUE540]] ], [ [[CONV543]], [[COND_FALSE542]] ]
28846 // SIMD-ONLY0-NEXT:    [[CONV546:%.*]] = trunc i32 [[COND545]] to i8
28847 // SIMD-ONLY0-NEXT:    store i8 [[CONV546]], ptr [[UCX]], align 1
28848 // SIMD-ONLY0-NEXT:    [[TMP226:%.*]] = load i8, ptr [[UCX]], align 1
28849 // SIMD-ONLY0-NEXT:    [[CONV547:%.*]] = zext i8 [[TMP226]] to i32
28850 // SIMD-ONLY0-NEXT:    [[TMP227:%.*]] = load i8, ptr [[UCE]], align 1
28851 // SIMD-ONLY0-NEXT:    [[CONV548:%.*]] = zext i8 [[TMP227]] to i32
28852 // SIMD-ONLY0-NEXT:    [[CMP549:%.*]] = icmp sgt i32 [[CONV547]], [[CONV548]]
28853 // SIMD-ONLY0-NEXT:    br i1 [[CMP549]], label [[IF_THEN551:%.*]], label [[IF_END552:%.*]]
28854 // SIMD-ONLY0:       if.then551:
28855 // SIMD-ONLY0-NEXT:    [[TMP228:%.*]] = load i8, ptr [[UCE]], align 1
28856 // SIMD-ONLY0-NEXT:    store i8 [[TMP228]], ptr [[UCX]], align 1
28857 // SIMD-ONLY0-NEXT:    br label [[IF_END552]]
28858 // SIMD-ONLY0:       if.end552:
28859 // SIMD-ONLY0-NEXT:    [[TMP229:%.*]] = load i8, ptr [[UCX]], align 1
28860 // SIMD-ONLY0-NEXT:    [[CONV553:%.*]] = zext i8 [[TMP229]] to i32
28861 // SIMD-ONLY0-NEXT:    [[TMP230:%.*]] = load i8, ptr [[UCE]], align 1
28862 // SIMD-ONLY0-NEXT:    [[CONV554:%.*]] = zext i8 [[TMP230]] to i32
28863 // SIMD-ONLY0-NEXT:    [[CMP555:%.*]] = icmp slt i32 [[CONV553]], [[CONV554]]
28864 // SIMD-ONLY0-NEXT:    br i1 [[CMP555]], label [[IF_THEN557:%.*]], label [[IF_END558:%.*]]
28865 // SIMD-ONLY0:       if.then557:
28866 // SIMD-ONLY0-NEXT:    [[TMP231:%.*]] = load i8, ptr [[UCE]], align 1
28867 // SIMD-ONLY0-NEXT:    store i8 [[TMP231]], ptr [[UCX]], align 1
28868 // SIMD-ONLY0-NEXT:    br label [[IF_END558]]
28869 // SIMD-ONLY0:       if.end558:
28870 // SIMD-ONLY0-NEXT:    [[TMP232:%.*]] = load i8, ptr [[UCE]], align 1
28871 // SIMD-ONLY0-NEXT:    [[CONV559:%.*]] = zext i8 [[TMP232]] to i32
28872 // SIMD-ONLY0-NEXT:    [[TMP233:%.*]] = load i8, ptr [[UCX]], align 1
28873 // SIMD-ONLY0-NEXT:    [[CONV560:%.*]] = zext i8 [[TMP233]] to i32
28874 // SIMD-ONLY0-NEXT:    [[CMP561:%.*]] = icmp sgt i32 [[CONV559]], [[CONV560]]
28875 // SIMD-ONLY0-NEXT:    br i1 [[CMP561]], label [[IF_THEN563:%.*]], label [[IF_END564:%.*]]
28876 // SIMD-ONLY0:       if.then563:
28877 // SIMD-ONLY0-NEXT:    [[TMP234:%.*]] = load i8, ptr [[UCE]], align 1
28878 // SIMD-ONLY0-NEXT:    store i8 [[TMP234]], ptr [[UCX]], align 1
28879 // SIMD-ONLY0-NEXT:    br label [[IF_END564]]
28880 // SIMD-ONLY0:       if.end564:
28881 // SIMD-ONLY0-NEXT:    [[TMP235:%.*]] = load i8, ptr [[UCE]], align 1
28882 // SIMD-ONLY0-NEXT:    [[CONV565:%.*]] = zext i8 [[TMP235]] to i32
28883 // SIMD-ONLY0-NEXT:    [[TMP236:%.*]] = load i8, ptr [[UCX]], align 1
28884 // SIMD-ONLY0-NEXT:    [[CONV566:%.*]] = zext i8 [[TMP236]] to i32
28885 // SIMD-ONLY0-NEXT:    [[CMP567:%.*]] = icmp slt i32 [[CONV565]], [[CONV566]]
28886 // SIMD-ONLY0-NEXT:    br i1 [[CMP567]], label [[IF_THEN569:%.*]], label [[IF_END570:%.*]]
28887 // SIMD-ONLY0:       if.then569:
28888 // SIMD-ONLY0-NEXT:    [[TMP237:%.*]] = load i8, ptr [[UCE]], align 1
28889 // SIMD-ONLY0-NEXT:    store i8 [[TMP237]], ptr [[UCX]], align 1
28890 // SIMD-ONLY0-NEXT:    br label [[IF_END570]]
28891 // SIMD-ONLY0:       if.end570:
28892 // SIMD-ONLY0-NEXT:    [[TMP238:%.*]] = load i8, ptr [[UCX]], align 1
28893 // SIMD-ONLY0-NEXT:    [[CONV571:%.*]] = zext i8 [[TMP238]] to i32
28894 // SIMD-ONLY0-NEXT:    [[TMP239:%.*]] = load i8, ptr [[UCE]], align 1
28895 // SIMD-ONLY0-NEXT:    [[CONV572:%.*]] = zext i8 [[TMP239]] to i32
28896 // SIMD-ONLY0-NEXT:    [[CMP573:%.*]] = icmp eq i32 [[CONV571]], [[CONV572]]
28897 // SIMD-ONLY0-NEXT:    br i1 [[CMP573]], label [[COND_TRUE575:%.*]], label [[COND_FALSE577:%.*]]
28898 // SIMD-ONLY0:       cond.true575:
28899 // SIMD-ONLY0-NEXT:    [[TMP240:%.*]] = load i8, ptr [[UCD]], align 1
28900 // SIMD-ONLY0-NEXT:    [[CONV576:%.*]] = zext i8 [[TMP240]] to i32
28901 // SIMD-ONLY0-NEXT:    br label [[COND_END579:%.*]]
28902 // SIMD-ONLY0:       cond.false577:
28903 // SIMD-ONLY0-NEXT:    [[TMP241:%.*]] = load i8, ptr [[UCX]], align 1
28904 // SIMD-ONLY0-NEXT:    [[CONV578:%.*]] = zext i8 [[TMP241]] to i32
28905 // SIMD-ONLY0-NEXT:    br label [[COND_END579]]
28906 // SIMD-ONLY0:       cond.end579:
28907 // SIMD-ONLY0-NEXT:    [[COND580:%.*]] = phi i32 [ [[CONV576]], [[COND_TRUE575]] ], [ [[CONV578]], [[COND_FALSE577]] ]
28908 // SIMD-ONLY0-NEXT:    [[CONV581:%.*]] = trunc i32 [[COND580]] to i8
28909 // SIMD-ONLY0-NEXT:    store i8 [[CONV581]], ptr [[UCX]], align 1
28910 // SIMD-ONLY0-NEXT:    [[TMP242:%.*]] = load i8, ptr [[UCE]], align 1
28911 // SIMD-ONLY0-NEXT:    [[CONV582:%.*]] = zext i8 [[TMP242]] to i32
28912 // SIMD-ONLY0-NEXT:    [[TMP243:%.*]] = load i8, ptr [[UCX]], align 1
28913 // SIMD-ONLY0-NEXT:    [[CONV583:%.*]] = zext i8 [[TMP243]] to i32
28914 // SIMD-ONLY0-NEXT:    [[CMP584:%.*]] = icmp eq i32 [[CONV582]], [[CONV583]]
28915 // SIMD-ONLY0-NEXT:    br i1 [[CMP584]], label [[COND_TRUE586:%.*]], label [[COND_FALSE588:%.*]]
28916 // SIMD-ONLY0:       cond.true586:
28917 // SIMD-ONLY0-NEXT:    [[TMP244:%.*]] = load i8, ptr [[UCD]], align 1
28918 // SIMD-ONLY0-NEXT:    [[CONV587:%.*]] = zext i8 [[TMP244]] to i32
28919 // SIMD-ONLY0-NEXT:    br label [[COND_END590:%.*]]
28920 // SIMD-ONLY0:       cond.false588:
28921 // SIMD-ONLY0-NEXT:    [[TMP245:%.*]] = load i8, ptr [[UCX]], align 1
28922 // SIMD-ONLY0-NEXT:    [[CONV589:%.*]] = zext i8 [[TMP245]] to i32
28923 // SIMD-ONLY0-NEXT:    br label [[COND_END590]]
28924 // SIMD-ONLY0:       cond.end590:
28925 // SIMD-ONLY0-NEXT:    [[COND591:%.*]] = phi i32 [ [[CONV587]], [[COND_TRUE586]] ], [ [[CONV589]], [[COND_FALSE588]] ]
28926 // SIMD-ONLY0-NEXT:    [[CONV592:%.*]] = trunc i32 [[COND591]] to i8
28927 // SIMD-ONLY0-NEXT:    store i8 [[CONV592]], ptr [[UCX]], align 1
28928 // SIMD-ONLY0-NEXT:    [[TMP246:%.*]] = load i8, ptr [[UCX]], align 1
28929 // SIMD-ONLY0-NEXT:    [[CONV593:%.*]] = zext i8 [[TMP246]] to i32
28930 // SIMD-ONLY0-NEXT:    [[TMP247:%.*]] = load i8, ptr [[UCE]], align 1
28931 // SIMD-ONLY0-NEXT:    [[CONV594:%.*]] = zext i8 [[TMP247]] to i32
28932 // SIMD-ONLY0-NEXT:    [[CMP595:%.*]] = icmp eq i32 [[CONV593]], [[CONV594]]
28933 // SIMD-ONLY0-NEXT:    br i1 [[CMP595]], label [[IF_THEN597:%.*]], label [[IF_END598:%.*]]
28934 // SIMD-ONLY0:       if.then597:
28935 // SIMD-ONLY0-NEXT:    [[TMP248:%.*]] = load i8, ptr [[UCD]], align 1
28936 // SIMD-ONLY0-NEXT:    store i8 [[TMP248]], ptr [[UCX]], align 1
28937 // SIMD-ONLY0-NEXT:    br label [[IF_END598]]
28938 // SIMD-ONLY0:       if.end598:
28939 // SIMD-ONLY0-NEXT:    [[TMP249:%.*]] = load i8, ptr [[UCE]], align 1
28940 // SIMD-ONLY0-NEXT:    [[CONV599:%.*]] = zext i8 [[TMP249]] to i32
28941 // SIMD-ONLY0-NEXT:    [[TMP250:%.*]] = load i8, ptr [[UCX]], align 1
28942 // SIMD-ONLY0-NEXT:    [[CONV600:%.*]] = zext i8 [[TMP250]] to i32
28943 // SIMD-ONLY0-NEXT:    [[CMP601:%.*]] = icmp eq i32 [[CONV599]], [[CONV600]]
28944 // SIMD-ONLY0-NEXT:    br i1 [[CMP601]], label [[IF_THEN603:%.*]], label [[IF_END604:%.*]]
28945 // SIMD-ONLY0:       if.then603:
28946 // SIMD-ONLY0-NEXT:    [[TMP251:%.*]] = load i8, ptr [[UCD]], align 1
28947 // SIMD-ONLY0-NEXT:    store i8 [[TMP251]], ptr [[UCX]], align 1
28948 // SIMD-ONLY0-NEXT:    br label [[IF_END604]]
28949 // SIMD-ONLY0:       if.end604:
28950 // SIMD-ONLY0-NEXT:    [[TMP252:%.*]] = load i8, ptr [[CX]], align 1
28951 // SIMD-ONLY0-NEXT:    [[CONV605:%.*]] = sext i8 [[TMP252]] to i32
28952 // SIMD-ONLY0-NEXT:    [[TMP253:%.*]] = load i8, ptr [[CE]], align 1
28953 // SIMD-ONLY0-NEXT:    [[CONV606:%.*]] = sext i8 [[TMP253]] to i32
28954 // SIMD-ONLY0-NEXT:    [[CMP607:%.*]] = icmp sgt i32 [[CONV605]], [[CONV606]]
28955 // SIMD-ONLY0-NEXT:    br i1 [[CMP607]], label [[COND_TRUE609:%.*]], label [[COND_FALSE611:%.*]]
28956 // SIMD-ONLY0:       cond.true609:
28957 // SIMD-ONLY0-NEXT:    [[TMP254:%.*]] = load i8, ptr [[CE]], align 1
28958 // SIMD-ONLY0-NEXT:    [[CONV610:%.*]] = sext i8 [[TMP254]] to i32
28959 // SIMD-ONLY0-NEXT:    br label [[COND_END613:%.*]]
28960 // SIMD-ONLY0:       cond.false611:
28961 // SIMD-ONLY0-NEXT:    [[TMP255:%.*]] = load i8, ptr [[CX]], align 1
28962 // SIMD-ONLY0-NEXT:    [[CONV612:%.*]] = sext i8 [[TMP255]] to i32
28963 // SIMD-ONLY0-NEXT:    br label [[COND_END613]]
28964 // SIMD-ONLY0:       cond.end613:
28965 // SIMD-ONLY0-NEXT:    [[COND614:%.*]] = phi i32 [ [[CONV610]], [[COND_TRUE609]] ], [ [[CONV612]], [[COND_FALSE611]] ]
28966 // SIMD-ONLY0-NEXT:    [[CONV615:%.*]] = trunc i32 [[COND614]] to i8
28967 // SIMD-ONLY0-NEXT:    store i8 [[CONV615]], ptr [[CX]], align 1
28968 // SIMD-ONLY0-NEXT:    [[TMP256:%.*]] = load i8, ptr [[CX]], align 1
28969 // SIMD-ONLY0-NEXT:    [[CONV616:%.*]] = sext i8 [[TMP256]] to i32
28970 // SIMD-ONLY0-NEXT:    [[TMP257:%.*]] = load i8, ptr [[CE]], align 1
28971 // SIMD-ONLY0-NEXT:    [[CONV617:%.*]] = sext i8 [[TMP257]] to i32
28972 // SIMD-ONLY0-NEXT:    [[CMP618:%.*]] = icmp slt i32 [[CONV616]], [[CONV617]]
28973 // SIMD-ONLY0-NEXT:    br i1 [[CMP618]], label [[COND_TRUE620:%.*]], label [[COND_FALSE622:%.*]]
28974 // SIMD-ONLY0:       cond.true620:
28975 // SIMD-ONLY0-NEXT:    [[TMP258:%.*]] = load i8, ptr [[CE]], align 1
28976 // SIMD-ONLY0-NEXT:    [[CONV621:%.*]] = sext i8 [[TMP258]] to i32
28977 // SIMD-ONLY0-NEXT:    br label [[COND_END624:%.*]]
28978 // SIMD-ONLY0:       cond.false622:
28979 // SIMD-ONLY0-NEXT:    [[TMP259:%.*]] = load i8, ptr [[CX]], align 1
28980 // SIMD-ONLY0-NEXT:    [[CONV623:%.*]] = sext i8 [[TMP259]] to i32
28981 // SIMD-ONLY0-NEXT:    br label [[COND_END624]]
28982 // SIMD-ONLY0:       cond.end624:
28983 // SIMD-ONLY0-NEXT:    [[COND625:%.*]] = phi i32 [ [[CONV621]], [[COND_TRUE620]] ], [ [[CONV623]], [[COND_FALSE622]] ]
28984 // SIMD-ONLY0-NEXT:    [[CONV626:%.*]] = trunc i32 [[COND625]] to i8
28985 // SIMD-ONLY0-NEXT:    store i8 [[CONV626]], ptr [[CX]], align 1
28986 // SIMD-ONLY0-NEXT:    [[TMP260:%.*]] = load i8, ptr [[CE]], align 1
28987 // SIMD-ONLY0-NEXT:    [[CONV627:%.*]] = sext i8 [[TMP260]] to i32
28988 // SIMD-ONLY0-NEXT:    [[TMP261:%.*]] = load i8, ptr [[CX]], align 1
28989 // SIMD-ONLY0-NEXT:    [[CONV628:%.*]] = sext i8 [[TMP261]] to i32
28990 // SIMD-ONLY0-NEXT:    [[CMP629:%.*]] = icmp sgt i32 [[CONV627]], [[CONV628]]
28991 // SIMD-ONLY0-NEXT:    br i1 [[CMP629]], label [[COND_TRUE631:%.*]], label [[COND_FALSE633:%.*]]
28992 // SIMD-ONLY0:       cond.true631:
28993 // SIMD-ONLY0-NEXT:    [[TMP262:%.*]] = load i8, ptr [[CE]], align 1
28994 // SIMD-ONLY0-NEXT:    [[CONV632:%.*]] = sext i8 [[TMP262]] to i32
28995 // SIMD-ONLY0-NEXT:    br label [[COND_END635:%.*]]
28996 // SIMD-ONLY0:       cond.false633:
28997 // SIMD-ONLY0-NEXT:    [[TMP263:%.*]] = load i8, ptr [[CX]], align 1
28998 // SIMD-ONLY0-NEXT:    [[CONV634:%.*]] = sext i8 [[TMP263]] to i32
28999 // SIMD-ONLY0-NEXT:    br label [[COND_END635]]
29000 // SIMD-ONLY0:       cond.end635:
29001 // SIMD-ONLY0-NEXT:    [[COND636:%.*]] = phi i32 [ [[CONV632]], [[COND_TRUE631]] ], [ [[CONV634]], [[COND_FALSE633]] ]
29002 // SIMD-ONLY0-NEXT:    [[CONV637:%.*]] = trunc i32 [[COND636]] to i8
29003 // SIMD-ONLY0-NEXT:    store i8 [[CONV637]], ptr [[CX]], align 1
29004 // SIMD-ONLY0-NEXT:    [[TMP264:%.*]] = load i8, ptr [[CE]], align 1
29005 // SIMD-ONLY0-NEXT:    [[CONV638:%.*]] = sext i8 [[TMP264]] to i32
29006 // SIMD-ONLY0-NEXT:    [[TMP265:%.*]] = load i8, ptr [[CX]], align 1
29007 // SIMD-ONLY0-NEXT:    [[CONV639:%.*]] = sext i8 [[TMP265]] to i32
29008 // SIMD-ONLY0-NEXT:    [[CMP640:%.*]] = icmp slt i32 [[CONV638]], [[CONV639]]
29009 // SIMD-ONLY0-NEXT:    br i1 [[CMP640]], label [[COND_TRUE642:%.*]], label [[COND_FALSE644:%.*]]
29010 // SIMD-ONLY0:       cond.true642:
29011 // SIMD-ONLY0-NEXT:    [[TMP266:%.*]] = load i8, ptr [[CE]], align 1
29012 // SIMD-ONLY0-NEXT:    [[CONV643:%.*]] = sext i8 [[TMP266]] to i32
29013 // SIMD-ONLY0-NEXT:    br label [[COND_END646:%.*]]
29014 // SIMD-ONLY0:       cond.false644:
29015 // SIMD-ONLY0-NEXT:    [[TMP267:%.*]] = load i8, ptr [[CX]], align 1
29016 // SIMD-ONLY0-NEXT:    [[CONV645:%.*]] = sext i8 [[TMP267]] to i32
29017 // SIMD-ONLY0-NEXT:    br label [[COND_END646]]
29018 // SIMD-ONLY0:       cond.end646:
29019 // SIMD-ONLY0-NEXT:    [[COND647:%.*]] = phi i32 [ [[CONV643]], [[COND_TRUE642]] ], [ [[CONV645]], [[COND_FALSE644]] ]
29020 // SIMD-ONLY0-NEXT:    [[CONV648:%.*]] = trunc i32 [[COND647]] to i8
29021 // SIMD-ONLY0-NEXT:    store i8 [[CONV648]], ptr [[CX]], align 1
29022 // SIMD-ONLY0-NEXT:    [[TMP268:%.*]] = load i8, ptr [[CX]], align 1
29023 // SIMD-ONLY0-NEXT:    [[CONV649:%.*]] = sext i8 [[TMP268]] to i32
29024 // SIMD-ONLY0-NEXT:    [[TMP269:%.*]] = load i8, ptr [[CE]], align 1
29025 // SIMD-ONLY0-NEXT:    [[CONV650:%.*]] = sext i8 [[TMP269]] to i32
29026 // SIMD-ONLY0-NEXT:    [[CMP651:%.*]] = icmp sgt i32 [[CONV649]], [[CONV650]]
29027 // SIMD-ONLY0-NEXT:    br i1 [[CMP651]], label [[IF_THEN653:%.*]], label [[IF_END654:%.*]]
29028 // SIMD-ONLY0:       if.then653:
29029 // SIMD-ONLY0-NEXT:    [[TMP270:%.*]] = load i8, ptr [[CE]], align 1
29030 // SIMD-ONLY0-NEXT:    store i8 [[TMP270]], ptr [[CX]], align 1
29031 // SIMD-ONLY0-NEXT:    br label [[IF_END654]]
29032 // SIMD-ONLY0:       if.end654:
29033 // SIMD-ONLY0-NEXT:    [[TMP271:%.*]] = load i8, ptr [[CX]], align 1
29034 // SIMD-ONLY0-NEXT:    [[CONV655:%.*]] = sext i8 [[TMP271]] to i32
29035 // SIMD-ONLY0-NEXT:    [[TMP272:%.*]] = load i8, ptr [[CE]], align 1
29036 // SIMD-ONLY0-NEXT:    [[CONV656:%.*]] = sext i8 [[TMP272]] to i32
29037 // SIMD-ONLY0-NEXT:    [[CMP657:%.*]] = icmp slt i32 [[CONV655]], [[CONV656]]
29038 // SIMD-ONLY0-NEXT:    br i1 [[CMP657]], label [[IF_THEN659:%.*]], label [[IF_END660:%.*]]
29039 // SIMD-ONLY0:       if.then659:
29040 // SIMD-ONLY0-NEXT:    [[TMP273:%.*]] = load i8, ptr [[CE]], align 1
29041 // SIMD-ONLY0-NEXT:    store i8 [[TMP273]], ptr [[CX]], align 1
29042 // SIMD-ONLY0-NEXT:    br label [[IF_END660]]
29043 // SIMD-ONLY0:       if.end660:
29044 // SIMD-ONLY0-NEXT:    [[TMP274:%.*]] = load i8, ptr [[CE]], align 1
29045 // SIMD-ONLY0-NEXT:    [[CONV661:%.*]] = sext i8 [[TMP274]] to i32
29046 // SIMD-ONLY0-NEXT:    [[TMP275:%.*]] = load i8, ptr [[CX]], align 1
29047 // SIMD-ONLY0-NEXT:    [[CONV662:%.*]] = sext i8 [[TMP275]] to i32
29048 // SIMD-ONLY0-NEXT:    [[CMP663:%.*]] = icmp sgt i32 [[CONV661]], [[CONV662]]
29049 // SIMD-ONLY0-NEXT:    br i1 [[CMP663]], label [[IF_THEN665:%.*]], label [[IF_END666:%.*]]
29050 // SIMD-ONLY0:       if.then665:
29051 // SIMD-ONLY0-NEXT:    [[TMP276:%.*]] = load i8, ptr [[CE]], align 1
29052 // SIMD-ONLY0-NEXT:    store i8 [[TMP276]], ptr [[CX]], align 1
29053 // SIMD-ONLY0-NEXT:    br label [[IF_END666]]
29054 // SIMD-ONLY0:       if.end666:
29055 // SIMD-ONLY0-NEXT:    [[TMP277:%.*]] = load i8, ptr [[CE]], align 1
29056 // SIMD-ONLY0-NEXT:    [[CONV667:%.*]] = sext i8 [[TMP277]] to i32
29057 // SIMD-ONLY0-NEXT:    [[TMP278:%.*]] = load i8, ptr [[CX]], align 1
29058 // SIMD-ONLY0-NEXT:    [[CONV668:%.*]] = sext i8 [[TMP278]] to i32
29059 // SIMD-ONLY0-NEXT:    [[CMP669:%.*]] = icmp slt i32 [[CONV667]], [[CONV668]]
29060 // SIMD-ONLY0-NEXT:    br i1 [[CMP669]], label [[IF_THEN671:%.*]], label [[IF_END672:%.*]]
29061 // SIMD-ONLY0:       if.then671:
29062 // SIMD-ONLY0-NEXT:    [[TMP279:%.*]] = load i8, ptr [[CE]], align 1
29063 // SIMD-ONLY0-NEXT:    store i8 [[TMP279]], ptr [[CX]], align 1
29064 // SIMD-ONLY0-NEXT:    br label [[IF_END672]]
29065 // SIMD-ONLY0:       if.end672:
29066 // SIMD-ONLY0-NEXT:    [[TMP280:%.*]] = load i8, ptr [[CX]], align 1
29067 // SIMD-ONLY0-NEXT:    [[CONV673:%.*]] = sext i8 [[TMP280]] to i32
29068 // SIMD-ONLY0-NEXT:    [[TMP281:%.*]] = load i8, ptr [[CE]], align 1
29069 // SIMD-ONLY0-NEXT:    [[CONV674:%.*]] = sext i8 [[TMP281]] to i32
29070 // SIMD-ONLY0-NEXT:    [[CMP675:%.*]] = icmp eq i32 [[CONV673]], [[CONV674]]
29071 // SIMD-ONLY0-NEXT:    br i1 [[CMP675]], label [[COND_TRUE677:%.*]], label [[COND_FALSE679:%.*]]
29072 // SIMD-ONLY0:       cond.true677:
29073 // SIMD-ONLY0-NEXT:    [[TMP282:%.*]] = load i8, ptr [[CD]], align 1
29074 // SIMD-ONLY0-NEXT:    [[CONV678:%.*]] = sext i8 [[TMP282]] to i32
29075 // SIMD-ONLY0-NEXT:    br label [[COND_END681:%.*]]
29076 // SIMD-ONLY0:       cond.false679:
29077 // SIMD-ONLY0-NEXT:    [[TMP283:%.*]] = load i8, ptr [[CX]], align 1
29078 // SIMD-ONLY0-NEXT:    [[CONV680:%.*]] = sext i8 [[TMP283]] to i32
29079 // SIMD-ONLY0-NEXT:    br label [[COND_END681]]
29080 // SIMD-ONLY0:       cond.end681:
29081 // SIMD-ONLY0-NEXT:    [[COND682:%.*]] = phi i32 [ [[CONV678]], [[COND_TRUE677]] ], [ [[CONV680]], [[COND_FALSE679]] ]
29082 // SIMD-ONLY0-NEXT:    [[CONV683:%.*]] = trunc i32 [[COND682]] to i8
29083 // SIMD-ONLY0-NEXT:    store i8 [[CONV683]], ptr [[CX]], align 1
29084 // SIMD-ONLY0-NEXT:    [[TMP284:%.*]] = load i8, ptr [[CE]], align 1
29085 // SIMD-ONLY0-NEXT:    [[CONV684:%.*]] = sext i8 [[TMP284]] to i32
29086 // SIMD-ONLY0-NEXT:    [[TMP285:%.*]] = load i8, ptr [[CX]], align 1
29087 // SIMD-ONLY0-NEXT:    [[CONV685:%.*]] = sext i8 [[TMP285]] to i32
29088 // SIMD-ONLY0-NEXT:    [[CMP686:%.*]] = icmp eq i32 [[CONV684]], [[CONV685]]
29089 // SIMD-ONLY0-NEXT:    br i1 [[CMP686]], label [[COND_TRUE688:%.*]], label [[COND_FALSE690:%.*]]
29090 // SIMD-ONLY0:       cond.true688:
29091 // SIMD-ONLY0-NEXT:    [[TMP286:%.*]] = load i8, ptr [[CD]], align 1
29092 // SIMD-ONLY0-NEXT:    [[CONV689:%.*]] = sext i8 [[TMP286]] to i32
29093 // SIMD-ONLY0-NEXT:    br label [[COND_END692:%.*]]
29094 // SIMD-ONLY0:       cond.false690:
29095 // SIMD-ONLY0-NEXT:    [[TMP287:%.*]] = load i8, ptr [[CX]], align 1
29096 // SIMD-ONLY0-NEXT:    [[CONV691:%.*]] = sext i8 [[TMP287]] to i32
29097 // SIMD-ONLY0-NEXT:    br label [[COND_END692]]
29098 // SIMD-ONLY0:       cond.end692:
29099 // SIMD-ONLY0-NEXT:    [[COND693:%.*]] = phi i32 [ [[CONV689]], [[COND_TRUE688]] ], [ [[CONV691]], [[COND_FALSE690]] ]
29100 // SIMD-ONLY0-NEXT:    [[CONV694:%.*]] = trunc i32 [[COND693]] to i8
29101 // SIMD-ONLY0-NEXT:    store i8 [[CONV694]], ptr [[CX]], align 1
29102 // SIMD-ONLY0-NEXT:    [[TMP288:%.*]] = load i8, ptr [[CX]], align 1
29103 // SIMD-ONLY0-NEXT:    [[CONV695:%.*]] = sext i8 [[TMP288]] to i32
29104 // SIMD-ONLY0-NEXT:    [[TMP289:%.*]] = load i8, ptr [[CE]], align 1
29105 // SIMD-ONLY0-NEXT:    [[CONV696:%.*]] = sext i8 [[TMP289]] to i32
29106 // SIMD-ONLY0-NEXT:    [[CMP697:%.*]] = icmp eq i32 [[CONV695]], [[CONV696]]
29107 // SIMD-ONLY0-NEXT:    br i1 [[CMP697]], label [[IF_THEN699:%.*]], label [[IF_END700:%.*]]
29108 // SIMD-ONLY0:       if.then699:
29109 // SIMD-ONLY0-NEXT:    [[TMP290:%.*]] = load i8, ptr [[CD]], align 1
29110 // SIMD-ONLY0-NEXT:    store i8 [[TMP290]], ptr [[CX]], align 1
29111 // SIMD-ONLY0-NEXT:    br label [[IF_END700]]
29112 // SIMD-ONLY0:       if.end700:
29113 // SIMD-ONLY0-NEXT:    [[TMP291:%.*]] = load i8, ptr [[CE]], align 1
29114 // SIMD-ONLY0-NEXT:    [[CONV701:%.*]] = sext i8 [[TMP291]] to i32
29115 // SIMD-ONLY0-NEXT:    [[TMP292:%.*]] = load i8, ptr [[CX]], align 1
29116 // SIMD-ONLY0-NEXT:    [[CONV702:%.*]] = sext i8 [[TMP292]] to i32
29117 // SIMD-ONLY0-NEXT:    [[CMP703:%.*]] = icmp eq i32 [[CONV701]], [[CONV702]]
29118 // SIMD-ONLY0-NEXT:    br i1 [[CMP703]], label [[IF_THEN705:%.*]], label [[IF_END706:%.*]]
29119 // SIMD-ONLY0:       if.then705:
29120 // SIMD-ONLY0-NEXT:    [[TMP293:%.*]] = load i8, ptr [[CD]], align 1
29121 // SIMD-ONLY0-NEXT:    store i8 [[TMP293]], ptr [[CX]], align 1
29122 // SIMD-ONLY0-NEXT:    br label [[IF_END706]]
29123 // SIMD-ONLY0:       if.end706:
29124 // SIMD-ONLY0-NEXT:    [[TMP294:%.*]] = load i8, ptr [[UCX]], align 1
29125 // SIMD-ONLY0-NEXT:    [[CONV707:%.*]] = zext i8 [[TMP294]] to i32
29126 // SIMD-ONLY0-NEXT:    [[TMP295:%.*]] = load i8, ptr [[UCE]], align 1
29127 // SIMD-ONLY0-NEXT:    [[CONV708:%.*]] = zext i8 [[TMP295]] to i32
29128 // SIMD-ONLY0-NEXT:    [[CMP709:%.*]] = icmp sgt i32 [[CONV707]], [[CONV708]]
29129 // SIMD-ONLY0-NEXT:    br i1 [[CMP709]], label [[COND_TRUE711:%.*]], label [[COND_FALSE713:%.*]]
29130 // SIMD-ONLY0:       cond.true711:
29131 // SIMD-ONLY0-NEXT:    [[TMP296:%.*]] = load i8, ptr [[UCE]], align 1
29132 // SIMD-ONLY0-NEXT:    [[CONV712:%.*]] = zext i8 [[TMP296]] to i32
29133 // SIMD-ONLY0-NEXT:    br label [[COND_END715:%.*]]
29134 // SIMD-ONLY0:       cond.false713:
29135 // SIMD-ONLY0-NEXT:    [[TMP297:%.*]] = load i8, ptr [[UCX]], align 1
29136 // SIMD-ONLY0-NEXT:    [[CONV714:%.*]] = zext i8 [[TMP297]] to i32
29137 // SIMD-ONLY0-NEXT:    br label [[COND_END715]]
29138 // SIMD-ONLY0:       cond.end715:
29139 // SIMD-ONLY0-NEXT:    [[COND716:%.*]] = phi i32 [ [[CONV712]], [[COND_TRUE711]] ], [ [[CONV714]], [[COND_FALSE713]] ]
29140 // SIMD-ONLY0-NEXT:    [[CONV717:%.*]] = trunc i32 [[COND716]] to i8
29141 // SIMD-ONLY0-NEXT:    store i8 [[CONV717]], ptr [[UCX]], align 1
29142 // SIMD-ONLY0-NEXT:    [[TMP298:%.*]] = load i8, ptr [[UCX]], align 1
29143 // SIMD-ONLY0-NEXT:    [[CONV718:%.*]] = zext i8 [[TMP298]] to i32
29144 // SIMD-ONLY0-NEXT:    [[TMP299:%.*]] = load i8, ptr [[UCE]], align 1
29145 // SIMD-ONLY0-NEXT:    [[CONV719:%.*]] = zext i8 [[TMP299]] to i32
29146 // SIMD-ONLY0-NEXT:    [[CMP720:%.*]] = icmp slt i32 [[CONV718]], [[CONV719]]
29147 // SIMD-ONLY0-NEXT:    br i1 [[CMP720]], label [[COND_TRUE722:%.*]], label [[COND_FALSE724:%.*]]
29148 // SIMD-ONLY0:       cond.true722:
29149 // SIMD-ONLY0-NEXT:    [[TMP300:%.*]] = load i8, ptr [[UCE]], align 1
29150 // SIMD-ONLY0-NEXT:    [[CONV723:%.*]] = zext i8 [[TMP300]] to i32
29151 // SIMD-ONLY0-NEXT:    br label [[COND_END726:%.*]]
29152 // SIMD-ONLY0:       cond.false724:
29153 // SIMD-ONLY0-NEXT:    [[TMP301:%.*]] = load i8, ptr [[UCX]], align 1
29154 // SIMD-ONLY0-NEXT:    [[CONV725:%.*]] = zext i8 [[TMP301]] to i32
29155 // SIMD-ONLY0-NEXT:    br label [[COND_END726]]
29156 // SIMD-ONLY0:       cond.end726:
29157 // SIMD-ONLY0-NEXT:    [[COND727:%.*]] = phi i32 [ [[CONV723]], [[COND_TRUE722]] ], [ [[CONV725]], [[COND_FALSE724]] ]
29158 // SIMD-ONLY0-NEXT:    [[CONV728:%.*]] = trunc i32 [[COND727]] to i8
29159 // SIMD-ONLY0-NEXT:    store i8 [[CONV728]], ptr [[UCX]], align 1
29160 // SIMD-ONLY0-NEXT:    [[TMP302:%.*]] = load i8, ptr [[UCE]], align 1
29161 // SIMD-ONLY0-NEXT:    [[CONV729:%.*]] = zext i8 [[TMP302]] to i32
29162 // SIMD-ONLY0-NEXT:    [[TMP303:%.*]] = load i8, ptr [[UCX]], align 1
29163 // SIMD-ONLY0-NEXT:    [[CONV730:%.*]] = zext i8 [[TMP303]] to i32
29164 // SIMD-ONLY0-NEXT:    [[CMP731:%.*]] = icmp sgt i32 [[CONV729]], [[CONV730]]
29165 // SIMD-ONLY0-NEXT:    br i1 [[CMP731]], label [[COND_TRUE733:%.*]], label [[COND_FALSE735:%.*]]
29166 // SIMD-ONLY0:       cond.true733:
29167 // SIMD-ONLY0-NEXT:    [[TMP304:%.*]] = load i8, ptr [[UCE]], align 1
29168 // SIMD-ONLY0-NEXT:    [[CONV734:%.*]] = zext i8 [[TMP304]] to i32
29169 // SIMD-ONLY0-NEXT:    br label [[COND_END737:%.*]]
29170 // SIMD-ONLY0:       cond.false735:
29171 // SIMD-ONLY0-NEXT:    [[TMP305:%.*]] = load i8, ptr [[UCX]], align 1
29172 // SIMD-ONLY0-NEXT:    [[CONV736:%.*]] = zext i8 [[TMP305]] to i32
29173 // SIMD-ONLY0-NEXT:    br label [[COND_END737]]
29174 // SIMD-ONLY0:       cond.end737:
29175 // SIMD-ONLY0-NEXT:    [[COND738:%.*]] = phi i32 [ [[CONV734]], [[COND_TRUE733]] ], [ [[CONV736]], [[COND_FALSE735]] ]
29176 // SIMD-ONLY0-NEXT:    [[CONV739:%.*]] = trunc i32 [[COND738]] to i8
29177 // SIMD-ONLY0-NEXT:    store i8 [[CONV739]], ptr [[UCX]], align 1
29178 // SIMD-ONLY0-NEXT:    [[TMP306:%.*]] = load i8, ptr [[UCE]], align 1
29179 // SIMD-ONLY0-NEXT:    [[CONV740:%.*]] = zext i8 [[TMP306]] to i32
29180 // SIMD-ONLY0-NEXT:    [[TMP307:%.*]] = load i8, ptr [[UCX]], align 1
29181 // SIMD-ONLY0-NEXT:    [[CONV741:%.*]] = zext i8 [[TMP307]] to i32
29182 // SIMD-ONLY0-NEXT:    [[CMP742:%.*]] = icmp slt i32 [[CONV740]], [[CONV741]]
29183 // SIMD-ONLY0-NEXT:    br i1 [[CMP742]], label [[COND_TRUE744:%.*]], label [[COND_FALSE746:%.*]]
29184 // SIMD-ONLY0:       cond.true744:
29185 // SIMD-ONLY0-NEXT:    [[TMP308:%.*]] = load i8, ptr [[UCE]], align 1
29186 // SIMD-ONLY0-NEXT:    [[CONV745:%.*]] = zext i8 [[TMP308]] to i32
29187 // SIMD-ONLY0-NEXT:    br label [[COND_END748:%.*]]
29188 // SIMD-ONLY0:       cond.false746:
29189 // SIMD-ONLY0-NEXT:    [[TMP309:%.*]] = load i8, ptr [[UCX]], align 1
29190 // SIMD-ONLY0-NEXT:    [[CONV747:%.*]] = zext i8 [[TMP309]] to i32
29191 // SIMD-ONLY0-NEXT:    br label [[COND_END748]]
29192 // SIMD-ONLY0:       cond.end748:
29193 // SIMD-ONLY0-NEXT:    [[COND749:%.*]] = phi i32 [ [[CONV745]], [[COND_TRUE744]] ], [ [[CONV747]], [[COND_FALSE746]] ]
29194 // SIMD-ONLY0-NEXT:    [[CONV750:%.*]] = trunc i32 [[COND749]] to i8
29195 // SIMD-ONLY0-NEXT:    store i8 [[CONV750]], ptr [[UCX]], align 1
29196 // SIMD-ONLY0-NEXT:    [[TMP310:%.*]] = load i8, ptr [[UCX]], align 1
29197 // SIMD-ONLY0-NEXT:    [[CONV751:%.*]] = zext i8 [[TMP310]] to i32
29198 // SIMD-ONLY0-NEXT:    [[TMP311:%.*]] = load i8, ptr [[UCE]], align 1
29199 // SIMD-ONLY0-NEXT:    [[CONV752:%.*]] = zext i8 [[TMP311]] to i32
29200 // SIMD-ONLY0-NEXT:    [[CMP753:%.*]] = icmp sgt i32 [[CONV751]], [[CONV752]]
29201 // SIMD-ONLY0-NEXT:    br i1 [[CMP753]], label [[IF_THEN755:%.*]], label [[IF_END756:%.*]]
29202 // SIMD-ONLY0:       if.then755:
29203 // SIMD-ONLY0-NEXT:    [[TMP312:%.*]] = load i8, ptr [[UCE]], align 1
29204 // SIMD-ONLY0-NEXT:    store i8 [[TMP312]], ptr [[UCX]], align 1
29205 // SIMD-ONLY0-NEXT:    br label [[IF_END756]]
29206 // SIMD-ONLY0:       if.end756:
29207 // SIMD-ONLY0-NEXT:    [[TMP313:%.*]] = load i8, ptr [[UCX]], align 1
29208 // SIMD-ONLY0-NEXT:    [[CONV757:%.*]] = zext i8 [[TMP313]] to i32
29209 // SIMD-ONLY0-NEXT:    [[TMP314:%.*]] = load i8, ptr [[UCE]], align 1
29210 // SIMD-ONLY0-NEXT:    [[CONV758:%.*]] = zext i8 [[TMP314]] to i32
29211 // SIMD-ONLY0-NEXT:    [[CMP759:%.*]] = icmp slt i32 [[CONV757]], [[CONV758]]
29212 // SIMD-ONLY0-NEXT:    br i1 [[CMP759]], label [[IF_THEN761:%.*]], label [[IF_END762:%.*]]
29213 // SIMD-ONLY0:       if.then761:
29214 // SIMD-ONLY0-NEXT:    [[TMP315:%.*]] = load i8, ptr [[UCE]], align 1
29215 // SIMD-ONLY0-NEXT:    store i8 [[TMP315]], ptr [[UCX]], align 1
29216 // SIMD-ONLY0-NEXT:    br label [[IF_END762]]
29217 // SIMD-ONLY0:       if.end762:
29218 // SIMD-ONLY0-NEXT:    [[TMP316:%.*]] = load i8, ptr [[UCE]], align 1
29219 // SIMD-ONLY0-NEXT:    [[CONV763:%.*]] = zext i8 [[TMP316]] to i32
29220 // SIMD-ONLY0-NEXT:    [[TMP317:%.*]] = load i8, ptr [[UCX]], align 1
29221 // SIMD-ONLY0-NEXT:    [[CONV764:%.*]] = zext i8 [[TMP317]] to i32
29222 // SIMD-ONLY0-NEXT:    [[CMP765:%.*]] = icmp sgt i32 [[CONV763]], [[CONV764]]
29223 // SIMD-ONLY0-NEXT:    br i1 [[CMP765]], label [[IF_THEN767:%.*]], label [[IF_END768:%.*]]
29224 // SIMD-ONLY0:       if.then767:
29225 // SIMD-ONLY0-NEXT:    [[TMP318:%.*]] = load i8, ptr [[UCE]], align 1
29226 // SIMD-ONLY0-NEXT:    store i8 [[TMP318]], ptr [[UCX]], align 1
29227 // SIMD-ONLY0-NEXT:    br label [[IF_END768]]
29228 // SIMD-ONLY0:       if.end768:
29229 // SIMD-ONLY0-NEXT:    [[TMP319:%.*]] = load i8, ptr [[UCE]], align 1
29230 // SIMD-ONLY0-NEXT:    [[CONV769:%.*]] = zext i8 [[TMP319]] to i32
29231 // SIMD-ONLY0-NEXT:    [[TMP320:%.*]] = load i8, ptr [[UCX]], align 1
29232 // SIMD-ONLY0-NEXT:    [[CONV770:%.*]] = zext i8 [[TMP320]] to i32
29233 // SIMD-ONLY0-NEXT:    [[CMP771:%.*]] = icmp slt i32 [[CONV769]], [[CONV770]]
29234 // SIMD-ONLY0-NEXT:    br i1 [[CMP771]], label [[IF_THEN773:%.*]], label [[IF_END774:%.*]]
29235 // SIMD-ONLY0:       if.then773:
29236 // SIMD-ONLY0-NEXT:    [[TMP321:%.*]] = load i8, ptr [[UCE]], align 1
29237 // SIMD-ONLY0-NEXT:    store i8 [[TMP321]], ptr [[UCX]], align 1
29238 // SIMD-ONLY0-NEXT:    br label [[IF_END774]]
29239 // SIMD-ONLY0:       if.end774:
29240 // SIMD-ONLY0-NEXT:    [[TMP322:%.*]] = load i8, ptr [[UCX]], align 1
29241 // SIMD-ONLY0-NEXT:    [[CONV775:%.*]] = zext i8 [[TMP322]] to i32
29242 // SIMD-ONLY0-NEXT:    [[TMP323:%.*]] = load i8, ptr [[UCE]], align 1
29243 // SIMD-ONLY0-NEXT:    [[CONV776:%.*]] = zext i8 [[TMP323]] to i32
29244 // SIMD-ONLY0-NEXT:    [[CMP777:%.*]] = icmp eq i32 [[CONV775]], [[CONV776]]
29245 // SIMD-ONLY0-NEXT:    br i1 [[CMP777]], label [[COND_TRUE779:%.*]], label [[COND_FALSE781:%.*]]
29246 // SIMD-ONLY0:       cond.true779:
29247 // SIMD-ONLY0-NEXT:    [[TMP324:%.*]] = load i8, ptr [[UCD]], align 1
29248 // SIMD-ONLY0-NEXT:    [[CONV780:%.*]] = zext i8 [[TMP324]] to i32
29249 // SIMD-ONLY0-NEXT:    br label [[COND_END783:%.*]]
29250 // SIMD-ONLY0:       cond.false781:
29251 // SIMD-ONLY0-NEXT:    [[TMP325:%.*]] = load i8, ptr [[UCX]], align 1
29252 // SIMD-ONLY0-NEXT:    [[CONV782:%.*]] = zext i8 [[TMP325]] to i32
29253 // SIMD-ONLY0-NEXT:    br label [[COND_END783]]
29254 // SIMD-ONLY0:       cond.end783:
29255 // SIMD-ONLY0-NEXT:    [[COND784:%.*]] = phi i32 [ [[CONV780]], [[COND_TRUE779]] ], [ [[CONV782]], [[COND_FALSE781]] ]
29256 // SIMD-ONLY0-NEXT:    [[CONV785:%.*]] = trunc i32 [[COND784]] to i8
29257 // SIMD-ONLY0-NEXT:    store i8 [[CONV785]], ptr [[UCX]], align 1
29258 // SIMD-ONLY0-NEXT:    [[TMP326:%.*]] = load i8, ptr [[UCE]], align 1
29259 // SIMD-ONLY0-NEXT:    [[CONV786:%.*]] = zext i8 [[TMP326]] to i32
29260 // SIMD-ONLY0-NEXT:    [[TMP327:%.*]] = load i8, ptr [[UCX]], align 1
29261 // SIMD-ONLY0-NEXT:    [[CONV787:%.*]] = zext i8 [[TMP327]] to i32
29262 // SIMD-ONLY0-NEXT:    [[CMP788:%.*]] = icmp eq i32 [[CONV786]], [[CONV787]]
29263 // SIMD-ONLY0-NEXT:    br i1 [[CMP788]], label [[COND_TRUE790:%.*]], label [[COND_FALSE792:%.*]]
29264 // SIMD-ONLY0:       cond.true790:
29265 // SIMD-ONLY0-NEXT:    [[TMP328:%.*]] = load i8, ptr [[UCD]], align 1
29266 // SIMD-ONLY0-NEXT:    [[CONV791:%.*]] = zext i8 [[TMP328]] to i32
29267 // SIMD-ONLY0-NEXT:    br label [[COND_END794:%.*]]
29268 // SIMD-ONLY0:       cond.false792:
29269 // SIMD-ONLY0-NEXT:    [[TMP329:%.*]] = load i8, ptr [[UCX]], align 1
29270 // SIMD-ONLY0-NEXT:    [[CONV793:%.*]] = zext i8 [[TMP329]] to i32
29271 // SIMD-ONLY0-NEXT:    br label [[COND_END794]]
29272 // SIMD-ONLY0:       cond.end794:
29273 // SIMD-ONLY0-NEXT:    [[COND795:%.*]] = phi i32 [ [[CONV791]], [[COND_TRUE790]] ], [ [[CONV793]], [[COND_FALSE792]] ]
29274 // SIMD-ONLY0-NEXT:    [[CONV796:%.*]] = trunc i32 [[COND795]] to i8
29275 // SIMD-ONLY0-NEXT:    store i8 [[CONV796]], ptr [[UCX]], align 1
29276 // SIMD-ONLY0-NEXT:    [[TMP330:%.*]] = load i8, ptr [[UCX]], align 1
29277 // SIMD-ONLY0-NEXT:    [[CONV797:%.*]] = zext i8 [[TMP330]] to i32
29278 // SIMD-ONLY0-NEXT:    [[TMP331:%.*]] = load i8, ptr [[UCE]], align 1
29279 // SIMD-ONLY0-NEXT:    [[CONV798:%.*]] = zext i8 [[TMP331]] to i32
29280 // SIMD-ONLY0-NEXT:    [[CMP799:%.*]] = icmp eq i32 [[CONV797]], [[CONV798]]
29281 // SIMD-ONLY0-NEXT:    br i1 [[CMP799]], label [[IF_THEN801:%.*]], label [[IF_END802:%.*]]
29282 // SIMD-ONLY0:       if.then801:
29283 // SIMD-ONLY0-NEXT:    [[TMP332:%.*]] = load i8, ptr [[UCD]], align 1
29284 // SIMD-ONLY0-NEXT:    store i8 [[TMP332]], ptr [[UCX]], align 1
29285 // SIMD-ONLY0-NEXT:    br label [[IF_END802]]
29286 // SIMD-ONLY0:       if.end802:
29287 // SIMD-ONLY0-NEXT:    [[TMP333:%.*]] = load i8, ptr [[UCE]], align 1
29288 // SIMD-ONLY0-NEXT:    [[CONV803:%.*]] = zext i8 [[TMP333]] to i32
29289 // SIMD-ONLY0-NEXT:    [[TMP334:%.*]] = load i8, ptr [[UCX]], align 1
29290 // SIMD-ONLY0-NEXT:    [[CONV804:%.*]] = zext i8 [[TMP334]] to i32
29291 // SIMD-ONLY0-NEXT:    [[CMP805:%.*]] = icmp eq i32 [[CONV803]], [[CONV804]]
29292 // SIMD-ONLY0-NEXT:    br i1 [[CMP805]], label [[IF_THEN807:%.*]], label [[IF_END808:%.*]]
29293 // SIMD-ONLY0:       if.then807:
29294 // SIMD-ONLY0-NEXT:    [[TMP335:%.*]] = load i8, ptr [[UCD]], align 1
29295 // SIMD-ONLY0-NEXT:    store i8 [[TMP335]], ptr [[UCX]], align 1
29296 // SIMD-ONLY0-NEXT:    br label [[IF_END808]]
29297 // SIMD-ONLY0:       if.end808:
29298 // SIMD-ONLY0-NEXT:    [[TMP336:%.*]] = load i8, ptr [[CX]], align 1
29299 // SIMD-ONLY0-NEXT:    [[CONV809:%.*]] = sext i8 [[TMP336]] to i32
29300 // SIMD-ONLY0-NEXT:    [[TMP337:%.*]] = load i8, ptr [[CE]], align 1
29301 // SIMD-ONLY0-NEXT:    [[CONV810:%.*]] = sext i8 [[TMP337]] to i32
29302 // SIMD-ONLY0-NEXT:    [[CMP811:%.*]] = icmp sgt i32 [[CONV809]], [[CONV810]]
29303 // SIMD-ONLY0-NEXT:    br i1 [[CMP811]], label [[COND_TRUE813:%.*]], label [[COND_FALSE815:%.*]]
29304 // SIMD-ONLY0:       cond.true813:
29305 // SIMD-ONLY0-NEXT:    [[TMP338:%.*]] = load i8, ptr [[CE]], align 1
29306 // SIMD-ONLY0-NEXT:    [[CONV814:%.*]] = sext i8 [[TMP338]] to i32
29307 // SIMD-ONLY0-NEXT:    br label [[COND_END817:%.*]]
29308 // SIMD-ONLY0:       cond.false815:
29309 // SIMD-ONLY0-NEXT:    [[TMP339:%.*]] = load i8, ptr [[CX]], align 1
29310 // SIMD-ONLY0-NEXT:    [[CONV816:%.*]] = sext i8 [[TMP339]] to i32
29311 // SIMD-ONLY0-NEXT:    br label [[COND_END817]]
29312 // SIMD-ONLY0:       cond.end817:
29313 // SIMD-ONLY0-NEXT:    [[COND818:%.*]] = phi i32 [ [[CONV814]], [[COND_TRUE813]] ], [ [[CONV816]], [[COND_FALSE815]] ]
29314 // SIMD-ONLY0-NEXT:    [[CONV819:%.*]] = trunc i32 [[COND818]] to i8
29315 // SIMD-ONLY0-NEXT:    store i8 [[CONV819]], ptr [[CX]], align 1
29316 // SIMD-ONLY0-NEXT:    [[TMP340:%.*]] = load i8, ptr [[CX]], align 1
29317 // SIMD-ONLY0-NEXT:    [[CONV820:%.*]] = sext i8 [[TMP340]] to i32
29318 // SIMD-ONLY0-NEXT:    [[TMP341:%.*]] = load i8, ptr [[CE]], align 1
29319 // SIMD-ONLY0-NEXT:    [[CONV821:%.*]] = sext i8 [[TMP341]] to i32
29320 // SIMD-ONLY0-NEXT:    [[CMP822:%.*]] = icmp slt i32 [[CONV820]], [[CONV821]]
29321 // SIMD-ONLY0-NEXT:    br i1 [[CMP822]], label [[COND_TRUE824:%.*]], label [[COND_FALSE826:%.*]]
29322 // SIMD-ONLY0:       cond.true824:
29323 // SIMD-ONLY0-NEXT:    [[TMP342:%.*]] = load i8, ptr [[CE]], align 1
29324 // SIMD-ONLY0-NEXT:    [[CONV825:%.*]] = sext i8 [[TMP342]] to i32
29325 // SIMD-ONLY0-NEXT:    br label [[COND_END828:%.*]]
29326 // SIMD-ONLY0:       cond.false826:
29327 // SIMD-ONLY0-NEXT:    [[TMP343:%.*]] = load i8, ptr [[CX]], align 1
29328 // SIMD-ONLY0-NEXT:    [[CONV827:%.*]] = sext i8 [[TMP343]] to i32
29329 // SIMD-ONLY0-NEXT:    br label [[COND_END828]]
29330 // SIMD-ONLY0:       cond.end828:
29331 // SIMD-ONLY0-NEXT:    [[COND829:%.*]] = phi i32 [ [[CONV825]], [[COND_TRUE824]] ], [ [[CONV827]], [[COND_FALSE826]] ]
29332 // SIMD-ONLY0-NEXT:    [[CONV830:%.*]] = trunc i32 [[COND829]] to i8
29333 // SIMD-ONLY0-NEXT:    store i8 [[CONV830]], ptr [[CX]], align 1
29334 // SIMD-ONLY0-NEXT:    [[TMP344:%.*]] = load i8, ptr [[CE]], align 1
29335 // SIMD-ONLY0-NEXT:    [[CONV831:%.*]] = sext i8 [[TMP344]] to i32
29336 // SIMD-ONLY0-NEXT:    [[TMP345:%.*]] = load i8, ptr [[CX]], align 1
29337 // SIMD-ONLY0-NEXT:    [[CONV832:%.*]] = sext i8 [[TMP345]] to i32
29338 // SIMD-ONLY0-NEXT:    [[CMP833:%.*]] = icmp sgt i32 [[CONV831]], [[CONV832]]
29339 // SIMD-ONLY0-NEXT:    br i1 [[CMP833]], label [[COND_TRUE835:%.*]], label [[COND_FALSE837:%.*]]
29340 // SIMD-ONLY0:       cond.true835:
29341 // SIMD-ONLY0-NEXT:    [[TMP346:%.*]] = load i8, ptr [[CE]], align 1
29342 // SIMD-ONLY0-NEXT:    [[CONV836:%.*]] = sext i8 [[TMP346]] to i32
29343 // SIMD-ONLY0-NEXT:    br label [[COND_END839:%.*]]
29344 // SIMD-ONLY0:       cond.false837:
29345 // SIMD-ONLY0-NEXT:    [[TMP347:%.*]] = load i8, ptr [[CX]], align 1
29346 // SIMD-ONLY0-NEXT:    [[CONV838:%.*]] = sext i8 [[TMP347]] to i32
29347 // SIMD-ONLY0-NEXT:    br label [[COND_END839]]
29348 // SIMD-ONLY0:       cond.end839:
29349 // SIMD-ONLY0-NEXT:    [[COND840:%.*]] = phi i32 [ [[CONV836]], [[COND_TRUE835]] ], [ [[CONV838]], [[COND_FALSE837]] ]
29350 // SIMD-ONLY0-NEXT:    [[CONV841:%.*]] = trunc i32 [[COND840]] to i8
29351 // SIMD-ONLY0-NEXT:    store i8 [[CONV841]], ptr [[CX]], align 1
29352 // SIMD-ONLY0-NEXT:    [[TMP348:%.*]] = load i8, ptr [[CE]], align 1
29353 // SIMD-ONLY0-NEXT:    [[CONV842:%.*]] = sext i8 [[TMP348]] to i32
29354 // SIMD-ONLY0-NEXT:    [[TMP349:%.*]] = load i8, ptr [[CX]], align 1
29355 // SIMD-ONLY0-NEXT:    [[CONV843:%.*]] = sext i8 [[TMP349]] to i32
29356 // SIMD-ONLY0-NEXT:    [[CMP844:%.*]] = icmp slt i32 [[CONV842]], [[CONV843]]
29357 // SIMD-ONLY0-NEXT:    br i1 [[CMP844]], label [[COND_TRUE846:%.*]], label [[COND_FALSE848:%.*]]
29358 // SIMD-ONLY0:       cond.true846:
29359 // SIMD-ONLY0-NEXT:    [[TMP350:%.*]] = load i8, ptr [[CE]], align 1
29360 // SIMD-ONLY0-NEXT:    [[CONV847:%.*]] = sext i8 [[TMP350]] to i32
29361 // SIMD-ONLY0-NEXT:    br label [[COND_END850:%.*]]
29362 // SIMD-ONLY0:       cond.false848:
29363 // SIMD-ONLY0-NEXT:    [[TMP351:%.*]] = load i8, ptr [[CX]], align 1
29364 // SIMD-ONLY0-NEXT:    [[CONV849:%.*]] = sext i8 [[TMP351]] to i32
29365 // SIMD-ONLY0-NEXT:    br label [[COND_END850]]
29366 // SIMD-ONLY0:       cond.end850:
29367 // SIMD-ONLY0-NEXT:    [[COND851:%.*]] = phi i32 [ [[CONV847]], [[COND_TRUE846]] ], [ [[CONV849]], [[COND_FALSE848]] ]
29368 // SIMD-ONLY0-NEXT:    [[CONV852:%.*]] = trunc i32 [[COND851]] to i8
29369 // SIMD-ONLY0-NEXT:    store i8 [[CONV852]], ptr [[CX]], align 1
29370 // SIMD-ONLY0-NEXT:    [[TMP352:%.*]] = load i8, ptr [[CX]], align 1
29371 // SIMD-ONLY0-NEXT:    [[CONV853:%.*]] = sext i8 [[TMP352]] to i32
29372 // SIMD-ONLY0-NEXT:    [[TMP353:%.*]] = load i8, ptr [[CE]], align 1
29373 // SIMD-ONLY0-NEXT:    [[CONV854:%.*]] = sext i8 [[TMP353]] to i32
29374 // SIMD-ONLY0-NEXT:    [[CMP855:%.*]] = icmp sgt i32 [[CONV853]], [[CONV854]]
29375 // SIMD-ONLY0-NEXT:    br i1 [[CMP855]], label [[IF_THEN857:%.*]], label [[IF_END858:%.*]]
29376 // SIMD-ONLY0:       if.then857:
29377 // SIMD-ONLY0-NEXT:    [[TMP354:%.*]] = load i8, ptr [[CE]], align 1
29378 // SIMD-ONLY0-NEXT:    store i8 [[TMP354]], ptr [[CX]], align 1
29379 // SIMD-ONLY0-NEXT:    br label [[IF_END858]]
29380 // SIMD-ONLY0:       if.end858:
29381 // SIMD-ONLY0-NEXT:    [[TMP355:%.*]] = load i8, ptr [[CX]], align 1
29382 // SIMD-ONLY0-NEXT:    [[CONV859:%.*]] = sext i8 [[TMP355]] to i32
29383 // SIMD-ONLY0-NEXT:    [[TMP356:%.*]] = load i8, ptr [[CE]], align 1
29384 // SIMD-ONLY0-NEXT:    [[CONV860:%.*]] = sext i8 [[TMP356]] to i32
29385 // SIMD-ONLY0-NEXT:    [[CMP861:%.*]] = icmp slt i32 [[CONV859]], [[CONV860]]
29386 // SIMD-ONLY0-NEXT:    br i1 [[CMP861]], label [[IF_THEN863:%.*]], label [[IF_END864:%.*]]
29387 // SIMD-ONLY0:       if.then863:
29388 // SIMD-ONLY0-NEXT:    [[TMP357:%.*]] = load i8, ptr [[CE]], align 1
29389 // SIMD-ONLY0-NEXT:    store i8 [[TMP357]], ptr [[CX]], align 1
29390 // SIMD-ONLY0-NEXT:    br label [[IF_END864]]
29391 // SIMD-ONLY0:       if.end864:
29392 // SIMD-ONLY0-NEXT:    [[TMP358:%.*]] = load i8, ptr [[CE]], align 1
29393 // SIMD-ONLY0-NEXT:    [[CONV865:%.*]] = sext i8 [[TMP358]] to i32
29394 // SIMD-ONLY0-NEXT:    [[TMP359:%.*]] = load i8, ptr [[CX]], align 1
29395 // SIMD-ONLY0-NEXT:    [[CONV866:%.*]] = sext i8 [[TMP359]] to i32
29396 // SIMD-ONLY0-NEXT:    [[CMP867:%.*]] = icmp sgt i32 [[CONV865]], [[CONV866]]
29397 // SIMD-ONLY0-NEXT:    br i1 [[CMP867]], label [[IF_THEN869:%.*]], label [[IF_END870:%.*]]
29398 // SIMD-ONLY0:       if.then869:
29399 // SIMD-ONLY0-NEXT:    [[TMP360:%.*]] = load i8, ptr [[CE]], align 1
29400 // SIMD-ONLY0-NEXT:    store i8 [[TMP360]], ptr [[CX]], align 1
29401 // SIMD-ONLY0-NEXT:    br label [[IF_END870]]
29402 // SIMD-ONLY0:       if.end870:
29403 // SIMD-ONLY0-NEXT:    [[TMP361:%.*]] = load i8, ptr [[CE]], align 1
29404 // SIMD-ONLY0-NEXT:    [[CONV871:%.*]] = sext i8 [[TMP361]] to i32
29405 // SIMD-ONLY0-NEXT:    [[TMP362:%.*]] = load i8, ptr [[CX]], align 1
29406 // SIMD-ONLY0-NEXT:    [[CONV872:%.*]] = sext i8 [[TMP362]] to i32
29407 // SIMD-ONLY0-NEXT:    [[CMP873:%.*]] = icmp slt i32 [[CONV871]], [[CONV872]]
29408 // SIMD-ONLY0-NEXT:    br i1 [[CMP873]], label [[IF_THEN875:%.*]], label [[IF_END876:%.*]]
29409 // SIMD-ONLY0:       if.then875:
29410 // SIMD-ONLY0-NEXT:    [[TMP363:%.*]] = load i8, ptr [[CE]], align 1
29411 // SIMD-ONLY0-NEXT:    store i8 [[TMP363]], ptr [[CX]], align 1
29412 // SIMD-ONLY0-NEXT:    br label [[IF_END876]]
29413 // SIMD-ONLY0:       if.end876:
29414 // SIMD-ONLY0-NEXT:    [[TMP364:%.*]] = load i8, ptr [[CX]], align 1
29415 // SIMD-ONLY0-NEXT:    [[CONV877:%.*]] = sext i8 [[TMP364]] to i32
29416 // SIMD-ONLY0-NEXT:    [[TMP365:%.*]] = load i8, ptr [[CE]], align 1
29417 // SIMD-ONLY0-NEXT:    [[CONV878:%.*]] = sext i8 [[TMP365]] to i32
29418 // SIMD-ONLY0-NEXT:    [[CMP879:%.*]] = icmp eq i32 [[CONV877]], [[CONV878]]
29419 // SIMD-ONLY0-NEXT:    br i1 [[CMP879]], label [[COND_TRUE881:%.*]], label [[COND_FALSE883:%.*]]
29420 // SIMD-ONLY0:       cond.true881:
29421 // SIMD-ONLY0-NEXT:    [[TMP366:%.*]] = load i8, ptr [[CD]], align 1
29422 // SIMD-ONLY0-NEXT:    [[CONV882:%.*]] = sext i8 [[TMP366]] to i32
29423 // SIMD-ONLY0-NEXT:    br label [[COND_END885:%.*]]
29424 // SIMD-ONLY0:       cond.false883:
29425 // SIMD-ONLY0-NEXT:    [[TMP367:%.*]] = load i8, ptr [[CX]], align 1
29426 // SIMD-ONLY0-NEXT:    [[CONV884:%.*]] = sext i8 [[TMP367]] to i32
29427 // SIMD-ONLY0-NEXT:    br label [[COND_END885]]
29428 // SIMD-ONLY0:       cond.end885:
29429 // SIMD-ONLY0-NEXT:    [[COND886:%.*]] = phi i32 [ [[CONV882]], [[COND_TRUE881]] ], [ [[CONV884]], [[COND_FALSE883]] ]
29430 // SIMD-ONLY0-NEXT:    [[CONV887:%.*]] = trunc i32 [[COND886]] to i8
29431 // SIMD-ONLY0-NEXT:    store i8 [[CONV887]], ptr [[CX]], align 1
29432 // SIMD-ONLY0-NEXT:    [[TMP368:%.*]] = load i8, ptr [[CE]], align 1
29433 // SIMD-ONLY0-NEXT:    [[CONV888:%.*]] = sext i8 [[TMP368]] to i32
29434 // SIMD-ONLY0-NEXT:    [[TMP369:%.*]] = load i8, ptr [[CX]], align 1
29435 // SIMD-ONLY0-NEXT:    [[CONV889:%.*]] = sext i8 [[TMP369]] to i32
29436 // SIMD-ONLY0-NEXT:    [[CMP890:%.*]] = icmp eq i32 [[CONV888]], [[CONV889]]
29437 // SIMD-ONLY0-NEXT:    br i1 [[CMP890]], label [[COND_TRUE892:%.*]], label [[COND_FALSE894:%.*]]
29438 // SIMD-ONLY0:       cond.true892:
29439 // SIMD-ONLY0-NEXT:    [[TMP370:%.*]] = load i8, ptr [[CD]], align 1
29440 // SIMD-ONLY0-NEXT:    [[CONV893:%.*]] = sext i8 [[TMP370]] to i32
29441 // SIMD-ONLY0-NEXT:    br label [[COND_END896:%.*]]
29442 // SIMD-ONLY0:       cond.false894:
29443 // SIMD-ONLY0-NEXT:    [[TMP371:%.*]] = load i8, ptr [[CX]], align 1
29444 // SIMD-ONLY0-NEXT:    [[CONV895:%.*]] = sext i8 [[TMP371]] to i32
29445 // SIMD-ONLY0-NEXT:    br label [[COND_END896]]
29446 // SIMD-ONLY0:       cond.end896:
29447 // SIMD-ONLY0-NEXT:    [[COND897:%.*]] = phi i32 [ [[CONV893]], [[COND_TRUE892]] ], [ [[CONV895]], [[COND_FALSE894]] ]
29448 // SIMD-ONLY0-NEXT:    [[CONV898:%.*]] = trunc i32 [[COND897]] to i8
29449 // SIMD-ONLY0-NEXT:    store i8 [[CONV898]], ptr [[CX]], align 1
29450 // SIMD-ONLY0-NEXT:    [[TMP372:%.*]] = load i8, ptr [[CX]], align 1
29451 // SIMD-ONLY0-NEXT:    [[CONV899:%.*]] = sext i8 [[TMP372]] to i32
29452 // SIMD-ONLY0-NEXT:    [[TMP373:%.*]] = load i8, ptr [[CE]], align 1
29453 // SIMD-ONLY0-NEXT:    [[CONV900:%.*]] = sext i8 [[TMP373]] to i32
29454 // SIMD-ONLY0-NEXT:    [[CMP901:%.*]] = icmp eq i32 [[CONV899]], [[CONV900]]
29455 // SIMD-ONLY0-NEXT:    br i1 [[CMP901]], label [[IF_THEN903:%.*]], label [[IF_END904:%.*]]
29456 // SIMD-ONLY0:       if.then903:
29457 // SIMD-ONLY0-NEXT:    [[TMP374:%.*]] = load i8, ptr [[CD]], align 1
29458 // SIMD-ONLY0-NEXT:    store i8 [[TMP374]], ptr [[CX]], align 1
29459 // SIMD-ONLY0-NEXT:    br label [[IF_END904]]
29460 // SIMD-ONLY0:       if.end904:
29461 // SIMD-ONLY0-NEXT:    [[TMP375:%.*]] = load i8, ptr [[CE]], align 1
29462 // SIMD-ONLY0-NEXT:    [[CONV905:%.*]] = sext i8 [[TMP375]] to i32
29463 // SIMD-ONLY0-NEXT:    [[TMP376:%.*]] = load i8, ptr [[CX]], align 1
29464 // SIMD-ONLY0-NEXT:    [[CONV906:%.*]] = sext i8 [[TMP376]] to i32
29465 // SIMD-ONLY0-NEXT:    [[CMP907:%.*]] = icmp eq i32 [[CONV905]], [[CONV906]]
29466 // SIMD-ONLY0-NEXT:    br i1 [[CMP907]], label [[IF_THEN909:%.*]], label [[IF_END910:%.*]]
29467 // SIMD-ONLY0:       if.then909:
29468 // SIMD-ONLY0-NEXT:    [[TMP377:%.*]] = load i8, ptr [[CD]], align 1
29469 // SIMD-ONLY0-NEXT:    store i8 [[TMP377]], ptr [[CX]], align 1
29470 // SIMD-ONLY0-NEXT:    br label [[IF_END910]]
29471 // SIMD-ONLY0:       if.end910:
29472 // SIMD-ONLY0-NEXT:    [[TMP378:%.*]] = load i8, ptr [[UCX]], align 1
29473 // SIMD-ONLY0-NEXT:    [[CONV911:%.*]] = zext i8 [[TMP378]] to i32
29474 // SIMD-ONLY0-NEXT:    [[TMP379:%.*]] = load i8, ptr [[UCE]], align 1
29475 // SIMD-ONLY0-NEXT:    [[CONV912:%.*]] = zext i8 [[TMP379]] to i32
29476 // SIMD-ONLY0-NEXT:    [[CMP913:%.*]] = icmp sgt i32 [[CONV911]], [[CONV912]]
29477 // SIMD-ONLY0-NEXT:    br i1 [[CMP913]], label [[COND_TRUE915:%.*]], label [[COND_FALSE917:%.*]]
29478 // SIMD-ONLY0:       cond.true915:
29479 // SIMD-ONLY0-NEXT:    [[TMP380:%.*]] = load i8, ptr [[UCE]], align 1
29480 // SIMD-ONLY0-NEXT:    [[CONV916:%.*]] = zext i8 [[TMP380]] to i32
29481 // SIMD-ONLY0-NEXT:    br label [[COND_END919:%.*]]
29482 // SIMD-ONLY0:       cond.false917:
29483 // SIMD-ONLY0-NEXT:    [[TMP381:%.*]] = load i8, ptr [[UCX]], align 1
29484 // SIMD-ONLY0-NEXT:    [[CONV918:%.*]] = zext i8 [[TMP381]] to i32
29485 // SIMD-ONLY0-NEXT:    br label [[COND_END919]]
29486 // SIMD-ONLY0:       cond.end919:
29487 // SIMD-ONLY0-NEXT:    [[COND920:%.*]] = phi i32 [ [[CONV916]], [[COND_TRUE915]] ], [ [[CONV918]], [[COND_FALSE917]] ]
29488 // SIMD-ONLY0-NEXT:    [[CONV921:%.*]] = trunc i32 [[COND920]] to i8
29489 // SIMD-ONLY0-NEXT:    store i8 [[CONV921]], ptr [[UCX]], align 1
29490 // SIMD-ONLY0-NEXT:    [[TMP382:%.*]] = load i8, ptr [[UCX]], align 1
29491 // SIMD-ONLY0-NEXT:    [[CONV922:%.*]] = zext i8 [[TMP382]] to i32
29492 // SIMD-ONLY0-NEXT:    [[TMP383:%.*]] = load i8, ptr [[UCE]], align 1
29493 // SIMD-ONLY0-NEXT:    [[CONV923:%.*]] = zext i8 [[TMP383]] to i32
29494 // SIMD-ONLY0-NEXT:    [[CMP924:%.*]] = icmp slt i32 [[CONV922]], [[CONV923]]
29495 // SIMD-ONLY0-NEXT:    br i1 [[CMP924]], label [[COND_TRUE926:%.*]], label [[COND_FALSE928:%.*]]
29496 // SIMD-ONLY0:       cond.true926:
29497 // SIMD-ONLY0-NEXT:    [[TMP384:%.*]] = load i8, ptr [[UCE]], align 1
29498 // SIMD-ONLY0-NEXT:    [[CONV927:%.*]] = zext i8 [[TMP384]] to i32
29499 // SIMD-ONLY0-NEXT:    br label [[COND_END930:%.*]]
29500 // SIMD-ONLY0:       cond.false928:
29501 // SIMD-ONLY0-NEXT:    [[TMP385:%.*]] = load i8, ptr [[UCX]], align 1
29502 // SIMD-ONLY0-NEXT:    [[CONV929:%.*]] = zext i8 [[TMP385]] to i32
29503 // SIMD-ONLY0-NEXT:    br label [[COND_END930]]
29504 // SIMD-ONLY0:       cond.end930:
29505 // SIMD-ONLY0-NEXT:    [[COND931:%.*]] = phi i32 [ [[CONV927]], [[COND_TRUE926]] ], [ [[CONV929]], [[COND_FALSE928]] ]
29506 // SIMD-ONLY0-NEXT:    [[CONV932:%.*]] = trunc i32 [[COND931]] to i8
29507 // SIMD-ONLY0-NEXT:    store i8 [[CONV932]], ptr [[UCX]], align 1
29508 // SIMD-ONLY0-NEXT:    [[TMP386:%.*]] = load i8, ptr [[UCE]], align 1
29509 // SIMD-ONLY0-NEXT:    [[CONV933:%.*]] = zext i8 [[TMP386]] to i32
29510 // SIMD-ONLY0-NEXT:    [[TMP387:%.*]] = load i8, ptr [[UCX]], align 1
29511 // SIMD-ONLY0-NEXT:    [[CONV934:%.*]] = zext i8 [[TMP387]] to i32
29512 // SIMD-ONLY0-NEXT:    [[CMP935:%.*]] = icmp sgt i32 [[CONV933]], [[CONV934]]
29513 // SIMD-ONLY0-NEXT:    br i1 [[CMP935]], label [[COND_TRUE937:%.*]], label [[COND_FALSE939:%.*]]
29514 // SIMD-ONLY0:       cond.true937:
29515 // SIMD-ONLY0-NEXT:    [[TMP388:%.*]] = load i8, ptr [[UCE]], align 1
29516 // SIMD-ONLY0-NEXT:    [[CONV938:%.*]] = zext i8 [[TMP388]] to i32
29517 // SIMD-ONLY0-NEXT:    br label [[COND_END941:%.*]]
29518 // SIMD-ONLY0:       cond.false939:
29519 // SIMD-ONLY0-NEXT:    [[TMP389:%.*]] = load i8, ptr [[UCX]], align 1
29520 // SIMD-ONLY0-NEXT:    [[CONV940:%.*]] = zext i8 [[TMP389]] to i32
29521 // SIMD-ONLY0-NEXT:    br label [[COND_END941]]
29522 // SIMD-ONLY0:       cond.end941:
29523 // SIMD-ONLY0-NEXT:    [[COND942:%.*]] = phi i32 [ [[CONV938]], [[COND_TRUE937]] ], [ [[CONV940]], [[COND_FALSE939]] ]
29524 // SIMD-ONLY0-NEXT:    [[CONV943:%.*]] = trunc i32 [[COND942]] to i8
29525 // SIMD-ONLY0-NEXT:    store i8 [[CONV943]], ptr [[UCX]], align 1
29526 // SIMD-ONLY0-NEXT:    [[TMP390:%.*]] = load i8, ptr [[UCE]], align 1
29527 // SIMD-ONLY0-NEXT:    [[CONV944:%.*]] = zext i8 [[TMP390]] to i32
29528 // SIMD-ONLY0-NEXT:    [[TMP391:%.*]] = load i8, ptr [[UCX]], align 1
29529 // SIMD-ONLY0-NEXT:    [[CONV945:%.*]] = zext i8 [[TMP391]] to i32
29530 // SIMD-ONLY0-NEXT:    [[CMP946:%.*]] = icmp slt i32 [[CONV944]], [[CONV945]]
29531 // SIMD-ONLY0-NEXT:    br i1 [[CMP946]], label [[COND_TRUE948:%.*]], label [[COND_FALSE950:%.*]]
29532 // SIMD-ONLY0:       cond.true948:
29533 // SIMD-ONLY0-NEXT:    [[TMP392:%.*]] = load i8, ptr [[UCE]], align 1
29534 // SIMD-ONLY0-NEXT:    [[CONV949:%.*]] = zext i8 [[TMP392]] to i32
29535 // SIMD-ONLY0-NEXT:    br label [[COND_END952:%.*]]
29536 // SIMD-ONLY0:       cond.false950:
29537 // SIMD-ONLY0-NEXT:    [[TMP393:%.*]] = load i8, ptr [[UCX]], align 1
29538 // SIMD-ONLY0-NEXT:    [[CONV951:%.*]] = zext i8 [[TMP393]] to i32
29539 // SIMD-ONLY0-NEXT:    br label [[COND_END952]]
29540 // SIMD-ONLY0:       cond.end952:
29541 // SIMD-ONLY0-NEXT:    [[COND953:%.*]] = phi i32 [ [[CONV949]], [[COND_TRUE948]] ], [ [[CONV951]], [[COND_FALSE950]] ]
29542 // SIMD-ONLY0-NEXT:    [[CONV954:%.*]] = trunc i32 [[COND953]] to i8
29543 // SIMD-ONLY0-NEXT:    store i8 [[CONV954]], ptr [[UCX]], align 1
29544 // SIMD-ONLY0-NEXT:    [[TMP394:%.*]] = load i8, ptr [[UCX]], align 1
29545 // SIMD-ONLY0-NEXT:    [[CONV955:%.*]] = zext i8 [[TMP394]] to i32
29546 // SIMD-ONLY0-NEXT:    [[TMP395:%.*]] = load i8, ptr [[UCE]], align 1
29547 // SIMD-ONLY0-NEXT:    [[CONV956:%.*]] = zext i8 [[TMP395]] to i32
29548 // SIMD-ONLY0-NEXT:    [[CMP957:%.*]] = icmp sgt i32 [[CONV955]], [[CONV956]]
29549 // SIMD-ONLY0-NEXT:    br i1 [[CMP957]], label [[IF_THEN959:%.*]], label [[IF_END960:%.*]]
29550 // SIMD-ONLY0:       if.then959:
29551 // SIMD-ONLY0-NEXT:    [[TMP396:%.*]] = load i8, ptr [[UCE]], align 1
29552 // SIMD-ONLY0-NEXT:    store i8 [[TMP396]], ptr [[UCX]], align 1
29553 // SIMD-ONLY0-NEXT:    br label [[IF_END960]]
29554 // SIMD-ONLY0:       if.end960:
29555 // SIMD-ONLY0-NEXT:    [[TMP397:%.*]] = load i8, ptr [[UCX]], align 1
29556 // SIMD-ONLY0-NEXT:    [[CONV961:%.*]] = zext i8 [[TMP397]] to i32
29557 // SIMD-ONLY0-NEXT:    [[TMP398:%.*]] = load i8, ptr [[UCE]], align 1
29558 // SIMD-ONLY0-NEXT:    [[CONV962:%.*]] = zext i8 [[TMP398]] to i32
29559 // SIMD-ONLY0-NEXT:    [[CMP963:%.*]] = icmp slt i32 [[CONV961]], [[CONV962]]
29560 // SIMD-ONLY0-NEXT:    br i1 [[CMP963]], label [[IF_THEN965:%.*]], label [[IF_END966:%.*]]
29561 // SIMD-ONLY0:       if.then965:
29562 // SIMD-ONLY0-NEXT:    [[TMP399:%.*]] = load i8, ptr [[UCE]], align 1
29563 // SIMD-ONLY0-NEXT:    store i8 [[TMP399]], ptr [[UCX]], align 1
29564 // SIMD-ONLY0-NEXT:    br label [[IF_END966]]
29565 // SIMD-ONLY0:       if.end966:
29566 // SIMD-ONLY0-NEXT:    [[TMP400:%.*]] = load i8, ptr [[UCE]], align 1
29567 // SIMD-ONLY0-NEXT:    [[CONV967:%.*]] = zext i8 [[TMP400]] to i32
29568 // SIMD-ONLY0-NEXT:    [[TMP401:%.*]] = load i8, ptr [[UCX]], align 1
29569 // SIMD-ONLY0-NEXT:    [[CONV968:%.*]] = zext i8 [[TMP401]] to i32
29570 // SIMD-ONLY0-NEXT:    [[CMP969:%.*]] = icmp sgt i32 [[CONV967]], [[CONV968]]
29571 // SIMD-ONLY0-NEXT:    br i1 [[CMP969]], label [[IF_THEN971:%.*]], label [[IF_END972:%.*]]
29572 // SIMD-ONLY0:       if.then971:
29573 // SIMD-ONLY0-NEXT:    [[TMP402:%.*]] = load i8, ptr [[UCE]], align 1
29574 // SIMD-ONLY0-NEXT:    store i8 [[TMP402]], ptr [[UCX]], align 1
29575 // SIMD-ONLY0-NEXT:    br label [[IF_END972]]
29576 // SIMD-ONLY0:       if.end972:
29577 // SIMD-ONLY0-NEXT:    [[TMP403:%.*]] = load i8, ptr [[UCE]], align 1
29578 // SIMD-ONLY0-NEXT:    [[CONV973:%.*]] = zext i8 [[TMP403]] to i32
29579 // SIMD-ONLY0-NEXT:    [[TMP404:%.*]] = load i8, ptr [[UCX]], align 1
29580 // SIMD-ONLY0-NEXT:    [[CONV974:%.*]] = zext i8 [[TMP404]] to i32
29581 // SIMD-ONLY0-NEXT:    [[CMP975:%.*]] = icmp slt i32 [[CONV973]], [[CONV974]]
29582 // SIMD-ONLY0-NEXT:    br i1 [[CMP975]], label [[IF_THEN977:%.*]], label [[IF_END978:%.*]]
29583 // SIMD-ONLY0:       if.then977:
29584 // SIMD-ONLY0-NEXT:    [[TMP405:%.*]] = load i8, ptr [[UCE]], align 1
29585 // SIMD-ONLY0-NEXT:    store i8 [[TMP405]], ptr [[UCX]], align 1
29586 // SIMD-ONLY0-NEXT:    br label [[IF_END978]]
29587 // SIMD-ONLY0:       if.end978:
29588 // SIMD-ONLY0-NEXT:    [[TMP406:%.*]] = load i8, ptr [[UCX]], align 1
29589 // SIMD-ONLY0-NEXT:    [[CONV979:%.*]] = zext i8 [[TMP406]] to i32
29590 // SIMD-ONLY0-NEXT:    [[TMP407:%.*]] = load i8, ptr [[UCE]], align 1
29591 // SIMD-ONLY0-NEXT:    [[CONV980:%.*]] = zext i8 [[TMP407]] to i32
29592 // SIMD-ONLY0-NEXT:    [[CMP981:%.*]] = icmp eq i32 [[CONV979]], [[CONV980]]
29593 // SIMD-ONLY0-NEXT:    br i1 [[CMP981]], label [[COND_TRUE983:%.*]], label [[COND_FALSE985:%.*]]
29594 // SIMD-ONLY0:       cond.true983:
29595 // SIMD-ONLY0-NEXT:    [[TMP408:%.*]] = load i8, ptr [[UCD]], align 1
29596 // SIMD-ONLY0-NEXT:    [[CONV984:%.*]] = zext i8 [[TMP408]] to i32
29597 // SIMD-ONLY0-NEXT:    br label [[COND_END987:%.*]]
29598 // SIMD-ONLY0:       cond.false985:
29599 // SIMD-ONLY0-NEXT:    [[TMP409:%.*]] = load i8, ptr [[UCX]], align 1
29600 // SIMD-ONLY0-NEXT:    [[CONV986:%.*]] = zext i8 [[TMP409]] to i32
29601 // SIMD-ONLY0-NEXT:    br label [[COND_END987]]
29602 // SIMD-ONLY0:       cond.end987:
29603 // SIMD-ONLY0-NEXT:    [[COND988:%.*]] = phi i32 [ [[CONV984]], [[COND_TRUE983]] ], [ [[CONV986]], [[COND_FALSE985]] ]
29604 // SIMD-ONLY0-NEXT:    [[CONV989:%.*]] = trunc i32 [[COND988]] to i8
29605 // SIMD-ONLY0-NEXT:    store i8 [[CONV989]], ptr [[UCX]], align 1
29606 // SIMD-ONLY0-NEXT:    [[TMP410:%.*]] = load i8, ptr [[UCE]], align 1
29607 // SIMD-ONLY0-NEXT:    [[CONV990:%.*]] = zext i8 [[TMP410]] to i32
29608 // SIMD-ONLY0-NEXT:    [[TMP411:%.*]] = load i8, ptr [[UCX]], align 1
29609 // SIMD-ONLY0-NEXT:    [[CONV991:%.*]] = zext i8 [[TMP411]] to i32
29610 // SIMD-ONLY0-NEXT:    [[CMP992:%.*]] = icmp eq i32 [[CONV990]], [[CONV991]]
29611 // SIMD-ONLY0-NEXT:    br i1 [[CMP992]], label [[COND_TRUE994:%.*]], label [[COND_FALSE996:%.*]]
29612 // SIMD-ONLY0:       cond.true994:
29613 // SIMD-ONLY0-NEXT:    [[TMP412:%.*]] = load i8, ptr [[UCD]], align 1
29614 // SIMD-ONLY0-NEXT:    [[CONV995:%.*]] = zext i8 [[TMP412]] to i32
29615 // SIMD-ONLY0-NEXT:    br label [[COND_END998:%.*]]
29616 // SIMD-ONLY0:       cond.false996:
29617 // SIMD-ONLY0-NEXT:    [[TMP413:%.*]] = load i8, ptr [[UCX]], align 1
29618 // SIMD-ONLY0-NEXT:    [[CONV997:%.*]] = zext i8 [[TMP413]] to i32
29619 // SIMD-ONLY0-NEXT:    br label [[COND_END998]]
29620 // SIMD-ONLY0:       cond.end998:
29621 // SIMD-ONLY0-NEXT:    [[COND999:%.*]] = phi i32 [ [[CONV995]], [[COND_TRUE994]] ], [ [[CONV997]], [[COND_FALSE996]] ]
29622 // SIMD-ONLY0-NEXT:    [[CONV1000:%.*]] = trunc i32 [[COND999]] to i8
29623 // SIMD-ONLY0-NEXT:    store i8 [[CONV1000]], ptr [[UCX]], align 1
29624 // SIMD-ONLY0-NEXT:    [[TMP414:%.*]] = load i8, ptr [[UCX]], align 1
29625 // SIMD-ONLY0-NEXT:    [[CONV1001:%.*]] = zext i8 [[TMP414]] to i32
29626 // SIMD-ONLY0-NEXT:    [[TMP415:%.*]] = load i8, ptr [[UCE]], align 1
29627 // SIMD-ONLY0-NEXT:    [[CONV1002:%.*]] = zext i8 [[TMP415]] to i32
29628 // SIMD-ONLY0-NEXT:    [[CMP1003:%.*]] = icmp eq i32 [[CONV1001]], [[CONV1002]]
29629 // SIMD-ONLY0-NEXT:    br i1 [[CMP1003]], label [[IF_THEN1005:%.*]], label [[IF_END1006:%.*]]
29630 // SIMD-ONLY0:       if.then1005:
29631 // SIMD-ONLY0-NEXT:    [[TMP416:%.*]] = load i8, ptr [[UCD]], align 1
29632 // SIMD-ONLY0-NEXT:    store i8 [[TMP416]], ptr [[UCX]], align 1
29633 // SIMD-ONLY0-NEXT:    br label [[IF_END1006]]
29634 // SIMD-ONLY0:       if.end1006:
29635 // SIMD-ONLY0-NEXT:    [[TMP417:%.*]] = load i8, ptr [[UCE]], align 1
29636 // SIMD-ONLY0-NEXT:    [[CONV1007:%.*]] = zext i8 [[TMP417]] to i32
29637 // SIMD-ONLY0-NEXT:    [[TMP418:%.*]] = load i8, ptr [[UCX]], align 1
29638 // SIMD-ONLY0-NEXT:    [[CONV1008:%.*]] = zext i8 [[TMP418]] to i32
29639 // SIMD-ONLY0-NEXT:    [[CMP1009:%.*]] = icmp eq i32 [[CONV1007]], [[CONV1008]]
29640 // SIMD-ONLY0-NEXT:    br i1 [[CMP1009]], label [[IF_THEN1011:%.*]], label [[IF_END1012:%.*]]
29641 // SIMD-ONLY0:       if.then1011:
29642 // SIMD-ONLY0-NEXT:    [[TMP419:%.*]] = load i8, ptr [[UCD]], align 1
29643 // SIMD-ONLY0-NEXT:    store i8 [[TMP419]], ptr [[UCX]], align 1
29644 // SIMD-ONLY0-NEXT:    br label [[IF_END1012]]
29645 // SIMD-ONLY0:       if.end1012:
29646 // SIMD-ONLY0-NEXT:    [[TMP420:%.*]] = load i8, ptr [[CX]], align 1
29647 // SIMD-ONLY0-NEXT:    [[CONV1013:%.*]] = sext i8 [[TMP420]] to i32
29648 // SIMD-ONLY0-NEXT:    [[TMP421:%.*]] = load i8, ptr [[CE]], align 1
29649 // SIMD-ONLY0-NEXT:    [[CONV1014:%.*]] = sext i8 [[TMP421]] to i32
29650 // SIMD-ONLY0-NEXT:    [[CMP1015:%.*]] = icmp sgt i32 [[CONV1013]], [[CONV1014]]
29651 // SIMD-ONLY0-NEXT:    br i1 [[CMP1015]], label [[COND_TRUE1017:%.*]], label [[COND_FALSE1019:%.*]]
29652 // SIMD-ONLY0:       cond.true1017:
29653 // SIMD-ONLY0-NEXT:    [[TMP422:%.*]] = load i8, ptr [[CE]], align 1
29654 // SIMD-ONLY0-NEXT:    [[CONV1018:%.*]] = sext i8 [[TMP422]] to i32
29655 // SIMD-ONLY0-NEXT:    br label [[COND_END1021:%.*]]
29656 // SIMD-ONLY0:       cond.false1019:
29657 // SIMD-ONLY0-NEXT:    [[TMP423:%.*]] = load i8, ptr [[CX]], align 1
29658 // SIMD-ONLY0-NEXT:    [[CONV1020:%.*]] = sext i8 [[TMP423]] to i32
29659 // SIMD-ONLY0-NEXT:    br label [[COND_END1021]]
29660 // SIMD-ONLY0:       cond.end1021:
29661 // SIMD-ONLY0-NEXT:    [[COND1022:%.*]] = phi i32 [ [[CONV1018]], [[COND_TRUE1017]] ], [ [[CONV1020]], [[COND_FALSE1019]] ]
29662 // SIMD-ONLY0-NEXT:    [[CONV1023:%.*]] = trunc i32 [[COND1022]] to i8
29663 // SIMD-ONLY0-NEXT:    store i8 [[CONV1023]], ptr [[CX]], align 1
29664 // SIMD-ONLY0-NEXT:    [[TMP424:%.*]] = load i8, ptr [[CX]], align 1
29665 // SIMD-ONLY0-NEXT:    [[CONV1024:%.*]] = sext i8 [[TMP424]] to i32
29666 // SIMD-ONLY0-NEXT:    [[TMP425:%.*]] = load i8, ptr [[CE]], align 1
29667 // SIMD-ONLY0-NEXT:    [[CONV1025:%.*]] = sext i8 [[TMP425]] to i32
29668 // SIMD-ONLY0-NEXT:    [[CMP1026:%.*]] = icmp slt i32 [[CONV1024]], [[CONV1025]]
29669 // SIMD-ONLY0-NEXT:    br i1 [[CMP1026]], label [[COND_TRUE1028:%.*]], label [[COND_FALSE1030:%.*]]
29670 // SIMD-ONLY0:       cond.true1028:
29671 // SIMD-ONLY0-NEXT:    [[TMP426:%.*]] = load i8, ptr [[CE]], align 1
29672 // SIMD-ONLY0-NEXT:    [[CONV1029:%.*]] = sext i8 [[TMP426]] to i32
29673 // SIMD-ONLY0-NEXT:    br label [[COND_END1032:%.*]]
29674 // SIMD-ONLY0:       cond.false1030:
29675 // SIMD-ONLY0-NEXT:    [[TMP427:%.*]] = load i8, ptr [[CX]], align 1
29676 // SIMD-ONLY0-NEXT:    [[CONV1031:%.*]] = sext i8 [[TMP427]] to i32
29677 // SIMD-ONLY0-NEXT:    br label [[COND_END1032]]
29678 // SIMD-ONLY0:       cond.end1032:
29679 // SIMD-ONLY0-NEXT:    [[COND1033:%.*]] = phi i32 [ [[CONV1029]], [[COND_TRUE1028]] ], [ [[CONV1031]], [[COND_FALSE1030]] ]
29680 // SIMD-ONLY0-NEXT:    [[CONV1034:%.*]] = trunc i32 [[COND1033]] to i8
29681 // SIMD-ONLY0-NEXT:    store i8 [[CONV1034]], ptr [[CX]], align 1
29682 // SIMD-ONLY0-NEXT:    [[TMP428:%.*]] = load i8, ptr [[CE]], align 1
29683 // SIMD-ONLY0-NEXT:    [[CONV1035:%.*]] = sext i8 [[TMP428]] to i32
29684 // SIMD-ONLY0-NEXT:    [[TMP429:%.*]] = load i8, ptr [[CX]], align 1
29685 // SIMD-ONLY0-NEXT:    [[CONV1036:%.*]] = sext i8 [[TMP429]] to i32
29686 // SIMD-ONLY0-NEXT:    [[CMP1037:%.*]] = icmp sgt i32 [[CONV1035]], [[CONV1036]]
29687 // SIMD-ONLY0-NEXT:    br i1 [[CMP1037]], label [[COND_TRUE1039:%.*]], label [[COND_FALSE1041:%.*]]
29688 // SIMD-ONLY0:       cond.true1039:
29689 // SIMD-ONLY0-NEXT:    [[TMP430:%.*]] = load i8, ptr [[CE]], align 1
29690 // SIMD-ONLY0-NEXT:    [[CONV1040:%.*]] = sext i8 [[TMP430]] to i32
29691 // SIMD-ONLY0-NEXT:    br label [[COND_END1043:%.*]]
29692 // SIMD-ONLY0:       cond.false1041:
29693 // SIMD-ONLY0-NEXT:    [[TMP431:%.*]] = load i8, ptr [[CX]], align 1
29694 // SIMD-ONLY0-NEXT:    [[CONV1042:%.*]] = sext i8 [[TMP431]] to i32
29695 // SIMD-ONLY0-NEXT:    br label [[COND_END1043]]
29696 // SIMD-ONLY0:       cond.end1043:
29697 // SIMD-ONLY0-NEXT:    [[COND1044:%.*]] = phi i32 [ [[CONV1040]], [[COND_TRUE1039]] ], [ [[CONV1042]], [[COND_FALSE1041]] ]
29698 // SIMD-ONLY0-NEXT:    [[CONV1045:%.*]] = trunc i32 [[COND1044]] to i8
29699 // SIMD-ONLY0-NEXT:    store i8 [[CONV1045]], ptr [[CX]], align 1
29700 // SIMD-ONLY0-NEXT:    [[TMP432:%.*]] = load i8, ptr [[CE]], align 1
29701 // SIMD-ONLY0-NEXT:    [[CONV1046:%.*]] = sext i8 [[TMP432]] to i32
29702 // SIMD-ONLY0-NEXT:    [[TMP433:%.*]] = load i8, ptr [[CX]], align 1
29703 // SIMD-ONLY0-NEXT:    [[CONV1047:%.*]] = sext i8 [[TMP433]] to i32
29704 // SIMD-ONLY0-NEXT:    [[CMP1048:%.*]] = icmp slt i32 [[CONV1046]], [[CONV1047]]
29705 // SIMD-ONLY0-NEXT:    br i1 [[CMP1048]], label [[COND_TRUE1050:%.*]], label [[COND_FALSE1052:%.*]]
29706 // SIMD-ONLY0:       cond.true1050:
29707 // SIMD-ONLY0-NEXT:    [[TMP434:%.*]] = load i8, ptr [[CE]], align 1
29708 // SIMD-ONLY0-NEXT:    [[CONV1051:%.*]] = sext i8 [[TMP434]] to i32
29709 // SIMD-ONLY0-NEXT:    br label [[COND_END1054:%.*]]
29710 // SIMD-ONLY0:       cond.false1052:
29711 // SIMD-ONLY0-NEXT:    [[TMP435:%.*]] = load i8, ptr [[CX]], align 1
29712 // SIMD-ONLY0-NEXT:    [[CONV1053:%.*]] = sext i8 [[TMP435]] to i32
29713 // SIMD-ONLY0-NEXT:    br label [[COND_END1054]]
29714 // SIMD-ONLY0:       cond.end1054:
29715 // SIMD-ONLY0-NEXT:    [[COND1055:%.*]] = phi i32 [ [[CONV1051]], [[COND_TRUE1050]] ], [ [[CONV1053]], [[COND_FALSE1052]] ]
29716 // SIMD-ONLY0-NEXT:    [[CONV1056:%.*]] = trunc i32 [[COND1055]] to i8
29717 // SIMD-ONLY0-NEXT:    store i8 [[CONV1056]], ptr [[CX]], align 1
29718 // SIMD-ONLY0-NEXT:    [[TMP436:%.*]] = load i8, ptr [[CX]], align 1
29719 // SIMD-ONLY0-NEXT:    [[CONV1057:%.*]] = sext i8 [[TMP436]] to i32
29720 // SIMD-ONLY0-NEXT:    [[TMP437:%.*]] = load i8, ptr [[CE]], align 1
29721 // SIMD-ONLY0-NEXT:    [[CONV1058:%.*]] = sext i8 [[TMP437]] to i32
29722 // SIMD-ONLY0-NEXT:    [[CMP1059:%.*]] = icmp sgt i32 [[CONV1057]], [[CONV1058]]
29723 // SIMD-ONLY0-NEXT:    br i1 [[CMP1059]], label [[IF_THEN1061:%.*]], label [[IF_END1062:%.*]]
29724 // SIMD-ONLY0:       if.then1061:
29725 // SIMD-ONLY0-NEXT:    [[TMP438:%.*]] = load i8, ptr [[CE]], align 1
29726 // SIMD-ONLY0-NEXT:    store i8 [[TMP438]], ptr [[CX]], align 1
29727 // SIMD-ONLY0-NEXT:    br label [[IF_END1062]]
29728 // SIMD-ONLY0:       if.end1062:
29729 // SIMD-ONLY0-NEXT:    [[TMP439:%.*]] = load i8, ptr [[CX]], align 1
29730 // SIMD-ONLY0-NEXT:    [[CONV1063:%.*]] = sext i8 [[TMP439]] to i32
29731 // SIMD-ONLY0-NEXT:    [[TMP440:%.*]] = load i8, ptr [[CE]], align 1
29732 // SIMD-ONLY0-NEXT:    [[CONV1064:%.*]] = sext i8 [[TMP440]] to i32
29733 // SIMD-ONLY0-NEXT:    [[CMP1065:%.*]] = icmp slt i32 [[CONV1063]], [[CONV1064]]
29734 // SIMD-ONLY0-NEXT:    br i1 [[CMP1065]], label [[IF_THEN1067:%.*]], label [[IF_END1068:%.*]]
29735 // SIMD-ONLY0:       if.then1067:
29736 // SIMD-ONLY0-NEXT:    [[TMP441:%.*]] = load i8, ptr [[CE]], align 1
29737 // SIMD-ONLY0-NEXT:    store i8 [[TMP441]], ptr [[CX]], align 1
29738 // SIMD-ONLY0-NEXT:    br label [[IF_END1068]]
29739 // SIMD-ONLY0:       if.end1068:
29740 // SIMD-ONLY0-NEXT:    [[TMP442:%.*]] = load i8, ptr [[CE]], align 1
29741 // SIMD-ONLY0-NEXT:    [[CONV1069:%.*]] = sext i8 [[TMP442]] to i32
29742 // SIMD-ONLY0-NEXT:    [[TMP443:%.*]] = load i8, ptr [[CX]], align 1
29743 // SIMD-ONLY0-NEXT:    [[CONV1070:%.*]] = sext i8 [[TMP443]] to i32
29744 // SIMD-ONLY0-NEXT:    [[CMP1071:%.*]] = icmp sgt i32 [[CONV1069]], [[CONV1070]]
29745 // SIMD-ONLY0-NEXT:    br i1 [[CMP1071]], label [[IF_THEN1073:%.*]], label [[IF_END1074:%.*]]
29746 // SIMD-ONLY0:       if.then1073:
29747 // SIMD-ONLY0-NEXT:    [[TMP444:%.*]] = load i8, ptr [[CE]], align 1
29748 // SIMD-ONLY0-NEXT:    store i8 [[TMP444]], ptr [[CX]], align 1
29749 // SIMD-ONLY0-NEXT:    br label [[IF_END1074]]
29750 // SIMD-ONLY0:       if.end1074:
29751 // SIMD-ONLY0-NEXT:    [[TMP445:%.*]] = load i8, ptr [[CE]], align 1
29752 // SIMD-ONLY0-NEXT:    [[CONV1075:%.*]] = sext i8 [[TMP445]] to i32
29753 // SIMD-ONLY0-NEXT:    [[TMP446:%.*]] = load i8, ptr [[CX]], align 1
29754 // SIMD-ONLY0-NEXT:    [[CONV1076:%.*]] = sext i8 [[TMP446]] to i32
29755 // SIMD-ONLY0-NEXT:    [[CMP1077:%.*]] = icmp slt i32 [[CONV1075]], [[CONV1076]]
29756 // SIMD-ONLY0-NEXT:    br i1 [[CMP1077]], label [[IF_THEN1079:%.*]], label [[IF_END1080:%.*]]
29757 // SIMD-ONLY0:       if.then1079:
29758 // SIMD-ONLY0-NEXT:    [[TMP447:%.*]] = load i8, ptr [[CE]], align 1
29759 // SIMD-ONLY0-NEXT:    store i8 [[TMP447]], ptr [[CX]], align 1
29760 // SIMD-ONLY0-NEXT:    br label [[IF_END1080]]
29761 // SIMD-ONLY0:       if.end1080:
29762 // SIMD-ONLY0-NEXT:    [[TMP448:%.*]] = load i8, ptr [[CX]], align 1
29763 // SIMD-ONLY0-NEXT:    [[CONV1081:%.*]] = sext i8 [[TMP448]] to i32
29764 // SIMD-ONLY0-NEXT:    [[TMP449:%.*]] = load i8, ptr [[CE]], align 1
29765 // SIMD-ONLY0-NEXT:    [[CONV1082:%.*]] = sext i8 [[TMP449]] to i32
29766 // SIMD-ONLY0-NEXT:    [[CMP1083:%.*]] = icmp eq i32 [[CONV1081]], [[CONV1082]]
29767 // SIMD-ONLY0-NEXT:    br i1 [[CMP1083]], label [[COND_TRUE1085:%.*]], label [[COND_FALSE1087:%.*]]
29768 // SIMD-ONLY0:       cond.true1085:
29769 // SIMD-ONLY0-NEXT:    [[TMP450:%.*]] = load i8, ptr [[CD]], align 1
29770 // SIMD-ONLY0-NEXT:    [[CONV1086:%.*]] = sext i8 [[TMP450]] to i32
29771 // SIMD-ONLY0-NEXT:    br label [[COND_END1089:%.*]]
29772 // SIMD-ONLY0:       cond.false1087:
29773 // SIMD-ONLY0-NEXT:    [[TMP451:%.*]] = load i8, ptr [[CX]], align 1
29774 // SIMD-ONLY0-NEXT:    [[CONV1088:%.*]] = sext i8 [[TMP451]] to i32
29775 // SIMD-ONLY0-NEXT:    br label [[COND_END1089]]
29776 // SIMD-ONLY0:       cond.end1089:
29777 // SIMD-ONLY0-NEXT:    [[COND1090:%.*]] = phi i32 [ [[CONV1086]], [[COND_TRUE1085]] ], [ [[CONV1088]], [[COND_FALSE1087]] ]
29778 // SIMD-ONLY0-NEXT:    [[CONV1091:%.*]] = trunc i32 [[COND1090]] to i8
29779 // SIMD-ONLY0-NEXT:    store i8 [[CONV1091]], ptr [[CX]], align 1
29780 // SIMD-ONLY0-NEXT:    [[TMP452:%.*]] = load i8, ptr [[CE]], align 1
29781 // SIMD-ONLY0-NEXT:    [[CONV1092:%.*]] = sext i8 [[TMP452]] to i32
29782 // SIMD-ONLY0-NEXT:    [[TMP453:%.*]] = load i8, ptr [[CX]], align 1
29783 // SIMD-ONLY0-NEXT:    [[CONV1093:%.*]] = sext i8 [[TMP453]] to i32
29784 // SIMD-ONLY0-NEXT:    [[CMP1094:%.*]] = icmp eq i32 [[CONV1092]], [[CONV1093]]
29785 // SIMD-ONLY0-NEXT:    br i1 [[CMP1094]], label [[COND_TRUE1096:%.*]], label [[COND_FALSE1098:%.*]]
29786 // SIMD-ONLY0:       cond.true1096:
29787 // SIMD-ONLY0-NEXT:    [[TMP454:%.*]] = load i8, ptr [[CD]], align 1
29788 // SIMD-ONLY0-NEXT:    [[CONV1097:%.*]] = sext i8 [[TMP454]] to i32
29789 // SIMD-ONLY0-NEXT:    br label [[COND_END1100:%.*]]
29790 // SIMD-ONLY0:       cond.false1098:
29791 // SIMD-ONLY0-NEXT:    [[TMP455:%.*]] = load i8, ptr [[CX]], align 1
29792 // SIMD-ONLY0-NEXT:    [[CONV1099:%.*]] = sext i8 [[TMP455]] to i32
29793 // SIMD-ONLY0-NEXT:    br label [[COND_END1100]]
29794 // SIMD-ONLY0:       cond.end1100:
29795 // SIMD-ONLY0-NEXT:    [[COND1101:%.*]] = phi i32 [ [[CONV1097]], [[COND_TRUE1096]] ], [ [[CONV1099]], [[COND_FALSE1098]] ]
29796 // SIMD-ONLY0-NEXT:    [[CONV1102:%.*]] = trunc i32 [[COND1101]] to i8
29797 // SIMD-ONLY0-NEXT:    store i8 [[CONV1102]], ptr [[CX]], align 1
29798 // SIMD-ONLY0-NEXT:    [[TMP456:%.*]] = load i8, ptr [[CX]], align 1
29799 // SIMD-ONLY0-NEXT:    [[CONV1103:%.*]] = sext i8 [[TMP456]] to i32
29800 // SIMD-ONLY0-NEXT:    [[TMP457:%.*]] = load i8, ptr [[CE]], align 1
29801 // SIMD-ONLY0-NEXT:    [[CONV1104:%.*]] = sext i8 [[TMP457]] to i32
29802 // SIMD-ONLY0-NEXT:    [[CMP1105:%.*]] = icmp eq i32 [[CONV1103]], [[CONV1104]]
29803 // SIMD-ONLY0-NEXT:    br i1 [[CMP1105]], label [[IF_THEN1107:%.*]], label [[IF_END1108:%.*]]
29804 // SIMD-ONLY0:       if.then1107:
29805 // SIMD-ONLY0-NEXT:    [[TMP458:%.*]] = load i8, ptr [[CD]], align 1
29806 // SIMD-ONLY0-NEXT:    store i8 [[TMP458]], ptr [[CX]], align 1
29807 // SIMD-ONLY0-NEXT:    br label [[IF_END1108]]
29808 // SIMD-ONLY0:       if.end1108:
29809 // SIMD-ONLY0-NEXT:    [[TMP459:%.*]] = load i8, ptr [[CE]], align 1
29810 // SIMD-ONLY0-NEXT:    [[CONV1109:%.*]] = sext i8 [[TMP459]] to i32
29811 // SIMD-ONLY0-NEXT:    [[TMP460:%.*]] = load i8, ptr [[CX]], align 1
29812 // SIMD-ONLY0-NEXT:    [[CONV1110:%.*]] = sext i8 [[TMP460]] to i32
29813 // SIMD-ONLY0-NEXT:    [[CMP1111:%.*]] = icmp eq i32 [[CONV1109]], [[CONV1110]]
29814 // SIMD-ONLY0-NEXT:    br i1 [[CMP1111]], label [[IF_THEN1113:%.*]], label [[IF_END1114:%.*]]
29815 // SIMD-ONLY0:       if.then1113:
29816 // SIMD-ONLY0-NEXT:    [[TMP461:%.*]] = load i8, ptr [[CD]], align 1
29817 // SIMD-ONLY0-NEXT:    store i8 [[TMP461]], ptr [[CX]], align 1
29818 // SIMD-ONLY0-NEXT:    br label [[IF_END1114]]
29819 // SIMD-ONLY0:       if.end1114:
29820 // SIMD-ONLY0-NEXT:    [[TMP462:%.*]] = load i8, ptr [[UCX]], align 1
29821 // SIMD-ONLY0-NEXT:    [[CONV1115:%.*]] = zext i8 [[TMP462]] to i32
29822 // SIMD-ONLY0-NEXT:    [[TMP463:%.*]] = load i8, ptr [[UCE]], align 1
29823 // SIMD-ONLY0-NEXT:    [[CONV1116:%.*]] = zext i8 [[TMP463]] to i32
29824 // SIMD-ONLY0-NEXT:    [[CMP1117:%.*]] = icmp sgt i32 [[CONV1115]], [[CONV1116]]
29825 // SIMD-ONLY0-NEXT:    br i1 [[CMP1117]], label [[COND_TRUE1119:%.*]], label [[COND_FALSE1121:%.*]]
29826 // SIMD-ONLY0:       cond.true1119:
29827 // SIMD-ONLY0-NEXT:    [[TMP464:%.*]] = load i8, ptr [[UCE]], align 1
29828 // SIMD-ONLY0-NEXT:    [[CONV1120:%.*]] = zext i8 [[TMP464]] to i32
29829 // SIMD-ONLY0-NEXT:    br label [[COND_END1123:%.*]]
29830 // SIMD-ONLY0:       cond.false1121:
29831 // SIMD-ONLY0-NEXT:    [[TMP465:%.*]] = load i8, ptr [[UCX]], align 1
29832 // SIMD-ONLY0-NEXT:    [[CONV1122:%.*]] = zext i8 [[TMP465]] to i32
29833 // SIMD-ONLY0-NEXT:    br label [[COND_END1123]]
29834 // SIMD-ONLY0:       cond.end1123:
29835 // SIMD-ONLY0-NEXT:    [[COND1124:%.*]] = phi i32 [ [[CONV1120]], [[COND_TRUE1119]] ], [ [[CONV1122]], [[COND_FALSE1121]] ]
29836 // SIMD-ONLY0-NEXT:    [[CONV1125:%.*]] = trunc i32 [[COND1124]] to i8
29837 // SIMD-ONLY0-NEXT:    store i8 [[CONV1125]], ptr [[UCX]], align 1
29838 // SIMD-ONLY0-NEXT:    [[TMP466:%.*]] = load i8, ptr [[UCX]], align 1
29839 // SIMD-ONLY0-NEXT:    [[CONV1126:%.*]] = zext i8 [[TMP466]] to i32
29840 // SIMD-ONLY0-NEXT:    [[TMP467:%.*]] = load i8, ptr [[UCE]], align 1
29841 // SIMD-ONLY0-NEXT:    [[CONV1127:%.*]] = zext i8 [[TMP467]] to i32
29842 // SIMD-ONLY0-NEXT:    [[CMP1128:%.*]] = icmp slt i32 [[CONV1126]], [[CONV1127]]
29843 // SIMD-ONLY0-NEXT:    br i1 [[CMP1128]], label [[COND_TRUE1130:%.*]], label [[COND_FALSE1132:%.*]]
29844 // SIMD-ONLY0:       cond.true1130:
29845 // SIMD-ONLY0-NEXT:    [[TMP468:%.*]] = load i8, ptr [[UCE]], align 1
29846 // SIMD-ONLY0-NEXT:    [[CONV1131:%.*]] = zext i8 [[TMP468]] to i32
29847 // SIMD-ONLY0-NEXT:    br label [[COND_END1134:%.*]]
29848 // SIMD-ONLY0:       cond.false1132:
29849 // SIMD-ONLY0-NEXT:    [[TMP469:%.*]] = load i8, ptr [[UCX]], align 1
29850 // SIMD-ONLY0-NEXT:    [[CONV1133:%.*]] = zext i8 [[TMP469]] to i32
29851 // SIMD-ONLY0-NEXT:    br label [[COND_END1134]]
29852 // SIMD-ONLY0:       cond.end1134:
29853 // SIMD-ONLY0-NEXT:    [[COND1135:%.*]] = phi i32 [ [[CONV1131]], [[COND_TRUE1130]] ], [ [[CONV1133]], [[COND_FALSE1132]] ]
29854 // SIMD-ONLY0-NEXT:    [[CONV1136:%.*]] = trunc i32 [[COND1135]] to i8
29855 // SIMD-ONLY0-NEXT:    store i8 [[CONV1136]], ptr [[UCX]], align 1
29856 // SIMD-ONLY0-NEXT:    [[TMP470:%.*]] = load i8, ptr [[UCE]], align 1
29857 // SIMD-ONLY0-NEXT:    [[CONV1137:%.*]] = zext i8 [[TMP470]] to i32
29858 // SIMD-ONLY0-NEXT:    [[TMP471:%.*]] = load i8, ptr [[UCX]], align 1
29859 // SIMD-ONLY0-NEXT:    [[CONV1138:%.*]] = zext i8 [[TMP471]] to i32
29860 // SIMD-ONLY0-NEXT:    [[CMP1139:%.*]] = icmp sgt i32 [[CONV1137]], [[CONV1138]]
29861 // SIMD-ONLY0-NEXT:    br i1 [[CMP1139]], label [[COND_TRUE1141:%.*]], label [[COND_FALSE1143:%.*]]
29862 // SIMD-ONLY0:       cond.true1141:
29863 // SIMD-ONLY0-NEXT:    [[TMP472:%.*]] = load i8, ptr [[UCE]], align 1
29864 // SIMD-ONLY0-NEXT:    [[CONV1142:%.*]] = zext i8 [[TMP472]] to i32
29865 // SIMD-ONLY0-NEXT:    br label [[COND_END1145:%.*]]
29866 // SIMD-ONLY0:       cond.false1143:
29867 // SIMD-ONLY0-NEXT:    [[TMP473:%.*]] = load i8, ptr [[UCX]], align 1
29868 // SIMD-ONLY0-NEXT:    [[CONV1144:%.*]] = zext i8 [[TMP473]] to i32
29869 // SIMD-ONLY0-NEXT:    br label [[COND_END1145]]
29870 // SIMD-ONLY0:       cond.end1145:
29871 // SIMD-ONLY0-NEXT:    [[COND1146:%.*]] = phi i32 [ [[CONV1142]], [[COND_TRUE1141]] ], [ [[CONV1144]], [[COND_FALSE1143]] ]
29872 // SIMD-ONLY0-NEXT:    [[CONV1147:%.*]] = trunc i32 [[COND1146]] to i8
29873 // SIMD-ONLY0-NEXT:    store i8 [[CONV1147]], ptr [[UCX]], align 1
29874 // SIMD-ONLY0-NEXT:    [[TMP474:%.*]] = load i8, ptr [[UCE]], align 1
29875 // SIMD-ONLY0-NEXT:    [[CONV1148:%.*]] = zext i8 [[TMP474]] to i32
29876 // SIMD-ONLY0-NEXT:    [[TMP475:%.*]] = load i8, ptr [[UCX]], align 1
29877 // SIMD-ONLY0-NEXT:    [[CONV1149:%.*]] = zext i8 [[TMP475]] to i32
29878 // SIMD-ONLY0-NEXT:    [[CMP1150:%.*]] = icmp slt i32 [[CONV1148]], [[CONV1149]]
29879 // SIMD-ONLY0-NEXT:    br i1 [[CMP1150]], label [[COND_TRUE1152:%.*]], label [[COND_FALSE1154:%.*]]
29880 // SIMD-ONLY0:       cond.true1152:
29881 // SIMD-ONLY0-NEXT:    [[TMP476:%.*]] = load i8, ptr [[UCE]], align 1
29882 // SIMD-ONLY0-NEXT:    [[CONV1153:%.*]] = zext i8 [[TMP476]] to i32
29883 // SIMD-ONLY0-NEXT:    br label [[COND_END1156:%.*]]
29884 // SIMD-ONLY0:       cond.false1154:
29885 // SIMD-ONLY0-NEXT:    [[TMP477:%.*]] = load i8, ptr [[UCX]], align 1
29886 // SIMD-ONLY0-NEXT:    [[CONV1155:%.*]] = zext i8 [[TMP477]] to i32
29887 // SIMD-ONLY0-NEXT:    br label [[COND_END1156]]
29888 // SIMD-ONLY0:       cond.end1156:
29889 // SIMD-ONLY0-NEXT:    [[COND1157:%.*]] = phi i32 [ [[CONV1153]], [[COND_TRUE1152]] ], [ [[CONV1155]], [[COND_FALSE1154]] ]
29890 // SIMD-ONLY0-NEXT:    [[CONV1158:%.*]] = trunc i32 [[COND1157]] to i8
29891 // SIMD-ONLY0-NEXT:    store i8 [[CONV1158]], ptr [[UCX]], align 1
29892 // SIMD-ONLY0-NEXT:    [[TMP478:%.*]] = load i8, ptr [[UCX]], align 1
29893 // SIMD-ONLY0-NEXT:    [[CONV1159:%.*]] = zext i8 [[TMP478]] to i32
29894 // SIMD-ONLY0-NEXT:    [[TMP479:%.*]] = load i8, ptr [[UCE]], align 1
29895 // SIMD-ONLY0-NEXT:    [[CONV1160:%.*]] = zext i8 [[TMP479]] to i32
29896 // SIMD-ONLY0-NEXT:    [[CMP1161:%.*]] = icmp sgt i32 [[CONV1159]], [[CONV1160]]
29897 // SIMD-ONLY0-NEXT:    br i1 [[CMP1161]], label [[IF_THEN1163:%.*]], label [[IF_END1164:%.*]]
29898 // SIMD-ONLY0:       if.then1163:
29899 // SIMD-ONLY0-NEXT:    [[TMP480:%.*]] = load i8, ptr [[UCE]], align 1
29900 // SIMD-ONLY0-NEXT:    store i8 [[TMP480]], ptr [[UCX]], align 1
29901 // SIMD-ONLY0-NEXT:    br label [[IF_END1164]]
29902 // SIMD-ONLY0:       if.end1164:
29903 // SIMD-ONLY0-NEXT:    [[TMP481:%.*]] = load i8, ptr [[UCX]], align 1
29904 // SIMD-ONLY0-NEXT:    [[CONV1165:%.*]] = zext i8 [[TMP481]] to i32
29905 // SIMD-ONLY0-NEXT:    [[TMP482:%.*]] = load i8, ptr [[UCE]], align 1
29906 // SIMD-ONLY0-NEXT:    [[CONV1166:%.*]] = zext i8 [[TMP482]] to i32
29907 // SIMD-ONLY0-NEXT:    [[CMP1167:%.*]] = icmp slt i32 [[CONV1165]], [[CONV1166]]
29908 // SIMD-ONLY0-NEXT:    br i1 [[CMP1167]], label [[IF_THEN1169:%.*]], label [[IF_END1170:%.*]]
29909 // SIMD-ONLY0:       if.then1169:
29910 // SIMD-ONLY0-NEXT:    [[TMP483:%.*]] = load i8, ptr [[UCE]], align 1
29911 // SIMD-ONLY0-NEXT:    store i8 [[TMP483]], ptr [[UCX]], align 1
29912 // SIMD-ONLY0-NEXT:    br label [[IF_END1170]]
29913 // SIMD-ONLY0:       if.end1170:
29914 // SIMD-ONLY0-NEXT:    [[TMP484:%.*]] = load i8, ptr [[UCE]], align 1
29915 // SIMD-ONLY0-NEXT:    [[CONV1171:%.*]] = zext i8 [[TMP484]] to i32
29916 // SIMD-ONLY0-NEXT:    [[TMP485:%.*]] = load i8, ptr [[UCX]], align 1
29917 // SIMD-ONLY0-NEXT:    [[CONV1172:%.*]] = zext i8 [[TMP485]] to i32
29918 // SIMD-ONLY0-NEXT:    [[CMP1173:%.*]] = icmp sgt i32 [[CONV1171]], [[CONV1172]]
29919 // SIMD-ONLY0-NEXT:    br i1 [[CMP1173]], label [[IF_THEN1175:%.*]], label [[IF_END1176:%.*]]
29920 // SIMD-ONLY0:       if.then1175:
29921 // SIMD-ONLY0-NEXT:    [[TMP486:%.*]] = load i8, ptr [[UCE]], align 1
29922 // SIMD-ONLY0-NEXT:    store i8 [[TMP486]], ptr [[UCX]], align 1
29923 // SIMD-ONLY0-NEXT:    br label [[IF_END1176]]
29924 // SIMD-ONLY0:       if.end1176:
29925 // SIMD-ONLY0-NEXT:    [[TMP487:%.*]] = load i8, ptr [[UCE]], align 1
29926 // SIMD-ONLY0-NEXT:    [[CONV1177:%.*]] = zext i8 [[TMP487]] to i32
29927 // SIMD-ONLY0-NEXT:    [[TMP488:%.*]] = load i8, ptr [[UCX]], align 1
29928 // SIMD-ONLY0-NEXT:    [[CONV1178:%.*]] = zext i8 [[TMP488]] to i32
29929 // SIMD-ONLY0-NEXT:    [[CMP1179:%.*]] = icmp slt i32 [[CONV1177]], [[CONV1178]]
29930 // SIMD-ONLY0-NEXT:    br i1 [[CMP1179]], label [[IF_THEN1181:%.*]], label [[IF_END1182:%.*]]
29931 // SIMD-ONLY0:       if.then1181:
29932 // SIMD-ONLY0-NEXT:    [[TMP489:%.*]] = load i8, ptr [[UCE]], align 1
29933 // SIMD-ONLY0-NEXT:    store i8 [[TMP489]], ptr [[UCX]], align 1
29934 // SIMD-ONLY0-NEXT:    br label [[IF_END1182]]
29935 // SIMD-ONLY0:       if.end1182:
29936 // SIMD-ONLY0-NEXT:    [[TMP490:%.*]] = load i8, ptr [[UCX]], align 1
29937 // SIMD-ONLY0-NEXT:    [[CONV1183:%.*]] = zext i8 [[TMP490]] to i32
29938 // SIMD-ONLY0-NEXT:    [[TMP491:%.*]] = load i8, ptr [[UCE]], align 1
29939 // SIMD-ONLY0-NEXT:    [[CONV1184:%.*]] = zext i8 [[TMP491]] to i32
29940 // SIMD-ONLY0-NEXT:    [[CMP1185:%.*]] = icmp eq i32 [[CONV1183]], [[CONV1184]]
29941 // SIMD-ONLY0-NEXT:    br i1 [[CMP1185]], label [[COND_TRUE1187:%.*]], label [[COND_FALSE1189:%.*]]
29942 // SIMD-ONLY0:       cond.true1187:
29943 // SIMD-ONLY0-NEXT:    [[TMP492:%.*]] = load i8, ptr [[UCD]], align 1
29944 // SIMD-ONLY0-NEXT:    [[CONV1188:%.*]] = zext i8 [[TMP492]] to i32
29945 // SIMD-ONLY0-NEXT:    br label [[COND_END1191:%.*]]
29946 // SIMD-ONLY0:       cond.false1189:
29947 // SIMD-ONLY0-NEXT:    [[TMP493:%.*]] = load i8, ptr [[UCX]], align 1
29948 // SIMD-ONLY0-NEXT:    [[CONV1190:%.*]] = zext i8 [[TMP493]] to i32
29949 // SIMD-ONLY0-NEXT:    br label [[COND_END1191]]
29950 // SIMD-ONLY0:       cond.end1191:
29951 // SIMD-ONLY0-NEXT:    [[COND1192:%.*]] = phi i32 [ [[CONV1188]], [[COND_TRUE1187]] ], [ [[CONV1190]], [[COND_FALSE1189]] ]
29952 // SIMD-ONLY0-NEXT:    [[CONV1193:%.*]] = trunc i32 [[COND1192]] to i8
29953 // SIMD-ONLY0-NEXT:    store i8 [[CONV1193]], ptr [[UCX]], align 1
29954 // SIMD-ONLY0-NEXT:    [[TMP494:%.*]] = load i8, ptr [[UCE]], align 1
29955 // SIMD-ONLY0-NEXT:    [[CONV1194:%.*]] = zext i8 [[TMP494]] to i32
29956 // SIMD-ONLY0-NEXT:    [[TMP495:%.*]] = load i8, ptr [[UCX]], align 1
29957 // SIMD-ONLY0-NEXT:    [[CONV1195:%.*]] = zext i8 [[TMP495]] to i32
29958 // SIMD-ONLY0-NEXT:    [[CMP1196:%.*]] = icmp eq i32 [[CONV1194]], [[CONV1195]]
29959 // SIMD-ONLY0-NEXT:    br i1 [[CMP1196]], label [[COND_TRUE1198:%.*]], label [[COND_FALSE1200:%.*]]
29960 // SIMD-ONLY0:       cond.true1198:
29961 // SIMD-ONLY0-NEXT:    [[TMP496:%.*]] = load i8, ptr [[UCD]], align 1
29962 // SIMD-ONLY0-NEXT:    [[CONV1199:%.*]] = zext i8 [[TMP496]] to i32
29963 // SIMD-ONLY0-NEXT:    br label [[COND_END1202:%.*]]
29964 // SIMD-ONLY0:       cond.false1200:
29965 // SIMD-ONLY0-NEXT:    [[TMP497:%.*]] = load i8, ptr [[UCX]], align 1
29966 // SIMD-ONLY0-NEXT:    [[CONV1201:%.*]] = zext i8 [[TMP497]] to i32
29967 // SIMD-ONLY0-NEXT:    br label [[COND_END1202]]
29968 // SIMD-ONLY0:       cond.end1202:
29969 // SIMD-ONLY0-NEXT:    [[COND1203:%.*]] = phi i32 [ [[CONV1199]], [[COND_TRUE1198]] ], [ [[CONV1201]], [[COND_FALSE1200]] ]
29970 // SIMD-ONLY0-NEXT:    [[CONV1204:%.*]] = trunc i32 [[COND1203]] to i8
29971 // SIMD-ONLY0-NEXT:    store i8 [[CONV1204]], ptr [[UCX]], align 1
29972 // SIMD-ONLY0-NEXT:    [[TMP498:%.*]] = load i8, ptr [[UCX]], align 1
29973 // SIMD-ONLY0-NEXT:    [[CONV1205:%.*]] = zext i8 [[TMP498]] to i32
29974 // SIMD-ONLY0-NEXT:    [[TMP499:%.*]] = load i8, ptr [[UCE]], align 1
29975 // SIMD-ONLY0-NEXT:    [[CONV1206:%.*]] = zext i8 [[TMP499]] to i32
29976 // SIMD-ONLY0-NEXT:    [[CMP1207:%.*]] = icmp eq i32 [[CONV1205]], [[CONV1206]]
29977 // SIMD-ONLY0-NEXT:    br i1 [[CMP1207]], label [[IF_THEN1209:%.*]], label [[IF_END1210:%.*]]
29978 // SIMD-ONLY0:       if.then1209:
29979 // SIMD-ONLY0-NEXT:    [[TMP500:%.*]] = load i8, ptr [[UCD]], align 1
29980 // SIMD-ONLY0-NEXT:    store i8 [[TMP500]], ptr [[UCX]], align 1
29981 // SIMD-ONLY0-NEXT:    br label [[IF_END1210]]
29982 // SIMD-ONLY0:       if.end1210:
29983 // SIMD-ONLY0-NEXT:    [[TMP501:%.*]] = load i8, ptr [[UCE]], align 1
29984 // SIMD-ONLY0-NEXT:    [[CONV1211:%.*]] = zext i8 [[TMP501]] to i32
29985 // SIMD-ONLY0-NEXT:    [[TMP502:%.*]] = load i8, ptr [[UCX]], align 1
29986 // SIMD-ONLY0-NEXT:    [[CONV1212:%.*]] = zext i8 [[TMP502]] to i32
29987 // SIMD-ONLY0-NEXT:    [[CMP1213:%.*]] = icmp eq i32 [[CONV1211]], [[CONV1212]]
29988 // SIMD-ONLY0-NEXT:    br i1 [[CMP1213]], label [[IF_THEN1215:%.*]], label [[IF_END1216:%.*]]
29989 // SIMD-ONLY0:       if.then1215:
29990 // SIMD-ONLY0-NEXT:    [[TMP503:%.*]] = load i8, ptr [[UCD]], align 1
29991 // SIMD-ONLY0-NEXT:    store i8 [[TMP503]], ptr [[UCX]], align 1
29992 // SIMD-ONLY0-NEXT:    br label [[IF_END1216]]
29993 // SIMD-ONLY0:       if.end1216:
29994 // SIMD-ONLY0-NEXT:    [[TMP504:%.*]] = load i16, ptr [[SX]], align 2
29995 // SIMD-ONLY0-NEXT:    [[CONV1217:%.*]] = sext i16 [[TMP504]] to i32
29996 // SIMD-ONLY0-NEXT:    [[TMP505:%.*]] = load i16, ptr [[SE]], align 2
29997 // SIMD-ONLY0-NEXT:    [[CONV1218:%.*]] = sext i16 [[TMP505]] to i32
29998 // SIMD-ONLY0-NEXT:    [[CMP1219:%.*]] = icmp sgt i32 [[CONV1217]], [[CONV1218]]
29999 // SIMD-ONLY0-NEXT:    br i1 [[CMP1219]], label [[COND_TRUE1221:%.*]], label [[COND_FALSE1223:%.*]]
30000 // SIMD-ONLY0:       cond.true1221:
30001 // SIMD-ONLY0-NEXT:    [[TMP506:%.*]] = load i16, ptr [[SE]], align 2
30002 // SIMD-ONLY0-NEXT:    [[CONV1222:%.*]] = sext i16 [[TMP506]] to i32
30003 // SIMD-ONLY0-NEXT:    br label [[COND_END1225:%.*]]
30004 // SIMD-ONLY0:       cond.false1223:
30005 // SIMD-ONLY0-NEXT:    [[TMP507:%.*]] = load i16, ptr [[SX]], align 2
30006 // SIMD-ONLY0-NEXT:    [[CONV1224:%.*]] = sext i16 [[TMP507]] to i32
30007 // SIMD-ONLY0-NEXT:    br label [[COND_END1225]]
30008 // SIMD-ONLY0:       cond.end1225:
30009 // SIMD-ONLY0-NEXT:    [[COND1226:%.*]] = phi i32 [ [[CONV1222]], [[COND_TRUE1221]] ], [ [[CONV1224]], [[COND_FALSE1223]] ]
30010 // SIMD-ONLY0-NEXT:    [[CONV1227:%.*]] = trunc i32 [[COND1226]] to i16
30011 // SIMD-ONLY0-NEXT:    store i16 [[CONV1227]], ptr [[SX]], align 2
30012 // SIMD-ONLY0-NEXT:    [[TMP508:%.*]] = load i16, ptr [[SX]], align 2
30013 // SIMD-ONLY0-NEXT:    [[CONV1228:%.*]] = sext i16 [[TMP508]] to i32
30014 // SIMD-ONLY0-NEXT:    [[TMP509:%.*]] = load i16, ptr [[SE]], align 2
30015 // SIMD-ONLY0-NEXT:    [[CONV1229:%.*]] = sext i16 [[TMP509]] to i32
30016 // SIMD-ONLY0-NEXT:    [[CMP1230:%.*]] = icmp slt i32 [[CONV1228]], [[CONV1229]]
30017 // SIMD-ONLY0-NEXT:    br i1 [[CMP1230]], label [[COND_TRUE1232:%.*]], label [[COND_FALSE1234:%.*]]
30018 // SIMD-ONLY0:       cond.true1232:
30019 // SIMD-ONLY0-NEXT:    [[TMP510:%.*]] = load i16, ptr [[SE]], align 2
30020 // SIMD-ONLY0-NEXT:    [[CONV1233:%.*]] = sext i16 [[TMP510]] to i32
30021 // SIMD-ONLY0-NEXT:    br label [[COND_END1236:%.*]]
30022 // SIMD-ONLY0:       cond.false1234:
30023 // SIMD-ONLY0-NEXT:    [[TMP511:%.*]] = load i16, ptr [[SX]], align 2
30024 // SIMD-ONLY0-NEXT:    [[CONV1235:%.*]] = sext i16 [[TMP511]] to i32
30025 // SIMD-ONLY0-NEXT:    br label [[COND_END1236]]
30026 // SIMD-ONLY0:       cond.end1236:
30027 // SIMD-ONLY0-NEXT:    [[COND1237:%.*]] = phi i32 [ [[CONV1233]], [[COND_TRUE1232]] ], [ [[CONV1235]], [[COND_FALSE1234]] ]
30028 // SIMD-ONLY0-NEXT:    [[CONV1238:%.*]] = trunc i32 [[COND1237]] to i16
30029 // SIMD-ONLY0-NEXT:    store i16 [[CONV1238]], ptr [[SX]], align 2
30030 // SIMD-ONLY0-NEXT:    [[TMP512:%.*]] = load i16, ptr [[SE]], align 2
30031 // SIMD-ONLY0-NEXT:    [[CONV1239:%.*]] = sext i16 [[TMP512]] to i32
30032 // SIMD-ONLY0-NEXT:    [[TMP513:%.*]] = load i16, ptr [[SX]], align 2
30033 // SIMD-ONLY0-NEXT:    [[CONV1240:%.*]] = sext i16 [[TMP513]] to i32
30034 // SIMD-ONLY0-NEXT:    [[CMP1241:%.*]] = icmp sgt i32 [[CONV1239]], [[CONV1240]]
30035 // SIMD-ONLY0-NEXT:    br i1 [[CMP1241]], label [[COND_TRUE1243:%.*]], label [[COND_FALSE1245:%.*]]
30036 // SIMD-ONLY0:       cond.true1243:
30037 // SIMD-ONLY0-NEXT:    [[TMP514:%.*]] = load i16, ptr [[SE]], align 2
30038 // SIMD-ONLY0-NEXT:    [[CONV1244:%.*]] = sext i16 [[TMP514]] to i32
30039 // SIMD-ONLY0-NEXT:    br label [[COND_END1247:%.*]]
30040 // SIMD-ONLY0:       cond.false1245:
30041 // SIMD-ONLY0-NEXT:    [[TMP515:%.*]] = load i16, ptr [[SX]], align 2
30042 // SIMD-ONLY0-NEXT:    [[CONV1246:%.*]] = sext i16 [[TMP515]] to i32
30043 // SIMD-ONLY0-NEXT:    br label [[COND_END1247]]
30044 // SIMD-ONLY0:       cond.end1247:
30045 // SIMD-ONLY0-NEXT:    [[COND1248:%.*]] = phi i32 [ [[CONV1244]], [[COND_TRUE1243]] ], [ [[CONV1246]], [[COND_FALSE1245]] ]
30046 // SIMD-ONLY0-NEXT:    [[CONV1249:%.*]] = trunc i32 [[COND1248]] to i16
30047 // SIMD-ONLY0-NEXT:    store i16 [[CONV1249]], ptr [[SX]], align 2
30048 // SIMD-ONLY0-NEXT:    [[TMP516:%.*]] = load i16, ptr [[SE]], align 2
30049 // SIMD-ONLY0-NEXT:    [[CONV1250:%.*]] = sext i16 [[TMP516]] to i32
30050 // SIMD-ONLY0-NEXT:    [[TMP517:%.*]] = load i16, ptr [[SX]], align 2
30051 // SIMD-ONLY0-NEXT:    [[CONV1251:%.*]] = sext i16 [[TMP517]] to i32
30052 // SIMD-ONLY0-NEXT:    [[CMP1252:%.*]] = icmp slt i32 [[CONV1250]], [[CONV1251]]
30053 // SIMD-ONLY0-NEXT:    br i1 [[CMP1252]], label [[COND_TRUE1254:%.*]], label [[COND_FALSE1256:%.*]]
30054 // SIMD-ONLY0:       cond.true1254:
30055 // SIMD-ONLY0-NEXT:    [[TMP518:%.*]] = load i16, ptr [[SE]], align 2
30056 // SIMD-ONLY0-NEXT:    [[CONV1255:%.*]] = sext i16 [[TMP518]] to i32
30057 // SIMD-ONLY0-NEXT:    br label [[COND_END1258:%.*]]
30058 // SIMD-ONLY0:       cond.false1256:
30059 // SIMD-ONLY0-NEXT:    [[TMP519:%.*]] = load i16, ptr [[SX]], align 2
30060 // SIMD-ONLY0-NEXT:    [[CONV1257:%.*]] = sext i16 [[TMP519]] to i32
30061 // SIMD-ONLY0-NEXT:    br label [[COND_END1258]]
30062 // SIMD-ONLY0:       cond.end1258:
30063 // SIMD-ONLY0-NEXT:    [[COND1259:%.*]] = phi i32 [ [[CONV1255]], [[COND_TRUE1254]] ], [ [[CONV1257]], [[COND_FALSE1256]] ]
30064 // SIMD-ONLY0-NEXT:    [[CONV1260:%.*]] = trunc i32 [[COND1259]] to i16
30065 // SIMD-ONLY0-NEXT:    store i16 [[CONV1260]], ptr [[SX]], align 2
30066 // SIMD-ONLY0-NEXT:    [[TMP520:%.*]] = load i16, ptr [[SX]], align 2
30067 // SIMD-ONLY0-NEXT:    [[CONV1261:%.*]] = sext i16 [[TMP520]] to i32
30068 // SIMD-ONLY0-NEXT:    [[TMP521:%.*]] = load i16, ptr [[SE]], align 2
30069 // SIMD-ONLY0-NEXT:    [[CONV1262:%.*]] = sext i16 [[TMP521]] to i32
30070 // SIMD-ONLY0-NEXT:    [[CMP1263:%.*]] = icmp sgt i32 [[CONV1261]], [[CONV1262]]
30071 // SIMD-ONLY0-NEXT:    br i1 [[CMP1263]], label [[IF_THEN1265:%.*]], label [[IF_END1266:%.*]]
30072 // SIMD-ONLY0:       if.then1265:
30073 // SIMD-ONLY0-NEXT:    [[TMP522:%.*]] = load i16, ptr [[SE]], align 2
30074 // SIMD-ONLY0-NEXT:    store i16 [[TMP522]], ptr [[SX]], align 2
30075 // SIMD-ONLY0-NEXT:    br label [[IF_END1266]]
30076 // SIMD-ONLY0:       if.end1266:
30077 // SIMD-ONLY0-NEXT:    [[TMP523:%.*]] = load i16, ptr [[SX]], align 2
30078 // SIMD-ONLY0-NEXT:    [[CONV1267:%.*]] = sext i16 [[TMP523]] to i32
30079 // SIMD-ONLY0-NEXT:    [[TMP524:%.*]] = load i16, ptr [[SE]], align 2
30080 // SIMD-ONLY0-NEXT:    [[CONV1268:%.*]] = sext i16 [[TMP524]] to i32
30081 // SIMD-ONLY0-NEXT:    [[CMP1269:%.*]] = icmp slt i32 [[CONV1267]], [[CONV1268]]
30082 // SIMD-ONLY0-NEXT:    br i1 [[CMP1269]], label [[IF_THEN1271:%.*]], label [[IF_END1272:%.*]]
30083 // SIMD-ONLY0:       if.then1271:
30084 // SIMD-ONLY0-NEXT:    [[TMP525:%.*]] = load i16, ptr [[SE]], align 2
30085 // SIMD-ONLY0-NEXT:    store i16 [[TMP525]], ptr [[SX]], align 2
30086 // SIMD-ONLY0-NEXT:    br label [[IF_END1272]]
30087 // SIMD-ONLY0:       if.end1272:
30088 // SIMD-ONLY0-NEXT:    [[TMP526:%.*]] = load i16, ptr [[SE]], align 2
30089 // SIMD-ONLY0-NEXT:    [[CONV1273:%.*]] = sext i16 [[TMP526]] to i32
30090 // SIMD-ONLY0-NEXT:    [[TMP527:%.*]] = load i16, ptr [[SX]], align 2
30091 // SIMD-ONLY0-NEXT:    [[CONV1274:%.*]] = sext i16 [[TMP527]] to i32
30092 // SIMD-ONLY0-NEXT:    [[CMP1275:%.*]] = icmp sgt i32 [[CONV1273]], [[CONV1274]]
30093 // SIMD-ONLY0-NEXT:    br i1 [[CMP1275]], label [[IF_THEN1277:%.*]], label [[IF_END1278:%.*]]
30094 // SIMD-ONLY0:       if.then1277:
30095 // SIMD-ONLY0-NEXT:    [[TMP528:%.*]] = load i16, ptr [[SE]], align 2
30096 // SIMD-ONLY0-NEXT:    store i16 [[TMP528]], ptr [[SX]], align 2
30097 // SIMD-ONLY0-NEXT:    br label [[IF_END1278]]
30098 // SIMD-ONLY0:       if.end1278:
30099 // SIMD-ONLY0-NEXT:    [[TMP529:%.*]] = load i16, ptr [[SE]], align 2
30100 // SIMD-ONLY0-NEXT:    [[CONV1279:%.*]] = sext i16 [[TMP529]] to i32
30101 // SIMD-ONLY0-NEXT:    [[TMP530:%.*]] = load i16, ptr [[SX]], align 2
30102 // SIMD-ONLY0-NEXT:    [[CONV1280:%.*]] = sext i16 [[TMP530]] to i32
30103 // SIMD-ONLY0-NEXT:    [[CMP1281:%.*]] = icmp slt i32 [[CONV1279]], [[CONV1280]]
30104 // SIMD-ONLY0-NEXT:    br i1 [[CMP1281]], label [[IF_THEN1283:%.*]], label [[IF_END1284:%.*]]
30105 // SIMD-ONLY0:       if.then1283:
30106 // SIMD-ONLY0-NEXT:    [[TMP531:%.*]] = load i16, ptr [[SE]], align 2
30107 // SIMD-ONLY0-NEXT:    store i16 [[TMP531]], ptr [[SX]], align 2
30108 // SIMD-ONLY0-NEXT:    br label [[IF_END1284]]
30109 // SIMD-ONLY0:       if.end1284:
30110 // SIMD-ONLY0-NEXT:    [[TMP532:%.*]] = load i16, ptr [[SX]], align 2
30111 // SIMD-ONLY0-NEXT:    [[CONV1285:%.*]] = sext i16 [[TMP532]] to i32
30112 // SIMD-ONLY0-NEXT:    [[TMP533:%.*]] = load i16, ptr [[SE]], align 2
30113 // SIMD-ONLY0-NEXT:    [[CONV1286:%.*]] = sext i16 [[TMP533]] to i32
30114 // SIMD-ONLY0-NEXT:    [[CMP1287:%.*]] = icmp eq i32 [[CONV1285]], [[CONV1286]]
30115 // SIMD-ONLY0-NEXT:    br i1 [[CMP1287]], label [[COND_TRUE1289:%.*]], label [[COND_FALSE1291:%.*]]
30116 // SIMD-ONLY0:       cond.true1289:
30117 // SIMD-ONLY0-NEXT:    [[TMP534:%.*]] = load i16, ptr [[SD]], align 2
30118 // SIMD-ONLY0-NEXT:    [[CONV1290:%.*]] = sext i16 [[TMP534]] to i32
30119 // SIMD-ONLY0-NEXT:    br label [[COND_END1293:%.*]]
30120 // SIMD-ONLY0:       cond.false1291:
30121 // SIMD-ONLY0-NEXT:    [[TMP535:%.*]] = load i16, ptr [[SX]], align 2
30122 // SIMD-ONLY0-NEXT:    [[CONV1292:%.*]] = sext i16 [[TMP535]] to i32
30123 // SIMD-ONLY0-NEXT:    br label [[COND_END1293]]
30124 // SIMD-ONLY0:       cond.end1293:
30125 // SIMD-ONLY0-NEXT:    [[COND1294:%.*]] = phi i32 [ [[CONV1290]], [[COND_TRUE1289]] ], [ [[CONV1292]], [[COND_FALSE1291]] ]
30126 // SIMD-ONLY0-NEXT:    [[CONV1295:%.*]] = trunc i32 [[COND1294]] to i16
30127 // SIMD-ONLY0-NEXT:    store i16 [[CONV1295]], ptr [[SX]], align 2
30128 // SIMD-ONLY0-NEXT:    [[TMP536:%.*]] = load i16, ptr [[SE]], align 2
30129 // SIMD-ONLY0-NEXT:    [[CONV1296:%.*]] = sext i16 [[TMP536]] to i32
30130 // SIMD-ONLY0-NEXT:    [[TMP537:%.*]] = load i16, ptr [[SX]], align 2
30131 // SIMD-ONLY0-NEXT:    [[CONV1297:%.*]] = sext i16 [[TMP537]] to i32
30132 // SIMD-ONLY0-NEXT:    [[CMP1298:%.*]] = icmp eq i32 [[CONV1296]], [[CONV1297]]
30133 // SIMD-ONLY0-NEXT:    br i1 [[CMP1298]], label [[COND_TRUE1300:%.*]], label [[COND_FALSE1302:%.*]]
30134 // SIMD-ONLY0:       cond.true1300:
30135 // SIMD-ONLY0-NEXT:    [[TMP538:%.*]] = load i16, ptr [[SD]], align 2
30136 // SIMD-ONLY0-NEXT:    [[CONV1301:%.*]] = sext i16 [[TMP538]] to i32
30137 // SIMD-ONLY0-NEXT:    br label [[COND_END1304:%.*]]
30138 // SIMD-ONLY0:       cond.false1302:
30139 // SIMD-ONLY0-NEXT:    [[TMP539:%.*]] = load i16, ptr [[SX]], align 2
30140 // SIMD-ONLY0-NEXT:    [[CONV1303:%.*]] = sext i16 [[TMP539]] to i32
30141 // SIMD-ONLY0-NEXT:    br label [[COND_END1304]]
30142 // SIMD-ONLY0:       cond.end1304:
30143 // SIMD-ONLY0-NEXT:    [[COND1305:%.*]] = phi i32 [ [[CONV1301]], [[COND_TRUE1300]] ], [ [[CONV1303]], [[COND_FALSE1302]] ]
30144 // SIMD-ONLY0-NEXT:    [[CONV1306:%.*]] = trunc i32 [[COND1305]] to i16
30145 // SIMD-ONLY0-NEXT:    store i16 [[CONV1306]], ptr [[SX]], align 2
30146 // SIMD-ONLY0-NEXT:    [[TMP540:%.*]] = load i16, ptr [[SX]], align 2
30147 // SIMD-ONLY0-NEXT:    [[CONV1307:%.*]] = sext i16 [[TMP540]] to i32
30148 // SIMD-ONLY0-NEXT:    [[TMP541:%.*]] = load i16, ptr [[SE]], align 2
30149 // SIMD-ONLY0-NEXT:    [[CONV1308:%.*]] = sext i16 [[TMP541]] to i32
30150 // SIMD-ONLY0-NEXT:    [[CMP1309:%.*]] = icmp eq i32 [[CONV1307]], [[CONV1308]]
30151 // SIMD-ONLY0-NEXT:    br i1 [[CMP1309]], label [[IF_THEN1311:%.*]], label [[IF_END1312:%.*]]
30152 // SIMD-ONLY0:       if.then1311:
30153 // SIMD-ONLY0-NEXT:    [[TMP542:%.*]] = load i16, ptr [[SD]], align 2
30154 // SIMD-ONLY0-NEXT:    store i16 [[TMP542]], ptr [[SX]], align 2
30155 // SIMD-ONLY0-NEXT:    br label [[IF_END1312]]
30156 // SIMD-ONLY0:       if.end1312:
30157 // SIMD-ONLY0-NEXT:    [[TMP543:%.*]] = load i16, ptr [[SE]], align 2
30158 // SIMD-ONLY0-NEXT:    [[CONV1313:%.*]] = sext i16 [[TMP543]] to i32
30159 // SIMD-ONLY0-NEXT:    [[TMP544:%.*]] = load i16, ptr [[SX]], align 2
30160 // SIMD-ONLY0-NEXT:    [[CONV1314:%.*]] = sext i16 [[TMP544]] to i32
30161 // SIMD-ONLY0-NEXT:    [[CMP1315:%.*]] = icmp eq i32 [[CONV1313]], [[CONV1314]]
30162 // SIMD-ONLY0-NEXT:    br i1 [[CMP1315]], label [[IF_THEN1317:%.*]], label [[IF_END1318:%.*]]
30163 // SIMD-ONLY0:       if.then1317:
30164 // SIMD-ONLY0-NEXT:    [[TMP545:%.*]] = load i16, ptr [[SD]], align 2
30165 // SIMD-ONLY0-NEXT:    store i16 [[TMP545]], ptr [[SX]], align 2
30166 // SIMD-ONLY0-NEXT:    br label [[IF_END1318]]
30167 // SIMD-ONLY0:       if.end1318:
30168 // SIMD-ONLY0-NEXT:    [[TMP546:%.*]] = load i16, ptr [[USX]], align 2
30169 // SIMD-ONLY0-NEXT:    [[CONV1319:%.*]] = zext i16 [[TMP546]] to i32
30170 // SIMD-ONLY0-NEXT:    [[TMP547:%.*]] = load i16, ptr [[USE]], align 2
30171 // SIMD-ONLY0-NEXT:    [[CONV1320:%.*]] = zext i16 [[TMP547]] to i32
30172 // SIMD-ONLY0-NEXT:    [[CMP1321:%.*]] = icmp sgt i32 [[CONV1319]], [[CONV1320]]
30173 // SIMD-ONLY0-NEXT:    br i1 [[CMP1321]], label [[COND_TRUE1323:%.*]], label [[COND_FALSE1325:%.*]]
30174 // SIMD-ONLY0:       cond.true1323:
30175 // SIMD-ONLY0-NEXT:    [[TMP548:%.*]] = load i16, ptr [[USE]], align 2
30176 // SIMD-ONLY0-NEXT:    [[CONV1324:%.*]] = zext i16 [[TMP548]] to i32
30177 // SIMD-ONLY0-NEXT:    br label [[COND_END1327:%.*]]
30178 // SIMD-ONLY0:       cond.false1325:
30179 // SIMD-ONLY0-NEXT:    [[TMP549:%.*]] = load i16, ptr [[USX]], align 2
30180 // SIMD-ONLY0-NEXT:    [[CONV1326:%.*]] = zext i16 [[TMP549]] to i32
30181 // SIMD-ONLY0-NEXT:    br label [[COND_END1327]]
30182 // SIMD-ONLY0:       cond.end1327:
30183 // SIMD-ONLY0-NEXT:    [[COND1328:%.*]] = phi i32 [ [[CONV1324]], [[COND_TRUE1323]] ], [ [[CONV1326]], [[COND_FALSE1325]] ]
30184 // SIMD-ONLY0-NEXT:    [[CONV1329:%.*]] = trunc i32 [[COND1328]] to i16
30185 // SIMD-ONLY0-NEXT:    store i16 [[CONV1329]], ptr [[USX]], align 2
30186 // SIMD-ONLY0-NEXT:    [[TMP550:%.*]] = load i16, ptr [[USX]], align 2
30187 // SIMD-ONLY0-NEXT:    [[CONV1330:%.*]] = zext i16 [[TMP550]] to i32
30188 // SIMD-ONLY0-NEXT:    [[TMP551:%.*]] = load i16, ptr [[USE]], align 2
30189 // SIMD-ONLY0-NEXT:    [[CONV1331:%.*]] = zext i16 [[TMP551]] to i32
30190 // SIMD-ONLY0-NEXT:    [[CMP1332:%.*]] = icmp slt i32 [[CONV1330]], [[CONV1331]]
30191 // SIMD-ONLY0-NEXT:    br i1 [[CMP1332]], label [[COND_TRUE1334:%.*]], label [[COND_FALSE1336:%.*]]
30192 // SIMD-ONLY0:       cond.true1334:
30193 // SIMD-ONLY0-NEXT:    [[TMP552:%.*]] = load i16, ptr [[USE]], align 2
30194 // SIMD-ONLY0-NEXT:    [[CONV1335:%.*]] = zext i16 [[TMP552]] to i32
30195 // SIMD-ONLY0-NEXT:    br label [[COND_END1338:%.*]]
30196 // SIMD-ONLY0:       cond.false1336:
30197 // SIMD-ONLY0-NEXT:    [[TMP553:%.*]] = load i16, ptr [[USX]], align 2
30198 // SIMD-ONLY0-NEXT:    [[CONV1337:%.*]] = zext i16 [[TMP553]] to i32
30199 // SIMD-ONLY0-NEXT:    br label [[COND_END1338]]
30200 // SIMD-ONLY0:       cond.end1338:
30201 // SIMD-ONLY0-NEXT:    [[COND1339:%.*]] = phi i32 [ [[CONV1335]], [[COND_TRUE1334]] ], [ [[CONV1337]], [[COND_FALSE1336]] ]
30202 // SIMD-ONLY0-NEXT:    [[CONV1340:%.*]] = trunc i32 [[COND1339]] to i16
30203 // SIMD-ONLY0-NEXT:    store i16 [[CONV1340]], ptr [[USX]], align 2
30204 // SIMD-ONLY0-NEXT:    [[TMP554:%.*]] = load i16, ptr [[USE]], align 2
30205 // SIMD-ONLY0-NEXT:    [[CONV1341:%.*]] = zext i16 [[TMP554]] to i32
30206 // SIMD-ONLY0-NEXT:    [[TMP555:%.*]] = load i16, ptr [[USX]], align 2
30207 // SIMD-ONLY0-NEXT:    [[CONV1342:%.*]] = zext i16 [[TMP555]] to i32
30208 // SIMD-ONLY0-NEXT:    [[CMP1343:%.*]] = icmp sgt i32 [[CONV1341]], [[CONV1342]]
30209 // SIMD-ONLY0-NEXT:    br i1 [[CMP1343]], label [[COND_TRUE1345:%.*]], label [[COND_FALSE1347:%.*]]
30210 // SIMD-ONLY0:       cond.true1345:
30211 // SIMD-ONLY0-NEXT:    [[TMP556:%.*]] = load i16, ptr [[USE]], align 2
30212 // SIMD-ONLY0-NEXT:    [[CONV1346:%.*]] = zext i16 [[TMP556]] to i32
30213 // SIMD-ONLY0-NEXT:    br label [[COND_END1349:%.*]]
30214 // SIMD-ONLY0:       cond.false1347:
30215 // SIMD-ONLY0-NEXT:    [[TMP557:%.*]] = load i16, ptr [[USX]], align 2
30216 // SIMD-ONLY0-NEXT:    [[CONV1348:%.*]] = zext i16 [[TMP557]] to i32
30217 // SIMD-ONLY0-NEXT:    br label [[COND_END1349]]
30218 // SIMD-ONLY0:       cond.end1349:
30219 // SIMD-ONLY0-NEXT:    [[COND1350:%.*]] = phi i32 [ [[CONV1346]], [[COND_TRUE1345]] ], [ [[CONV1348]], [[COND_FALSE1347]] ]
30220 // SIMD-ONLY0-NEXT:    [[CONV1351:%.*]] = trunc i32 [[COND1350]] to i16
30221 // SIMD-ONLY0-NEXT:    store i16 [[CONV1351]], ptr [[USX]], align 2
30222 // SIMD-ONLY0-NEXT:    [[TMP558:%.*]] = load i16, ptr [[USE]], align 2
30223 // SIMD-ONLY0-NEXT:    [[CONV1352:%.*]] = zext i16 [[TMP558]] to i32
30224 // SIMD-ONLY0-NEXT:    [[TMP559:%.*]] = load i16, ptr [[USX]], align 2
30225 // SIMD-ONLY0-NEXT:    [[CONV1353:%.*]] = zext i16 [[TMP559]] to i32
30226 // SIMD-ONLY0-NEXT:    [[CMP1354:%.*]] = icmp slt i32 [[CONV1352]], [[CONV1353]]
30227 // SIMD-ONLY0-NEXT:    br i1 [[CMP1354]], label [[COND_TRUE1356:%.*]], label [[COND_FALSE1358:%.*]]
30228 // SIMD-ONLY0:       cond.true1356:
30229 // SIMD-ONLY0-NEXT:    [[TMP560:%.*]] = load i16, ptr [[USE]], align 2
30230 // SIMD-ONLY0-NEXT:    [[CONV1357:%.*]] = zext i16 [[TMP560]] to i32
30231 // SIMD-ONLY0-NEXT:    br label [[COND_END1360:%.*]]
30232 // SIMD-ONLY0:       cond.false1358:
30233 // SIMD-ONLY0-NEXT:    [[TMP561:%.*]] = load i16, ptr [[USX]], align 2
30234 // SIMD-ONLY0-NEXT:    [[CONV1359:%.*]] = zext i16 [[TMP561]] to i32
30235 // SIMD-ONLY0-NEXT:    br label [[COND_END1360]]
30236 // SIMD-ONLY0:       cond.end1360:
30237 // SIMD-ONLY0-NEXT:    [[COND1361:%.*]] = phi i32 [ [[CONV1357]], [[COND_TRUE1356]] ], [ [[CONV1359]], [[COND_FALSE1358]] ]
30238 // SIMD-ONLY0-NEXT:    [[CONV1362:%.*]] = trunc i32 [[COND1361]] to i16
30239 // SIMD-ONLY0-NEXT:    store i16 [[CONV1362]], ptr [[USX]], align 2
30240 // SIMD-ONLY0-NEXT:    [[TMP562:%.*]] = load i16, ptr [[USX]], align 2
30241 // SIMD-ONLY0-NEXT:    [[CONV1363:%.*]] = zext i16 [[TMP562]] to i32
30242 // SIMD-ONLY0-NEXT:    [[TMP563:%.*]] = load i16, ptr [[USE]], align 2
30243 // SIMD-ONLY0-NEXT:    [[CONV1364:%.*]] = zext i16 [[TMP563]] to i32
30244 // SIMD-ONLY0-NEXT:    [[CMP1365:%.*]] = icmp sgt i32 [[CONV1363]], [[CONV1364]]
30245 // SIMD-ONLY0-NEXT:    br i1 [[CMP1365]], label [[IF_THEN1367:%.*]], label [[IF_END1368:%.*]]
30246 // SIMD-ONLY0:       if.then1367:
30247 // SIMD-ONLY0-NEXT:    [[TMP564:%.*]] = load i16, ptr [[USE]], align 2
30248 // SIMD-ONLY0-NEXT:    store i16 [[TMP564]], ptr [[USX]], align 2
30249 // SIMD-ONLY0-NEXT:    br label [[IF_END1368]]
30250 // SIMD-ONLY0:       if.end1368:
30251 // SIMD-ONLY0-NEXT:    [[TMP565:%.*]] = load i16, ptr [[USX]], align 2
30252 // SIMD-ONLY0-NEXT:    [[CONV1369:%.*]] = zext i16 [[TMP565]] to i32
30253 // SIMD-ONLY0-NEXT:    [[TMP566:%.*]] = load i16, ptr [[USE]], align 2
30254 // SIMD-ONLY0-NEXT:    [[CONV1370:%.*]] = zext i16 [[TMP566]] to i32
30255 // SIMD-ONLY0-NEXT:    [[CMP1371:%.*]] = icmp slt i32 [[CONV1369]], [[CONV1370]]
30256 // SIMD-ONLY0-NEXT:    br i1 [[CMP1371]], label [[IF_THEN1373:%.*]], label [[IF_END1374:%.*]]
30257 // SIMD-ONLY0:       if.then1373:
30258 // SIMD-ONLY0-NEXT:    [[TMP567:%.*]] = load i16, ptr [[USE]], align 2
30259 // SIMD-ONLY0-NEXT:    store i16 [[TMP567]], ptr [[USX]], align 2
30260 // SIMD-ONLY0-NEXT:    br label [[IF_END1374]]
30261 // SIMD-ONLY0:       if.end1374:
30262 // SIMD-ONLY0-NEXT:    [[TMP568:%.*]] = load i16, ptr [[USE]], align 2
30263 // SIMD-ONLY0-NEXT:    [[CONV1375:%.*]] = zext i16 [[TMP568]] to i32
30264 // SIMD-ONLY0-NEXT:    [[TMP569:%.*]] = load i16, ptr [[USX]], align 2
30265 // SIMD-ONLY0-NEXT:    [[CONV1376:%.*]] = zext i16 [[TMP569]] to i32
30266 // SIMD-ONLY0-NEXT:    [[CMP1377:%.*]] = icmp sgt i32 [[CONV1375]], [[CONV1376]]
30267 // SIMD-ONLY0-NEXT:    br i1 [[CMP1377]], label [[IF_THEN1379:%.*]], label [[IF_END1380:%.*]]
30268 // SIMD-ONLY0:       if.then1379:
30269 // SIMD-ONLY0-NEXT:    [[TMP570:%.*]] = load i16, ptr [[USE]], align 2
30270 // SIMD-ONLY0-NEXT:    store i16 [[TMP570]], ptr [[USX]], align 2
30271 // SIMD-ONLY0-NEXT:    br label [[IF_END1380]]
30272 // SIMD-ONLY0:       if.end1380:
30273 // SIMD-ONLY0-NEXT:    [[TMP571:%.*]] = load i16, ptr [[USE]], align 2
30274 // SIMD-ONLY0-NEXT:    [[CONV1381:%.*]] = zext i16 [[TMP571]] to i32
30275 // SIMD-ONLY0-NEXT:    [[TMP572:%.*]] = load i16, ptr [[USX]], align 2
30276 // SIMD-ONLY0-NEXT:    [[CONV1382:%.*]] = zext i16 [[TMP572]] to i32
30277 // SIMD-ONLY0-NEXT:    [[CMP1383:%.*]] = icmp slt i32 [[CONV1381]], [[CONV1382]]
30278 // SIMD-ONLY0-NEXT:    br i1 [[CMP1383]], label [[IF_THEN1385:%.*]], label [[IF_END1386:%.*]]
30279 // SIMD-ONLY0:       if.then1385:
30280 // SIMD-ONLY0-NEXT:    [[TMP573:%.*]] = load i16, ptr [[USE]], align 2
30281 // SIMD-ONLY0-NEXT:    store i16 [[TMP573]], ptr [[USX]], align 2
30282 // SIMD-ONLY0-NEXT:    br label [[IF_END1386]]
30283 // SIMD-ONLY0:       if.end1386:
30284 // SIMD-ONLY0-NEXT:    [[TMP574:%.*]] = load i16, ptr [[USX]], align 2
30285 // SIMD-ONLY0-NEXT:    [[CONV1387:%.*]] = zext i16 [[TMP574]] to i32
30286 // SIMD-ONLY0-NEXT:    [[TMP575:%.*]] = load i16, ptr [[USE]], align 2
30287 // SIMD-ONLY0-NEXT:    [[CONV1388:%.*]] = zext i16 [[TMP575]] to i32
30288 // SIMD-ONLY0-NEXT:    [[CMP1389:%.*]] = icmp eq i32 [[CONV1387]], [[CONV1388]]
30289 // SIMD-ONLY0-NEXT:    br i1 [[CMP1389]], label [[COND_TRUE1391:%.*]], label [[COND_FALSE1393:%.*]]
30290 // SIMD-ONLY0:       cond.true1391:
30291 // SIMD-ONLY0-NEXT:    [[TMP576:%.*]] = load i16, ptr [[USD]], align 2
30292 // SIMD-ONLY0-NEXT:    [[CONV1392:%.*]] = zext i16 [[TMP576]] to i32
30293 // SIMD-ONLY0-NEXT:    br label [[COND_END1395:%.*]]
30294 // SIMD-ONLY0:       cond.false1393:
30295 // SIMD-ONLY0-NEXT:    [[TMP577:%.*]] = load i16, ptr [[USX]], align 2
30296 // SIMD-ONLY0-NEXT:    [[CONV1394:%.*]] = zext i16 [[TMP577]] to i32
30297 // SIMD-ONLY0-NEXT:    br label [[COND_END1395]]
30298 // SIMD-ONLY0:       cond.end1395:
30299 // SIMD-ONLY0-NEXT:    [[COND1396:%.*]] = phi i32 [ [[CONV1392]], [[COND_TRUE1391]] ], [ [[CONV1394]], [[COND_FALSE1393]] ]
30300 // SIMD-ONLY0-NEXT:    [[CONV1397:%.*]] = trunc i32 [[COND1396]] to i16
30301 // SIMD-ONLY0-NEXT:    store i16 [[CONV1397]], ptr [[USX]], align 2
30302 // SIMD-ONLY0-NEXT:    [[TMP578:%.*]] = load i16, ptr [[USE]], align 2
30303 // SIMD-ONLY0-NEXT:    [[CONV1398:%.*]] = zext i16 [[TMP578]] to i32
30304 // SIMD-ONLY0-NEXT:    [[TMP579:%.*]] = load i16, ptr [[USX]], align 2
30305 // SIMD-ONLY0-NEXT:    [[CONV1399:%.*]] = zext i16 [[TMP579]] to i32
30306 // SIMD-ONLY0-NEXT:    [[CMP1400:%.*]] = icmp eq i32 [[CONV1398]], [[CONV1399]]
30307 // SIMD-ONLY0-NEXT:    br i1 [[CMP1400]], label [[COND_TRUE1402:%.*]], label [[COND_FALSE1404:%.*]]
30308 // SIMD-ONLY0:       cond.true1402:
30309 // SIMD-ONLY0-NEXT:    [[TMP580:%.*]] = load i16, ptr [[USD]], align 2
30310 // SIMD-ONLY0-NEXT:    [[CONV1403:%.*]] = zext i16 [[TMP580]] to i32
30311 // SIMD-ONLY0-NEXT:    br label [[COND_END1406:%.*]]
30312 // SIMD-ONLY0:       cond.false1404:
30313 // SIMD-ONLY0-NEXT:    [[TMP581:%.*]] = load i16, ptr [[USX]], align 2
30314 // SIMD-ONLY0-NEXT:    [[CONV1405:%.*]] = zext i16 [[TMP581]] to i32
30315 // SIMD-ONLY0-NEXT:    br label [[COND_END1406]]
30316 // SIMD-ONLY0:       cond.end1406:
30317 // SIMD-ONLY0-NEXT:    [[COND1407:%.*]] = phi i32 [ [[CONV1403]], [[COND_TRUE1402]] ], [ [[CONV1405]], [[COND_FALSE1404]] ]
30318 // SIMD-ONLY0-NEXT:    [[CONV1408:%.*]] = trunc i32 [[COND1407]] to i16
30319 // SIMD-ONLY0-NEXT:    store i16 [[CONV1408]], ptr [[USX]], align 2
30320 // SIMD-ONLY0-NEXT:    [[TMP582:%.*]] = load i16, ptr [[USX]], align 2
30321 // SIMD-ONLY0-NEXT:    [[CONV1409:%.*]] = zext i16 [[TMP582]] to i32
30322 // SIMD-ONLY0-NEXT:    [[TMP583:%.*]] = load i16, ptr [[USE]], align 2
30323 // SIMD-ONLY0-NEXT:    [[CONV1410:%.*]] = zext i16 [[TMP583]] to i32
30324 // SIMD-ONLY0-NEXT:    [[CMP1411:%.*]] = icmp eq i32 [[CONV1409]], [[CONV1410]]
30325 // SIMD-ONLY0-NEXT:    br i1 [[CMP1411]], label [[IF_THEN1413:%.*]], label [[IF_END1414:%.*]]
30326 // SIMD-ONLY0:       if.then1413:
30327 // SIMD-ONLY0-NEXT:    [[TMP584:%.*]] = load i16, ptr [[USD]], align 2
30328 // SIMD-ONLY0-NEXT:    store i16 [[TMP584]], ptr [[USX]], align 2
30329 // SIMD-ONLY0-NEXT:    br label [[IF_END1414]]
30330 // SIMD-ONLY0:       if.end1414:
30331 // SIMD-ONLY0-NEXT:    [[TMP585:%.*]] = load i16, ptr [[USE]], align 2
30332 // SIMD-ONLY0-NEXT:    [[CONV1415:%.*]] = zext i16 [[TMP585]] to i32
30333 // SIMD-ONLY0-NEXT:    [[TMP586:%.*]] = load i16, ptr [[USX]], align 2
30334 // SIMD-ONLY0-NEXT:    [[CONV1416:%.*]] = zext i16 [[TMP586]] to i32
30335 // SIMD-ONLY0-NEXT:    [[CMP1417:%.*]] = icmp eq i32 [[CONV1415]], [[CONV1416]]
30336 // SIMD-ONLY0-NEXT:    br i1 [[CMP1417]], label [[IF_THEN1419:%.*]], label [[IF_END1420:%.*]]
30337 // SIMD-ONLY0:       if.then1419:
30338 // SIMD-ONLY0-NEXT:    [[TMP587:%.*]] = load i16, ptr [[USD]], align 2
30339 // SIMD-ONLY0-NEXT:    store i16 [[TMP587]], ptr [[USX]], align 2
30340 // SIMD-ONLY0-NEXT:    br label [[IF_END1420]]
30341 // SIMD-ONLY0:       if.end1420:
30342 // SIMD-ONLY0-NEXT:    [[TMP588:%.*]] = load i16, ptr [[SX]], align 2
30343 // SIMD-ONLY0-NEXT:    [[CONV1421:%.*]] = sext i16 [[TMP588]] to i32
30344 // SIMD-ONLY0-NEXT:    [[TMP589:%.*]] = load i16, ptr [[SE]], align 2
30345 // SIMD-ONLY0-NEXT:    [[CONV1422:%.*]] = sext i16 [[TMP589]] to i32
30346 // SIMD-ONLY0-NEXT:    [[CMP1423:%.*]] = icmp sgt i32 [[CONV1421]], [[CONV1422]]
30347 // SIMD-ONLY0-NEXT:    br i1 [[CMP1423]], label [[COND_TRUE1425:%.*]], label [[COND_FALSE1427:%.*]]
30348 // SIMD-ONLY0:       cond.true1425:
30349 // SIMD-ONLY0-NEXT:    [[TMP590:%.*]] = load i16, ptr [[SE]], align 2
30350 // SIMD-ONLY0-NEXT:    [[CONV1426:%.*]] = sext i16 [[TMP590]] to i32
30351 // SIMD-ONLY0-NEXT:    br label [[COND_END1429:%.*]]
30352 // SIMD-ONLY0:       cond.false1427:
30353 // SIMD-ONLY0-NEXT:    [[TMP591:%.*]] = load i16, ptr [[SX]], align 2
30354 // SIMD-ONLY0-NEXT:    [[CONV1428:%.*]] = sext i16 [[TMP591]] to i32
30355 // SIMD-ONLY0-NEXT:    br label [[COND_END1429]]
30356 // SIMD-ONLY0:       cond.end1429:
30357 // SIMD-ONLY0-NEXT:    [[COND1430:%.*]] = phi i32 [ [[CONV1426]], [[COND_TRUE1425]] ], [ [[CONV1428]], [[COND_FALSE1427]] ]
30358 // SIMD-ONLY0-NEXT:    [[CONV1431:%.*]] = trunc i32 [[COND1430]] to i16
30359 // SIMD-ONLY0-NEXT:    store i16 [[CONV1431]], ptr [[SX]], align 2
30360 // SIMD-ONLY0-NEXT:    [[TMP592:%.*]] = load i16, ptr [[SX]], align 2
30361 // SIMD-ONLY0-NEXT:    [[CONV1432:%.*]] = sext i16 [[TMP592]] to i32
30362 // SIMD-ONLY0-NEXT:    [[TMP593:%.*]] = load i16, ptr [[SE]], align 2
30363 // SIMD-ONLY0-NEXT:    [[CONV1433:%.*]] = sext i16 [[TMP593]] to i32
30364 // SIMD-ONLY0-NEXT:    [[CMP1434:%.*]] = icmp slt i32 [[CONV1432]], [[CONV1433]]
30365 // SIMD-ONLY0-NEXT:    br i1 [[CMP1434]], label [[COND_TRUE1436:%.*]], label [[COND_FALSE1438:%.*]]
30366 // SIMD-ONLY0:       cond.true1436:
30367 // SIMD-ONLY0-NEXT:    [[TMP594:%.*]] = load i16, ptr [[SE]], align 2
30368 // SIMD-ONLY0-NEXT:    [[CONV1437:%.*]] = sext i16 [[TMP594]] to i32
30369 // SIMD-ONLY0-NEXT:    br label [[COND_END1440:%.*]]
30370 // SIMD-ONLY0:       cond.false1438:
30371 // SIMD-ONLY0-NEXT:    [[TMP595:%.*]] = load i16, ptr [[SX]], align 2
30372 // SIMD-ONLY0-NEXT:    [[CONV1439:%.*]] = sext i16 [[TMP595]] to i32
30373 // SIMD-ONLY0-NEXT:    br label [[COND_END1440]]
30374 // SIMD-ONLY0:       cond.end1440:
30375 // SIMD-ONLY0-NEXT:    [[COND1441:%.*]] = phi i32 [ [[CONV1437]], [[COND_TRUE1436]] ], [ [[CONV1439]], [[COND_FALSE1438]] ]
30376 // SIMD-ONLY0-NEXT:    [[CONV1442:%.*]] = trunc i32 [[COND1441]] to i16
30377 // SIMD-ONLY0-NEXT:    store i16 [[CONV1442]], ptr [[SX]], align 2
30378 // SIMD-ONLY0-NEXT:    [[TMP596:%.*]] = load i16, ptr [[SE]], align 2
30379 // SIMD-ONLY0-NEXT:    [[CONV1443:%.*]] = sext i16 [[TMP596]] to i32
30380 // SIMD-ONLY0-NEXT:    [[TMP597:%.*]] = load i16, ptr [[SX]], align 2
30381 // SIMD-ONLY0-NEXT:    [[CONV1444:%.*]] = sext i16 [[TMP597]] to i32
30382 // SIMD-ONLY0-NEXT:    [[CMP1445:%.*]] = icmp sgt i32 [[CONV1443]], [[CONV1444]]
30383 // SIMD-ONLY0-NEXT:    br i1 [[CMP1445]], label [[COND_TRUE1447:%.*]], label [[COND_FALSE1449:%.*]]
30384 // SIMD-ONLY0:       cond.true1447:
30385 // SIMD-ONLY0-NEXT:    [[TMP598:%.*]] = load i16, ptr [[SE]], align 2
30386 // SIMD-ONLY0-NEXT:    [[CONV1448:%.*]] = sext i16 [[TMP598]] to i32
30387 // SIMD-ONLY0-NEXT:    br label [[COND_END1451:%.*]]
30388 // SIMD-ONLY0:       cond.false1449:
30389 // SIMD-ONLY0-NEXT:    [[TMP599:%.*]] = load i16, ptr [[SX]], align 2
30390 // SIMD-ONLY0-NEXT:    [[CONV1450:%.*]] = sext i16 [[TMP599]] to i32
30391 // SIMD-ONLY0-NEXT:    br label [[COND_END1451]]
30392 // SIMD-ONLY0:       cond.end1451:
30393 // SIMD-ONLY0-NEXT:    [[COND1452:%.*]] = phi i32 [ [[CONV1448]], [[COND_TRUE1447]] ], [ [[CONV1450]], [[COND_FALSE1449]] ]
30394 // SIMD-ONLY0-NEXT:    [[CONV1453:%.*]] = trunc i32 [[COND1452]] to i16
30395 // SIMD-ONLY0-NEXT:    store i16 [[CONV1453]], ptr [[SX]], align 2
30396 // SIMD-ONLY0-NEXT:    [[TMP600:%.*]] = load i16, ptr [[SE]], align 2
30397 // SIMD-ONLY0-NEXT:    [[CONV1454:%.*]] = sext i16 [[TMP600]] to i32
30398 // SIMD-ONLY0-NEXT:    [[TMP601:%.*]] = load i16, ptr [[SX]], align 2
30399 // SIMD-ONLY0-NEXT:    [[CONV1455:%.*]] = sext i16 [[TMP601]] to i32
30400 // SIMD-ONLY0-NEXT:    [[CMP1456:%.*]] = icmp slt i32 [[CONV1454]], [[CONV1455]]
30401 // SIMD-ONLY0-NEXT:    br i1 [[CMP1456]], label [[COND_TRUE1458:%.*]], label [[COND_FALSE1460:%.*]]
30402 // SIMD-ONLY0:       cond.true1458:
30403 // SIMD-ONLY0-NEXT:    [[TMP602:%.*]] = load i16, ptr [[SE]], align 2
30404 // SIMD-ONLY0-NEXT:    [[CONV1459:%.*]] = sext i16 [[TMP602]] to i32
30405 // SIMD-ONLY0-NEXT:    br label [[COND_END1462:%.*]]
30406 // SIMD-ONLY0:       cond.false1460:
30407 // SIMD-ONLY0-NEXT:    [[TMP603:%.*]] = load i16, ptr [[SX]], align 2
30408 // SIMD-ONLY0-NEXT:    [[CONV1461:%.*]] = sext i16 [[TMP603]] to i32
30409 // SIMD-ONLY0-NEXT:    br label [[COND_END1462]]
30410 // SIMD-ONLY0:       cond.end1462:
30411 // SIMD-ONLY0-NEXT:    [[COND1463:%.*]] = phi i32 [ [[CONV1459]], [[COND_TRUE1458]] ], [ [[CONV1461]], [[COND_FALSE1460]] ]
30412 // SIMD-ONLY0-NEXT:    [[CONV1464:%.*]] = trunc i32 [[COND1463]] to i16
30413 // SIMD-ONLY0-NEXT:    store i16 [[CONV1464]], ptr [[SX]], align 2
30414 // SIMD-ONLY0-NEXT:    [[TMP604:%.*]] = load i16, ptr [[SX]], align 2
30415 // SIMD-ONLY0-NEXT:    [[CONV1465:%.*]] = sext i16 [[TMP604]] to i32
30416 // SIMD-ONLY0-NEXT:    [[TMP605:%.*]] = load i16, ptr [[SE]], align 2
30417 // SIMD-ONLY0-NEXT:    [[CONV1466:%.*]] = sext i16 [[TMP605]] to i32
30418 // SIMD-ONLY0-NEXT:    [[CMP1467:%.*]] = icmp sgt i32 [[CONV1465]], [[CONV1466]]
30419 // SIMD-ONLY0-NEXT:    br i1 [[CMP1467]], label [[IF_THEN1469:%.*]], label [[IF_END1470:%.*]]
30420 // SIMD-ONLY0:       if.then1469:
30421 // SIMD-ONLY0-NEXT:    [[TMP606:%.*]] = load i16, ptr [[SE]], align 2
30422 // SIMD-ONLY0-NEXT:    store i16 [[TMP606]], ptr [[SX]], align 2
30423 // SIMD-ONLY0-NEXT:    br label [[IF_END1470]]
30424 // SIMD-ONLY0:       if.end1470:
30425 // SIMD-ONLY0-NEXT:    [[TMP607:%.*]] = load i16, ptr [[SX]], align 2
30426 // SIMD-ONLY0-NEXT:    [[CONV1471:%.*]] = sext i16 [[TMP607]] to i32
30427 // SIMD-ONLY0-NEXT:    [[TMP608:%.*]] = load i16, ptr [[SE]], align 2
30428 // SIMD-ONLY0-NEXT:    [[CONV1472:%.*]] = sext i16 [[TMP608]] to i32
30429 // SIMD-ONLY0-NEXT:    [[CMP1473:%.*]] = icmp slt i32 [[CONV1471]], [[CONV1472]]
30430 // SIMD-ONLY0-NEXT:    br i1 [[CMP1473]], label [[IF_THEN1475:%.*]], label [[IF_END1476:%.*]]
30431 // SIMD-ONLY0:       if.then1475:
30432 // SIMD-ONLY0-NEXT:    [[TMP609:%.*]] = load i16, ptr [[SE]], align 2
30433 // SIMD-ONLY0-NEXT:    store i16 [[TMP609]], ptr [[SX]], align 2
30434 // SIMD-ONLY0-NEXT:    br label [[IF_END1476]]
30435 // SIMD-ONLY0:       if.end1476:
30436 // SIMD-ONLY0-NEXT:    [[TMP610:%.*]] = load i16, ptr [[SE]], align 2
30437 // SIMD-ONLY0-NEXT:    [[CONV1477:%.*]] = sext i16 [[TMP610]] to i32
30438 // SIMD-ONLY0-NEXT:    [[TMP611:%.*]] = load i16, ptr [[SX]], align 2
30439 // SIMD-ONLY0-NEXT:    [[CONV1478:%.*]] = sext i16 [[TMP611]] to i32
30440 // SIMD-ONLY0-NEXT:    [[CMP1479:%.*]] = icmp sgt i32 [[CONV1477]], [[CONV1478]]
30441 // SIMD-ONLY0-NEXT:    br i1 [[CMP1479]], label [[IF_THEN1481:%.*]], label [[IF_END1482:%.*]]
30442 // SIMD-ONLY0:       if.then1481:
30443 // SIMD-ONLY0-NEXT:    [[TMP612:%.*]] = load i16, ptr [[SE]], align 2
30444 // SIMD-ONLY0-NEXT:    store i16 [[TMP612]], ptr [[SX]], align 2
30445 // SIMD-ONLY0-NEXT:    br label [[IF_END1482]]
30446 // SIMD-ONLY0:       if.end1482:
30447 // SIMD-ONLY0-NEXT:    [[TMP613:%.*]] = load i16, ptr [[SE]], align 2
30448 // SIMD-ONLY0-NEXT:    [[CONV1483:%.*]] = sext i16 [[TMP613]] to i32
30449 // SIMD-ONLY0-NEXT:    [[TMP614:%.*]] = load i16, ptr [[SX]], align 2
30450 // SIMD-ONLY0-NEXT:    [[CONV1484:%.*]] = sext i16 [[TMP614]] to i32
30451 // SIMD-ONLY0-NEXT:    [[CMP1485:%.*]] = icmp slt i32 [[CONV1483]], [[CONV1484]]
30452 // SIMD-ONLY0-NEXT:    br i1 [[CMP1485]], label [[IF_THEN1487:%.*]], label [[IF_END1488:%.*]]
30453 // SIMD-ONLY0:       if.then1487:
30454 // SIMD-ONLY0-NEXT:    [[TMP615:%.*]] = load i16, ptr [[SE]], align 2
30455 // SIMD-ONLY0-NEXT:    store i16 [[TMP615]], ptr [[SX]], align 2
30456 // SIMD-ONLY0-NEXT:    br label [[IF_END1488]]
30457 // SIMD-ONLY0:       if.end1488:
30458 // SIMD-ONLY0-NEXT:    [[TMP616:%.*]] = load i16, ptr [[SX]], align 2
30459 // SIMD-ONLY0-NEXT:    [[CONV1489:%.*]] = sext i16 [[TMP616]] to i32
30460 // SIMD-ONLY0-NEXT:    [[TMP617:%.*]] = load i16, ptr [[SE]], align 2
30461 // SIMD-ONLY0-NEXT:    [[CONV1490:%.*]] = sext i16 [[TMP617]] to i32
30462 // SIMD-ONLY0-NEXT:    [[CMP1491:%.*]] = icmp eq i32 [[CONV1489]], [[CONV1490]]
30463 // SIMD-ONLY0-NEXT:    br i1 [[CMP1491]], label [[COND_TRUE1493:%.*]], label [[COND_FALSE1495:%.*]]
30464 // SIMD-ONLY0:       cond.true1493:
30465 // SIMD-ONLY0-NEXT:    [[TMP618:%.*]] = load i16, ptr [[SD]], align 2
30466 // SIMD-ONLY0-NEXT:    [[CONV1494:%.*]] = sext i16 [[TMP618]] to i32
30467 // SIMD-ONLY0-NEXT:    br label [[COND_END1497:%.*]]
30468 // SIMD-ONLY0:       cond.false1495:
30469 // SIMD-ONLY0-NEXT:    [[TMP619:%.*]] = load i16, ptr [[SX]], align 2
30470 // SIMD-ONLY0-NEXT:    [[CONV1496:%.*]] = sext i16 [[TMP619]] to i32
30471 // SIMD-ONLY0-NEXT:    br label [[COND_END1497]]
30472 // SIMD-ONLY0:       cond.end1497:
30473 // SIMD-ONLY0-NEXT:    [[COND1498:%.*]] = phi i32 [ [[CONV1494]], [[COND_TRUE1493]] ], [ [[CONV1496]], [[COND_FALSE1495]] ]
30474 // SIMD-ONLY0-NEXT:    [[CONV1499:%.*]] = trunc i32 [[COND1498]] to i16
30475 // SIMD-ONLY0-NEXT:    store i16 [[CONV1499]], ptr [[SX]], align 2
30476 // SIMD-ONLY0-NEXT:    [[TMP620:%.*]] = load i16, ptr [[SE]], align 2
30477 // SIMD-ONLY0-NEXT:    [[CONV1500:%.*]] = sext i16 [[TMP620]] to i32
30478 // SIMD-ONLY0-NEXT:    [[TMP621:%.*]] = load i16, ptr [[SX]], align 2
30479 // SIMD-ONLY0-NEXT:    [[CONV1501:%.*]] = sext i16 [[TMP621]] to i32
30480 // SIMD-ONLY0-NEXT:    [[CMP1502:%.*]] = icmp eq i32 [[CONV1500]], [[CONV1501]]
30481 // SIMD-ONLY0-NEXT:    br i1 [[CMP1502]], label [[COND_TRUE1504:%.*]], label [[COND_FALSE1506:%.*]]
30482 // SIMD-ONLY0:       cond.true1504:
30483 // SIMD-ONLY0-NEXT:    [[TMP622:%.*]] = load i16, ptr [[SD]], align 2
30484 // SIMD-ONLY0-NEXT:    [[CONV1505:%.*]] = sext i16 [[TMP622]] to i32
30485 // SIMD-ONLY0-NEXT:    br label [[COND_END1508:%.*]]
30486 // SIMD-ONLY0:       cond.false1506:
30487 // SIMD-ONLY0-NEXT:    [[TMP623:%.*]] = load i16, ptr [[SX]], align 2
30488 // SIMD-ONLY0-NEXT:    [[CONV1507:%.*]] = sext i16 [[TMP623]] to i32
30489 // SIMD-ONLY0-NEXT:    br label [[COND_END1508]]
30490 // SIMD-ONLY0:       cond.end1508:
30491 // SIMD-ONLY0-NEXT:    [[COND1509:%.*]] = phi i32 [ [[CONV1505]], [[COND_TRUE1504]] ], [ [[CONV1507]], [[COND_FALSE1506]] ]
30492 // SIMD-ONLY0-NEXT:    [[CONV1510:%.*]] = trunc i32 [[COND1509]] to i16
30493 // SIMD-ONLY0-NEXT:    store i16 [[CONV1510]], ptr [[SX]], align 2
30494 // SIMD-ONLY0-NEXT:    [[TMP624:%.*]] = load i16, ptr [[SX]], align 2
30495 // SIMD-ONLY0-NEXT:    [[CONV1511:%.*]] = sext i16 [[TMP624]] to i32
30496 // SIMD-ONLY0-NEXT:    [[TMP625:%.*]] = load i16, ptr [[SE]], align 2
30497 // SIMD-ONLY0-NEXT:    [[CONV1512:%.*]] = sext i16 [[TMP625]] to i32
30498 // SIMD-ONLY0-NEXT:    [[CMP1513:%.*]] = icmp eq i32 [[CONV1511]], [[CONV1512]]
30499 // SIMD-ONLY0-NEXT:    br i1 [[CMP1513]], label [[IF_THEN1515:%.*]], label [[IF_END1516:%.*]]
30500 // SIMD-ONLY0:       if.then1515:
30501 // SIMD-ONLY0-NEXT:    [[TMP626:%.*]] = load i16, ptr [[SD]], align 2
30502 // SIMD-ONLY0-NEXT:    store i16 [[TMP626]], ptr [[SX]], align 2
30503 // SIMD-ONLY0-NEXT:    br label [[IF_END1516]]
30504 // SIMD-ONLY0:       if.end1516:
30505 // SIMD-ONLY0-NEXT:    [[TMP627:%.*]] = load i16, ptr [[SE]], align 2
30506 // SIMD-ONLY0-NEXT:    [[CONV1517:%.*]] = sext i16 [[TMP627]] to i32
30507 // SIMD-ONLY0-NEXT:    [[TMP628:%.*]] = load i16, ptr [[SX]], align 2
30508 // SIMD-ONLY0-NEXT:    [[CONV1518:%.*]] = sext i16 [[TMP628]] to i32
30509 // SIMD-ONLY0-NEXT:    [[CMP1519:%.*]] = icmp eq i32 [[CONV1517]], [[CONV1518]]
30510 // SIMD-ONLY0-NEXT:    br i1 [[CMP1519]], label [[IF_THEN1521:%.*]], label [[IF_END1522:%.*]]
30511 // SIMD-ONLY0:       if.then1521:
30512 // SIMD-ONLY0-NEXT:    [[TMP629:%.*]] = load i16, ptr [[SD]], align 2
30513 // SIMD-ONLY0-NEXT:    store i16 [[TMP629]], ptr [[SX]], align 2
30514 // SIMD-ONLY0-NEXT:    br label [[IF_END1522]]
30515 // SIMD-ONLY0:       if.end1522:
30516 // SIMD-ONLY0-NEXT:    [[TMP630:%.*]] = load i16, ptr [[USX]], align 2
30517 // SIMD-ONLY0-NEXT:    [[CONV1523:%.*]] = zext i16 [[TMP630]] to i32
30518 // SIMD-ONLY0-NEXT:    [[TMP631:%.*]] = load i16, ptr [[USE]], align 2
30519 // SIMD-ONLY0-NEXT:    [[CONV1524:%.*]] = zext i16 [[TMP631]] to i32
30520 // SIMD-ONLY0-NEXT:    [[CMP1525:%.*]] = icmp sgt i32 [[CONV1523]], [[CONV1524]]
30521 // SIMD-ONLY0-NEXT:    br i1 [[CMP1525]], label [[COND_TRUE1527:%.*]], label [[COND_FALSE1529:%.*]]
30522 // SIMD-ONLY0:       cond.true1527:
30523 // SIMD-ONLY0-NEXT:    [[TMP632:%.*]] = load i16, ptr [[USE]], align 2
30524 // SIMD-ONLY0-NEXT:    [[CONV1528:%.*]] = zext i16 [[TMP632]] to i32
30525 // SIMD-ONLY0-NEXT:    br label [[COND_END1531:%.*]]
30526 // SIMD-ONLY0:       cond.false1529:
30527 // SIMD-ONLY0-NEXT:    [[TMP633:%.*]] = load i16, ptr [[USX]], align 2
30528 // SIMD-ONLY0-NEXT:    [[CONV1530:%.*]] = zext i16 [[TMP633]] to i32
30529 // SIMD-ONLY0-NEXT:    br label [[COND_END1531]]
30530 // SIMD-ONLY0:       cond.end1531:
30531 // SIMD-ONLY0-NEXT:    [[COND1532:%.*]] = phi i32 [ [[CONV1528]], [[COND_TRUE1527]] ], [ [[CONV1530]], [[COND_FALSE1529]] ]
30532 // SIMD-ONLY0-NEXT:    [[CONV1533:%.*]] = trunc i32 [[COND1532]] to i16
30533 // SIMD-ONLY0-NEXT:    store i16 [[CONV1533]], ptr [[USX]], align 2
30534 // SIMD-ONLY0-NEXT:    [[TMP634:%.*]] = load i16, ptr [[USX]], align 2
30535 // SIMD-ONLY0-NEXT:    [[CONV1534:%.*]] = zext i16 [[TMP634]] to i32
30536 // SIMD-ONLY0-NEXT:    [[TMP635:%.*]] = load i16, ptr [[USE]], align 2
30537 // SIMD-ONLY0-NEXT:    [[CONV1535:%.*]] = zext i16 [[TMP635]] to i32
30538 // SIMD-ONLY0-NEXT:    [[CMP1536:%.*]] = icmp slt i32 [[CONV1534]], [[CONV1535]]
30539 // SIMD-ONLY0-NEXT:    br i1 [[CMP1536]], label [[COND_TRUE1538:%.*]], label [[COND_FALSE1540:%.*]]
30540 // SIMD-ONLY0:       cond.true1538:
30541 // SIMD-ONLY0-NEXT:    [[TMP636:%.*]] = load i16, ptr [[USE]], align 2
30542 // SIMD-ONLY0-NEXT:    [[CONV1539:%.*]] = zext i16 [[TMP636]] to i32
30543 // SIMD-ONLY0-NEXT:    br label [[COND_END1542:%.*]]
30544 // SIMD-ONLY0:       cond.false1540:
30545 // SIMD-ONLY0-NEXT:    [[TMP637:%.*]] = load i16, ptr [[USX]], align 2
30546 // SIMD-ONLY0-NEXT:    [[CONV1541:%.*]] = zext i16 [[TMP637]] to i32
30547 // SIMD-ONLY0-NEXT:    br label [[COND_END1542]]
30548 // SIMD-ONLY0:       cond.end1542:
30549 // SIMD-ONLY0-NEXT:    [[COND1543:%.*]] = phi i32 [ [[CONV1539]], [[COND_TRUE1538]] ], [ [[CONV1541]], [[COND_FALSE1540]] ]
30550 // SIMD-ONLY0-NEXT:    [[CONV1544:%.*]] = trunc i32 [[COND1543]] to i16
30551 // SIMD-ONLY0-NEXT:    store i16 [[CONV1544]], ptr [[USX]], align 2
30552 // SIMD-ONLY0-NEXT:    [[TMP638:%.*]] = load i16, ptr [[USE]], align 2
30553 // SIMD-ONLY0-NEXT:    [[CONV1545:%.*]] = zext i16 [[TMP638]] to i32
30554 // SIMD-ONLY0-NEXT:    [[TMP639:%.*]] = load i16, ptr [[USX]], align 2
30555 // SIMD-ONLY0-NEXT:    [[CONV1546:%.*]] = zext i16 [[TMP639]] to i32
30556 // SIMD-ONLY0-NEXT:    [[CMP1547:%.*]] = icmp sgt i32 [[CONV1545]], [[CONV1546]]
30557 // SIMD-ONLY0-NEXT:    br i1 [[CMP1547]], label [[COND_TRUE1549:%.*]], label [[COND_FALSE1551:%.*]]
30558 // SIMD-ONLY0:       cond.true1549:
30559 // SIMD-ONLY0-NEXT:    [[TMP640:%.*]] = load i16, ptr [[USE]], align 2
30560 // SIMD-ONLY0-NEXT:    [[CONV1550:%.*]] = zext i16 [[TMP640]] to i32
30561 // SIMD-ONLY0-NEXT:    br label [[COND_END1553:%.*]]
30562 // SIMD-ONLY0:       cond.false1551:
30563 // SIMD-ONLY0-NEXT:    [[TMP641:%.*]] = load i16, ptr [[USX]], align 2
30564 // SIMD-ONLY0-NEXT:    [[CONV1552:%.*]] = zext i16 [[TMP641]] to i32
30565 // SIMD-ONLY0-NEXT:    br label [[COND_END1553]]
30566 // SIMD-ONLY0:       cond.end1553:
30567 // SIMD-ONLY0-NEXT:    [[COND1554:%.*]] = phi i32 [ [[CONV1550]], [[COND_TRUE1549]] ], [ [[CONV1552]], [[COND_FALSE1551]] ]
30568 // SIMD-ONLY0-NEXT:    [[CONV1555:%.*]] = trunc i32 [[COND1554]] to i16
30569 // SIMD-ONLY0-NEXT:    store i16 [[CONV1555]], ptr [[USX]], align 2
30570 // SIMD-ONLY0-NEXT:    [[TMP642:%.*]] = load i16, ptr [[USE]], align 2
30571 // SIMD-ONLY0-NEXT:    [[CONV1556:%.*]] = zext i16 [[TMP642]] to i32
30572 // SIMD-ONLY0-NEXT:    [[TMP643:%.*]] = load i16, ptr [[USX]], align 2
30573 // SIMD-ONLY0-NEXT:    [[CONV1557:%.*]] = zext i16 [[TMP643]] to i32
30574 // SIMD-ONLY0-NEXT:    [[CMP1558:%.*]] = icmp slt i32 [[CONV1556]], [[CONV1557]]
30575 // SIMD-ONLY0-NEXT:    br i1 [[CMP1558]], label [[COND_TRUE1560:%.*]], label [[COND_FALSE1562:%.*]]
30576 // SIMD-ONLY0:       cond.true1560:
30577 // SIMD-ONLY0-NEXT:    [[TMP644:%.*]] = load i16, ptr [[USE]], align 2
30578 // SIMD-ONLY0-NEXT:    [[CONV1561:%.*]] = zext i16 [[TMP644]] to i32
30579 // SIMD-ONLY0-NEXT:    br label [[COND_END1564:%.*]]
30580 // SIMD-ONLY0:       cond.false1562:
30581 // SIMD-ONLY0-NEXT:    [[TMP645:%.*]] = load i16, ptr [[USX]], align 2
30582 // SIMD-ONLY0-NEXT:    [[CONV1563:%.*]] = zext i16 [[TMP645]] to i32
30583 // SIMD-ONLY0-NEXT:    br label [[COND_END1564]]
30584 // SIMD-ONLY0:       cond.end1564:
30585 // SIMD-ONLY0-NEXT:    [[COND1565:%.*]] = phi i32 [ [[CONV1561]], [[COND_TRUE1560]] ], [ [[CONV1563]], [[COND_FALSE1562]] ]
30586 // SIMD-ONLY0-NEXT:    [[CONV1566:%.*]] = trunc i32 [[COND1565]] to i16
30587 // SIMD-ONLY0-NEXT:    store i16 [[CONV1566]], ptr [[USX]], align 2
30588 // SIMD-ONLY0-NEXT:    [[TMP646:%.*]] = load i16, ptr [[USX]], align 2
30589 // SIMD-ONLY0-NEXT:    [[CONV1567:%.*]] = zext i16 [[TMP646]] to i32
30590 // SIMD-ONLY0-NEXT:    [[TMP647:%.*]] = load i16, ptr [[USE]], align 2
30591 // SIMD-ONLY0-NEXT:    [[CONV1568:%.*]] = zext i16 [[TMP647]] to i32
30592 // SIMD-ONLY0-NEXT:    [[CMP1569:%.*]] = icmp sgt i32 [[CONV1567]], [[CONV1568]]
30593 // SIMD-ONLY0-NEXT:    br i1 [[CMP1569]], label [[IF_THEN1571:%.*]], label [[IF_END1572:%.*]]
30594 // SIMD-ONLY0:       if.then1571:
30595 // SIMD-ONLY0-NEXT:    [[TMP648:%.*]] = load i16, ptr [[USE]], align 2
30596 // SIMD-ONLY0-NEXT:    store i16 [[TMP648]], ptr [[USX]], align 2
30597 // SIMD-ONLY0-NEXT:    br label [[IF_END1572]]
30598 // SIMD-ONLY0:       if.end1572:
30599 // SIMD-ONLY0-NEXT:    [[TMP649:%.*]] = load i16, ptr [[USX]], align 2
30600 // SIMD-ONLY0-NEXT:    [[CONV1573:%.*]] = zext i16 [[TMP649]] to i32
30601 // SIMD-ONLY0-NEXT:    [[TMP650:%.*]] = load i16, ptr [[USE]], align 2
30602 // SIMD-ONLY0-NEXT:    [[CONV1574:%.*]] = zext i16 [[TMP650]] to i32
30603 // SIMD-ONLY0-NEXT:    [[CMP1575:%.*]] = icmp slt i32 [[CONV1573]], [[CONV1574]]
30604 // SIMD-ONLY0-NEXT:    br i1 [[CMP1575]], label [[IF_THEN1577:%.*]], label [[IF_END1578:%.*]]
30605 // SIMD-ONLY0:       if.then1577:
30606 // SIMD-ONLY0-NEXT:    [[TMP651:%.*]] = load i16, ptr [[USE]], align 2
30607 // SIMD-ONLY0-NEXT:    store i16 [[TMP651]], ptr [[USX]], align 2
30608 // SIMD-ONLY0-NEXT:    br label [[IF_END1578]]
30609 // SIMD-ONLY0:       if.end1578:
30610 // SIMD-ONLY0-NEXT:    [[TMP652:%.*]] = load i16, ptr [[USE]], align 2
30611 // SIMD-ONLY0-NEXT:    [[CONV1579:%.*]] = zext i16 [[TMP652]] to i32
30612 // SIMD-ONLY0-NEXT:    [[TMP653:%.*]] = load i16, ptr [[USX]], align 2
30613 // SIMD-ONLY0-NEXT:    [[CONV1580:%.*]] = zext i16 [[TMP653]] to i32
30614 // SIMD-ONLY0-NEXT:    [[CMP1581:%.*]] = icmp sgt i32 [[CONV1579]], [[CONV1580]]
30615 // SIMD-ONLY0-NEXT:    br i1 [[CMP1581]], label [[IF_THEN1583:%.*]], label [[IF_END1584:%.*]]
30616 // SIMD-ONLY0:       if.then1583:
30617 // SIMD-ONLY0-NEXT:    [[TMP654:%.*]] = load i16, ptr [[USE]], align 2
30618 // SIMD-ONLY0-NEXT:    store i16 [[TMP654]], ptr [[USX]], align 2
30619 // SIMD-ONLY0-NEXT:    br label [[IF_END1584]]
30620 // SIMD-ONLY0:       if.end1584:
30621 // SIMD-ONLY0-NEXT:    [[TMP655:%.*]] = load i16, ptr [[USE]], align 2
30622 // SIMD-ONLY0-NEXT:    [[CONV1585:%.*]] = zext i16 [[TMP655]] to i32
30623 // SIMD-ONLY0-NEXT:    [[TMP656:%.*]] = load i16, ptr [[USX]], align 2
30624 // SIMD-ONLY0-NEXT:    [[CONV1586:%.*]] = zext i16 [[TMP656]] to i32
30625 // SIMD-ONLY0-NEXT:    [[CMP1587:%.*]] = icmp slt i32 [[CONV1585]], [[CONV1586]]
30626 // SIMD-ONLY0-NEXT:    br i1 [[CMP1587]], label [[IF_THEN1589:%.*]], label [[IF_END1590:%.*]]
30627 // SIMD-ONLY0:       if.then1589:
30628 // SIMD-ONLY0-NEXT:    [[TMP657:%.*]] = load i16, ptr [[USE]], align 2
30629 // SIMD-ONLY0-NEXT:    store i16 [[TMP657]], ptr [[USX]], align 2
30630 // SIMD-ONLY0-NEXT:    br label [[IF_END1590]]
30631 // SIMD-ONLY0:       if.end1590:
30632 // SIMD-ONLY0-NEXT:    [[TMP658:%.*]] = load i16, ptr [[USX]], align 2
30633 // SIMD-ONLY0-NEXT:    [[CONV1591:%.*]] = zext i16 [[TMP658]] to i32
30634 // SIMD-ONLY0-NEXT:    [[TMP659:%.*]] = load i16, ptr [[USE]], align 2
30635 // SIMD-ONLY0-NEXT:    [[CONV1592:%.*]] = zext i16 [[TMP659]] to i32
30636 // SIMD-ONLY0-NEXT:    [[CMP1593:%.*]] = icmp eq i32 [[CONV1591]], [[CONV1592]]
30637 // SIMD-ONLY0-NEXT:    br i1 [[CMP1593]], label [[COND_TRUE1595:%.*]], label [[COND_FALSE1597:%.*]]
30638 // SIMD-ONLY0:       cond.true1595:
30639 // SIMD-ONLY0-NEXT:    [[TMP660:%.*]] = load i16, ptr [[USD]], align 2
30640 // SIMD-ONLY0-NEXT:    [[CONV1596:%.*]] = zext i16 [[TMP660]] to i32
30641 // SIMD-ONLY0-NEXT:    br label [[COND_END1599:%.*]]
30642 // SIMD-ONLY0:       cond.false1597:
30643 // SIMD-ONLY0-NEXT:    [[TMP661:%.*]] = load i16, ptr [[USX]], align 2
30644 // SIMD-ONLY0-NEXT:    [[CONV1598:%.*]] = zext i16 [[TMP661]] to i32
30645 // SIMD-ONLY0-NEXT:    br label [[COND_END1599]]
30646 // SIMD-ONLY0:       cond.end1599:
30647 // SIMD-ONLY0-NEXT:    [[COND1600:%.*]] = phi i32 [ [[CONV1596]], [[COND_TRUE1595]] ], [ [[CONV1598]], [[COND_FALSE1597]] ]
30648 // SIMD-ONLY0-NEXT:    [[CONV1601:%.*]] = trunc i32 [[COND1600]] to i16
30649 // SIMD-ONLY0-NEXT:    store i16 [[CONV1601]], ptr [[USX]], align 2
30650 // SIMD-ONLY0-NEXT:    [[TMP662:%.*]] = load i16, ptr [[USE]], align 2
30651 // SIMD-ONLY0-NEXT:    [[CONV1602:%.*]] = zext i16 [[TMP662]] to i32
30652 // SIMD-ONLY0-NEXT:    [[TMP663:%.*]] = load i16, ptr [[USX]], align 2
30653 // SIMD-ONLY0-NEXT:    [[CONV1603:%.*]] = zext i16 [[TMP663]] to i32
30654 // SIMD-ONLY0-NEXT:    [[CMP1604:%.*]] = icmp eq i32 [[CONV1602]], [[CONV1603]]
30655 // SIMD-ONLY0-NEXT:    br i1 [[CMP1604]], label [[COND_TRUE1606:%.*]], label [[COND_FALSE1608:%.*]]
30656 // SIMD-ONLY0:       cond.true1606:
30657 // SIMD-ONLY0-NEXT:    [[TMP664:%.*]] = load i16, ptr [[USD]], align 2
30658 // SIMD-ONLY0-NEXT:    [[CONV1607:%.*]] = zext i16 [[TMP664]] to i32
30659 // SIMD-ONLY0-NEXT:    br label [[COND_END1610:%.*]]
30660 // SIMD-ONLY0:       cond.false1608:
30661 // SIMD-ONLY0-NEXT:    [[TMP665:%.*]] = load i16, ptr [[USX]], align 2
30662 // SIMD-ONLY0-NEXT:    [[CONV1609:%.*]] = zext i16 [[TMP665]] to i32
30663 // SIMD-ONLY0-NEXT:    br label [[COND_END1610]]
30664 // SIMD-ONLY0:       cond.end1610:
30665 // SIMD-ONLY0-NEXT:    [[COND1611:%.*]] = phi i32 [ [[CONV1607]], [[COND_TRUE1606]] ], [ [[CONV1609]], [[COND_FALSE1608]] ]
30666 // SIMD-ONLY0-NEXT:    [[CONV1612:%.*]] = trunc i32 [[COND1611]] to i16
30667 // SIMD-ONLY0-NEXT:    store i16 [[CONV1612]], ptr [[USX]], align 2
30668 // SIMD-ONLY0-NEXT:    [[TMP666:%.*]] = load i16, ptr [[USX]], align 2
30669 // SIMD-ONLY0-NEXT:    [[CONV1613:%.*]] = zext i16 [[TMP666]] to i32
30670 // SIMD-ONLY0-NEXT:    [[TMP667:%.*]] = load i16, ptr [[USE]], align 2
30671 // SIMD-ONLY0-NEXT:    [[CONV1614:%.*]] = zext i16 [[TMP667]] to i32
30672 // SIMD-ONLY0-NEXT:    [[CMP1615:%.*]] = icmp eq i32 [[CONV1613]], [[CONV1614]]
30673 // SIMD-ONLY0-NEXT:    br i1 [[CMP1615]], label [[IF_THEN1617:%.*]], label [[IF_END1618:%.*]]
30674 // SIMD-ONLY0:       if.then1617:
30675 // SIMD-ONLY0-NEXT:    [[TMP668:%.*]] = load i16, ptr [[USD]], align 2
30676 // SIMD-ONLY0-NEXT:    store i16 [[TMP668]], ptr [[USX]], align 2
30677 // SIMD-ONLY0-NEXT:    br label [[IF_END1618]]
30678 // SIMD-ONLY0:       if.end1618:
30679 // SIMD-ONLY0-NEXT:    [[TMP669:%.*]] = load i16, ptr [[USE]], align 2
30680 // SIMD-ONLY0-NEXT:    [[CONV1619:%.*]] = zext i16 [[TMP669]] to i32
30681 // SIMD-ONLY0-NEXT:    [[TMP670:%.*]] = load i16, ptr [[USX]], align 2
30682 // SIMD-ONLY0-NEXT:    [[CONV1620:%.*]] = zext i16 [[TMP670]] to i32
30683 // SIMD-ONLY0-NEXT:    [[CMP1621:%.*]] = icmp eq i32 [[CONV1619]], [[CONV1620]]
30684 // SIMD-ONLY0-NEXT:    br i1 [[CMP1621]], label [[IF_THEN1623:%.*]], label [[IF_END1624:%.*]]
30685 // SIMD-ONLY0:       if.then1623:
30686 // SIMD-ONLY0-NEXT:    [[TMP671:%.*]] = load i16, ptr [[USD]], align 2
30687 // SIMD-ONLY0-NEXT:    store i16 [[TMP671]], ptr [[USX]], align 2
30688 // SIMD-ONLY0-NEXT:    br label [[IF_END1624]]
30689 // SIMD-ONLY0:       if.end1624:
30690 // SIMD-ONLY0-NEXT:    [[TMP672:%.*]] = load i16, ptr [[SX]], align 2
30691 // SIMD-ONLY0-NEXT:    [[CONV1625:%.*]] = sext i16 [[TMP672]] to i32
30692 // SIMD-ONLY0-NEXT:    [[TMP673:%.*]] = load i16, ptr [[SE]], align 2
30693 // SIMD-ONLY0-NEXT:    [[CONV1626:%.*]] = sext i16 [[TMP673]] to i32
30694 // SIMD-ONLY0-NEXT:    [[CMP1627:%.*]] = icmp sgt i32 [[CONV1625]], [[CONV1626]]
30695 // SIMD-ONLY0-NEXT:    br i1 [[CMP1627]], label [[COND_TRUE1629:%.*]], label [[COND_FALSE1631:%.*]]
30696 // SIMD-ONLY0:       cond.true1629:
30697 // SIMD-ONLY0-NEXT:    [[TMP674:%.*]] = load i16, ptr [[SE]], align 2
30698 // SIMD-ONLY0-NEXT:    [[CONV1630:%.*]] = sext i16 [[TMP674]] to i32
30699 // SIMD-ONLY0-NEXT:    br label [[COND_END1633:%.*]]
30700 // SIMD-ONLY0:       cond.false1631:
30701 // SIMD-ONLY0-NEXT:    [[TMP675:%.*]] = load i16, ptr [[SX]], align 2
30702 // SIMD-ONLY0-NEXT:    [[CONV1632:%.*]] = sext i16 [[TMP675]] to i32
30703 // SIMD-ONLY0-NEXT:    br label [[COND_END1633]]
30704 // SIMD-ONLY0:       cond.end1633:
30705 // SIMD-ONLY0-NEXT:    [[COND1634:%.*]] = phi i32 [ [[CONV1630]], [[COND_TRUE1629]] ], [ [[CONV1632]], [[COND_FALSE1631]] ]
30706 // SIMD-ONLY0-NEXT:    [[CONV1635:%.*]] = trunc i32 [[COND1634]] to i16
30707 // SIMD-ONLY0-NEXT:    store i16 [[CONV1635]], ptr [[SX]], align 2
30708 // SIMD-ONLY0-NEXT:    [[TMP676:%.*]] = load i16, ptr [[SX]], align 2
30709 // SIMD-ONLY0-NEXT:    [[CONV1636:%.*]] = sext i16 [[TMP676]] to i32
30710 // SIMD-ONLY0-NEXT:    [[TMP677:%.*]] = load i16, ptr [[SE]], align 2
30711 // SIMD-ONLY0-NEXT:    [[CONV1637:%.*]] = sext i16 [[TMP677]] to i32
30712 // SIMD-ONLY0-NEXT:    [[CMP1638:%.*]] = icmp slt i32 [[CONV1636]], [[CONV1637]]
30713 // SIMD-ONLY0-NEXT:    br i1 [[CMP1638]], label [[COND_TRUE1640:%.*]], label [[COND_FALSE1642:%.*]]
30714 // SIMD-ONLY0:       cond.true1640:
30715 // SIMD-ONLY0-NEXT:    [[TMP678:%.*]] = load i16, ptr [[SE]], align 2
30716 // SIMD-ONLY0-NEXT:    [[CONV1641:%.*]] = sext i16 [[TMP678]] to i32
30717 // SIMD-ONLY0-NEXT:    br label [[COND_END1644:%.*]]
30718 // SIMD-ONLY0:       cond.false1642:
30719 // SIMD-ONLY0-NEXT:    [[TMP679:%.*]] = load i16, ptr [[SX]], align 2
30720 // SIMD-ONLY0-NEXT:    [[CONV1643:%.*]] = sext i16 [[TMP679]] to i32
30721 // SIMD-ONLY0-NEXT:    br label [[COND_END1644]]
30722 // SIMD-ONLY0:       cond.end1644:
30723 // SIMD-ONLY0-NEXT:    [[COND1645:%.*]] = phi i32 [ [[CONV1641]], [[COND_TRUE1640]] ], [ [[CONV1643]], [[COND_FALSE1642]] ]
30724 // SIMD-ONLY0-NEXT:    [[CONV1646:%.*]] = trunc i32 [[COND1645]] to i16
30725 // SIMD-ONLY0-NEXT:    store i16 [[CONV1646]], ptr [[SX]], align 2
30726 // SIMD-ONLY0-NEXT:    [[TMP680:%.*]] = load i16, ptr [[SE]], align 2
30727 // SIMD-ONLY0-NEXT:    [[CONV1647:%.*]] = sext i16 [[TMP680]] to i32
30728 // SIMD-ONLY0-NEXT:    [[TMP681:%.*]] = load i16, ptr [[SX]], align 2
30729 // SIMD-ONLY0-NEXT:    [[CONV1648:%.*]] = sext i16 [[TMP681]] to i32
30730 // SIMD-ONLY0-NEXT:    [[CMP1649:%.*]] = icmp sgt i32 [[CONV1647]], [[CONV1648]]
30731 // SIMD-ONLY0-NEXT:    br i1 [[CMP1649]], label [[COND_TRUE1651:%.*]], label [[COND_FALSE1653:%.*]]
30732 // SIMD-ONLY0:       cond.true1651:
30733 // SIMD-ONLY0-NEXT:    [[TMP682:%.*]] = load i16, ptr [[SE]], align 2
30734 // SIMD-ONLY0-NEXT:    [[CONV1652:%.*]] = sext i16 [[TMP682]] to i32
30735 // SIMD-ONLY0-NEXT:    br label [[COND_END1655:%.*]]
30736 // SIMD-ONLY0:       cond.false1653:
30737 // SIMD-ONLY0-NEXT:    [[TMP683:%.*]] = load i16, ptr [[SX]], align 2
30738 // SIMD-ONLY0-NEXT:    [[CONV1654:%.*]] = sext i16 [[TMP683]] to i32
30739 // SIMD-ONLY0-NEXT:    br label [[COND_END1655]]
30740 // SIMD-ONLY0:       cond.end1655:
30741 // SIMD-ONLY0-NEXT:    [[COND1656:%.*]] = phi i32 [ [[CONV1652]], [[COND_TRUE1651]] ], [ [[CONV1654]], [[COND_FALSE1653]] ]
30742 // SIMD-ONLY0-NEXT:    [[CONV1657:%.*]] = trunc i32 [[COND1656]] to i16
30743 // SIMD-ONLY0-NEXT:    store i16 [[CONV1657]], ptr [[SX]], align 2
30744 // SIMD-ONLY0-NEXT:    [[TMP684:%.*]] = load i16, ptr [[SE]], align 2
30745 // SIMD-ONLY0-NEXT:    [[CONV1658:%.*]] = sext i16 [[TMP684]] to i32
30746 // SIMD-ONLY0-NEXT:    [[TMP685:%.*]] = load i16, ptr [[SX]], align 2
30747 // SIMD-ONLY0-NEXT:    [[CONV1659:%.*]] = sext i16 [[TMP685]] to i32
30748 // SIMD-ONLY0-NEXT:    [[CMP1660:%.*]] = icmp slt i32 [[CONV1658]], [[CONV1659]]
30749 // SIMD-ONLY0-NEXT:    br i1 [[CMP1660]], label [[COND_TRUE1662:%.*]], label [[COND_FALSE1664:%.*]]
30750 // SIMD-ONLY0:       cond.true1662:
30751 // SIMD-ONLY0-NEXT:    [[TMP686:%.*]] = load i16, ptr [[SE]], align 2
30752 // SIMD-ONLY0-NEXT:    [[CONV1663:%.*]] = sext i16 [[TMP686]] to i32
30753 // SIMD-ONLY0-NEXT:    br label [[COND_END1666:%.*]]
30754 // SIMD-ONLY0:       cond.false1664:
30755 // SIMD-ONLY0-NEXT:    [[TMP687:%.*]] = load i16, ptr [[SX]], align 2
30756 // SIMD-ONLY0-NEXT:    [[CONV1665:%.*]] = sext i16 [[TMP687]] to i32
30757 // SIMD-ONLY0-NEXT:    br label [[COND_END1666]]
30758 // SIMD-ONLY0:       cond.end1666:
30759 // SIMD-ONLY0-NEXT:    [[COND1667:%.*]] = phi i32 [ [[CONV1663]], [[COND_TRUE1662]] ], [ [[CONV1665]], [[COND_FALSE1664]] ]
30760 // SIMD-ONLY0-NEXT:    [[CONV1668:%.*]] = trunc i32 [[COND1667]] to i16
30761 // SIMD-ONLY0-NEXT:    store i16 [[CONV1668]], ptr [[SX]], align 2
30762 // SIMD-ONLY0-NEXT:    [[TMP688:%.*]] = load i16, ptr [[SX]], align 2
30763 // SIMD-ONLY0-NEXT:    [[CONV1669:%.*]] = sext i16 [[TMP688]] to i32
30764 // SIMD-ONLY0-NEXT:    [[TMP689:%.*]] = load i16, ptr [[SE]], align 2
30765 // SIMD-ONLY0-NEXT:    [[CONV1670:%.*]] = sext i16 [[TMP689]] to i32
30766 // SIMD-ONLY0-NEXT:    [[CMP1671:%.*]] = icmp sgt i32 [[CONV1669]], [[CONV1670]]
30767 // SIMD-ONLY0-NEXT:    br i1 [[CMP1671]], label [[IF_THEN1673:%.*]], label [[IF_END1674:%.*]]
30768 // SIMD-ONLY0:       if.then1673:
30769 // SIMD-ONLY0-NEXT:    [[TMP690:%.*]] = load i16, ptr [[SE]], align 2
30770 // SIMD-ONLY0-NEXT:    store i16 [[TMP690]], ptr [[SX]], align 2
30771 // SIMD-ONLY0-NEXT:    br label [[IF_END1674]]
30772 // SIMD-ONLY0:       if.end1674:
30773 // SIMD-ONLY0-NEXT:    [[TMP691:%.*]] = load i16, ptr [[SX]], align 2
30774 // SIMD-ONLY0-NEXT:    [[CONV1675:%.*]] = sext i16 [[TMP691]] to i32
30775 // SIMD-ONLY0-NEXT:    [[TMP692:%.*]] = load i16, ptr [[SE]], align 2
30776 // SIMD-ONLY0-NEXT:    [[CONV1676:%.*]] = sext i16 [[TMP692]] to i32
30777 // SIMD-ONLY0-NEXT:    [[CMP1677:%.*]] = icmp slt i32 [[CONV1675]], [[CONV1676]]
30778 // SIMD-ONLY0-NEXT:    br i1 [[CMP1677]], label [[IF_THEN1679:%.*]], label [[IF_END1680:%.*]]
30779 // SIMD-ONLY0:       if.then1679:
30780 // SIMD-ONLY0-NEXT:    [[TMP693:%.*]] = load i16, ptr [[SE]], align 2
30781 // SIMD-ONLY0-NEXT:    store i16 [[TMP693]], ptr [[SX]], align 2
30782 // SIMD-ONLY0-NEXT:    br label [[IF_END1680]]
30783 // SIMD-ONLY0:       if.end1680:
30784 // SIMD-ONLY0-NEXT:    [[TMP694:%.*]] = load i16, ptr [[SE]], align 2
30785 // SIMD-ONLY0-NEXT:    [[CONV1681:%.*]] = sext i16 [[TMP694]] to i32
30786 // SIMD-ONLY0-NEXT:    [[TMP695:%.*]] = load i16, ptr [[SX]], align 2
30787 // SIMD-ONLY0-NEXT:    [[CONV1682:%.*]] = sext i16 [[TMP695]] to i32
30788 // SIMD-ONLY0-NEXT:    [[CMP1683:%.*]] = icmp sgt i32 [[CONV1681]], [[CONV1682]]
30789 // SIMD-ONLY0-NEXT:    br i1 [[CMP1683]], label [[IF_THEN1685:%.*]], label [[IF_END1686:%.*]]
30790 // SIMD-ONLY0:       if.then1685:
30791 // SIMD-ONLY0-NEXT:    [[TMP696:%.*]] = load i16, ptr [[SE]], align 2
30792 // SIMD-ONLY0-NEXT:    store i16 [[TMP696]], ptr [[SX]], align 2
30793 // SIMD-ONLY0-NEXT:    br label [[IF_END1686]]
30794 // SIMD-ONLY0:       if.end1686:
30795 // SIMD-ONLY0-NEXT:    [[TMP697:%.*]] = load i16, ptr [[SE]], align 2
30796 // SIMD-ONLY0-NEXT:    [[CONV1687:%.*]] = sext i16 [[TMP697]] to i32
30797 // SIMD-ONLY0-NEXT:    [[TMP698:%.*]] = load i16, ptr [[SX]], align 2
30798 // SIMD-ONLY0-NEXT:    [[CONV1688:%.*]] = sext i16 [[TMP698]] to i32
30799 // SIMD-ONLY0-NEXT:    [[CMP1689:%.*]] = icmp slt i32 [[CONV1687]], [[CONV1688]]
30800 // SIMD-ONLY0-NEXT:    br i1 [[CMP1689]], label [[IF_THEN1691:%.*]], label [[IF_END1692:%.*]]
30801 // SIMD-ONLY0:       if.then1691:
30802 // SIMD-ONLY0-NEXT:    [[TMP699:%.*]] = load i16, ptr [[SE]], align 2
30803 // SIMD-ONLY0-NEXT:    store i16 [[TMP699]], ptr [[SX]], align 2
30804 // SIMD-ONLY0-NEXT:    br label [[IF_END1692]]
30805 // SIMD-ONLY0:       if.end1692:
30806 // SIMD-ONLY0-NEXT:    [[TMP700:%.*]] = load i16, ptr [[SX]], align 2
30807 // SIMD-ONLY0-NEXT:    [[CONV1693:%.*]] = sext i16 [[TMP700]] to i32
30808 // SIMD-ONLY0-NEXT:    [[TMP701:%.*]] = load i16, ptr [[SE]], align 2
30809 // SIMD-ONLY0-NEXT:    [[CONV1694:%.*]] = sext i16 [[TMP701]] to i32
30810 // SIMD-ONLY0-NEXT:    [[CMP1695:%.*]] = icmp eq i32 [[CONV1693]], [[CONV1694]]
30811 // SIMD-ONLY0-NEXT:    br i1 [[CMP1695]], label [[COND_TRUE1697:%.*]], label [[COND_FALSE1699:%.*]]
30812 // SIMD-ONLY0:       cond.true1697:
30813 // SIMD-ONLY0-NEXT:    [[TMP702:%.*]] = load i16, ptr [[SD]], align 2
30814 // SIMD-ONLY0-NEXT:    [[CONV1698:%.*]] = sext i16 [[TMP702]] to i32
30815 // SIMD-ONLY0-NEXT:    br label [[COND_END1701:%.*]]
30816 // SIMD-ONLY0:       cond.false1699:
30817 // SIMD-ONLY0-NEXT:    [[TMP703:%.*]] = load i16, ptr [[SX]], align 2
30818 // SIMD-ONLY0-NEXT:    [[CONV1700:%.*]] = sext i16 [[TMP703]] to i32
30819 // SIMD-ONLY0-NEXT:    br label [[COND_END1701]]
30820 // SIMD-ONLY0:       cond.end1701:
30821 // SIMD-ONLY0-NEXT:    [[COND1702:%.*]] = phi i32 [ [[CONV1698]], [[COND_TRUE1697]] ], [ [[CONV1700]], [[COND_FALSE1699]] ]
30822 // SIMD-ONLY0-NEXT:    [[CONV1703:%.*]] = trunc i32 [[COND1702]] to i16
30823 // SIMD-ONLY0-NEXT:    store i16 [[CONV1703]], ptr [[SX]], align 2
30824 // SIMD-ONLY0-NEXT:    [[TMP704:%.*]] = load i16, ptr [[SE]], align 2
30825 // SIMD-ONLY0-NEXT:    [[CONV1704:%.*]] = sext i16 [[TMP704]] to i32
30826 // SIMD-ONLY0-NEXT:    [[TMP705:%.*]] = load i16, ptr [[SX]], align 2
30827 // SIMD-ONLY0-NEXT:    [[CONV1705:%.*]] = sext i16 [[TMP705]] to i32
30828 // SIMD-ONLY0-NEXT:    [[CMP1706:%.*]] = icmp eq i32 [[CONV1704]], [[CONV1705]]
30829 // SIMD-ONLY0-NEXT:    br i1 [[CMP1706]], label [[COND_TRUE1708:%.*]], label [[COND_FALSE1710:%.*]]
30830 // SIMD-ONLY0:       cond.true1708:
30831 // SIMD-ONLY0-NEXT:    [[TMP706:%.*]] = load i16, ptr [[SD]], align 2
30832 // SIMD-ONLY0-NEXT:    [[CONV1709:%.*]] = sext i16 [[TMP706]] to i32
30833 // SIMD-ONLY0-NEXT:    br label [[COND_END1712:%.*]]
30834 // SIMD-ONLY0:       cond.false1710:
30835 // SIMD-ONLY0-NEXT:    [[TMP707:%.*]] = load i16, ptr [[SX]], align 2
30836 // SIMD-ONLY0-NEXT:    [[CONV1711:%.*]] = sext i16 [[TMP707]] to i32
30837 // SIMD-ONLY0-NEXT:    br label [[COND_END1712]]
30838 // SIMD-ONLY0:       cond.end1712:
30839 // SIMD-ONLY0-NEXT:    [[COND1713:%.*]] = phi i32 [ [[CONV1709]], [[COND_TRUE1708]] ], [ [[CONV1711]], [[COND_FALSE1710]] ]
30840 // SIMD-ONLY0-NEXT:    [[CONV1714:%.*]] = trunc i32 [[COND1713]] to i16
30841 // SIMD-ONLY0-NEXT:    store i16 [[CONV1714]], ptr [[SX]], align 2
30842 // SIMD-ONLY0-NEXT:    [[TMP708:%.*]] = load i16, ptr [[SX]], align 2
30843 // SIMD-ONLY0-NEXT:    [[CONV1715:%.*]] = sext i16 [[TMP708]] to i32
30844 // SIMD-ONLY0-NEXT:    [[TMP709:%.*]] = load i16, ptr [[SE]], align 2
30845 // SIMD-ONLY0-NEXT:    [[CONV1716:%.*]] = sext i16 [[TMP709]] to i32
30846 // SIMD-ONLY0-NEXT:    [[CMP1717:%.*]] = icmp eq i32 [[CONV1715]], [[CONV1716]]
30847 // SIMD-ONLY0-NEXT:    br i1 [[CMP1717]], label [[IF_THEN1719:%.*]], label [[IF_END1720:%.*]]
30848 // SIMD-ONLY0:       if.then1719:
30849 // SIMD-ONLY0-NEXT:    [[TMP710:%.*]] = load i16, ptr [[SD]], align 2
30850 // SIMD-ONLY0-NEXT:    store i16 [[TMP710]], ptr [[SX]], align 2
30851 // SIMD-ONLY0-NEXT:    br label [[IF_END1720]]
30852 // SIMD-ONLY0:       if.end1720:
30853 // SIMD-ONLY0-NEXT:    [[TMP711:%.*]] = load i16, ptr [[SE]], align 2
30854 // SIMD-ONLY0-NEXT:    [[CONV1721:%.*]] = sext i16 [[TMP711]] to i32
30855 // SIMD-ONLY0-NEXT:    [[TMP712:%.*]] = load i16, ptr [[SX]], align 2
30856 // SIMD-ONLY0-NEXT:    [[CONV1722:%.*]] = sext i16 [[TMP712]] to i32
30857 // SIMD-ONLY0-NEXT:    [[CMP1723:%.*]] = icmp eq i32 [[CONV1721]], [[CONV1722]]
30858 // SIMD-ONLY0-NEXT:    br i1 [[CMP1723]], label [[IF_THEN1725:%.*]], label [[IF_END1726:%.*]]
30859 // SIMD-ONLY0:       if.then1725:
30860 // SIMD-ONLY0-NEXT:    [[TMP713:%.*]] = load i16, ptr [[SD]], align 2
30861 // SIMD-ONLY0-NEXT:    store i16 [[TMP713]], ptr [[SX]], align 2
30862 // SIMD-ONLY0-NEXT:    br label [[IF_END1726]]
30863 // SIMD-ONLY0:       if.end1726:
30864 // SIMD-ONLY0-NEXT:    [[TMP714:%.*]] = load i16, ptr [[USX]], align 2
30865 // SIMD-ONLY0-NEXT:    [[CONV1727:%.*]] = zext i16 [[TMP714]] to i32
30866 // SIMD-ONLY0-NEXT:    [[TMP715:%.*]] = load i16, ptr [[USE]], align 2
30867 // SIMD-ONLY0-NEXT:    [[CONV1728:%.*]] = zext i16 [[TMP715]] to i32
30868 // SIMD-ONLY0-NEXT:    [[CMP1729:%.*]] = icmp sgt i32 [[CONV1727]], [[CONV1728]]
30869 // SIMD-ONLY0-NEXT:    br i1 [[CMP1729]], label [[COND_TRUE1731:%.*]], label [[COND_FALSE1733:%.*]]
30870 // SIMD-ONLY0:       cond.true1731:
30871 // SIMD-ONLY0-NEXT:    [[TMP716:%.*]] = load i16, ptr [[USE]], align 2
30872 // SIMD-ONLY0-NEXT:    [[CONV1732:%.*]] = zext i16 [[TMP716]] to i32
30873 // SIMD-ONLY0-NEXT:    br label [[COND_END1735:%.*]]
30874 // SIMD-ONLY0:       cond.false1733:
30875 // SIMD-ONLY0-NEXT:    [[TMP717:%.*]] = load i16, ptr [[USX]], align 2
30876 // SIMD-ONLY0-NEXT:    [[CONV1734:%.*]] = zext i16 [[TMP717]] to i32
30877 // SIMD-ONLY0-NEXT:    br label [[COND_END1735]]
30878 // SIMD-ONLY0:       cond.end1735:
30879 // SIMD-ONLY0-NEXT:    [[COND1736:%.*]] = phi i32 [ [[CONV1732]], [[COND_TRUE1731]] ], [ [[CONV1734]], [[COND_FALSE1733]] ]
30880 // SIMD-ONLY0-NEXT:    [[CONV1737:%.*]] = trunc i32 [[COND1736]] to i16
30881 // SIMD-ONLY0-NEXT:    store i16 [[CONV1737]], ptr [[USX]], align 2
30882 // SIMD-ONLY0-NEXT:    [[TMP718:%.*]] = load i16, ptr [[USX]], align 2
30883 // SIMD-ONLY0-NEXT:    [[CONV1738:%.*]] = zext i16 [[TMP718]] to i32
30884 // SIMD-ONLY0-NEXT:    [[TMP719:%.*]] = load i16, ptr [[USE]], align 2
30885 // SIMD-ONLY0-NEXT:    [[CONV1739:%.*]] = zext i16 [[TMP719]] to i32
30886 // SIMD-ONLY0-NEXT:    [[CMP1740:%.*]] = icmp slt i32 [[CONV1738]], [[CONV1739]]
30887 // SIMD-ONLY0-NEXT:    br i1 [[CMP1740]], label [[COND_TRUE1742:%.*]], label [[COND_FALSE1744:%.*]]
30888 // SIMD-ONLY0:       cond.true1742:
30889 // SIMD-ONLY0-NEXT:    [[TMP720:%.*]] = load i16, ptr [[USE]], align 2
30890 // SIMD-ONLY0-NEXT:    [[CONV1743:%.*]] = zext i16 [[TMP720]] to i32
30891 // SIMD-ONLY0-NEXT:    br label [[COND_END1746:%.*]]
30892 // SIMD-ONLY0:       cond.false1744:
30893 // SIMD-ONLY0-NEXT:    [[TMP721:%.*]] = load i16, ptr [[USX]], align 2
30894 // SIMD-ONLY0-NEXT:    [[CONV1745:%.*]] = zext i16 [[TMP721]] to i32
30895 // SIMD-ONLY0-NEXT:    br label [[COND_END1746]]
30896 // SIMD-ONLY0:       cond.end1746:
30897 // SIMD-ONLY0-NEXT:    [[COND1747:%.*]] = phi i32 [ [[CONV1743]], [[COND_TRUE1742]] ], [ [[CONV1745]], [[COND_FALSE1744]] ]
30898 // SIMD-ONLY0-NEXT:    [[CONV1748:%.*]] = trunc i32 [[COND1747]] to i16
30899 // SIMD-ONLY0-NEXT:    store i16 [[CONV1748]], ptr [[USX]], align 2
30900 // SIMD-ONLY0-NEXT:    [[TMP722:%.*]] = load i16, ptr [[USE]], align 2
30901 // SIMD-ONLY0-NEXT:    [[CONV1749:%.*]] = zext i16 [[TMP722]] to i32
30902 // SIMD-ONLY0-NEXT:    [[TMP723:%.*]] = load i16, ptr [[USX]], align 2
30903 // SIMD-ONLY0-NEXT:    [[CONV1750:%.*]] = zext i16 [[TMP723]] to i32
30904 // SIMD-ONLY0-NEXT:    [[CMP1751:%.*]] = icmp sgt i32 [[CONV1749]], [[CONV1750]]
30905 // SIMD-ONLY0-NEXT:    br i1 [[CMP1751]], label [[COND_TRUE1753:%.*]], label [[COND_FALSE1755:%.*]]
30906 // SIMD-ONLY0:       cond.true1753:
30907 // SIMD-ONLY0-NEXT:    [[TMP724:%.*]] = load i16, ptr [[USE]], align 2
30908 // SIMD-ONLY0-NEXT:    [[CONV1754:%.*]] = zext i16 [[TMP724]] to i32
30909 // SIMD-ONLY0-NEXT:    br label [[COND_END1757:%.*]]
30910 // SIMD-ONLY0:       cond.false1755:
30911 // SIMD-ONLY0-NEXT:    [[TMP725:%.*]] = load i16, ptr [[USX]], align 2
30912 // SIMD-ONLY0-NEXT:    [[CONV1756:%.*]] = zext i16 [[TMP725]] to i32
30913 // SIMD-ONLY0-NEXT:    br label [[COND_END1757]]
30914 // SIMD-ONLY0:       cond.end1757:
30915 // SIMD-ONLY0-NEXT:    [[COND1758:%.*]] = phi i32 [ [[CONV1754]], [[COND_TRUE1753]] ], [ [[CONV1756]], [[COND_FALSE1755]] ]
30916 // SIMD-ONLY0-NEXT:    [[CONV1759:%.*]] = trunc i32 [[COND1758]] to i16
30917 // SIMD-ONLY0-NEXT:    store i16 [[CONV1759]], ptr [[USX]], align 2
30918 // SIMD-ONLY0-NEXT:    [[TMP726:%.*]] = load i16, ptr [[USE]], align 2
30919 // SIMD-ONLY0-NEXT:    [[CONV1760:%.*]] = zext i16 [[TMP726]] to i32
30920 // SIMD-ONLY0-NEXT:    [[TMP727:%.*]] = load i16, ptr [[USX]], align 2
30921 // SIMD-ONLY0-NEXT:    [[CONV1761:%.*]] = zext i16 [[TMP727]] to i32
30922 // SIMD-ONLY0-NEXT:    [[CMP1762:%.*]] = icmp slt i32 [[CONV1760]], [[CONV1761]]
30923 // SIMD-ONLY0-NEXT:    br i1 [[CMP1762]], label [[COND_TRUE1764:%.*]], label [[COND_FALSE1766:%.*]]
30924 // SIMD-ONLY0:       cond.true1764:
30925 // SIMD-ONLY0-NEXT:    [[TMP728:%.*]] = load i16, ptr [[USE]], align 2
30926 // SIMD-ONLY0-NEXT:    [[CONV1765:%.*]] = zext i16 [[TMP728]] to i32
30927 // SIMD-ONLY0-NEXT:    br label [[COND_END1768:%.*]]
30928 // SIMD-ONLY0:       cond.false1766:
30929 // SIMD-ONLY0-NEXT:    [[TMP729:%.*]] = load i16, ptr [[USX]], align 2
30930 // SIMD-ONLY0-NEXT:    [[CONV1767:%.*]] = zext i16 [[TMP729]] to i32
30931 // SIMD-ONLY0-NEXT:    br label [[COND_END1768]]
30932 // SIMD-ONLY0:       cond.end1768:
30933 // SIMD-ONLY0-NEXT:    [[COND1769:%.*]] = phi i32 [ [[CONV1765]], [[COND_TRUE1764]] ], [ [[CONV1767]], [[COND_FALSE1766]] ]
30934 // SIMD-ONLY0-NEXT:    [[CONV1770:%.*]] = trunc i32 [[COND1769]] to i16
30935 // SIMD-ONLY0-NEXT:    store i16 [[CONV1770]], ptr [[USX]], align 2
30936 // SIMD-ONLY0-NEXT:    [[TMP730:%.*]] = load i16, ptr [[USX]], align 2
30937 // SIMD-ONLY0-NEXT:    [[CONV1771:%.*]] = zext i16 [[TMP730]] to i32
30938 // SIMD-ONLY0-NEXT:    [[TMP731:%.*]] = load i16, ptr [[USE]], align 2
30939 // SIMD-ONLY0-NEXT:    [[CONV1772:%.*]] = zext i16 [[TMP731]] to i32
30940 // SIMD-ONLY0-NEXT:    [[CMP1773:%.*]] = icmp sgt i32 [[CONV1771]], [[CONV1772]]
30941 // SIMD-ONLY0-NEXT:    br i1 [[CMP1773]], label [[IF_THEN1775:%.*]], label [[IF_END1776:%.*]]
30942 // SIMD-ONLY0:       if.then1775:
30943 // SIMD-ONLY0-NEXT:    [[TMP732:%.*]] = load i16, ptr [[USE]], align 2
30944 // SIMD-ONLY0-NEXT:    store i16 [[TMP732]], ptr [[USX]], align 2
30945 // SIMD-ONLY0-NEXT:    br label [[IF_END1776]]
30946 // SIMD-ONLY0:       if.end1776:
30947 // SIMD-ONLY0-NEXT:    [[TMP733:%.*]] = load i16, ptr [[USX]], align 2
30948 // SIMD-ONLY0-NEXT:    [[CONV1777:%.*]] = zext i16 [[TMP733]] to i32
30949 // SIMD-ONLY0-NEXT:    [[TMP734:%.*]] = load i16, ptr [[USE]], align 2
30950 // SIMD-ONLY0-NEXT:    [[CONV1778:%.*]] = zext i16 [[TMP734]] to i32
30951 // SIMD-ONLY0-NEXT:    [[CMP1779:%.*]] = icmp slt i32 [[CONV1777]], [[CONV1778]]
30952 // SIMD-ONLY0-NEXT:    br i1 [[CMP1779]], label [[IF_THEN1781:%.*]], label [[IF_END1782:%.*]]
30953 // SIMD-ONLY0:       if.then1781:
30954 // SIMD-ONLY0-NEXT:    [[TMP735:%.*]] = load i16, ptr [[USE]], align 2
30955 // SIMD-ONLY0-NEXT:    store i16 [[TMP735]], ptr [[USX]], align 2
30956 // SIMD-ONLY0-NEXT:    br label [[IF_END1782]]
30957 // SIMD-ONLY0:       if.end1782:
30958 // SIMD-ONLY0-NEXT:    [[TMP736:%.*]] = load i16, ptr [[USE]], align 2
30959 // SIMD-ONLY0-NEXT:    [[CONV1783:%.*]] = zext i16 [[TMP736]] to i32
30960 // SIMD-ONLY0-NEXT:    [[TMP737:%.*]] = load i16, ptr [[USX]], align 2
30961 // SIMD-ONLY0-NEXT:    [[CONV1784:%.*]] = zext i16 [[TMP737]] to i32
30962 // SIMD-ONLY0-NEXT:    [[CMP1785:%.*]] = icmp sgt i32 [[CONV1783]], [[CONV1784]]
30963 // SIMD-ONLY0-NEXT:    br i1 [[CMP1785]], label [[IF_THEN1787:%.*]], label [[IF_END1788:%.*]]
30964 // SIMD-ONLY0:       if.then1787:
30965 // SIMD-ONLY0-NEXT:    [[TMP738:%.*]] = load i16, ptr [[USE]], align 2
30966 // SIMD-ONLY0-NEXT:    store i16 [[TMP738]], ptr [[USX]], align 2
30967 // SIMD-ONLY0-NEXT:    br label [[IF_END1788]]
30968 // SIMD-ONLY0:       if.end1788:
30969 // SIMD-ONLY0-NEXT:    [[TMP739:%.*]] = load i16, ptr [[USE]], align 2
30970 // SIMD-ONLY0-NEXT:    [[CONV1789:%.*]] = zext i16 [[TMP739]] to i32
30971 // SIMD-ONLY0-NEXT:    [[TMP740:%.*]] = load i16, ptr [[USX]], align 2
30972 // SIMD-ONLY0-NEXT:    [[CONV1790:%.*]] = zext i16 [[TMP740]] to i32
30973 // SIMD-ONLY0-NEXT:    [[CMP1791:%.*]] = icmp slt i32 [[CONV1789]], [[CONV1790]]
30974 // SIMD-ONLY0-NEXT:    br i1 [[CMP1791]], label [[IF_THEN1793:%.*]], label [[IF_END1794:%.*]]
30975 // SIMD-ONLY0:       if.then1793:
30976 // SIMD-ONLY0-NEXT:    [[TMP741:%.*]] = load i16, ptr [[USE]], align 2
30977 // SIMD-ONLY0-NEXT:    store i16 [[TMP741]], ptr [[USX]], align 2
30978 // SIMD-ONLY0-NEXT:    br label [[IF_END1794]]
30979 // SIMD-ONLY0:       if.end1794:
30980 // SIMD-ONLY0-NEXT:    [[TMP742:%.*]] = load i16, ptr [[USX]], align 2
30981 // SIMD-ONLY0-NEXT:    [[CONV1795:%.*]] = zext i16 [[TMP742]] to i32
30982 // SIMD-ONLY0-NEXT:    [[TMP743:%.*]] = load i16, ptr [[USE]], align 2
30983 // SIMD-ONLY0-NEXT:    [[CONV1796:%.*]] = zext i16 [[TMP743]] to i32
30984 // SIMD-ONLY0-NEXT:    [[CMP1797:%.*]] = icmp eq i32 [[CONV1795]], [[CONV1796]]
30985 // SIMD-ONLY0-NEXT:    br i1 [[CMP1797]], label [[COND_TRUE1799:%.*]], label [[COND_FALSE1801:%.*]]
30986 // SIMD-ONLY0:       cond.true1799:
30987 // SIMD-ONLY0-NEXT:    [[TMP744:%.*]] = load i16, ptr [[USD]], align 2
30988 // SIMD-ONLY0-NEXT:    [[CONV1800:%.*]] = zext i16 [[TMP744]] to i32
30989 // SIMD-ONLY0-NEXT:    br label [[COND_END1803:%.*]]
30990 // SIMD-ONLY0:       cond.false1801:
30991 // SIMD-ONLY0-NEXT:    [[TMP745:%.*]] = load i16, ptr [[USX]], align 2
30992 // SIMD-ONLY0-NEXT:    [[CONV1802:%.*]] = zext i16 [[TMP745]] to i32
30993 // SIMD-ONLY0-NEXT:    br label [[COND_END1803]]
30994 // SIMD-ONLY0:       cond.end1803:
30995 // SIMD-ONLY0-NEXT:    [[COND1804:%.*]] = phi i32 [ [[CONV1800]], [[COND_TRUE1799]] ], [ [[CONV1802]], [[COND_FALSE1801]] ]
30996 // SIMD-ONLY0-NEXT:    [[CONV1805:%.*]] = trunc i32 [[COND1804]] to i16
30997 // SIMD-ONLY0-NEXT:    store i16 [[CONV1805]], ptr [[USX]], align 2
30998 // SIMD-ONLY0-NEXT:    [[TMP746:%.*]] = load i16, ptr [[USE]], align 2
30999 // SIMD-ONLY0-NEXT:    [[CONV1806:%.*]] = zext i16 [[TMP746]] to i32
31000 // SIMD-ONLY0-NEXT:    [[TMP747:%.*]] = load i16, ptr [[USX]], align 2
31001 // SIMD-ONLY0-NEXT:    [[CONV1807:%.*]] = zext i16 [[TMP747]] to i32
31002 // SIMD-ONLY0-NEXT:    [[CMP1808:%.*]] = icmp eq i32 [[CONV1806]], [[CONV1807]]
31003 // SIMD-ONLY0-NEXT:    br i1 [[CMP1808]], label [[COND_TRUE1810:%.*]], label [[COND_FALSE1812:%.*]]
31004 // SIMD-ONLY0:       cond.true1810:
31005 // SIMD-ONLY0-NEXT:    [[TMP748:%.*]] = load i16, ptr [[USD]], align 2
31006 // SIMD-ONLY0-NEXT:    [[CONV1811:%.*]] = zext i16 [[TMP748]] to i32
31007 // SIMD-ONLY0-NEXT:    br label [[COND_END1814:%.*]]
31008 // SIMD-ONLY0:       cond.false1812:
31009 // SIMD-ONLY0-NEXT:    [[TMP749:%.*]] = load i16, ptr [[USX]], align 2
31010 // SIMD-ONLY0-NEXT:    [[CONV1813:%.*]] = zext i16 [[TMP749]] to i32
31011 // SIMD-ONLY0-NEXT:    br label [[COND_END1814]]
31012 // SIMD-ONLY0:       cond.end1814:
31013 // SIMD-ONLY0-NEXT:    [[COND1815:%.*]] = phi i32 [ [[CONV1811]], [[COND_TRUE1810]] ], [ [[CONV1813]], [[COND_FALSE1812]] ]
31014 // SIMD-ONLY0-NEXT:    [[CONV1816:%.*]] = trunc i32 [[COND1815]] to i16
31015 // SIMD-ONLY0-NEXT:    store i16 [[CONV1816]], ptr [[USX]], align 2
31016 // SIMD-ONLY0-NEXT:    [[TMP750:%.*]] = load i16, ptr [[USX]], align 2
31017 // SIMD-ONLY0-NEXT:    [[CONV1817:%.*]] = zext i16 [[TMP750]] to i32
31018 // SIMD-ONLY0-NEXT:    [[TMP751:%.*]] = load i16, ptr [[USE]], align 2
31019 // SIMD-ONLY0-NEXT:    [[CONV1818:%.*]] = zext i16 [[TMP751]] to i32
31020 // SIMD-ONLY0-NEXT:    [[CMP1819:%.*]] = icmp eq i32 [[CONV1817]], [[CONV1818]]
31021 // SIMD-ONLY0-NEXT:    br i1 [[CMP1819]], label [[IF_THEN1821:%.*]], label [[IF_END1822:%.*]]
31022 // SIMD-ONLY0:       if.then1821:
31023 // SIMD-ONLY0-NEXT:    [[TMP752:%.*]] = load i16, ptr [[USD]], align 2
31024 // SIMD-ONLY0-NEXT:    store i16 [[TMP752]], ptr [[USX]], align 2
31025 // SIMD-ONLY0-NEXT:    br label [[IF_END1822]]
31026 // SIMD-ONLY0:       if.end1822:
31027 // SIMD-ONLY0-NEXT:    [[TMP753:%.*]] = load i16, ptr [[USE]], align 2
31028 // SIMD-ONLY0-NEXT:    [[CONV1823:%.*]] = zext i16 [[TMP753]] to i32
31029 // SIMD-ONLY0-NEXT:    [[TMP754:%.*]] = load i16, ptr [[USX]], align 2
31030 // SIMD-ONLY0-NEXT:    [[CONV1824:%.*]] = zext i16 [[TMP754]] to i32
31031 // SIMD-ONLY0-NEXT:    [[CMP1825:%.*]] = icmp eq i32 [[CONV1823]], [[CONV1824]]
31032 // SIMD-ONLY0-NEXT:    br i1 [[CMP1825]], label [[IF_THEN1827:%.*]], label [[IF_END1828:%.*]]
31033 // SIMD-ONLY0:       if.then1827:
31034 // SIMD-ONLY0-NEXT:    [[TMP755:%.*]] = load i16, ptr [[USD]], align 2
31035 // SIMD-ONLY0-NEXT:    store i16 [[TMP755]], ptr [[USX]], align 2
31036 // SIMD-ONLY0-NEXT:    br label [[IF_END1828]]
31037 // SIMD-ONLY0:       if.end1828:
31038 // SIMD-ONLY0-NEXT:    [[TMP756:%.*]] = load i16, ptr [[SX]], align 2
31039 // SIMD-ONLY0-NEXT:    [[CONV1829:%.*]] = sext i16 [[TMP756]] to i32
31040 // SIMD-ONLY0-NEXT:    [[TMP757:%.*]] = load i16, ptr [[SE]], align 2
31041 // SIMD-ONLY0-NEXT:    [[CONV1830:%.*]] = sext i16 [[TMP757]] to i32
31042 // SIMD-ONLY0-NEXT:    [[CMP1831:%.*]] = icmp sgt i32 [[CONV1829]], [[CONV1830]]
31043 // SIMD-ONLY0-NEXT:    br i1 [[CMP1831]], label [[COND_TRUE1833:%.*]], label [[COND_FALSE1835:%.*]]
31044 // SIMD-ONLY0:       cond.true1833:
31045 // SIMD-ONLY0-NEXT:    [[TMP758:%.*]] = load i16, ptr [[SE]], align 2
31046 // SIMD-ONLY0-NEXT:    [[CONV1834:%.*]] = sext i16 [[TMP758]] to i32
31047 // SIMD-ONLY0-NEXT:    br label [[COND_END1837:%.*]]
31048 // SIMD-ONLY0:       cond.false1835:
31049 // SIMD-ONLY0-NEXT:    [[TMP759:%.*]] = load i16, ptr [[SX]], align 2
31050 // SIMD-ONLY0-NEXT:    [[CONV1836:%.*]] = sext i16 [[TMP759]] to i32
31051 // SIMD-ONLY0-NEXT:    br label [[COND_END1837]]
31052 // SIMD-ONLY0:       cond.end1837:
31053 // SIMD-ONLY0-NEXT:    [[COND1838:%.*]] = phi i32 [ [[CONV1834]], [[COND_TRUE1833]] ], [ [[CONV1836]], [[COND_FALSE1835]] ]
31054 // SIMD-ONLY0-NEXT:    [[CONV1839:%.*]] = trunc i32 [[COND1838]] to i16
31055 // SIMD-ONLY0-NEXT:    store i16 [[CONV1839]], ptr [[SX]], align 2
31056 // SIMD-ONLY0-NEXT:    [[TMP760:%.*]] = load i16, ptr [[SX]], align 2
31057 // SIMD-ONLY0-NEXT:    [[CONV1840:%.*]] = sext i16 [[TMP760]] to i32
31058 // SIMD-ONLY0-NEXT:    [[TMP761:%.*]] = load i16, ptr [[SE]], align 2
31059 // SIMD-ONLY0-NEXT:    [[CONV1841:%.*]] = sext i16 [[TMP761]] to i32
31060 // SIMD-ONLY0-NEXT:    [[CMP1842:%.*]] = icmp slt i32 [[CONV1840]], [[CONV1841]]
31061 // SIMD-ONLY0-NEXT:    br i1 [[CMP1842]], label [[COND_TRUE1844:%.*]], label [[COND_FALSE1846:%.*]]
31062 // SIMD-ONLY0:       cond.true1844:
31063 // SIMD-ONLY0-NEXT:    [[TMP762:%.*]] = load i16, ptr [[SE]], align 2
31064 // SIMD-ONLY0-NEXT:    [[CONV1845:%.*]] = sext i16 [[TMP762]] to i32
31065 // SIMD-ONLY0-NEXT:    br label [[COND_END1848:%.*]]
31066 // SIMD-ONLY0:       cond.false1846:
31067 // SIMD-ONLY0-NEXT:    [[TMP763:%.*]] = load i16, ptr [[SX]], align 2
31068 // SIMD-ONLY0-NEXT:    [[CONV1847:%.*]] = sext i16 [[TMP763]] to i32
31069 // SIMD-ONLY0-NEXT:    br label [[COND_END1848]]
31070 // SIMD-ONLY0:       cond.end1848:
31071 // SIMD-ONLY0-NEXT:    [[COND1849:%.*]] = phi i32 [ [[CONV1845]], [[COND_TRUE1844]] ], [ [[CONV1847]], [[COND_FALSE1846]] ]
31072 // SIMD-ONLY0-NEXT:    [[CONV1850:%.*]] = trunc i32 [[COND1849]] to i16
31073 // SIMD-ONLY0-NEXT:    store i16 [[CONV1850]], ptr [[SX]], align 2
31074 // SIMD-ONLY0-NEXT:    [[TMP764:%.*]] = load i16, ptr [[SE]], align 2
31075 // SIMD-ONLY0-NEXT:    [[CONV1851:%.*]] = sext i16 [[TMP764]] to i32
31076 // SIMD-ONLY0-NEXT:    [[TMP765:%.*]] = load i16, ptr [[SX]], align 2
31077 // SIMD-ONLY0-NEXT:    [[CONV1852:%.*]] = sext i16 [[TMP765]] to i32
31078 // SIMD-ONLY0-NEXT:    [[CMP1853:%.*]] = icmp sgt i32 [[CONV1851]], [[CONV1852]]
31079 // SIMD-ONLY0-NEXT:    br i1 [[CMP1853]], label [[COND_TRUE1855:%.*]], label [[COND_FALSE1857:%.*]]
31080 // SIMD-ONLY0:       cond.true1855:
31081 // SIMD-ONLY0-NEXT:    [[TMP766:%.*]] = load i16, ptr [[SE]], align 2
31082 // SIMD-ONLY0-NEXT:    [[CONV1856:%.*]] = sext i16 [[TMP766]] to i32
31083 // SIMD-ONLY0-NEXT:    br label [[COND_END1859:%.*]]
31084 // SIMD-ONLY0:       cond.false1857:
31085 // SIMD-ONLY0-NEXT:    [[TMP767:%.*]] = load i16, ptr [[SX]], align 2
31086 // SIMD-ONLY0-NEXT:    [[CONV1858:%.*]] = sext i16 [[TMP767]] to i32
31087 // SIMD-ONLY0-NEXT:    br label [[COND_END1859]]
31088 // SIMD-ONLY0:       cond.end1859:
31089 // SIMD-ONLY0-NEXT:    [[COND1860:%.*]] = phi i32 [ [[CONV1856]], [[COND_TRUE1855]] ], [ [[CONV1858]], [[COND_FALSE1857]] ]
31090 // SIMD-ONLY0-NEXT:    [[CONV1861:%.*]] = trunc i32 [[COND1860]] to i16
31091 // SIMD-ONLY0-NEXT:    store i16 [[CONV1861]], ptr [[SX]], align 2
31092 // SIMD-ONLY0-NEXT:    [[TMP768:%.*]] = load i16, ptr [[SE]], align 2
31093 // SIMD-ONLY0-NEXT:    [[CONV1862:%.*]] = sext i16 [[TMP768]] to i32
31094 // SIMD-ONLY0-NEXT:    [[TMP769:%.*]] = load i16, ptr [[SX]], align 2
31095 // SIMD-ONLY0-NEXT:    [[CONV1863:%.*]] = sext i16 [[TMP769]] to i32
31096 // SIMD-ONLY0-NEXT:    [[CMP1864:%.*]] = icmp slt i32 [[CONV1862]], [[CONV1863]]
31097 // SIMD-ONLY0-NEXT:    br i1 [[CMP1864]], label [[COND_TRUE1866:%.*]], label [[COND_FALSE1868:%.*]]
31098 // SIMD-ONLY0:       cond.true1866:
31099 // SIMD-ONLY0-NEXT:    [[TMP770:%.*]] = load i16, ptr [[SE]], align 2
31100 // SIMD-ONLY0-NEXT:    [[CONV1867:%.*]] = sext i16 [[TMP770]] to i32
31101 // SIMD-ONLY0-NEXT:    br label [[COND_END1870:%.*]]
31102 // SIMD-ONLY0:       cond.false1868:
31103 // SIMD-ONLY0-NEXT:    [[TMP771:%.*]] = load i16, ptr [[SX]], align 2
31104 // SIMD-ONLY0-NEXT:    [[CONV1869:%.*]] = sext i16 [[TMP771]] to i32
31105 // SIMD-ONLY0-NEXT:    br label [[COND_END1870]]
31106 // SIMD-ONLY0:       cond.end1870:
31107 // SIMD-ONLY0-NEXT:    [[COND1871:%.*]] = phi i32 [ [[CONV1867]], [[COND_TRUE1866]] ], [ [[CONV1869]], [[COND_FALSE1868]] ]
31108 // SIMD-ONLY0-NEXT:    [[CONV1872:%.*]] = trunc i32 [[COND1871]] to i16
31109 // SIMD-ONLY0-NEXT:    store i16 [[CONV1872]], ptr [[SX]], align 2
31110 // SIMD-ONLY0-NEXT:    [[TMP772:%.*]] = load i16, ptr [[SX]], align 2
31111 // SIMD-ONLY0-NEXT:    [[CONV1873:%.*]] = sext i16 [[TMP772]] to i32
31112 // SIMD-ONLY0-NEXT:    [[TMP773:%.*]] = load i16, ptr [[SE]], align 2
31113 // SIMD-ONLY0-NEXT:    [[CONV1874:%.*]] = sext i16 [[TMP773]] to i32
31114 // SIMD-ONLY0-NEXT:    [[CMP1875:%.*]] = icmp sgt i32 [[CONV1873]], [[CONV1874]]
31115 // SIMD-ONLY0-NEXT:    br i1 [[CMP1875]], label [[IF_THEN1877:%.*]], label [[IF_END1878:%.*]]
31116 // SIMD-ONLY0:       if.then1877:
31117 // SIMD-ONLY0-NEXT:    [[TMP774:%.*]] = load i16, ptr [[SE]], align 2
31118 // SIMD-ONLY0-NEXT:    store i16 [[TMP774]], ptr [[SX]], align 2
31119 // SIMD-ONLY0-NEXT:    br label [[IF_END1878]]
31120 // SIMD-ONLY0:       if.end1878:
31121 // SIMD-ONLY0-NEXT:    [[TMP775:%.*]] = load i16, ptr [[SX]], align 2
31122 // SIMD-ONLY0-NEXT:    [[CONV1879:%.*]] = sext i16 [[TMP775]] to i32
31123 // SIMD-ONLY0-NEXT:    [[TMP776:%.*]] = load i16, ptr [[SE]], align 2
31124 // SIMD-ONLY0-NEXT:    [[CONV1880:%.*]] = sext i16 [[TMP776]] to i32
31125 // SIMD-ONLY0-NEXT:    [[CMP1881:%.*]] = icmp slt i32 [[CONV1879]], [[CONV1880]]
31126 // SIMD-ONLY0-NEXT:    br i1 [[CMP1881]], label [[IF_THEN1883:%.*]], label [[IF_END1884:%.*]]
31127 // SIMD-ONLY0:       if.then1883:
31128 // SIMD-ONLY0-NEXT:    [[TMP777:%.*]] = load i16, ptr [[SE]], align 2
31129 // SIMD-ONLY0-NEXT:    store i16 [[TMP777]], ptr [[SX]], align 2
31130 // SIMD-ONLY0-NEXT:    br label [[IF_END1884]]
31131 // SIMD-ONLY0:       if.end1884:
31132 // SIMD-ONLY0-NEXT:    [[TMP778:%.*]] = load i16, ptr [[SE]], align 2
31133 // SIMD-ONLY0-NEXT:    [[CONV1885:%.*]] = sext i16 [[TMP778]] to i32
31134 // SIMD-ONLY0-NEXT:    [[TMP779:%.*]] = load i16, ptr [[SX]], align 2
31135 // SIMD-ONLY0-NEXT:    [[CONV1886:%.*]] = sext i16 [[TMP779]] to i32
31136 // SIMD-ONLY0-NEXT:    [[CMP1887:%.*]] = icmp sgt i32 [[CONV1885]], [[CONV1886]]
31137 // SIMD-ONLY0-NEXT:    br i1 [[CMP1887]], label [[IF_THEN1889:%.*]], label [[IF_END1890:%.*]]
31138 // SIMD-ONLY0:       if.then1889:
31139 // SIMD-ONLY0-NEXT:    [[TMP780:%.*]] = load i16, ptr [[SE]], align 2
31140 // SIMD-ONLY0-NEXT:    store i16 [[TMP780]], ptr [[SX]], align 2
31141 // SIMD-ONLY0-NEXT:    br label [[IF_END1890]]
31142 // SIMD-ONLY0:       if.end1890:
31143 // SIMD-ONLY0-NEXT:    [[TMP781:%.*]] = load i16, ptr [[SE]], align 2
31144 // SIMD-ONLY0-NEXT:    [[CONV1891:%.*]] = sext i16 [[TMP781]] to i32
31145 // SIMD-ONLY0-NEXT:    [[TMP782:%.*]] = load i16, ptr [[SX]], align 2
31146 // SIMD-ONLY0-NEXT:    [[CONV1892:%.*]] = sext i16 [[TMP782]] to i32
31147 // SIMD-ONLY0-NEXT:    [[CMP1893:%.*]] = icmp slt i32 [[CONV1891]], [[CONV1892]]
31148 // SIMD-ONLY0-NEXT:    br i1 [[CMP1893]], label [[IF_THEN1895:%.*]], label [[IF_END1896:%.*]]
31149 // SIMD-ONLY0:       if.then1895:
31150 // SIMD-ONLY0-NEXT:    [[TMP783:%.*]] = load i16, ptr [[SE]], align 2
31151 // SIMD-ONLY0-NEXT:    store i16 [[TMP783]], ptr [[SX]], align 2
31152 // SIMD-ONLY0-NEXT:    br label [[IF_END1896]]
31153 // SIMD-ONLY0:       if.end1896:
31154 // SIMD-ONLY0-NEXT:    [[TMP784:%.*]] = load i16, ptr [[SX]], align 2
31155 // SIMD-ONLY0-NEXT:    [[CONV1897:%.*]] = sext i16 [[TMP784]] to i32
31156 // SIMD-ONLY0-NEXT:    [[TMP785:%.*]] = load i16, ptr [[SE]], align 2
31157 // SIMD-ONLY0-NEXT:    [[CONV1898:%.*]] = sext i16 [[TMP785]] to i32
31158 // SIMD-ONLY0-NEXT:    [[CMP1899:%.*]] = icmp eq i32 [[CONV1897]], [[CONV1898]]
31159 // SIMD-ONLY0-NEXT:    br i1 [[CMP1899]], label [[COND_TRUE1901:%.*]], label [[COND_FALSE1903:%.*]]
31160 // SIMD-ONLY0:       cond.true1901:
31161 // SIMD-ONLY0-NEXT:    [[TMP786:%.*]] = load i16, ptr [[SD]], align 2
31162 // SIMD-ONLY0-NEXT:    [[CONV1902:%.*]] = sext i16 [[TMP786]] to i32
31163 // SIMD-ONLY0-NEXT:    br label [[COND_END1905:%.*]]
31164 // SIMD-ONLY0:       cond.false1903:
31165 // SIMD-ONLY0-NEXT:    [[TMP787:%.*]] = load i16, ptr [[SX]], align 2
31166 // SIMD-ONLY0-NEXT:    [[CONV1904:%.*]] = sext i16 [[TMP787]] to i32
31167 // SIMD-ONLY0-NEXT:    br label [[COND_END1905]]
31168 // SIMD-ONLY0:       cond.end1905:
31169 // SIMD-ONLY0-NEXT:    [[COND1906:%.*]] = phi i32 [ [[CONV1902]], [[COND_TRUE1901]] ], [ [[CONV1904]], [[COND_FALSE1903]] ]
31170 // SIMD-ONLY0-NEXT:    [[CONV1907:%.*]] = trunc i32 [[COND1906]] to i16
31171 // SIMD-ONLY0-NEXT:    store i16 [[CONV1907]], ptr [[SX]], align 2
31172 // SIMD-ONLY0-NEXT:    [[TMP788:%.*]] = load i16, ptr [[SE]], align 2
31173 // SIMD-ONLY0-NEXT:    [[CONV1908:%.*]] = sext i16 [[TMP788]] to i32
31174 // SIMD-ONLY0-NEXT:    [[TMP789:%.*]] = load i16, ptr [[SX]], align 2
31175 // SIMD-ONLY0-NEXT:    [[CONV1909:%.*]] = sext i16 [[TMP789]] to i32
31176 // SIMD-ONLY0-NEXT:    [[CMP1910:%.*]] = icmp eq i32 [[CONV1908]], [[CONV1909]]
31177 // SIMD-ONLY0-NEXT:    br i1 [[CMP1910]], label [[COND_TRUE1912:%.*]], label [[COND_FALSE1914:%.*]]
31178 // SIMD-ONLY0:       cond.true1912:
31179 // SIMD-ONLY0-NEXT:    [[TMP790:%.*]] = load i16, ptr [[SD]], align 2
31180 // SIMD-ONLY0-NEXT:    [[CONV1913:%.*]] = sext i16 [[TMP790]] to i32
31181 // SIMD-ONLY0-NEXT:    br label [[COND_END1916:%.*]]
31182 // SIMD-ONLY0:       cond.false1914:
31183 // SIMD-ONLY0-NEXT:    [[TMP791:%.*]] = load i16, ptr [[SX]], align 2
31184 // SIMD-ONLY0-NEXT:    [[CONV1915:%.*]] = sext i16 [[TMP791]] to i32
31185 // SIMD-ONLY0-NEXT:    br label [[COND_END1916]]
31186 // SIMD-ONLY0:       cond.end1916:
31187 // SIMD-ONLY0-NEXT:    [[COND1917:%.*]] = phi i32 [ [[CONV1913]], [[COND_TRUE1912]] ], [ [[CONV1915]], [[COND_FALSE1914]] ]
31188 // SIMD-ONLY0-NEXT:    [[CONV1918:%.*]] = trunc i32 [[COND1917]] to i16
31189 // SIMD-ONLY0-NEXT:    store i16 [[CONV1918]], ptr [[SX]], align 2
31190 // SIMD-ONLY0-NEXT:    [[TMP792:%.*]] = load i16, ptr [[SX]], align 2
31191 // SIMD-ONLY0-NEXT:    [[CONV1919:%.*]] = sext i16 [[TMP792]] to i32
31192 // SIMD-ONLY0-NEXT:    [[TMP793:%.*]] = load i16, ptr [[SE]], align 2
31193 // SIMD-ONLY0-NEXT:    [[CONV1920:%.*]] = sext i16 [[TMP793]] to i32
31194 // SIMD-ONLY0-NEXT:    [[CMP1921:%.*]] = icmp eq i32 [[CONV1919]], [[CONV1920]]
31195 // SIMD-ONLY0-NEXT:    br i1 [[CMP1921]], label [[IF_THEN1923:%.*]], label [[IF_END1924:%.*]]
31196 // SIMD-ONLY0:       if.then1923:
31197 // SIMD-ONLY0-NEXT:    [[TMP794:%.*]] = load i16, ptr [[SD]], align 2
31198 // SIMD-ONLY0-NEXT:    store i16 [[TMP794]], ptr [[SX]], align 2
31199 // SIMD-ONLY0-NEXT:    br label [[IF_END1924]]
31200 // SIMD-ONLY0:       if.end1924:
31201 // SIMD-ONLY0-NEXT:    [[TMP795:%.*]] = load i16, ptr [[SE]], align 2
31202 // SIMD-ONLY0-NEXT:    [[CONV1925:%.*]] = sext i16 [[TMP795]] to i32
31203 // SIMD-ONLY0-NEXT:    [[TMP796:%.*]] = load i16, ptr [[SX]], align 2
31204 // SIMD-ONLY0-NEXT:    [[CONV1926:%.*]] = sext i16 [[TMP796]] to i32
31205 // SIMD-ONLY0-NEXT:    [[CMP1927:%.*]] = icmp eq i32 [[CONV1925]], [[CONV1926]]
31206 // SIMD-ONLY0-NEXT:    br i1 [[CMP1927]], label [[IF_THEN1929:%.*]], label [[IF_END1930:%.*]]
31207 // SIMD-ONLY0:       if.then1929:
31208 // SIMD-ONLY0-NEXT:    [[TMP797:%.*]] = load i16, ptr [[SD]], align 2
31209 // SIMD-ONLY0-NEXT:    store i16 [[TMP797]], ptr [[SX]], align 2
31210 // SIMD-ONLY0-NEXT:    br label [[IF_END1930]]
31211 // SIMD-ONLY0:       if.end1930:
31212 // SIMD-ONLY0-NEXT:    [[TMP798:%.*]] = load i16, ptr [[USX]], align 2
31213 // SIMD-ONLY0-NEXT:    [[CONV1931:%.*]] = zext i16 [[TMP798]] to i32
31214 // SIMD-ONLY0-NEXT:    [[TMP799:%.*]] = load i16, ptr [[USE]], align 2
31215 // SIMD-ONLY0-NEXT:    [[CONV1932:%.*]] = zext i16 [[TMP799]] to i32
31216 // SIMD-ONLY0-NEXT:    [[CMP1933:%.*]] = icmp sgt i32 [[CONV1931]], [[CONV1932]]
31217 // SIMD-ONLY0-NEXT:    br i1 [[CMP1933]], label [[COND_TRUE1935:%.*]], label [[COND_FALSE1937:%.*]]
31218 // SIMD-ONLY0:       cond.true1935:
31219 // SIMD-ONLY0-NEXT:    [[TMP800:%.*]] = load i16, ptr [[USE]], align 2
31220 // SIMD-ONLY0-NEXT:    [[CONV1936:%.*]] = zext i16 [[TMP800]] to i32
31221 // SIMD-ONLY0-NEXT:    br label [[COND_END1939:%.*]]
31222 // SIMD-ONLY0:       cond.false1937:
31223 // SIMD-ONLY0-NEXT:    [[TMP801:%.*]] = load i16, ptr [[USX]], align 2
31224 // SIMD-ONLY0-NEXT:    [[CONV1938:%.*]] = zext i16 [[TMP801]] to i32
31225 // SIMD-ONLY0-NEXT:    br label [[COND_END1939]]
31226 // SIMD-ONLY0:       cond.end1939:
31227 // SIMD-ONLY0-NEXT:    [[COND1940:%.*]] = phi i32 [ [[CONV1936]], [[COND_TRUE1935]] ], [ [[CONV1938]], [[COND_FALSE1937]] ]
31228 // SIMD-ONLY0-NEXT:    [[CONV1941:%.*]] = trunc i32 [[COND1940]] to i16
31229 // SIMD-ONLY0-NEXT:    store i16 [[CONV1941]], ptr [[USX]], align 2
31230 // SIMD-ONLY0-NEXT:    [[TMP802:%.*]] = load i16, ptr [[USX]], align 2
31231 // SIMD-ONLY0-NEXT:    [[CONV1942:%.*]] = zext i16 [[TMP802]] to i32
31232 // SIMD-ONLY0-NEXT:    [[TMP803:%.*]] = load i16, ptr [[USE]], align 2
31233 // SIMD-ONLY0-NEXT:    [[CONV1943:%.*]] = zext i16 [[TMP803]] to i32
31234 // SIMD-ONLY0-NEXT:    [[CMP1944:%.*]] = icmp slt i32 [[CONV1942]], [[CONV1943]]
31235 // SIMD-ONLY0-NEXT:    br i1 [[CMP1944]], label [[COND_TRUE1946:%.*]], label [[COND_FALSE1948:%.*]]
31236 // SIMD-ONLY0:       cond.true1946:
31237 // SIMD-ONLY0-NEXT:    [[TMP804:%.*]] = load i16, ptr [[USE]], align 2
31238 // SIMD-ONLY0-NEXT:    [[CONV1947:%.*]] = zext i16 [[TMP804]] to i32
31239 // SIMD-ONLY0-NEXT:    br label [[COND_END1950:%.*]]
31240 // SIMD-ONLY0:       cond.false1948:
31241 // SIMD-ONLY0-NEXT:    [[TMP805:%.*]] = load i16, ptr [[USX]], align 2
31242 // SIMD-ONLY0-NEXT:    [[CONV1949:%.*]] = zext i16 [[TMP805]] to i32
31243 // SIMD-ONLY0-NEXT:    br label [[COND_END1950]]
31244 // SIMD-ONLY0:       cond.end1950:
31245 // SIMD-ONLY0-NEXT:    [[COND1951:%.*]] = phi i32 [ [[CONV1947]], [[COND_TRUE1946]] ], [ [[CONV1949]], [[COND_FALSE1948]] ]
31246 // SIMD-ONLY0-NEXT:    [[CONV1952:%.*]] = trunc i32 [[COND1951]] to i16
31247 // SIMD-ONLY0-NEXT:    store i16 [[CONV1952]], ptr [[USX]], align 2
31248 // SIMD-ONLY0-NEXT:    [[TMP806:%.*]] = load i16, ptr [[USE]], align 2
31249 // SIMD-ONLY0-NEXT:    [[CONV1953:%.*]] = zext i16 [[TMP806]] to i32
31250 // SIMD-ONLY0-NEXT:    [[TMP807:%.*]] = load i16, ptr [[USX]], align 2
31251 // SIMD-ONLY0-NEXT:    [[CONV1954:%.*]] = zext i16 [[TMP807]] to i32
31252 // SIMD-ONLY0-NEXT:    [[CMP1955:%.*]] = icmp sgt i32 [[CONV1953]], [[CONV1954]]
31253 // SIMD-ONLY0-NEXT:    br i1 [[CMP1955]], label [[COND_TRUE1957:%.*]], label [[COND_FALSE1959:%.*]]
31254 // SIMD-ONLY0:       cond.true1957:
31255 // SIMD-ONLY0-NEXT:    [[TMP808:%.*]] = load i16, ptr [[USE]], align 2
31256 // SIMD-ONLY0-NEXT:    [[CONV1958:%.*]] = zext i16 [[TMP808]] to i32
31257 // SIMD-ONLY0-NEXT:    br label [[COND_END1961:%.*]]
31258 // SIMD-ONLY0:       cond.false1959:
31259 // SIMD-ONLY0-NEXT:    [[TMP809:%.*]] = load i16, ptr [[USX]], align 2
31260 // SIMD-ONLY0-NEXT:    [[CONV1960:%.*]] = zext i16 [[TMP809]] to i32
31261 // SIMD-ONLY0-NEXT:    br label [[COND_END1961]]
31262 // SIMD-ONLY0:       cond.end1961:
31263 // SIMD-ONLY0-NEXT:    [[COND1962:%.*]] = phi i32 [ [[CONV1958]], [[COND_TRUE1957]] ], [ [[CONV1960]], [[COND_FALSE1959]] ]
31264 // SIMD-ONLY0-NEXT:    [[CONV1963:%.*]] = trunc i32 [[COND1962]] to i16
31265 // SIMD-ONLY0-NEXT:    store i16 [[CONV1963]], ptr [[USX]], align 2
31266 // SIMD-ONLY0-NEXT:    [[TMP810:%.*]] = load i16, ptr [[USE]], align 2
31267 // SIMD-ONLY0-NEXT:    [[CONV1964:%.*]] = zext i16 [[TMP810]] to i32
31268 // SIMD-ONLY0-NEXT:    [[TMP811:%.*]] = load i16, ptr [[USX]], align 2
31269 // SIMD-ONLY0-NEXT:    [[CONV1965:%.*]] = zext i16 [[TMP811]] to i32
31270 // SIMD-ONLY0-NEXT:    [[CMP1966:%.*]] = icmp slt i32 [[CONV1964]], [[CONV1965]]
31271 // SIMD-ONLY0-NEXT:    br i1 [[CMP1966]], label [[COND_TRUE1968:%.*]], label [[COND_FALSE1970:%.*]]
31272 // SIMD-ONLY0:       cond.true1968:
31273 // SIMD-ONLY0-NEXT:    [[TMP812:%.*]] = load i16, ptr [[USE]], align 2
31274 // SIMD-ONLY0-NEXT:    [[CONV1969:%.*]] = zext i16 [[TMP812]] to i32
31275 // SIMD-ONLY0-NEXT:    br label [[COND_END1972:%.*]]
31276 // SIMD-ONLY0:       cond.false1970:
31277 // SIMD-ONLY0-NEXT:    [[TMP813:%.*]] = load i16, ptr [[USX]], align 2
31278 // SIMD-ONLY0-NEXT:    [[CONV1971:%.*]] = zext i16 [[TMP813]] to i32
31279 // SIMD-ONLY0-NEXT:    br label [[COND_END1972]]
31280 // SIMD-ONLY0:       cond.end1972:
31281 // SIMD-ONLY0-NEXT:    [[COND1973:%.*]] = phi i32 [ [[CONV1969]], [[COND_TRUE1968]] ], [ [[CONV1971]], [[COND_FALSE1970]] ]
31282 // SIMD-ONLY0-NEXT:    [[CONV1974:%.*]] = trunc i32 [[COND1973]] to i16
31283 // SIMD-ONLY0-NEXT:    store i16 [[CONV1974]], ptr [[USX]], align 2
31284 // SIMD-ONLY0-NEXT:    [[TMP814:%.*]] = load i16, ptr [[USX]], align 2
31285 // SIMD-ONLY0-NEXT:    [[CONV1975:%.*]] = zext i16 [[TMP814]] to i32
31286 // SIMD-ONLY0-NEXT:    [[TMP815:%.*]] = load i16, ptr [[USE]], align 2
31287 // SIMD-ONLY0-NEXT:    [[CONV1976:%.*]] = zext i16 [[TMP815]] to i32
31288 // SIMD-ONLY0-NEXT:    [[CMP1977:%.*]] = icmp sgt i32 [[CONV1975]], [[CONV1976]]
31289 // SIMD-ONLY0-NEXT:    br i1 [[CMP1977]], label [[IF_THEN1979:%.*]], label [[IF_END1980:%.*]]
31290 // SIMD-ONLY0:       if.then1979:
31291 // SIMD-ONLY0-NEXT:    [[TMP816:%.*]] = load i16, ptr [[USE]], align 2
31292 // SIMD-ONLY0-NEXT:    store i16 [[TMP816]], ptr [[USX]], align 2
31293 // SIMD-ONLY0-NEXT:    br label [[IF_END1980]]
31294 // SIMD-ONLY0:       if.end1980:
31295 // SIMD-ONLY0-NEXT:    [[TMP817:%.*]] = load i16, ptr [[USX]], align 2
31296 // SIMD-ONLY0-NEXT:    [[CONV1981:%.*]] = zext i16 [[TMP817]] to i32
31297 // SIMD-ONLY0-NEXT:    [[TMP818:%.*]] = load i16, ptr [[USE]], align 2
31298 // SIMD-ONLY0-NEXT:    [[CONV1982:%.*]] = zext i16 [[TMP818]] to i32
31299 // SIMD-ONLY0-NEXT:    [[CMP1983:%.*]] = icmp slt i32 [[CONV1981]], [[CONV1982]]
31300 // SIMD-ONLY0-NEXT:    br i1 [[CMP1983]], label [[IF_THEN1985:%.*]], label [[IF_END1986:%.*]]
31301 // SIMD-ONLY0:       if.then1985:
31302 // SIMD-ONLY0-NEXT:    [[TMP819:%.*]] = load i16, ptr [[USE]], align 2
31303 // SIMD-ONLY0-NEXT:    store i16 [[TMP819]], ptr [[USX]], align 2
31304 // SIMD-ONLY0-NEXT:    br label [[IF_END1986]]
31305 // SIMD-ONLY0:       if.end1986:
31306 // SIMD-ONLY0-NEXT:    [[TMP820:%.*]] = load i16, ptr [[USE]], align 2
31307 // SIMD-ONLY0-NEXT:    [[CONV1987:%.*]] = zext i16 [[TMP820]] to i32
31308 // SIMD-ONLY0-NEXT:    [[TMP821:%.*]] = load i16, ptr [[USX]], align 2
31309 // SIMD-ONLY0-NEXT:    [[CONV1988:%.*]] = zext i16 [[TMP821]] to i32
31310 // SIMD-ONLY0-NEXT:    [[CMP1989:%.*]] = icmp sgt i32 [[CONV1987]], [[CONV1988]]
31311 // SIMD-ONLY0-NEXT:    br i1 [[CMP1989]], label [[IF_THEN1991:%.*]], label [[IF_END1992:%.*]]
31312 // SIMD-ONLY0:       if.then1991:
31313 // SIMD-ONLY0-NEXT:    [[TMP822:%.*]] = load i16, ptr [[USE]], align 2
31314 // SIMD-ONLY0-NEXT:    store i16 [[TMP822]], ptr [[USX]], align 2
31315 // SIMD-ONLY0-NEXT:    br label [[IF_END1992]]
31316 // SIMD-ONLY0:       if.end1992:
31317 // SIMD-ONLY0-NEXT:    [[TMP823:%.*]] = load i16, ptr [[USE]], align 2
31318 // SIMD-ONLY0-NEXT:    [[CONV1993:%.*]] = zext i16 [[TMP823]] to i32
31319 // SIMD-ONLY0-NEXT:    [[TMP824:%.*]] = load i16, ptr [[USX]], align 2
31320 // SIMD-ONLY0-NEXT:    [[CONV1994:%.*]] = zext i16 [[TMP824]] to i32
31321 // SIMD-ONLY0-NEXT:    [[CMP1995:%.*]] = icmp slt i32 [[CONV1993]], [[CONV1994]]
31322 // SIMD-ONLY0-NEXT:    br i1 [[CMP1995]], label [[IF_THEN1997:%.*]], label [[IF_END1998:%.*]]
31323 // SIMD-ONLY0:       if.then1997:
31324 // SIMD-ONLY0-NEXT:    [[TMP825:%.*]] = load i16, ptr [[USE]], align 2
31325 // SIMD-ONLY0-NEXT:    store i16 [[TMP825]], ptr [[USX]], align 2
31326 // SIMD-ONLY0-NEXT:    br label [[IF_END1998]]
31327 // SIMD-ONLY0:       if.end1998:
31328 // SIMD-ONLY0-NEXT:    [[TMP826:%.*]] = load i16, ptr [[USX]], align 2
31329 // SIMD-ONLY0-NEXT:    [[CONV1999:%.*]] = zext i16 [[TMP826]] to i32
31330 // SIMD-ONLY0-NEXT:    [[TMP827:%.*]] = load i16, ptr [[USE]], align 2
31331 // SIMD-ONLY0-NEXT:    [[CONV2000:%.*]] = zext i16 [[TMP827]] to i32
31332 // SIMD-ONLY0-NEXT:    [[CMP2001:%.*]] = icmp eq i32 [[CONV1999]], [[CONV2000]]
31333 // SIMD-ONLY0-NEXT:    br i1 [[CMP2001]], label [[COND_TRUE2003:%.*]], label [[COND_FALSE2005:%.*]]
31334 // SIMD-ONLY0:       cond.true2003:
31335 // SIMD-ONLY0-NEXT:    [[TMP828:%.*]] = load i16, ptr [[USD]], align 2
31336 // SIMD-ONLY0-NEXT:    [[CONV2004:%.*]] = zext i16 [[TMP828]] to i32
31337 // SIMD-ONLY0-NEXT:    br label [[COND_END2007:%.*]]
31338 // SIMD-ONLY0:       cond.false2005:
31339 // SIMD-ONLY0-NEXT:    [[TMP829:%.*]] = load i16, ptr [[USX]], align 2
31340 // SIMD-ONLY0-NEXT:    [[CONV2006:%.*]] = zext i16 [[TMP829]] to i32
31341 // SIMD-ONLY0-NEXT:    br label [[COND_END2007]]
31342 // SIMD-ONLY0:       cond.end2007:
31343 // SIMD-ONLY0-NEXT:    [[COND2008:%.*]] = phi i32 [ [[CONV2004]], [[COND_TRUE2003]] ], [ [[CONV2006]], [[COND_FALSE2005]] ]
31344 // SIMD-ONLY0-NEXT:    [[CONV2009:%.*]] = trunc i32 [[COND2008]] to i16
31345 // SIMD-ONLY0-NEXT:    store i16 [[CONV2009]], ptr [[USX]], align 2
31346 // SIMD-ONLY0-NEXT:    [[TMP830:%.*]] = load i16, ptr [[USE]], align 2
31347 // SIMD-ONLY0-NEXT:    [[CONV2010:%.*]] = zext i16 [[TMP830]] to i32
31348 // SIMD-ONLY0-NEXT:    [[TMP831:%.*]] = load i16, ptr [[USX]], align 2
31349 // SIMD-ONLY0-NEXT:    [[CONV2011:%.*]] = zext i16 [[TMP831]] to i32
31350 // SIMD-ONLY0-NEXT:    [[CMP2012:%.*]] = icmp eq i32 [[CONV2010]], [[CONV2011]]
31351 // SIMD-ONLY0-NEXT:    br i1 [[CMP2012]], label [[COND_TRUE2014:%.*]], label [[COND_FALSE2016:%.*]]
31352 // SIMD-ONLY0:       cond.true2014:
31353 // SIMD-ONLY0-NEXT:    [[TMP832:%.*]] = load i16, ptr [[USD]], align 2
31354 // SIMD-ONLY0-NEXT:    [[CONV2015:%.*]] = zext i16 [[TMP832]] to i32
31355 // SIMD-ONLY0-NEXT:    br label [[COND_END2018:%.*]]
31356 // SIMD-ONLY0:       cond.false2016:
31357 // SIMD-ONLY0-NEXT:    [[TMP833:%.*]] = load i16, ptr [[USX]], align 2
31358 // SIMD-ONLY0-NEXT:    [[CONV2017:%.*]] = zext i16 [[TMP833]] to i32
31359 // SIMD-ONLY0-NEXT:    br label [[COND_END2018]]
31360 // SIMD-ONLY0:       cond.end2018:
31361 // SIMD-ONLY0-NEXT:    [[COND2019:%.*]] = phi i32 [ [[CONV2015]], [[COND_TRUE2014]] ], [ [[CONV2017]], [[COND_FALSE2016]] ]
31362 // SIMD-ONLY0-NEXT:    [[CONV2020:%.*]] = trunc i32 [[COND2019]] to i16
31363 // SIMD-ONLY0-NEXT:    store i16 [[CONV2020]], ptr [[USX]], align 2
31364 // SIMD-ONLY0-NEXT:    [[TMP834:%.*]] = load i16, ptr [[USX]], align 2
31365 // SIMD-ONLY0-NEXT:    [[CONV2021:%.*]] = zext i16 [[TMP834]] to i32
31366 // SIMD-ONLY0-NEXT:    [[TMP835:%.*]] = load i16, ptr [[USE]], align 2
31367 // SIMD-ONLY0-NEXT:    [[CONV2022:%.*]] = zext i16 [[TMP835]] to i32
31368 // SIMD-ONLY0-NEXT:    [[CMP2023:%.*]] = icmp eq i32 [[CONV2021]], [[CONV2022]]
31369 // SIMD-ONLY0-NEXT:    br i1 [[CMP2023]], label [[IF_THEN2025:%.*]], label [[IF_END2026:%.*]]
31370 // SIMD-ONLY0:       if.then2025:
31371 // SIMD-ONLY0-NEXT:    [[TMP836:%.*]] = load i16, ptr [[USD]], align 2
31372 // SIMD-ONLY0-NEXT:    store i16 [[TMP836]], ptr [[USX]], align 2
31373 // SIMD-ONLY0-NEXT:    br label [[IF_END2026]]
31374 // SIMD-ONLY0:       if.end2026:
31375 // SIMD-ONLY0-NEXT:    [[TMP837:%.*]] = load i16, ptr [[USE]], align 2
31376 // SIMD-ONLY0-NEXT:    [[CONV2027:%.*]] = zext i16 [[TMP837]] to i32
31377 // SIMD-ONLY0-NEXT:    [[TMP838:%.*]] = load i16, ptr [[USX]], align 2
31378 // SIMD-ONLY0-NEXT:    [[CONV2028:%.*]] = zext i16 [[TMP838]] to i32
31379 // SIMD-ONLY0-NEXT:    [[CMP2029:%.*]] = icmp eq i32 [[CONV2027]], [[CONV2028]]
31380 // SIMD-ONLY0-NEXT:    br i1 [[CMP2029]], label [[IF_THEN2031:%.*]], label [[IF_END2032:%.*]]
31381 // SIMD-ONLY0:       if.then2031:
31382 // SIMD-ONLY0-NEXT:    [[TMP839:%.*]] = load i16, ptr [[USD]], align 2
31383 // SIMD-ONLY0-NEXT:    store i16 [[TMP839]], ptr [[USX]], align 2
31384 // SIMD-ONLY0-NEXT:    br label [[IF_END2032]]
31385 // SIMD-ONLY0:       if.end2032:
31386 // SIMD-ONLY0-NEXT:    [[TMP840:%.*]] = load i16, ptr [[SX]], align 2
31387 // SIMD-ONLY0-NEXT:    [[CONV2033:%.*]] = sext i16 [[TMP840]] to i32
31388 // SIMD-ONLY0-NEXT:    [[TMP841:%.*]] = load i16, ptr [[SE]], align 2
31389 // SIMD-ONLY0-NEXT:    [[CONV2034:%.*]] = sext i16 [[TMP841]] to i32
31390 // SIMD-ONLY0-NEXT:    [[CMP2035:%.*]] = icmp sgt i32 [[CONV2033]], [[CONV2034]]
31391 // SIMD-ONLY0-NEXT:    br i1 [[CMP2035]], label [[COND_TRUE2037:%.*]], label [[COND_FALSE2039:%.*]]
31392 // SIMD-ONLY0:       cond.true2037:
31393 // SIMD-ONLY0-NEXT:    [[TMP842:%.*]] = load i16, ptr [[SE]], align 2
31394 // SIMD-ONLY0-NEXT:    [[CONV2038:%.*]] = sext i16 [[TMP842]] to i32
31395 // SIMD-ONLY0-NEXT:    br label [[COND_END2041:%.*]]
31396 // SIMD-ONLY0:       cond.false2039:
31397 // SIMD-ONLY0-NEXT:    [[TMP843:%.*]] = load i16, ptr [[SX]], align 2
31398 // SIMD-ONLY0-NEXT:    [[CONV2040:%.*]] = sext i16 [[TMP843]] to i32
31399 // SIMD-ONLY0-NEXT:    br label [[COND_END2041]]
31400 // SIMD-ONLY0:       cond.end2041:
31401 // SIMD-ONLY0-NEXT:    [[COND2042:%.*]] = phi i32 [ [[CONV2038]], [[COND_TRUE2037]] ], [ [[CONV2040]], [[COND_FALSE2039]] ]
31402 // SIMD-ONLY0-NEXT:    [[CONV2043:%.*]] = trunc i32 [[COND2042]] to i16
31403 // SIMD-ONLY0-NEXT:    store i16 [[CONV2043]], ptr [[SX]], align 2
31404 // SIMD-ONLY0-NEXT:    [[TMP844:%.*]] = load i16, ptr [[SX]], align 2
31405 // SIMD-ONLY0-NEXT:    [[CONV2044:%.*]] = sext i16 [[TMP844]] to i32
31406 // SIMD-ONLY0-NEXT:    [[TMP845:%.*]] = load i16, ptr [[SE]], align 2
31407 // SIMD-ONLY0-NEXT:    [[CONV2045:%.*]] = sext i16 [[TMP845]] to i32
31408 // SIMD-ONLY0-NEXT:    [[CMP2046:%.*]] = icmp slt i32 [[CONV2044]], [[CONV2045]]
31409 // SIMD-ONLY0-NEXT:    br i1 [[CMP2046]], label [[COND_TRUE2048:%.*]], label [[COND_FALSE2050:%.*]]
31410 // SIMD-ONLY0:       cond.true2048:
31411 // SIMD-ONLY0-NEXT:    [[TMP846:%.*]] = load i16, ptr [[SE]], align 2
31412 // SIMD-ONLY0-NEXT:    [[CONV2049:%.*]] = sext i16 [[TMP846]] to i32
31413 // SIMD-ONLY0-NEXT:    br label [[COND_END2052:%.*]]
31414 // SIMD-ONLY0:       cond.false2050:
31415 // SIMD-ONLY0-NEXT:    [[TMP847:%.*]] = load i16, ptr [[SX]], align 2
31416 // SIMD-ONLY0-NEXT:    [[CONV2051:%.*]] = sext i16 [[TMP847]] to i32
31417 // SIMD-ONLY0-NEXT:    br label [[COND_END2052]]
31418 // SIMD-ONLY0:       cond.end2052:
31419 // SIMD-ONLY0-NEXT:    [[COND2053:%.*]] = phi i32 [ [[CONV2049]], [[COND_TRUE2048]] ], [ [[CONV2051]], [[COND_FALSE2050]] ]
31420 // SIMD-ONLY0-NEXT:    [[CONV2054:%.*]] = trunc i32 [[COND2053]] to i16
31421 // SIMD-ONLY0-NEXT:    store i16 [[CONV2054]], ptr [[SX]], align 2
31422 // SIMD-ONLY0-NEXT:    [[TMP848:%.*]] = load i16, ptr [[SE]], align 2
31423 // SIMD-ONLY0-NEXT:    [[CONV2055:%.*]] = sext i16 [[TMP848]] to i32
31424 // SIMD-ONLY0-NEXT:    [[TMP849:%.*]] = load i16, ptr [[SX]], align 2
31425 // SIMD-ONLY0-NEXT:    [[CONV2056:%.*]] = sext i16 [[TMP849]] to i32
31426 // SIMD-ONLY0-NEXT:    [[CMP2057:%.*]] = icmp sgt i32 [[CONV2055]], [[CONV2056]]
31427 // SIMD-ONLY0-NEXT:    br i1 [[CMP2057]], label [[COND_TRUE2059:%.*]], label [[COND_FALSE2061:%.*]]
31428 // SIMD-ONLY0:       cond.true2059:
31429 // SIMD-ONLY0-NEXT:    [[TMP850:%.*]] = load i16, ptr [[SE]], align 2
31430 // SIMD-ONLY0-NEXT:    [[CONV2060:%.*]] = sext i16 [[TMP850]] to i32
31431 // SIMD-ONLY0-NEXT:    br label [[COND_END2063:%.*]]
31432 // SIMD-ONLY0:       cond.false2061:
31433 // SIMD-ONLY0-NEXT:    [[TMP851:%.*]] = load i16, ptr [[SX]], align 2
31434 // SIMD-ONLY0-NEXT:    [[CONV2062:%.*]] = sext i16 [[TMP851]] to i32
31435 // SIMD-ONLY0-NEXT:    br label [[COND_END2063]]
31436 // SIMD-ONLY0:       cond.end2063:
31437 // SIMD-ONLY0-NEXT:    [[COND2064:%.*]] = phi i32 [ [[CONV2060]], [[COND_TRUE2059]] ], [ [[CONV2062]], [[COND_FALSE2061]] ]
31438 // SIMD-ONLY0-NEXT:    [[CONV2065:%.*]] = trunc i32 [[COND2064]] to i16
31439 // SIMD-ONLY0-NEXT:    store i16 [[CONV2065]], ptr [[SX]], align 2
31440 // SIMD-ONLY0-NEXT:    [[TMP852:%.*]] = load i16, ptr [[SE]], align 2
31441 // SIMD-ONLY0-NEXT:    [[CONV2066:%.*]] = sext i16 [[TMP852]] to i32
31442 // SIMD-ONLY0-NEXT:    [[TMP853:%.*]] = load i16, ptr [[SX]], align 2
31443 // SIMD-ONLY0-NEXT:    [[CONV2067:%.*]] = sext i16 [[TMP853]] to i32
31444 // SIMD-ONLY0-NEXT:    [[CMP2068:%.*]] = icmp slt i32 [[CONV2066]], [[CONV2067]]
31445 // SIMD-ONLY0-NEXT:    br i1 [[CMP2068]], label [[COND_TRUE2070:%.*]], label [[COND_FALSE2072:%.*]]
31446 // SIMD-ONLY0:       cond.true2070:
31447 // SIMD-ONLY0-NEXT:    [[TMP854:%.*]] = load i16, ptr [[SE]], align 2
31448 // SIMD-ONLY0-NEXT:    [[CONV2071:%.*]] = sext i16 [[TMP854]] to i32
31449 // SIMD-ONLY0-NEXT:    br label [[COND_END2074:%.*]]
31450 // SIMD-ONLY0:       cond.false2072:
31451 // SIMD-ONLY0-NEXT:    [[TMP855:%.*]] = load i16, ptr [[SX]], align 2
31452 // SIMD-ONLY0-NEXT:    [[CONV2073:%.*]] = sext i16 [[TMP855]] to i32
31453 // SIMD-ONLY0-NEXT:    br label [[COND_END2074]]
31454 // SIMD-ONLY0:       cond.end2074:
31455 // SIMD-ONLY0-NEXT:    [[COND2075:%.*]] = phi i32 [ [[CONV2071]], [[COND_TRUE2070]] ], [ [[CONV2073]], [[COND_FALSE2072]] ]
31456 // SIMD-ONLY0-NEXT:    [[CONV2076:%.*]] = trunc i32 [[COND2075]] to i16
31457 // SIMD-ONLY0-NEXT:    store i16 [[CONV2076]], ptr [[SX]], align 2
31458 // SIMD-ONLY0-NEXT:    [[TMP856:%.*]] = load i16, ptr [[SX]], align 2
31459 // SIMD-ONLY0-NEXT:    [[CONV2077:%.*]] = sext i16 [[TMP856]] to i32
31460 // SIMD-ONLY0-NEXT:    [[TMP857:%.*]] = load i16, ptr [[SE]], align 2
31461 // SIMD-ONLY0-NEXT:    [[CONV2078:%.*]] = sext i16 [[TMP857]] to i32
31462 // SIMD-ONLY0-NEXT:    [[CMP2079:%.*]] = icmp sgt i32 [[CONV2077]], [[CONV2078]]
31463 // SIMD-ONLY0-NEXT:    br i1 [[CMP2079]], label [[IF_THEN2081:%.*]], label [[IF_END2082:%.*]]
31464 // SIMD-ONLY0:       if.then2081:
31465 // SIMD-ONLY0-NEXT:    [[TMP858:%.*]] = load i16, ptr [[SE]], align 2
31466 // SIMD-ONLY0-NEXT:    store i16 [[TMP858]], ptr [[SX]], align 2
31467 // SIMD-ONLY0-NEXT:    br label [[IF_END2082]]
31468 // SIMD-ONLY0:       if.end2082:
31469 // SIMD-ONLY0-NEXT:    [[TMP859:%.*]] = load i16, ptr [[SX]], align 2
31470 // SIMD-ONLY0-NEXT:    [[CONV2083:%.*]] = sext i16 [[TMP859]] to i32
31471 // SIMD-ONLY0-NEXT:    [[TMP860:%.*]] = load i16, ptr [[SE]], align 2
31472 // SIMD-ONLY0-NEXT:    [[CONV2084:%.*]] = sext i16 [[TMP860]] to i32
31473 // SIMD-ONLY0-NEXT:    [[CMP2085:%.*]] = icmp slt i32 [[CONV2083]], [[CONV2084]]
31474 // SIMD-ONLY0-NEXT:    br i1 [[CMP2085]], label [[IF_THEN2087:%.*]], label [[IF_END2088:%.*]]
31475 // SIMD-ONLY0:       if.then2087:
31476 // SIMD-ONLY0-NEXT:    [[TMP861:%.*]] = load i16, ptr [[SE]], align 2
31477 // SIMD-ONLY0-NEXT:    store i16 [[TMP861]], ptr [[SX]], align 2
31478 // SIMD-ONLY0-NEXT:    br label [[IF_END2088]]
31479 // SIMD-ONLY0:       if.end2088:
31480 // SIMD-ONLY0-NEXT:    [[TMP862:%.*]] = load i16, ptr [[SE]], align 2
31481 // SIMD-ONLY0-NEXT:    [[CONV2089:%.*]] = sext i16 [[TMP862]] to i32
31482 // SIMD-ONLY0-NEXT:    [[TMP863:%.*]] = load i16, ptr [[SX]], align 2
31483 // SIMD-ONLY0-NEXT:    [[CONV2090:%.*]] = sext i16 [[TMP863]] to i32
31484 // SIMD-ONLY0-NEXT:    [[CMP2091:%.*]] = icmp sgt i32 [[CONV2089]], [[CONV2090]]
31485 // SIMD-ONLY0-NEXT:    br i1 [[CMP2091]], label [[IF_THEN2093:%.*]], label [[IF_END2094:%.*]]
31486 // SIMD-ONLY0:       if.then2093:
31487 // SIMD-ONLY0-NEXT:    [[TMP864:%.*]] = load i16, ptr [[SE]], align 2
31488 // SIMD-ONLY0-NEXT:    store i16 [[TMP864]], ptr [[SX]], align 2
31489 // SIMD-ONLY0-NEXT:    br label [[IF_END2094]]
31490 // SIMD-ONLY0:       if.end2094:
31491 // SIMD-ONLY0-NEXT:    [[TMP865:%.*]] = load i16, ptr [[SE]], align 2
31492 // SIMD-ONLY0-NEXT:    [[CONV2095:%.*]] = sext i16 [[TMP865]] to i32
31493 // SIMD-ONLY0-NEXT:    [[TMP866:%.*]] = load i16, ptr [[SX]], align 2
31494 // SIMD-ONLY0-NEXT:    [[CONV2096:%.*]] = sext i16 [[TMP866]] to i32
31495 // SIMD-ONLY0-NEXT:    [[CMP2097:%.*]] = icmp slt i32 [[CONV2095]], [[CONV2096]]
31496 // SIMD-ONLY0-NEXT:    br i1 [[CMP2097]], label [[IF_THEN2099:%.*]], label [[IF_END2100:%.*]]
31497 // SIMD-ONLY0:       if.then2099:
31498 // SIMD-ONLY0-NEXT:    [[TMP867:%.*]] = load i16, ptr [[SE]], align 2
31499 // SIMD-ONLY0-NEXT:    store i16 [[TMP867]], ptr [[SX]], align 2
31500 // SIMD-ONLY0-NEXT:    br label [[IF_END2100]]
31501 // SIMD-ONLY0:       if.end2100:
31502 // SIMD-ONLY0-NEXT:    [[TMP868:%.*]] = load i16, ptr [[SX]], align 2
31503 // SIMD-ONLY0-NEXT:    [[CONV2101:%.*]] = sext i16 [[TMP868]] to i32
31504 // SIMD-ONLY0-NEXT:    [[TMP869:%.*]] = load i16, ptr [[SE]], align 2
31505 // SIMD-ONLY0-NEXT:    [[CONV2102:%.*]] = sext i16 [[TMP869]] to i32
31506 // SIMD-ONLY0-NEXT:    [[CMP2103:%.*]] = icmp eq i32 [[CONV2101]], [[CONV2102]]
31507 // SIMD-ONLY0-NEXT:    br i1 [[CMP2103]], label [[COND_TRUE2105:%.*]], label [[COND_FALSE2107:%.*]]
31508 // SIMD-ONLY0:       cond.true2105:
31509 // SIMD-ONLY0-NEXT:    [[TMP870:%.*]] = load i16, ptr [[SD]], align 2
31510 // SIMD-ONLY0-NEXT:    [[CONV2106:%.*]] = sext i16 [[TMP870]] to i32
31511 // SIMD-ONLY0-NEXT:    br label [[COND_END2109:%.*]]
31512 // SIMD-ONLY0:       cond.false2107:
31513 // SIMD-ONLY0-NEXT:    [[TMP871:%.*]] = load i16, ptr [[SX]], align 2
31514 // SIMD-ONLY0-NEXT:    [[CONV2108:%.*]] = sext i16 [[TMP871]] to i32
31515 // SIMD-ONLY0-NEXT:    br label [[COND_END2109]]
31516 // SIMD-ONLY0:       cond.end2109:
31517 // SIMD-ONLY0-NEXT:    [[COND2110:%.*]] = phi i32 [ [[CONV2106]], [[COND_TRUE2105]] ], [ [[CONV2108]], [[COND_FALSE2107]] ]
31518 // SIMD-ONLY0-NEXT:    [[CONV2111:%.*]] = trunc i32 [[COND2110]] to i16
31519 // SIMD-ONLY0-NEXT:    store i16 [[CONV2111]], ptr [[SX]], align 2
31520 // SIMD-ONLY0-NEXT:    [[TMP872:%.*]] = load i16, ptr [[SE]], align 2
31521 // SIMD-ONLY0-NEXT:    [[CONV2112:%.*]] = sext i16 [[TMP872]] to i32
31522 // SIMD-ONLY0-NEXT:    [[TMP873:%.*]] = load i16, ptr [[SX]], align 2
31523 // SIMD-ONLY0-NEXT:    [[CONV2113:%.*]] = sext i16 [[TMP873]] to i32
31524 // SIMD-ONLY0-NEXT:    [[CMP2114:%.*]] = icmp eq i32 [[CONV2112]], [[CONV2113]]
31525 // SIMD-ONLY0-NEXT:    br i1 [[CMP2114]], label [[COND_TRUE2116:%.*]], label [[COND_FALSE2118:%.*]]
31526 // SIMD-ONLY0:       cond.true2116:
31527 // SIMD-ONLY0-NEXT:    [[TMP874:%.*]] = load i16, ptr [[SD]], align 2
31528 // SIMD-ONLY0-NEXT:    [[CONV2117:%.*]] = sext i16 [[TMP874]] to i32
31529 // SIMD-ONLY0-NEXT:    br label [[COND_END2120:%.*]]
31530 // SIMD-ONLY0:       cond.false2118:
31531 // SIMD-ONLY0-NEXT:    [[TMP875:%.*]] = load i16, ptr [[SX]], align 2
31532 // SIMD-ONLY0-NEXT:    [[CONV2119:%.*]] = sext i16 [[TMP875]] to i32
31533 // SIMD-ONLY0-NEXT:    br label [[COND_END2120]]
31534 // SIMD-ONLY0:       cond.end2120:
31535 // SIMD-ONLY0-NEXT:    [[COND2121:%.*]] = phi i32 [ [[CONV2117]], [[COND_TRUE2116]] ], [ [[CONV2119]], [[COND_FALSE2118]] ]
31536 // SIMD-ONLY0-NEXT:    [[CONV2122:%.*]] = trunc i32 [[COND2121]] to i16
31537 // SIMD-ONLY0-NEXT:    store i16 [[CONV2122]], ptr [[SX]], align 2
31538 // SIMD-ONLY0-NEXT:    [[TMP876:%.*]] = load i16, ptr [[SX]], align 2
31539 // SIMD-ONLY0-NEXT:    [[CONV2123:%.*]] = sext i16 [[TMP876]] to i32
31540 // SIMD-ONLY0-NEXT:    [[TMP877:%.*]] = load i16, ptr [[SE]], align 2
31541 // SIMD-ONLY0-NEXT:    [[CONV2124:%.*]] = sext i16 [[TMP877]] to i32
31542 // SIMD-ONLY0-NEXT:    [[CMP2125:%.*]] = icmp eq i32 [[CONV2123]], [[CONV2124]]
31543 // SIMD-ONLY0-NEXT:    br i1 [[CMP2125]], label [[IF_THEN2127:%.*]], label [[IF_END2128:%.*]]
31544 // SIMD-ONLY0:       if.then2127:
31545 // SIMD-ONLY0-NEXT:    [[TMP878:%.*]] = load i16, ptr [[SD]], align 2
31546 // SIMD-ONLY0-NEXT:    store i16 [[TMP878]], ptr [[SX]], align 2
31547 // SIMD-ONLY0-NEXT:    br label [[IF_END2128]]
31548 // SIMD-ONLY0:       if.end2128:
31549 // SIMD-ONLY0-NEXT:    [[TMP879:%.*]] = load i16, ptr [[SE]], align 2
31550 // SIMD-ONLY0-NEXT:    [[CONV2129:%.*]] = sext i16 [[TMP879]] to i32
31551 // SIMD-ONLY0-NEXT:    [[TMP880:%.*]] = load i16, ptr [[SX]], align 2
31552 // SIMD-ONLY0-NEXT:    [[CONV2130:%.*]] = sext i16 [[TMP880]] to i32
31553 // SIMD-ONLY0-NEXT:    [[CMP2131:%.*]] = icmp eq i32 [[CONV2129]], [[CONV2130]]
31554 // SIMD-ONLY0-NEXT:    br i1 [[CMP2131]], label [[IF_THEN2133:%.*]], label [[IF_END2134:%.*]]
31555 // SIMD-ONLY0:       if.then2133:
31556 // SIMD-ONLY0-NEXT:    [[TMP881:%.*]] = load i16, ptr [[SD]], align 2
31557 // SIMD-ONLY0-NEXT:    store i16 [[TMP881]], ptr [[SX]], align 2
31558 // SIMD-ONLY0-NEXT:    br label [[IF_END2134]]
31559 // SIMD-ONLY0:       if.end2134:
31560 // SIMD-ONLY0-NEXT:    [[TMP882:%.*]] = load i16, ptr [[USX]], align 2
31561 // SIMD-ONLY0-NEXT:    [[CONV2135:%.*]] = zext i16 [[TMP882]] to i32
31562 // SIMD-ONLY0-NEXT:    [[TMP883:%.*]] = load i16, ptr [[USE]], align 2
31563 // SIMD-ONLY0-NEXT:    [[CONV2136:%.*]] = zext i16 [[TMP883]] to i32
31564 // SIMD-ONLY0-NEXT:    [[CMP2137:%.*]] = icmp sgt i32 [[CONV2135]], [[CONV2136]]
31565 // SIMD-ONLY0-NEXT:    br i1 [[CMP2137]], label [[COND_TRUE2139:%.*]], label [[COND_FALSE2141:%.*]]
31566 // SIMD-ONLY0:       cond.true2139:
31567 // SIMD-ONLY0-NEXT:    [[TMP884:%.*]] = load i16, ptr [[USE]], align 2
31568 // SIMD-ONLY0-NEXT:    [[CONV2140:%.*]] = zext i16 [[TMP884]] to i32
31569 // SIMD-ONLY0-NEXT:    br label [[COND_END2143:%.*]]
31570 // SIMD-ONLY0:       cond.false2141:
31571 // SIMD-ONLY0-NEXT:    [[TMP885:%.*]] = load i16, ptr [[USX]], align 2
31572 // SIMD-ONLY0-NEXT:    [[CONV2142:%.*]] = zext i16 [[TMP885]] to i32
31573 // SIMD-ONLY0-NEXT:    br label [[COND_END2143]]
31574 // SIMD-ONLY0:       cond.end2143:
31575 // SIMD-ONLY0-NEXT:    [[COND2144:%.*]] = phi i32 [ [[CONV2140]], [[COND_TRUE2139]] ], [ [[CONV2142]], [[COND_FALSE2141]] ]
31576 // SIMD-ONLY0-NEXT:    [[CONV2145:%.*]] = trunc i32 [[COND2144]] to i16
31577 // SIMD-ONLY0-NEXT:    store i16 [[CONV2145]], ptr [[USX]], align 2
31578 // SIMD-ONLY0-NEXT:    [[TMP886:%.*]] = load i16, ptr [[USX]], align 2
31579 // SIMD-ONLY0-NEXT:    [[CONV2146:%.*]] = zext i16 [[TMP886]] to i32
31580 // SIMD-ONLY0-NEXT:    [[TMP887:%.*]] = load i16, ptr [[USE]], align 2
31581 // SIMD-ONLY0-NEXT:    [[CONV2147:%.*]] = zext i16 [[TMP887]] to i32
31582 // SIMD-ONLY0-NEXT:    [[CMP2148:%.*]] = icmp slt i32 [[CONV2146]], [[CONV2147]]
31583 // SIMD-ONLY0-NEXT:    br i1 [[CMP2148]], label [[COND_TRUE2150:%.*]], label [[COND_FALSE2152:%.*]]
31584 // SIMD-ONLY0:       cond.true2150:
31585 // SIMD-ONLY0-NEXT:    [[TMP888:%.*]] = load i16, ptr [[USE]], align 2
31586 // SIMD-ONLY0-NEXT:    [[CONV2151:%.*]] = zext i16 [[TMP888]] to i32
31587 // SIMD-ONLY0-NEXT:    br label [[COND_END2154:%.*]]
31588 // SIMD-ONLY0:       cond.false2152:
31589 // SIMD-ONLY0-NEXT:    [[TMP889:%.*]] = load i16, ptr [[USX]], align 2
31590 // SIMD-ONLY0-NEXT:    [[CONV2153:%.*]] = zext i16 [[TMP889]] to i32
31591 // SIMD-ONLY0-NEXT:    br label [[COND_END2154]]
31592 // SIMD-ONLY0:       cond.end2154:
31593 // SIMD-ONLY0-NEXT:    [[COND2155:%.*]] = phi i32 [ [[CONV2151]], [[COND_TRUE2150]] ], [ [[CONV2153]], [[COND_FALSE2152]] ]
31594 // SIMD-ONLY0-NEXT:    [[CONV2156:%.*]] = trunc i32 [[COND2155]] to i16
31595 // SIMD-ONLY0-NEXT:    store i16 [[CONV2156]], ptr [[USX]], align 2
31596 // SIMD-ONLY0-NEXT:    [[TMP890:%.*]] = load i16, ptr [[USE]], align 2
31597 // SIMD-ONLY0-NEXT:    [[CONV2157:%.*]] = zext i16 [[TMP890]] to i32
31598 // SIMD-ONLY0-NEXT:    [[TMP891:%.*]] = load i16, ptr [[USX]], align 2
31599 // SIMD-ONLY0-NEXT:    [[CONV2158:%.*]] = zext i16 [[TMP891]] to i32
31600 // SIMD-ONLY0-NEXT:    [[CMP2159:%.*]] = icmp sgt i32 [[CONV2157]], [[CONV2158]]
31601 // SIMD-ONLY0-NEXT:    br i1 [[CMP2159]], label [[COND_TRUE2161:%.*]], label [[COND_FALSE2163:%.*]]
31602 // SIMD-ONLY0:       cond.true2161:
31603 // SIMD-ONLY0-NEXT:    [[TMP892:%.*]] = load i16, ptr [[USE]], align 2
31604 // SIMD-ONLY0-NEXT:    [[CONV2162:%.*]] = zext i16 [[TMP892]] to i32
31605 // SIMD-ONLY0-NEXT:    br label [[COND_END2165:%.*]]
31606 // SIMD-ONLY0:       cond.false2163:
31607 // SIMD-ONLY0-NEXT:    [[TMP893:%.*]] = load i16, ptr [[USX]], align 2
31608 // SIMD-ONLY0-NEXT:    [[CONV2164:%.*]] = zext i16 [[TMP893]] to i32
31609 // SIMD-ONLY0-NEXT:    br label [[COND_END2165]]
31610 // SIMD-ONLY0:       cond.end2165:
31611 // SIMD-ONLY0-NEXT:    [[COND2166:%.*]] = phi i32 [ [[CONV2162]], [[COND_TRUE2161]] ], [ [[CONV2164]], [[COND_FALSE2163]] ]
31612 // SIMD-ONLY0-NEXT:    [[CONV2167:%.*]] = trunc i32 [[COND2166]] to i16
31613 // SIMD-ONLY0-NEXT:    store i16 [[CONV2167]], ptr [[USX]], align 2
31614 // SIMD-ONLY0-NEXT:    [[TMP894:%.*]] = load i16, ptr [[USE]], align 2
31615 // SIMD-ONLY0-NEXT:    [[CONV2168:%.*]] = zext i16 [[TMP894]] to i32
31616 // SIMD-ONLY0-NEXT:    [[TMP895:%.*]] = load i16, ptr [[USX]], align 2
31617 // SIMD-ONLY0-NEXT:    [[CONV2169:%.*]] = zext i16 [[TMP895]] to i32
31618 // SIMD-ONLY0-NEXT:    [[CMP2170:%.*]] = icmp slt i32 [[CONV2168]], [[CONV2169]]
31619 // SIMD-ONLY0-NEXT:    br i1 [[CMP2170]], label [[COND_TRUE2172:%.*]], label [[COND_FALSE2174:%.*]]
31620 // SIMD-ONLY0:       cond.true2172:
31621 // SIMD-ONLY0-NEXT:    [[TMP896:%.*]] = load i16, ptr [[USE]], align 2
31622 // SIMD-ONLY0-NEXT:    [[CONV2173:%.*]] = zext i16 [[TMP896]] to i32
31623 // SIMD-ONLY0-NEXT:    br label [[COND_END2176:%.*]]
31624 // SIMD-ONLY0:       cond.false2174:
31625 // SIMD-ONLY0-NEXT:    [[TMP897:%.*]] = load i16, ptr [[USX]], align 2
31626 // SIMD-ONLY0-NEXT:    [[CONV2175:%.*]] = zext i16 [[TMP897]] to i32
31627 // SIMD-ONLY0-NEXT:    br label [[COND_END2176]]
31628 // SIMD-ONLY0:       cond.end2176:
31629 // SIMD-ONLY0-NEXT:    [[COND2177:%.*]] = phi i32 [ [[CONV2173]], [[COND_TRUE2172]] ], [ [[CONV2175]], [[COND_FALSE2174]] ]
31630 // SIMD-ONLY0-NEXT:    [[CONV2178:%.*]] = trunc i32 [[COND2177]] to i16
31631 // SIMD-ONLY0-NEXT:    store i16 [[CONV2178]], ptr [[USX]], align 2
31632 // SIMD-ONLY0-NEXT:    [[TMP898:%.*]] = load i16, ptr [[USX]], align 2
31633 // SIMD-ONLY0-NEXT:    [[CONV2179:%.*]] = zext i16 [[TMP898]] to i32
31634 // SIMD-ONLY0-NEXT:    [[TMP899:%.*]] = load i16, ptr [[USE]], align 2
31635 // SIMD-ONLY0-NEXT:    [[CONV2180:%.*]] = zext i16 [[TMP899]] to i32
31636 // SIMD-ONLY0-NEXT:    [[CMP2181:%.*]] = icmp sgt i32 [[CONV2179]], [[CONV2180]]
31637 // SIMD-ONLY0-NEXT:    br i1 [[CMP2181]], label [[IF_THEN2183:%.*]], label [[IF_END2184:%.*]]
31638 // SIMD-ONLY0:       if.then2183:
31639 // SIMD-ONLY0-NEXT:    [[TMP900:%.*]] = load i16, ptr [[USE]], align 2
31640 // SIMD-ONLY0-NEXT:    store i16 [[TMP900]], ptr [[USX]], align 2
31641 // SIMD-ONLY0-NEXT:    br label [[IF_END2184]]
31642 // SIMD-ONLY0:       if.end2184:
31643 // SIMD-ONLY0-NEXT:    [[TMP901:%.*]] = load i16, ptr [[USX]], align 2
31644 // SIMD-ONLY0-NEXT:    [[CONV2185:%.*]] = zext i16 [[TMP901]] to i32
31645 // SIMD-ONLY0-NEXT:    [[TMP902:%.*]] = load i16, ptr [[USE]], align 2
31646 // SIMD-ONLY0-NEXT:    [[CONV2186:%.*]] = zext i16 [[TMP902]] to i32
31647 // SIMD-ONLY0-NEXT:    [[CMP2187:%.*]] = icmp slt i32 [[CONV2185]], [[CONV2186]]
31648 // SIMD-ONLY0-NEXT:    br i1 [[CMP2187]], label [[IF_THEN2189:%.*]], label [[IF_END2190:%.*]]
31649 // SIMD-ONLY0:       if.then2189:
31650 // SIMD-ONLY0-NEXT:    [[TMP903:%.*]] = load i16, ptr [[USE]], align 2
31651 // SIMD-ONLY0-NEXT:    store i16 [[TMP903]], ptr [[USX]], align 2
31652 // SIMD-ONLY0-NEXT:    br label [[IF_END2190]]
31653 // SIMD-ONLY0:       if.end2190:
31654 // SIMD-ONLY0-NEXT:    [[TMP904:%.*]] = load i16, ptr [[USE]], align 2
31655 // SIMD-ONLY0-NEXT:    [[CONV2191:%.*]] = zext i16 [[TMP904]] to i32
31656 // SIMD-ONLY0-NEXT:    [[TMP905:%.*]] = load i16, ptr [[USX]], align 2
31657 // SIMD-ONLY0-NEXT:    [[CONV2192:%.*]] = zext i16 [[TMP905]] to i32
31658 // SIMD-ONLY0-NEXT:    [[CMP2193:%.*]] = icmp sgt i32 [[CONV2191]], [[CONV2192]]
31659 // SIMD-ONLY0-NEXT:    br i1 [[CMP2193]], label [[IF_THEN2195:%.*]], label [[IF_END2196:%.*]]
31660 // SIMD-ONLY0:       if.then2195:
31661 // SIMD-ONLY0-NEXT:    [[TMP906:%.*]] = load i16, ptr [[USE]], align 2
31662 // SIMD-ONLY0-NEXT:    store i16 [[TMP906]], ptr [[USX]], align 2
31663 // SIMD-ONLY0-NEXT:    br label [[IF_END2196]]
31664 // SIMD-ONLY0:       if.end2196:
31665 // SIMD-ONLY0-NEXT:    [[TMP907:%.*]] = load i16, ptr [[USE]], align 2
31666 // SIMD-ONLY0-NEXT:    [[CONV2197:%.*]] = zext i16 [[TMP907]] to i32
31667 // SIMD-ONLY0-NEXT:    [[TMP908:%.*]] = load i16, ptr [[USX]], align 2
31668 // SIMD-ONLY0-NEXT:    [[CONV2198:%.*]] = zext i16 [[TMP908]] to i32
31669 // SIMD-ONLY0-NEXT:    [[CMP2199:%.*]] = icmp slt i32 [[CONV2197]], [[CONV2198]]
31670 // SIMD-ONLY0-NEXT:    br i1 [[CMP2199]], label [[IF_THEN2201:%.*]], label [[IF_END2202:%.*]]
31671 // SIMD-ONLY0:       if.then2201:
31672 // SIMD-ONLY0-NEXT:    [[TMP909:%.*]] = load i16, ptr [[USE]], align 2
31673 // SIMD-ONLY0-NEXT:    store i16 [[TMP909]], ptr [[USX]], align 2
31674 // SIMD-ONLY0-NEXT:    br label [[IF_END2202]]
31675 // SIMD-ONLY0:       if.end2202:
31676 // SIMD-ONLY0-NEXT:    [[TMP910:%.*]] = load i16, ptr [[USX]], align 2
31677 // SIMD-ONLY0-NEXT:    [[CONV2203:%.*]] = zext i16 [[TMP910]] to i32
31678 // SIMD-ONLY0-NEXT:    [[TMP911:%.*]] = load i16, ptr [[USE]], align 2
31679 // SIMD-ONLY0-NEXT:    [[CONV2204:%.*]] = zext i16 [[TMP911]] to i32
31680 // SIMD-ONLY0-NEXT:    [[CMP2205:%.*]] = icmp eq i32 [[CONV2203]], [[CONV2204]]
31681 // SIMD-ONLY0-NEXT:    br i1 [[CMP2205]], label [[COND_TRUE2207:%.*]], label [[COND_FALSE2209:%.*]]
31682 // SIMD-ONLY0:       cond.true2207:
31683 // SIMD-ONLY0-NEXT:    [[TMP912:%.*]] = load i16, ptr [[USD]], align 2
31684 // SIMD-ONLY0-NEXT:    [[CONV2208:%.*]] = zext i16 [[TMP912]] to i32
31685 // SIMD-ONLY0-NEXT:    br label [[COND_END2211:%.*]]
31686 // SIMD-ONLY0:       cond.false2209:
31687 // SIMD-ONLY0-NEXT:    [[TMP913:%.*]] = load i16, ptr [[USX]], align 2
31688 // SIMD-ONLY0-NEXT:    [[CONV2210:%.*]] = zext i16 [[TMP913]] to i32
31689 // SIMD-ONLY0-NEXT:    br label [[COND_END2211]]
31690 // SIMD-ONLY0:       cond.end2211:
31691 // SIMD-ONLY0-NEXT:    [[COND2212:%.*]] = phi i32 [ [[CONV2208]], [[COND_TRUE2207]] ], [ [[CONV2210]], [[COND_FALSE2209]] ]
31692 // SIMD-ONLY0-NEXT:    [[CONV2213:%.*]] = trunc i32 [[COND2212]] to i16
31693 // SIMD-ONLY0-NEXT:    store i16 [[CONV2213]], ptr [[USX]], align 2
31694 // SIMD-ONLY0-NEXT:    [[TMP914:%.*]] = load i16, ptr [[USE]], align 2
31695 // SIMD-ONLY0-NEXT:    [[CONV2214:%.*]] = zext i16 [[TMP914]] to i32
31696 // SIMD-ONLY0-NEXT:    [[TMP915:%.*]] = load i16, ptr [[USX]], align 2
31697 // SIMD-ONLY0-NEXT:    [[CONV2215:%.*]] = zext i16 [[TMP915]] to i32
31698 // SIMD-ONLY0-NEXT:    [[CMP2216:%.*]] = icmp eq i32 [[CONV2214]], [[CONV2215]]
31699 // SIMD-ONLY0-NEXT:    br i1 [[CMP2216]], label [[COND_TRUE2218:%.*]], label [[COND_FALSE2220:%.*]]
31700 // SIMD-ONLY0:       cond.true2218:
31701 // SIMD-ONLY0-NEXT:    [[TMP916:%.*]] = load i16, ptr [[USD]], align 2
31702 // SIMD-ONLY0-NEXT:    [[CONV2219:%.*]] = zext i16 [[TMP916]] to i32
31703 // SIMD-ONLY0-NEXT:    br label [[COND_END2222:%.*]]
31704 // SIMD-ONLY0:       cond.false2220:
31705 // SIMD-ONLY0-NEXT:    [[TMP917:%.*]] = load i16, ptr [[USX]], align 2
31706 // SIMD-ONLY0-NEXT:    [[CONV2221:%.*]] = zext i16 [[TMP917]] to i32
31707 // SIMD-ONLY0-NEXT:    br label [[COND_END2222]]
31708 // SIMD-ONLY0:       cond.end2222:
31709 // SIMD-ONLY0-NEXT:    [[COND2223:%.*]] = phi i32 [ [[CONV2219]], [[COND_TRUE2218]] ], [ [[CONV2221]], [[COND_FALSE2220]] ]
31710 // SIMD-ONLY0-NEXT:    [[CONV2224:%.*]] = trunc i32 [[COND2223]] to i16
31711 // SIMD-ONLY0-NEXT:    store i16 [[CONV2224]], ptr [[USX]], align 2
31712 // SIMD-ONLY0-NEXT:    [[TMP918:%.*]] = load i16, ptr [[USX]], align 2
31713 // SIMD-ONLY0-NEXT:    [[CONV2225:%.*]] = zext i16 [[TMP918]] to i32
31714 // SIMD-ONLY0-NEXT:    [[TMP919:%.*]] = load i16, ptr [[USE]], align 2
31715 // SIMD-ONLY0-NEXT:    [[CONV2226:%.*]] = zext i16 [[TMP919]] to i32
31716 // SIMD-ONLY0-NEXT:    [[CMP2227:%.*]] = icmp eq i32 [[CONV2225]], [[CONV2226]]
31717 // SIMD-ONLY0-NEXT:    br i1 [[CMP2227]], label [[IF_THEN2229:%.*]], label [[IF_END2230:%.*]]
31718 // SIMD-ONLY0:       if.then2229:
31719 // SIMD-ONLY0-NEXT:    [[TMP920:%.*]] = load i16, ptr [[USD]], align 2
31720 // SIMD-ONLY0-NEXT:    store i16 [[TMP920]], ptr [[USX]], align 2
31721 // SIMD-ONLY0-NEXT:    br label [[IF_END2230]]
31722 // SIMD-ONLY0:       if.end2230:
31723 // SIMD-ONLY0-NEXT:    [[TMP921:%.*]] = load i16, ptr [[USE]], align 2
31724 // SIMD-ONLY0-NEXT:    [[CONV2231:%.*]] = zext i16 [[TMP921]] to i32
31725 // SIMD-ONLY0-NEXT:    [[TMP922:%.*]] = load i16, ptr [[USX]], align 2
31726 // SIMD-ONLY0-NEXT:    [[CONV2232:%.*]] = zext i16 [[TMP922]] to i32
31727 // SIMD-ONLY0-NEXT:    [[CMP2233:%.*]] = icmp eq i32 [[CONV2231]], [[CONV2232]]
31728 // SIMD-ONLY0-NEXT:    br i1 [[CMP2233]], label [[IF_THEN2235:%.*]], label [[IF_END2236:%.*]]
31729 // SIMD-ONLY0:       if.then2235:
31730 // SIMD-ONLY0-NEXT:    [[TMP923:%.*]] = load i16, ptr [[USD]], align 2
31731 // SIMD-ONLY0-NEXT:    store i16 [[TMP923]], ptr [[USX]], align 2
31732 // SIMD-ONLY0-NEXT:    br label [[IF_END2236]]
31733 // SIMD-ONLY0:       if.end2236:
31734 // SIMD-ONLY0-NEXT:    [[TMP924:%.*]] = load i16, ptr [[SX]], align 2
31735 // SIMD-ONLY0-NEXT:    [[CONV2237:%.*]] = sext i16 [[TMP924]] to i32
31736 // SIMD-ONLY0-NEXT:    [[TMP925:%.*]] = load i16, ptr [[SE]], align 2
31737 // SIMD-ONLY0-NEXT:    [[CONV2238:%.*]] = sext i16 [[TMP925]] to i32
31738 // SIMD-ONLY0-NEXT:    [[CMP2239:%.*]] = icmp sgt i32 [[CONV2237]], [[CONV2238]]
31739 // SIMD-ONLY0-NEXT:    br i1 [[CMP2239]], label [[COND_TRUE2241:%.*]], label [[COND_FALSE2243:%.*]]
31740 // SIMD-ONLY0:       cond.true2241:
31741 // SIMD-ONLY0-NEXT:    [[TMP926:%.*]] = load i16, ptr [[SE]], align 2
31742 // SIMD-ONLY0-NEXT:    [[CONV2242:%.*]] = sext i16 [[TMP926]] to i32
31743 // SIMD-ONLY0-NEXT:    br label [[COND_END2245:%.*]]
31744 // SIMD-ONLY0:       cond.false2243:
31745 // SIMD-ONLY0-NEXT:    [[TMP927:%.*]] = load i16, ptr [[SX]], align 2
31746 // SIMD-ONLY0-NEXT:    [[CONV2244:%.*]] = sext i16 [[TMP927]] to i32
31747 // SIMD-ONLY0-NEXT:    br label [[COND_END2245]]
31748 // SIMD-ONLY0:       cond.end2245:
31749 // SIMD-ONLY0-NEXT:    [[COND2246:%.*]] = phi i32 [ [[CONV2242]], [[COND_TRUE2241]] ], [ [[CONV2244]], [[COND_FALSE2243]] ]
31750 // SIMD-ONLY0-NEXT:    [[CONV2247:%.*]] = trunc i32 [[COND2246]] to i16
31751 // SIMD-ONLY0-NEXT:    store i16 [[CONV2247]], ptr [[SX]], align 2
31752 // SIMD-ONLY0-NEXT:    [[TMP928:%.*]] = load i16, ptr [[SX]], align 2
31753 // SIMD-ONLY0-NEXT:    [[CONV2248:%.*]] = sext i16 [[TMP928]] to i32
31754 // SIMD-ONLY0-NEXT:    [[TMP929:%.*]] = load i16, ptr [[SE]], align 2
31755 // SIMD-ONLY0-NEXT:    [[CONV2249:%.*]] = sext i16 [[TMP929]] to i32
31756 // SIMD-ONLY0-NEXT:    [[CMP2250:%.*]] = icmp slt i32 [[CONV2248]], [[CONV2249]]
31757 // SIMD-ONLY0-NEXT:    br i1 [[CMP2250]], label [[COND_TRUE2252:%.*]], label [[COND_FALSE2254:%.*]]
31758 // SIMD-ONLY0:       cond.true2252:
31759 // SIMD-ONLY0-NEXT:    [[TMP930:%.*]] = load i16, ptr [[SE]], align 2
31760 // SIMD-ONLY0-NEXT:    [[CONV2253:%.*]] = sext i16 [[TMP930]] to i32
31761 // SIMD-ONLY0-NEXT:    br label [[COND_END2256:%.*]]
31762 // SIMD-ONLY0:       cond.false2254:
31763 // SIMD-ONLY0-NEXT:    [[TMP931:%.*]] = load i16, ptr [[SX]], align 2
31764 // SIMD-ONLY0-NEXT:    [[CONV2255:%.*]] = sext i16 [[TMP931]] to i32
31765 // SIMD-ONLY0-NEXT:    br label [[COND_END2256]]
31766 // SIMD-ONLY0:       cond.end2256:
31767 // SIMD-ONLY0-NEXT:    [[COND2257:%.*]] = phi i32 [ [[CONV2253]], [[COND_TRUE2252]] ], [ [[CONV2255]], [[COND_FALSE2254]] ]
31768 // SIMD-ONLY0-NEXT:    [[CONV2258:%.*]] = trunc i32 [[COND2257]] to i16
31769 // SIMD-ONLY0-NEXT:    store i16 [[CONV2258]], ptr [[SX]], align 2
31770 // SIMD-ONLY0-NEXT:    [[TMP932:%.*]] = load i16, ptr [[SE]], align 2
31771 // SIMD-ONLY0-NEXT:    [[CONV2259:%.*]] = sext i16 [[TMP932]] to i32
31772 // SIMD-ONLY0-NEXT:    [[TMP933:%.*]] = load i16, ptr [[SX]], align 2
31773 // SIMD-ONLY0-NEXT:    [[CONV2260:%.*]] = sext i16 [[TMP933]] to i32
31774 // SIMD-ONLY0-NEXT:    [[CMP2261:%.*]] = icmp sgt i32 [[CONV2259]], [[CONV2260]]
31775 // SIMD-ONLY0-NEXT:    br i1 [[CMP2261]], label [[COND_TRUE2263:%.*]], label [[COND_FALSE2265:%.*]]
31776 // SIMD-ONLY0:       cond.true2263:
31777 // SIMD-ONLY0-NEXT:    [[TMP934:%.*]] = load i16, ptr [[SE]], align 2
31778 // SIMD-ONLY0-NEXT:    [[CONV2264:%.*]] = sext i16 [[TMP934]] to i32
31779 // SIMD-ONLY0-NEXT:    br label [[COND_END2267:%.*]]
31780 // SIMD-ONLY0:       cond.false2265:
31781 // SIMD-ONLY0-NEXT:    [[TMP935:%.*]] = load i16, ptr [[SX]], align 2
31782 // SIMD-ONLY0-NEXT:    [[CONV2266:%.*]] = sext i16 [[TMP935]] to i32
31783 // SIMD-ONLY0-NEXT:    br label [[COND_END2267]]
31784 // SIMD-ONLY0:       cond.end2267:
31785 // SIMD-ONLY0-NEXT:    [[COND2268:%.*]] = phi i32 [ [[CONV2264]], [[COND_TRUE2263]] ], [ [[CONV2266]], [[COND_FALSE2265]] ]
31786 // SIMD-ONLY0-NEXT:    [[CONV2269:%.*]] = trunc i32 [[COND2268]] to i16
31787 // SIMD-ONLY0-NEXT:    store i16 [[CONV2269]], ptr [[SX]], align 2
31788 // SIMD-ONLY0-NEXT:    [[TMP936:%.*]] = load i16, ptr [[SE]], align 2
31789 // SIMD-ONLY0-NEXT:    [[CONV2270:%.*]] = sext i16 [[TMP936]] to i32
31790 // SIMD-ONLY0-NEXT:    [[TMP937:%.*]] = load i16, ptr [[SX]], align 2
31791 // SIMD-ONLY0-NEXT:    [[CONV2271:%.*]] = sext i16 [[TMP937]] to i32
31792 // SIMD-ONLY0-NEXT:    [[CMP2272:%.*]] = icmp slt i32 [[CONV2270]], [[CONV2271]]
31793 // SIMD-ONLY0-NEXT:    br i1 [[CMP2272]], label [[COND_TRUE2274:%.*]], label [[COND_FALSE2276:%.*]]
31794 // SIMD-ONLY0:       cond.true2274:
31795 // SIMD-ONLY0-NEXT:    [[TMP938:%.*]] = load i16, ptr [[SE]], align 2
31796 // SIMD-ONLY0-NEXT:    [[CONV2275:%.*]] = sext i16 [[TMP938]] to i32
31797 // SIMD-ONLY0-NEXT:    br label [[COND_END2278:%.*]]
31798 // SIMD-ONLY0:       cond.false2276:
31799 // SIMD-ONLY0-NEXT:    [[TMP939:%.*]] = load i16, ptr [[SX]], align 2
31800 // SIMD-ONLY0-NEXT:    [[CONV2277:%.*]] = sext i16 [[TMP939]] to i32
31801 // SIMD-ONLY0-NEXT:    br label [[COND_END2278]]
31802 // SIMD-ONLY0:       cond.end2278:
31803 // SIMD-ONLY0-NEXT:    [[COND2279:%.*]] = phi i32 [ [[CONV2275]], [[COND_TRUE2274]] ], [ [[CONV2277]], [[COND_FALSE2276]] ]
31804 // SIMD-ONLY0-NEXT:    [[CONV2280:%.*]] = trunc i32 [[COND2279]] to i16
31805 // SIMD-ONLY0-NEXT:    store i16 [[CONV2280]], ptr [[SX]], align 2
31806 // SIMD-ONLY0-NEXT:    [[TMP940:%.*]] = load i16, ptr [[SX]], align 2
31807 // SIMD-ONLY0-NEXT:    [[CONV2281:%.*]] = sext i16 [[TMP940]] to i32
31808 // SIMD-ONLY0-NEXT:    [[TMP941:%.*]] = load i16, ptr [[SE]], align 2
31809 // SIMD-ONLY0-NEXT:    [[CONV2282:%.*]] = sext i16 [[TMP941]] to i32
31810 // SIMD-ONLY0-NEXT:    [[CMP2283:%.*]] = icmp sgt i32 [[CONV2281]], [[CONV2282]]
31811 // SIMD-ONLY0-NEXT:    br i1 [[CMP2283]], label [[IF_THEN2285:%.*]], label [[IF_END2286:%.*]]
31812 // SIMD-ONLY0:       if.then2285:
31813 // SIMD-ONLY0-NEXT:    [[TMP942:%.*]] = load i16, ptr [[SE]], align 2
31814 // SIMD-ONLY0-NEXT:    store i16 [[TMP942]], ptr [[SX]], align 2
31815 // SIMD-ONLY0-NEXT:    br label [[IF_END2286]]
31816 // SIMD-ONLY0:       if.end2286:
31817 // SIMD-ONLY0-NEXT:    [[TMP943:%.*]] = load i16, ptr [[SX]], align 2
31818 // SIMD-ONLY0-NEXT:    [[CONV2287:%.*]] = sext i16 [[TMP943]] to i32
31819 // SIMD-ONLY0-NEXT:    [[TMP944:%.*]] = load i16, ptr [[SE]], align 2
31820 // SIMD-ONLY0-NEXT:    [[CONV2288:%.*]] = sext i16 [[TMP944]] to i32
31821 // SIMD-ONLY0-NEXT:    [[CMP2289:%.*]] = icmp slt i32 [[CONV2287]], [[CONV2288]]
31822 // SIMD-ONLY0-NEXT:    br i1 [[CMP2289]], label [[IF_THEN2291:%.*]], label [[IF_END2292:%.*]]
31823 // SIMD-ONLY0:       if.then2291:
31824 // SIMD-ONLY0-NEXT:    [[TMP945:%.*]] = load i16, ptr [[SE]], align 2
31825 // SIMD-ONLY0-NEXT:    store i16 [[TMP945]], ptr [[SX]], align 2
31826 // SIMD-ONLY0-NEXT:    br label [[IF_END2292]]
31827 // SIMD-ONLY0:       if.end2292:
31828 // SIMD-ONLY0-NEXT:    [[TMP946:%.*]] = load i16, ptr [[SE]], align 2
31829 // SIMD-ONLY0-NEXT:    [[CONV2293:%.*]] = sext i16 [[TMP946]] to i32
31830 // SIMD-ONLY0-NEXT:    [[TMP947:%.*]] = load i16, ptr [[SX]], align 2
31831 // SIMD-ONLY0-NEXT:    [[CONV2294:%.*]] = sext i16 [[TMP947]] to i32
31832 // SIMD-ONLY0-NEXT:    [[CMP2295:%.*]] = icmp sgt i32 [[CONV2293]], [[CONV2294]]
31833 // SIMD-ONLY0-NEXT:    br i1 [[CMP2295]], label [[IF_THEN2297:%.*]], label [[IF_END2298:%.*]]
31834 // SIMD-ONLY0:       if.then2297:
31835 // SIMD-ONLY0-NEXT:    [[TMP948:%.*]] = load i16, ptr [[SE]], align 2
31836 // SIMD-ONLY0-NEXT:    store i16 [[TMP948]], ptr [[SX]], align 2
31837 // SIMD-ONLY0-NEXT:    br label [[IF_END2298]]
31838 // SIMD-ONLY0:       if.end2298:
31839 // SIMD-ONLY0-NEXT:    [[TMP949:%.*]] = load i16, ptr [[SE]], align 2
31840 // SIMD-ONLY0-NEXT:    [[CONV2299:%.*]] = sext i16 [[TMP949]] to i32
31841 // SIMD-ONLY0-NEXT:    [[TMP950:%.*]] = load i16, ptr [[SX]], align 2
31842 // SIMD-ONLY0-NEXT:    [[CONV2300:%.*]] = sext i16 [[TMP950]] to i32
31843 // SIMD-ONLY0-NEXT:    [[CMP2301:%.*]] = icmp slt i32 [[CONV2299]], [[CONV2300]]
31844 // SIMD-ONLY0-NEXT:    br i1 [[CMP2301]], label [[IF_THEN2303:%.*]], label [[IF_END2304:%.*]]
31845 // SIMD-ONLY0:       if.then2303:
31846 // SIMD-ONLY0-NEXT:    [[TMP951:%.*]] = load i16, ptr [[SE]], align 2
31847 // SIMD-ONLY0-NEXT:    store i16 [[TMP951]], ptr [[SX]], align 2
31848 // SIMD-ONLY0-NEXT:    br label [[IF_END2304]]
31849 // SIMD-ONLY0:       if.end2304:
31850 // SIMD-ONLY0-NEXT:    [[TMP952:%.*]] = load i16, ptr [[SX]], align 2
31851 // SIMD-ONLY0-NEXT:    [[CONV2305:%.*]] = sext i16 [[TMP952]] to i32
31852 // SIMD-ONLY0-NEXT:    [[TMP953:%.*]] = load i16, ptr [[SE]], align 2
31853 // SIMD-ONLY0-NEXT:    [[CONV2306:%.*]] = sext i16 [[TMP953]] to i32
31854 // SIMD-ONLY0-NEXT:    [[CMP2307:%.*]] = icmp eq i32 [[CONV2305]], [[CONV2306]]
31855 // SIMD-ONLY0-NEXT:    br i1 [[CMP2307]], label [[COND_TRUE2309:%.*]], label [[COND_FALSE2311:%.*]]
31856 // SIMD-ONLY0:       cond.true2309:
31857 // SIMD-ONLY0-NEXT:    [[TMP954:%.*]] = load i16, ptr [[SD]], align 2
31858 // SIMD-ONLY0-NEXT:    [[CONV2310:%.*]] = sext i16 [[TMP954]] to i32
31859 // SIMD-ONLY0-NEXT:    br label [[COND_END2313:%.*]]
31860 // SIMD-ONLY0:       cond.false2311:
31861 // SIMD-ONLY0-NEXT:    [[TMP955:%.*]] = load i16, ptr [[SX]], align 2
31862 // SIMD-ONLY0-NEXT:    [[CONV2312:%.*]] = sext i16 [[TMP955]] to i32
31863 // SIMD-ONLY0-NEXT:    br label [[COND_END2313]]
31864 // SIMD-ONLY0:       cond.end2313:
31865 // SIMD-ONLY0-NEXT:    [[COND2314:%.*]] = phi i32 [ [[CONV2310]], [[COND_TRUE2309]] ], [ [[CONV2312]], [[COND_FALSE2311]] ]
31866 // SIMD-ONLY0-NEXT:    [[CONV2315:%.*]] = trunc i32 [[COND2314]] to i16
31867 // SIMD-ONLY0-NEXT:    store i16 [[CONV2315]], ptr [[SX]], align 2
31868 // SIMD-ONLY0-NEXT:    [[TMP956:%.*]] = load i16, ptr [[SE]], align 2
31869 // SIMD-ONLY0-NEXT:    [[CONV2316:%.*]] = sext i16 [[TMP956]] to i32
31870 // SIMD-ONLY0-NEXT:    [[TMP957:%.*]] = load i16, ptr [[SX]], align 2
31871 // SIMD-ONLY0-NEXT:    [[CONV2317:%.*]] = sext i16 [[TMP957]] to i32
31872 // SIMD-ONLY0-NEXT:    [[CMP2318:%.*]] = icmp eq i32 [[CONV2316]], [[CONV2317]]
31873 // SIMD-ONLY0-NEXT:    br i1 [[CMP2318]], label [[COND_TRUE2320:%.*]], label [[COND_FALSE2322:%.*]]
31874 // SIMD-ONLY0:       cond.true2320:
31875 // SIMD-ONLY0-NEXT:    [[TMP958:%.*]] = load i16, ptr [[SD]], align 2
31876 // SIMD-ONLY0-NEXT:    [[CONV2321:%.*]] = sext i16 [[TMP958]] to i32
31877 // SIMD-ONLY0-NEXT:    br label [[COND_END2324:%.*]]
31878 // SIMD-ONLY0:       cond.false2322:
31879 // SIMD-ONLY0-NEXT:    [[TMP959:%.*]] = load i16, ptr [[SX]], align 2
31880 // SIMD-ONLY0-NEXT:    [[CONV2323:%.*]] = sext i16 [[TMP959]] to i32
31881 // SIMD-ONLY0-NEXT:    br label [[COND_END2324]]
31882 // SIMD-ONLY0:       cond.end2324:
31883 // SIMD-ONLY0-NEXT:    [[COND2325:%.*]] = phi i32 [ [[CONV2321]], [[COND_TRUE2320]] ], [ [[CONV2323]], [[COND_FALSE2322]] ]
31884 // SIMD-ONLY0-NEXT:    [[CONV2326:%.*]] = trunc i32 [[COND2325]] to i16
31885 // SIMD-ONLY0-NEXT:    store i16 [[CONV2326]], ptr [[SX]], align 2
31886 // SIMD-ONLY0-NEXT:    [[TMP960:%.*]] = load i16, ptr [[SX]], align 2
31887 // SIMD-ONLY0-NEXT:    [[CONV2327:%.*]] = sext i16 [[TMP960]] to i32
31888 // SIMD-ONLY0-NEXT:    [[TMP961:%.*]] = load i16, ptr [[SE]], align 2
31889 // SIMD-ONLY0-NEXT:    [[CONV2328:%.*]] = sext i16 [[TMP961]] to i32
31890 // SIMD-ONLY0-NEXT:    [[CMP2329:%.*]] = icmp eq i32 [[CONV2327]], [[CONV2328]]
31891 // SIMD-ONLY0-NEXT:    br i1 [[CMP2329]], label [[IF_THEN2331:%.*]], label [[IF_END2332:%.*]]
31892 // SIMD-ONLY0:       if.then2331:
31893 // SIMD-ONLY0-NEXT:    [[TMP962:%.*]] = load i16, ptr [[SD]], align 2
31894 // SIMD-ONLY0-NEXT:    store i16 [[TMP962]], ptr [[SX]], align 2
31895 // SIMD-ONLY0-NEXT:    br label [[IF_END2332]]
31896 // SIMD-ONLY0:       if.end2332:
31897 // SIMD-ONLY0-NEXT:    [[TMP963:%.*]] = load i16, ptr [[SE]], align 2
31898 // SIMD-ONLY0-NEXT:    [[CONV2333:%.*]] = sext i16 [[TMP963]] to i32
31899 // SIMD-ONLY0-NEXT:    [[TMP964:%.*]] = load i16, ptr [[SX]], align 2
31900 // SIMD-ONLY0-NEXT:    [[CONV2334:%.*]] = sext i16 [[TMP964]] to i32
31901 // SIMD-ONLY0-NEXT:    [[CMP2335:%.*]] = icmp eq i32 [[CONV2333]], [[CONV2334]]
31902 // SIMD-ONLY0-NEXT:    br i1 [[CMP2335]], label [[IF_THEN2337:%.*]], label [[IF_END2338:%.*]]
31903 // SIMD-ONLY0:       if.then2337:
31904 // SIMD-ONLY0-NEXT:    [[TMP965:%.*]] = load i16, ptr [[SD]], align 2
31905 // SIMD-ONLY0-NEXT:    store i16 [[TMP965]], ptr [[SX]], align 2
31906 // SIMD-ONLY0-NEXT:    br label [[IF_END2338]]
31907 // SIMD-ONLY0:       if.end2338:
31908 // SIMD-ONLY0-NEXT:    [[TMP966:%.*]] = load i16, ptr [[USX]], align 2
31909 // SIMD-ONLY0-NEXT:    [[CONV2339:%.*]] = zext i16 [[TMP966]] to i32
31910 // SIMD-ONLY0-NEXT:    [[TMP967:%.*]] = load i16, ptr [[USE]], align 2
31911 // SIMD-ONLY0-NEXT:    [[CONV2340:%.*]] = zext i16 [[TMP967]] to i32
31912 // SIMD-ONLY0-NEXT:    [[CMP2341:%.*]] = icmp sgt i32 [[CONV2339]], [[CONV2340]]
31913 // SIMD-ONLY0-NEXT:    br i1 [[CMP2341]], label [[COND_TRUE2343:%.*]], label [[COND_FALSE2345:%.*]]
31914 // SIMD-ONLY0:       cond.true2343:
31915 // SIMD-ONLY0-NEXT:    [[TMP968:%.*]] = load i16, ptr [[USE]], align 2
31916 // SIMD-ONLY0-NEXT:    [[CONV2344:%.*]] = zext i16 [[TMP968]] to i32
31917 // SIMD-ONLY0-NEXT:    br label [[COND_END2347:%.*]]
31918 // SIMD-ONLY0:       cond.false2345:
31919 // SIMD-ONLY0-NEXT:    [[TMP969:%.*]] = load i16, ptr [[USX]], align 2
31920 // SIMD-ONLY0-NEXT:    [[CONV2346:%.*]] = zext i16 [[TMP969]] to i32
31921 // SIMD-ONLY0-NEXT:    br label [[COND_END2347]]
31922 // SIMD-ONLY0:       cond.end2347:
31923 // SIMD-ONLY0-NEXT:    [[COND2348:%.*]] = phi i32 [ [[CONV2344]], [[COND_TRUE2343]] ], [ [[CONV2346]], [[COND_FALSE2345]] ]
31924 // SIMD-ONLY0-NEXT:    [[CONV2349:%.*]] = trunc i32 [[COND2348]] to i16
31925 // SIMD-ONLY0-NEXT:    store i16 [[CONV2349]], ptr [[USX]], align 2
31926 // SIMD-ONLY0-NEXT:    [[TMP970:%.*]] = load i16, ptr [[USX]], align 2
31927 // SIMD-ONLY0-NEXT:    [[CONV2350:%.*]] = zext i16 [[TMP970]] to i32
31928 // SIMD-ONLY0-NEXT:    [[TMP971:%.*]] = load i16, ptr [[USE]], align 2
31929 // SIMD-ONLY0-NEXT:    [[CONV2351:%.*]] = zext i16 [[TMP971]] to i32
31930 // SIMD-ONLY0-NEXT:    [[CMP2352:%.*]] = icmp slt i32 [[CONV2350]], [[CONV2351]]
31931 // SIMD-ONLY0-NEXT:    br i1 [[CMP2352]], label [[COND_TRUE2354:%.*]], label [[COND_FALSE2356:%.*]]
31932 // SIMD-ONLY0:       cond.true2354:
31933 // SIMD-ONLY0-NEXT:    [[TMP972:%.*]] = load i16, ptr [[USE]], align 2
31934 // SIMD-ONLY0-NEXT:    [[CONV2355:%.*]] = zext i16 [[TMP972]] to i32
31935 // SIMD-ONLY0-NEXT:    br label [[COND_END2358:%.*]]
31936 // SIMD-ONLY0:       cond.false2356:
31937 // SIMD-ONLY0-NEXT:    [[TMP973:%.*]] = load i16, ptr [[USX]], align 2
31938 // SIMD-ONLY0-NEXT:    [[CONV2357:%.*]] = zext i16 [[TMP973]] to i32
31939 // SIMD-ONLY0-NEXT:    br label [[COND_END2358]]
31940 // SIMD-ONLY0:       cond.end2358:
31941 // SIMD-ONLY0-NEXT:    [[COND2359:%.*]] = phi i32 [ [[CONV2355]], [[COND_TRUE2354]] ], [ [[CONV2357]], [[COND_FALSE2356]] ]
31942 // SIMD-ONLY0-NEXT:    [[CONV2360:%.*]] = trunc i32 [[COND2359]] to i16
31943 // SIMD-ONLY0-NEXT:    store i16 [[CONV2360]], ptr [[USX]], align 2
31944 // SIMD-ONLY0-NEXT:    [[TMP974:%.*]] = load i16, ptr [[USE]], align 2
31945 // SIMD-ONLY0-NEXT:    [[CONV2361:%.*]] = zext i16 [[TMP974]] to i32
31946 // SIMD-ONLY0-NEXT:    [[TMP975:%.*]] = load i16, ptr [[USX]], align 2
31947 // SIMD-ONLY0-NEXT:    [[CONV2362:%.*]] = zext i16 [[TMP975]] to i32
31948 // SIMD-ONLY0-NEXT:    [[CMP2363:%.*]] = icmp sgt i32 [[CONV2361]], [[CONV2362]]
31949 // SIMD-ONLY0-NEXT:    br i1 [[CMP2363]], label [[COND_TRUE2365:%.*]], label [[COND_FALSE2367:%.*]]
31950 // SIMD-ONLY0:       cond.true2365:
31951 // SIMD-ONLY0-NEXT:    [[TMP976:%.*]] = load i16, ptr [[USE]], align 2
31952 // SIMD-ONLY0-NEXT:    [[CONV2366:%.*]] = zext i16 [[TMP976]] to i32
31953 // SIMD-ONLY0-NEXT:    br label [[COND_END2369:%.*]]
31954 // SIMD-ONLY0:       cond.false2367:
31955 // SIMD-ONLY0-NEXT:    [[TMP977:%.*]] = load i16, ptr [[USX]], align 2
31956 // SIMD-ONLY0-NEXT:    [[CONV2368:%.*]] = zext i16 [[TMP977]] to i32
31957 // SIMD-ONLY0-NEXT:    br label [[COND_END2369]]
31958 // SIMD-ONLY0:       cond.end2369:
31959 // SIMD-ONLY0-NEXT:    [[COND2370:%.*]] = phi i32 [ [[CONV2366]], [[COND_TRUE2365]] ], [ [[CONV2368]], [[COND_FALSE2367]] ]
31960 // SIMD-ONLY0-NEXT:    [[CONV2371:%.*]] = trunc i32 [[COND2370]] to i16
31961 // SIMD-ONLY0-NEXT:    store i16 [[CONV2371]], ptr [[USX]], align 2
31962 // SIMD-ONLY0-NEXT:    [[TMP978:%.*]] = load i16, ptr [[USE]], align 2
31963 // SIMD-ONLY0-NEXT:    [[CONV2372:%.*]] = zext i16 [[TMP978]] to i32
31964 // SIMD-ONLY0-NEXT:    [[TMP979:%.*]] = load i16, ptr [[USX]], align 2
31965 // SIMD-ONLY0-NEXT:    [[CONV2373:%.*]] = zext i16 [[TMP979]] to i32
31966 // SIMD-ONLY0-NEXT:    [[CMP2374:%.*]] = icmp slt i32 [[CONV2372]], [[CONV2373]]
31967 // SIMD-ONLY0-NEXT:    br i1 [[CMP2374]], label [[COND_TRUE2376:%.*]], label [[COND_FALSE2378:%.*]]
31968 // SIMD-ONLY0:       cond.true2376:
31969 // SIMD-ONLY0-NEXT:    [[TMP980:%.*]] = load i16, ptr [[USE]], align 2
31970 // SIMD-ONLY0-NEXT:    [[CONV2377:%.*]] = zext i16 [[TMP980]] to i32
31971 // SIMD-ONLY0-NEXT:    br label [[COND_END2380:%.*]]
31972 // SIMD-ONLY0:       cond.false2378:
31973 // SIMD-ONLY0-NEXT:    [[TMP981:%.*]] = load i16, ptr [[USX]], align 2
31974 // SIMD-ONLY0-NEXT:    [[CONV2379:%.*]] = zext i16 [[TMP981]] to i32
31975 // SIMD-ONLY0-NEXT:    br label [[COND_END2380]]
31976 // SIMD-ONLY0:       cond.end2380:
31977 // SIMD-ONLY0-NEXT:    [[COND2381:%.*]] = phi i32 [ [[CONV2377]], [[COND_TRUE2376]] ], [ [[CONV2379]], [[COND_FALSE2378]] ]
31978 // SIMD-ONLY0-NEXT:    [[CONV2382:%.*]] = trunc i32 [[COND2381]] to i16
31979 // SIMD-ONLY0-NEXT:    store i16 [[CONV2382]], ptr [[USX]], align 2
31980 // SIMD-ONLY0-NEXT:    [[TMP982:%.*]] = load i16, ptr [[USX]], align 2
31981 // SIMD-ONLY0-NEXT:    [[CONV2383:%.*]] = zext i16 [[TMP982]] to i32
31982 // SIMD-ONLY0-NEXT:    [[TMP983:%.*]] = load i16, ptr [[USE]], align 2
31983 // SIMD-ONLY0-NEXT:    [[CONV2384:%.*]] = zext i16 [[TMP983]] to i32
31984 // SIMD-ONLY0-NEXT:    [[CMP2385:%.*]] = icmp sgt i32 [[CONV2383]], [[CONV2384]]
31985 // SIMD-ONLY0-NEXT:    br i1 [[CMP2385]], label [[IF_THEN2387:%.*]], label [[IF_END2388:%.*]]
31986 // SIMD-ONLY0:       if.then2387:
31987 // SIMD-ONLY0-NEXT:    [[TMP984:%.*]] = load i16, ptr [[USE]], align 2
31988 // SIMD-ONLY0-NEXT:    store i16 [[TMP984]], ptr [[USX]], align 2
31989 // SIMD-ONLY0-NEXT:    br label [[IF_END2388]]
31990 // SIMD-ONLY0:       if.end2388:
31991 // SIMD-ONLY0-NEXT:    [[TMP985:%.*]] = load i16, ptr [[USX]], align 2
31992 // SIMD-ONLY0-NEXT:    [[CONV2389:%.*]] = zext i16 [[TMP985]] to i32
31993 // SIMD-ONLY0-NEXT:    [[TMP986:%.*]] = load i16, ptr [[USE]], align 2
31994 // SIMD-ONLY0-NEXT:    [[CONV2390:%.*]] = zext i16 [[TMP986]] to i32
31995 // SIMD-ONLY0-NEXT:    [[CMP2391:%.*]] = icmp slt i32 [[CONV2389]], [[CONV2390]]
31996 // SIMD-ONLY0-NEXT:    br i1 [[CMP2391]], label [[IF_THEN2393:%.*]], label [[IF_END2394:%.*]]
31997 // SIMD-ONLY0:       if.then2393:
31998 // SIMD-ONLY0-NEXT:    [[TMP987:%.*]] = load i16, ptr [[USE]], align 2
31999 // SIMD-ONLY0-NEXT:    store i16 [[TMP987]], ptr [[USX]], align 2
32000 // SIMD-ONLY0-NEXT:    br label [[IF_END2394]]
32001 // SIMD-ONLY0:       if.end2394:
32002 // SIMD-ONLY0-NEXT:    [[TMP988:%.*]] = load i16, ptr [[USE]], align 2
32003 // SIMD-ONLY0-NEXT:    [[CONV2395:%.*]] = zext i16 [[TMP988]] to i32
32004 // SIMD-ONLY0-NEXT:    [[TMP989:%.*]] = load i16, ptr [[USX]], align 2
32005 // SIMD-ONLY0-NEXT:    [[CONV2396:%.*]] = zext i16 [[TMP989]] to i32
32006 // SIMD-ONLY0-NEXT:    [[CMP2397:%.*]] = icmp sgt i32 [[CONV2395]], [[CONV2396]]
32007 // SIMD-ONLY0-NEXT:    br i1 [[CMP2397]], label [[IF_THEN2399:%.*]], label [[IF_END2400:%.*]]
32008 // SIMD-ONLY0:       if.then2399:
32009 // SIMD-ONLY0-NEXT:    [[TMP990:%.*]] = load i16, ptr [[USE]], align 2
32010 // SIMD-ONLY0-NEXT:    store i16 [[TMP990]], ptr [[USX]], align 2
32011 // SIMD-ONLY0-NEXT:    br label [[IF_END2400]]
32012 // SIMD-ONLY0:       if.end2400:
32013 // SIMD-ONLY0-NEXT:    [[TMP991:%.*]] = load i16, ptr [[USE]], align 2
32014 // SIMD-ONLY0-NEXT:    [[CONV2401:%.*]] = zext i16 [[TMP991]] to i32
32015 // SIMD-ONLY0-NEXT:    [[TMP992:%.*]] = load i16, ptr [[USX]], align 2
32016 // SIMD-ONLY0-NEXT:    [[CONV2402:%.*]] = zext i16 [[TMP992]] to i32
32017 // SIMD-ONLY0-NEXT:    [[CMP2403:%.*]] = icmp slt i32 [[CONV2401]], [[CONV2402]]
32018 // SIMD-ONLY0-NEXT:    br i1 [[CMP2403]], label [[IF_THEN2405:%.*]], label [[IF_END2406:%.*]]
32019 // SIMD-ONLY0:       if.then2405:
32020 // SIMD-ONLY0-NEXT:    [[TMP993:%.*]] = load i16, ptr [[USE]], align 2
32021 // SIMD-ONLY0-NEXT:    store i16 [[TMP993]], ptr [[USX]], align 2
32022 // SIMD-ONLY0-NEXT:    br label [[IF_END2406]]
32023 // SIMD-ONLY0:       if.end2406:
32024 // SIMD-ONLY0-NEXT:    [[TMP994:%.*]] = load i16, ptr [[USX]], align 2
32025 // SIMD-ONLY0-NEXT:    [[CONV2407:%.*]] = zext i16 [[TMP994]] to i32
32026 // SIMD-ONLY0-NEXT:    [[TMP995:%.*]] = load i16, ptr [[USE]], align 2
32027 // SIMD-ONLY0-NEXT:    [[CONV2408:%.*]] = zext i16 [[TMP995]] to i32
32028 // SIMD-ONLY0-NEXT:    [[CMP2409:%.*]] = icmp eq i32 [[CONV2407]], [[CONV2408]]
32029 // SIMD-ONLY0-NEXT:    br i1 [[CMP2409]], label [[COND_TRUE2411:%.*]], label [[COND_FALSE2413:%.*]]
32030 // SIMD-ONLY0:       cond.true2411:
32031 // SIMD-ONLY0-NEXT:    [[TMP996:%.*]] = load i16, ptr [[USD]], align 2
32032 // SIMD-ONLY0-NEXT:    [[CONV2412:%.*]] = zext i16 [[TMP996]] to i32
32033 // SIMD-ONLY0-NEXT:    br label [[COND_END2415:%.*]]
32034 // SIMD-ONLY0:       cond.false2413:
32035 // SIMD-ONLY0-NEXT:    [[TMP997:%.*]] = load i16, ptr [[USX]], align 2
32036 // SIMD-ONLY0-NEXT:    [[CONV2414:%.*]] = zext i16 [[TMP997]] to i32
32037 // SIMD-ONLY0-NEXT:    br label [[COND_END2415]]
32038 // SIMD-ONLY0:       cond.end2415:
32039 // SIMD-ONLY0-NEXT:    [[COND2416:%.*]] = phi i32 [ [[CONV2412]], [[COND_TRUE2411]] ], [ [[CONV2414]], [[COND_FALSE2413]] ]
32040 // SIMD-ONLY0-NEXT:    [[CONV2417:%.*]] = trunc i32 [[COND2416]] to i16
32041 // SIMD-ONLY0-NEXT:    store i16 [[CONV2417]], ptr [[USX]], align 2
32042 // SIMD-ONLY0-NEXT:    [[TMP998:%.*]] = load i16, ptr [[USE]], align 2
32043 // SIMD-ONLY0-NEXT:    [[CONV2418:%.*]] = zext i16 [[TMP998]] to i32
32044 // SIMD-ONLY0-NEXT:    [[TMP999:%.*]] = load i16, ptr [[USX]], align 2
32045 // SIMD-ONLY0-NEXT:    [[CONV2419:%.*]] = zext i16 [[TMP999]] to i32
32046 // SIMD-ONLY0-NEXT:    [[CMP2420:%.*]] = icmp eq i32 [[CONV2418]], [[CONV2419]]
32047 // SIMD-ONLY0-NEXT:    br i1 [[CMP2420]], label [[COND_TRUE2422:%.*]], label [[COND_FALSE2424:%.*]]
32048 // SIMD-ONLY0:       cond.true2422:
32049 // SIMD-ONLY0-NEXT:    [[TMP1000:%.*]] = load i16, ptr [[USD]], align 2
32050 // SIMD-ONLY0-NEXT:    [[CONV2423:%.*]] = zext i16 [[TMP1000]] to i32
32051 // SIMD-ONLY0-NEXT:    br label [[COND_END2426:%.*]]
32052 // SIMD-ONLY0:       cond.false2424:
32053 // SIMD-ONLY0-NEXT:    [[TMP1001:%.*]] = load i16, ptr [[USX]], align 2
32054 // SIMD-ONLY0-NEXT:    [[CONV2425:%.*]] = zext i16 [[TMP1001]] to i32
32055 // SIMD-ONLY0-NEXT:    br label [[COND_END2426]]
32056 // SIMD-ONLY0:       cond.end2426:
32057 // SIMD-ONLY0-NEXT:    [[COND2427:%.*]] = phi i32 [ [[CONV2423]], [[COND_TRUE2422]] ], [ [[CONV2425]], [[COND_FALSE2424]] ]
32058 // SIMD-ONLY0-NEXT:    [[CONV2428:%.*]] = trunc i32 [[COND2427]] to i16
32059 // SIMD-ONLY0-NEXT:    store i16 [[CONV2428]], ptr [[USX]], align 2
32060 // SIMD-ONLY0-NEXT:    [[TMP1002:%.*]] = load i16, ptr [[USX]], align 2
32061 // SIMD-ONLY0-NEXT:    [[CONV2429:%.*]] = zext i16 [[TMP1002]] to i32
32062 // SIMD-ONLY0-NEXT:    [[TMP1003:%.*]] = load i16, ptr [[USE]], align 2
32063 // SIMD-ONLY0-NEXT:    [[CONV2430:%.*]] = zext i16 [[TMP1003]] to i32
32064 // SIMD-ONLY0-NEXT:    [[CMP2431:%.*]] = icmp eq i32 [[CONV2429]], [[CONV2430]]
32065 // SIMD-ONLY0-NEXT:    br i1 [[CMP2431]], label [[IF_THEN2433:%.*]], label [[IF_END2434:%.*]]
32066 // SIMD-ONLY0:       if.then2433:
32067 // SIMD-ONLY0-NEXT:    [[TMP1004:%.*]] = load i16, ptr [[USD]], align 2
32068 // SIMD-ONLY0-NEXT:    store i16 [[TMP1004]], ptr [[USX]], align 2
32069 // SIMD-ONLY0-NEXT:    br label [[IF_END2434]]
32070 // SIMD-ONLY0:       if.end2434:
32071 // SIMD-ONLY0-NEXT:    [[TMP1005:%.*]] = load i16, ptr [[USE]], align 2
32072 // SIMD-ONLY0-NEXT:    [[CONV2435:%.*]] = zext i16 [[TMP1005]] to i32
32073 // SIMD-ONLY0-NEXT:    [[TMP1006:%.*]] = load i16, ptr [[USX]], align 2
32074 // SIMD-ONLY0-NEXT:    [[CONV2436:%.*]] = zext i16 [[TMP1006]] to i32
32075 // SIMD-ONLY0-NEXT:    [[CMP2437:%.*]] = icmp eq i32 [[CONV2435]], [[CONV2436]]
32076 // SIMD-ONLY0-NEXT:    br i1 [[CMP2437]], label [[IF_THEN2439:%.*]], label [[IF_END2440:%.*]]
32077 // SIMD-ONLY0:       if.then2439:
32078 // SIMD-ONLY0-NEXT:    [[TMP1007:%.*]] = load i16, ptr [[USD]], align 2
32079 // SIMD-ONLY0-NEXT:    store i16 [[TMP1007]], ptr [[USX]], align 2
32080 // SIMD-ONLY0-NEXT:    br label [[IF_END2440]]
32081 // SIMD-ONLY0:       if.end2440:
32082 // SIMD-ONLY0-NEXT:    [[TMP1008:%.*]] = load i32, ptr [[IX]], align 4
32083 // SIMD-ONLY0-NEXT:    [[TMP1009:%.*]] = load i32, ptr [[IE]], align 4
32084 // SIMD-ONLY0-NEXT:    [[CMP2441:%.*]] = icmp sgt i32 [[TMP1008]], [[TMP1009]]
32085 // SIMD-ONLY0-NEXT:    br i1 [[CMP2441]], label [[COND_TRUE2443:%.*]], label [[COND_FALSE2444:%.*]]
32086 // SIMD-ONLY0:       cond.true2443:
32087 // SIMD-ONLY0-NEXT:    [[TMP1010:%.*]] = load i32, ptr [[IE]], align 4
32088 // SIMD-ONLY0-NEXT:    br label [[COND_END2445:%.*]]
32089 // SIMD-ONLY0:       cond.false2444:
32090 // SIMD-ONLY0-NEXT:    [[TMP1011:%.*]] = load i32, ptr [[IX]], align 4
32091 // SIMD-ONLY0-NEXT:    br label [[COND_END2445]]
32092 // SIMD-ONLY0:       cond.end2445:
32093 // SIMD-ONLY0-NEXT:    [[COND2446:%.*]] = phi i32 [ [[TMP1010]], [[COND_TRUE2443]] ], [ [[TMP1011]], [[COND_FALSE2444]] ]
32094 // SIMD-ONLY0-NEXT:    store i32 [[COND2446]], ptr [[IX]], align 4
32095 // SIMD-ONLY0-NEXT:    [[TMP1012:%.*]] = load i32, ptr [[IX]], align 4
32096 // SIMD-ONLY0-NEXT:    [[TMP1013:%.*]] = load i32, ptr [[IE]], align 4
32097 // SIMD-ONLY0-NEXT:    [[CMP2447:%.*]] = icmp slt i32 [[TMP1012]], [[TMP1013]]
32098 // SIMD-ONLY0-NEXT:    br i1 [[CMP2447]], label [[COND_TRUE2449:%.*]], label [[COND_FALSE2450:%.*]]
32099 // SIMD-ONLY0:       cond.true2449:
32100 // SIMD-ONLY0-NEXT:    [[TMP1014:%.*]] = load i32, ptr [[IE]], align 4
32101 // SIMD-ONLY0-NEXT:    br label [[COND_END2451:%.*]]
32102 // SIMD-ONLY0:       cond.false2450:
32103 // SIMD-ONLY0-NEXT:    [[TMP1015:%.*]] = load i32, ptr [[IX]], align 4
32104 // SIMD-ONLY0-NEXT:    br label [[COND_END2451]]
32105 // SIMD-ONLY0:       cond.end2451:
32106 // SIMD-ONLY0-NEXT:    [[COND2452:%.*]] = phi i32 [ [[TMP1014]], [[COND_TRUE2449]] ], [ [[TMP1015]], [[COND_FALSE2450]] ]
32107 // SIMD-ONLY0-NEXT:    store i32 [[COND2452]], ptr [[IX]], align 4
32108 // SIMD-ONLY0-NEXT:    [[TMP1016:%.*]] = load i32, ptr [[IE]], align 4
32109 // SIMD-ONLY0-NEXT:    [[TMP1017:%.*]] = load i32, ptr [[IX]], align 4
32110 // SIMD-ONLY0-NEXT:    [[CMP2453:%.*]] = icmp sgt i32 [[TMP1016]], [[TMP1017]]
32111 // SIMD-ONLY0-NEXT:    br i1 [[CMP2453]], label [[COND_TRUE2455:%.*]], label [[COND_FALSE2456:%.*]]
32112 // SIMD-ONLY0:       cond.true2455:
32113 // SIMD-ONLY0-NEXT:    [[TMP1018:%.*]] = load i32, ptr [[IE]], align 4
32114 // SIMD-ONLY0-NEXT:    br label [[COND_END2457:%.*]]
32115 // SIMD-ONLY0:       cond.false2456:
32116 // SIMD-ONLY0-NEXT:    [[TMP1019:%.*]] = load i32, ptr [[IX]], align 4
32117 // SIMD-ONLY0-NEXT:    br label [[COND_END2457]]
32118 // SIMD-ONLY0:       cond.end2457:
32119 // SIMD-ONLY0-NEXT:    [[COND2458:%.*]] = phi i32 [ [[TMP1018]], [[COND_TRUE2455]] ], [ [[TMP1019]], [[COND_FALSE2456]] ]
32120 // SIMD-ONLY0-NEXT:    store i32 [[COND2458]], ptr [[IX]], align 4
32121 // SIMD-ONLY0-NEXT:    [[TMP1020:%.*]] = load i32, ptr [[IE]], align 4
32122 // SIMD-ONLY0-NEXT:    [[TMP1021:%.*]] = load i32, ptr [[IX]], align 4
32123 // SIMD-ONLY0-NEXT:    [[CMP2459:%.*]] = icmp slt i32 [[TMP1020]], [[TMP1021]]
32124 // SIMD-ONLY0-NEXT:    br i1 [[CMP2459]], label [[COND_TRUE2461:%.*]], label [[COND_FALSE2462:%.*]]
32125 // SIMD-ONLY0:       cond.true2461:
32126 // SIMD-ONLY0-NEXT:    [[TMP1022:%.*]] = load i32, ptr [[IE]], align 4
32127 // SIMD-ONLY0-NEXT:    br label [[COND_END2463:%.*]]
32128 // SIMD-ONLY0:       cond.false2462:
32129 // SIMD-ONLY0-NEXT:    [[TMP1023:%.*]] = load i32, ptr [[IX]], align 4
32130 // SIMD-ONLY0-NEXT:    br label [[COND_END2463]]
32131 // SIMD-ONLY0:       cond.end2463:
32132 // SIMD-ONLY0-NEXT:    [[COND2464:%.*]] = phi i32 [ [[TMP1022]], [[COND_TRUE2461]] ], [ [[TMP1023]], [[COND_FALSE2462]] ]
32133 // SIMD-ONLY0-NEXT:    store i32 [[COND2464]], ptr [[IX]], align 4
32134 // SIMD-ONLY0-NEXT:    [[TMP1024:%.*]] = load i32, ptr [[IX]], align 4
32135 // SIMD-ONLY0-NEXT:    [[TMP1025:%.*]] = load i32, ptr [[IE]], align 4
32136 // SIMD-ONLY0-NEXT:    [[CMP2465:%.*]] = icmp sgt i32 [[TMP1024]], [[TMP1025]]
32137 // SIMD-ONLY0-NEXT:    br i1 [[CMP2465]], label [[IF_THEN2467:%.*]], label [[IF_END2468:%.*]]
32138 // SIMD-ONLY0:       if.then2467:
32139 // SIMD-ONLY0-NEXT:    [[TMP1026:%.*]] = load i32, ptr [[IE]], align 4
32140 // SIMD-ONLY0-NEXT:    store i32 [[TMP1026]], ptr [[IX]], align 4
32141 // SIMD-ONLY0-NEXT:    br label [[IF_END2468]]
32142 // SIMD-ONLY0:       if.end2468:
32143 // SIMD-ONLY0-NEXT:    [[TMP1027:%.*]] = load i32, ptr [[IX]], align 4
32144 // SIMD-ONLY0-NEXT:    [[TMP1028:%.*]] = load i32, ptr [[IE]], align 4
32145 // SIMD-ONLY0-NEXT:    [[CMP2469:%.*]] = icmp slt i32 [[TMP1027]], [[TMP1028]]
32146 // SIMD-ONLY0-NEXT:    br i1 [[CMP2469]], label [[IF_THEN2471:%.*]], label [[IF_END2472:%.*]]
32147 // SIMD-ONLY0:       if.then2471:
32148 // SIMD-ONLY0-NEXT:    [[TMP1029:%.*]] = load i32, ptr [[IE]], align 4
32149 // SIMD-ONLY0-NEXT:    store i32 [[TMP1029]], ptr [[IX]], align 4
32150 // SIMD-ONLY0-NEXT:    br label [[IF_END2472]]
32151 // SIMD-ONLY0:       if.end2472:
32152 // SIMD-ONLY0-NEXT:    [[TMP1030:%.*]] = load i32, ptr [[IE]], align 4
32153 // SIMD-ONLY0-NEXT:    [[TMP1031:%.*]] = load i32, ptr [[IX]], align 4
32154 // SIMD-ONLY0-NEXT:    [[CMP2473:%.*]] = icmp sgt i32 [[TMP1030]], [[TMP1031]]
32155 // SIMD-ONLY0-NEXT:    br i1 [[CMP2473]], label [[IF_THEN2475:%.*]], label [[IF_END2476:%.*]]
32156 // SIMD-ONLY0:       if.then2475:
32157 // SIMD-ONLY0-NEXT:    [[TMP1032:%.*]] = load i32, ptr [[IE]], align 4
32158 // SIMD-ONLY0-NEXT:    store i32 [[TMP1032]], ptr [[IX]], align 4
32159 // SIMD-ONLY0-NEXT:    br label [[IF_END2476]]
32160 // SIMD-ONLY0:       if.end2476:
32161 // SIMD-ONLY0-NEXT:    [[TMP1033:%.*]] = load i32, ptr [[IE]], align 4
32162 // SIMD-ONLY0-NEXT:    [[TMP1034:%.*]] = load i32, ptr [[IX]], align 4
32163 // SIMD-ONLY0-NEXT:    [[CMP2477:%.*]] = icmp slt i32 [[TMP1033]], [[TMP1034]]
32164 // SIMD-ONLY0-NEXT:    br i1 [[CMP2477]], label [[IF_THEN2479:%.*]], label [[IF_END2480:%.*]]
32165 // SIMD-ONLY0:       if.then2479:
32166 // SIMD-ONLY0-NEXT:    [[TMP1035:%.*]] = load i32, ptr [[IE]], align 4
32167 // SIMD-ONLY0-NEXT:    store i32 [[TMP1035]], ptr [[IX]], align 4
32168 // SIMD-ONLY0-NEXT:    br label [[IF_END2480]]
32169 // SIMD-ONLY0:       if.end2480:
32170 // SIMD-ONLY0-NEXT:    [[TMP1036:%.*]] = load i32, ptr [[IX]], align 4
32171 // SIMD-ONLY0-NEXT:    [[TMP1037:%.*]] = load i32, ptr [[IE]], align 4
32172 // SIMD-ONLY0-NEXT:    [[CMP2481:%.*]] = icmp eq i32 [[TMP1036]], [[TMP1037]]
32173 // SIMD-ONLY0-NEXT:    br i1 [[CMP2481]], label [[COND_TRUE2483:%.*]], label [[COND_FALSE2484:%.*]]
32174 // SIMD-ONLY0:       cond.true2483:
32175 // SIMD-ONLY0-NEXT:    [[TMP1038:%.*]] = load i32, ptr [[ID]], align 4
32176 // SIMD-ONLY0-NEXT:    br label [[COND_END2485:%.*]]
32177 // SIMD-ONLY0:       cond.false2484:
32178 // SIMD-ONLY0-NEXT:    [[TMP1039:%.*]] = load i32, ptr [[IX]], align 4
32179 // SIMD-ONLY0-NEXT:    br label [[COND_END2485]]
32180 // SIMD-ONLY0:       cond.end2485:
32181 // SIMD-ONLY0-NEXT:    [[COND2486:%.*]] = phi i32 [ [[TMP1038]], [[COND_TRUE2483]] ], [ [[TMP1039]], [[COND_FALSE2484]] ]
32182 // SIMD-ONLY0-NEXT:    store i32 [[COND2486]], ptr [[IX]], align 4
32183 // SIMD-ONLY0-NEXT:    [[TMP1040:%.*]] = load i32, ptr [[IE]], align 4
32184 // SIMD-ONLY0-NEXT:    [[TMP1041:%.*]] = load i32, ptr [[IX]], align 4
32185 // SIMD-ONLY0-NEXT:    [[CMP2487:%.*]] = icmp eq i32 [[TMP1040]], [[TMP1041]]
32186 // SIMD-ONLY0-NEXT:    br i1 [[CMP2487]], label [[COND_TRUE2489:%.*]], label [[COND_FALSE2490:%.*]]
32187 // SIMD-ONLY0:       cond.true2489:
32188 // SIMD-ONLY0-NEXT:    [[TMP1042:%.*]] = load i32, ptr [[ID]], align 4
32189 // SIMD-ONLY0-NEXT:    br label [[COND_END2491:%.*]]
32190 // SIMD-ONLY0:       cond.false2490:
32191 // SIMD-ONLY0-NEXT:    [[TMP1043:%.*]] = load i32, ptr [[IX]], align 4
32192 // SIMD-ONLY0-NEXT:    br label [[COND_END2491]]
32193 // SIMD-ONLY0:       cond.end2491:
32194 // SIMD-ONLY0-NEXT:    [[COND2492:%.*]] = phi i32 [ [[TMP1042]], [[COND_TRUE2489]] ], [ [[TMP1043]], [[COND_FALSE2490]] ]
32195 // SIMD-ONLY0-NEXT:    store i32 [[COND2492]], ptr [[IX]], align 4
32196 // SIMD-ONLY0-NEXT:    [[TMP1044:%.*]] = load i32, ptr [[IX]], align 4
32197 // SIMD-ONLY0-NEXT:    [[TMP1045:%.*]] = load i32, ptr [[IE]], align 4
32198 // SIMD-ONLY0-NEXT:    [[CMP2493:%.*]] = icmp eq i32 [[TMP1044]], [[TMP1045]]
32199 // SIMD-ONLY0-NEXT:    br i1 [[CMP2493]], label [[IF_THEN2495:%.*]], label [[IF_END2496:%.*]]
32200 // SIMD-ONLY0:       if.then2495:
32201 // SIMD-ONLY0-NEXT:    [[TMP1046:%.*]] = load i32, ptr [[ID]], align 4
32202 // SIMD-ONLY0-NEXT:    store i32 [[TMP1046]], ptr [[IX]], align 4
32203 // SIMD-ONLY0-NEXT:    br label [[IF_END2496]]
32204 // SIMD-ONLY0:       if.end2496:
32205 // SIMD-ONLY0-NEXT:    [[TMP1047:%.*]] = load i32, ptr [[IE]], align 4
32206 // SIMD-ONLY0-NEXT:    [[TMP1048:%.*]] = load i32, ptr [[IX]], align 4
32207 // SIMD-ONLY0-NEXT:    [[CMP2497:%.*]] = icmp eq i32 [[TMP1047]], [[TMP1048]]
32208 // SIMD-ONLY0-NEXT:    br i1 [[CMP2497]], label [[IF_THEN2499:%.*]], label [[IF_END2500:%.*]]
32209 // SIMD-ONLY0:       if.then2499:
32210 // SIMD-ONLY0-NEXT:    [[TMP1049:%.*]] = load i32, ptr [[ID]], align 4
32211 // SIMD-ONLY0-NEXT:    store i32 [[TMP1049]], ptr [[IX]], align 4
32212 // SIMD-ONLY0-NEXT:    br label [[IF_END2500]]
32213 // SIMD-ONLY0:       if.end2500:
32214 // SIMD-ONLY0-NEXT:    [[TMP1050:%.*]] = load i32, ptr [[UIX]], align 4
32215 // SIMD-ONLY0-NEXT:    [[TMP1051:%.*]] = load i32, ptr [[UIE]], align 4
32216 // SIMD-ONLY0-NEXT:    [[CMP2501:%.*]] = icmp ugt i32 [[TMP1050]], [[TMP1051]]
32217 // SIMD-ONLY0-NEXT:    br i1 [[CMP2501]], label [[COND_TRUE2503:%.*]], label [[COND_FALSE2504:%.*]]
32218 // SIMD-ONLY0:       cond.true2503:
32219 // SIMD-ONLY0-NEXT:    [[TMP1052:%.*]] = load i32, ptr [[UIE]], align 4
32220 // SIMD-ONLY0-NEXT:    br label [[COND_END2505:%.*]]
32221 // SIMD-ONLY0:       cond.false2504:
32222 // SIMD-ONLY0-NEXT:    [[TMP1053:%.*]] = load i32, ptr [[UIX]], align 4
32223 // SIMD-ONLY0-NEXT:    br label [[COND_END2505]]
32224 // SIMD-ONLY0:       cond.end2505:
32225 // SIMD-ONLY0-NEXT:    [[COND2506:%.*]] = phi i32 [ [[TMP1052]], [[COND_TRUE2503]] ], [ [[TMP1053]], [[COND_FALSE2504]] ]
32226 // SIMD-ONLY0-NEXT:    store i32 [[COND2506]], ptr [[UIX]], align 4
32227 // SIMD-ONLY0-NEXT:    [[TMP1054:%.*]] = load i32, ptr [[UIX]], align 4
32228 // SIMD-ONLY0-NEXT:    [[TMP1055:%.*]] = load i32, ptr [[UIE]], align 4
32229 // SIMD-ONLY0-NEXT:    [[CMP2507:%.*]] = icmp ult i32 [[TMP1054]], [[TMP1055]]
32230 // SIMD-ONLY0-NEXT:    br i1 [[CMP2507]], label [[COND_TRUE2509:%.*]], label [[COND_FALSE2510:%.*]]
32231 // SIMD-ONLY0:       cond.true2509:
32232 // SIMD-ONLY0-NEXT:    [[TMP1056:%.*]] = load i32, ptr [[UIE]], align 4
32233 // SIMD-ONLY0-NEXT:    br label [[COND_END2511:%.*]]
32234 // SIMD-ONLY0:       cond.false2510:
32235 // SIMD-ONLY0-NEXT:    [[TMP1057:%.*]] = load i32, ptr [[UIX]], align 4
32236 // SIMD-ONLY0-NEXT:    br label [[COND_END2511]]
32237 // SIMD-ONLY0:       cond.end2511:
32238 // SIMD-ONLY0-NEXT:    [[COND2512:%.*]] = phi i32 [ [[TMP1056]], [[COND_TRUE2509]] ], [ [[TMP1057]], [[COND_FALSE2510]] ]
32239 // SIMD-ONLY0-NEXT:    store i32 [[COND2512]], ptr [[UIX]], align 4
32240 // SIMD-ONLY0-NEXT:    [[TMP1058:%.*]] = load i32, ptr [[UIE]], align 4
32241 // SIMD-ONLY0-NEXT:    [[TMP1059:%.*]] = load i32, ptr [[UIX]], align 4
32242 // SIMD-ONLY0-NEXT:    [[CMP2513:%.*]] = icmp ugt i32 [[TMP1058]], [[TMP1059]]
32243 // SIMD-ONLY0-NEXT:    br i1 [[CMP2513]], label [[COND_TRUE2515:%.*]], label [[COND_FALSE2516:%.*]]
32244 // SIMD-ONLY0:       cond.true2515:
32245 // SIMD-ONLY0-NEXT:    [[TMP1060:%.*]] = load i32, ptr [[UIE]], align 4
32246 // SIMD-ONLY0-NEXT:    br label [[COND_END2517:%.*]]
32247 // SIMD-ONLY0:       cond.false2516:
32248 // SIMD-ONLY0-NEXT:    [[TMP1061:%.*]] = load i32, ptr [[UIX]], align 4
32249 // SIMD-ONLY0-NEXT:    br label [[COND_END2517]]
32250 // SIMD-ONLY0:       cond.end2517:
32251 // SIMD-ONLY0-NEXT:    [[COND2518:%.*]] = phi i32 [ [[TMP1060]], [[COND_TRUE2515]] ], [ [[TMP1061]], [[COND_FALSE2516]] ]
32252 // SIMD-ONLY0-NEXT:    store i32 [[COND2518]], ptr [[UIX]], align 4
32253 // SIMD-ONLY0-NEXT:    [[TMP1062:%.*]] = load i32, ptr [[UIE]], align 4
32254 // SIMD-ONLY0-NEXT:    [[TMP1063:%.*]] = load i32, ptr [[UIX]], align 4
32255 // SIMD-ONLY0-NEXT:    [[CMP2519:%.*]] = icmp ult i32 [[TMP1062]], [[TMP1063]]
32256 // SIMD-ONLY0-NEXT:    br i1 [[CMP2519]], label [[COND_TRUE2521:%.*]], label [[COND_FALSE2522:%.*]]
32257 // SIMD-ONLY0:       cond.true2521:
32258 // SIMD-ONLY0-NEXT:    [[TMP1064:%.*]] = load i32, ptr [[UIE]], align 4
32259 // SIMD-ONLY0-NEXT:    br label [[COND_END2523:%.*]]
32260 // SIMD-ONLY0:       cond.false2522:
32261 // SIMD-ONLY0-NEXT:    [[TMP1065:%.*]] = load i32, ptr [[UIX]], align 4
32262 // SIMD-ONLY0-NEXT:    br label [[COND_END2523]]
32263 // SIMD-ONLY0:       cond.end2523:
32264 // SIMD-ONLY0-NEXT:    [[COND2524:%.*]] = phi i32 [ [[TMP1064]], [[COND_TRUE2521]] ], [ [[TMP1065]], [[COND_FALSE2522]] ]
32265 // SIMD-ONLY0-NEXT:    store i32 [[COND2524]], ptr [[UIX]], align 4
32266 // SIMD-ONLY0-NEXT:    [[TMP1066:%.*]] = load i32, ptr [[UIX]], align 4
32267 // SIMD-ONLY0-NEXT:    [[TMP1067:%.*]] = load i32, ptr [[UIE]], align 4
32268 // SIMD-ONLY0-NEXT:    [[CMP2525:%.*]] = icmp ugt i32 [[TMP1066]], [[TMP1067]]
32269 // SIMD-ONLY0-NEXT:    br i1 [[CMP2525]], label [[IF_THEN2527:%.*]], label [[IF_END2528:%.*]]
32270 // SIMD-ONLY0:       if.then2527:
32271 // SIMD-ONLY0-NEXT:    [[TMP1068:%.*]] = load i32, ptr [[UIE]], align 4
32272 // SIMD-ONLY0-NEXT:    store i32 [[TMP1068]], ptr [[UIX]], align 4
32273 // SIMD-ONLY0-NEXT:    br label [[IF_END2528]]
32274 // SIMD-ONLY0:       if.end2528:
32275 // SIMD-ONLY0-NEXT:    [[TMP1069:%.*]] = load i32, ptr [[UIX]], align 4
32276 // SIMD-ONLY0-NEXT:    [[TMP1070:%.*]] = load i32, ptr [[UIE]], align 4
32277 // SIMD-ONLY0-NEXT:    [[CMP2529:%.*]] = icmp ult i32 [[TMP1069]], [[TMP1070]]
32278 // SIMD-ONLY0-NEXT:    br i1 [[CMP2529]], label [[IF_THEN2531:%.*]], label [[IF_END2532:%.*]]
32279 // SIMD-ONLY0:       if.then2531:
32280 // SIMD-ONLY0-NEXT:    [[TMP1071:%.*]] = load i32, ptr [[UIE]], align 4
32281 // SIMD-ONLY0-NEXT:    store i32 [[TMP1071]], ptr [[UIX]], align 4
32282 // SIMD-ONLY0-NEXT:    br label [[IF_END2532]]
32283 // SIMD-ONLY0:       if.end2532:
32284 // SIMD-ONLY0-NEXT:    [[TMP1072:%.*]] = load i32, ptr [[UIE]], align 4
32285 // SIMD-ONLY0-NEXT:    [[TMP1073:%.*]] = load i32, ptr [[UIX]], align 4
32286 // SIMD-ONLY0-NEXT:    [[CMP2533:%.*]] = icmp ugt i32 [[TMP1072]], [[TMP1073]]
32287 // SIMD-ONLY0-NEXT:    br i1 [[CMP2533]], label [[IF_THEN2535:%.*]], label [[IF_END2536:%.*]]
32288 // SIMD-ONLY0:       if.then2535:
32289 // SIMD-ONLY0-NEXT:    [[TMP1074:%.*]] = load i32, ptr [[UIE]], align 4
32290 // SIMD-ONLY0-NEXT:    store i32 [[TMP1074]], ptr [[UIX]], align 4
32291 // SIMD-ONLY0-NEXT:    br label [[IF_END2536]]
32292 // SIMD-ONLY0:       if.end2536:
32293 // SIMD-ONLY0-NEXT:    [[TMP1075:%.*]] = load i32, ptr [[UIE]], align 4
32294 // SIMD-ONLY0-NEXT:    [[TMP1076:%.*]] = load i32, ptr [[UIX]], align 4
32295 // SIMD-ONLY0-NEXT:    [[CMP2537:%.*]] = icmp ult i32 [[TMP1075]], [[TMP1076]]
32296 // SIMD-ONLY0-NEXT:    br i1 [[CMP2537]], label [[IF_THEN2539:%.*]], label [[IF_END2540:%.*]]
32297 // SIMD-ONLY0:       if.then2539:
32298 // SIMD-ONLY0-NEXT:    [[TMP1077:%.*]] = load i32, ptr [[UIE]], align 4
32299 // SIMD-ONLY0-NEXT:    store i32 [[TMP1077]], ptr [[UIX]], align 4
32300 // SIMD-ONLY0-NEXT:    br label [[IF_END2540]]
32301 // SIMD-ONLY0:       if.end2540:
32302 // SIMD-ONLY0-NEXT:    [[TMP1078:%.*]] = load i32, ptr [[UIX]], align 4
32303 // SIMD-ONLY0-NEXT:    [[TMP1079:%.*]] = load i32, ptr [[UIE]], align 4
32304 // SIMD-ONLY0-NEXT:    [[CMP2541:%.*]] = icmp eq i32 [[TMP1078]], [[TMP1079]]
32305 // SIMD-ONLY0-NEXT:    br i1 [[CMP2541]], label [[COND_TRUE2543:%.*]], label [[COND_FALSE2544:%.*]]
32306 // SIMD-ONLY0:       cond.true2543:
32307 // SIMD-ONLY0-NEXT:    [[TMP1080:%.*]] = load i32, ptr [[UID]], align 4
32308 // SIMD-ONLY0-NEXT:    br label [[COND_END2545:%.*]]
32309 // SIMD-ONLY0:       cond.false2544:
32310 // SIMD-ONLY0-NEXT:    [[TMP1081:%.*]] = load i32, ptr [[UIX]], align 4
32311 // SIMD-ONLY0-NEXT:    br label [[COND_END2545]]
32312 // SIMD-ONLY0:       cond.end2545:
32313 // SIMD-ONLY0-NEXT:    [[COND2546:%.*]] = phi i32 [ [[TMP1080]], [[COND_TRUE2543]] ], [ [[TMP1081]], [[COND_FALSE2544]] ]
32314 // SIMD-ONLY0-NEXT:    store i32 [[COND2546]], ptr [[UIX]], align 4
32315 // SIMD-ONLY0-NEXT:    [[TMP1082:%.*]] = load i32, ptr [[UIE]], align 4
32316 // SIMD-ONLY0-NEXT:    [[TMP1083:%.*]] = load i32, ptr [[UIX]], align 4
32317 // SIMD-ONLY0-NEXT:    [[CMP2547:%.*]] = icmp eq i32 [[TMP1082]], [[TMP1083]]
32318 // SIMD-ONLY0-NEXT:    br i1 [[CMP2547]], label [[COND_TRUE2549:%.*]], label [[COND_FALSE2550:%.*]]
32319 // SIMD-ONLY0:       cond.true2549:
32320 // SIMD-ONLY0-NEXT:    [[TMP1084:%.*]] = load i32, ptr [[UID]], align 4
32321 // SIMD-ONLY0-NEXT:    br label [[COND_END2551:%.*]]
32322 // SIMD-ONLY0:       cond.false2550:
32323 // SIMD-ONLY0-NEXT:    [[TMP1085:%.*]] = load i32, ptr [[UIX]], align 4
32324 // SIMD-ONLY0-NEXT:    br label [[COND_END2551]]
32325 // SIMD-ONLY0:       cond.end2551:
32326 // SIMD-ONLY0-NEXT:    [[COND2552:%.*]] = phi i32 [ [[TMP1084]], [[COND_TRUE2549]] ], [ [[TMP1085]], [[COND_FALSE2550]] ]
32327 // SIMD-ONLY0-NEXT:    store i32 [[COND2552]], ptr [[UIX]], align 4
32328 // SIMD-ONLY0-NEXT:    [[TMP1086:%.*]] = load i32, ptr [[UIX]], align 4
32329 // SIMD-ONLY0-NEXT:    [[TMP1087:%.*]] = load i32, ptr [[UIE]], align 4
32330 // SIMD-ONLY0-NEXT:    [[CMP2553:%.*]] = icmp eq i32 [[TMP1086]], [[TMP1087]]
32331 // SIMD-ONLY0-NEXT:    br i1 [[CMP2553]], label [[IF_THEN2555:%.*]], label [[IF_END2556:%.*]]
32332 // SIMD-ONLY0:       if.then2555:
32333 // SIMD-ONLY0-NEXT:    [[TMP1088:%.*]] = load i32, ptr [[UID]], align 4
32334 // SIMD-ONLY0-NEXT:    store i32 [[TMP1088]], ptr [[UIX]], align 4
32335 // SIMD-ONLY0-NEXT:    br label [[IF_END2556]]
32336 // SIMD-ONLY0:       if.end2556:
32337 // SIMD-ONLY0-NEXT:    [[TMP1089:%.*]] = load i32, ptr [[UIE]], align 4
32338 // SIMD-ONLY0-NEXT:    [[TMP1090:%.*]] = load i32, ptr [[UIX]], align 4
32339 // SIMD-ONLY0-NEXT:    [[CMP2557:%.*]] = icmp eq i32 [[TMP1089]], [[TMP1090]]
32340 // SIMD-ONLY0-NEXT:    br i1 [[CMP2557]], label [[IF_THEN2559:%.*]], label [[IF_END2560:%.*]]
32341 // SIMD-ONLY0:       if.then2559:
32342 // SIMD-ONLY0-NEXT:    [[TMP1091:%.*]] = load i32, ptr [[UID]], align 4
32343 // SIMD-ONLY0-NEXT:    store i32 [[TMP1091]], ptr [[UIX]], align 4
32344 // SIMD-ONLY0-NEXT:    br label [[IF_END2560]]
32345 // SIMD-ONLY0:       if.end2560:
32346 // SIMD-ONLY0-NEXT:    [[TMP1092:%.*]] = load i32, ptr [[IX]], align 4
32347 // SIMD-ONLY0-NEXT:    [[TMP1093:%.*]] = load i32, ptr [[IE]], align 4
32348 // SIMD-ONLY0-NEXT:    [[CMP2561:%.*]] = icmp sgt i32 [[TMP1092]], [[TMP1093]]
32349 // SIMD-ONLY0-NEXT:    br i1 [[CMP2561]], label [[COND_TRUE2563:%.*]], label [[COND_FALSE2564:%.*]]
32350 // SIMD-ONLY0:       cond.true2563:
32351 // SIMD-ONLY0-NEXT:    [[TMP1094:%.*]] = load i32, ptr [[IE]], align 4
32352 // SIMD-ONLY0-NEXT:    br label [[COND_END2565:%.*]]
32353 // SIMD-ONLY0:       cond.false2564:
32354 // SIMD-ONLY0-NEXT:    [[TMP1095:%.*]] = load i32, ptr [[IX]], align 4
32355 // SIMD-ONLY0-NEXT:    br label [[COND_END2565]]
32356 // SIMD-ONLY0:       cond.end2565:
32357 // SIMD-ONLY0-NEXT:    [[COND2566:%.*]] = phi i32 [ [[TMP1094]], [[COND_TRUE2563]] ], [ [[TMP1095]], [[COND_FALSE2564]] ]
32358 // SIMD-ONLY0-NEXT:    store i32 [[COND2566]], ptr [[IX]], align 4
32359 // SIMD-ONLY0-NEXT:    [[TMP1096:%.*]] = load i32, ptr [[IX]], align 4
32360 // SIMD-ONLY0-NEXT:    [[TMP1097:%.*]] = load i32, ptr [[IE]], align 4
32361 // SIMD-ONLY0-NEXT:    [[CMP2567:%.*]] = icmp slt i32 [[TMP1096]], [[TMP1097]]
32362 // SIMD-ONLY0-NEXT:    br i1 [[CMP2567]], label [[COND_TRUE2569:%.*]], label [[COND_FALSE2570:%.*]]
32363 // SIMD-ONLY0:       cond.true2569:
32364 // SIMD-ONLY0-NEXT:    [[TMP1098:%.*]] = load i32, ptr [[IE]], align 4
32365 // SIMD-ONLY0-NEXT:    br label [[COND_END2571:%.*]]
32366 // SIMD-ONLY0:       cond.false2570:
32367 // SIMD-ONLY0-NEXT:    [[TMP1099:%.*]] = load i32, ptr [[IX]], align 4
32368 // SIMD-ONLY0-NEXT:    br label [[COND_END2571]]
32369 // SIMD-ONLY0:       cond.end2571:
32370 // SIMD-ONLY0-NEXT:    [[COND2572:%.*]] = phi i32 [ [[TMP1098]], [[COND_TRUE2569]] ], [ [[TMP1099]], [[COND_FALSE2570]] ]
32371 // SIMD-ONLY0-NEXT:    store i32 [[COND2572]], ptr [[IX]], align 4
32372 // SIMD-ONLY0-NEXT:    [[TMP1100:%.*]] = load i32, ptr [[IE]], align 4
32373 // SIMD-ONLY0-NEXT:    [[TMP1101:%.*]] = load i32, ptr [[IX]], align 4
32374 // SIMD-ONLY0-NEXT:    [[CMP2573:%.*]] = icmp sgt i32 [[TMP1100]], [[TMP1101]]
32375 // SIMD-ONLY0-NEXT:    br i1 [[CMP2573]], label [[COND_TRUE2575:%.*]], label [[COND_FALSE2576:%.*]]
32376 // SIMD-ONLY0:       cond.true2575:
32377 // SIMD-ONLY0-NEXT:    [[TMP1102:%.*]] = load i32, ptr [[IE]], align 4
32378 // SIMD-ONLY0-NEXT:    br label [[COND_END2577:%.*]]
32379 // SIMD-ONLY0:       cond.false2576:
32380 // SIMD-ONLY0-NEXT:    [[TMP1103:%.*]] = load i32, ptr [[IX]], align 4
32381 // SIMD-ONLY0-NEXT:    br label [[COND_END2577]]
32382 // SIMD-ONLY0:       cond.end2577:
32383 // SIMD-ONLY0-NEXT:    [[COND2578:%.*]] = phi i32 [ [[TMP1102]], [[COND_TRUE2575]] ], [ [[TMP1103]], [[COND_FALSE2576]] ]
32384 // SIMD-ONLY0-NEXT:    store i32 [[COND2578]], ptr [[IX]], align 4
32385 // SIMD-ONLY0-NEXT:    [[TMP1104:%.*]] = load i32, ptr [[IE]], align 4
32386 // SIMD-ONLY0-NEXT:    [[TMP1105:%.*]] = load i32, ptr [[IX]], align 4
32387 // SIMD-ONLY0-NEXT:    [[CMP2579:%.*]] = icmp slt i32 [[TMP1104]], [[TMP1105]]
32388 // SIMD-ONLY0-NEXT:    br i1 [[CMP2579]], label [[COND_TRUE2581:%.*]], label [[COND_FALSE2582:%.*]]
32389 // SIMD-ONLY0:       cond.true2581:
32390 // SIMD-ONLY0-NEXT:    [[TMP1106:%.*]] = load i32, ptr [[IE]], align 4
32391 // SIMD-ONLY0-NEXT:    br label [[COND_END2583:%.*]]
32392 // SIMD-ONLY0:       cond.false2582:
32393 // SIMD-ONLY0-NEXT:    [[TMP1107:%.*]] = load i32, ptr [[IX]], align 4
32394 // SIMD-ONLY0-NEXT:    br label [[COND_END2583]]
32395 // SIMD-ONLY0:       cond.end2583:
32396 // SIMD-ONLY0-NEXT:    [[COND2584:%.*]] = phi i32 [ [[TMP1106]], [[COND_TRUE2581]] ], [ [[TMP1107]], [[COND_FALSE2582]] ]
32397 // SIMD-ONLY0-NEXT:    store i32 [[COND2584]], ptr [[IX]], align 4
32398 // SIMD-ONLY0-NEXT:    [[TMP1108:%.*]] = load i32, ptr [[IX]], align 4
32399 // SIMD-ONLY0-NEXT:    [[TMP1109:%.*]] = load i32, ptr [[IE]], align 4
32400 // SIMD-ONLY0-NEXT:    [[CMP2585:%.*]] = icmp sgt i32 [[TMP1108]], [[TMP1109]]
32401 // SIMD-ONLY0-NEXT:    br i1 [[CMP2585]], label [[IF_THEN2587:%.*]], label [[IF_END2588:%.*]]
32402 // SIMD-ONLY0:       if.then2587:
32403 // SIMD-ONLY0-NEXT:    [[TMP1110:%.*]] = load i32, ptr [[IE]], align 4
32404 // SIMD-ONLY0-NEXT:    store i32 [[TMP1110]], ptr [[IX]], align 4
32405 // SIMD-ONLY0-NEXT:    br label [[IF_END2588]]
32406 // SIMD-ONLY0:       if.end2588:
32407 // SIMD-ONLY0-NEXT:    [[TMP1111:%.*]] = load i32, ptr [[IX]], align 4
32408 // SIMD-ONLY0-NEXT:    [[TMP1112:%.*]] = load i32, ptr [[IE]], align 4
32409 // SIMD-ONLY0-NEXT:    [[CMP2589:%.*]] = icmp slt i32 [[TMP1111]], [[TMP1112]]
32410 // SIMD-ONLY0-NEXT:    br i1 [[CMP2589]], label [[IF_THEN2591:%.*]], label [[IF_END2592:%.*]]
32411 // SIMD-ONLY0:       if.then2591:
32412 // SIMD-ONLY0-NEXT:    [[TMP1113:%.*]] = load i32, ptr [[IE]], align 4
32413 // SIMD-ONLY0-NEXT:    store i32 [[TMP1113]], ptr [[IX]], align 4
32414 // SIMD-ONLY0-NEXT:    br label [[IF_END2592]]
32415 // SIMD-ONLY0:       if.end2592:
32416 // SIMD-ONLY0-NEXT:    [[TMP1114:%.*]] = load i32, ptr [[IE]], align 4
32417 // SIMD-ONLY0-NEXT:    [[TMP1115:%.*]] = load i32, ptr [[IX]], align 4
32418 // SIMD-ONLY0-NEXT:    [[CMP2593:%.*]] = icmp sgt i32 [[TMP1114]], [[TMP1115]]
32419 // SIMD-ONLY0-NEXT:    br i1 [[CMP2593]], label [[IF_THEN2595:%.*]], label [[IF_END2596:%.*]]
32420 // SIMD-ONLY0:       if.then2595:
32421 // SIMD-ONLY0-NEXT:    [[TMP1116:%.*]] = load i32, ptr [[IE]], align 4
32422 // SIMD-ONLY0-NEXT:    store i32 [[TMP1116]], ptr [[IX]], align 4
32423 // SIMD-ONLY0-NEXT:    br label [[IF_END2596]]
32424 // SIMD-ONLY0:       if.end2596:
32425 // SIMD-ONLY0-NEXT:    [[TMP1117:%.*]] = load i32, ptr [[IE]], align 4
32426 // SIMD-ONLY0-NEXT:    [[TMP1118:%.*]] = load i32, ptr [[IX]], align 4
32427 // SIMD-ONLY0-NEXT:    [[CMP2597:%.*]] = icmp slt i32 [[TMP1117]], [[TMP1118]]
32428 // SIMD-ONLY0-NEXT:    br i1 [[CMP2597]], label [[IF_THEN2599:%.*]], label [[IF_END2600:%.*]]
32429 // SIMD-ONLY0:       if.then2599:
32430 // SIMD-ONLY0-NEXT:    [[TMP1119:%.*]] = load i32, ptr [[IE]], align 4
32431 // SIMD-ONLY0-NEXT:    store i32 [[TMP1119]], ptr [[IX]], align 4
32432 // SIMD-ONLY0-NEXT:    br label [[IF_END2600]]
32433 // SIMD-ONLY0:       if.end2600:
32434 // SIMD-ONLY0-NEXT:    [[TMP1120:%.*]] = load i32, ptr [[IX]], align 4
32435 // SIMD-ONLY0-NEXT:    [[TMP1121:%.*]] = load i32, ptr [[IE]], align 4
32436 // SIMD-ONLY0-NEXT:    [[CMP2601:%.*]] = icmp eq i32 [[TMP1120]], [[TMP1121]]
32437 // SIMD-ONLY0-NEXT:    br i1 [[CMP2601]], label [[COND_TRUE2603:%.*]], label [[COND_FALSE2604:%.*]]
32438 // SIMD-ONLY0:       cond.true2603:
32439 // SIMD-ONLY0-NEXT:    [[TMP1122:%.*]] = load i32, ptr [[ID]], align 4
32440 // SIMD-ONLY0-NEXT:    br label [[COND_END2605:%.*]]
32441 // SIMD-ONLY0:       cond.false2604:
32442 // SIMD-ONLY0-NEXT:    [[TMP1123:%.*]] = load i32, ptr [[IX]], align 4
32443 // SIMD-ONLY0-NEXT:    br label [[COND_END2605]]
32444 // SIMD-ONLY0:       cond.end2605:
32445 // SIMD-ONLY0-NEXT:    [[COND2606:%.*]] = phi i32 [ [[TMP1122]], [[COND_TRUE2603]] ], [ [[TMP1123]], [[COND_FALSE2604]] ]
32446 // SIMD-ONLY0-NEXT:    store i32 [[COND2606]], ptr [[IX]], align 4
32447 // SIMD-ONLY0-NEXT:    [[TMP1124:%.*]] = load i32, ptr [[IE]], align 4
32448 // SIMD-ONLY0-NEXT:    [[TMP1125:%.*]] = load i32, ptr [[IX]], align 4
32449 // SIMD-ONLY0-NEXT:    [[CMP2607:%.*]] = icmp eq i32 [[TMP1124]], [[TMP1125]]
32450 // SIMD-ONLY0-NEXT:    br i1 [[CMP2607]], label [[COND_TRUE2609:%.*]], label [[COND_FALSE2610:%.*]]
32451 // SIMD-ONLY0:       cond.true2609:
32452 // SIMD-ONLY0-NEXT:    [[TMP1126:%.*]] = load i32, ptr [[ID]], align 4
32453 // SIMD-ONLY0-NEXT:    br label [[COND_END2611:%.*]]
32454 // SIMD-ONLY0:       cond.false2610:
32455 // SIMD-ONLY0-NEXT:    [[TMP1127:%.*]] = load i32, ptr [[IX]], align 4
32456 // SIMD-ONLY0-NEXT:    br label [[COND_END2611]]
32457 // SIMD-ONLY0:       cond.end2611:
32458 // SIMD-ONLY0-NEXT:    [[COND2612:%.*]] = phi i32 [ [[TMP1126]], [[COND_TRUE2609]] ], [ [[TMP1127]], [[COND_FALSE2610]] ]
32459 // SIMD-ONLY0-NEXT:    store i32 [[COND2612]], ptr [[IX]], align 4
32460 // SIMD-ONLY0-NEXT:    [[TMP1128:%.*]] = load i32, ptr [[IX]], align 4
32461 // SIMD-ONLY0-NEXT:    [[TMP1129:%.*]] = load i32, ptr [[IE]], align 4
32462 // SIMD-ONLY0-NEXT:    [[CMP2613:%.*]] = icmp eq i32 [[TMP1128]], [[TMP1129]]
32463 // SIMD-ONLY0-NEXT:    br i1 [[CMP2613]], label [[IF_THEN2615:%.*]], label [[IF_END2616:%.*]]
32464 // SIMD-ONLY0:       if.then2615:
32465 // SIMD-ONLY0-NEXT:    [[TMP1130:%.*]] = load i32, ptr [[ID]], align 4
32466 // SIMD-ONLY0-NEXT:    store i32 [[TMP1130]], ptr [[IX]], align 4
32467 // SIMD-ONLY0-NEXT:    br label [[IF_END2616]]
32468 // SIMD-ONLY0:       if.end2616:
32469 // SIMD-ONLY0-NEXT:    [[TMP1131:%.*]] = load i32, ptr [[IE]], align 4
32470 // SIMD-ONLY0-NEXT:    [[TMP1132:%.*]] = load i32, ptr [[IX]], align 4
32471 // SIMD-ONLY0-NEXT:    [[CMP2617:%.*]] = icmp eq i32 [[TMP1131]], [[TMP1132]]
32472 // SIMD-ONLY0-NEXT:    br i1 [[CMP2617]], label [[IF_THEN2619:%.*]], label [[IF_END2620:%.*]]
32473 // SIMD-ONLY0:       if.then2619:
32474 // SIMD-ONLY0-NEXT:    [[TMP1133:%.*]] = load i32, ptr [[ID]], align 4
32475 // SIMD-ONLY0-NEXT:    store i32 [[TMP1133]], ptr [[IX]], align 4
32476 // SIMD-ONLY0-NEXT:    br label [[IF_END2620]]
32477 // SIMD-ONLY0:       if.end2620:
32478 // SIMD-ONLY0-NEXT:    [[TMP1134:%.*]] = load i32, ptr [[UIX]], align 4
32479 // SIMD-ONLY0-NEXT:    [[TMP1135:%.*]] = load i32, ptr [[UIE]], align 4
32480 // SIMD-ONLY0-NEXT:    [[CMP2621:%.*]] = icmp ugt i32 [[TMP1134]], [[TMP1135]]
32481 // SIMD-ONLY0-NEXT:    br i1 [[CMP2621]], label [[COND_TRUE2623:%.*]], label [[COND_FALSE2624:%.*]]
32482 // SIMD-ONLY0:       cond.true2623:
32483 // SIMD-ONLY0-NEXT:    [[TMP1136:%.*]] = load i32, ptr [[UIE]], align 4
32484 // SIMD-ONLY0-NEXT:    br label [[COND_END2625:%.*]]
32485 // SIMD-ONLY0:       cond.false2624:
32486 // SIMD-ONLY0-NEXT:    [[TMP1137:%.*]] = load i32, ptr [[UIX]], align 4
32487 // SIMD-ONLY0-NEXT:    br label [[COND_END2625]]
32488 // SIMD-ONLY0:       cond.end2625:
32489 // SIMD-ONLY0-NEXT:    [[COND2626:%.*]] = phi i32 [ [[TMP1136]], [[COND_TRUE2623]] ], [ [[TMP1137]], [[COND_FALSE2624]] ]
32490 // SIMD-ONLY0-NEXT:    store i32 [[COND2626]], ptr [[UIX]], align 4
32491 // SIMD-ONLY0-NEXT:    [[TMP1138:%.*]] = load i32, ptr [[UIX]], align 4
32492 // SIMD-ONLY0-NEXT:    [[TMP1139:%.*]] = load i32, ptr [[UIE]], align 4
32493 // SIMD-ONLY0-NEXT:    [[CMP2627:%.*]] = icmp ult i32 [[TMP1138]], [[TMP1139]]
32494 // SIMD-ONLY0-NEXT:    br i1 [[CMP2627]], label [[COND_TRUE2629:%.*]], label [[COND_FALSE2630:%.*]]
32495 // SIMD-ONLY0:       cond.true2629:
32496 // SIMD-ONLY0-NEXT:    [[TMP1140:%.*]] = load i32, ptr [[UIE]], align 4
32497 // SIMD-ONLY0-NEXT:    br label [[COND_END2631:%.*]]
32498 // SIMD-ONLY0:       cond.false2630:
32499 // SIMD-ONLY0-NEXT:    [[TMP1141:%.*]] = load i32, ptr [[UIX]], align 4
32500 // SIMD-ONLY0-NEXT:    br label [[COND_END2631]]
32501 // SIMD-ONLY0:       cond.end2631:
32502 // SIMD-ONLY0-NEXT:    [[COND2632:%.*]] = phi i32 [ [[TMP1140]], [[COND_TRUE2629]] ], [ [[TMP1141]], [[COND_FALSE2630]] ]
32503 // SIMD-ONLY0-NEXT:    store i32 [[COND2632]], ptr [[UIX]], align 4
32504 // SIMD-ONLY0-NEXT:    [[TMP1142:%.*]] = load i32, ptr [[UIE]], align 4
32505 // SIMD-ONLY0-NEXT:    [[TMP1143:%.*]] = load i32, ptr [[UIX]], align 4
32506 // SIMD-ONLY0-NEXT:    [[CMP2633:%.*]] = icmp ugt i32 [[TMP1142]], [[TMP1143]]
32507 // SIMD-ONLY0-NEXT:    br i1 [[CMP2633]], label [[COND_TRUE2635:%.*]], label [[COND_FALSE2636:%.*]]
32508 // SIMD-ONLY0:       cond.true2635:
32509 // SIMD-ONLY0-NEXT:    [[TMP1144:%.*]] = load i32, ptr [[UIE]], align 4
32510 // SIMD-ONLY0-NEXT:    br label [[COND_END2637:%.*]]
32511 // SIMD-ONLY0:       cond.false2636:
32512 // SIMD-ONLY0-NEXT:    [[TMP1145:%.*]] = load i32, ptr [[UIX]], align 4
32513 // SIMD-ONLY0-NEXT:    br label [[COND_END2637]]
32514 // SIMD-ONLY0:       cond.end2637:
32515 // SIMD-ONLY0-NEXT:    [[COND2638:%.*]] = phi i32 [ [[TMP1144]], [[COND_TRUE2635]] ], [ [[TMP1145]], [[COND_FALSE2636]] ]
32516 // SIMD-ONLY0-NEXT:    store i32 [[COND2638]], ptr [[UIX]], align 4
32517 // SIMD-ONLY0-NEXT:    [[TMP1146:%.*]] = load i32, ptr [[UIE]], align 4
32518 // SIMD-ONLY0-NEXT:    [[TMP1147:%.*]] = load i32, ptr [[UIX]], align 4
32519 // SIMD-ONLY0-NEXT:    [[CMP2639:%.*]] = icmp ult i32 [[TMP1146]], [[TMP1147]]
32520 // SIMD-ONLY0-NEXT:    br i1 [[CMP2639]], label [[COND_TRUE2641:%.*]], label [[COND_FALSE2642:%.*]]
32521 // SIMD-ONLY0:       cond.true2641:
32522 // SIMD-ONLY0-NEXT:    [[TMP1148:%.*]] = load i32, ptr [[UIE]], align 4
32523 // SIMD-ONLY0-NEXT:    br label [[COND_END2643:%.*]]
32524 // SIMD-ONLY0:       cond.false2642:
32525 // SIMD-ONLY0-NEXT:    [[TMP1149:%.*]] = load i32, ptr [[UIX]], align 4
32526 // SIMD-ONLY0-NEXT:    br label [[COND_END2643]]
32527 // SIMD-ONLY0:       cond.end2643:
32528 // SIMD-ONLY0-NEXT:    [[COND2644:%.*]] = phi i32 [ [[TMP1148]], [[COND_TRUE2641]] ], [ [[TMP1149]], [[COND_FALSE2642]] ]
32529 // SIMD-ONLY0-NEXT:    store i32 [[COND2644]], ptr [[UIX]], align 4
32530 // SIMD-ONLY0-NEXT:    [[TMP1150:%.*]] = load i32, ptr [[UIX]], align 4
32531 // SIMD-ONLY0-NEXT:    [[TMP1151:%.*]] = load i32, ptr [[UIE]], align 4
32532 // SIMD-ONLY0-NEXT:    [[CMP2645:%.*]] = icmp ugt i32 [[TMP1150]], [[TMP1151]]
32533 // SIMD-ONLY0-NEXT:    br i1 [[CMP2645]], label [[IF_THEN2647:%.*]], label [[IF_END2648:%.*]]
32534 // SIMD-ONLY0:       if.then2647:
32535 // SIMD-ONLY0-NEXT:    [[TMP1152:%.*]] = load i32, ptr [[UIE]], align 4
32536 // SIMD-ONLY0-NEXT:    store i32 [[TMP1152]], ptr [[UIX]], align 4
32537 // SIMD-ONLY0-NEXT:    br label [[IF_END2648]]
32538 // SIMD-ONLY0:       if.end2648:
32539 // SIMD-ONLY0-NEXT:    [[TMP1153:%.*]] = load i32, ptr [[UIX]], align 4
32540 // SIMD-ONLY0-NEXT:    [[TMP1154:%.*]] = load i32, ptr [[UIE]], align 4
32541 // SIMD-ONLY0-NEXT:    [[CMP2649:%.*]] = icmp ult i32 [[TMP1153]], [[TMP1154]]
32542 // SIMD-ONLY0-NEXT:    br i1 [[CMP2649]], label [[IF_THEN2651:%.*]], label [[IF_END2652:%.*]]
32543 // SIMD-ONLY0:       if.then2651:
32544 // SIMD-ONLY0-NEXT:    [[TMP1155:%.*]] = load i32, ptr [[UIE]], align 4
32545 // SIMD-ONLY0-NEXT:    store i32 [[TMP1155]], ptr [[UIX]], align 4
32546 // SIMD-ONLY0-NEXT:    br label [[IF_END2652]]
32547 // SIMD-ONLY0:       if.end2652:
32548 // SIMD-ONLY0-NEXT:    [[TMP1156:%.*]] = load i32, ptr [[UIE]], align 4
32549 // SIMD-ONLY0-NEXT:    [[TMP1157:%.*]] = load i32, ptr [[UIX]], align 4
32550 // SIMD-ONLY0-NEXT:    [[CMP2653:%.*]] = icmp ugt i32 [[TMP1156]], [[TMP1157]]
32551 // SIMD-ONLY0-NEXT:    br i1 [[CMP2653]], label [[IF_THEN2655:%.*]], label [[IF_END2656:%.*]]
32552 // SIMD-ONLY0:       if.then2655:
32553 // SIMD-ONLY0-NEXT:    [[TMP1158:%.*]] = load i32, ptr [[UIE]], align 4
32554 // SIMD-ONLY0-NEXT:    store i32 [[TMP1158]], ptr [[UIX]], align 4
32555 // SIMD-ONLY0-NEXT:    br label [[IF_END2656]]
32556 // SIMD-ONLY0:       if.end2656:
32557 // SIMD-ONLY0-NEXT:    [[TMP1159:%.*]] = load i32, ptr [[UIE]], align 4
32558 // SIMD-ONLY0-NEXT:    [[TMP1160:%.*]] = load i32, ptr [[UIX]], align 4
32559 // SIMD-ONLY0-NEXT:    [[CMP2657:%.*]] = icmp ult i32 [[TMP1159]], [[TMP1160]]
32560 // SIMD-ONLY0-NEXT:    br i1 [[CMP2657]], label [[IF_THEN2659:%.*]], label [[IF_END2660:%.*]]
32561 // SIMD-ONLY0:       if.then2659:
32562 // SIMD-ONLY0-NEXT:    [[TMP1161:%.*]] = load i32, ptr [[UIE]], align 4
32563 // SIMD-ONLY0-NEXT:    store i32 [[TMP1161]], ptr [[UIX]], align 4
32564 // SIMD-ONLY0-NEXT:    br label [[IF_END2660]]
32565 // SIMD-ONLY0:       if.end2660:
32566 // SIMD-ONLY0-NEXT:    [[TMP1162:%.*]] = load i32, ptr [[UIX]], align 4
32567 // SIMD-ONLY0-NEXT:    [[TMP1163:%.*]] = load i32, ptr [[UIE]], align 4
32568 // SIMD-ONLY0-NEXT:    [[CMP2661:%.*]] = icmp eq i32 [[TMP1162]], [[TMP1163]]
32569 // SIMD-ONLY0-NEXT:    br i1 [[CMP2661]], label [[COND_TRUE2663:%.*]], label [[COND_FALSE2664:%.*]]
32570 // SIMD-ONLY0:       cond.true2663:
32571 // SIMD-ONLY0-NEXT:    [[TMP1164:%.*]] = load i32, ptr [[UID]], align 4
32572 // SIMD-ONLY0-NEXT:    br label [[COND_END2665:%.*]]
32573 // SIMD-ONLY0:       cond.false2664:
32574 // SIMD-ONLY0-NEXT:    [[TMP1165:%.*]] = load i32, ptr [[UIX]], align 4
32575 // SIMD-ONLY0-NEXT:    br label [[COND_END2665]]
32576 // SIMD-ONLY0:       cond.end2665:
32577 // SIMD-ONLY0-NEXT:    [[COND2666:%.*]] = phi i32 [ [[TMP1164]], [[COND_TRUE2663]] ], [ [[TMP1165]], [[COND_FALSE2664]] ]
32578 // SIMD-ONLY0-NEXT:    store i32 [[COND2666]], ptr [[UIX]], align 4
32579 // SIMD-ONLY0-NEXT:    [[TMP1166:%.*]] = load i32, ptr [[UIE]], align 4
32580 // SIMD-ONLY0-NEXT:    [[TMP1167:%.*]] = load i32, ptr [[UIX]], align 4
32581 // SIMD-ONLY0-NEXT:    [[CMP2667:%.*]] = icmp eq i32 [[TMP1166]], [[TMP1167]]
32582 // SIMD-ONLY0-NEXT:    br i1 [[CMP2667]], label [[COND_TRUE2669:%.*]], label [[COND_FALSE2670:%.*]]
32583 // SIMD-ONLY0:       cond.true2669:
32584 // SIMD-ONLY0-NEXT:    [[TMP1168:%.*]] = load i32, ptr [[UID]], align 4
32585 // SIMD-ONLY0-NEXT:    br label [[COND_END2671:%.*]]
32586 // SIMD-ONLY0:       cond.false2670:
32587 // SIMD-ONLY0-NEXT:    [[TMP1169:%.*]] = load i32, ptr [[UIX]], align 4
32588 // SIMD-ONLY0-NEXT:    br label [[COND_END2671]]
32589 // SIMD-ONLY0:       cond.end2671:
32590 // SIMD-ONLY0-NEXT:    [[COND2672:%.*]] = phi i32 [ [[TMP1168]], [[COND_TRUE2669]] ], [ [[TMP1169]], [[COND_FALSE2670]] ]
32591 // SIMD-ONLY0-NEXT:    store i32 [[COND2672]], ptr [[UIX]], align 4
32592 // SIMD-ONLY0-NEXT:    [[TMP1170:%.*]] = load i32, ptr [[UIX]], align 4
32593 // SIMD-ONLY0-NEXT:    [[TMP1171:%.*]] = load i32, ptr [[UIE]], align 4
32594 // SIMD-ONLY0-NEXT:    [[CMP2673:%.*]] = icmp eq i32 [[TMP1170]], [[TMP1171]]
32595 // SIMD-ONLY0-NEXT:    br i1 [[CMP2673]], label [[IF_THEN2675:%.*]], label [[IF_END2676:%.*]]
32596 // SIMD-ONLY0:       if.then2675:
32597 // SIMD-ONLY0-NEXT:    [[TMP1172:%.*]] = load i32, ptr [[UID]], align 4
32598 // SIMD-ONLY0-NEXT:    store i32 [[TMP1172]], ptr [[UIX]], align 4
32599 // SIMD-ONLY0-NEXT:    br label [[IF_END2676]]
32600 // SIMD-ONLY0:       if.end2676:
32601 // SIMD-ONLY0-NEXT:    [[TMP1173:%.*]] = load i32, ptr [[UIE]], align 4
32602 // SIMD-ONLY0-NEXT:    [[TMP1174:%.*]] = load i32, ptr [[UIX]], align 4
32603 // SIMD-ONLY0-NEXT:    [[CMP2677:%.*]] = icmp eq i32 [[TMP1173]], [[TMP1174]]
32604 // SIMD-ONLY0-NEXT:    br i1 [[CMP2677]], label [[IF_THEN2679:%.*]], label [[IF_END2680:%.*]]
32605 // SIMD-ONLY0:       if.then2679:
32606 // SIMD-ONLY0-NEXT:    [[TMP1175:%.*]] = load i32, ptr [[UID]], align 4
32607 // SIMD-ONLY0-NEXT:    store i32 [[TMP1175]], ptr [[UIX]], align 4
32608 // SIMD-ONLY0-NEXT:    br label [[IF_END2680]]
32609 // SIMD-ONLY0:       if.end2680:
32610 // SIMD-ONLY0-NEXT:    [[TMP1176:%.*]] = load i32, ptr [[IX]], align 4
32611 // SIMD-ONLY0-NEXT:    [[TMP1177:%.*]] = load i32, ptr [[IE]], align 4
32612 // SIMD-ONLY0-NEXT:    [[CMP2681:%.*]] = icmp sgt i32 [[TMP1176]], [[TMP1177]]
32613 // SIMD-ONLY0-NEXT:    br i1 [[CMP2681]], label [[COND_TRUE2683:%.*]], label [[COND_FALSE2684:%.*]]
32614 // SIMD-ONLY0:       cond.true2683:
32615 // SIMD-ONLY0-NEXT:    [[TMP1178:%.*]] = load i32, ptr [[IE]], align 4
32616 // SIMD-ONLY0-NEXT:    br label [[COND_END2685:%.*]]
32617 // SIMD-ONLY0:       cond.false2684:
32618 // SIMD-ONLY0-NEXT:    [[TMP1179:%.*]] = load i32, ptr [[IX]], align 4
32619 // SIMD-ONLY0-NEXT:    br label [[COND_END2685]]
32620 // SIMD-ONLY0:       cond.end2685:
32621 // SIMD-ONLY0-NEXT:    [[COND2686:%.*]] = phi i32 [ [[TMP1178]], [[COND_TRUE2683]] ], [ [[TMP1179]], [[COND_FALSE2684]] ]
32622 // SIMD-ONLY0-NEXT:    store i32 [[COND2686]], ptr [[IX]], align 4
32623 // SIMD-ONLY0-NEXT:    [[TMP1180:%.*]] = load i32, ptr [[IX]], align 4
32624 // SIMD-ONLY0-NEXT:    [[TMP1181:%.*]] = load i32, ptr [[IE]], align 4
32625 // SIMD-ONLY0-NEXT:    [[CMP2687:%.*]] = icmp slt i32 [[TMP1180]], [[TMP1181]]
32626 // SIMD-ONLY0-NEXT:    br i1 [[CMP2687]], label [[COND_TRUE2689:%.*]], label [[COND_FALSE2690:%.*]]
32627 // SIMD-ONLY0:       cond.true2689:
32628 // SIMD-ONLY0-NEXT:    [[TMP1182:%.*]] = load i32, ptr [[IE]], align 4
32629 // SIMD-ONLY0-NEXT:    br label [[COND_END2691:%.*]]
32630 // SIMD-ONLY0:       cond.false2690:
32631 // SIMD-ONLY0-NEXT:    [[TMP1183:%.*]] = load i32, ptr [[IX]], align 4
32632 // SIMD-ONLY0-NEXT:    br label [[COND_END2691]]
32633 // SIMD-ONLY0:       cond.end2691:
32634 // SIMD-ONLY0-NEXT:    [[COND2692:%.*]] = phi i32 [ [[TMP1182]], [[COND_TRUE2689]] ], [ [[TMP1183]], [[COND_FALSE2690]] ]
32635 // SIMD-ONLY0-NEXT:    store i32 [[COND2692]], ptr [[IX]], align 4
32636 // SIMD-ONLY0-NEXT:    [[TMP1184:%.*]] = load i32, ptr [[IE]], align 4
32637 // SIMD-ONLY0-NEXT:    [[TMP1185:%.*]] = load i32, ptr [[IX]], align 4
32638 // SIMD-ONLY0-NEXT:    [[CMP2693:%.*]] = icmp sgt i32 [[TMP1184]], [[TMP1185]]
32639 // SIMD-ONLY0-NEXT:    br i1 [[CMP2693]], label [[COND_TRUE2695:%.*]], label [[COND_FALSE2696:%.*]]
32640 // SIMD-ONLY0:       cond.true2695:
32641 // SIMD-ONLY0-NEXT:    [[TMP1186:%.*]] = load i32, ptr [[IE]], align 4
32642 // SIMD-ONLY0-NEXT:    br label [[COND_END2697:%.*]]
32643 // SIMD-ONLY0:       cond.false2696:
32644 // SIMD-ONLY0-NEXT:    [[TMP1187:%.*]] = load i32, ptr [[IX]], align 4
32645 // SIMD-ONLY0-NEXT:    br label [[COND_END2697]]
32646 // SIMD-ONLY0:       cond.end2697:
32647 // SIMD-ONLY0-NEXT:    [[COND2698:%.*]] = phi i32 [ [[TMP1186]], [[COND_TRUE2695]] ], [ [[TMP1187]], [[COND_FALSE2696]] ]
32648 // SIMD-ONLY0-NEXT:    store i32 [[COND2698]], ptr [[IX]], align 4
32649 // SIMD-ONLY0-NEXT:    [[TMP1188:%.*]] = load i32, ptr [[IE]], align 4
32650 // SIMD-ONLY0-NEXT:    [[TMP1189:%.*]] = load i32, ptr [[IX]], align 4
32651 // SIMD-ONLY0-NEXT:    [[CMP2699:%.*]] = icmp slt i32 [[TMP1188]], [[TMP1189]]
32652 // SIMD-ONLY0-NEXT:    br i1 [[CMP2699]], label [[COND_TRUE2701:%.*]], label [[COND_FALSE2702:%.*]]
32653 // SIMD-ONLY0:       cond.true2701:
32654 // SIMD-ONLY0-NEXT:    [[TMP1190:%.*]] = load i32, ptr [[IE]], align 4
32655 // SIMD-ONLY0-NEXT:    br label [[COND_END2703:%.*]]
32656 // SIMD-ONLY0:       cond.false2702:
32657 // SIMD-ONLY0-NEXT:    [[TMP1191:%.*]] = load i32, ptr [[IX]], align 4
32658 // SIMD-ONLY0-NEXT:    br label [[COND_END2703]]
32659 // SIMD-ONLY0:       cond.end2703:
32660 // SIMD-ONLY0-NEXT:    [[COND2704:%.*]] = phi i32 [ [[TMP1190]], [[COND_TRUE2701]] ], [ [[TMP1191]], [[COND_FALSE2702]] ]
32661 // SIMD-ONLY0-NEXT:    store i32 [[COND2704]], ptr [[IX]], align 4
32662 // SIMD-ONLY0-NEXT:    [[TMP1192:%.*]] = load i32, ptr [[IX]], align 4
32663 // SIMD-ONLY0-NEXT:    [[TMP1193:%.*]] = load i32, ptr [[IE]], align 4
32664 // SIMD-ONLY0-NEXT:    [[CMP2705:%.*]] = icmp sgt i32 [[TMP1192]], [[TMP1193]]
32665 // SIMD-ONLY0-NEXT:    br i1 [[CMP2705]], label [[IF_THEN2707:%.*]], label [[IF_END2708:%.*]]
32666 // SIMD-ONLY0:       if.then2707:
32667 // SIMD-ONLY0-NEXT:    [[TMP1194:%.*]] = load i32, ptr [[IE]], align 4
32668 // SIMD-ONLY0-NEXT:    store i32 [[TMP1194]], ptr [[IX]], align 4
32669 // SIMD-ONLY0-NEXT:    br label [[IF_END2708]]
32670 // SIMD-ONLY0:       if.end2708:
32671 // SIMD-ONLY0-NEXT:    [[TMP1195:%.*]] = load i32, ptr [[IX]], align 4
32672 // SIMD-ONLY0-NEXT:    [[TMP1196:%.*]] = load i32, ptr [[IE]], align 4
32673 // SIMD-ONLY0-NEXT:    [[CMP2709:%.*]] = icmp slt i32 [[TMP1195]], [[TMP1196]]
32674 // SIMD-ONLY0-NEXT:    br i1 [[CMP2709]], label [[IF_THEN2711:%.*]], label [[IF_END2712:%.*]]
32675 // SIMD-ONLY0:       if.then2711:
32676 // SIMD-ONLY0-NEXT:    [[TMP1197:%.*]] = load i32, ptr [[IE]], align 4
32677 // SIMD-ONLY0-NEXT:    store i32 [[TMP1197]], ptr [[IX]], align 4
32678 // SIMD-ONLY0-NEXT:    br label [[IF_END2712]]
32679 // SIMD-ONLY0:       if.end2712:
32680 // SIMD-ONLY0-NEXT:    [[TMP1198:%.*]] = load i32, ptr [[IE]], align 4
32681 // SIMD-ONLY0-NEXT:    [[TMP1199:%.*]] = load i32, ptr [[IX]], align 4
32682 // SIMD-ONLY0-NEXT:    [[CMP2713:%.*]] = icmp sgt i32 [[TMP1198]], [[TMP1199]]
32683 // SIMD-ONLY0-NEXT:    br i1 [[CMP2713]], label [[IF_THEN2715:%.*]], label [[IF_END2716:%.*]]
32684 // SIMD-ONLY0:       if.then2715:
32685 // SIMD-ONLY0-NEXT:    [[TMP1200:%.*]] = load i32, ptr [[IE]], align 4
32686 // SIMD-ONLY0-NEXT:    store i32 [[TMP1200]], ptr [[IX]], align 4
32687 // SIMD-ONLY0-NEXT:    br label [[IF_END2716]]
32688 // SIMD-ONLY0:       if.end2716:
32689 // SIMD-ONLY0-NEXT:    [[TMP1201:%.*]] = load i32, ptr [[IE]], align 4
32690 // SIMD-ONLY0-NEXT:    [[TMP1202:%.*]] = load i32, ptr [[IX]], align 4
32691 // SIMD-ONLY0-NEXT:    [[CMP2717:%.*]] = icmp slt i32 [[TMP1201]], [[TMP1202]]
32692 // SIMD-ONLY0-NEXT:    br i1 [[CMP2717]], label [[IF_THEN2719:%.*]], label [[IF_END2720:%.*]]
32693 // SIMD-ONLY0:       if.then2719:
32694 // SIMD-ONLY0-NEXT:    [[TMP1203:%.*]] = load i32, ptr [[IE]], align 4
32695 // SIMD-ONLY0-NEXT:    store i32 [[TMP1203]], ptr [[IX]], align 4
32696 // SIMD-ONLY0-NEXT:    br label [[IF_END2720]]
32697 // SIMD-ONLY0:       if.end2720:
32698 // SIMD-ONLY0-NEXT:    [[TMP1204:%.*]] = load i32, ptr [[IX]], align 4
32699 // SIMD-ONLY0-NEXT:    [[TMP1205:%.*]] = load i32, ptr [[IE]], align 4
32700 // SIMD-ONLY0-NEXT:    [[CMP2721:%.*]] = icmp eq i32 [[TMP1204]], [[TMP1205]]
32701 // SIMD-ONLY0-NEXT:    br i1 [[CMP2721]], label [[COND_TRUE2723:%.*]], label [[COND_FALSE2724:%.*]]
32702 // SIMD-ONLY0:       cond.true2723:
32703 // SIMD-ONLY0-NEXT:    [[TMP1206:%.*]] = load i32, ptr [[ID]], align 4
32704 // SIMD-ONLY0-NEXT:    br label [[COND_END2725:%.*]]
32705 // SIMD-ONLY0:       cond.false2724:
32706 // SIMD-ONLY0-NEXT:    [[TMP1207:%.*]] = load i32, ptr [[IX]], align 4
32707 // SIMD-ONLY0-NEXT:    br label [[COND_END2725]]
32708 // SIMD-ONLY0:       cond.end2725:
32709 // SIMD-ONLY0-NEXT:    [[COND2726:%.*]] = phi i32 [ [[TMP1206]], [[COND_TRUE2723]] ], [ [[TMP1207]], [[COND_FALSE2724]] ]
32710 // SIMD-ONLY0-NEXT:    store i32 [[COND2726]], ptr [[IX]], align 4
32711 // SIMD-ONLY0-NEXT:    [[TMP1208:%.*]] = load i32, ptr [[IE]], align 4
32712 // SIMD-ONLY0-NEXT:    [[TMP1209:%.*]] = load i32, ptr [[IX]], align 4
32713 // SIMD-ONLY0-NEXT:    [[CMP2727:%.*]] = icmp eq i32 [[TMP1208]], [[TMP1209]]
32714 // SIMD-ONLY0-NEXT:    br i1 [[CMP2727]], label [[COND_TRUE2729:%.*]], label [[COND_FALSE2730:%.*]]
32715 // SIMD-ONLY0:       cond.true2729:
32716 // SIMD-ONLY0-NEXT:    [[TMP1210:%.*]] = load i32, ptr [[ID]], align 4
32717 // SIMD-ONLY0-NEXT:    br label [[COND_END2731:%.*]]
32718 // SIMD-ONLY0:       cond.false2730:
32719 // SIMD-ONLY0-NEXT:    [[TMP1211:%.*]] = load i32, ptr [[IX]], align 4
32720 // SIMD-ONLY0-NEXT:    br label [[COND_END2731]]
32721 // SIMD-ONLY0:       cond.end2731:
32722 // SIMD-ONLY0-NEXT:    [[COND2732:%.*]] = phi i32 [ [[TMP1210]], [[COND_TRUE2729]] ], [ [[TMP1211]], [[COND_FALSE2730]] ]
32723 // SIMD-ONLY0-NEXT:    store i32 [[COND2732]], ptr [[IX]], align 4
32724 // SIMD-ONLY0-NEXT:    [[TMP1212:%.*]] = load i32, ptr [[IX]], align 4
32725 // SIMD-ONLY0-NEXT:    [[TMP1213:%.*]] = load i32, ptr [[IE]], align 4
32726 // SIMD-ONLY0-NEXT:    [[CMP2733:%.*]] = icmp eq i32 [[TMP1212]], [[TMP1213]]
32727 // SIMD-ONLY0-NEXT:    br i1 [[CMP2733]], label [[IF_THEN2735:%.*]], label [[IF_END2736:%.*]]
32728 // SIMD-ONLY0:       if.then2735:
32729 // SIMD-ONLY0-NEXT:    [[TMP1214:%.*]] = load i32, ptr [[ID]], align 4
32730 // SIMD-ONLY0-NEXT:    store i32 [[TMP1214]], ptr [[IX]], align 4
32731 // SIMD-ONLY0-NEXT:    br label [[IF_END2736]]
32732 // SIMD-ONLY0:       if.end2736:
32733 // SIMD-ONLY0-NEXT:    [[TMP1215:%.*]] = load i32, ptr [[IE]], align 4
32734 // SIMD-ONLY0-NEXT:    [[TMP1216:%.*]] = load i32, ptr [[IX]], align 4
32735 // SIMD-ONLY0-NEXT:    [[CMP2737:%.*]] = icmp eq i32 [[TMP1215]], [[TMP1216]]
32736 // SIMD-ONLY0-NEXT:    br i1 [[CMP2737]], label [[IF_THEN2739:%.*]], label [[IF_END2740:%.*]]
32737 // SIMD-ONLY0:       if.then2739:
32738 // SIMD-ONLY0-NEXT:    [[TMP1217:%.*]] = load i32, ptr [[ID]], align 4
32739 // SIMD-ONLY0-NEXT:    store i32 [[TMP1217]], ptr [[IX]], align 4
32740 // SIMD-ONLY0-NEXT:    br label [[IF_END2740]]
32741 // SIMD-ONLY0:       if.end2740:
32742 // SIMD-ONLY0-NEXT:    [[TMP1218:%.*]] = load i32, ptr [[UIX]], align 4
32743 // SIMD-ONLY0-NEXT:    [[TMP1219:%.*]] = load i32, ptr [[UIE]], align 4
32744 // SIMD-ONLY0-NEXT:    [[CMP2741:%.*]] = icmp ugt i32 [[TMP1218]], [[TMP1219]]
32745 // SIMD-ONLY0-NEXT:    br i1 [[CMP2741]], label [[COND_TRUE2743:%.*]], label [[COND_FALSE2744:%.*]]
32746 // SIMD-ONLY0:       cond.true2743:
32747 // SIMD-ONLY0-NEXT:    [[TMP1220:%.*]] = load i32, ptr [[UIE]], align 4
32748 // SIMD-ONLY0-NEXT:    br label [[COND_END2745:%.*]]
32749 // SIMD-ONLY0:       cond.false2744:
32750 // SIMD-ONLY0-NEXT:    [[TMP1221:%.*]] = load i32, ptr [[UIX]], align 4
32751 // SIMD-ONLY0-NEXT:    br label [[COND_END2745]]
32752 // SIMD-ONLY0:       cond.end2745:
32753 // SIMD-ONLY0-NEXT:    [[COND2746:%.*]] = phi i32 [ [[TMP1220]], [[COND_TRUE2743]] ], [ [[TMP1221]], [[COND_FALSE2744]] ]
32754 // SIMD-ONLY0-NEXT:    store i32 [[COND2746]], ptr [[UIX]], align 4
32755 // SIMD-ONLY0-NEXT:    [[TMP1222:%.*]] = load i32, ptr [[UIX]], align 4
32756 // SIMD-ONLY0-NEXT:    [[TMP1223:%.*]] = load i32, ptr [[UIE]], align 4
32757 // SIMD-ONLY0-NEXT:    [[CMP2747:%.*]] = icmp ult i32 [[TMP1222]], [[TMP1223]]
32758 // SIMD-ONLY0-NEXT:    br i1 [[CMP2747]], label [[COND_TRUE2749:%.*]], label [[COND_FALSE2750:%.*]]
32759 // SIMD-ONLY0:       cond.true2749:
32760 // SIMD-ONLY0-NEXT:    [[TMP1224:%.*]] = load i32, ptr [[UIE]], align 4
32761 // SIMD-ONLY0-NEXT:    br label [[COND_END2751:%.*]]
32762 // SIMD-ONLY0:       cond.false2750:
32763 // SIMD-ONLY0-NEXT:    [[TMP1225:%.*]] = load i32, ptr [[UIX]], align 4
32764 // SIMD-ONLY0-NEXT:    br label [[COND_END2751]]
32765 // SIMD-ONLY0:       cond.end2751:
32766 // SIMD-ONLY0-NEXT:    [[COND2752:%.*]] = phi i32 [ [[TMP1224]], [[COND_TRUE2749]] ], [ [[TMP1225]], [[COND_FALSE2750]] ]
32767 // SIMD-ONLY0-NEXT:    store i32 [[COND2752]], ptr [[UIX]], align 4
32768 // SIMD-ONLY0-NEXT:    [[TMP1226:%.*]] = load i32, ptr [[UIE]], align 4
32769 // SIMD-ONLY0-NEXT:    [[TMP1227:%.*]] = load i32, ptr [[UIX]], align 4
32770 // SIMD-ONLY0-NEXT:    [[CMP2753:%.*]] = icmp ugt i32 [[TMP1226]], [[TMP1227]]
32771 // SIMD-ONLY0-NEXT:    br i1 [[CMP2753]], label [[COND_TRUE2755:%.*]], label [[COND_FALSE2756:%.*]]
32772 // SIMD-ONLY0:       cond.true2755:
32773 // SIMD-ONLY0-NEXT:    [[TMP1228:%.*]] = load i32, ptr [[UIE]], align 4
32774 // SIMD-ONLY0-NEXT:    br label [[COND_END2757:%.*]]
32775 // SIMD-ONLY0:       cond.false2756:
32776 // SIMD-ONLY0-NEXT:    [[TMP1229:%.*]] = load i32, ptr [[UIX]], align 4
32777 // SIMD-ONLY0-NEXT:    br label [[COND_END2757]]
32778 // SIMD-ONLY0:       cond.end2757:
32779 // SIMD-ONLY0-NEXT:    [[COND2758:%.*]] = phi i32 [ [[TMP1228]], [[COND_TRUE2755]] ], [ [[TMP1229]], [[COND_FALSE2756]] ]
32780 // SIMD-ONLY0-NEXT:    store i32 [[COND2758]], ptr [[UIX]], align 4
32781 // SIMD-ONLY0-NEXT:    [[TMP1230:%.*]] = load i32, ptr [[UIE]], align 4
32782 // SIMD-ONLY0-NEXT:    [[TMP1231:%.*]] = load i32, ptr [[UIX]], align 4
32783 // SIMD-ONLY0-NEXT:    [[CMP2759:%.*]] = icmp ult i32 [[TMP1230]], [[TMP1231]]
32784 // SIMD-ONLY0-NEXT:    br i1 [[CMP2759]], label [[COND_TRUE2761:%.*]], label [[COND_FALSE2762:%.*]]
32785 // SIMD-ONLY0:       cond.true2761:
32786 // SIMD-ONLY0-NEXT:    [[TMP1232:%.*]] = load i32, ptr [[UIE]], align 4
32787 // SIMD-ONLY0-NEXT:    br label [[COND_END2763:%.*]]
32788 // SIMD-ONLY0:       cond.false2762:
32789 // SIMD-ONLY0-NEXT:    [[TMP1233:%.*]] = load i32, ptr [[UIX]], align 4
32790 // SIMD-ONLY0-NEXT:    br label [[COND_END2763]]
32791 // SIMD-ONLY0:       cond.end2763:
32792 // SIMD-ONLY0-NEXT:    [[COND2764:%.*]] = phi i32 [ [[TMP1232]], [[COND_TRUE2761]] ], [ [[TMP1233]], [[COND_FALSE2762]] ]
32793 // SIMD-ONLY0-NEXT:    store i32 [[COND2764]], ptr [[UIX]], align 4
32794 // SIMD-ONLY0-NEXT:    [[TMP1234:%.*]] = load i32, ptr [[UIX]], align 4
32795 // SIMD-ONLY0-NEXT:    [[TMP1235:%.*]] = load i32, ptr [[UIE]], align 4
32796 // SIMD-ONLY0-NEXT:    [[CMP2765:%.*]] = icmp ugt i32 [[TMP1234]], [[TMP1235]]
32797 // SIMD-ONLY0-NEXT:    br i1 [[CMP2765]], label [[IF_THEN2767:%.*]], label [[IF_END2768:%.*]]
32798 // SIMD-ONLY0:       if.then2767:
32799 // SIMD-ONLY0-NEXT:    [[TMP1236:%.*]] = load i32, ptr [[UIE]], align 4
32800 // SIMD-ONLY0-NEXT:    store i32 [[TMP1236]], ptr [[UIX]], align 4
32801 // SIMD-ONLY0-NEXT:    br label [[IF_END2768]]
32802 // SIMD-ONLY0:       if.end2768:
32803 // SIMD-ONLY0-NEXT:    [[TMP1237:%.*]] = load i32, ptr [[UIX]], align 4
32804 // SIMD-ONLY0-NEXT:    [[TMP1238:%.*]] = load i32, ptr [[UIE]], align 4
32805 // SIMD-ONLY0-NEXT:    [[CMP2769:%.*]] = icmp ult i32 [[TMP1237]], [[TMP1238]]
32806 // SIMD-ONLY0-NEXT:    br i1 [[CMP2769]], label [[IF_THEN2771:%.*]], label [[IF_END2772:%.*]]
32807 // SIMD-ONLY0:       if.then2771:
32808 // SIMD-ONLY0-NEXT:    [[TMP1239:%.*]] = load i32, ptr [[UIE]], align 4
32809 // SIMD-ONLY0-NEXT:    store i32 [[TMP1239]], ptr [[UIX]], align 4
32810 // SIMD-ONLY0-NEXT:    br label [[IF_END2772]]
32811 // SIMD-ONLY0:       if.end2772:
32812 // SIMD-ONLY0-NEXT:    [[TMP1240:%.*]] = load i32, ptr [[UIE]], align 4
32813 // SIMD-ONLY0-NEXT:    [[TMP1241:%.*]] = load i32, ptr [[UIX]], align 4
32814 // SIMD-ONLY0-NEXT:    [[CMP2773:%.*]] = icmp ugt i32 [[TMP1240]], [[TMP1241]]
32815 // SIMD-ONLY0-NEXT:    br i1 [[CMP2773]], label [[IF_THEN2775:%.*]], label [[IF_END2776:%.*]]
32816 // SIMD-ONLY0:       if.then2775:
32817 // SIMD-ONLY0-NEXT:    [[TMP1242:%.*]] = load i32, ptr [[UIE]], align 4
32818 // SIMD-ONLY0-NEXT:    store i32 [[TMP1242]], ptr [[UIX]], align 4
32819 // SIMD-ONLY0-NEXT:    br label [[IF_END2776]]
32820 // SIMD-ONLY0:       if.end2776:
32821 // SIMD-ONLY0-NEXT:    [[TMP1243:%.*]] = load i32, ptr [[UIE]], align 4
32822 // SIMD-ONLY0-NEXT:    [[TMP1244:%.*]] = load i32, ptr [[UIX]], align 4
32823 // SIMD-ONLY0-NEXT:    [[CMP2777:%.*]] = icmp ult i32 [[TMP1243]], [[TMP1244]]
32824 // SIMD-ONLY0-NEXT:    br i1 [[CMP2777]], label [[IF_THEN2779:%.*]], label [[IF_END2780:%.*]]
32825 // SIMD-ONLY0:       if.then2779:
32826 // SIMD-ONLY0-NEXT:    [[TMP1245:%.*]] = load i32, ptr [[UIE]], align 4
32827 // SIMD-ONLY0-NEXT:    store i32 [[TMP1245]], ptr [[UIX]], align 4
32828 // SIMD-ONLY0-NEXT:    br label [[IF_END2780]]
32829 // SIMD-ONLY0:       if.end2780:
32830 // SIMD-ONLY0-NEXT:    [[TMP1246:%.*]] = load i32, ptr [[UIX]], align 4
32831 // SIMD-ONLY0-NEXT:    [[TMP1247:%.*]] = load i32, ptr [[UIE]], align 4
32832 // SIMD-ONLY0-NEXT:    [[CMP2781:%.*]] = icmp eq i32 [[TMP1246]], [[TMP1247]]
32833 // SIMD-ONLY0-NEXT:    br i1 [[CMP2781]], label [[COND_TRUE2783:%.*]], label [[COND_FALSE2784:%.*]]
32834 // SIMD-ONLY0:       cond.true2783:
32835 // SIMD-ONLY0-NEXT:    [[TMP1248:%.*]] = load i32, ptr [[UID]], align 4
32836 // SIMD-ONLY0-NEXT:    br label [[COND_END2785:%.*]]
32837 // SIMD-ONLY0:       cond.false2784:
32838 // SIMD-ONLY0-NEXT:    [[TMP1249:%.*]] = load i32, ptr [[UIX]], align 4
32839 // SIMD-ONLY0-NEXT:    br label [[COND_END2785]]
32840 // SIMD-ONLY0:       cond.end2785:
32841 // SIMD-ONLY0-NEXT:    [[COND2786:%.*]] = phi i32 [ [[TMP1248]], [[COND_TRUE2783]] ], [ [[TMP1249]], [[COND_FALSE2784]] ]
32842 // SIMD-ONLY0-NEXT:    store i32 [[COND2786]], ptr [[UIX]], align 4
32843 // SIMD-ONLY0-NEXT:    [[TMP1250:%.*]] = load i32, ptr [[UIE]], align 4
32844 // SIMD-ONLY0-NEXT:    [[TMP1251:%.*]] = load i32, ptr [[UIX]], align 4
32845 // SIMD-ONLY0-NEXT:    [[CMP2787:%.*]] = icmp eq i32 [[TMP1250]], [[TMP1251]]
32846 // SIMD-ONLY0-NEXT:    br i1 [[CMP2787]], label [[COND_TRUE2789:%.*]], label [[COND_FALSE2790:%.*]]
32847 // SIMD-ONLY0:       cond.true2789:
32848 // SIMD-ONLY0-NEXT:    [[TMP1252:%.*]] = load i32, ptr [[UID]], align 4
32849 // SIMD-ONLY0-NEXT:    br label [[COND_END2791:%.*]]
32850 // SIMD-ONLY0:       cond.false2790:
32851 // SIMD-ONLY0-NEXT:    [[TMP1253:%.*]] = load i32, ptr [[UIX]], align 4
32852 // SIMD-ONLY0-NEXT:    br label [[COND_END2791]]
32853 // SIMD-ONLY0:       cond.end2791:
32854 // SIMD-ONLY0-NEXT:    [[COND2792:%.*]] = phi i32 [ [[TMP1252]], [[COND_TRUE2789]] ], [ [[TMP1253]], [[COND_FALSE2790]] ]
32855 // SIMD-ONLY0-NEXT:    store i32 [[COND2792]], ptr [[UIX]], align 4
32856 // SIMD-ONLY0-NEXT:    [[TMP1254:%.*]] = load i32, ptr [[UIX]], align 4
32857 // SIMD-ONLY0-NEXT:    [[TMP1255:%.*]] = load i32, ptr [[UIE]], align 4
32858 // SIMD-ONLY0-NEXT:    [[CMP2793:%.*]] = icmp eq i32 [[TMP1254]], [[TMP1255]]
32859 // SIMD-ONLY0-NEXT:    br i1 [[CMP2793]], label [[IF_THEN2795:%.*]], label [[IF_END2796:%.*]]
32860 // SIMD-ONLY0:       if.then2795:
32861 // SIMD-ONLY0-NEXT:    [[TMP1256:%.*]] = load i32, ptr [[UID]], align 4
32862 // SIMD-ONLY0-NEXT:    store i32 [[TMP1256]], ptr [[UIX]], align 4
32863 // SIMD-ONLY0-NEXT:    br label [[IF_END2796]]
32864 // SIMD-ONLY0:       if.end2796:
32865 // SIMD-ONLY0-NEXT:    [[TMP1257:%.*]] = load i32, ptr [[UIE]], align 4
32866 // SIMD-ONLY0-NEXT:    [[TMP1258:%.*]] = load i32, ptr [[UIX]], align 4
32867 // SIMD-ONLY0-NEXT:    [[CMP2797:%.*]] = icmp eq i32 [[TMP1257]], [[TMP1258]]
32868 // SIMD-ONLY0-NEXT:    br i1 [[CMP2797]], label [[IF_THEN2799:%.*]], label [[IF_END2800:%.*]]
32869 // SIMD-ONLY0:       if.then2799:
32870 // SIMD-ONLY0-NEXT:    [[TMP1259:%.*]] = load i32, ptr [[UID]], align 4
32871 // SIMD-ONLY0-NEXT:    store i32 [[TMP1259]], ptr [[UIX]], align 4
32872 // SIMD-ONLY0-NEXT:    br label [[IF_END2800]]
32873 // SIMD-ONLY0:       if.end2800:
32874 // SIMD-ONLY0-NEXT:    [[TMP1260:%.*]] = load i32, ptr [[IX]], align 4
32875 // SIMD-ONLY0-NEXT:    [[TMP1261:%.*]] = load i32, ptr [[IE]], align 4
32876 // SIMD-ONLY0-NEXT:    [[CMP2801:%.*]] = icmp sgt i32 [[TMP1260]], [[TMP1261]]
32877 // SIMD-ONLY0-NEXT:    br i1 [[CMP2801]], label [[COND_TRUE2803:%.*]], label [[COND_FALSE2804:%.*]]
32878 // SIMD-ONLY0:       cond.true2803:
32879 // SIMD-ONLY0-NEXT:    [[TMP1262:%.*]] = load i32, ptr [[IE]], align 4
32880 // SIMD-ONLY0-NEXT:    br label [[COND_END2805:%.*]]
32881 // SIMD-ONLY0:       cond.false2804:
32882 // SIMD-ONLY0-NEXT:    [[TMP1263:%.*]] = load i32, ptr [[IX]], align 4
32883 // SIMD-ONLY0-NEXT:    br label [[COND_END2805]]
32884 // SIMD-ONLY0:       cond.end2805:
32885 // SIMD-ONLY0-NEXT:    [[COND2806:%.*]] = phi i32 [ [[TMP1262]], [[COND_TRUE2803]] ], [ [[TMP1263]], [[COND_FALSE2804]] ]
32886 // SIMD-ONLY0-NEXT:    store i32 [[COND2806]], ptr [[IX]], align 4
32887 // SIMD-ONLY0-NEXT:    [[TMP1264:%.*]] = load i32, ptr [[IX]], align 4
32888 // SIMD-ONLY0-NEXT:    [[TMP1265:%.*]] = load i32, ptr [[IE]], align 4
32889 // SIMD-ONLY0-NEXT:    [[CMP2807:%.*]] = icmp slt i32 [[TMP1264]], [[TMP1265]]
32890 // SIMD-ONLY0-NEXT:    br i1 [[CMP2807]], label [[COND_TRUE2809:%.*]], label [[COND_FALSE2810:%.*]]
32891 // SIMD-ONLY0:       cond.true2809:
32892 // SIMD-ONLY0-NEXT:    [[TMP1266:%.*]] = load i32, ptr [[IE]], align 4
32893 // SIMD-ONLY0-NEXT:    br label [[COND_END2811:%.*]]
32894 // SIMD-ONLY0:       cond.false2810:
32895 // SIMD-ONLY0-NEXT:    [[TMP1267:%.*]] = load i32, ptr [[IX]], align 4
32896 // SIMD-ONLY0-NEXT:    br label [[COND_END2811]]
32897 // SIMD-ONLY0:       cond.end2811:
32898 // SIMD-ONLY0-NEXT:    [[COND2812:%.*]] = phi i32 [ [[TMP1266]], [[COND_TRUE2809]] ], [ [[TMP1267]], [[COND_FALSE2810]] ]
32899 // SIMD-ONLY0-NEXT:    store i32 [[COND2812]], ptr [[IX]], align 4
32900 // SIMD-ONLY0-NEXT:    [[TMP1268:%.*]] = load i32, ptr [[IE]], align 4
32901 // SIMD-ONLY0-NEXT:    [[TMP1269:%.*]] = load i32, ptr [[IX]], align 4
32902 // SIMD-ONLY0-NEXT:    [[CMP2813:%.*]] = icmp sgt i32 [[TMP1268]], [[TMP1269]]
32903 // SIMD-ONLY0-NEXT:    br i1 [[CMP2813]], label [[COND_TRUE2815:%.*]], label [[COND_FALSE2816:%.*]]
32904 // SIMD-ONLY0:       cond.true2815:
32905 // SIMD-ONLY0-NEXT:    [[TMP1270:%.*]] = load i32, ptr [[IE]], align 4
32906 // SIMD-ONLY0-NEXT:    br label [[COND_END2817:%.*]]
32907 // SIMD-ONLY0:       cond.false2816:
32908 // SIMD-ONLY0-NEXT:    [[TMP1271:%.*]] = load i32, ptr [[IX]], align 4
32909 // SIMD-ONLY0-NEXT:    br label [[COND_END2817]]
32910 // SIMD-ONLY0:       cond.end2817:
32911 // SIMD-ONLY0-NEXT:    [[COND2818:%.*]] = phi i32 [ [[TMP1270]], [[COND_TRUE2815]] ], [ [[TMP1271]], [[COND_FALSE2816]] ]
32912 // SIMD-ONLY0-NEXT:    store i32 [[COND2818]], ptr [[IX]], align 4
32913 // SIMD-ONLY0-NEXT:    [[TMP1272:%.*]] = load i32, ptr [[IE]], align 4
32914 // SIMD-ONLY0-NEXT:    [[TMP1273:%.*]] = load i32, ptr [[IX]], align 4
32915 // SIMD-ONLY0-NEXT:    [[CMP2819:%.*]] = icmp slt i32 [[TMP1272]], [[TMP1273]]
32916 // SIMD-ONLY0-NEXT:    br i1 [[CMP2819]], label [[COND_TRUE2821:%.*]], label [[COND_FALSE2822:%.*]]
32917 // SIMD-ONLY0:       cond.true2821:
32918 // SIMD-ONLY0-NEXT:    [[TMP1274:%.*]] = load i32, ptr [[IE]], align 4
32919 // SIMD-ONLY0-NEXT:    br label [[COND_END2823:%.*]]
32920 // SIMD-ONLY0:       cond.false2822:
32921 // SIMD-ONLY0-NEXT:    [[TMP1275:%.*]] = load i32, ptr [[IX]], align 4
32922 // SIMD-ONLY0-NEXT:    br label [[COND_END2823]]
32923 // SIMD-ONLY0:       cond.end2823:
32924 // SIMD-ONLY0-NEXT:    [[COND2824:%.*]] = phi i32 [ [[TMP1274]], [[COND_TRUE2821]] ], [ [[TMP1275]], [[COND_FALSE2822]] ]
32925 // SIMD-ONLY0-NEXT:    store i32 [[COND2824]], ptr [[IX]], align 4
32926 // SIMD-ONLY0-NEXT:    [[TMP1276:%.*]] = load i32, ptr [[IX]], align 4
32927 // SIMD-ONLY0-NEXT:    [[TMP1277:%.*]] = load i32, ptr [[IE]], align 4
32928 // SIMD-ONLY0-NEXT:    [[CMP2825:%.*]] = icmp sgt i32 [[TMP1276]], [[TMP1277]]
32929 // SIMD-ONLY0-NEXT:    br i1 [[CMP2825]], label [[IF_THEN2827:%.*]], label [[IF_END2828:%.*]]
32930 // SIMD-ONLY0:       if.then2827:
32931 // SIMD-ONLY0-NEXT:    [[TMP1278:%.*]] = load i32, ptr [[IE]], align 4
32932 // SIMD-ONLY0-NEXT:    store i32 [[TMP1278]], ptr [[IX]], align 4
32933 // SIMD-ONLY0-NEXT:    br label [[IF_END2828]]
32934 // SIMD-ONLY0:       if.end2828:
32935 // SIMD-ONLY0-NEXT:    [[TMP1279:%.*]] = load i32, ptr [[IX]], align 4
32936 // SIMD-ONLY0-NEXT:    [[TMP1280:%.*]] = load i32, ptr [[IE]], align 4
32937 // SIMD-ONLY0-NEXT:    [[CMP2829:%.*]] = icmp slt i32 [[TMP1279]], [[TMP1280]]
32938 // SIMD-ONLY0-NEXT:    br i1 [[CMP2829]], label [[IF_THEN2831:%.*]], label [[IF_END2832:%.*]]
32939 // SIMD-ONLY0:       if.then2831:
32940 // SIMD-ONLY0-NEXT:    [[TMP1281:%.*]] = load i32, ptr [[IE]], align 4
32941 // SIMD-ONLY0-NEXT:    store i32 [[TMP1281]], ptr [[IX]], align 4
32942 // SIMD-ONLY0-NEXT:    br label [[IF_END2832]]
32943 // SIMD-ONLY0:       if.end2832:
32944 // SIMD-ONLY0-NEXT:    [[TMP1282:%.*]] = load i32, ptr [[IE]], align 4
32945 // SIMD-ONLY0-NEXT:    [[TMP1283:%.*]] = load i32, ptr [[IX]], align 4
32946 // SIMD-ONLY0-NEXT:    [[CMP2833:%.*]] = icmp sgt i32 [[TMP1282]], [[TMP1283]]
32947 // SIMD-ONLY0-NEXT:    br i1 [[CMP2833]], label [[IF_THEN2835:%.*]], label [[IF_END2836:%.*]]
32948 // SIMD-ONLY0:       if.then2835:
32949 // SIMD-ONLY0-NEXT:    [[TMP1284:%.*]] = load i32, ptr [[IE]], align 4
32950 // SIMD-ONLY0-NEXT:    store i32 [[TMP1284]], ptr [[IX]], align 4
32951 // SIMD-ONLY0-NEXT:    br label [[IF_END2836]]
32952 // SIMD-ONLY0:       if.end2836:
32953 // SIMD-ONLY0-NEXT:    [[TMP1285:%.*]] = load i32, ptr [[IE]], align 4
32954 // SIMD-ONLY0-NEXT:    [[TMP1286:%.*]] = load i32, ptr [[IX]], align 4
32955 // SIMD-ONLY0-NEXT:    [[CMP2837:%.*]] = icmp slt i32 [[TMP1285]], [[TMP1286]]
32956 // SIMD-ONLY0-NEXT:    br i1 [[CMP2837]], label [[IF_THEN2839:%.*]], label [[IF_END2840:%.*]]
32957 // SIMD-ONLY0:       if.then2839:
32958 // SIMD-ONLY0-NEXT:    [[TMP1287:%.*]] = load i32, ptr [[IE]], align 4
32959 // SIMD-ONLY0-NEXT:    store i32 [[TMP1287]], ptr [[IX]], align 4
32960 // SIMD-ONLY0-NEXT:    br label [[IF_END2840]]
32961 // SIMD-ONLY0:       if.end2840:
32962 // SIMD-ONLY0-NEXT:    [[TMP1288:%.*]] = load i32, ptr [[IX]], align 4
32963 // SIMD-ONLY0-NEXT:    [[TMP1289:%.*]] = load i32, ptr [[IE]], align 4
32964 // SIMD-ONLY0-NEXT:    [[CMP2841:%.*]] = icmp eq i32 [[TMP1288]], [[TMP1289]]
32965 // SIMD-ONLY0-NEXT:    br i1 [[CMP2841]], label [[COND_TRUE2843:%.*]], label [[COND_FALSE2844:%.*]]
32966 // SIMD-ONLY0:       cond.true2843:
32967 // SIMD-ONLY0-NEXT:    [[TMP1290:%.*]] = load i32, ptr [[ID]], align 4
32968 // SIMD-ONLY0-NEXT:    br label [[COND_END2845:%.*]]
32969 // SIMD-ONLY0:       cond.false2844:
32970 // SIMD-ONLY0-NEXT:    [[TMP1291:%.*]] = load i32, ptr [[IX]], align 4
32971 // SIMD-ONLY0-NEXT:    br label [[COND_END2845]]
32972 // SIMD-ONLY0:       cond.end2845:
32973 // SIMD-ONLY0-NEXT:    [[COND2846:%.*]] = phi i32 [ [[TMP1290]], [[COND_TRUE2843]] ], [ [[TMP1291]], [[COND_FALSE2844]] ]
32974 // SIMD-ONLY0-NEXT:    store i32 [[COND2846]], ptr [[IX]], align 4
32975 // SIMD-ONLY0-NEXT:    [[TMP1292:%.*]] = load i32, ptr [[IE]], align 4
32976 // SIMD-ONLY0-NEXT:    [[TMP1293:%.*]] = load i32, ptr [[IX]], align 4
32977 // SIMD-ONLY0-NEXT:    [[CMP2847:%.*]] = icmp eq i32 [[TMP1292]], [[TMP1293]]
32978 // SIMD-ONLY0-NEXT:    br i1 [[CMP2847]], label [[COND_TRUE2849:%.*]], label [[COND_FALSE2850:%.*]]
32979 // SIMD-ONLY0:       cond.true2849:
32980 // SIMD-ONLY0-NEXT:    [[TMP1294:%.*]] = load i32, ptr [[ID]], align 4
32981 // SIMD-ONLY0-NEXT:    br label [[COND_END2851:%.*]]
32982 // SIMD-ONLY0:       cond.false2850:
32983 // SIMD-ONLY0-NEXT:    [[TMP1295:%.*]] = load i32, ptr [[IX]], align 4
32984 // SIMD-ONLY0-NEXT:    br label [[COND_END2851]]
32985 // SIMD-ONLY0:       cond.end2851:
32986 // SIMD-ONLY0-NEXT:    [[COND2852:%.*]] = phi i32 [ [[TMP1294]], [[COND_TRUE2849]] ], [ [[TMP1295]], [[COND_FALSE2850]] ]
32987 // SIMD-ONLY0-NEXT:    store i32 [[COND2852]], ptr [[IX]], align 4
32988 // SIMD-ONLY0-NEXT:    [[TMP1296:%.*]] = load i32, ptr [[IX]], align 4
32989 // SIMD-ONLY0-NEXT:    [[TMP1297:%.*]] = load i32, ptr [[IE]], align 4
32990 // SIMD-ONLY0-NEXT:    [[CMP2853:%.*]] = icmp eq i32 [[TMP1296]], [[TMP1297]]
32991 // SIMD-ONLY0-NEXT:    br i1 [[CMP2853]], label [[IF_THEN2855:%.*]], label [[IF_END2856:%.*]]
32992 // SIMD-ONLY0:       if.then2855:
32993 // SIMD-ONLY0-NEXT:    [[TMP1298:%.*]] = load i32, ptr [[ID]], align 4
32994 // SIMD-ONLY0-NEXT:    store i32 [[TMP1298]], ptr [[IX]], align 4
32995 // SIMD-ONLY0-NEXT:    br label [[IF_END2856]]
32996 // SIMD-ONLY0:       if.end2856:
32997 // SIMD-ONLY0-NEXT:    [[TMP1299:%.*]] = load i32, ptr [[IE]], align 4
32998 // SIMD-ONLY0-NEXT:    [[TMP1300:%.*]] = load i32, ptr [[IX]], align 4
32999 // SIMD-ONLY0-NEXT:    [[CMP2857:%.*]] = icmp eq i32 [[TMP1299]], [[TMP1300]]
33000 // SIMD-ONLY0-NEXT:    br i1 [[CMP2857]], label [[IF_THEN2859:%.*]], label [[IF_END2860:%.*]]
33001 // SIMD-ONLY0:       if.then2859:
33002 // SIMD-ONLY0-NEXT:    [[TMP1301:%.*]] = load i32, ptr [[ID]], align 4
33003 // SIMD-ONLY0-NEXT:    store i32 [[TMP1301]], ptr [[IX]], align 4
33004 // SIMD-ONLY0-NEXT:    br label [[IF_END2860]]
33005 // SIMD-ONLY0:       if.end2860:
33006 // SIMD-ONLY0-NEXT:    [[TMP1302:%.*]] = load i32, ptr [[UIX]], align 4
33007 // SIMD-ONLY0-NEXT:    [[TMP1303:%.*]] = load i32, ptr [[UIE]], align 4
33008 // SIMD-ONLY0-NEXT:    [[CMP2861:%.*]] = icmp ugt i32 [[TMP1302]], [[TMP1303]]
33009 // SIMD-ONLY0-NEXT:    br i1 [[CMP2861]], label [[COND_TRUE2863:%.*]], label [[COND_FALSE2864:%.*]]
33010 // SIMD-ONLY0:       cond.true2863:
33011 // SIMD-ONLY0-NEXT:    [[TMP1304:%.*]] = load i32, ptr [[UIE]], align 4
33012 // SIMD-ONLY0-NEXT:    br label [[COND_END2865:%.*]]
33013 // SIMD-ONLY0:       cond.false2864:
33014 // SIMD-ONLY0-NEXT:    [[TMP1305:%.*]] = load i32, ptr [[UIX]], align 4
33015 // SIMD-ONLY0-NEXT:    br label [[COND_END2865]]
33016 // SIMD-ONLY0:       cond.end2865:
33017 // SIMD-ONLY0-NEXT:    [[COND2866:%.*]] = phi i32 [ [[TMP1304]], [[COND_TRUE2863]] ], [ [[TMP1305]], [[COND_FALSE2864]] ]
33018 // SIMD-ONLY0-NEXT:    store i32 [[COND2866]], ptr [[UIX]], align 4
33019 // SIMD-ONLY0-NEXT:    [[TMP1306:%.*]] = load i32, ptr [[UIX]], align 4
33020 // SIMD-ONLY0-NEXT:    [[TMP1307:%.*]] = load i32, ptr [[UIE]], align 4
33021 // SIMD-ONLY0-NEXT:    [[CMP2867:%.*]] = icmp ult i32 [[TMP1306]], [[TMP1307]]
33022 // SIMD-ONLY0-NEXT:    br i1 [[CMP2867]], label [[COND_TRUE2869:%.*]], label [[COND_FALSE2870:%.*]]
33023 // SIMD-ONLY0:       cond.true2869:
33024 // SIMD-ONLY0-NEXT:    [[TMP1308:%.*]] = load i32, ptr [[UIE]], align 4
33025 // SIMD-ONLY0-NEXT:    br label [[COND_END2871:%.*]]
33026 // SIMD-ONLY0:       cond.false2870:
33027 // SIMD-ONLY0-NEXT:    [[TMP1309:%.*]] = load i32, ptr [[UIX]], align 4
33028 // SIMD-ONLY0-NEXT:    br label [[COND_END2871]]
33029 // SIMD-ONLY0:       cond.end2871:
33030 // SIMD-ONLY0-NEXT:    [[COND2872:%.*]] = phi i32 [ [[TMP1308]], [[COND_TRUE2869]] ], [ [[TMP1309]], [[COND_FALSE2870]] ]
33031 // SIMD-ONLY0-NEXT:    store i32 [[COND2872]], ptr [[UIX]], align 4
33032 // SIMD-ONLY0-NEXT:    [[TMP1310:%.*]] = load i32, ptr [[UIE]], align 4
33033 // SIMD-ONLY0-NEXT:    [[TMP1311:%.*]] = load i32, ptr [[UIX]], align 4
33034 // SIMD-ONLY0-NEXT:    [[CMP2873:%.*]] = icmp ugt i32 [[TMP1310]], [[TMP1311]]
33035 // SIMD-ONLY0-NEXT:    br i1 [[CMP2873]], label [[COND_TRUE2875:%.*]], label [[COND_FALSE2876:%.*]]
33036 // SIMD-ONLY0:       cond.true2875:
33037 // SIMD-ONLY0-NEXT:    [[TMP1312:%.*]] = load i32, ptr [[UIE]], align 4
33038 // SIMD-ONLY0-NEXT:    br label [[COND_END2877:%.*]]
33039 // SIMD-ONLY0:       cond.false2876:
33040 // SIMD-ONLY0-NEXT:    [[TMP1313:%.*]] = load i32, ptr [[UIX]], align 4
33041 // SIMD-ONLY0-NEXT:    br label [[COND_END2877]]
33042 // SIMD-ONLY0:       cond.end2877:
33043 // SIMD-ONLY0-NEXT:    [[COND2878:%.*]] = phi i32 [ [[TMP1312]], [[COND_TRUE2875]] ], [ [[TMP1313]], [[COND_FALSE2876]] ]
33044 // SIMD-ONLY0-NEXT:    store i32 [[COND2878]], ptr [[UIX]], align 4
33045 // SIMD-ONLY0-NEXT:    [[TMP1314:%.*]] = load i32, ptr [[UIE]], align 4
33046 // SIMD-ONLY0-NEXT:    [[TMP1315:%.*]] = load i32, ptr [[UIX]], align 4
33047 // SIMD-ONLY0-NEXT:    [[CMP2879:%.*]] = icmp ult i32 [[TMP1314]], [[TMP1315]]
33048 // SIMD-ONLY0-NEXT:    br i1 [[CMP2879]], label [[COND_TRUE2881:%.*]], label [[COND_FALSE2882:%.*]]
33049 // SIMD-ONLY0:       cond.true2881:
33050 // SIMD-ONLY0-NEXT:    [[TMP1316:%.*]] = load i32, ptr [[UIE]], align 4
33051 // SIMD-ONLY0-NEXT:    br label [[COND_END2883:%.*]]
33052 // SIMD-ONLY0:       cond.false2882:
33053 // SIMD-ONLY0-NEXT:    [[TMP1317:%.*]] = load i32, ptr [[UIX]], align 4
33054 // SIMD-ONLY0-NEXT:    br label [[COND_END2883]]
33055 // SIMD-ONLY0:       cond.end2883:
33056 // SIMD-ONLY0-NEXT:    [[COND2884:%.*]] = phi i32 [ [[TMP1316]], [[COND_TRUE2881]] ], [ [[TMP1317]], [[COND_FALSE2882]] ]
33057 // SIMD-ONLY0-NEXT:    store i32 [[COND2884]], ptr [[UIX]], align 4
33058 // SIMD-ONLY0-NEXT:    [[TMP1318:%.*]] = load i32, ptr [[UIX]], align 4
33059 // SIMD-ONLY0-NEXT:    [[TMP1319:%.*]] = load i32, ptr [[UIE]], align 4
33060 // SIMD-ONLY0-NEXT:    [[CMP2885:%.*]] = icmp ugt i32 [[TMP1318]], [[TMP1319]]
33061 // SIMD-ONLY0-NEXT:    br i1 [[CMP2885]], label [[IF_THEN2887:%.*]], label [[IF_END2888:%.*]]
33062 // SIMD-ONLY0:       if.then2887:
33063 // SIMD-ONLY0-NEXT:    [[TMP1320:%.*]] = load i32, ptr [[UIE]], align 4
33064 // SIMD-ONLY0-NEXT:    store i32 [[TMP1320]], ptr [[UIX]], align 4
33065 // SIMD-ONLY0-NEXT:    br label [[IF_END2888]]
33066 // SIMD-ONLY0:       if.end2888:
33067 // SIMD-ONLY0-NEXT:    [[TMP1321:%.*]] = load i32, ptr [[UIX]], align 4
33068 // SIMD-ONLY0-NEXT:    [[TMP1322:%.*]] = load i32, ptr [[UIE]], align 4
33069 // SIMD-ONLY0-NEXT:    [[CMP2889:%.*]] = icmp ult i32 [[TMP1321]], [[TMP1322]]
33070 // SIMD-ONLY0-NEXT:    br i1 [[CMP2889]], label [[IF_THEN2891:%.*]], label [[IF_END2892:%.*]]
33071 // SIMD-ONLY0:       if.then2891:
33072 // SIMD-ONLY0-NEXT:    [[TMP1323:%.*]] = load i32, ptr [[UIE]], align 4
33073 // SIMD-ONLY0-NEXT:    store i32 [[TMP1323]], ptr [[UIX]], align 4
33074 // SIMD-ONLY0-NEXT:    br label [[IF_END2892]]
33075 // SIMD-ONLY0:       if.end2892:
33076 // SIMD-ONLY0-NEXT:    [[TMP1324:%.*]] = load i32, ptr [[UIE]], align 4
33077 // SIMD-ONLY0-NEXT:    [[TMP1325:%.*]] = load i32, ptr [[UIX]], align 4
33078 // SIMD-ONLY0-NEXT:    [[CMP2893:%.*]] = icmp ugt i32 [[TMP1324]], [[TMP1325]]
33079 // SIMD-ONLY0-NEXT:    br i1 [[CMP2893]], label [[IF_THEN2895:%.*]], label [[IF_END2896:%.*]]
33080 // SIMD-ONLY0:       if.then2895:
33081 // SIMD-ONLY0-NEXT:    [[TMP1326:%.*]] = load i32, ptr [[UIE]], align 4
33082 // SIMD-ONLY0-NEXT:    store i32 [[TMP1326]], ptr [[UIX]], align 4
33083 // SIMD-ONLY0-NEXT:    br label [[IF_END2896]]
33084 // SIMD-ONLY0:       if.end2896:
33085 // SIMD-ONLY0-NEXT:    [[TMP1327:%.*]] = load i32, ptr [[UIE]], align 4
33086 // SIMD-ONLY0-NEXT:    [[TMP1328:%.*]] = load i32, ptr [[UIX]], align 4
33087 // SIMD-ONLY0-NEXT:    [[CMP2897:%.*]] = icmp ult i32 [[TMP1327]], [[TMP1328]]
33088 // SIMD-ONLY0-NEXT:    br i1 [[CMP2897]], label [[IF_THEN2899:%.*]], label [[IF_END2900:%.*]]
33089 // SIMD-ONLY0:       if.then2899:
33090 // SIMD-ONLY0-NEXT:    [[TMP1329:%.*]] = load i32, ptr [[UIE]], align 4
33091 // SIMD-ONLY0-NEXT:    store i32 [[TMP1329]], ptr [[UIX]], align 4
33092 // SIMD-ONLY0-NEXT:    br label [[IF_END2900]]
33093 // SIMD-ONLY0:       if.end2900:
33094 // SIMD-ONLY0-NEXT:    [[TMP1330:%.*]] = load i32, ptr [[UIX]], align 4
33095 // SIMD-ONLY0-NEXT:    [[TMP1331:%.*]] = load i32, ptr [[UIE]], align 4
33096 // SIMD-ONLY0-NEXT:    [[CMP2901:%.*]] = icmp eq i32 [[TMP1330]], [[TMP1331]]
33097 // SIMD-ONLY0-NEXT:    br i1 [[CMP2901]], label [[COND_TRUE2903:%.*]], label [[COND_FALSE2904:%.*]]
33098 // SIMD-ONLY0:       cond.true2903:
33099 // SIMD-ONLY0-NEXT:    [[TMP1332:%.*]] = load i32, ptr [[UID]], align 4
33100 // SIMD-ONLY0-NEXT:    br label [[COND_END2905:%.*]]
33101 // SIMD-ONLY0:       cond.false2904:
33102 // SIMD-ONLY0-NEXT:    [[TMP1333:%.*]] = load i32, ptr [[UIX]], align 4
33103 // SIMD-ONLY0-NEXT:    br label [[COND_END2905]]
33104 // SIMD-ONLY0:       cond.end2905:
33105 // SIMD-ONLY0-NEXT:    [[COND2906:%.*]] = phi i32 [ [[TMP1332]], [[COND_TRUE2903]] ], [ [[TMP1333]], [[COND_FALSE2904]] ]
33106 // SIMD-ONLY0-NEXT:    store i32 [[COND2906]], ptr [[UIX]], align 4
33107 // SIMD-ONLY0-NEXT:    [[TMP1334:%.*]] = load i32, ptr [[UIE]], align 4
33108 // SIMD-ONLY0-NEXT:    [[TMP1335:%.*]] = load i32, ptr [[UIX]], align 4
33109 // SIMD-ONLY0-NEXT:    [[CMP2907:%.*]] = icmp eq i32 [[TMP1334]], [[TMP1335]]
33110 // SIMD-ONLY0-NEXT:    br i1 [[CMP2907]], label [[COND_TRUE2909:%.*]], label [[COND_FALSE2910:%.*]]
33111 // SIMD-ONLY0:       cond.true2909:
33112 // SIMD-ONLY0-NEXT:    [[TMP1336:%.*]] = load i32, ptr [[UID]], align 4
33113 // SIMD-ONLY0-NEXT:    br label [[COND_END2911:%.*]]
33114 // SIMD-ONLY0:       cond.false2910:
33115 // SIMD-ONLY0-NEXT:    [[TMP1337:%.*]] = load i32, ptr [[UIX]], align 4
33116 // SIMD-ONLY0-NEXT:    br label [[COND_END2911]]
33117 // SIMD-ONLY0:       cond.end2911:
33118 // SIMD-ONLY0-NEXT:    [[COND2912:%.*]] = phi i32 [ [[TMP1336]], [[COND_TRUE2909]] ], [ [[TMP1337]], [[COND_FALSE2910]] ]
33119 // SIMD-ONLY0-NEXT:    store i32 [[COND2912]], ptr [[UIX]], align 4
33120 // SIMD-ONLY0-NEXT:    [[TMP1338:%.*]] = load i32, ptr [[UIX]], align 4
33121 // SIMD-ONLY0-NEXT:    [[TMP1339:%.*]] = load i32, ptr [[UIE]], align 4
33122 // SIMD-ONLY0-NEXT:    [[CMP2913:%.*]] = icmp eq i32 [[TMP1338]], [[TMP1339]]
33123 // SIMD-ONLY0-NEXT:    br i1 [[CMP2913]], label [[IF_THEN2915:%.*]], label [[IF_END2916:%.*]]
33124 // SIMD-ONLY0:       if.then2915:
33125 // SIMD-ONLY0-NEXT:    [[TMP1340:%.*]] = load i32, ptr [[UID]], align 4
33126 // SIMD-ONLY0-NEXT:    store i32 [[TMP1340]], ptr [[UIX]], align 4
33127 // SIMD-ONLY0-NEXT:    br label [[IF_END2916]]
33128 // SIMD-ONLY0:       if.end2916:
33129 // SIMD-ONLY0-NEXT:    [[TMP1341:%.*]] = load i32, ptr [[UIE]], align 4
33130 // SIMD-ONLY0-NEXT:    [[TMP1342:%.*]] = load i32, ptr [[UIX]], align 4
33131 // SIMD-ONLY0-NEXT:    [[CMP2917:%.*]] = icmp eq i32 [[TMP1341]], [[TMP1342]]
33132 // SIMD-ONLY0-NEXT:    br i1 [[CMP2917]], label [[IF_THEN2919:%.*]], label [[IF_END2920:%.*]]
33133 // SIMD-ONLY0:       if.then2919:
33134 // SIMD-ONLY0-NEXT:    [[TMP1343:%.*]] = load i32, ptr [[UID]], align 4
33135 // SIMD-ONLY0-NEXT:    store i32 [[TMP1343]], ptr [[UIX]], align 4
33136 // SIMD-ONLY0-NEXT:    br label [[IF_END2920]]
33137 // SIMD-ONLY0:       if.end2920:
33138 // SIMD-ONLY0-NEXT:    [[TMP1344:%.*]] = load i32, ptr [[IX]], align 4
33139 // SIMD-ONLY0-NEXT:    [[TMP1345:%.*]] = load i32, ptr [[IE]], align 4
33140 // SIMD-ONLY0-NEXT:    [[CMP2921:%.*]] = icmp sgt i32 [[TMP1344]], [[TMP1345]]
33141 // SIMD-ONLY0-NEXT:    br i1 [[CMP2921]], label [[COND_TRUE2923:%.*]], label [[COND_FALSE2924:%.*]]
33142 // SIMD-ONLY0:       cond.true2923:
33143 // SIMD-ONLY0-NEXT:    [[TMP1346:%.*]] = load i32, ptr [[IE]], align 4
33144 // SIMD-ONLY0-NEXT:    br label [[COND_END2925:%.*]]
33145 // SIMD-ONLY0:       cond.false2924:
33146 // SIMD-ONLY0-NEXT:    [[TMP1347:%.*]] = load i32, ptr [[IX]], align 4
33147 // SIMD-ONLY0-NEXT:    br label [[COND_END2925]]
33148 // SIMD-ONLY0:       cond.end2925:
33149 // SIMD-ONLY0-NEXT:    [[COND2926:%.*]] = phi i32 [ [[TMP1346]], [[COND_TRUE2923]] ], [ [[TMP1347]], [[COND_FALSE2924]] ]
33150 // SIMD-ONLY0-NEXT:    store i32 [[COND2926]], ptr [[IX]], align 4
33151 // SIMD-ONLY0-NEXT:    [[TMP1348:%.*]] = load i32, ptr [[IX]], align 4
33152 // SIMD-ONLY0-NEXT:    [[TMP1349:%.*]] = load i32, ptr [[IE]], align 4
33153 // SIMD-ONLY0-NEXT:    [[CMP2927:%.*]] = icmp slt i32 [[TMP1348]], [[TMP1349]]
33154 // SIMD-ONLY0-NEXT:    br i1 [[CMP2927]], label [[COND_TRUE2929:%.*]], label [[COND_FALSE2930:%.*]]
33155 // SIMD-ONLY0:       cond.true2929:
33156 // SIMD-ONLY0-NEXT:    [[TMP1350:%.*]] = load i32, ptr [[IE]], align 4
33157 // SIMD-ONLY0-NEXT:    br label [[COND_END2931:%.*]]
33158 // SIMD-ONLY0:       cond.false2930:
33159 // SIMD-ONLY0-NEXT:    [[TMP1351:%.*]] = load i32, ptr [[IX]], align 4
33160 // SIMD-ONLY0-NEXT:    br label [[COND_END2931]]
33161 // SIMD-ONLY0:       cond.end2931:
33162 // SIMD-ONLY0-NEXT:    [[COND2932:%.*]] = phi i32 [ [[TMP1350]], [[COND_TRUE2929]] ], [ [[TMP1351]], [[COND_FALSE2930]] ]
33163 // SIMD-ONLY0-NEXT:    store i32 [[COND2932]], ptr [[IX]], align 4
33164 // SIMD-ONLY0-NEXT:    [[TMP1352:%.*]] = load i32, ptr [[IE]], align 4
33165 // SIMD-ONLY0-NEXT:    [[TMP1353:%.*]] = load i32, ptr [[IX]], align 4
33166 // SIMD-ONLY0-NEXT:    [[CMP2933:%.*]] = icmp sgt i32 [[TMP1352]], [[TMP1353]]
33167 // SIMD-ONLY0-NEXT:    br i1 [[CMP2933]], label [[COND_TRUE2935:%.*]], label [[COND_FALSE2936:%.*]]
33168 // SIMD-ONLY0:       cond.true2935:
33169 // SIMD-ONLY0-NEXT:    [[TMP1354:%.*]] = load i32, ptr [[IE]], align 4
33170 // SIMD-ONLY0-NEXT:    br label [[COND_END2937:%.*]]
33171 // SIMD-ONLY0:       cond.false2936:
33172 // SIMD-ONLY0-NEXT:    [[TMP1355:%.*]] = load i32, ptr [[IX]], align 4
33173 // SIMD-ONLY0-NEXT:    br label [[COND_END2937]]
33174 // SIMD-ONLY0:       cond.end2937:
33175 // SIMD-ONLY0-NEXT:    [[COND2938:%.*]] = phi i32 [ [[TMP1354]], [[COND_TRUE2935]] ], [ [[TMP1355]], [[COND_FALSE2936]] ]
33176 // SIMD-ONLY0-NEXT:    store i32 [[COND2938]], ptr [[IX]], align 4
33177 // SIMD-ONLY0-NEXT:    [[TMP1356:%.*]] = load i32, ptr [[IE]], align 4
33178 // SIMD-ONLY0-NEXT:    [[TMP1357:%.*]] = load i32, ptr [[IX]], align 4
33179 // SIMD-ONLY0-NEXT:    [[CMP2939:%.*]] = icmp slt i32 [[TMP1356]], [[TMP1357]]
33180 // SIMD-ONLY0-NEXT:    br i1 [[CMP2939]], label [[COND_TRUE2941:%.*]], label [[COND_FALSE2942:%.*]]
33181 // SIMD-ONLY0:       cond.true2941:
33182 // SIMD-ONLY0-NEXT:    [[TMP1358:%.*]] = load i32, ptr [[IE]], align 4
33183 // SIMD-ONLY0-NEXT:    br label [[COND_END2943:%.*]]
33184 // SIMD-ONLY0:       cond.false2942:
33185 // SIMD-ONLY0-NEXT:    [[TMP1359:%.*]] = load i32, ptr [[IX]], align 4
33186 // SIMD-ONLY0-NEXT:    br label [[COND_END2943]]
33187 // SIMD-ONLY0:       cond.end2943:
33188 // SIMD-ONLY0-NEXT:    [[COND2944:%.*]] = phi i32 [ [[TMP1358]], [[COND_TRUE2941]] ], [ [[TMP1359]], [[COND_FALSE2942]] ]
33189 // SIMD-ONLY0-NEXT:    store i32 [[COND2944]], ptr [[IX]], align 4
33190 // SIMD-ONLY0-NEXT:    [[TMP1360:%.*]] = load i32, ptr [[IX]], align 4
33191 // SIMD-ONLY0-NEXT:    [[TMP1361:%.*]] = load i32, ptr [[IE]], align 4
33192 // SIMD-ONLY0-NEXT:    [[CMP2945:%.*]] = icmp sgt i32 [[TMP1360]], [[TMP1361]]
33193 // SIMD-ONLY0-NEXT:    br i1 [[CMP2945]], label [[IF_THEN2947:%.*]], label [[IF_END2948:%.*]]
33194 // SIMD-ONLY0:       if.then2947:
33195 // SIMD-ONLY0-NEXT:    [[TMP1362:%.*]] = load i32, ptr [[IE]], align 4
33196 // SIMD-ONLY0-NEXT:    store i32 [[TMP1362]], ptr [[IX]], align 4
33197 // SIMD-ONLY0-NEXT:    br label [[IF_END2948]]
33198 // SIMD-ONLY0:       if.end2948:
33199 // SIMD-ONLY0-NEXT:    [[TMP1363:%.*]] = load i32, ptr [[IX]], align 4
33200 // SIMD-ONLY0-NEXT:    [[TMP1364:%.*]] = load i32, ptr [[IE]], align 4
33201 // SIMD-ONLY0-NEXT:    [[CMP2949:%.*]] = icmp slt i32 [[TMP1363]], [[TMP1364]]
33202 // SIMD-ONLY0-NEXT:    br i1 [[CMP2949]], label [[IF_THEN2951:%.*]], label [[IF_END2952:%.*]]
33203 // SIMD-ONLY0:       if.then2951:
33204 // SIMD-ONLY0-NEXT:    [[TMP1365:%.*]] = load i32, ptr [[IE]], align 4
33205 // SIMD-ONLY0-NEXT:    store i32 [[TMP1365]], ptr [[IX]], align 4
33206 // SIMD-ONLY0-NEXT:    br label [[IF_END2952]]
33207 // SIMD-ONLY0:       if.end2952:
33208 // SIMD-ONLY0-NEXT:    [[TMP1366:%.*]] = load i32, ptr [[IE]], align 4
33209 // SIMD-ONLY0-NEXT:    [[TMP1367:%.*]] = load i32, ptr [[IX]], align 4
33210 // SIMD-ONLY0-NEXT:    [[CMP2953:%.*]] = icmp sgt i32 [[TMP1366]], [[TMP1367]]
33211 // SIMD-ONLY0-NEXT:    br i1 [[CMP2953]], label [[IF_THEN2955:%.*]], label [[IF_END2956:%.*]]
33212 // SIMD-ONLY0:       if.then2955:
33213 // SIMD-ONLY0-NEXT:    [[TMP1368:%.*]] = load i32, ptr [[IE]], align 4
33214 // SIMD-ONLY0-NEXT:    store i32 [[TMP1368]], ptr [[IX]], align 4
33215 // SIMD-ONLY0-NEXT:    br label [[IF_END2956]]
33216 // SIMD-ONLY0:       if.end2956:
33217 // SIMD-ONLY0-NEXT:    [[TMP1369:%.*]] = load i32, ptr [[IE]], align 4
33218 // SIMD-ONLY0-NEXT:    [[TMP1370:%.*]] = load i32, ptr [[IX]], align 4
33219 // SIMD-ONLY0-NEXT:    [[CMP2957:%.*]] = icmp slt i32 [[TMP1369]], [[TMP1370]]
33220 // SIMD-ONLY0-NEXT:    br i1 [[CMP2957]], label [[IF_THEN2959:%.*]], label [[IF_END2960:%.*]]
33221 // SIMD-ONLY0:       if.then2959:
33222 // SIMD-ONLY0-NEXT:    [[TMP1371:%.*]] = load i32, ptr [[IE]], align 4
33223 // SIMD-ONLY0-NEXT:    store i32 [[TMP1371]], ptr [[IX]], align 4
33224 // SIMD-ONLY0-NEXT:    br label [[IF_END2960]]
33225 // SIMD-ONLY0:       if.end2960:
33226 // SIMD-ONLY0-NEXT:    [[TMP1372:%.*]] = load i32, ptr [[IX]], align 4
33227 // SIMD-ONLY0-NEXT:    [[TMP1373:%.*]] = load i32, ptr [[IE]], align 4
33228 // SIMD-ONLY0-NEXT:    [[CMP2961:%.*]] = icmp eq i32 [[TMP1372]], [[TMP1373]]
33229 // SIMD-ONLY0-NEXT:    br i1 [[CMP2961]], label [[COND_TRUE2963:%.*]], label [[COND_FALSE2964:%.*]]
33230 // SIMD-ONLY0:       cond.true2963:
33231 // SIMD-ONLY0-NEXT:    [[TMP1374:%.*]] = load i32, ptr [[ID]], align 4
33232 // SIMD-ONLY0-NEXT:    br label [[COND_END2965:%.*]]
33233 // SIMD-ONLY0:       cond.false2964:
33234 // SIMD-ONLY0-NEXT:    [[TMP1375:%.*]] = load i32, ptr [[IX]], align 4
33235 // SIMD-ONLY0-NEXT:    br label [[COND_END2965]]
33236 // SIMD-ONLY0:       cond.end2965:
33237 // SIMD-ONLY0-NEXT:    [[COND2966:%.*]] = phi i32 [ [[TMP1374]], [[COND_TRUE2963]] ], [ [[TMP1375]], [[COND_FALSE2964]] ]
33238 // SIMD-ONLY0-NEXT:    store i32 [[COND2966]], ptr [[IX]], align 4
33239 // SIMD-ONLY0-NEXT:    [[TMP1376:%.*]] = load i32, ptr [[IE]], align 4
33240 // SIMD-ONLY0-NEXT:    [[TMP1377:%.*]] = load i32, ptr [[IX]], align 4
33241 // SIMD-ONLY0-NEXT:    [[CMP2967:%.*]] = icmp eq i32 [[TMP1376]], [[TMP1377]]
33242 // SIMD-ONLY0-NEXT:    br i1 [[CMP2967]], label [[COND_TRUE2969:%.*]], label [[COND_FALSE2970:%.*]]
33243 // SIMD-ONLY0:       cond.true2969:
33244 // SIMD-ONLY0-NEXT:    [[TMP1378:%.*]] = load i32, ptr [[ID]], align 4
33245 // SIMD-ONLY0-NEXT:    br label [[COND_END2971:%.*]]
33246 // SIMD-ONLY0:       cond.false2970:
33247 // SIMD-ONLY0-NEXT:    [[TMP1379:%.*]] = load i32, ptr [[IX]], align 4
33248 // SIMD-ONLY0-NEXT:    br label [[COND_END2971]]
33249 // SIMD-ONLY0:       cond.end2971:
33250 // SIMD-ONLY0-NEXT:    [[COND2972:%.*]] = phi i32 [ [[TMP1378]], [[COND_TRUE2969]] ], [ [[TMP1379]], [[COND_FALSE2970]] ]
33251 // SIMD-ONLY0-NEXT:    store i32 [[COND2972]], ptr [[IX]], align 4
33252 // SIMD-ONLY0-NEXT:    [[TMP1380:%.*]] = load i32, ptr [[IX]], align 4
33253 // SIMD-ONLY0-NEXT:    [[TMP1381:%.*]] = load i32, ptr [[IE]], align 4
33254 // SIMD-ONLY0-NEXT:    [[CMP2973:%.*]] = icmp eq i32 [[TMP1380]], [[TMP1381]]
33255 // SIMD-ONLY0-NEXT:    br i1 [[CMP2973]], label [[IF_THEN2975:%.*]], label [[IF_END2976:%.*]]
33256 // SIMD-ONLY0:       if.then2975:
33257 // SIMD-ONLY0-NEXT:    [[TMP1382:%.*]] = load i32, ptr [[ID]], align 4
33258 // SIMD-ONLY0-NEXT:    store i32 [[TMP1382]], ptr [[IX]], align 4
33259 // SIMD-ONLY0-NEXT:    br label [[IF_END2976]]
33260 // SIMD-ONLY0:       if.end2976:
33261 // SIMD-ONLY0-NEXT:    [[TMP1383:%.*]] = load i32, ptr [[IE]], align 4
33262 // SIMD-ONLY0-NEXT:    [[TMP1384:%.*]] = load i32, ptr [[IX]], align 4
33263 // SIMD-ONLY0-NEXT:    [[CMP2977:%.*]] = icmp eq i32 [[TMP1383]], [[TMP1384]]
33264 // SIMD-ONLY0-NEXT:    br i1 [[CMP2977]], label [[IF_THEN2979:%.*]], label [[IF_END2980:%.*]]
33265 // SIMD-ONLY0:       if.then2979:
33266 // SIMD-ONLY0-NEXT:    [[TMP1385:%.*]] = load i32, ptr [[ID]], align 4
33267 // SIMD-ONLY0-NEXT:    store i32 [[TMP1385]], ptr [[IX]], align 4
33268 // SIMD-ONLY0-NEXT:    br label [[IF_END2980]]
33269 // SIMD-ONLY0:       if.end2980:
33270 // SIMD-ONLY0-NEXT:    [[TMP1386:%.*]] = load i32, ptr [[UIX]], align 4
33271 // SIMD-ONLY0-NEXT:    [[TMP1387:%.*]] = load i32, ptr [[UIE]], align 4
33272 // SIMD-ONLY0-NEXT:    [[CMP2981:%.*]] = icmp ugt i32 [[TMP1386]], [[TMP1387]]
33273 // SIMD-ONLY0-NEXT:    br i1 [[CMP2981]], label [[COND_TRUE2983:%.*]], label [[COND_FALSE2984:%.*]]
33274 // SIMD-ONLY0:       cond.true2983:
33275 // SIMD-ONLY0-NEXT:    [[TMP1388:%.*]] = load i32, ptr [[UIE]], align 4
33276 // SIMD-ONLY0-NEXT:    br label [[COND_END2985:%.*]]
33277 // SIMD-ONLY0:       cond.false2984:
33278 // SIMD-ONLY0-NEXT:    [[TMP1389:%.*]] = load i32, ptr [[UIX]], align 4
33279 // SIMD-ONLY0-NEXT:    br label [[COND_END2985]]
33280 // SIMD-ONLY0:       cond.end2985:
33281 // SIMD-ONLY0-NEXT:    [[COND2986:%.*]] = phi i32 [ [[TMP1388]], [[COND_TRUE2983]] ], [ [[TMP1389]], [[COND_FALSE2984]] ]
33282 // SIMD-ONLY0-NEXT:    store i32 [[COND2986]], ptr [[UIX]], align 4
33283 // SIMD-ONLY0-NEXT:    [[TMP1390:%.*]] = load i32, ptr [[UIX]], align 4
33284 // SIMD-ONLY0-NEXT:    [[TMP1391:%.*]] = load i32, ptr [[UIE]], align 4
33285 // SIMD-ONLY0-NEXT:    [[CMP2987:%.*]] = icmp ult i32 [[TMP1390]], [[TMP1391]]
33286 // SIMD-ONLY0-NEXT:    br i1 [[CMP2987]], label [[COND_TRUE2989:%.*]], label [[COND_FALSE2990:%.*]]
33287 // SIMD-ONLY0:       cond.true2989:
33288 // SIMD-ONLY0-NEXT:    [[TMP1392:%.*]] = load i32, ptr [[UIE]], align 4
33289 // SIMD-ONLY0-NEXT:    br label [[COND_END2991:%.*]]
33290 // SIMD-ONLY0:       cond.false2990:
33291 // SIMD-ONLY0-NEXT:    [[TMP1393:%.*]] = load i32, ptr [[UIX]], align 4
33292 // SIMD-ONLY0-NEXT:    br label [[COND_END2991]]
33293 // SIMD-ONLY0:       cond.end2991:
33294 // SIMD-ONLY0-NEXT:    [[COND2992:%.*]] = phi i32 [ [[TMP1392]], [[COND_TRUE2989]] ], [ [[TMP1393]], [[COND_FALSE2990]] ]
33295 // SIMD-ONLY0-NEXT:    store i32 [[COND2992]], ptr [[UIX]], align 4
33296 // SIMD-ONLY0-NEXT:    [[TMP1394:%.*]] = load i32, ptr [[UIE]], align 4
33297 // SIMD-ONLY0-NEXT:    [[TMP1395:%.*]] = load i32, ptr [[UIX]], align 4
33298 // SIMD-ONLY0-NEXT:    [[CMP2993:%.*]] = icmp ugt i32 [[TMP1394]], [[TMP1395]]
33299 // SIMD-ONLY0-NEXT:    br i1 [[CMP2993]], label [[COND_TRUE2995:%.*]], label [[COND_FALSE2996:%.*]]
33300 // SIMD-ONLY0:       cond.true2995:
33301 // SIMD-ONLY0-NEXT:    [[TMP1396:%.*]] = load i32, ptr [[UIE]], align 4
33302 // SIMD-ONLY0-NEXT:    br label [[COND_END2997:%.*]]
33303 // SIMD-ONLY0:       cond.false2996:
33304 // SIMD-ONLY0-NEXT:    [[TMP1397:%.*]] = load i32, ptr [[UIX]], align 4
33305 // SIMD-ONLY0-NEXT:    br label [[COND_END2997]]
33306 // SIMD-ONLY0:       cond.end2997:
33307 // SIMD-ONLY0-NEXT:    [[COND2998:%.*]] = phi i32 [ [[TMP1396]], [[COND_TRUE2995]] ], [ [[TMP1397]], [[COND_FALSE2996]] ]
33308 // SIMD-ONLY0-NEXT:    store i32 [[COND2998]], ptr [[UIX]], align 4
33309 // SIMD-ONLY0-NEXT:    [[TMP1398:%.*]] = load i32, ptr [[UIE]], align 4
33310 // SIMD-ONLY0-NEXT:    [[TMP1399:%.*]] = load i32, ptr [[UIX]], align 4
33311 // SIMD-ONLY0-NEXT:    [[CMP2999:%.*]] = icmp ult i32 [[TMP1398]], [[TMP1399]]
33312 // SIMD-ONLY0-NEXT:    br i1 [[CMP2999]], label [[COND_TRUE3001:%.*]], label [[COND_FALSE3002:%.*]]
33313 // SIMD-ONLY0:       cond.true3001:
33314 // SIMD-ONLY0-NEXT:    [[TMP1400:%.*]] = load i32, ptr [[UIE]], align 4
33315 // SIMD-ONLY0-NEXT:    br label [[COND_END3003:%.*]]
33316 // SIMD-ONLY0:       cond.false3002:
33317 // SIMD-ONLY0-NEXT:    [[TMP1401:%.*]] = load i32, ptr [[UIX]], align 4
33318 // SIMD-ONLY0-NEXT:    br label [[COND_END3003]]
33319 // SIMD-ONLY0:       cond.end3003:
33320 // SIMD-ONLY0-NEXT:    [[COND3004:%.*]] = phi i32 [ [[TMP1400]], [[COND_TRUE3001]] ], [ [[TMP1401]], [[COND_FALSE3002]] ]
33321 // SIMD-ONLY0-NEXT:    store i32 [[COND3004]], ptr [[UIX]], align 4
33322 // SIMD-ONLY0-NEXT:    [[TMP1402:%.*]] = load i32, ptr [[UIX]], align 4
33323 // SIMD-ONLY0-NEXT:    [[TMP1403:%.*]] = load i32, ptr [[UIE]], align 4
33324 // SIMD-ONLY0-NEXT:    [[CMP3005:%.*]] = icmp ugt i32 [[TMP1402]], [[TMP1403]]
33325 // SIMD-ONLY0-NEXT:    br i1 [[CMP3005]], label [[IF_THEN3007:%.*]], label [[IF_END3008:%.*]]
33326 // SIMD-ONLY0:       if.then3007:
33327 // SIMD-ONLY0-NEXT:    [[TMP1404:%.*]] = load i32, ptr [[UIE]], align 4
33328 // SIMD-ONLY0-NEXT:    store i32 [[TMP1404]], ptr [[UIX]], align 4
33329 // SIMD-ONLY0-NEXT:    br label [[IF_END3008]]
33330 // SIMD-ONLY0:       if.end3008:
33331 // SIMD-ONLY0-NEXT:    [[TMP1405:%.*]] = load i32, ptr [[UIX]], align 4
33332 // SIMD-ONLY0-NEXT:    [[TMP1406:%.*]] = load i32, ptr [[UIE]], align 4
33333 // SIMD-ONLY0-NEXT:    [[CMP3009:%.*]] = icmp ult i32 [[TMP1405]], [[TMP1406]]
33334 // SIMD-ONLY0-NEXT:    br i1 [[CMP3009]], label [[IF_THEN3011:%.*]], label [[IF_END3012:%.*]]
33335 // SIMD-ONLY0:       if.then3011:
33336 // SIMD-ONLY0-NEXT:    [[TMP1407:%.*]] = load i32, ptr [[UIE]], align 4
33337 // SIMD-ONLY0-NEXT:    store i32 [[TMP1407]], ptr [[UIX]], align 4
33338 // SIMD-ONLY0-NEXT:    br label [[IF_END3012]]
33339 // SIMD-ONLY0:       if.end3012:
33340 // SIMD-ONLY0-NEXT:    [[TMP1408:%.*]] = load i32, ptr [[UIE]], align 4
33341 // SIMD-ONLY0-NEXT:    [[TMP1409:%.*]] = load i32, ptr [[UIX]], align 4
33342 // SIMD-ONLY0-NEXT:    [[CMP3013:%.*]] = icmp ugt i32 [[TMP1408]], [[TMP1409]]
33343 // SIMD-ONLY0-NEXT:    br i1 [[CMP3013]], label [[IF_THEN3015:%.*]], label [[IF_END3016:%.*]]
33344 // SIMD-ONLY0:       if.then3015:
33345 // SIMD-ONLY0-NEXT:    [[TMP1410:%.*]] = load i32, ptr [[UIE]], align 4
33346 // SIMD-ONLY0-NEXT:    store i32 [[TMP1410]], ptr [[UIX]], align 4
33347 // SIMD-ONLY0-NEXT:    br label [[IF_END3016]]
33348 // SIMD-ONLY0:       if.end3016:
33349 // SIMD-ONLY0-NEXT:    [[TMP1411:%.*]] = load i32, ptr [[UIE]], align 4
33350 // SIMD-ONLY0-NEXT:    [[TMP1412:%.*]] = load i32, ptr [[UIX]], align 4
33351 // SIMD-ONLY0-NEXT:    [[CMP3017:%.*]] = icmp ult i32 [[TMP1411]], [[TMP1412]]
33352 // SIMD-ONLY0-NEXT:    br i1 [[CMP3017]], label [[IF_THEN3019:%.*]], label [[IF_END3020:%.*]]
33353 // SIMD-ONLY0:       if.then3019:
33354 // SIMD-ONLY0-NEXT:    [[TMP1413:%.*]] = load i32, ptr [[UIE]], align 4
33355 // SIMD-ONLY0-NEXT:    store i32 [[TMP1413]], ptr [[UIX]], align 4
33356 // SIMD-ONLY0-NEXT:    br label [[IF_END3020]]
33357 // SIMD-ONLY0:       if.end3020:
33358 // SIMD-ONLY0-NEXT:    [[TMP1414:%.*]] = load i32, ptr [[UIX]], align 4
33359 // SIMD-ONLY0-NEXT:    [[TMP1415:%.*]] = load i32, ptr [[UIE]], align 4
33360 // SIMD-ONLY0-NEXT:    [[CMP3021:%.*]] = icmp eq i32 [[TMP1414]], [[TMP1415]]
33361 // SIMD-ONLY0-NEXT:    br i1 [[CMP3021]], label [[COND_TRUE3023:%.*]], label [[COND_FALSE3024:%.*]]
33362 // SIMD-ONLY0:       cond.true3023:
33363 // SIMD-ONLY0-NEXT:    [[TMP1416:%.*]] = load i32, ptr [[UID]], align 4
33364 // SIMD-ONLY0-NEXT:    br label [[COND_END3025:%.*]]
33365 // SIMD-ONLY0:       cond.false3024:
33366 // SIMD-ONLY0-NEXT:    [[TMP1417:%.*]] = load i32, ptr [[UIX]], align 4
33367 // SIMD-ONLY0-NEXT:    br label [[COND_END3025]]
33368 // SIMD-ONLY0:       cond.end3025:
33369 // SIMD-ONLY0-NEXT:    [[COND3026:%.*]] = phi i32 [ [[TMP1416]], [[COND_TRUE3023]] ], [ [[TMP1417]], [[COND_FALSE3024]] ]
33370 // SIMD-ONLY0-NEXT:    store i32 [[COND3026]], ptr [[UIX]], align 4
33371 // SIMD-ONLY0-NEXT:    [[TMP1418:%.*]] = load i32, ptr [[UIE]], align 4
33372 // SIMD-ONLY0-NEXT:    [[TMP1419:%.*]] = load i32, ptr [[UIX]], align 4
33373 // SIMD-ONLY0-NEXT:    [[CMP3027:%.*]] = icmp eq i32 [[TMP1418]], [[TMP1419]]
33374 // SIMD-ONLY0-NEXT:    br i1 [[CMP3027]], label [[COND_TRUE3029:%.*]], label [[COND_FALSE3030:%.*]]
33375 // SIMD-ONLY0:       cond.true3029:
33376 // SIMD-ONLY0-NEXT:    [[TMP1420:%.*]] = load i32, ptr [[UID]], align 4
33377 // SIMD-ONLY0-NEXT:    br label [[COND_END3031:%.*]]
33378 // SIMD-ONLY0:       cond.false3030:
33379 // SIMD-ONLY0-NEXT:    [[TMP1421:%.*]] = load i32, ptr [[UIX]], align 4
33380 // SIMD-ONLY0-NEXT:    br label [[COND_END3031]]
33381 // SIMD-ONLY0:       cond.end3031:
33382 // SIMD-ONLY0-NEXT:    [[COND3032:%.*]] = phi i32 [ [[TMP1420]], [[COND_TRUE3029]] ], [ [[TMP1421]], [[COND_FALSE3030]] ]
33383 // SIMD-ONLY0-NEXT:    store i32 [[COND3032]], ptr [[UIX]], align 4
33384 // SIMD-ONLY0-NEXT:    [[TMP1422:%.*]] = load i32, ptr [[UIX]], align 4
33385 // SIMD-ONLY0-NEXT:    [[TMP1423:%.*]] = load i32, ptr [[UIE]], align 4
33386 // SIMD-ONLY0-NEXT:    [[CMP3033:%.*]] = icmp eq i32 [[TMP1422]], [[TMP1423]]
33387 // SIMD-ONLY0-NEXT:    br i1 [[CMP3033]], label [[IF_THEN3035:%.*]], label [[IF_END3036:%.*]]
33388 // SIMD-ONLY0:       if.then3035:
33389 // SIMD-ONLY0-NEXT:    [[TMP1424:%.*]] = load i32, ptr [[UID]], align 4
33390 // SIMD-ONLY0-NEXT:    store i32 [[TMP1424]], ptr [[UIX]], align 4
33391 // SIMD-ONLY0-NEXT:    br label [[IF_END3036]]
33392 // SIMD-ONLY0:       if.end3036:
33393 // SIMD-ONLY0-NEXT:    [[TMP1425:%.*]] = load i32, ptr [[UIE]], align 4
33394 // SIMD-ONLY0-NEXT:    [[TMP1426:%.*]] = load i32, ptr [[UIX]], align 4
33395 // SIMD-ONLY0-NEXT:    [[CMP3037:%.*]] = icmp eq i32 [[TMP1425]], [[TMP1426]]
33396 // SIMD-ONLY0-NEXT:    br i1 [[CMP3037]], label [[IF_THEN3039:%.*]], label [[IF_END3040:%.*]]
33397 // SIMD-ONLY0:       if.then3039:
33398 // SIMD-ONLY0-NEXT:    [[TMP1427:%.*]] = load i32, ptr [[UID]], align 4
33399 // SIMD-ONLY0-NEXT:    store i32 [[TMP1427]], ptr [[UIX]], align 4
33400 // SIMD-ONLY0-NEXT:    br label [[IF_END3040]]
33401 // SIMD-ONLY0:       if.end3040:
33402 // SIMD-ONLY0-NEXT:    [[TMP1428:%.*]] = load i32, ptr [[IX]], align 4
33403 // SIMD-ONLY0-NEXT:    [[TMP1429:%.*]] = load i32, ptr [[IE]], align 4
33404 // SIMD-ONLY0-NEXT:    [[CMP3041:%.*]] = icmp sgt i32 [[TMP1428]], [[TMP1429]]
33405 // SIMD-ONLY0-NEXT:    br i1 [[CMP3041]], label [[COND_TRUE3043:%.*]], label [[COND_FALSE3044:%.*]]
33406 // SIMD-ONLY0:       cond.true3043:
33407 // SIMD-ONLY0-NEXT:    [[TMP1430:%.*]] = load i32, ptr [[IE]], align 4
33408 // SIMD-ONLY0-NEXT:    br label [[COND_END3045:%.*]]
33409 // SIMD-ONLY0:       cond.false3044:
33410 // SIMD-ONLY0-NEXT:    [[TMP1431:%.*]] = load i32, ptr [[IX]], align 4
33411 // SIMD-ONLY0-NEXT:    br label [[COND_END3045]]
33412 // SIMD-ONLY0:       cond.end3045:
33413 // SIMD-ONLY0-NEXT:    [[COND3046:%.*]] = phi i32 [ [[TMP1430]], [[COND_TRUE3043]] ], [ [[TMP1431]], [[COND_FALSE3044]] ]
33414 // SIMD-ONLY0-NEXT:    store i32 [[COND3046]], ptr [[IX]], align 4
33415 // SIMD-ONLY0-NEXT:    [[TMP1432:%.*]] = load i32, ptr [[IX]], align 4
33416 // SIMD-ONLY0-NEXT:    [[TMP1433:%.*]] = load i32, ptr [[IE]], align 4
33417 // SIMD-ONLY0-NEXT:    [[CMP3047:%.*]] = icmp slt i32 [[TMP1432]], [[TMP1433]]
33418 // SIMD-ONLY0-NEXT:    br i1 [[CMP3047]], label [[COND_TRUE3049:%.*]], label [[COND_FALSE3050:%.*]]
33419 // SIMD-ONLY0:       cond.true3049:
33420 // SIMD-ONLY0-NEXT:    [[TMP1434:%.*]] = load i32, ptr [[IE]], align 4
33421 // SIMD-ONLY0-NEXT:    br label [[COND_END3051:%.*]]
33422 // SIMD-ONLY0:       cond.false3050:
33423 // SIMD-ONLY0-NEXT:    [[TMP1435:%.*]] = load i32, ptr [[IX]], align 4
33424 // SIMD-ONLY0-NEXT:    br label [[COND_END3051]]
33425 // SIMD-ONLY0:       cond.end3051:
33426 // SIMD-ONLY0-NEXT:    [[COND3052:%.*]] = phi i32 [ [[TMP1434]], [[COND_TRUE3049]] ], [ [[TMP1435]], [[COND_FALSE3050]] ]
33427 // SIMD-ONLY0-NEXT:    store i32 [[COND3052]], ptr [[IX]], align 4
33428 // SIMD-ONLY0-NEXT:    [[TMP1436:%.*]] = load i32, ptr [[IE]], align 4
33429 // SIMD-ONLY0-NEXT:    [[TMP1437:%.*]] = load i32, ptr [[IX]], align 4
33430 // SIMD-ONLY0-NEXT:    [[CMP3053:%.*]] = icmp sgt i32 [[TMP1436]], [[TMP1437]]
33431 // SIMD-ONLY0-NEXT:    br i1 [[CMP3053]], label [[COND_TRUE3055:%.*]], label [[COND_FALSE3056:%.*]]
33432 // SIMD-ONLY0:       cond.true3055:
33433 // SIMD-ONLY0-NEXT:    [[TMP1438:%.*]] = load i32, ptr [[IE]], align 4
33434 // SIMD-ONLY0-NEXT:    br label [[COND_END3057:%.*]]
33435 // SIMD-ONLY0:       cond.false3056:
33436 // SIMD-ONLY0-NEXT:    [[TMP1439:%.*]] = load i32, ptr [[IX]], align 4
33437 // SIMD-ONLY0-NEXT:    br label [[COND_END3057]]
33438 // SIMD-ONLY0:       cond.end3057:
33439 // SIMD-ONLY0-NEXT:    [[COND3058:%.*]] = phi i32 [ [[TMP1438]], [[COND_TRUE3055]] ], [ [[TMP1439]], [[COND_FALSE3056]] ]
33440 // SIMD-ONLY0-NEXT:    store i32 [[COND3058]], ptr [[IX]], align 4
33441 // SIMD-ONLY0-NEXT:    [[TMP1440:%.*]] = load i32, ptr [[IE]], align 4
33442 // SIMD-ONLY0-NEXT:    [[TMP1441:%.*]] = load i32, ptr [[IX]], align 4
33443 // SIMD-ONLY0-NEXT:    [[CMP3059:%.*]] = icmp slt i32 [[TMP1440]], [[TMP1441]]
33444 // SIMD-ONLY0-NEXT:    br i1 [[CMP3059]], label [[COND_TRUE3061:%.*]], label [[COND_FALSE3062:%.*]]
33445 // SIMD-ONLY0:       cond.true3061:
33446 // SIMD-ONLY0-NEXT:    [[TMP1442:%.*]] = load i32, ptr [[IE]], align 4
33447 // SIMD-ONLY0-NEXT:    br label [[COND_END3063:%.*]]
33448 // SIMD-ONLY0:       cond.false3062:
33449 // SIMD-ONLY0-NEXT:    [[TMP1443:%.*]] = load i32, ptr [[IX]], align 4
33450 // SIMD-ONLY0-NEXT:    br label [[COND_END3063]]
33451 // SIMD-ONLY0:       cond.end3063:
33452 // SIMD-ONLY0-NEXT:    [[COND3064:%.*]] = phi i32 [ [[TMP1442]], [[COND_TRUE3061]] ], [ [[TMP1443]], [[COND_FALSE3062]] ]
33453 // SIMD-ONLY0-NEXT:    store i32 [[COND3064]], ptr [[IX]], align 4
33454 // SIMD-ONLY0-NEXT:    [[TMP1444:%.*]] = load i32, ptr [[IX]], align 4
33455 // SIMD-ONLY0-NEXT:    [[TMP1445:%.*]] = load i32, ptr [[IE]], align 4
33456 // SIMD-ONLY0-NEXT:    [[CMP3065:%.*]] = icmp sgt i32 [[TMP1444]], [[TMP1445]]
33457 // SIMD-ONLY0-NEXT:    br i1 [[CMP3065]], label [[IF_THEN3067:%.*]], label [[IF_END3068:%.*]]
33458 // SIMD-ONLY0:       if.then3067:
33459 // SIMD-ONLY0-NEXT:    [[TMP1446:%.*]] = load i32, ptr [[IE]], align 4
33460 // SIMD-ONLY0-NEXT:    store i32 [[TMP1446]], ptr [[IX]], align 4
33461 // SIMD-ONLY0-NEXT:    br label [[IF_END3068]]
33462 // SIMD-ONLY0:       if.end3068:
33463 // SIMD-ONLY0-NEXT:    [[TMP1447:%.*]] = load i32, ptr [[IX]], align 4
33464 // SIMD-ONLY0-NEXT:    [[TMP1448:%.*]] = load i32, ptr [[IE]], align 4
33465 // SIMD-ONLY0-NEXT:    [[CMP3069:%.*]] = icmp slt i32 [[TMP1447]], [[TMP1448]]
33466 // SIMD-ONLY0-NEXT:    br i1 [[CMP3069]], label [[IF_THEN3071:%.*]], label [[IF_END3072:%.*]]
33467 // SIMD-ONLY0:       if.then3071:
33468 // SIMD-ONLY0-NEXT:    [[TMP1449:%.*]] = load i32, ptr [[IE]], align 4
33469 // SIMD-ONLY0-NEXT:    store i32 [[TMP1449]], ptr [[IX]], align 4
33470 // SIMD-ONLY0-NEXT:    br label [[IF_END3072]]
33471 // SIMD-ONLY0:       if.end3072:
33472 // SIMD-ONLY0-NEXT:    [[TMP1450:%.*]] = load i32, ptr [[IE]], align 4
33473 // SIMD-ONLY0-NEXT:    [[TMP1451:%.*]] = load i32, ptr [[IX]], align 4
33474 // SIMD-ONLY0-NEXT:    [[CMP3073:%.*]] = icmp sgt i32 [[TMP1450]], [[TMP1451]]
33475 // SIMD-ONLY0-NEXT:    br i1 [[CMP3073]], label [[IF_THEN3075:%.*]], label [[IF_END3076:%.*]]
33476 // SIMD-ONLY0:       if.then3075:
33477 // SIMD-ONLY0-NEXT:    [[TMP1452:%.*]] = load i32, ptr [[IE]], align 4
33478 // SIMD-ONLY0-NEXT:    store i32 [[TMP1452]], ptr [[IX]], align 4
33479 // SIMD-ONLY0-NEXT:    br label [[IF_END3076]]
33480 // SIMD-ONLY0:       if.end3076:
33481 // SIMD-ONLY0-NEXT:    [[TMP1453:%.*]] = load i32, ptr [[IE]], align 4
33482 // SIMD-ONLY0-NEXT:    [[TMP1454:%.*]] = load i32, ptr [[IX]], align 4
33483 // SIMD-ONLY0-NEXT:    [[CMP3077:%.*]] = icmp slt i32 [[TMP1453]], [[TMP1454]]
33484 // SIMD-ONLY0-NEXT:    br i1 [[CMP3077]], label [[IF_THEN3079:%.*]], label [[IF_END3080:%.*]]
33485 // SIMD-ONLY0:       if.then3079:
33486 // SIMD-ONLY0-NEXT:    [[TMP1455:%.*]] = load i32, ptr [[IE]], align 4
33487 // SIMD-ONLY0-NEXT:    store i32 [[TMP1455]], ptr [[IX]], align 4
33488 // SIMD-ONLY0-NEXT:    br label [[IF_END3080]]
33489 // SIMD-ONLY0:       if.end3080:
33490 // SIMD-ONLY0-NEXT:    [[TMP1456:%.*]] = load i32, ptr [[IX]], align 4
33491 // SIMD-ONLY0-NEXT:    [[TMP1457:%.*]] = load i32, ptr [[IE]], align 4
33492 // SIMD-ONLY0-NEXT:    [[CMP3081:%.*]] = icmp eq i32 [[TMP1456]], [[TMP1457]]
33493 // SIMD-ONLY0-NEXT:    br i1 [[CMP3081]], label [[COND_TRUE3083:%.*]], label [[COND_FALSE3084:%.*]]
33494 // SIMD-ONLY0:       cond.true3083:
33495 // SIMD-ONLY0-NEXT:    [[TMP1458:%.*]] = load i32, ptr [[ID]], align 4
33496 // SIMD-ONLY0-NEXT:    br label [[COND_END3085:%.*]]
33497 // SIMD-ONLY0:       cond.false3084:
33498 // SIMD-ONLY0-NEXT:    [[TMP1459:%.*]] = load i32, ptr [[IX]], align 4
33499 // SIMD-ONLY0-NEXT:    br label [[COND_END3085]]
33500 // SIMD-ONLY0:       cond.end3085:
33501 // SIMD-ONLY0-NEXT:    [[COND3086:%.*]] = phi i32 [ [[TMP1458]], [[COND_TRUE3083]] ], [ [[TMP1459]], [[COND_FALSE3084]] ]
33502 // SIMD-ONLY0-NEXT:    store i32 [[COND3086]], ptr [[IX]], align 4
33503 // SIMD-ONLY0-NEXT:    [[TMP1460:%.*]] = load i32, ptr [[IE]], align 4
33504 // SIMD-ONLY0-NEXT:    [[TMP1461:%.*]] = load i32, ptr [[IX]], align 4
33505 // SIMD-ONLY0-NEXT:    [[CMP3087:%.*]] = icmp eq i32 [[TMP1460]], [[TMP1461]]
33506 // SIMD-ONLY0-NEXT:    br i1 [[CMP3087]], label [[COND_TRUE3089:%.*]], label [[COND_FALSE3090:%.*]]
33507 // SIMD-ONLY0:       cond.true3089:
33508 // SIMD-ONLY0-NEXT:    [[TMP1462:%.*]] = load i32, ptr [[ID]], align 4
33509 // SIMD-ONLY0-NEXT:    br label [[COND_END3091:%.*]]
33510 // SIMD-ONLY0:       cond.false3090:
33511 // SIMD-ONLY0-NEXT:    [[TMP1463:%.*]] = load i32, ptr [[IX]], align 4
33512 // SIMD-ONLY0-NEXT:    br label [[COND_END3091]]
33513 // SIMD-ONLY0:       cond.end3091:
33514 // SIMD-ONLY0-NEXT:    [[COND3092:%.*]] = phi i32 [ [[TMP1462]], [[COND_TRUE3089]] ], [ [[TMP1463]], [[COND_FALSE3090]] ]
33515 // SIMD-ONLY0-NEXT:    store i32 [[COND3092]], ptr [[IX]], align 4
33516 // SIMD-ONLY0-NEXT:    [[TMP1464:%.*]] = load i32, ptr [[IX]], align 4
33517 // SIMD-ONLY0-NEXT:    [[TMP1465:%.*]] = load i32, ptr [[IE]], align 4
33518 // SIMD-ONLY0-NEXT:    [[CMP3093:%.*]] = icmp eq i32 [[TMP1464]], [[TMP1465]]
33519 // SIMD-ONLY0-NEXT:    br i1 [[CMP3093]], label [[IF_THEN3095:%.*]], label [[IF_END3096:%.*]]
33520 // SIMD-ONLY0:       if.then3095:
33521 // SIMD-ONLY0-NEXT:    [[TMP1466:%.*]] = load i32, ptr [[ID]], align 4
33522 // SIMD-ONLY0-NEXT:    store i32 [[TMP1466]], ptr [[IX]], align 4
33523 // SIMD-ONLY0-NEXT:    br label [[IF_END3096]]
33524 // SIMD-ONLY0:       if.end3096:
33525 // SIMD-ONLY0-NEXT:    [[TMP1467:%.*]] = load i32, ptr [[IE]], align 4
33526 // SIMD-ONLY0-NEXT:    [[TMP1468:%.*]] = load i32, ptr [[IX]], align 4
33527 // SIMD-ONLY0-NEXT:    [[CMP3097:%.*]] = icmp eq i32 [[TMP1467]], [[TMP1468]]
33528 // SIMD-ONLY0-NEXT:    br i1 [[CMP3097]], label [[IF_THEN3099:%.*]], label [[IF_END3100:%.*]]
33529 // SIMD-ONLY0:       if.then3099:
33530 // SIMD-ONLY0-NEXT:    [[TMP1469:%.*]] = load i32, ptr [[ID]], align 4
33531 // SIMD-ONLY0-NEXT:    store i32 [[TMP1469]], ptr [[IX]], align 4
33532 // SIMD-ONLY0-NEXT:    br label [[IF_END3100]]
33533 // SIMD-ONLY0:       if.end3100:
33534 // SIMD-ONLY0-NEXT:    [[TMP1470:%.*]] = load i32, ptr [[UIX]], align 4
33535 // SIMD-ONLY0-NEXT:    [[TMP1471:%.*]] = load i32, ptr [[UIE]], align 4
33536 // SIMD-ONLY0-NEXT:    [[CMP3101:%.*]] = icmp ugt i32 [[TMP1470]], [[TMP1471]]
33537 // SIMD-ONLY0-NEXT:    br i1 [[CMP3101]], label [[COND_TRUE3103:%.*]], label [[COND_FALSE3104:%.*]]
33538 // SIMD-ONLY0:       cond.true3103:
33539 // SIMD-ONLY0-NEXT:    [[TMP1472:%.*]] = load i32, ptr [[UIE]], align 4
33540 // SIMD-ONLY0-NEXT:    br label [[COND_END3105:%.*]]
33541 // SIMD-ONLY0:       cond.false3104:
33542 // SIMD-ONLY0-NEXT:    [[TMP1473:%.*]] = load i32, ptr [[UIX]], align 4
33543 // SIMD-ONLY0-NEXT:    br label [[COND_END3105]]
33544 // SIMD-ONLY0:       cond.end3105:
33545 // SIMD-ONLY0-NEXT:    [[COND3106:%.*]] = phi i32 [ [[TMP1472]], [[COND_TRUE3103]] ], [ [[TMP1473]], [[COND_FALSE3104]] ]
33546 // SIMD-ONLY0-NEXT:    store i32 [[COND3106]], ptr [[UIX]], align 4
33547 // SIMD-ONLY0-NEXT:    [[TMP1474:%.*]] = load i32, ptr [[UIX]], align 4
33548 // SIMD-ONLY0-NEXT:    [[TMP1475:%.*]] = load i32, ptr [[UIE]], align 4
33549 // SIMD-ONLY0-NEXT:    [[CMP3107:%.*]] = icmp ult i32 [[TMP1474]], [[TMP1475]]
33550 // SIMD-ONLY0-NEXT:    br i1 [[CMP3107]], label [[COND_TRUE3109:%.*]], label [[COND_FALSE3110:%.*]]
33551 // SIMD-ONLY0:       cond.true3109:
33552 // SIMD-ONLY0-NEXT:    [[TMP1476:%.*]] = load i32, ptr [[UIE]], align 4
33553 // SIMD-ONLY0-NEXT:    br label [[COND_END3111:%.*]]
33554 // SIMD-ONLY0:       cond.false3110:
33555 // SIMD-ONLY0-NEXT:    [[TMP1477:%.*]] = load i32, ptr [[UIX]], align 4
33556 // SIMD-ONLY0-NEXT:    br label [[COND_END3111]]
33557 // SIMD-ONLY0:       cond.end3111:
33558 // SIMD-ONLY0-NEXT:    [[COND3112:%.*]] = phi i32 [ [[TMP1476]], [[COND_TRUE3109]] ], [ [[TMP1477]], [[COND_FALSE3110]] ]
33559 // SIMD-ONLY0-NEXT:    store i32 [[COND3112]], ptr [[UIX]], align 4
33560 // SIMD-ONLY0-NEXT:    [[TMP1478:%.*]] = load i32, ptr [[UIE]], align 4
33561 // SIMD-ONLY0-NEXT:    [[TMP1479:%.*]] = load i32, ptr [[UIX]], align 4
33562 // SIMD-ONLY0-NEXT:    [[CMP3113:%.*]] = icmp ugt i32 [[TMP1478]], [[TMP1479]]
33563 // SIMD-ONLY0-NEXT:    br i1 [[CMP3113]], label [[COND_TRUE3115:%.*]], label [[COND_FALSE3116:%.*]]
33564 // SIMD-ONLY0:       cond.true3115:
33565 // SIMD-ONLY0-NEXT:    [[TMP1480:%.*]] = load i32, ptr [[UIE]], align 4
33566 // SIMD-ONLY0-NEXT:    br label [[COND_END3117:%.*]]
33567 // SIMD-ONLY0:       cond.false3116:
33568 // SIMD-ONLY0-NEXT:    [[TMP1481:%.*]] = load i32, ptr [[UIX]], align 4
33569 // SIMD-ONLY0-NEXT:    br label [[COND_END3117]]
33570 // SIMD-ONLY0:       cond.end3117:
33571 // SIMD-ONLY0-NEXT:    [[COND3118:%.*]] = phi i32 [ [[TMP1480]], [[COND_TRUE3115]] ], [ [[TMP1481]], [[COND_FALSE3116]] ]
33572 // SIMD-ONLY0-NEXT:    store i32 [[COND3118]], ptr [[UIX]], align 4
33573 // SIMD-ONLY0-NEXT:    [[TMP1482:%.*]] = load i32, ptr [[UIE]], align 4
33574 // SIMD-ONLY0-NEXT:    [[TMP1483:%.*]] = load i32, ptr [[UIX]], align 4
33575 // SIMD-ONLY0-NEXT:    [[CMP3119:%.*]] = icmp ult i32 [[TMP1482]], [[TMP1483]]
33576 // SIMD-ONLY0-NEXT:    br i1 [[CMP3119]], label [[COND_TRUE3121:%.*]], label [[COND_FALSE3122:%.*]]
33577 // SIMD-ONLY0:       cond.true3121:
33578 // SIMD-ONLY0-NEXT:    [[TMP1484:%.*]] = load i32, ptr [[UIE]], align 4
33579 // SIMD-ONLY0-NEXT:    br label [[COND_END3123:%.*]]
33580 // SIMD-ONLY0:       cond.false3122:
33581 // SIMD-ONLY0-NEXT:    [[TMP1485:%.*]] = load i32, ptr [[UIX]], align 4
33582 // SIMD-ONLY0-NEXT:    br label [[COND_END3123]]
33583 // SIMD-ONLY0:       cond.end3123:
33584 // SIMD-ONLY0-NEXT:    [[COND3124:%.*]] = phi i32 [ [[TMP1484]], [[COND_TRUE3121]] ], [ [[TMP1485]], [[COND_FALSE3122]] ]
33585 // SIMD-ONLY0-NEXT:    store i32 [[COND3124]], ptr [[UIX]], align 4
33586 // SIMD-ONLY0-NEXT:    [[TMP1486:%.*]] = load i32, ptr [[UIX]], align 4
33587 // SIMD-ONLY0-NEXT:    [[TMP1487:%.*]] = load i32, ptr [[UIE]], align 4
33588 // SIMD-ONLY0-NEXT:    [[CMP3125:%.*]] = icmp ugt i32 [[TMP1486]], [[TMP1487]]
33589 // SIMD-ONLY0-NEXT:    br i1 [[CMP3125]], label [[IF_THEN3127:%.*]], label [[IF_END3128:%.*]]
33590 // SIMD-ONLY0:       if.then3127:
33591 // SIMD-ONLY0-NEXT:    [[TMP1488:%.*]] = load i32, ptr [[UIE]], align 4
33592 // SIMD-ONLY0-NEXT:    store i32 [[TMP1488]], ptr [[UIX]], align 4
33593 // SIMD-ONLY0-NEXT:    br label [[IF_END3128]]
33594 // SIMD-ONLY0:       if.end3128:
33595 // SIMD-ONLY0-NEXT:    [[TMP1489:%.*]] = load i32, ptr [[UIX]], align 4
33596 // SIMD-ONLY0-NEXT:    [[TMP1490:%.*]] = load i32, ptr [[UIE]], align 4
33597 // SIMD-ONLY0-NEXT:    [[CMP3129:%.*]] = icmp ult i32 [[TMP1489]], [[TMP1490]]
33598 // SIMD-ONLY0-NEXT:    br i1 [[CMP3129]], label [[IF_THEN3131:%.*]], label [[IF_END3132:%.*]]
33599 // SIMD-ONLY0:       if.then3131:
33600 // SIMD-ONLY0-NEXT:    [[TMP1491:%.*]] = load i32, ptr [[UIE]], align 4
33601 // SIMD-ONLY0-NEXT:    store i32 [[TMP1491]], ptr [[UIX]], align 4
33602 // SIMD-ONLY0-NEXT:    br label [[IF_END3132]]
33603 // SIMD-ONLY0:       if.end3132:
33604 // SIMD-ONLY0-NEXT:    [[TMP1492:%.*]] = load i32, ptr [[UIE]], align 4
33605 // SIMD-ONLY0-NEXT:    [[TMP1493:%.*]] = load i32, ptr [[UIX]], align 4
33606 // SIMD-ONLY0-NEXT:    [[CMP3133:%.*]] = icmp ugt i32 [[TMP1492]], [[TMP1493]]
33607 // SIMD-ONLY0-NEXT:    br i1 [[CMP3133]], label [[IF_THEN3135:%.*]], label [[IF_END3136:%.*]]
33608 // SIMD-ONLY0:       if.then3135:
33609 // SIMD-ONLY0-NEXT:    [[TMP1494:%.*]] = load i32, ptr [[UIE]], align 4
33610 // SIMD-ONLY0-NEXT:    store i32 [[TMP1494]], ptr [[UIX]], align 4
33611 // SIMD-ONLY0-NEXT:    br label [[IF_END3136]]
33612 // SIMD-ONLY0:       if.end3136:
33613 // SIMD-ONLY0-NEXT:    [[TMP1495:%.*]] = load i32, ptr [[UIE]], align 4
33614 // SIMD-ONLY0-NEXT:    [[TMP1496:%.*]] = load i32, ptr [[UIX]], align 4
33615 // SIMD-ONLY0-NEXT:    [[CMP3137:%.*]] = icmp ult i32 [[TMP1495]], [[TMP1496]]
33616 // SIMD-ONLY0-NEXT:    br i1 [[CMP3137]], label [[IF_THEN3139:%.*]], label [[IF_END3140:%.*]]
33617 // SIMD-ONLY0:       if.then3139:
33618 // SIMD-ONLY0-NEXT:    [[TMP1497:%.*]] = load i32, ptr [[UIE]], align 4
33619 // SIMD-ONLY0-NEXT:    store i32 [[TMP1497]], ptr [[UIX]], align 4
33620 // SIMD-ONLY0-NEXT:    br label [[IF_END3140]]
33621 // SIMD-ONLY0:       if.end3140:
33622 // SIMD-ONLY0-NEXT:    [[TMP1498:%.*]] = load i32, ptr [[UIX]], align 4
33623 // SIMD-ONLY0-NEXT:    [[TMP1499:%.*]] = load i32, ptr [[UIE]], align 4
33624 // SIMD-ONLY0-NEXT:    [[CMP3141:%.*]] = icmp eq i32 [[TMP1498]], [[TMP1499]]
33625 // SIMD-ONLY0-NEXT:    br i1 [[CMP3141]], label [[COND_TRUE3143:%.*]], label [[COND_FALSE3144:%.*]]
33626 // SIMD-ONLY0:       cond.true3143:
33627 // SIMD-ONLY0-NEXT:    [[TMP1500:%.*]] = load i32, ptr [[UID]], align 4
33628 // SIMD-ONLY0-NEXT:    br label [[COND_END3145:%.*]]
33629 // SIMD-ONLY0:       cond.false3144:
33630 // SIMD-ONLY0-NEXT:    [[TMP1501:%.*]] = load i32, ptr [[UIX]], align 4
33631 // SIMD-ONLY0-NEXT:    br label [[COND_END3145]]
33632 // SIMD-ONLY0:       cond.end3145:
33633 // SIMD-ONLY0-NEXT:    [[COND3146:%.*]] = phi i32 [ [[TMP1500]], [[COND_TRUE3143]] ], [ [[TMP1501]], [[COND_FALSE3144]] ]
33634 // SIMD-ONLY0-NEXT:    store i32 [[COND3146]], ptr [[UIX]], align 4
33635 // SIMD-ONLY0-NEXT:    [[TMP1502:%.*]] = load i32, ptr [[UIE]], align 4
33636 // SIMD-ONLY0-NEXT:    [[TMP1503:%.*]] = load i32, ptr [[UIX]], align 4
33637 // SIMD-ONLY0-NEXT:    [[CMP3147:%.*]] = icmp eq i32 [[TMP1502]], [[TMP1503]]
33638 // SIMD-ONLY0-NEXT:    br i1 [[CMP3147]], label [[COND_TRUE3149:%.*]], label [[COND_FALSE3150:%.*]]
33639 // SIMD-ONLY0:       cond.true3149:
33640 // SIMD-ONLY0-NEXT:    [[TMP1504:%.*]] = load i32, ptr [[UID]], align 4
33641 // SIMD-ONLY0-NEXT:    br label [[COND_END3151:%.*]]
33642 // SIMD-ONLY0:       cond.false3150:
33643 // SIMD-ONLY0-NEXT:    [[TMP1505:%.*]] = load i32, ptr [[UIX]], align 4
33644 // SIMD-ONLY0-NEXT:    br label [[COND_END3151]]
33645 // SIMD-ONLY0:       cond.end3151:
33646 // SIMD-ONLY0-NEXT:    [[COND3152:%.*]] = phi i32 [ [[TMP1504]], [[COND_TRUE3149]] ], [ [[TMP1505]], [[COND_FALSE3150]] ]
33647 // SIMD-ONLY0-NEXT:    store i32 [[COND3152]], ptr [[UIX]], align 4
33648 // SIMD-ONLY0-NEXT:    [[TMP1506:%.*]] = load i32, ptr [[UIX]], align 4
33649 // SIMD-ONLY0-NEXT:    [[TMP1507:%.*]] = load i32, ptr [[UIE]], align 4
33650 // SIMD-ONLY0-NEXT:    [[CMP3153:%.*]] = icmp eq i32 [[TMP1506]], [[TMP1507]]
33651 // SIMD-ONLY0-NEXT:    br i1 [[CMP3153]], label [[IF_THEN3155:%.*]], label [[IF_END3156:%.*]]
33652 // SIMD-ONLY0:       if.then3155:
33653 // SIMD-ONLY0-NEXT:    [[TMP1508:%.*]] = load i32, ptr [[UID]], align 4
33654 // SIMD-ONLY0-NEXT:    store i32 [[TMP1508]], ptr [[UIX]], align 4
33655 // SIMD-ONLY0-NEXT:    br label [[IF_END3156]]
33656 // SIMD-ONLY0:       if.end3156:
33657 // SIMD-ONLY0-NEXT:    [[TMP1509:%.*]] = load i32, ptr [[UIE]], align 4
33658 // SIMD-ONLY0-NEXT:    [[TMP1510:%.*]] = load i32, ptr [[UIX]], align 4
33659 // SIMD-ONLY0-NEXT:    [[CMP3157:%.*]] = icmp eq i32 [[TMP1509]], [[TMP1510]]
33660 // SIMD-ONLY0-NEXT:    br i1 [[CMP3157]], label [[IF_THEN3159:%.*]], label [[IF_END3160:%.*]]
33661 // SIMD-ONLY0:       if.then3159:
33662 // SIMD-ONLY0-NEXT:    [[TMP1511:%.*]] = load i32, ptr [[UID]], align 4
33663 // SIMD-ONLY0-NEXT:    store i32 [[TMP1511]], ptr [[UIX]], align 4
33664 // SIMD-ONLY0-NEXT:    br label [[IF_END3160]]
33665 // SIMD-ONLY0:       if.end3160:
33666 // SIMD-ONLY0-NEXT:    [[TMP1512:%.*]] = load i64, ptr [[LX]], align 8
33667 // SIMD-ONLY0-NEXT:    [[TMP1513:%.*]] = load i64, ptr [[LE]], align 8
33668 // SIMD-ONLY0-NEXT:    [[CMP3161:%.*]] = icmp sgt i64 [[TMP1512]], [[TMP1513]]
33669 // SIMD-ONLY0-NEXT:    br i1 [[CMP3161]], label [[COND_TRUE3163:%.*]], label [[COND_FALSE3164:%.*]]
33670 // SIMD-ONLY0:       cond.true3163:
33671 // SIMD-ONLY0-NEXT:    [[TMP1514:%.*]] = load i64, ptr [[LE]], align 8
33672 // SIMD-ONLY0-NEXT:    br label [[COND_END3165:%.*]]
33673 // SIMD-ONLY0:       cond.false3164:
33674 // SIMD-ONLY0-NEXT:    [[TMP1515:%.*]] = load i64, ptr [[LX]], align 8
33675 // SIMD-ONLY0-NEXT:    br label [[COND_END3165]]
33676 // SIMD-ONLY0:       cond.end3165:
33677 // SIMD-ONLY0-NEXT:    [[COND3166:%.*]] = phi i64 [ [[TMP1514]], [[COND_TRUE3163]] ], [ [[TMP1515]], [[COND_FALSE3164]] ]
33678 // SIMD-ONLY0-NEXT:    store i64 [[COND3166]], ptr [[LX]], align 8
33679 // SIMD-ONLY0-NEXT:    [[TMP1516:%.*]] = load i64, ptr [[LX]], align 8
33680 // SIMD-ONLY0-NEXT:    [[TMP1517:%.*]] = load i64, ptr [[LE]], align 8
33681 // SIMD-ONLY0-NEXT:    [[CMP3167:%.*]] = icmp slt i64 [[TMP1516]], [[TMP1517]]
33682 // SIMD-ONLY0-NEXT:    br i1 [[CMP3167]], label [[COND_TRUE3169:%.*]], label [[COND_FALSE3170:%.*]]
33683 // SIMD-ONLY0:       cond.true3169:
33684 // SIMD-ONLY0-NEXT:    [[TMP1518:%.*]] = load i64, ptr [[LE]], align 8
33685 // SIMD-ONLY0-NEXT:    br label [[COND_END3171:%.*]]
33686 // SIMD-ONLY0:       cond.false3170:
33687 // SIMD-ONLY0-NEXT:    [[TMP1519:%.*]] = load i64, ptr [[LX]], align 8
33688 // SIMD-ONLY0-NEXT:    br label [[COND_END3171]]
33689 // SIMD-ONLY0:       cond.end3171:
33690 // SIMD-ONLY0-NEXT:    [[COND3172:%.*]] = phi i64 [ [[TMP1518]], [[COND_TRUE3169]] ], [ [[TMP1519]], [[COND_FALSE3170]] ]
33691 // SIMD-ONLY0-NEXT:    store i64 [[COND3172]], ptr [[LX]], align 8
33692 // SIMD-ONLY0-NEXT:    [[TMP1520:%.*]] = load i64, ptr [[LE]], align 8
33693 // SIMD-ONLY0-NEXT:    [[TMP1521:%.*]] = load i64, ptr [[LX]], align 8
33694 // SIMD-ONLY0-NEXT:    [[CMP3173:%.*]] = icmp sgt i64 [[TMP1520]], [[TMP1521]]
33695 // SIMD-ONLY0-NEXT:    br i1 [[CMP3173]], label [[COND_TRUE3175:%.*]], label [[COND_FALSE3176:%.*]]
33696 // SIMD-ONLY0:       cond.true3175:
33697 // SIMD-ONLY0-NEXT:    [[TMP1522:%.*]] = load i64, ptr [[LE]], align 8
33698 // SIMD-ONLY0-NEXT:    br label [[COND_END3177:%.*]]
33699 // SIMD-ONLY0:       cond.false3176:
33700 // SIMD-ONLY0-NEXT:    [[TMP1523:%.*]] = load i64, ptr [[LX]], align 8
33701 // SIMD-ONLY0-NEXT:    br label [[COND_END3177]]
33702 // SIMD-ONLY0:       cond.end3177:
33703 // SIMD-ONLY0-NEXT:    [[COND3178:%.*]] = phi i64 [ [[TMP1522]], [[COND_TRUE3175]] ], [ [[TMP1523]], [[COND_FALSE3176]] ]
33704 // SIMD-ONLY0-NEXT:    store i64 [[COND3178]], ptr [[LX]], align 8
33705 // SIMD-ONLY0-NEXT:    [[TMP1524:%.*]] = load i64, ptr [[LE]], align 8
33706 // SIMD-ONLY0-NEXT:    [[TMP1525:%.*]] = load i64, ptr [[LX]], align 8
33707 // SIMD-ONLY0-NEXT:    [[CMP3179:%.*]] = icmp slt i64 [[TMP1524]], [[TMP1525]]
33708 // SIMD-ONLY0-NEXT:    br i1 [[CMP3179]], label [[COND_TRUE3181:%.*]], label [[COND_FALSE3182:%.*]]
33709 // SIMD-ONLY0:       cond.true3181:
33710 // SIMD-ONLY0-NEXT:    [[TMP1526:%.*]] = load i64, ptr [[LE]], align 8
33711 // SIMD-ONLY0-NEXT:    br label [[COND_END3183:%.*]]
33712 // SIMD-ONLY0:       cond.false3182:
33713 // SIMD-ONLY0-NEXT:    [[TMP1527:%.*]] = load i64, ptr [[LX]], align 8
33714 // SIMD-ONLY0-NEXT:    br label [[COND_END3183]]
33715 // SIMD-ONLY0:       cond.end3183:
33716 // SIMD-ONLY0-NEXT:    [[COND3184:%.*]] = phi i64 [ [[TMP1526]], [[COND_TRUE3181]] ], [ [[TMP1527]], [[COND_FALSE3182]] ]
33717 // SIMD-ONLY0-NEXT:    store i64 [[COND3184]], ptr [[LX]], align 8
33718 // SIMD-ONLY0-NEXT:    [[TMP1528:%.*]] = load i64, ptr [[LX]], align 8
33719 // SIMD-ONLY0-NEXT:    [[TMP1529:%.*]] = load i64, ptr [[LE]], align 8
33720 // SIMD-ONLY0-NEXT:    [[CMP3185:%.*]] = icmp sgt i64 [[TMP1528]], [[TMP1529]]
33721 // SIMD-ONLY0-NEXT:    br i1 [[CMP3185]], label [[IF_THEN3187:%.*]], label [[IF_END3188:%.*]]
33722 // SIMD-ONLY0:       if.then3187:
33723 // SIMD-ONLY0-NEXT:    [[TMP1530:%.*]] = load i64, ptr [[LE]], align 8
33724 // SIMD-ONLY0-NEXT:    store i64 [[TMP1530]], ptr [[LX]], align 8
33725 // SIMD-ONLY0-NEXT:    br label [[IF_END3188]]
33726 // SIMD-ONLY0:       if.end3188:
33727 // SIMD-ONLY0-NEXT:    [[TMP1531:%.*]] = load i64, ptr [[LX]], align 8
33728 // SIMD-ONLY0-NEXT:    [[TMP1532:%.*]] = load i64, ptr [[LE]], align 8
33729 // SIMD-ONLY0-NEXT:    [[CMP3189:%.*]] = icmp slt i64 [[TMP1531]], [[TMP1532]]
33730 // SIMD-ONLY0-NEXT:    br i1 [[CMP3189]], label [[IF_THEN3191:%.*]], label [[IF_END3192:%.*]]
33731 // SIMD-ONLY0:       if.then3191:
33732 // SIMD-ONLY0-NEXT:    [[TMP1533:%.*]] = load i64, ptr [[LE]], align 8
33733 // SIMD-ONLY0-NEXT:    store i64 [[TMP1533]], ptr [[LX]], align 8
33734 // SIMD-ONLY0-NEXT:    br label [[IF_END3192]]
33735 // SIMD-ONLY0:       if.end3192:
33736 // SIMD-ONLY0-NEXT:    [[TMP1534:%.*]] = load i64, ptr [[LE]], align 8
33737 // SIMD-ONLY0-NEXT:    [[TMP1535:%.*]] = load i64, ptr [[LX]], align 8
33738 // SIMD-ONLY0-NEXT:    [[CMP3193:%.*]] = icmp sgt i64 [[TMP1534]], [[TMP1535]]
33739 // SIMD-ONLY0-NEXT:    br i1 [[CMP3193]], label [[IF_THEN3195:%.*]], label [[IF_END3196:%.*]]
33740 // SIMD-ONLY0:       if.then3195:
33741 // SIMD-ONLY0-NEXT:    [[TMP1536:%.*]] = load i64, ptr [[LE]], align 8
33742 // SIMD-ONLY0-NEXT:    store i64 [[TMP1536]], ptr [[LX]], align 8
33743 // SIMD-ONLY0-NEXT:    br label [[IF_END3196]]
33744 // SIMD-ONLY0:       if.end3196:
33745 // SIMD-ONLY0-NEXT:    [[TMP1537:%.*]] = load i64, ptr [[LE]], align 8
33746 // SIMD-ONLY0-NEXT:    [[TMP1538:%.*]] = load i64, ptr [[LX]], align 8
33747 // SIMD-ONLY0-NEXT:    [[CMP3197:%.*]] = icmp slt i64 [[TMP1537]], [[TMP1538]]
33748 // SIMD-ONLY0-NEXT:    br i1 [[CMP3197]], label [[IF_THEN3199:%.*]], label [[IF_END3200:%.*]]
33749 // SIMD-ONLY0:       if.then3199:
33750 // SIMD-ONLY0-NEXT:    [[TMP1539:%.*]] = load i64, ptr [[LE]], align 8
33751 // SIMD-ONLY0-NEXT:    store i64 [[TMP1539]], ptr [[LX]], align 8
33752 // SIMD-ONLY0-NEXT:    br label [[IF_END3200]]
33753 // SIMD-ONLY0:       if.end3200:
33754 // SIMD-ONLY0-NEXT:    [[TMP1540:%.*]] = load i64, ptr [[LX]], align 8
33755 // SIMD-ONLY0-NEXT:    [[TMP1541:%.*]] = load i64, ptr [[LE]], align 8
33756 // SIMD-ONLY0-NEXT:    [[CMP3201:%.*]] = icmp eq i64 [[TMP1540]], [[TMP1541]]
33757 // SIMD-ONLY0-NEXT:    br i1 [[CMP3201]], label [[COND_TRUE3203:%.*]], label [[COND_FALSE3204:%.*]]
33758 // SIMD-ONLY0:       cond.true3203:
33759 // SIMD-ONLY0-NEXT:    [[TMP1542:%.*]] = load i64, ptr [[LD]], align 8
33760 // SIMD-ONLY0-NEXT:    br label [[COND_END3205:%.*]]
33761 // SIMD-ONLY0:       cond.false3204:
33762 // SIMD-ONLY0-NEXT:    [[TMP1543:%.*]] = load i64, ptr [[LX]], align 8
33763 // SIMD-ONLY0-NEXT:    br label [[COND_END3205]]
33764 // SIMD-ONLY0:       cond.end3205:
33765 // SIMD-ONLY0-NEXT:    [[COND3206:%.*]] = phi i64 [ [[TMP1542]], [[COND_TRUE3203]] ], [ [[TMP1543]], [[COND_FALSE3204]] ]
33766 // SIMD-ONLY0-NEXT:    store i64 [[COND3206]], ptr [[LX]], align 8
33767 // SIMD-ONLY0-NEXT:    [[TMP1544:%.*]] = load i64, ptr [[LE]], align 8
33768 // SIMD-ONLY0-NEXT:    [[TMP1545:%.*]] = load i64, ptr [[LX]], align 8
33769 // SIMD-ONLY0-NEXT:    [[CMP3207:%.*]] = icmp eq i64 [[TMP1544]], [[TMP1545]]
33770 // SIMD-ONLY0-NEXT:    br i1 [[CMP3207]], label [[COND_TRUE3209:%.*]], label [[COND_FALSE3210:%.*]]
33771 // SIMD-ONLY0:       cond.true3209:
33772 // SIMD-ONLY0-NEXT:    [[TMP1546:%.*]] = load i64, ptr [[LD]], align 8
33773 // SIMD-ONLY0-NEXT:    br label [[COND_END3211:%.*]]
33774 // SIMD-ONLY0:       cond.false3210:
33775 // SIMD-ONLY0-NEXT:    [[TMP1547:%.*]] = load i64, ptr [[LX]], align 8
33776 // SIMD-ONLY0-NEXT:    br label [[COND_END3211]]
33777 // SIMD-ONLY0:       cond.end3211:
33778 // SIMD-ONLY0-NEXT:    [[COND3212:%.*]] = phi i64 [ [[TMP1546]], [[COND_TRUE3209]] ], [ [[TMP1547]], [[COND_FALSE3210]] ]
33779 // SIMD-ONLY0-NEXT:    store i64 [[COND3212]], ptr [[LX]], align 8
33780 // SIMD-ONLY0-NEXT:    [[TMP1548:%.*]] = load i64, ptr [[LX]], align 8
33781 // SIMD-ONLY0-NEXT:    [[TMP1549:%.*]] = load i64, ptr [[LE]], align 8
33782 // SIMD-ONLY0-NEXT:    [[CMP3213:%.*]] = icmp eq i64 [[TMP1548]], [[TMP1549]]
33783 // SIMD-ONLY0-NEXT:    br i1 [[CMP3213]], label [[IF_THEN3215:%.*]], label [[IF_END3216:%.*]]
33784 // SIMD-ONLY0:       if.then3215:
33785 // SIMD-ONLY0-NEXT:    [[TMP1550:%.*]] = load i64, ptr [[LD]], align 8
33786 // SIMD-ONLY0-NEXT:    store i64 [[TMP1550]], ptr [[LX]], align 8
33787 // SIMD-ONLY0-NEXT:    br label [[IF_END3216]]
33788 // SIMD-ONLY0:       if.end3216:
33789 // SIMD-ONLY0-NEXT:    [[TMP1551:%.*]] = load i64, ptr [[LE]], align 8
33790 // SIMD-ONLY0-NEXT:    [[TMP1552:%.*]] = load i64, ptr [[LX]], align 8
33791 // SIMD-ONLY0-NEXT:    [[CMP3217:%.*]] = icmp eq i64 [[TMP1551]], [[TMP1552]]
33792 // SIMD-ONLY0-NEXT:    br i1 [[CMP3217]], label [[IF_THEN3219:%.*]], label [[IF_END3220:%.*]]
33793 // SIMD-ONLY0:       if.then3219:
33794 // SIMD-ONLY0-NEXT:    [[TMP1553:%.*]] = load i64, ptr [[LD]], align 8
33795 // SIMD-ONLY0-NEXT:    store i64 [[TMP1553]], ptr [[LX]], align 8
33796 // SIMD-ONLY0-NEXT:    br label [[IF_END3220]]
33797 // SIMD-ONLY0:       if.end3220:
33798 // SIMD-ONLY0-NEXT:    [[TMP1554:%.*]] = load i64, ptr [[ULX]], align 8
33799 // SIMD-ONLY0-NEXT:    [[TMP1555:%.*]] = load i64, ptr [[ULE]], align 8
33800 // SIMD-ONLY0-NEXT:    [[CMP3221:%.*]] = icmp ugt i64 [[TMP1554]], [[TMP1555]]
33801 // SIMD-ONLY0-NEXT:    br i1 [[CMP3221]], label [[COND_TRUE3223:%.*]], label [[COND_FALSE3224:%.*]]
33802 // SIMD-ONLY0:       cond.true3223:
33803 // SIMD-ONLY0-NEXT:    [[TMP1556:%.*]] = load i64, ptr [[ULE]], align 8
33804 // SIMD-ONLY0-NEXT:    br label [[COND_END3225:%.*]]
33805 // SIMD-ONLY0:       cond.false3224:
33806 // SIMD-ONLY0-NEXT:    [[TMP1557:%.*]] = load i64, ptr [[ULX]], align 8
33807 // SIMD-ONLY0-NEXT:    br label [[COND_END3225]]
33808 // SIMD-ONLY0:       cond.end3225:
33809 // SIMD-ONLY0-NEXT:    [[COND3226:%.*]] = phi i64 [ [[TMP1556]], [[COND_TRUE3223]] ], [ [[TMP1557]], [[COND_FALSE3224]] ]
33810 // SIMD-ONLY0-NEXT:    store i64 [[COND3226]], ptr [[ULX]], align 8
33811 // SIMD-ONLY0-NEXT:    [[TMP1558:%.*]] = load i64, ptr [[ULX]], align 8
33812 // SIMD-ONLY0-NEXT:    [[TMP1559:%.*]] = load i64, ptr [[ULE]], align 8
33813 // SIMD-ONLY0-NEXT:    [[CMP3227:%.*]] = icmp ult i64 [[TMP1558]], [[TMP1559]]
33814 // SIMD-ONLY0-NEXT:    br i1 [[CMP3227]], label [[COND_TRUE3229:%.*]], label [[COND_FALSE3230:%.*]]
33815 // SIMD-ONLY0:       cond.true3229:
33816 // SIMD-ONLY0-NEXT:    [[TMP1560:%.*]] = load i64, ptr [[ULE]], align 8
33817 // SIMD-ONLY0-NEXT:    br label [[COND_END3231:%.*]]
33818 // SIMD-ONLY0:       cond.false3230:
33819 // SIMD-ONLY0-NEXT:    [[TMP1561:%.*]] = load i64, ptr [[ULX]], align 8
33820 // SIMD-ONLY0-NEXT:    br label [[COND_END3231]]
33821 // SIMD-ONLY0:       cond.end3231:
33822 // SIMD-ONLY0-NEXT:    [[COND3232:%.*]] = phi i64 [ [[TMP1560]], [[COND_TRUE3229]] ], [ [[TMP1561]], [[COND_FALSE3230]] ]
33823 // SIMD-ONLY0-NEXT:    store i64 [[COND3232]], ptr [[ULX]], align 8
33824 // SIMD-ONLY0-NEXT:    [[TMP1562:%.*]] = load i64, ptr [[ULE]], align 8
33825 // SIMD-ONLY0-NEXT:    [[TMP1563:%.*]] = load i64, ptr [[ULX]], align 8
33826 // SIMD-ONLY0-NEXT:    [[CMP3233:%.*]] = icmp ugt i64 [[TMP1562]], [[TMP1563]]
33827 // SIMD-ONLY0-NEXT:    br i1 [[CMP3233]], label [[COND_TRUE3235:%.*]], label [[COND_FALSE3236:%.*]]
33828 // SIMD-ONLY0:       cond.true3235:
33829 // SIMD-ONLY0-NEXT:    [[TMP1564:%.*]] = load i64, ptr [[ULE]], align 8
33830 // SIMD-ONLY0-NEXT:    br label [[COND_END3237:%.*]]
33831 // SIMD-ONLY0:       cond.false3236:
33832 // SIMD-ONLY0-NEXT:    [[TMP1565:%.*]] = load i64, ptr [[ULX]], align 8
33833 // SIMD-ONLY0-NEXT:    br label [[COND_END3237]]
33834 // SIMD-ONLY0:       cond.end3237:
33835 // SIMD-ONLY0-NEXT:    [[COND3238:%.*]] = phi i64 [ [[TMP1564]], [[COND_TRUE3235]] ], [ [[TMP1565]], [[COND_FALSE3236]] ]
33836 // SIMD-ONLY0-NEXT:    store i64 [[COND3238]], ptr [[ULX]], align 8
33837 // SIMD-ONLY0-NEXT:    [[TMP1566:%.*]] = load i64, ptr [[ULE]], align 8
33838 // SIMD-ONLY0-NEXT:    [[TMP1567:%.*]] = load i64, ptr [[ULX]], align 8
33839 // SIMD-ONLY0-NEXT:    [[CMP3239:%.*]] = icmp ult i64 [[TMP1566]], [[TMP1567]]
33840 // SIMD-ONLY0-NEXT:    br i1 [[CMP3239]], label [[COND_TRUE3241:%.*]], label [[COND_FALSE3242:%.*]]
33841 // SIMD-ONLY0:       cond.true3241:
33842 // SIMD-ONLY0-NEXT:    [[TMP1568:%.*]] = load i64, ptr [[ULE]], align 8
33843 // SIMD-ONLY0-NEXT:    br label [[COND_END3243:%.*]]
33844 // SIMD-ONLY0:       cond.false3242:
33845 // SIMD-ONLY0-NEXT:    [[TMP1569:%.*]] = load i64, ptr [[ULX]], align 8
33846 // SIMD-ONLY0-NEXT:    br label [[COND_END3243]]
33847 // SIMD-ONLY0:       cond.end3243:
33848 // SIMD-ONLY0-NEXT:    [[COND3244:%.*]] = phi i64 [ [[TMP1568]], [[COND_TRUE3241]] ], [ [[TMP1569]], [[COND_FALSE3242]] ]
33849 // SIMD-ONLY0-NEXT:    store i64 [[COND3244]], ptr [[ULX]], align 8
33850 // SIMD-ONLY0-NEXT:    [[TMP1570:%.*]] = load i64, ptr [[ULX]], align 8
33851 // SIMD-ONLY0-NEXT:    [[TMP1571:%.*]] = load i64, ptr [[ULE]], align 8
33852 // SIMD-ONLY0-NEXT:    [[CMP3245:%.*]] = icmp ugt i64 [[TMP1570]], [[TMP1571]]
33853 // SIMD-ONLY0-NEXT:    br i1 [[CMP3245]], label [[IF_THEN3247:%.*]], label [[IF_END3248:%.*]]
33854 // SIMD-ONLY0:       if.then3247:
33855 // SIMD-ONLY0-NEXT:    [[TMP1572:%.*]] = load i64, ptr [[ULE]], align 8
33856 // SIMD-ONLY0-NEXT:    store i64 [[TMP1572]], ptr [[ULX]], align 8
33857 // SIMD-ONLY0-NEXT:    br label [[IF_END3248]]
33858 // SIMD-ONLY0:       if.end3248:
33859 // SIMD-ONLY0-NEXT:    [[TMP1573:%.*]] = load i64, ptr [[ULX]], align 8
33860 // SIMD-ONLY0-NEXT:    [[TMP1574:%.*]] = load i64, ptr [[ULE]], align 8
33861 // SIMD-ONLY0-NEXT:    [[CMP3249:%.*]] = icmp ult i64 [[TMP1573]], [[TMP1574]]
33862 // SIMD-ONLY0-NEXT:    br i1 [[CMP3249]], label [[IF_THEN3251:%.*]], label [[IF_END3252:%.*]]
33863 // SIMD-ONLY0:       if.then3251:
33864 // SIMD-ONLY0-NEXT:    [[TMP1575:%.*]] = load i64, ptr [[ULE]], align 8
33865 // SIMD-ONLY0-NEXT:    store i64 [[TMP1575]], ptr [[ULX]], align 8
33866 // SIMD-ONLY0-NEXT:    br label [[IF_END3252]]
33867 // SIMD-ONLY0:       if.end3252:
33868 // SIMD-ONLY0-NEXT:    [[TMP1576:%.*]] = load i64, ptr [[ULE]], align 8
33869 // SIMD-ONLY0-NEXT:    [[TMP1577:%.*]] = load i64, ptr [[ULX]], align 8
33870 // SIMD-ONLY0-NEXT:    [[CMP3253:%.*]] = icmp ugt i64 [[TMP1576]], [[TMP1577]]
33871 // SIMD-ONLY0-NEXT:    br i1 [[CMP3253]], label [[IF_THEN3255:%.*]], label [[IF_END3256:%.*]]
33872 // SIMD-ONLY0:       if.then3255:
33873 // SIMD-ONLY0-NEXT:    [[TMP1578:%.*]] = load i64, ptr [[ULE]], align 8
33874 // SIMD-ONLY0-NEXT:    store i64 [[TMP1578]], ptr [[ULX]], align 8
33875 // SIMD-ONLY0-NEXT:    br label [[IF_END3256]]
33876 // SIMD-ONLY0:       if.end3256:
33877 // SIMD-ONLY0-NEXT:    [[TMP1579:%.*]] = load i64, ptr [[ULE]], align 8
33878 // SIMD-ONLY0-NEXT:    [[TMP1580:%.*]] = load i64, ptr [[ULX]], align 8
33879 // SIMD-ONLY0-NEXT:    [[CMP3257:%.*]] = icmp ult i64 [[TMP1579]], [[TMP1580]]
33880 // SIMD-ONLY0-NEXT:    br i1 [[CMP3257]], label [[IF_THEN3259:%.*]], label [[IF_END3260:%.*]]
33881 // SIMD-ONLY0:       if.then3259:
33882 // SIMD-ONLY0-NEXT:    [[TMP1581:%.*]] = load i64, ptr [[ULE]], align 8
33883 // SIMD-ONLY0-NEXT:    store i64 [[TMP1581]], ptr [[ULX]], align 8
33884 // SIMD-ONLY0-NEXT:    br label [[IF_END3260]]
33885 // SIMD-ONLY0:       if.end3260:
33886 // SIMD-ONLY0-NEXT:    [[TMP1582:%.*]] = load i64, ptr [[ULX]], align 8
33887 // SIMD-ONLY0-NEXT:    [[TMP1583:%.*]] = load i64, ptr [[ULE]], align 8
33888 // SIMD-ONLY0-NEXT:    [[CMP3261:%.*]] = icmp eq i64 [[TMP1582]], [[TMP1583]]
33889 // SIMD-ONLY0-NEXT:    br i1 [[CMP3261]], label [[COND_TRUE3263:%.*]], label [[COND_FALSE3264:%.*]]
33890 // SIMD-ONLY0:       cond.true3263:
33891 // SIMD-ONLY0-NEXT:    [[TMP1584:%.*]] = load i64, ptr [[ULD]], align 8
33892 // SIMD-ONLY0-NEXT:    br label [[COND_END3265:%.*]]
33893 // SIMD-ONLY0:       cond.false3264:
33894 // SIMD-ONLY0-NEXT:    [[TMP1585:%.*]] = load i64, ptr [[ULX]], align 8
33895 // SIMD-ONLY0-NEXT:    br label [[COND_END3265]]
33896 // SIMD-ONLY0:       cond.end3265:
33897 // SIMD-ONLY0-NEXT:    [[COND3266:%.*]] = phi i64 [ [[TMP1584]], [[COND_TRUE3263]] ], [ [[TMP1585]], [[COND_FALSE3264]] ]
33898 // SIMD-ONLY0-NEXT:    store i64 [[COND3266]], ptr [[ULX]], align 8
33899 // SIMD-ONLY0-NEXT:    [[TMP1586:%.*]] = load i64, ptr [[ULE]], align 8
33900 // SIMD-ONLY0-NEXT:    [[TMP1587:%.*]] = load i64, ptr [[ULX]], align 8
33901 // SIMD-ONLY0-NEXT:    [[CMP3267:%.*]] = icmp eq i64 [[TMP1586]], [[TMP1587]]
33902 // SIMD-ONLY0-NEXT:    br i1 [[CMP3267]], label [[COND_TRUE3269:%.*]], label [[COND_FALSE3270:%.*]]
33903 // SIMD-ONLY0:       cond.true3269:
33904 // SIMD-ONLY0-NEXT:    [[TMP1588:%.*]] = load i64, ptr [[ULD]], align 8
33905 // SIMD-ONLY0-NEXT:    br label [[COND_END3271:%.*]]
33906 // SIMD-ONLY0:       cond.false3270:
33907 // SIMD-ONLY0-NEXT:    [[TMP1589:%.*]] = load i64, ptr [[ULX]], align 8
33908 // SIMD-ONLY0-NEXT:    br label [[COND_END3271]]
33909 // SIMD-ONLY0:       cond.end3271:
33910 // SIMD-ONLY0-NEXT:    [[COND3272:%.*]] = phi i64 [ [[TMP1588]], [[COND_TRUE3269]] ], [ [[TMP1589]], [[COND_FALSE3270]] ]
33911 // SIMD-ONLY0-NEXT:    store i64 [[COND3272]], ptr [[ULX]], align 8
33912 // SIMD-ONLY0-NEXT:    [[TMP1590:%.*]] = load i64, ptr [[ULX]], align 8
33913 // SIMD-ONLY0-NEXT:    [[TMP1591:%.*]] = load i64, ptr [[ULE]], align 8
33914 // SIMD-ONLY0-NEXT:    [[CMP3273:%.*]] = icmp eq i64 [[TMP1590]], [[TMP1591]]
33915 // SIMD-ONLY0-NEXT:    br i1 [[CMP3273]], label [[IF_THEN3275:%.*]], label [[IF_END3276:%.*]]
33916 // SIMD-ONLY0:       if.then3275:
33917 // SIMD-ONLY0-NEXT:    [[TMP1592:%.*]] = load i64, ptr [[ULD]], align 8
33918 // SIMD-ONLY0-NEXT:    store i64 [[TMP1592]], ptr [[ULX]], align 8
33919 // SIMD-ONLY0-NEXT:    br label [[IF_END3276]]
33920 // SIMD-ONLY0:       if.end3276:
33921 // SIMD-ONLY0-NEXT:    [[TMP1593:%.*]] = load i64, ptr [[ULE]], align 8
33922 // SIMD-ONLY0-NEXT:    [[TMP1594:%.*]] = load i64, ptr [[ULX]], align 8
33923 // SIMD-ONLY0-NEXT:    [[CMP3277:%.*]] = icmp eq i64 [[TMP1593]], [[TMP1594]]
33924 // SIMD-ONLY0-NEXT:    br i1 [[CMP3277]], label [[IF_THEN3279:%.*]], label [[IF_END3280:%.*]]
33925 // SIMD-ONLY0:       if.then3279:
33926 // SIMD-ONLY0-NEXT:    [[TMP1595:%.*]] = load i64, ptr [[ULD]], align 8
33927 // SIMD-ONLY0-NEXT:    store i64 [[TMP1595]], ptr [[ULX]], align 8
33928 // SIMD-ONLY0-NEXT:    br label [[IF_END3280]]
33929 // SIMD-ONLY0:       if.end3280:
33930 // SIMD-ONLY0-NEXT:    [[TMP1596:%.*]] = load i64, ptr [[LX]], align 8
33931 // SIMD-ONLY0-NEXT:    [[TMP1597:%.*]] = load i64, ptr [[LE]], align 8
33932 // SIMD-ONLY0-NEXT:    [[CMP3281:%.*]] = icmp sgt i64 [[TMP1596]], [[TMP1597]]
33933 // SIMD-ONLY0-NEXT:    br i1 [[CMP3281]], label [[COND_TRUE3283:%.*]], label [[COND_FALSE3284:%.*]]
33934 // SIMD-ONLY0:       cond.true3283:
33935 // SIMD-ONLY0-NEXT:    [[TMP1598:%.*]] = load i64, ptr [[LE]], align 8
33936 // SIMD-ONLY0-NEXT:    br label [[COND_END3285:%.*]]
33937 // SIMD-ONLY0:       cond.false3284:
33938 // SIMD-ONLY0-NEXT:    [[TMP1599:%.*]] = load i64, ptr [[LX]], align 8
33939 // SIMD-ONLY0-NEXT:    br label [[COND_END3285]]
33940 // SIMD-ONLY0:       cond.end3285:
33941 // SIMD-ONLY0-NEXT:    [[COND3286:%.*]] = phi i64 [ [[TMP1598]], [[COND_TRUE3283]] ], [ [[TMP1599]], [[COND_FALSE3284]] ]
33942 // SIMD-ONLY0-NEXT:    store i64 [[COND3286]], ptr [[LX]], align 8
33943 // SIMD-ONLY0-NEXT:    [[TMP1600:%.*]] = load i64, ptr [[LX]], align 8
33944 // SIMD-ONLY0-NEXT:    [[TMP1601:%.*]] = load i64, ptr [[LE]], align 8
33945 // SIMD-ONLY0-NEXT:    [[CMP3287:%.*]] = icmp slt i64 [[TMP1600]], [[TMP1601]]
33946 // SIMD-ONLY0-NEXT:    br i1 [[CMP3287]], label [[COND_TRUE3289:%.*]], label [[COND_FALSE3290:%.*]]
33947 // SIMD-ONLY0:       cond.true3289:
33948 // SIMD-ONLY0-NEXT:    [[TMP1602:%.*]] = load i64, ptr [[LE]], align 8
33949 // SIMD-ONLY0-NEXT:    br label [[COND_END3291:%.*]]
33950 // SIMD-ONLY0:       cond.false3290:
33951 // SIMD-ONLY0-NEXT:    [[TMP1603:%.*]] = load i64, ptr [[LX]], align 8
33952 // SIMD-ONLY0-NEXT:    br label [[COND_END3291]]
33953 // SIMD-ONLY0:       cond.end3291:
33954 // SIMD-ONLY0-NEXT:    [[COND3292:%.*]] = phi i64 [ [[TMP1602]], [[COND_TRUE3289]] ], [ [[TMP1603]], [[COND_FALSE3290]] ]
33955 // SIMD-ONLY0-NEXT:    store i64 [[COND3292]], ptr [[LX]], align 8
33956 // SIMD-ONLY0-NEXT:    [[TMP1604:%.*]] = load i64, ptr [[LE]], align 8
33957 // SIMD-ONLY0-NEXT:    [[TMP1605:%.*]] = load i64, ptr [[LX]], align 8
33958 // SIMD-ONLY0-NEXT:    [[CMP3293:%.*]] = icmp sgt i64 [[TMP1604]], [[TMP1605]]
33959 // SIMD-ONLY0-NEXT:    br i1 [[CMP3293]], label [[COND_TRUE3295:%.*]], label [[COND_FALSE3296:%.*]]
33960 // SIMD-ONLY0:       cond.true3295:
33961 // SIMD-ONLY0-NEXT:    [[TMP1606:%.*]] = load i64, ptr [[LE]], align 8
33962 // SIMD-ONLY0-NEXT:    br label [[COND_END3297:%.*]]
33963 // SIMD-ONLY0:       cond.false3296:
33964 // SIMD-ONLY0-NEXT:    [[TMP1607:%.*]] = load i64, ptr [[LX]], align 8
33965 // SIMD-ONLY0-NEXT:    br label [[COND_END3297]]
33966 // SIMD-ONLY0:       cond.end3297:
33967 // SIMD-ONLY0-NEXT:    [[COND3298:%.*]] = phi i64 [ [[TMP1606]], [[COND_TRUE3295]] ], [ [[TMP1607]], [[COND_FALSE3296]] ]
33968 // SIMD-ONLY0-NEXT:    store i64 [[COND3298]], ptr [[LX]], align 8
33969 // SIMD-ONLY0-NEXT:    [[TMP1608:%.*]] = load i64, ptr [[LE]], align 8
33970 // SIMD-ONLY0-NEXT:    [[TMP1609:%.*]] = load i64, ptr [[LX]], align 8
33971 // SIMD-ONLY0-NEXT:    [[CMP3299:%.*]] = icmp slt i64 [[TMP1608]], [[TMP1609]]
33972 // SIMD-ONLY0-NEXT:    br i1 [[CMP3299]], label [[COND_TRUE3301:%.*]], label [[COND_FALSE3302:%.*]]
33973 // SIMD-ONLY0:       cond.true3301:
33974 // SIMD-ONLY0-NEXT:    [[TMP1610:%.*]] = load i64, ptr [[LE]], align 8
33975 // SIMD-ONLY0-NEXT:    br label [[COND_END3303:%.*]]
33976 // SIMD-ONLY0:       cond.false3302:
33977 // SIMD-ONLY0-NEXT:    [[TMP1611:%.*]] = load i64, ptr [[LX]], align 8
33978 // SIMD-ONLY0-NEXT:    br label [[COND_END3303]]
33979 // SIMD-ONLY0:       cond.end3303:
33980 // SIMD-ONLY0-NEXT:    [[COND3304:%.*]] = phi i64 [ [[TMP1610]], [[COND_TRUE3301]] ], [ [[TMP1611]], [[COND_FALSE3302]] ]
33981 // SIMD-ONLY0-NEXT:    store i64 [[COND3304]], ptr [[LX]], align 8
33982 // SIMD-ONLY0-NEXT:    [[TMP1612:%.*]] = load i64, ptr [[LX]], align 8
33983 // SIMD-ONLY0-NEXT:    [[TMP1613:%.*]] = load i64, ptr [[LE]], align 8
33984 // SIMD-ONLY0-NEXT:    [[CMP3305:%.*]] = icmp sgt i64 [[TMP1612]], [[TMP1613]]
33985 // SIMD-ONLY0-NEXT:    br i1 [[CMP3305]], label [[IF_THEN3307:%.*]], label [[IF_END3308:%.*]]
33986 // SIMD-ONLY0:       if.then3307:
33987 // SIMD-ONLY0-NEXT:    [[TMP1614:%.*]] = load i64, ptr [[LE]], align 8
33988 // SIMD-ONLY0-NEXT:    store i64 [[TMP1614]], ptr [[LX]], align 8
33989 // SIMD-ONLY0-NEXT:    br label [[IF_END3308]]
33990 // SIMD-ONLY0:       if.end3308:
33991 // SIMD-ONLY0-NEXT:    [[TMP1615:%.*]] = load i64, ptr [[LX]], align 8
33992 // SIMD-ONLY0-NEXT:    [[TMP1616:%.*]] = load i64, ptr [[LE]], align 8
33993 // SIMD-ONLY0-NEXT:    [[CMP3309:%.*]] = icmp slt i64 [[TMP1615]], [[TMP1616]]
33994 // SIMD-ONLY0-NEXT:    br i1 [[CMP3309]], label [[IF_THEN3311:%.*]], label [[IF_END3312:%.*]]
33995 // SIMD-ONLY0:       if.then3311:
33996 // SIMD-ONLY0-NEXT:    [[TMP1617:%.*]] = load i64, ptr [[LE]], align 8
33997 // SIMD-ONLY0-NEXT:    store i64 [[TMP1617]], ptr [[LX]], align 8
33998 // SIMD-ONLY0-NEXT:    br label [[IF_END3312]]
33999 // SIMD-ONLY0:       if.end3312:
34000 // SIMD-ONLY0-NEXT:    [[TMP1618:%.*]] = load i64, ptr [[LE]], align 8
34001 // SIMD-ONLY0-NEXT:    [[TMP1619:%.*]] = load i64, ptr [[LX]], align 8
34002 // SIMD-ONLY0-NEXT:    [[CMP3313:%.*]] = icmp sgt i64 [[TMP1618]], [[TMP1619]]
34003 // SIMD-ONLY0-NEXT:    br i1 [[CMP3313]], label [[IF_THEN3315:%.*]], label [[IF_END3316:%.*]]
34004 // SIMD-ONLY0:       if.then3315:
34005 // SIMD-ONLY0-NEXT:    [[TMP1620:%.*]] = load i64, ptr [[LE]], align 8
34006 // SIMD-ONLY0-NEXT:    store i64 [[TMP1620]], ptr [[LX]], align 8
34007 // SIMD-ONLY0-NEXT:    br label [[IF_END3316]]
34008 // SIMD-ONLY0:       if.end3316:
34009 // SIMD-ONLY0-NEXT:    [[TMP1621:%.*]] = load i64, ptr [[LE]], align 8
34010 // SIMD-ONLY0-NEXT:    [[TMP1622:%.*]] = load i64, ptr [[LX]], align 8
34011 // SIMD-ONLY0-NEXT:    [[CMP3317:%.*]] = icmp slt i64 [[TMP1621]], [[TMP1622]]
34012 // SIMD-ONLY0-NEXT:    br i1 [[CMP3317]], label [[IF_THEN3319:%.*]], label [[IF_END3320:%.*]]
34013 // SIMD-ONLY0:       if.then3319:
34014 // SIMD-ONLY0-NEXT:    [[TMP1623:%.*]] = load i64, ptr [[LE]], align 8
34015 // SIMD-ONLY0-NEXT:    store i64 [[TMP1623]], ptr [[LX]], align 8
34016 // SIMD-ONLY0-NEXT:    br label [[IF_END3320]]
34017 // SIMD-ONLY0:       if.end3320:
34018 // SIMD-ONLY0-NEXT:    [[TMP1624:%.*]] = load i64, ptr [[LX]], align 8
34019 // SIMD-ONLY0-NEXT:    [[TMP1625:%.*]] = load i64, ptr [[LE]], align 8
34020 // SIMD-ONLY0-NEXT:    [[CMP3321:%.*]] = icmp eq i64 [[TMP1624]], [[TMP1625]]
34021 // SIMD-ONLY0-NEXT:    br i1 [[CMP3321]], label [[COND_TRUE3323:%.*]], label [[COND_FALSE3324:%.*]]
34022 // SIMD-ONLY0:       cond.true3323:
34023 // SIMD-ONLY0-NEXT:    [[TMP1626:%.*]] = load i64, ptr [[LD]], align 8
34024 // SIMD-ONLY0-NEXT:    br label [[COND_END3325:%.*]]
34025 // SIMD-ONLY0:       cond.false3324:
34026 // SIMD-ONLY0-NEXT:    [[TMP1627:%.*]] = load i64, ptr [[LX]], align 8
34027 // SIMD-ONLY0-NEXT:    br label [[COND_END3325]]
34028 // SIMD-ONLY0:       cond.end3325:
34029 // SIMD-ONLY0-NEXT:    [[COND3326:%.*]] = phi i64 [ [[TMP1626]], [[COND_TRUE3323]] ], [ [[TMP1627]], [[COND_FALSE3324]] ]
34030 // SIMD-ONLY0-NEXT:    store i64 [[COND3326]], ptr [[LX]], align 8
34031 // SIMD-ONLY0-NEXT:    [[TMP1628:%.*]] = load i64, ptr [[LE]], align 8
34032 // SIMD-ONLY0-NEXT:    [[TMP1629:%.*]] = load i64, ptr [[LX]], align 8
34033 // SIMD-ONLY0-NEXT:    [[CMP3327:%.*]] = icmp eq i64 [[TMP1628]], [[TMP1629]]
34034 // SIMD-ONLY0-NEXT:    br i1 [[CMP3327]], label [[COND_TRUE3329:%.*]], label [[COND_FALSE3330:%.*]]
34035 // SIMD-ONLY0:       cond.true3329:
34036 // SIMD-ONLY0-NEXT:    [[TMP1630:%.*]] = load i64, ptr [[LD]], align 8
34037 // SIMD-ONLY0-NEXT:    br label [[COND_END3331:%.*]]
34038 // SIMD-ONLY0:       cond.false3330:
34039 // SIMD-ONLY0-NEXT:    [[TMP1631:%.*]] = load i64, ptr [[LX]], align 8
34040 // SIMD-ONLY0-NEXT:    br label [[COND_END3331]]
34041 // SIMD-ONLY0:       cond.end3331:
34042 // SIMD-ONLY0-NEXT:    [[COND3332:%.*]] = phi i64 [ [[TMP1630]], [[COND_TRUE3329]] ], [ [[TMP1631]], [[COND_FALSE3330]] ]
34043 // SIMD-ONLY0-NEXT:    store i64 [[COND3332]], ptr [[LX]], align 8
34044 // SIMD-ONLY0-NEXT:    [[TMP1632:%.*]] = load i64, ptr [[LX]], align 8
34045 // SIMD-ONLY0-NEXT:    [[TMP1633:%.*]] = load i64, ptr [[LE]], align 8
34046 // SIMD-ONLY0-NEXT:    [[CMP3333:%.*]] = icmp eq i64 [[TMP1632]], [[TMP1633]]
34047 // SIMD-ONLY0-NEXT:    br i1 [[CMP3333]], label [[IF_THEN3335:%.*]], label [[IF_END3336:%.*]]
34048 // SIMD-ONLY0:       if.then3335:
34049 // SIMD-ONLY0-NEXT:    [[TMP1634:%.*]] = load i64, ptr [[LD]], align 8
34050 // SIMD-ONLY0-NEXT:    store i64 [[TMP1634]], ptr [[LX]], align 8
34051 // SIMD-ONLY0-NEXT:    br label [[IF_END3336]]
34052 // SIMD-ONLY0:       if.end3336:
34053 // SIMD-ONLY0-NEXT:    [[TMP1635:%.*]] = load i64, ptr [[LE]], align 8
34054 // SIMD-ONLY0-NEXT:    [[TMP1636:%.*]] = load i64, ptr [[LX]], align 8
34055 // SIMD-ONLY0-NEXT:    [[CMP3337:%.*]] = icmp eq i64 [[TMP1635]], [[TMP1636]]
34056 // SIMD-ONLY0-NEXT:    br i1 [[CMP3337]], label [[IF_THEN3339:%.*]], label [[IF_END3340:%.*]]
34057 // SIMD-ONLY0:       if.then3339:
34058 // SIMD-ONLY0-NEXT:    [[TMP1637:%.*]] = load i64, ptr [[LD]], align 8
34059 // SIMD-ONLY0-NEXT:    store i64 [[TMP1637]], ptr [[LX]], align 8
34060 // SIMD-ONLY0-NEXT:    br label [[IF_END3340]]
34061 // SIMD-ONLY0:       if.end3340:
34062 // SIMD-ONLY0-NEXT:    [[TMP1638:%.*]] = load i64, ptr [[ULX]], align 8
34063 // SIMD-ONLY0-NEXT:    [[TMP1639:%.*]] = load i64, ptr [[ULE]], align 8
34064 // SIMD-ONLY0-NEXT:    [[CMP3341:%.*]] = icmp ugt i64 [[TMP1638]], [[TMP1639]]
34065 // SIMD-ONLY0-NEXT:    br i1 [[CMP3341]], label [[COND_TRUE3343:%.*]], label [[COND_FALSE3344:%.*]]
34066 // SIMD-ONLY0:       cond.true3343:
34067 // SIMD-ONLY0-NEXT:    [[TMP1640:%.*]] = load i64, ptr [[ULE]], align 8
34068 // SIMD-ONLY0-NEXT:    br label [[COND_END3345:%.*]]
34069 // SIMD-ONLY0:       cond.false3344:
34070 // SIMD-ONLY0-NEXT:    [[TMP1641:%.*]] = load i64, ptr [[ULX]], align 8
34071 // SIMD-ONLY0-NEXT:    br label [[COND_END3345]]
34072 // SIMD-ONLY0:       cond.end3345:
34073 // SIMD-ONLY0-NEXT:    [[COND3346:%.*]] = phi i64 [ [[TMP1640]], [[COND_TRUE3343]] ], [ [[TMP1641]], [[COND_FALSE3344]] ]
34074 // SIMD-ONLY0-NEXT:    store i64 [[COND3346]], ptr [[ULX]], align 8
34075 // SIMD-ONLY0-NEXT:    [[TMP1642:%.*]] = load i64, ptr [[ULX]], align 8
34076 // SIMD-ONLY0-NEXT:    [[TMP1643:%.*]] = load i64, ptr [[ULE]], align 8
34077 // SIMD-ONLY0-NEXT:    [[CMP3347:%.*]] = icmp ult i64 [[TMP1642]], [[TMP1643]]
34078 // SIMD-ONLY0-NEXT:    br i1 [[CMP3347]], label [[COND_TRUE3349:%.*]], label [[COND_FALSE3350:%.*]]
34079 // SIMD-ONLY0:       cond.true3349:
34080 // SIMD-ONLY0-NEXT:    [[TMP1644:%.*]] = load i64, ptr [[ULE]], align 8
34081 // SIMD-ONLY0-NEXT:    br label [[COND_END3351:%.*]]
34082 // SIMD-ONLY0:       cond.false3350:
34083 // SIMD-ONLY0-NEXT:    [[TMP1645:%.*]] = load i64, ptr [[ULX]], align 8
34084 // SIMD-ONLY0-NEXT:    br label [[COND_END3351]]
34085 // SIMD-ONLY0:       cond.end3351:
34086 // SIMD-ONLY0-NEXT:    [[COND3352:%.*]] = phi i64 [ [[TMP1644]], [[COND_TRUE3349]] ], [ [[TMP1645]], [[COND_FALSE3350]] ]
34087 // SIMD-ONLY0-NEXT:    store i64 [[COND3352]], ptr [[ULX]], align 8
34088 // SIMD-ONLY0-NEXT:    [[TMP1646:%.*]] = load i64, ptr [[ULE]], align 8
34089 // SIMD-ONLY0-NEXT:    [[TMP1647:%.*]] = load i64, ptr [[ULX]], align 8
34090 // SIMD-ONLY0-NEXT:    [[CMP3353:%.*]] = icmp ugt i64 [[TMP1646]], [[TMP1647]]
34091 // SIMD-ONLY0-NEXT:    br i1 [[CMP3353]], label [[COND_TRUE3355:%.*]], label [[COND_FALSE3356:%.*]]
34092 // SIMD-ONLY0:       cond.true3355:
34093 // SIMD-ONLY0-NEXT:    [[TMP1648:%.*]] = load i64, ptr [[ULE]], align 8
34094 // SIMD-ONLY0-NEXT:    br label [[COND_END3357:%.*]]
34095 // SIMD-ONLY0:       cond.false3356:
34096 // SIMD-ONLY0-NEXT:    [[TMP1649:%.*]] = load i64, ptr [[ULX]], align 8
34097 // SIMD-ONLY0-NEXT:    br label [[COND_END3357]]
34098 // SIMD-ONLY0:       cond.end3357:
34099 // SIMD-ONLY0-NEXT:    [[COND3358:%.*]] = phi i64 [ [[TMP1648]], [[COND_TRUE3355]] ], [ [[TMP1649]], [[COND_FALSE3356]] ]
34100 // SIMD-ONLY0-NEXT:    store i64 [[COND3358]], ptr [[ULX]], align 8
34101 // SIMD-ONLY0-NEXT:    [[TMP1650:%.*]] = load i64, ptr [[ULE]], align 8
34102 // SIMD-ONLY0-NEXT:    [[TMP1651:%.*]] = load i64, ptr [[ULX]], align 8
34103 // SIMD-ONLY0-NEXT:    [[CMP3359:%.*]] = icmp ult i64 [[TMP1650]], [[TMP1651]]
34104 // SIMD-ONLY0-NEXT:    br i1 [[CMP3359]], label [[COND_TRUE3361:%.*]], label [[COND_FALSE3362:%.*]]
34105 // SIMD-ONLY0:       cond.true3361:
34106 // SIMD-ONLY0-NEXT:    [[TMP1652:%.*]] = load i64, ptr [[ULE]], align 8
34107 // SIMD-ONLY0-NEXT:    br label [[COND_END3363:%.*]]
34108 // SIMD-ONLY0:       cond.false3362:
34109 // SIMD-ONLY0-NEXT:    [[TMP1653:%.*]] = load i64, ptr [[ULX]], align 8
34110 // SIMD-ONLY0-NEXT:    br label [[COND_END3363]]
34111 // SIMD-ONLY0:       cond.end3363:
34112 // SIMD-ONLY0-NEXT:    [[COND3364:%.*]] = phi i64 [ [[TMP1652]], [[COND_TRUE3361]] ], [ [[TMP1653]], [[COND_FALSE3362]] ]
34113 // SIMD-ONLY0-NEXT:    store i64 [[COND3364]], ptr [[ULX]], align 8
34114 // SIMD-ONLY0-NEXT:    [[TMP1654:%.*]] = load i64, ptr [[ULX]], align 8
34115 // SIMD-ONLY0-NEXT:    [[TMP1655:%.*]] = load i64, ptr [[ULE]], align 8
34116 // SIMD-ONLY0-NEXT:    [[CMP3365:%.*]] = icmp ugt i64 [[TMP1654]], [[TMP1655]]
34117 // SIMD-ONLY0-NEXT:    br i1 [[CMP3365]], label [[IF_THEN3367:%.*]], label [[IF_END3368:%.*]]
34118 // SIMD-ONLY0:       if.then3367:
34119 // SIMD-ONLY0-NEXT:    [[TMP1656:%.*]] = load i64, ptr [[ULE]], align 8
34120 // SIMD-ONLY0-NEXT:    store i64 [[TMP1656]], ptr [[ULX]], align 8
34121 // SIMD-ONLY0-NEXT:    br label [[IF_END3368]]
34122 // SIMD-ONLY0:       if.end3368:
34123 // SIMD-ONLY0-NEXT:    [[TMP1657:%.*]] = load i64, ptr [[ULX]], align 8
34124 // SIMD-ONLY0-NEXT:    [[TMP1658:%.*]] = load i64, ptr [[ULE]], align 8
34125 // SIMD-ONLY0-NEXT:    [[CMP3369:%.*]] = icmp ult i64 [[TMP1657]], [[TMP1658]]
34126 // SIMD-ONLY0-NEXT:    br i1 [[CMP3369]], label [[IF_THEN3371:%.*]], label [[IF_END3372:%.*]]
34127 // SIMD-ONLY0:       if.then3371:
34128 // SIMD-ONLY0-NEXT:    [[TMP1659:%.*]] = load i64, ptr [[ULE]], align 8
34129 // SIMD-ONLY0-NEXT:    store i64 [[TMP1659]], ptr [[ULX]], align 8
34130 // SIMD-ONLY0-NEXT:    br label [[IF_END3372]]
34131 // SIMD-ONLY0:       if.end3372:
34132 // SIMD-ONLY0-NEXT:    [[TMP1660:%.*]] = load i64, ptr [[ULE]], align 8
34133 // SIMD-ONLY0-NEXT:    [[TMP1661:%.*]] = load i64, ptr [[ULX]], align 8
34134 // SIMD-ONLY0-NEXT:    [[CMP3373:%.*]] = icmp ugt i64 [[TMP1660]], [[TMP1661]]
34135 // SIMD-ONLY0-NEXT:    br i1 [[CMP3373]], label [[IF_THEN3375:%.*]], label [[IF_END3376:%.*]]
34136 // SIMD-ONLY0:       if.then3375:
34137 // SIMD-ONLY0-NEXT:    [[TMP1662:%.*]] = load i64, ptr [[ULE]], align 8
34138 // SIMD-ONLY0-NEXT:    store i64 [[TMP1662]], ptr [[ULX]], align 8
34139 // SIMD-ONLY0-NEXT:    br label [[IF_END3376]]
34140 // SIMD-ONLY0:       if.end3376:
34141 // SIMD-ONLY0-NEXT:    [[TMP1663:%.*]] = load i64, ptr [[ULE]], align 8
34142 // SIMD-ONLY0-NEXT:    [[TMP1664:%.*]] = load i64, ptr [[ULX]], align 8
34143 // SIMD-ONLY0-NEXT:    [[CMP3377:%.*]] = icmp ult i64 [[TMP1663]], [[TMP1664]]
34144 // SIMD-ONLY0-NEXT:    br i1 [[CMP3377]], label [[IF_THEN3379:%.*]], label [[IF_END3380:%.*]]
34145 // SIMD-ONLY0:       if.then3379:
34146 // SIMD-ONLY0-NEXT:    [[TMP1665:%.*]] = load i64, ptr [[ULE]], align 8
34147 // SIMD-ONLY0-NEXT:    store i64 [[TMP1665]], ptr [[ULX]], align 8
34148 // SIMD-ONLY0-NEXT:    br label [[IF_END3380]]
34149 // SIMD-ONLY0:       if.end3380:
34150 // SIMD-ONLY0-NEXT:    [[TMP1666:%.*]] = load i64, ptr [[ULX]], align 8
34151 // SIMD-ONLY0-NEXT:    [[TMP1667:%.*]] = load i64, ptr [[ULE]], align 8
34152 // SIMD-ONLY0-NEXT:    [[CMP3381:%.*]] = icmp eq i64 [[TMP1666]], [[TMP1667]]
34153 // SIMD-ONLY0-NEXT:    br i1 [[CMP3381]], label [[COND_TRUE3383:%.*]], label [[COND_FALSE3384:%.*]]
34154 // SIMD-ONLY0:       cond.true3383:
34155 // SIMD-ONLY0-NEXT:    [[TMP1668:%.*]] = load i64, ptr [[ULD]], align 8
34156 // SIMD-ONLY0-NEXT:    br label [[COND_END3385:%.*]]
34157 // SIMD-ONLY0:       cond.false3384:
34158 // SIMD-ONLY0-NEXT:    [[TMP1669:%.*]] = load i64, ptr [[ULX]], align 8
34159 // SIMD-ONLY0-NEXT:    br label [[COND_END3385]]
34160 // SIMD-ONLY0:       cond.end3385:
34161 // SIMD-ONLY0-NEXT:    [[COND3386:%.*]] = phi i64 [ [[TMP1668]], [[COND_TRUE3383]] ], [ [[TMP1669]], [[COND_FALSE3384]] ]
34162 // SIMD-ONLY0-NEXT:    store i64 [[COND3386]], ptr [[ULX]], align 8
34163 // SIMD-ONLY0-NEXT:    [[TMP1670:%.*]] = load i64, ptr [[ULE]], align 8
34164 // SIMD-ONLY0-NEXT:    [[TMP1671:%.*]] = load i64, ptr [[ULX]], align 8
34165 // SIMD-ONLY0-NEXT:    [[CMP3387:%.*]] = icmp eq i64 [[TMP1670]], [[TMP1671]]
34166 // SIMD-ONLY0-NEXT:    br i1 [[CMP3387]], label [[COND_TRUE3389:%.*]], label [[COND_FALSE3390:%.*]]
34167 // SIMD-ONLY0:       cond.true3389:
34168 // SIMD-ONLY0-NEXT:    [[TMP1672:%.*]] = load i64, ptr [[ULD]], align 8
34169 // SIMD-ONLY0-NEXT:    br label [[COND_END3391:%.*]]
34170 // SIMD-ONLY0:       cond.false3390:
34171 // SIMD-ONLY0-NEXT:    [[TMP1673:%.*]] = load i64, ptr [[ULX]], align 8
34172 // SIMD-ONLY0-NEXT:    br label [[COND_END3391]]
34173 // SIMD-ONLY0:       cond.end3391:
34174 // SIMD-ONLY0-NEXT:    [[COND3392:%.*]] = phi i64 [ [[TMP1672]], [[COND_TRUE3389]] ], [ [[TMP1673]], [[COND_FALSE3390]] ]
34175 // SIMD-ONLY0-NEXT:    store i64 [[COND3392]], ptr [[ULX]], align 8
34176 // SIMD-ONLY0-NEXT:    [[TMP1674:%.*]] = load i64, ptr [[ULX]], align 8
34177 // SIMD-ONLY0-NEXT:    [[TMP1675:%.*]] = load i64, ptr [[ULE]], align 8
34178 // SIMD-ONLY0-NEXT:    [[CMP3393:%.*]] = icmp eq i64 [[TMP1674]], [[TMP1675]]
34179 // SIMD-ONLY0-NEXT:    br i1 [[CMP3393]], label [[IF_THEN3395:%.*]], label [[IF_END3396:%.*]]
34180 // SIMD-ONLY0:       if.then3395:
34181 // SIMD-ONLY0-NEXT:    [[TMP1676:%.*]] = load i64, ptr [[ULD]], align 8
34182 // SIMD-ONLY0-NEXT:    store i64 [[TMP1676]], ptr [[ULX]], align 8
34183 // SIMD-ONLY0-NEXT:    br label [[IF_END3396]]
34184 // SIMD-ONLY0:       if.end3396:
34185 // SIMD-ONLY0-NEXT:    [[TMP1677:%.*]] = load i64, ptr [[ULE]], align 8
34186 // SIMD-ONLY0-NEXT:    [[TMP1678:%.*]] = load i64, ptr [[ULX]], align 8
34187 // SIMD-ONLY0-NEXT:    [[CMP3397:%.*]] = icmp eq i64 [[TMP1677]], [[TMP1678]]
34188 // SIMD-ONLY0-NEXT:    br i1 [[CMP3397]], label [[IF_THEN3399:%.*]], label [[IF_END3400:%.*]]
34189 // SIMD-ONLY0:       if.then3399:
34190 // SIMD-ONLY0-NEXT:    [[TMP1679:%.*]] = load i64, ptr [[ULD]], align 8
34191 // SIMD-ONLY0-NEXT:    store i64 [[TMP1679]], ptr [[ULX]], align 8
34192 // SIMD-ONLY0-NEXT:    br label [[IF_END3400]]
34193 // SIMD-ONLY0:       if.end3400:
34194 // SIMD-ONLY0-NEXT:    [[TMP1680:%.*]] = load i64, ptr [[LX]], align 8
34195 // SIMD-ONLY0-NEXT:    [[TMP1681:%.*]] = load i64, ptr [[LE]], align 8
34196 // SIMD-ONLY0-NEXT:    [[CMP3401:%.*]] = icmp sgt i64 [[TMP1680]], [[TMP1681]]
34197 // SIMD-ONLY0-NEXT:    br i1 [[CMP3401]], label [[COND_TRUE3403:%.*]], label [[COND_FALSE3404:%.*]]
34198 // SIMD-ONLY0:       cond.true3403:
34199 // SIMD-ONLY0-NEXT:    [[TMP1682:%.*]] = load i64, ptr [[LE]], align 8
34200 // SIMD-ONLY0-NEXT:    br label [[COND_END3405:%.*]]
34201 // SIMD-ONLY0:       cond.false3404:
34202 // SIMD-ONLY0-NEXT:    [[TMP1683:%.*]] = load i64, ptr [[LX]], align 8
34203 // SIMD-ONLY0-NEXT:    br label [[COND_END3405]]
34204 // SIMD-ONLY0:       cond.end3405:
34205 // SIMD-ONLY0-NEXT:    [[COND3406:%.*]] = phi i64 [ [[TMP1682]], [[COND_TRUE3403]] ], [ [[TMP1683]], [[COND_FALSE3404]] ]
34206 // SIMD-ONLY0-NEXT:    store i64 [[COND3406]], ptr [[LX]], align 8
34207 // SIMD-ONLY0-NEXT:    [[TMP1684:%.*]] = load i64, ptr [[LX]], align 8
34208 // SIMD-ONLY0-NEXT:    [[TMP1685:%.*]] = load i64, ptr [[LE]], align 8
34209 // SIMD-ONLY0-NEXT:    [[CMP3407:%.*]] = icmp slt i64 [[TMP1684]], [[TMP1685]]
34210 // SIMD-ONLY0-NEXT:    br i1 [[CMP3407]], label [[COND_TRUE3409:%.*]], label [[COND_FALSE3410:%.*]]
34211 // SIMD-ONLY0:       cond.true3409:
34212 // SIMD-ONLY0-NEXT:    [[TMP1686:%.*]] = load i64, ptr [[LE]], align 8
34213 // SIMD-ONLY0-NEXT:    br label [[COND_END3411:%.*]]
34214 // SIMD-ONLY0:       cond.false3410:
34215 // SIMD-ONLY0-NEXT:    [[TMP1687:%.*]] = load i64, ptr [[LX]], align 8
34216 // SIMD-ONLY0-NEXT:    br label [[COND_END3411]]
34217 // SIMD-ONLY0:       cond.end3411:
34218 // SIMD-ONLY0-NEXT:    [[COND3412:%.*]] = phi i64 [ [[TMP1686]], [[COND_TRUE3409]] ], [ [[TMP1687]], [[COND_FALSE3410]] ]
34219 // SIMD-ONLY0-NEXT:    store i64 [[COND3412]], ptr [[LX]], align 8
34220 // SIMD-ONLY0-NEXT:    [[TMP1688:%.*]] = load i64, ptr [[LE]], align 8
34221 // SIMD-ONLY0-NEXT:    [[TMP1689:%.*]] = load i64, ptr [[LX]], align 8
34222 // SIMD-ONLY0-NEXT:    [[CMP3413:%.*]] = icmp sgt i64 [[TMP1688]], [[TMP1689]]
34223 // SIMD-ONLY0-NEXT:    br i1 [[CMP3413]], label [[COND_TRUE3415:%.*]], label [[COND_FALSE3416:%.*]]
34224 // SIMD-ONLY0:       cond.true3415:
34225 // SIMD-ONLY0-NEXT:    [[TMP1690:%.*]] = load i64, ptr [[LE]], align 8
34226 // SIMD-ONLY0-NEXT:    br label [[COND_END3417:%.*]]
34227 // SIMD-ONLY0:       cond.false3416:
34228 // SIMD-ONLY0-NEXT:    [[TMP1691:%.*]] = load i64, ptr [[LX]], align 8
34229 // SIMD-ONLY0-NEXT:    br label [[COND_END3417]]
34230 // SIMD-ONLY0:       cond.end3417:
34231 // SIMD-ONLY0-NEXT:    [[COND3418:%.*]] = phi i64 [ [[TMP1690]], [[COND_TRUE3415]] ], [ [[TMP1691]], [[COND_FALSE3416]] ]
34232 // SIMD-ONLY0-NEXT:    store i64 [[COND3418]], ptr [[LX]], align 8
34233 // SIMD-ONLY0-NEXT:    [[TMP1692:%.*]] = load i64, ptr [[LE]], align 8
34234 // SIMD-ONLY0-NEXT:    [[TMP1693:%.*]] = load i64, ptr [[LX]], align 8
34235 // SIMD-ONLY0-NEXT:    [[CMP3419:%.*]] = icmp slt i64 [[TMP1692]], [[TMP1693]]
34236 // SIMD-ONLY0-NEXT:    br i1 [[CMP3419]], label [[COND_TRUE3421:%.*]], label [[COND_FALSE3422:%.*]]
34237 // SIMD-ONLY0:       cond.true3421:
34238 // SIMD-ONLY0-NEXT:    [[TMP1694:%.*]] = load i64, ptr [[LE]], align 8
34239 // SIMD-ONLY0-NEXT:    br label [[COND_END3423:%.*]]
34240 // SIMD-ONLY0:       cond.false3422:
34241 // SIMD-ONLY0-NEXT:    [[TMP1695:%.*]] = load i64, ptr [[LX]], align 8
34242 // SIMD-ONLY0-NEXT:    br label [[COND_END3423]]
34243 // SIMD-ONLY0:       cond.end3423:
34244 // SIMD-ONLY0-NEXT:    [[COND3424:%.*]] = phi i64 [ [[TMP1694]], [[COND_TRUE3421]] ], [ [[TMP1695]], [[COND_FALSE3422]] ]
34245 // SIMD-ONLY0-NEXT:    store i64 [[COND3424]], ptr [[LX]], align 8
34246 // SIMD-ONLY0-NEXT:    [[TMP1696:%.*]] = load i64, ptr [[LX]], align 8
34247 // SIMD-ONLY0-NEXT:    [[TMP1697:%.*]] = load i64, ptr [[LE]], align 8
34248 // SIMD-ONLY0-NEXT:    [[CMP3425:%.*]] = icmp sgt i64 [[TMP1696]], [[TMP1697]]
34249 // SIMD-ONLY0-NEXT:    br i1 [[CMP3425]], label [[IF_THEN3427:%.*]], label [[IF_END3428:%.*]]
34250 // SIMD-ONLY0:       if.then3427:
34251 // SIMD-ONLY0-NEXT:    [[TMP1698:%.*]] = load i64, ptr [[LE]], align 8
34252 // SIMD-ONLY0-NEXT:    store i64 [[TMP1698]], ptr [[LX]], align 8
34253 // SIMD-ONLY0-NEXT:    br label [[IF_END3428]]
34254 // SIMD-ONLY0:       if.end3428:
34255 // SIMD-ONLY0-NEXT:    [[TMP1699:%.*]] = load i64, ptr [[LX]], align 8
34256 // SIMD-ONLY0-NEXT:    [[TMP1700:%.*]] = load i64, ptr [[LE]], align 8
34257 // SIMD-ONLY0-NEXT:    [[CMP3429:%.*]] = icmp slt i64 [[TMP1699]], [[TMP1700]]
34258 // SIMD-ONLY0-NEXT:    br i1 [[CMP3429]], label [[IF_THEN3431:%.*]], label [[IF_END3432:%.*]]
34259 // SIMD-ONLY0:       if.then3431:
34260 // SIMD-ONLY0-NEXT:    [[TMP1701:%.*]] = load i64, ptr [[LE]], align 8
34261 // SIMD-ONLY0-NEXT:    store i64 [[TMP1701]], ptr [[LX]], align 8
34262 // SIMD-ONLY0-NEXT:    br label [[IF_END3432]]
34263 // SIMD-ONLY0:       if.end3432:
34264 // SIMD-ONLY0-NEXT:    [[TMP1702:%.*]] = load i64, ptr [[LE]], align 8
34265 // SIMD-ONLY0-NEXT:    [[TMP1703:%.*]] = load i64, ptr [[LX]], align 8
34266 // SIMD-ONLY0-NEXT:    [[CMP3433:%.*]] = icmp sgt i64 [[TMP1702]], [[TMP1703]]
34267 // SIMD-ONLY0-NEXT:    br i1 [[CMP3433]], label [[IF_THEN3435:%.*]], label [[IF_END3436:%.*]]
34268 // SIMD-ONLY0:       if.then3435:
34269 // SIMD-ONLY0-NEXT:    [[TMP1704:%.*]] = load i64, ptr [[LE]], align 8
34270 // SIMD-ONLY0-NEXT:    store i64 [[TMP1704]], ptr [[LX]], align 8
34271 // SIMD-ONLY0-NEXT:    br label [[IF_END3436]]
34272 // SIMD-ONLY0:       if.end3436:
34273 // SIMD-ONLY0-NEXT:    [[TMP1705:%.*]] = load i64, ptr [[LE]], align 8
34274 // SIMD-ONLY0-NEXT:    [[TMP1706:%.*]] = load i64, ptr [[LX]], align 8
34275 // SIMD-ONLY0-NEXT:    [[CMP3437:%.*]] = icmp slt i64 [[TMP1705]], [[TMP1706]]
34276 // SIMD-ONLY0-NEXT:    br i1 [[CMP3437]], label [[IF_THEN3439:%.*]], label [[IF_END3440:%.*]]
34277 // SIMD-ONLY0:       if.then3439:
34278 // SIMD-ONLY0-NEXT:    [[TMP1707:%.*]] = load i64, ptr [[LE]], align 8
34279 // SIMD-ONLY0-NEXT:    store i64 [[TMP1707]], ptr [[LX]], align 8
34280 // SIMD-ONLY0-NEXT:    br label [[IF_END3440]]
34281 // SIMD-ONLY0:       if.end3440:
34282 // SIMD-ONLY0-NEXT:    [[TMP1708:%.*]] = load i64, ptr [[LX]], align 8
34283 // SIMD-ONLY0-NEXT:    [[TMP1709:%.*]] = load i64, ptr [[LE]], align 8
34284 // SIMD-ONLY0-NEXT:    [[CMP3441:%.*]] = icmp eq i64 [[TMP1708]], [[TMP1709]]
34285 // SIMD-ONLY0-NEXT:    br i1 [[CMP3441]], label [[COND_TRUE3443:%.*]], label [[COND_FALSE3444:%.*]]
34286 // SIMD-ONLY0:       cond.true3443:
34287 // SIMD-ONLY0-NEXT:    [[TMP1710:%.*]] = load i64, ptr [[LD]], align 8
34288 // SIMD-ONLY0-NEXT:    br label [[COND_END3445:%.*]]
34289 // SIMD-ONLY0:       cond.false3444:
34290 // SIMD-ONLY0-NEXT:    [[TMP1711:%.*]] = load i64, ptr [[LX]], align 8
34291 // SIMD-ONLY0-NEXT:    br label [[COND_END3445]]
34292 // SIMD-ONLY0:       cond.end3445:
34293 // SIMD-ONLY0-NEXT:    [[COND3446:%.*]] = phi i64 [ [[TMP1710]], [[COND_TRUE3443]] ], [ [[TMP1711]], [[COND_FALSE3444]] ]
34294 // SIMD-ONLY0-NEXT:    store i64 [[COND3446]], ptr [[LX]], align 8
34295 // SIMD-ONLY0-NEXT:    [[TMP1712:%.*]] = load i64, ptr [[LE]], align 8
34296 // SIMD-ONLY0-NEXT:    [[TMP1713:%.*]] = load i64, ptr [[LX]], align 8
34297 // SIMD-ONLY0-NEXT:    [[CMP3447:%.*]] = icmp eq i64 [[TMP1712]], [[TMP1713]]
34298 // SIMD-ONLY0-NEXT:    br i1 [[CMP3447]], label [[COND_TRUE3449:%.*]], label [[COND_FALSE3450:%.*]]
34299 // SIMD-ONLY0:       cond.true3449:
34300 // SIMD-ONLY0-NEXT:    [[TMP1714:%.*]] = load i64, ptr [[LD]], align 8
34301 // SIMD-ONLY0-NEXT:    br label [[COND_END3451:%.*]]
34302 // SIMD-ONLY0:       cond.false3450:
34303 // SIMD-ONLY0-NEXT:    [[TMP1715:%.*]] = load i64, ptr [[LX]], align 8
34304 // SIMD-ONLY0-NEXT:    br label [[COND_END3451]]
34305 // SIMD-ONLY0:       cond.end3451:
34306 // SIMD-ONLY0-NEXT:    [[COND3452:%.*]] = phi i64 [ [[TMP1714]], [[COND_TRUE3449]] ], [ [[TMP1715]], [[COND_FALSE3450]] ]
34307 // SIMD-ONLY0-NEXT:    store i64 [[COND3452]], ptr [[LX]], align 8
34308 // SIMD-ONLY0-NEXT:    [[TMP1716:%.*]] = load i64, ptr [[LX]], align 8
34309 // SIMD-ONLY0-NEXT:    [[TMP1717:%.*]] = load i64, ptr [[LE]], align 8
34310 // SIMD-ONLY0-NEXT:    [[CMP3453:%.*]] = icmp eq i64 [[TMP1716]], [[TMP1717]]
34311 // SIMD-ONLY0-NEXT:    br i1 [[CMP3453]], label [[IF_THEN3455:%.*]], label [[IF_END3456:%.*]]
34312 // SIMD-ONLY0:       if.then3455:
34313 // SIMD-ONLY0-NEXT:    [[TMP1718:%.*]] = load i64, ptr [[LD]], align 8
34314 // SIMD-ONLY0-NEXT:    store i64 [[TMP1718]], ptr [[LX]], align 8
34315 // SIMD-ONLY0-NEXT:    br label [[IF_END3456]]
34316 // SIMD-ONLY0:       if.end3456:
34317 // SIMD-ONLY0-NEXT:    [[TMP1719:%.*]] = load i64, ptr [[LE]], align 8
34318 // SIMD-ONLY0-NEXT:    [[TMP1720:%.*]] = load i64, ptr [[LX]], align 8
34319 // SIMD-ONLY0-NEXT:    [[CMP3457:%.*]] = icmp eq i64 [[TMP1719]], [[TMP1720]]
34320 // SIMD-ONLY0-NEXT:    br i1 [[CMP3457]], label [[IF_THEN3459:%.*]], label [[IF_END3460:%.*]]
34321 // SIMD-ONLY0:       if.then3459:
34322 // SIMD-ONLY0-NEXT:    [[TMP1721:%.*]] = load i64, ptr [[LD]], align 8
34323 // SIMD-ONLY0-NEXT:    store i64 [[TMP1721]], ptr [[LX]], align 8
34324 // SIMD-ONLY0-NEXT:    br label [[IF_END3460]]
34325 // SIMD-ONLY0:       if.end3460:
34326 // SIMD-ONLY0-NEXT:    [[TMP1722:%.*]] = load i64, ptr [[ULX]], align 8
34327 // SIMD-ONLY0-NEXT:    [[TMP1723:%.*]] = load i64, ptr [[ULE]], align 8
34328 // SIMD-ONLY0-NEXT:    [[CMP3461:%.*]] = icmp ugt i64 [[TMP1722]], [[TMP1723]]
34329 // SIMD-ONLY0-NEXT:    br i1 [[CMP3461]], label [[COND_TRUE3463:%.*]], label [[COND_FALSE3464:%.*]]
34330 // SIMD-ONLY0:       cond.true3463:
34331 // SIMD-ONLY0-NEXT:    [[TMP1724:%.*]] = load i64, ptr [[ULE]], align 8
34332 // SIMD-ONLY0-NEXT:    br label [[COND_END3465:%.*]]
34333 // SIMD-ONLY0:       cond.false3464:
34334 // SIMD-ONLY0-NEXT:    [[TMP1725:%.*]] = load i64, ptr [[ULX]], align 8
34335 // SIMD-ONLY0-NEXT:    br label [[COND_END3465]]
34336 // SIMD-ONLY0:       cond.end3465:
34337 // SIMD-ONLY0-NEXT:    [[COND3466:%.*]] = phi i64 [ [[TMP1724]], [[COND_TRUE3463]] ], [ [[TMP1725]], [[COND_FALSE3464]] ]
34338 // SIMD-ONLY0-NEXT:    store i64 [[COND3466]], ptr [[ULX]], align 8
34339 // SIMD-ONLY0-NEXT:    [[TMP1726:%.*]] = load i64, ptr [[ULX]], align 8
34340 // SIMD-ONLY0-NEXT:    [[TMP1727:%.*]] = load i64, ptr [[ULE]], align 8
34341 // SIMD-ONLY0-NEXT:    [[CMP3467:%.*]] = icmp ult i64 [[TMP1726]], [[TMP1727]]
34342 // SIMD-ONLY0-NEXT:    br i1 [[CMP3467]], label [[COND_TRUE3469:%.*]], label [[COND_FALSE3470:%.*]]
34343 // SIMD-ONLY0:       cond.true3469:
34344 // SIMD-ONLY0-NEXT:    [[TMP1728:%.*]] = load i64, ptr [[ULE]], align 8
34345 // SIMD-ONLY0-NEXT:    br label [[COND_END3471:%.*]]
34346 // SIMD-ONLY0:       cond.false3470:
34347 // SIMD-ONLY0-NEXT:    [[TMP1729:%.*]] = load i64, ptr [[ULX]], align 8
34348 // SIMD-ONLY0-NEXT:    br label [[COND_END3471]]
34349 // SIMD-ONLY0:       cond.end3471:
34350 // SIMD-ONLY0-NEXT:    [[COND3472:%.*]] = phi i64 [ [[TMP1728]], [[COND_TRUE3469]] ], [ [[TMP1729]], [[COND_FALSE3470]] ]
34351 // SIMD-ONLY0-NEXT:    store i64 [[COND3472]], ptr [[ULX]], align 8
34352 // SIMD-ONLY0-NEXT:    [[TMP1730:%.*]] = load i64, ptr [[ULE]], align 8
34353 // SIMD-ONLY0-NEXT:    [[TMP1731:%.*]] = load i64, ptr [[ULX]], align 8
34354 // SIMD-ONLY0-NEXT:    [[CMP3473:%.*]] = icmp ugt i64 [[TMP1730]], [[TMP1731]]
34355 // SIMD-ONLY0-NEXT:    br i1 [[CMP3473]], label [[COND_TRUE3475:%.*]], label [[COND_FALSE3476:%.*]]
34356 // SIMD-ONLY0:       cond.true3475:
34357 // SIMD-ONLY0-NEXT:    [[TMP1732:%.*]] = load i64, ptr [[ULE]], align 8
34358 // SIMD-ONLY0-NEXT:    br label [[COND_END3477:%.*]]
34359 // SIMD-ONLY0:       cond.false3476:
34360 // SIMD-ONLY0-NEXT:    [[TMP1733:%.*]] = load i64, ptr [[ULX]], align 8
34361 // SIMD-ONLY0-NEXT:    br label [[COND_END3477]]
34362 // SIMD-ONLY0:       cond.end3477:
34363 // SIMD-ONLY0-NEXT:    [[COND3478:%.*]] = phi i64 [ [[TMP1732]], [[COND_TRUE3475]] ], [ [[TMP1733]], [[COND_FALSE3476]] ]
34364 // SIMD-ONLY0-NEXT:    store i64 [[COND3478]], ptr [[ULX]], align 8
34365 // SIMD-ONLY0-NEXT:    [[TMP1734:%.*]] = load i64, ptr [[ULE]], align 8
34366 // SIMD-ONLY0-NEXT:    [[TMP1735:%.*]] = load i64, ptr [[ULX]], align 8
34367 // SIMD-ONLY0-NEXT:    [[CMP3479:%.*]] = icmp ult i64 [[TMP1734]], [[TMP1735]]
34368 // SIMD-ONLY0-NEXT:    br i1 [[CMP3479]], label [[COND_TRUE3481:%.*]], label [[COND_FALSE3482:%.*]]
34369 // SIMD-ONLY0:       cond.true3481:
34370 // SIMD-ONLY0-NEXT:    [[TMP1736:%.*]] = load i64, ptr [[ULE]], align 8
34371 // SIMD-ONLY0-NEXT:    br label [[COND_END3483:%.*]]
34372 // SIMD-ONLY0:       cond.false3482:
34373 // SIMD-ONLY0-NEXT:    [[TMP1737:%.*]] = load i64, ptr [[ULX]], align 8
34374 // SIMD-ONLY0-NEXT:    br label [[COND_END3483]]
34375 // SIMD-ONLY0:       cond.end3483:
34376 // SIMD-ONLY0-NEXT:    [[COND3484:%.*]] = phi i64 [ [[TMP1736]], [[COND_TRUE3481]] ], [ [[TMP1737]], [[COND_FALSE3482]] ]
34377 // SIMD-ONLY0-NEXT:    store i64 [[COND3484]], ptr [[ULX]], align 8
34378 // SIMD-ONLY0-NEXT:    [[TMP1738:%.*]] = load i64, ptr [[ULX]], align 8
34379 // SIMD-ONLY0-NEXT:    [[TMP1739:%.*]] = load i64, ptr [[ULE]], align 8
34380 // SIMD-ONLY0-NEXT:    [[CMP3485:%.*]] = icmp ugt i64 [[TMP1738]], [[TMP1739]]
34381 // SIMD-ONLY0-NEXT:    br i1 [[CMP3485]], label [[IF_THEN3487:%.*]], label [[IF_END3488:%.*]]
34382 // SIMD-ONLY0:       if.then3487:
34383 // SIMD-ONLY0-NEXT:    [[TMP1740:%.*]] = load i64, ptr [[ULE]], align 8
34384 // SIMD-ONLY0-NEXT:    store i64 [[TMP1740]], ptr [[ULX]], align 8
34385 // SIMD-ONLY0-NEXT:    br label [[IF_END3488]]
34386 // SIMD-ONLY0:       if.end3488:
34387 // SIMD-ONLY0-NEXT:    [[TMP1741:%.*]] = load i64, ptr [[ULX]], align 8
34388 // SIMD-ONLY0-NEXT:    [[TMP1742:%.*]] = load i64, ptr [[ULE]], align 8
34389 // SIMD-ONLY0-NEXT:    [[CMP3489:%.*]] = icmp ult i64 [[TMP1741]], [[TMP1742]]
34390 // SIMD-ONLY0-NEXT:    br i1 [[CMP3489]], label [[IF_THEN3491:%.*]], label [[IF_END3492:%.*]]
34391 // SIMD-ONLY0:       if.then3491:
34392 // SIMD-ONLY0-NEXT:    [[TMP1743:%.*]] = load i64, ptr [[ULE]], align 8
34393 // SIMD-ONLY0-NEXT:    store i64 [[TMP1743]], ptr [[ULX]], align 8
34394 // SIMD-ONLY0-NEXT:    br label [[IF_END3492]]
34395 // SIMD-ONLY0:       if.end3492:
34396 // SIMD-ONLY0-NEXT:    [[TMP1744:%.*]] = load i64, ptr [[ULE]], align 8
34397 // SIMD-ONLY0-NEXT:    [[TMP1745:%.*]] = load i64, ptr [[ULX]], align 8
34398 // SIMD-ONLY0-NEXT:    [[CMP3493:%.*]] = icmp ugt i64 [[TMP1744]], [[TMP1745]]
34399 // SIMD-ONLY0-NEXT:    br i1 [[CMP3493]], label [[IF_THEN3495:%.*]], label [[IF_END3496:%.*]]
34400 // SIMD-ONLY0:       if.then3495:
34401 // SIMD-ONLY0-NEXT:    [[TMP1746:%.*]] = load i64, ptr [[ULE]], align 8
34402 // SIMD-ONLY0-NEXT:    store i64 [[TMP1746]], ptr [[ULX]], align 8
34403 // SIMD-ONLY0-NEXT:    br label [[IF_END3496]]
34404 // SIMD-ONLY0:       if.end3496:
34405 // SIMD-ONLY0-NEXT:    [[TMP1747:%.*]] = load i64, ptr [[ULE]], align 8
34406 // SIMD-ONLY0-NEXT:    [[TMP1748:%.*]] = load i64, ptr [[ULX]], align 8
34407 // SIMD-ONLY0-NEXT:    [[CMP3497:%.*]] = icmp ult i64 [[TMP1747]], [[TMP1748]]
34408 // SIMD-ONLY0-NEXT:    br i1 [[CMP3497]], label [[IF_THEN3499:%.*]], label [[IF_END3500:%.*]]
34409 // SIMD-ONLY0:       if.then3499:
34410 // SIMD-ONLY0-NEXT:    [[TMP1749:%.*]] = load i64, ptr [[ULE]], align 8
34411 // SIMD-ONLY0-NEXT:    store i64 [[TMP1749]], ptr [[ULX]], align 8
34412 // SIMD-ONLY0-NEXT:    br label [[IF_END3500]]
34413 // SIMD-ONLY0:       if.end3500:
34414 // SIMD-ONLY0-NEXT:    [[TMP1750:%.*]] = load i64, ptr [[ULX]], align 8
34415 // SIMD-ONLY0-NEXT:    [[TMP1751:%.*]] = load i64, ptr [[ULE]], align 8
34416 // SIMD-ONLY0-NEXT:    [[CMP3501:%.*]] = icmp eq i64 [[TMP1750]], [[TMP1751]]
34417 // SIMD-ONLY0-NEXT:    br i1 [[CMP3501]], label [[COND_TRUE3503:%.*]], label [[COND_FALSE3504:%.*]]
34418 // SIMD-ONLY0:       cond.true3503:
34419 // SIMD-ONLY0-NEXT:    [[TMP1752:%.*]] = load i64, ptr [[ULD]], align 8
34420 // SIMD-ONLY0-NEXT:    br label [[COND_END3505:%.*]]
34421 // SIMD-ONLY0:       cond.false3504:
34422 // SIMD-ONLY0-NEXT:    [[TMP1753:%.*]] = load i64, ptr [[ULX]], align 8
34423 // SIMD-ONLY0-NEXT:    br label [[COND_END3505]]
34424 // SIMD-ONLY0:       cond.end3505:
34425 // SIMD-ONLY0-NEXT:    [[COND3506:%.*]] = phi i64 [ [[TMP1752]], [[COND_TRUE3503]] ], [ [[TMP1753]], [[COND_FALSE3504]] ]
34426 // SIMD-ONLY0-NEXT:    store i64 [[COND3506]], ptr [[ULX]], align 8
34427 // SIMD-ONLY0-NEXT:    [[TMP1754:%.*]] = load i64, ptr [[ULE]], align 8
34428 // SIMD-ONLY0-NEXT:    [[TMP1755:%.*]] = load i64, ptr [[ULX]], align 8
34429 // SIMD-ONLY0-NEXT:    [[CMP3507:%.*]] = icmp eq i64 [[TMP1754]], [[TMP1755]]
34430 // SIMD-ONLY0-NEXT:    br i1 [[CMP3507]], label [[COND_TRUE3509:%.*]], label [[COND_FALSE3510:%.*]]
34431 // SIMD-ONLY0:       cond.true3509:
34432 // SIMD-ONLY0-NEXT:    [[TMP1756:%.*]] = load i64, ptr [[ULD]], align 8
34433 // SIMD-ONLY0-NEXT:    br label [[COND_END3511:%.*]]
34434 // SIMD-ONLY0:       cond.false3510:
34435 // SIMD-ONLY0-NEXT:    [[TMP1757:%.*]] = load i64, ptr [[ULX]], align 8
34436 // SIMD-ONLY0-NEXT:    br label [[COND_END3511]]
34437 // SIMD-ONLY0:       cond.end3511:
34438 // SIMD-ONLY0-NEXT:    [[COND3512:%.*]] = phi i64 [ [[TMP1756]], [[COND_TRUE3509]] ], [ [[TMP1757]], [[COND_FALSE3510]] ]
34439 // SIMD-ONLY0-NEXT:    store i64 [[COND3512]], ptr [[ULX]], align 8
34440 // SIMD-ONLY0-NEXT:    [[TMP1758:%.*]] = load i64, ptr [[ULX]], align 8
34441 // SIMD-ONLY0-NEXT:    [[TMP1759:%.*]] = load i64, ptr [[ULE]], align 8
34442 // SIMD-ONLY0-NEXT:    [[CMP3513:%.*]] = icmp eq i64 [[TMP1758]], [[TMP1759]]
34443 // SIMD-ONLY0-NEXT:    br i1 [[CMP3513]], label [[IF_THEN3515:%.*]], label [[IF_END3516:%.*]]
34444 // SIMD-ONLY0:       if.then3515:
34445 // SIMD-ONLY0-NEXT:    [[TMP1760:%.*]] = load i64, ptr [[ULD]], align 8
34446 // SIMD-ONLY0-NEXT:    store i64 [[TMP1760]], ptr [[ULX]], align 8
34447 // SIMD-ONLY0-NEXT:    br label [[IF_END3516]]
34448 // SIMD-ONLY0:       if.end3516:
34449 // SIMD-ONLY0-NEXT:    [[TMP1761:%.*]] = load i64, ptr [[ULE]], align 8
34450 // SIMD-ONLY0-NEXT:    [[TMP1762:%.*]] = load i64, ptr [[ULX]], align 8
34451 // SIMD-ONLY0-NEXT:    [[CMP3517:%.*]] = icmp eq i64 [[TMP1761]], [[TMP1762]]
34452 // SIMD-ONLY0-NEXT:    br i1 [[CMP3517]], label [[IF_THEN3519:%.*]], label [[IF_END3520:%.*]]
34453 // SIMD-ONLY0:       if.then3519:
34454 // SIMD-ONLY0-NEXT:    [[TMP1763:%.*]] = load i64, ptr [[ULD]], align 8
34455 // SIMD-ONLY0-NEXT:    store i64 [[TMP1763]], ptr [[ULX]], align 8
34456 // SIMD-ONLY0-NEXT:    br label [[IF_END3520]]
34457 // SIMD-ONLY0:       if.end3520:
34458 // SIMD-ONLY0-NEXT:    [[TMP1764:%.*]] = load i64, ptr [[LX]], align 8
34459 // SIMD-ONLY0-NEXT:    [[TMP1765:%.*]] = load i64, ptr [[LE]], align 8
34460 // SIMD-ONLY0-NEXT:    [[CMP3521:%.*]] = icmp sgt i64 [[TMP1764]], [[TMP1765]]
34461 // SIMD-ONLY0-NEXT:    br i1 [[CMP3521]], label [[COND_TRUE3523:%.*]], label [[COND_FALSE3524:%.*]]
34462 // SIMD-ONLY0:       cond.true3523:
34463 // SIMD-ONLY0-NEXT:    [[TMP1766:%.*]] = load i64, ptr [[LE]], align 8
34464 // SIMD-ONLY0-NEXT:    br label [[COND_END3525:%.*]]
34465 // SIMD-ONLY0:       cond.false3524:
34466 // SIMD-ONLY0-NEXT:    [[TMP1767:%.*]] = load i64, ptr [[LX]], align 8
34467 // SIMD-ONLY0-NEXT:    br label [[COND_END3525]]
34468 // SIMD-ONLY0:       cond.end3525:
34469 // SIMD-ONLY0-NEXT:    [[COND3526:%.*]] = phi i64 [ [[TMP1766]], [[COND_TRUE3523]] ], [ [[TMP1767]], [[COND_FALSE3524]] ]
34470 // SIMD-ONLY0-NEXT:    store i64 [[COND3526]], ptr [[LX]], align 8
34471 // SIMD-ONLY0-NEXT:    [[TMP1768:%.*]] = load i64, ptr [[LX]], align 8
34472 // SIMD-ONLY0-NEXT:    [[TMP1769:%.*]] = load i64, ptr [[LE]], align 8
34473 // SIMD-ONLY0-NEXT:    [[CMP3527:%.*]] = icmp slt i64 [[TMP1768]], [[TMP1769]]
34474 // SIMD-ONLY0-NEXT:    br i1 [[CMP3527]], label [[COND_TRUE3529:%.*]], label [[COND_FALSE3530:%.*]]
34475 // SIMD-ONLY0:       cond.true3529:
34476 // SIMD-ONLY0-NEXT:    [[TMP1770:%.*]] = load i64, ptr [[LE]], align 8
34477 // SIMD-ONLY0-NEXT:    br label [[COND_END3531:%.*]]
34478 // SIMD-ONLY0:       cond.false3530:
34479 // SIMD-ONLY0-NEXT:    [[TMP1771:%.*]] = load i64, ptr [[LX]], align 8
34480 // SIMD-ONLY0-NEXT:    br label [[COND_END3531]]
34481 // SIMD-ONLY0:       cond.end3531:
34482 // SIMD-ONLY0-NEXT:    [[COND3532:%.*]] = phi i64 [ [[TMP1770]], [[COND_TRUE3529]] ], [ [[TMP1771]], [[COND_FALSE3530]] ]
34483 // SIMD-ONLY0-NEXT:    store i64 [[COND3532]], ptr [[LX]], align 8
34484 // SIMD-ONLY0-NEXT:    [[TMP1772:%.*]] = load i64, ptr [[LE]], align 8
34485 // SIMD-ONLY0-NEXT:    [[TMP1773:%.*]] = load i64, ptr [[LX]], align 8
34486 // SIMD-ONLY0-NEXT:    [[CMP3533:%.*]] = icmp sgt i64 [[TMP1772]], [[TMP1773]]
34487 // SIMD-ONLY0-NEXT:    br i1 [[CMP3533]], label [[COND_TRUE3535:%.*]], label [[COND_FALSE3536:%.*]]
34488 // SIMD-ONLY0:       cond.true3535:
34489 // SIMD-ONLY0-NEXT:    [[TMP1774:%.*]] = load i64, ptr [[LE]], align 8
34490 // SIMD-ONLY0-NEXT:    br label [[COND_END3537:%.*]]
34491 // SIMD-ONLY0:       cond.false3536:
34492 // SIMD-ONLY0-NEXT:    [[TMP1775:%.*]] = load i64, ptr [[LX]], align 8
34493 // SIMD-ONLY0-NEXT:    br label [[COND_END3537]]
34494 // SIMD-ONLY0:       cond.end3537:
34495 // SIMD-ONLY0-NEXT:    [[COND3538:%.*]] = phi i64 [ [[TMP1774]], [[COND_TRUE3535]] ], [ [[TMP1775]], [[COND_FALSE3536]] ]
34496 // SIMD-ONLY0-NEXT:    store i64 [[COND3538]], ptr [[LX]], align 8
34497 // SIMD-ONLY0-NEXT:    [[TMP1776:%.*]] = load i64, ptr [[LE]], align 8
34498 // SIMD-ONLY0-NEXT:    [[TMP1777:%.*]] = load i64, ptr [[LX]], align 8
34499 // SIMD-ONLY0-NEXT:    [[CMP3539:%.*]] = icmp slt i64 [[TMP1776]], [[TMP1777]]
34500 // SIMD-ONLY0-NEXT:    br i1 [[CMP3539]], label [[COND_TRUE3541:%.*]], label [[COND_FALSE3542:%.*]]
34501 // SIMD-ONLY0:       cond.true3541:
34502 // SIMD-ONLY0-NEXT:    [[TMP1778:%.*]] = load i64, ptr [[LE]], align 8
34503 // SIMD-ONLY0-NEXT:    br label [[COND_END3543:%.*]]
34504 // SIMD-ONLY0:       cond.false3542:
34505 // SIMD-ONLY0-NEXT:    [[TMP1779:%.*]] = load i64, ptr [[LX]], align 8
34506 // SIMD-ONLY0-NEXT:    br label [[COND_END3543]]
34507 // SIMD-ONLY0:       cond.end3543:
34508 // SIMD-ONLY0-NEXT:    [[COND3544:%.*]] = phi i64 [ [[TMP1778]], [[COND_TRUE3541]] ], [ [[TMP1779]], [[COND_FALSE3542]] ]
34509 // SIMD-ONLY0-NEXT:    store i64 [[COND3544]], ptr [[LX]], align 8
34510 // SIMD-ONLY0-NEXT:    [[TMP1780:%.*]] = load i64, ptr [[LX]], align 8
34511 // SIMD-ONLY0-NEXT:    [[TMP1781:%.*]] = load i64, ptr [[LE]], align 8
34512 // SIMD-ONLY0-NEXT:    [[CMP3545:%.*]] = icmp sgt i64 [[TMP1780]], [[TMP1781]]
34513 // SIMD-ONLY0-NEXT:    br i1 [[CMP3545]], label [[IF_THEN3547:%.*]], label [[IF_END3548:%.*]]
34514 // SIMD-ONLY0:       if.then3547:
34515 // SIMD-ONLY0-NEXT:    [[TMP1782:%.*]] = load i64, ptr [[LE]], align 8
34516 // SIMD-ONLY0-NEXT:    store i64 [[TMP1782]], ptr [[LX]], align 8
34517 // SIMD-ONLY0-NEXT:    br label [[IF_END3548]]
34518 // SIMD-ONLY0:       if.end3548:
34519 // SIMD-ONLY0-NEXT:    [[TMP1783:%.*]] = load i64, ptr [[LX]], align 8
34520 // SIMD-ONLY0-NEXT:    [[TMP1784:%.*]] = load i64, ptr [[LE]], align 8
34521 // SIMD-ONLY0-NEXT:    [[CMP3549:%.*]] = icmp slt i64 [[TMP1783]], [[TMP1784]]
34522 // SIMD-ONLY0-NEXT:    br i1 [[CMP3549]], label [[IF_THEN3551:%.*]], label [[IF_END3552:%.*]]
34523 // SIMD-ONLY0:       if.then3551:
34524 // SIMD-ONLY0-NEXT:    [[TMP1785:%.*]] = load i64, ptr [[LE]], align 8
34525 // SIMD-ONLY0-NEXT:    store i64 [[TMP1785]], ptr [[LX]], align 8
34526 // SIMD-ONLY0-NEXT:    br label [[IF_END3552]]
34527 // SIMD-ONLY0:       if.end3552:
34528 // SIMD-ONLY0-NEXT:    [[TMP1786:%.*]] = load i64, ptr [[LE]], align 8
34529 // SIMD-ONLY0-NEXT:    [[TMP1787:%.*]] = load i64, ptr [[LX]], align 8
34530 // SIMD-ONLY0-NEXT:    [[CMP3553:%.*]] = icmp sgt i64 [[TMP1786]], [[TMP1787]]
34531 // SIMD-ONLY0-NEXT:    br i1 [[CMP3553]], label [[IF_THEN3555:%.*]], label [[IF_END3556:%.*]]
34532 // SIMD-ONLY0:       if.then3555:
34533 // SIMD-ONLY0-NEXT:    [[TMP1788:%.*]] = load i64, ptr [[LE]], align 8
34534 // SIMD-ONLY0-NEXT:    store i64 [[TMP1788]], ptr [[LX]], align 8
34535 // SIMD-ONLY0-NEXT:    br label [[IF_END3556]]
34536 // SIMD-ONLY0:       if.end3556:
34537 // SIMD-ONLY0-NEXT:    [[TMP1789:%.*]] = load i64, ptr [[LE]], align 8
34538 // SIMD-ONLY0-NEXT:    [[TMP1790:%.*]] = load i64, ptr [[LX]], align 8
34539 // SIMD-ONLY0-NEXT:    [[CMP3557:%.*]] = icmp slt i64 [[TMP1789]], [[TMP1790]]
34540 // SIMD-ONLY0-NEXT:    br i1 [[CMP3557]], label [[IF_THEN3559:%.*]], label [[IF_END3560:%.*]]
34541 // SIMD-ONLY0:       if.then3559:
34542 // SIMD-ONLY0-NEXT:    [[TMP1791:%.*]] = load i64, ptr [[LE]], align 8
34543 // SIMD-ONLY0-NEXT:    store i64 [[TMP1791]], ptr [[LX]], align 8
34544 // SIMD-ONLY0-NEXT:    br label [[IF_END3560]]
34545 // SIMD-ONLY0:       if.end3560:
34546 // SIMD-ONLY0-NEXT:    [[TMP1792:%.*]] = load i64, ptr [[LX]], align 8
34547 // SIMD-ONLY0-NEXT:    [[TMP1793:%.*]] = load i64, ptr [[LE]], align 8
34548 // SIMD-ONLY0-NEXT:    [[CMP3561:%.*]] = icmp eq i64 [[TMP1792]], [[TMP1793]]
34549 // SIMD-ONLY0-NEXT:    br i1 [[CMP3561]], label [[COND_TRUE3563:%.*]], label [[COND_FALSE3564:%.*]]
34550 // SIMD-ONLY0:       cond.true3563:
34551 // SIMD-ONLY0-NEXT:    [[TMP1794:%.*]] = load i64, ptr [[LD]], align 8
34552 // SIMD-ONLY0-NEXT:    br label [[COND_END3565:%.*]]
34553 // SIMD-ONLY0:       cond.false3564:
34554 // SIMD-ONLY0-NEXT:    [[TMP1795:%.*]] = load i64, ptr [[LX]], align 8
34555 // SIMD-ONLY0-NEXT:    br label [[COND_END3565]]
34556 // SIMD-ONLY0:       cond.end3565:
34557 // SIMD-ONLY0-NEXT:    [[COND3566:%.*]] = phi i64 [ [[TMP1794]], [[COND_TRUE3563]] ], [ [[TMP1795]], [[COND_FALSE3564]] ]
34558 // SIMD-ONLY0-NEXT:    store i64 [[COND3566]], ptr [[LX]], align 8
34559 // SIMD-ONLY0-NEXT:    [[TMP1796:%.*]] = load i64, ptr [[LE]], align 8
34560 // SIMD-ONLY0-NEXT:    [[TMP1797:%.*]] = load i64, ptr [[LX]], align 8
34561 // SIMD-ONLY0-NEXT:    [[CMP3567:%.*]] = icmp eq i64 [[TMP1796]], [[TMP1797]]
34562 // SIMD-ONLY0-NEXT:    br i1 [[CMP3567]], label [[COND_TRUE3569:%.*]], label [[COND_FALSE3570:%.*]]
34563 // SIMD-ONLY0:       cond.true3569:
34564 // SIMD-ONLY0-NEXT:    [[TMP1798:%.*]] = load i64, ptr [[LD]], align 8
34565 // SIMD-ONLY0-NEXT:    br label [[COND_END3571:%.*]]
34566 // SIMD-ONLY0:       cond.false3570:
34567 // SIMD-ONLY0-NEXT:    [[TMP1799:%.*]] = load i64, ptr [[LX]], align 8
34568 // SIMD-ONLY0-NEXT:    br label [[COND_END3571]]
34569 // SIMD-ONLY0:       cond.end3571:
34570 // SIMD-ONLY0-NEXT:    [[COND3572:%.*]] = phi i64 [ [[TMP1798]], [[COND_TRUE3569]] ], [ [[TMP1799]], [[COND_FALSE3570]] ]
34571 // SIMD-ONLY0-NEXT:    store i64 [[COND3572]], ptr [[LX]], align 8
34572 // SIMD-ONLY0-NEXT:    [[TMP1800:%.*]] = load i64, ptr [[LX]], align 8
34573 // SIMD-ONLY0-NEXT:    [[TMP1801:%.*]] = load i64, ptr [[LE]], align 8
34574 // SIMD-ONLY0-NEXT:    [[CMP3573:%.*]] = icmp eq i64 [[TMP1800]], [[TMP1801]]
34575 // SIMD-ONLY0-NEXT:    br i1 [[CMP3573]], label [[IF_THEN3575:%.*]], label [[IF_END3576:%.*]]
34576 // SIMD-ONLY0:       if.then3575:
34577 // SIMD-ONLY0-NEXT:    [[TMP1802:%.*]] = load i64, ptr [[LD]], align 8
34578 // SIMD-ONLY0-NEXT:    store i64 [[TMP1802]], ptr [[LX]], align 8
34579 // SIMD-ONLY0-NEXT:    br label [[IF_END3576]]
34580 // SIMD-ONLY0:       if.end3576:
34581 // SIMD-ONLY0-NEXT:    [[TMP1803:%.*]] = load i64, ptr [[LE]], align 8
34582 // SIMD-ONLY0-NEXT:    [[TMP1804:%.*]] = load i64, ptr [[LX]], align 8
34583 // SIMD-ONLY0-NEXT:    [[CMP3577:%.*]] = icmp eq i64 [[TMP1803]], [[TMP1804]]
34584 // SIMD-ONLY0-NEXT:    br i1 [[CMP3577]], label [[IF_THEN3579:%.*]], label [[IF_END3580:%.*]]
34585 // SIMD-ONLY0:       if.then3579:
34586 // SIMD-ONLY0-NEXT:    [[TMP1805:%.*]] = load i64, ptr [[LD]], align 8
34587 // SIMD-ONLY0-NEXT:    store i64 [[TMP1805]], ptr [[LX]], align 8
34588 // SIMD-ONLY0-NEXT:    br label [[IF_END3580]]
34589 // SIMD-ONLY0:       if.end3580:
34590 // SIMD-ONLY0-NEXT:    [[TMP1806:%.*]] = load i64, ptr [[ULX]], align 8
34591 // SIMD-ONLY0-NEXT:    [[TMP1807:%.*]] = load i64, ptr [[ULE]], align 8
34592 // SIMD-ONLY0-NEXT:    [[CMP3581:%.*]] = icmp ugt i64 [[TMP1806]], [[TMP1807]]
34593 // SIMD-ONLY0-NEXT:    br i1 [[CMP3581]], label [[COND_TRUE3583:%.*]], label [[COND_FALSE3584:%.*]]
34594 // SIMD-ONLY0:       cond.true3583:
34595 // SIMD-ONLY0-NEXT:    [[TMP1808:%.*]] = load i64, ptr [[ULE]], align 8
34596 // SIMD-ONLY0-NEXT:    br label [[COND_END3585:%.*]]
34597 // SIMD-ONLY0:       cond.false3584:
34598 // SIMD-ONLY0-NEXT:    [[TMP1809:%.*]] = load i64, ptr [[ULX]], align 8
34599 // SIMD-ONLY0-NEXT:    br label [[COND_END3585]]
34600 // SIMD-ONLY0:       cond.end3585:
34601 // SIMD-ONLY0-NEXT:    [[COND3586:%.*]] = phi i64 [ [[TMP1808]], [[COND_TRUE3583]] ], [ [[TMP1809]], [[COND_FALSE3584]] ]
34602 // SIMD-ONLY0-NEXT:    store i64 [[COND3586]], ptr [[ULX]], align 8
34603 // SIMD-ONLY0-NEXT:    [[TMP1810:%.*]] = load i64, ptr [[ULX]], align 8
34604 // SIMD-ONLY0-NEXT:    [[TMP1811:%.*]] = load i64, ptr [[ULE]], align 8
34605 // SIMD-ONLY0-NEXT:    [[CMP3587:%.*]] = icmp ult i64 [[TMP1810]], [[TMP1811]]
34606 // SIMD-ONLY0-NEXT:    br i1 [[CMP3587]], label [[COND_TRUE3589:%.*]], label [[COND_FALSE3590:%.*]]
34607 // SIMD-ONLY0:       cond.true3589:
34608 // SIMD-ONLY0-NEXT:    [[TMP1812:%.*]] = load i64, ptr [[ULE]], align 8
34609 // SIMD-ONLY0-NEXT:    br label [[COND_END3591:%.*]]
34610 // SIMD-ONLY0:       cond.false3590:
34611 // SIMD-ONLY0-NEXT:    [[TMP1813:%.*]] = load i64, ptr [[ULX]], align 8
34612 // SIMD-ONLY0-NEXT:    br label [[COND_END3591]]
34613 // SIMD-ONLY0:       cond.end3591:
34614 // SIMD-ONLY0-NEXT:    [[COND3592:%.*]] = phi i64 [ [[TMP1812]], [[COND_TRUE3589]] ], [ [[TMP1813]], [[COND_FALSE3590]] ]
34615 // SIMD-ONLY0-NEXT:    store i64 [[COND3592]], ptr [[ULX]], align 8
34616 // SIMD-ONLY0-NEXT:    [[TMP1814:%.*]] = load i64, ptr [[ULE]], align 8
34617 // SIMD-ONLY0-NEXT:    [[TMP1815:%.*]] = load i64, ptr [[ULX]], align 8
34618 // SIMD-ONLY0-NEXT:    [[CMP3593:%.*]] = icmp ugt i64 [[TMP1814]], [[TMP1815]]
34619 // SIMD-ONLY0-NEXT:    br i1 [[CMP3593]], label [[COND_TRUE3595:%.*]], label [[COND_FALSE3596:%.*]]
34620 // SIMD-ONLY0:       cond.true3595:
34621 // SIMD-ONLY0-NEXT:    [[TMP1816:%.*]] = load i64, ptr [[ULE]], align 8
34622 // SIMD-ONLY0-NEXT:    br label [[COND_END3597:%.*]]
34623 // SIMD-ONLY0:       cond.false3596:
34624 // SIMD-ONLY0-NEXT:    [[TMP1817:%.*]] = load i64, ptr [[ULX]], align 8
34625 // SIMD-ONLY0-NEXT:    br label [[COND_END3597]]
34626 // SIMD-ONLY0:       cond.end3597:
34627 // SIMD-ONLY0-NEXT:    [[COND3598:%.*]] = phi i64 [ [[TMP1816]], [[COND_TRUE3595]] ], [ [[TMP1817]], [[COND_FALSE3596]] ]
34628 // SIMD-ONLY0-NEXT:    store i64 [[COND3598]], ptr [[ULX]], align 8
34629 // SIMD-ONLY0-NEXT:    [[TMP1818:%.*]] = load i64, ptr [[ULE]], align 8
34630 // SIMD-ONLY0-NEXT:    [[TMP1819:%.*]] = load i64, ptr [[ULX]], align 8
34631 // SIMD-ONLY0-NEXT:    [[CMP3599:%.*]] = icmp ult i64 [[TMP1818]], [[TMP1819]]
34632 // SIMD-ONLY0-NEXT:    br i1 [[CMP3599]], label [[COND_TRUE3601:%.*]], label [[COND_FALSE3602:%.*]]
34633 // SIMD-ONLY0:       cond.true3601:
34634 // SIMD-ONLY0-NEXT:    [[TMP1820:%.*]] = load i64, ptr [[ULE]], align 8
34635 // SIMD-ONLY0-NEXT:    br label [[COND_END3603:%.*]]
34636 // SIMD-ONLY0:       cond.false3602:
34637 // SIMD-ONLY0-NEXT:    [[TMP1821:%.*]] = load i64, ptr [[ULX]], align 8
34638 // SIMD-ONLY0-NEXT:    br label [[COND_END3603]]
34639 // SIMD-ONLY0:       cond.end3603:
34640 // SIMD-ONLY0-NEXT:    [[COND3604:%.*]] = phi i64 [ [[TMP1820]], [[COND_TRUE3601]] ], [ [[TMP1821]], [[COND_FALSE3602]] ]
34641 // SIMD-ONLY0-NEXT:    store i64 [[COND3604]], ptr [[ULX]], align 8
34642 // SIMD-ONLY0-NEXT:    [[TMP1822:%.*]] = load i64, ptr [[ULX]], align 8
34643 // SIMD-ONLY0-NEXT:    [[TMP1823:%.*]] = load i64, ptr [[ULE]], align 8
34644 // SIMD-ONLY0-NEXT:    [[CMP3605:%.*]] = icmp ugt i64 [[TMP1822]], [[TMP1823]]
34645 // SIMD-ONLY0-NEXT:    br i1 [[CMP3605]], label [[IF_THEN3607:%.*]], label [[IF_END3608:%.*]]
34646 // SIMD-ONLY0:       if.then3607:
34647 // SIMD-ONLY0-NEXT:    [[TMP1824:%.*]] = load i64, ptr [[ULE]], align 8
34648 // SIMD-ONLY0-NEXT:    store i64 [[TMP1824]], ptr [[ULX]], align 8
34649 // SIMD-ONLY0-NEXT:    br label [[IF_END3608]]
34650 // SIMD-ONLY0:       if.end3608:
34651 // SIMD-ONLY0-NEXT:    [[TMP1825:%.*]] = load i64, ptr [[ULX]], align 8
34652 // SIMD-ONLY0-NEXT:    [[TMP1826:%.*]] = load i64, ptr [[ULE]], align 8
34653 // SIMD-ONLY0-NEXT:    [[CMP3609:%.*]] = icmp ult i64 [[TMP1825]], [[TMP1826]]
34654 // SIMD-ONLY0-NEXT:    br i1 [[CMP3609]], label [[IF_THEN3611:%.*]], label [[IF_END3612:%.*]]
34655 // SIMD-ONLY0:       if.then3611:
34656 // SIMD-ONLY0-NEXT:    [[TMP1827:%.*]] = load i64, ptr [[ULE]], align 8
34657 // SIMD-ONLY0-NEXT:    store i64 [[TMP1827]], ptr [[ULX]], align 8
34658 // SIMD-ONLY0-NEXT:    br label [[IF_END3612]]
34659 // SIMD-ONLY0:       if.end3612:
34660 // SIMD-ONLY0-NEXT:    [[TMP1828:%.*]] = load i64, ptr [[ULE]], align 8
34661 // SIMD-ONLY0-NEXT:    [[TMP1829:%.*]] = load i64, ptr [[ULX]], align 8
34662 // SIMD-ONLY0-NEXT:    [[CMP3613:%.*]] = icmp ugt i64 [[TMP1828]], [[TMP1829]]
34663 // SIMD-ONLY0-NEXT:    br i1 [[CMP3613]], label [[IF_THEN3615:%.*]], label [[IF_END3616:%.*]]
34664 // SIMD-ONLY0:       if.then3615:
34665 // SIMD-ONLY0-NEXT:    [[TMP1830:%.*]] = load i64, ptr [[ULE]], align 8
34666 // SIMD-ONLY0-NEXT:    store i64 [[TMP1830]], ptr [[ULX]], align 8
34667 // SIMD-ONLY0-NEXT:    br label [[IF_END3616]]
34668 // SIMD-ONLY0:       if.end3616:
34669 // SIMD-ONLY0-NEXT:    [[TMP1831:%.*]] = load i64, ptr [[ULE]], align 8
34670 // SIMD-ONLY0-NEXT:    [[TMP1832:%.*]] = load i64, ptr [[ULX]], align 8
34671 // SIMD-ONLY0-NEXT:    [[CMP3617:%.*]] = icmp ult i64 [[TMP1831]], [[TMP1832]]
34672 // SIMD-ONLY0-NEXT:    br i1 [[CMP3617]], label [[IF_THEN3619:%.*]], label [[IF_END3620:%.*]]
34673 // SIMD-ONLY0:       if.then3619:
34674 // SIMD-ONLY0-NEXT:    [[TMP1833:%.*]] = load i64, ptr [[ULE]], align 8
34675 // SIMD-ONLY0-NEXT:    store i64 [[TMP1833]], ptr [[ULX]], align 8
34676 // SIMD-ONLY0-NEXT:    br label [[IF_END3620]]
34677 // SIMD-ONLY0:       if.end3620:
34678 // SIMD-ONLY0-NEXT:    [[TMP1834:%.*]] = load i64, ptr [[ULX]], align 8
34679 // SIMD-ONLY0-NEXT:    [[TMP1835:%.*]] = load i64, ptr [[ULE]], align 8
34680 // SIMD-ONLY0-NEXT:    [[CMP3621:%.*]] = icmp eq i64 [[TMP1834]], [[TMP1835]]
34681 // SIMD-ONLY0-NEXT:    br i1 [[CMP3621]], label [[COND_TRUE3623:%.*]], label [[COND_FALSE3624:%.*]]
34682 // SIMD-ONLY0:       cond.true3623:
34683 // SIMD-ONLY0-NEXT:    [[TMP1836:%.*]] = load i64, ptr [[ULD]], align 8
34684 // SIMD-ONLY0-NEXT:    br label [[COND_END3625:%.*]]
34685 // SIMD-ONLY0:       cond.false3624:
34686 // SIMD-ONLY0-NEXT:    [[TMP1837:%.*]] = load i64, ptr [[ULX]], align 8
34687 // SIMD-ONLY0-NEXT:    br label [[COND_END3625]]
34688 // SIMD-ONLY0:       cond.end3625:
34689 // SIMD-ONLY0-NEXT:    [[COND3626:%.*]] = phi i64 [ [[TMP1836]], [[COND_TRUE3623]] ], [ [[TMP1837]], [[COND_FALSE3624]] ]
34690 // SIMD-ONLY0-NEXT:    store i64 [[COND3626]], ptr [[ULX]], align 8
34691 // SIMD-ONLY0-NEXT:    [[TMP1838:%.*]] = load i64, ptr [[ULE]], align 8
34692 // SIMD-ONLY0-NEXT:    [[TMP1839:%.*]] = load i64, ptr [[ULX]], align 8
34693 // SIMD-ONLY0-NEXT:    [[CMP3627:%.*]] = icmp eq i64 [[TMP1838]], [[TMP1839]]
34694 // SIMD-ONLY0-NEXT:    br i1 [[CMP3627]], label [[COND_TRUE3629:%.*]], label [[COND_FALSE3630:%.*]]
34695 // SIMD-ONLY0:       cond.true3629:
34696 // SIMD-ONLY0-NEXT:    [[TMP1840:%.*]] = load i64, ptr [[ULD]], align 8
34697 // SIMD-ONLY0-NEXT:    br label [[COND_END3631:%.*]]
34698 // SIMD-ONLY0:       cond.false3630:
34699 // SIMD-ONLY0-NEXT:    [[TMP1841:%.*]] = load i64, ptr [[ULX]], align 8
34700 // SIMD-ONLY0-NEXT:    br label [[COND_END3631]]
34701 // SIMD-ONLY0:       cond.end3631:
34702 // SIMD-ONLY0-NEXT:    [[COND3632:%.*]] = phi i64 [ [[TMP1840]], [[COND_TRUE3629]] ], [ [[TMP1841]], [[COND_FALSE3630]] ]
34703 // SIMD-ONLY0-NEXT:    store i64 [[COND3632]], ptr [[ULX]], align 8
34704 // SIMD-ONLY0-NEXT:    [[TMP1842:%.*]] = load i64, ptr [[ULX]], align 8
34705 // SIMD-ONLY0-NEXT:    [[TMP1843:%.*]] = load i64, ptr [[ULE]], align 8
34706 // SIMD-ONLY0-NEXT:    [[CMP3633:%.*]] = icmp eq i64 [[TMP1842]], [[TMP1843]]
34707 // SIMD-ONLY0-NEXT:    br i1 [[CMP3633]], label [[IF_THEN3635:%.*]], label [[IF_END3636:%.*]]
34708 // SIMD-ONLY0:       if.then3635:
34709 // SIMD-ONLY0-NEXT:    [[TMP1844:%.*]] = load i64, ptr [[ULD]], align 8
34710 // SIMD-ONLY0-NEXT:    store i64 [[TMP1844]], ptr [[ULX]], align 8
34711 // SIMD-ONLY0-NEXT:    br label [[IF_END3636]]
34712 // SIMD-ONLY0:       if.end3636:
34713 // SIMD-ONLY0-NEXT:    [[TMP1845:%.*]] = load i64, ptr [[ULE]], align 8
34714 // SIMD-ONLY0-NEXT:    [[TMP1846:%.*]] = load i64, ptr [[ULX]], align 8
34715 // SIMD-ONLY0-NEXT:    [[CMP3637:%.*]] = icmp eq i64 [[TMP1845]], [[TMP1846]]
34716 // SIMD-ONLY0-NEXT:    br i1 [[CMP3637]], label [[IF_THEN3639:%.*]], label [[IF_END3640:%.*]]
34717 // SIMD-ONLY0:       if.then3639:
34718 // SIMD-ONLY0-NEXT:    [[TMP1847:%.*]] = load i64, ptr [[ULD]], align 8
34719 // SIMD-ONLY0-NEXT:    store i64 [[TMP1847]], ptr [[ULX]], align 8
34720 // SIMD-ONLY0-NEXT:    br label [[IF_END3640]]
34721 // SIMD-ONLY0:       if.end3640:
34722 // SIMD-ONLY0-NEXT:    [[TMP1848:%.*]] = load i64, ptr [[LX]], align 8
34723 // SIMD-ONLY0-NEXT:    [[TMP1849:%.*]] = load i64, ptr [[LE]], align 8
34724 // SIMD-ONLY0-NEXT:    [[CMP3641:%.*]] = icmp sgt i64 [[TMP1848]], [[TMP1849]]
34725 // SIMD-ONLY0-NEXT:    br i1 [[CMP3641]], label [[COND_TRUE3643:%.*]], label [[COND_FALSE3644:%.*]]
34726 // SIMD-ONLY0:       cond.true3643:
34727 // SIMD-ONLY0-NEXT:    [[TMP1850:%.*]] = load i64, ptr [[LE]], align 8
34728 // SIMD-ONLY0-NEXT:    br label [[COND_END3645:%.*]]
34729 // SIMD-ONLY0:       cond.false3644:
34730 // SIMD-ONLY0-NEXT:    [[TMP1851:%.*]] = load i64, ptr [[LX]], align 8
34731 // SIMD-ONLY0-NEXT:    br label [[COND_END3645]]
34732 // SIMD-ONLY0:       cond.end3645:
34733 // SIMD-ONLY0-NEXT:    [[COND3646:%.*]] = phi i64 [ [[TMP1850]], [[COND_TRUE3643]] ], [ [[TMP1851]], [[COND_FALSE3644]] ]
34734 // SIMD-ONLY0-NEXT:    store i64 [[COND3646]], ptr [[LX]], align 8
34735 // SIMD-ONLY0-NEXT:    [[TMP1852:%.*]] = load i64, ptr [[LX]], align 8
34736 // SIMD-ONLY0-NEXT:    [[TMP1853:%.*]] = load i64, ptr [[LE]], align 8
34737 // SIMD-ONLY0-NEXT:    [[CMP3647:%.*]] = icmp slt i64 [[TMP1852]], [[TMP1853]]
34738 // SIMD-ONLY0-NEXT:    br i1 [[CMP3647]], label [[COND_TRUE3649:%.*]], label [[COND_FALSE3650:%.*]]
34739 // SIMD-ONLY0:       cond.true3649:
34740 // SIMD-ONLY0-NEXT:    [[TMP1854:%.*]] = load i64, ptr [[LE]], align 8
34741 // SIMD-ONLY0-NEXT:    br label [[COND_END3651:%.*]]
34742 // SIMD-ONLY0:       cond.false3650:
34743 // SIMD-ONLY0-NEXT:    [[TMP1855:%.*]] = load i64, ptr [[LX]], align 8
34744 // SIMD-ONLY0-NEXT:    br label [[COND_END3651]]
34745 // SIMD-ONLY0:       cond.end3651:
34746 // SIMD-ONLY0-NEXT:    [[COND3652:%.*]] = phi i64 [ [[TMP1854]], [[COND_TRUE3649]] ], [ [[TMP1855]], [[COND_FALSE3650]] ]
34747 // SIMD-ONLY0-NEXT:    store i64 [[COND3652]], ptr [[LX]], align 8
34748 // SIMD-ONLY0-NEXT:    [[TMP1856:%.*]] = load i64, ptr [[LE]], align 8
34749 // SIMD-ONLY0-NEXT:    [[TMP1857:%.*]] = load i64, ptr [[LX]], align 8
34750 // SIMD-ONLY0-NEXT:    [[CMP3653:%.*]] = icmp sgt i64 [[TMP1856]], [[TMP1857]]
34751 // SIMD-ONLY0-NEXT:    br i1 [[CMP3653]], label [[COND_TRUE3655:%.*]], label [[COND_FALSE3656:%.*]]
34752 // SIMD-ONLY0:       cond.true3655:
34753 // SIMD-ONLY0-NEXT:    [[TMP1858:%.*]] = load i64, ptr [[LE]], align 8
34754 // SIMD-ONLY0-NEXT:    br label [[COND_END3657:%.*]]
34755 // SIMD-ONLY0:       cond.false3656:
34756 // SIMD-ONLY0-NEXT:    [[TMP1859:%.*]] = load i64, ptr [[LX]], align 8
34757 // SIMD-ONLY0-NEXT:    br label [[COND_END3657]]
34758 // SIMD-ONLY0:       cond.end3657:
34759 // SIMD-ONLY0-NEXT:    [[COND3658:%.*]] = phi i64 [ [[TMP1858]], [[COND_TRUE3655]] ], [ [[TMP1859]], [[COND_FALSE3656]] ]
34760 // SIMD-ONLY0-NEXT:    store i64 [[COND3658]], ptr [[LX]], align 8
34761 // SIMD-ONLY0-NEXT:    [[TMP1860:%.*]] = load i64, ptr [[LE]], align 8
34762 // SIMD-ONLY0-NEXT:    [[TMP1861:%.*]] = load i64, ptr [[LX]], align 8
34763 // SIMD-ONLY0-NEXT:    [[CMP3659:%.*]] = icmp slt i64 [[TMP1860]], [[TMP1861]]
34764 // SIMD-ONLY0-NEXT:    br i1 [[CMP3659]], label [[COND_TRUE3661:%.*]], label [[COND_FALSE3662:%.*]]
34765 // SIMD-ONLY0:       cond.true3661:
34766 // SIMD-ONLY0-NEXT:    [[TMP1862:%.*]] = load i64, ptr [[LE]], align 8
34767 // SIMD-ONLY0-NEXT:    br label [[COND_END3663:%.*]]
34768 // SIMD-ONLY0:       cond.false3662:
34769 // SIMD-ONLY0-NEXT:    [[TMP1863:%.*]] = load i64, ptr [[LX]], align 8
34770 // SIMD-ONLY0-NEXT:    br label [[COND_END3663]]
34771 // SIMD-ONLY0:       cond.end3663:
34772 // SIMD-ONLY0-NEXT:    [[COND3664:%.*]] = phi i64 [ [[TMP1862]], [[COND_TRUE3661]] ], [ [[TMP1863]], [[COND_FALSE3662]] ]
34773 // SIMD-ONLY0-NEXT:    store i64 [[COND3664]], ptr [[LX]], align 8
34774 // SIMD-ONLY0-NEXT:    [[TMP1864:%.*]] = load i64, ptr [[LX]], align 8
34775 // SIMD-ONLY0-NEXT:    [[TMP1865:%.*]] = load i64, ptr [[LE]], align 8
34776 // SIMD-ONLY0-NEXT:    [[CMP3665:%.*]] = icmp sgt i64 [[TMP1864]], [[TMP1865]]
34777 // SIMD-ONLY0-NEXT:    br i1 [[CMP3665]], label [[IF_THEN3667:%.*]], label [[IF_END3668:%.*]]
34778 // SIMD-ONLY0:       if.then3667:
34779 // SIMD-ONLY0-NEXT:    [[TMP1866:%.*]] = load i64, ptr [[LE]], align 8
34780 // SIMD-ONLY0-NEXT:    store i64 [[TMP1866]], ptr [[LX]], align 8
34781 // SIMD-ONLY0-NEXT:    br label [[IF_END3668]]
34782 // SIMD-ONLY0:       if.end3668:
34783 // SIMD-ONLY0-NEXT:    [[TMP1867:%.*]] = load i64, ptr [[LX]], align 8
34784 // SIMD-ONLY0-NEXT:    [[TMP1868:%.*]] = load i64, ptr [[LE]], align 8
34785 // SIMD-ONLY0-NEXT:    [[CMP3669:%.*]] = icmp slt i64 [[TMP1867]], [[TMP1868]]
34786 // SIMD-ONLY0-NEXT:    br i1 [[CMP3669]], label [[IF_THEN3671:%.*]], label [[IF_END3672:%.*]]
34787 // SIMD-ONLY0:       if.then3671:
34788 // SIMD-ONLY0-NEXT:    [[TMP1869:%.*]] = load i64, ptr [[LE]], align 8
34789 // SIMD-ONLY0-NEXT:    store i64 [[TMP1869]], ptr [[LX]], align 8
34790 // SIMD-ONLY0-NEXT:    br label [[IF_END3672]]
34791 // SIMD-ONLY0:       if.end3672:
34792 // SIMD-ONLY0-NEXT:    [[TMP1870:%.*]] = load i64, ptr [[LE]], align 8
34793 // SIMD-ONLY0-NEXT:    [[TMP1871:%.*]] = load i64, ptr [[LX]], align 8
34794 // SIMD-ONLY0-NEXT:    [[CMP3673:%.*]] = icmp sgt i64 [[TMP1870]], [[TMP1871]]
34795 // SIMD-ONLY0-NEXT:    br i1 [[CMP3673]], label [[IF_THEN3675:%.*]], label [[IF_END3676:%.*]]
34796 // SIMD-ONLY0:       if.then3675:
34797 // SIMD-ONLY0-NEXT:    [[TMP1872:%.*]] = load i64, ptr [[LE]], align 8
34798 // SIMD-ONLY0-NEXT:    store i64 [[TMP1872]], ptr [[LX]], align 8
34799 // SIMD-ONLY0-NEXT:    br label [[IF_END3676]]
34800 // SIMD-ONLY0:       if.end3676:
34801 // SIMD-ONLY0-NEXT:    [[TMP1873:%.*]] = load i64, ptr [[LE]], align 8
34802 // SIMD-ONLY0-NEXT:    [[TMP1874:%.*]] = load i64, ptr [[LX]], align 8
34803 // SIMD-ONLY0-NEXT:    [[CMP3677:%.*]] = icmp slt i64 [[TMP1873]], [[TMP1874]]
34804 // SIMD-ONLY0-NEXT:    br i1 [[CMP3677]], label [[IF_THEN3679:%.*]], label [[IF_END3680:%.*]]
34805 // SIMD-ONLY0:       if.then3679:
34806 // SIMD-ONLY0-NEXT:    [[TMP1875:%.*]] = load i64, ptr [[LE]], align 8
34807 // SIMD-ONLY0-NEXT:    store i64 [[TMP1875]], ptr [[LX]], align 8
34808 // SIMD-ONLY0-NEXT:    br label [[IF_END3680]]
34809 // SIMD-ONLY0:       if.end3680:
34810 // SIMD-ONLY0-NEXT:    [[TMP1876:%.*]] = load i64, ptr [[LX]], align 8
34811 // SIMD-ONLY0-NEXT:    [[TMP1877:%.*]] = load i64, ptr [[LE]], align 8
34812 // SIMD-ONLY0-NEXT:    [[CMP3681:%.*]] = icmp eq i64 [[TMP1876]], [[TMP1877]]
34813 // SIMD-ONLY0-NEXT:    br i1 [[CMP3681]], label [[COND_TRUE3683:%.*]], label [[COND_FALSE3684:%.*]]
34814 // SIMD-ONLY0:       cond.true3683:
34815 // SIMD-ONLY0-NEXT:    [[TMP1878:%.*]] = load i64, ptr [[LD]], align 8
34816 // SIMD-ONLY0-NEXT:    br label [[COND_END3685:%.*]]
34817 // SIMD-ONLY0:       cond.false3684:
34818 // SIMD-ONLY0-NEXT:    [[TMP1879:%.*]] = load i64, ptr [[LX]], align 8
34819 // SIMD-ONLY0-NEXT:    br label [[COND_END3685]]
34820 // SIMD-ONLY0:       cond.end3685:
34821 // SIMD-ONLY0-NEXT:    [[COND3686:%.*]] = phi i64 [ [[TMP1878]], [[COND_TRUE3683]] ], [ [[TMP1879]], [[COND_FALSE3684]] ]
34822 // SIMD-ONLY0-NEXT:    store i64 [[COND3686]], ptr [[LX]], align 8
34823 // SIMD-ONLY0-NEXT:    [[TMP1880:%.*]] = load i64, ptr [[LE]], align 8
34824 // SIMD-ONLY0-NEXT:    [[TMP1881:%.*]] = load i64, ptr [[LX]], align 8
34825 // SIMD-ONLY0-NEXT:    [[CMP3687:%.*]] = icmp eq i64 [[TMP1880]], [[TMP1881]]
34826 // SIMD-ONLY0-NEXT:    br i1 [[CMP3687]], label [[COND_TRUE3689:%.*]], label [[COND_FALSE3690:%.*]]
34827 // SIMD-ONLY0:       cond.true3689:
34828 // SIMD-ONLY0-NEXT:    [[TMP1882:%.*]] = load i64, ptr [[LD]], align 8
34829 // SIMD-ONLY0-NEXT:    br label [[COND_END3691:%.*]]
34830 // SIMD-ONLY0:       cond.false3690:
34831 // SIMD-ONLY0-NEXT:    [[TMP1883:%.*]] = load i64, ptr [[LX]], align 8
34832 // SIMD-ONLY0-NEXT:    br label [[COND_END3691]]
34833 // SIMD-ONLY0:       cond.end3691:
34834 // SIMD-ONLY0-NEXT:    [[COND3692:%.*]] = phi i64 [ [[TMP1882]], [[COND_TRUE3689]] ], [ [[TMP1883]], [[COND_FALSE3690]] ]
34835 // SIMD-ONLY0-NEXT:    store i64 [[COND3692]], ptr [[LX]], align 8
34836 // SIMD-ONLY0-NEXT:    [[TMP1884:%.*]] = load i64, ptr [[LX]], align 8
34837 // SIMD-ONLY0-NEXT:    [[TMP1885:%.*]] = load i64, ptr [[LE]], align 8
34838 // SIMD-ONLY0-NEXT:    [[CMP3693:%.*]] = icmp eq i64 [[TMP1884]], [[TMP1885]]
34839 // SIMD-ONLY0-NEXT:    br i1 [[CMP3693]], label [[IF_THEN3695:%.*]], label [[IF_END3696:%.*]]
34840 // SIMD-ONLY0:       if.then3695:
34841 // SIMD-ONLY0-NEXT:    [[TMP1886:%.*]] = load i64, ptr [[LD]], align 8
34842 // SIMD-ONLY0-NEXT:    store i64 [[TMP1886]], ptr [[LX]], align 8
34843 // SIMD-ONLY0-NEXT:    br label [[IF_END3696]]
34844 // SIMD-ONLY0:       if.end3696:
34845 // SIMD-ONLY0-NEXT:    [[TMP1887:%.*]] = load i64, ptr [[LE]], align 8
34846 // SIMD-ONLY0-NEXT:    [[TMP1888:%.*]] = load i64, ptr [[LX]], align 8
34847 // SIMD-ONLY0-NEXT:    [[CMP3697:%.*]] = icmp eq i64 [[TMP1887]], [[TMP1888]]
34848 // SIMD-ONLY0-NEXT:    br i1 [[CMP3697]], label [[IF_THEN3699:%.*]], label [[IF_END3700:%.*]]
34849 // SIMD-ONLY0:       if.then3699:
34850 // SIMD-ONLY0-NEXT:    [[TMP1889:%.*]] = load i64, ptr [[LD]], align 8
34851 // SIMD-ONLY0-NEXT:    store i64 [[TMP1889]], ptr [[LX]], align 8
34852 // SIMD-ONLY0-NEXT:    br label [[IF_END3700]]
34853 // SIMD-ONLY0:       if.end3700:
34854 // SIMD-ONLY0-NEXT:    [[TMP1890:%.*]] = load i64, ptr [[ULX]], align 8
34855 // SIMD-ONLY0-NEXT:    [[TMP1891:%.*]] = load i64, ptr [[ULE]], align 8
34856 // SIMD-ONLY0-NEXT:    [[CMP3701:%.*]] = icmp ugt i64 [[TMP1890]], [[TMP1891]]
34857 // SIMD-ONLY0-NEXT:    br i1 [[CMP3701]], label [[COND_TRUE3703:%.*]], label [[COND_FALSE3704:%.*]]
34858 // SIMD-ONLY0:       cond.true3703:
34859 // SIMD-ONLY0-NEXT:    [[TMP1892:%.*]] = load i64, ptr [[ULE]], align 8
34860 // SIMD-ONLY0-NEXT:    br label [[COND_END3705:%.*]]
34861 // SIMD-ONLY0:       cond.false3704:
34862 // SIMD-ONLY0-NEXT:    [[TMP1893:%.*]] = load i64, ptr [[ULX]], align 8
34863 // SIMD-ONLY0-NEXT:    br label [[COND_END3705]]
34864 // SIMD-ONLY0:       cond.end3705:
34865 // SIMD-ONLY0-NEXT:    [[COND3706:%.*]] = phi i64 [ [[TMP1892]], [[COND_TRUE3703]] ], [ [[TMP1893]], [[COND_FALSE3704]] ]
34866 // SIMD-ONLY0-NEXT:    store i64 [[COND3706]], ptr [[ULX]], align 8
34867 // SIMD-ONLY0-NEXT:    [[TMP1894:%.*]] = load i64, ptr [[ULX]], align 8
34868 // SIMD-ONLY0-NEXT:    [[TMP1895:%.*]] = load i64, ptr [[ULE]], align 8
34869 // SIMD-ONLY0-NEXT:    [[CMP3707:%.*]] = icmp ult i64 [[TMP1894]], [[TMP1895]]
34870 // SIMD-ONLY0-NEXT:    br i1 [[CMP3707]], label [[COND_TRUE3709:%.*]], label [[COND_FALSE3710:%.*]]
34871 // SIMD-ONLY0:       cond.true3709:
34872 // SIMD-ONLY0-NEXT:    [[TMP1896:%.*]] = load i64, ptr [[ULE]], align 8
34873 // SIMD-ONLY0-NEXT:    br label [[COND_END3711:%.*]]
34874 // SIMD-ONLY0:       cond.false3710:
34875 // SIMD-ONLY0-NEXT:    [[TMP1897:%.*]] = load i64, ptr [[ULX]], align 8
34876 // SIMD-ONLY0-NEXT:    br label [[COND_END3711]]
34877 // SIMD-ONLY0:       cond.end3711:
34878 // SIMD-ONLY0-NEXT:    [[COND3712:%.*]] = phi i64 [ [[TMP1896]], [[COND_TRUE3709]] ], [ [[TMP1897]], [[COND_FALSE3710]] ]
34879 // SIMD-ONLY0-NEXT:    store i64 [[COND3712]], ptr [[ULX]], align 8
34880 // SIMD-ONLY0-NEXT:    [[TMP1898:%.*]] = load i64, ptr [[ULE]], align 8
34881 // SIMD-ONLY0-NEXT:    [[TMP1899:%.*]] = load i64, ptr [[ULX]], align 8
34882 // SIMD-ONLY0-NEXT:    [[CMP3713:%.*]] = icmp ugt i64 [[TMP1898]], [[TMP1899]]
34883 // SIMD-ONLY0-NEXT:    br i1 [[CMP3713]], label [[COND_TRUE3715:%.*]], label [[COND_FALSE3716:%.*]]
34884 // SIMD-ONLY0:       cond.true3715:
34885 // SIMD-ONLY0-NEXT:    [[TMP1900:%.*]] = load i64, ptr [[ULE]], align 8
34886 // SIMD-ONLY0-NEXT:    br label [[COND_END3717:%.*]]
34887 // SIMD-ONLY0:       cond.false3716:
34888 // SIMD-ONLY0-NEXT:    [[TMP1901:%.*]] = load i64, ptr [[ULX]], align 8
34889 // SIMD-ONLY0-NEXT:    br label [[COND_END3717]]
34890 // SIMD-ONLY0:       cond.end3717:
34891 // SIMD-ONLY0-NEXT:    [[COND3718:%.*]] = phi i64 [ [[TMP1900]], [[COND_TRUE3715]] ], [ [[TMP1901]], [[COND_FALSE3716]] ]
34892 // SIMD-ONLY0-NEXT:    store i64 [[COND3718]], ptr [[ULX]], align 8
34893 // SIMD-ONLY0-NEXT:    [[TMP1902:%.*]] = load i64, ptr [[ULE]], align 8
34894 // SIMD-ONLY0-NEXT:    [[TMP1903:%.*]] = load i64, ptr [[ULX]], align 8
34895 // SIMD-ONLY0-NEXT:    [[CMP3719:%.*]] = icmp ult i64 [[TMP1902]], [[TMP1903]]
34896 // SIMD-ONLY0-NEXT:    br i1 [[CMP3719]], label [[COND_TRUE3721:%.*]], label [[COND_FALSE3722:%.*]]
34897 // SIMD-ONLY0:       cond.true3721:
34898 // SIMD-ONLY0-NEXT:    [[TMP1904:%.*]] = load i64, ptr [[ULE]], align 8
34899 // SIMD-ONLY0-NEXT:    br label [[COND_END3723:%.*]]
34900 // SIMD-ONLY0:       cond.false3722:
34901 // SIMD-ONLY0-NEXT:    [[TMP1905:%.*]] = load i64, ptr [[ULX]], align 8
34902 // SIMD-ONLY0-NEXT:    br label [[COND_END3723]]
34903 // SIMD-ONLY0:       cond.end3723:
34904 // SIMD-ONLY0-NEXT:    [[COND3724:%.*]] = phi i64 [ [[TMP1904]], [[COND_TRUE3721]] ], [ [[TMP1905]], [[COND_FALSE3722]] ]
34905 // SIMD-ONLY0-NEXT:    store i64 [[COND3724]], ptr [[ULX]], align 8
34906 // SIMD-ONLY0-NEXT:    [[TMP1906:%.*]] = load i64, ptr [[ULX]], align 8
34907 // SIMD-ONLY0-NEXT:    [[TMP1907:%.*]] = load i64, ptr [[ULE]], align 8
34908 // SIMD-ONLY0-NEXT:    [[CMP3725:%.*]] = icmp ugt i64 [[TMP1906]], [[TMP1907]]
34909 // SIMD-ONLY0-NEXT:    br i1 [[CMP3725]], label [[IF_THEN3727:%.*]], label [[IF_END3728:%.*]]
34910 // SIMD-ONLY0:       if.then3727:
34911 // SIMD-ONLY0-NEXT:    [[TMP1908:%.*]] = load i64, ptr [[ULE]], align 8
34912 // SIMD-ONLY0-NEXT:    store i64 [[TMP1908]], ptr [[ULX]], align 8
34913 // SIMD-ONLY0-NEXT:    br label [[IF_END3728]]
34914 // SIMD-ONLY0:       if.end3728:
34915 // SIMD-ONLY0-NEXT:    [[TMP1909:%.*]] = load i64, ptr [[ULX]], align 8
34916 // SIMD-ONLY0-NEXT:    [[TMP1910:%.*]] = load i64, ptr [[ULE]], align 8
34917 // SIMD-ONLY0-NEXT:    [[CMP3729:%.*]] = icmp ult i64 [[TMP1909]], [[TMP1910]]
34918 // SIMD-ONLY0-NEXT:    br i1 [[CMP3729]], label [[IF_THEN3731:%.*]], label [[IF_END3732:%.*]]
34919 // SIMD-ONLY0:       if.then3731:
34920 // SIMD-ONLY0-NEXT:    [[TMP1911:%.*]] = load i64, ptr [[ULE]], align 8
34921 // SIMD-ONLY0-NEXT:    store i64 [[TMP1911]], ptr [[ULX]], align 8
34922 // SIMD-ONLY0-NEXT:    br label [[IF_END3732]]
34923 // SIMD-ONLY0:       if.end3732:
34924 // SIMD-ONLY0-NEXT:    [[TMP1912:%.*]] = load i64, ptr [[ULE]], align 8
34925 // SIMD-ONLY0-NEXT:    [[TMP1913:%.*]] = load i64, ptr [[ULX]], align 8
34926 // SIMD-ONLY0-NEXT:    [[CMP3733:%.*]] = icmp ugt i64 [[TMP1912]], [[TMP1913]]
34927 // SIMD-ONLY0-NEXT:    br i1 [[CMP3733]], label [[IF_THEN3735:%.*]], label [[IF_END3736:%.*]]
34928 // SIMD-ONLY0:       if.then3735:
34929 // SIMD-ONLY0-NEXT:    [[TMP1914:%.*]] = load i64, ptr [[ULE]], align 8
34930 // SIMD-ONLY0-NEXT:    store i64 [[TMP1914]], ptr [[ULX]], align 8
34931 // SIMD-ONLY0-NEXT:    br label [[IF_END3736]]
34932 // SIMD-ONLY0:       if.end3736:
34933 // SIMD-ONLY0-NEXT:    [[TMP1915:%.*]] = load i64, ptr [[ULE]], align 8
34934 // SIMD-ONLY0-NEXT:    [[TMP1916:%.*]] = load i64, ptr [[ULX]], align 8
34935 // SIMD-ONLY0-NEXT:    [[CMP3737:%.*]] = icmp ult i64 [[TMP1915]], [[TMP1916]]
34936 // SIMD-ONLY0-NEXT:    br i1 [[CMP3737]], label [[IF_THEN3739:%.*]], label [[IF_END3740:%.*]]
34937 // SIMD-ONLY0:       if.then3739:
34938 // SIMD-ONLY0-NEXT:    [[TMP1917:%.*]] = load i64, ptr [[ULE]], align 8
34939 // SIMD-ONLY0-NEXT:    store i64 [[TMP1917]], ptr [[ULX]], align 8
34940 // SIMD-ONLY0-NEXT:    br label [[IF_END3740]]
34941 // SIMD-ONLY0:       if.end3740:
34942 // SIMD-ONLY0-NEXT:    [[TMP1918:%.*]] = load i64, ptr [[ULX]], align 8
34943 // SIMD-ONLY0-NEXT:    [[TMP1919:%.*]] = load i64, ptr [[ULE]], align 8
34944 // SIMD-ONLY0-NEXT:    [[CMP3741:%.*]] = icmp eq i64 [[TMP1918]], [[TMP1919]]
34945 // SIMD-ONLY0-NEXT:    br i1 [[CMP3741]], label [[COND_TRUE3743:%.*]], label [[COND_FALSE3744:%.*]]
34946 // SIMD-ONLY0:       cond.true3743:
34947 // SIMD-ONLY0-NEXT:    [[TMP1920:%.*]] = load i64, ptr [[ULD]], align 8
34948 // SIMD-ONLY0-NEXT:    br label [[COND_END3745:%.*]]
34949 // SIMD-ONLY0:       cond.false3744:
34950 // SIMD-ONLY0-NEXT:    [[TMP1921:%.*]] = load i64, ptr [[ULX]], align 8
34951 // SIMD-ONLY0-NEXT:    br label [[COND_END3745]]
34952 // SIMD-ONLY0:       cond.end3745:
34953 // SIMD-ONLY0-NEXT:    [[COND3746:%.*]] = phi i64 [ [[TMP1920]], [[COND_TRUE3743]] ], [ [[TMP1921]], [[COND_FALSE3744]] ]
34954 // SIMD-ONLY0-NEXT:    store i64 [[COND3746]], ptr [[ULX]], align 8
34955 // SIMD-ONLY0-NEXT:    [[TMP1922:%.*]] = load i64, ptr [[ULE]], align 8
34956 // SIMD-ONLY0-NEXT:    [[TMP1923:%.*]] = load i64, ptr [[ULX]], align 8
34957 // SIMD-ONLY0-NEXT:    [[CMP3747:%.*]] = icmp eq i64 [[TMP1922]], [[TMP1923]]
34958 // SIMD-ONLY0-NEXT:    br i1 [[CMP3747]], label [[COND_TRUE3749:%.*]], label [[COND_FALSE3750:%.*]]
34959 // SIMD-ONLY0:       cond.true3749:
34960 // SIMD-ONLY0-NEXT:    [[TMP1924:%.*]] = load i64, ptr [[ULD]], align 8
34961 // SIMD-ONLY0-NEXT:    br label [[COND_END3751:%.*]]
34962 // SIMD-ONLY0:       cond.false3750:
34963 // SIMD-ONLY0-NEXT:    [[TMP1925:%.*]] = load i64, ptr [[ULX]], align 8
34964 // SIMD-ONLY0-NEXT:    br label [[COND_END3751]]
34965 // SIMD-ONLY0:       cond.end3751:
34966 // SIMD-ONLY0-NEXT:    [[COND3752:%.*]] = phi i64 [ [[TMP1924]], [[COND_TRUE3749]] ], [ [[TMP1925]], [[COND_FALSE3750]] ]
34967 // SIMD-ONLY0-NEXT:    store i64 [[COND3752]], ptr [[ULX]], align 8
34968 // SIMD-ONLY0-NEXT:    [[TMP1926:%.*]] = load i64, ptr [[ULX]], align 8
34969 // SIMD-ONLY0-NEXT:    [[TMP1927:%.*]] = load i64, ptr [[ULE]], align 8
34970 // SIMD-ONLY0-NEXT:    [[CMP3753:%.*]] = icmp eq i64 [[TMP1926]], [[TMP1927]]
34971 // SIMD-ONLY0-NEXT:    br i1 [[CMP3753]], label [[IF_THEN3755:%.*]], label [[IF_END3756:%.*]]
34972 // SIMD-ONLY0:       if.then3755:
34973 // SIMD-ONLY0-NEXT:    [[TMP1928:%.*]] = load i64, ptr [[ULD]], align 8
34974 // SIMD-ONLY0-NEXT:    store i64 [[TMP1928]], ptr [[ULX]], align 8
34975 // SIMD-ONLY0-NEXT:    br label [[IF_END3756]]
34976 // SIMD-ONLY0:       if.end3756:
34977 // SIMD-ONLY0-NEXT:    [[TMP1929:%.*]] = load i64, ptr [[ULE]], align 8
34978 // SIMD-ONLY0-NEXT:    [[TMP1930:%.*]] = load i64, ptr [[ULX]], align 8
34979 // SIMD-ONLY0-NEXT:    [[CMP3757:%.*]] = icmp eq i64 [[TMP1929]], [[TMP1930]]
34980 // SIMD-ONLY0-NEXT:    br i1 [[CMP3757]], label [[IF_THEN3759:%.*]], label [[IF_END3760:%.*]]
34981 // SIMD-ONLY0:       if.then3759:
34982 // SIMD-ONLY0-NEXT:    [[TMP1931:%.*]] = load i64, ptr [[ULD]], align 8
34983 // SIMD-ONLY0-NEXT:    store i64 [[TMP1931]], ptr [[ULX]], align 8
34984 // SIMD-ONLY0-NEXT:    br label [[IF_END3760]]
34985 // SIMD-ONLY0:       if.end3760:
34986 // SIMD-ONLY0-NEXT:    [[TMP1932:%.*]] = load i64, ptr [[LX]], align 8
34987 // SIMD-ONLY0-NEXT:    [[TMP1933:%.*]] = load i64, ptr [[LE]], align 8
34988 // SIMD-ONLY0-NEXT:    [[CMP3761:%.*]] = icmp sgt i64 [[TMP1932]], [[TMP1933]]
34989 // SIMD-ONLY0-NEXT:    br i1 [[CMP3761]], label [[COND_TRUE3763:%.*]], label [[COND_FALSE3764:%.*]]
34990 // SIMD-ONLY0:       cond.true3763:
34991 // SIMD-ONLY0-NEXT:    [[TMP1934:%.*]] = load i64, ptr [[LE]], align 8
34992 // SIMD-ONLY0-NEXT:    br label [[COND_END3765:%.*]]
34993 // SIMD-ONLY0:       cond.false3764:
34994 // SIMD-ONLY0-NEXT:    [[TMP1935:%.*]] = load i64, ptr [[LX]], align 8
34995 // SIMD-ONLY0-NEXT:    br label [[COND_END3765]]
34996 // SIMD-ONLY0:       cond.end3765:
34997 // SIMD-ONLY0-NEXT:    [[COND3766:%.*]] = phi i64 [ [[TMP1934]], [[COND_TRUE3763]] ], [ [[TMP1935]], [[COND_FALSE3764]] ]
34998 // SIMD-ONLY0-NEXT:    store i64 [[COND3766]], ptr [[LX]], align 8
34999 // SIMD-ONLY0-NEXT:    [[TMP1936:%.*]] = load i64, ptr [[LX]], align 8
35000 // SIMD-ONLY0-NEXT:    [[TMP1937:%.*]] = load i64, ptr [[LE]], align 8
35001 // SIMD-ONLY0-NEXT:    [[CMP3767:%.*]] = icmp slt i64 [[TMP1936]], [[TMP1937]]
35002 // SIMD-ONLY0-NEXT:    br i1 [[CMP3767]], label [[COND_TRUE3769:%.*]], label [[COND_FALSE3770:%.*]]
35003 // SIMD-ONLY0:       cond.true3769:
35004 // SIMD-ONLY0-NEXT:    [[TMP1938:%.*]] = load i64, ptr [[LE]], align 8
35005 // SIMD-ONLY0-NEXT:    br label [[COND_END3771:%.*]]
35006 // SIMD-ONLY0:       cond.false3770:
35007 // SIMD-ONLY0-NEXT:    [[TMP1939:%.*]] = load i64, ptr [[LX]], align 8
35008 // SIMD-ONLY0-NEXT:    br label [[COND_END3771]]
35009 // SIMD-ONLY0:       cond.end3771:
35010 // SIMD-ONLY0-NEXT:    [[COND3772:%.*]] = phi i64 [ [[TMP1938]], [[COND_TRUE3769]] ], [ [[TMP1939]], [[COND_FALSE3770]] ]
35011 // SIMD-ONLY0-NEXT:    store i64 [[COND3772]], ptr [[LX]], align 8
35012 // SIMD-ONLY0-NEXT:    [[TMP1940:%.*]] = load i64, ptr [[LE]], align 8
35013 // SIMD-ONLY0-NEXT:    [[TMP1941:%.*]] = load i64, ptr [[LX]], align 8
35014 // SIMD-ONLY0-NEXT:    [[CMP3773:%.*]] = icmp sgt i64 [[TMP1940]], [[TMP1941]]
35015 // SIMD-ONLY0-NEXT:    br i1 [[CMP3773]], label [[COND_TRUE3775:%.*]], label [[COND_FALSE3776:%.*]]
35016 // SIMD-ONLY0:       cond.true3775:
35017 // SIMD-ONLY0-NEXT:    [[TMP1942:%.*]] = load i64, ptr [[LE]], align 8
35018 // SIMD-ONLY0-NEXT:    br label [[COND_END3777:%.*]]
35019 // SIMD-ONLY0:       cond.false3776:
35020 // SIMD-ONLY0-NEXT:    [[TMP1943:%.*]] = load i64, ptr [[LX]], align 8
35021 // SIMD-ONLY0-NEXT:    br label [[COND_END3777]]
35022 // SIMD-ONLY0:       cond.end3777:
35023 // SIMD-ONLY0-NEXT:    [[COND3778:%.*]] = phi i64 [ [[TMP1942]], [[COND_TRUE3775]] ], [ [[TMP1943]], [[COND_FALSE3776]] ]
35024 // SIMD-ONLY0-NEXT:    store i64 [[COND3778]], ptr [[LX]], align 8
35025 // SIMD-ONLY0-NEXT:    [[TMP1944:%.*]] = load i64, ptr [[LE]], align 8
35026 // SIMD-ONLY0-NEXT:    [[TMP1945:%.*]] = load i64, ptr [[LX]], align 8
35027 // SIMD-ONLY0-NEXT:    [[CMP3779:%.*]] = icmp slt i64 [[TMP1944]], [[TMP1945]]
35028 // SIMD-ONLY0-NEXT:    br i1 [[CMP3779]], label [[COND_TRUE3781:%.*]], label [[COND_FALSE3782:%.*]]
35029 // SIMD-ONLY0:       cond.true3781:
35030 // SIMD-ONLY0-NEXT:    [[TMP1946:%.*]] = load i64, ptr [[LE]], align 8
35031 // SIMD-ONLY0-NEXT:    br label [[COND_END3783:%.*]]
35032 // SIMD-ONLY0:       cond.false3782:
35033 // SIMD-ONLY0-NEXT:    [[TMP1947:%.*]] = load i64, ptr [[LX]], align 8
35034 // SIMD-ONLY0-NEXT:    br label [[COND_END3783]]
35035 // SIMD-ONLY0:       cond.end3783:
35036 // SIMD-ONLY0-NEXT:    [[COND3784:%.*]] = phi i64 [ [[TMP1946]], [[COND_TRUE3781]] ], [ [[TMP1947]], [[COND_FALSE3782]] ]
35037 // SIMD-ONLY0-NEXT:    store i64 [[COND3784]], ptr [[LX]], align 8
35038 // SIMD-ONLY0-NEXT:    [[TMP1948:%.*]] = load i64, ptr [[LX]], align 8
35039 // SIMD-ONLY0-NEXT:    [[TMP1949:%.*]] = load i64, ptr [[LE]], align 8
35040 // SIMD-ONLY0-NEXT:    [[CMP3785:%.*]] = icmp sgt i64 [[TMP1948]], [[TMP1949]]
35041 // SIMD-ONLY0-NEXT:    br i1 [[CMP3785]], label [[IF_THEN3787:%.*]], label [[IF_END3788:%.*]]
35042 // SIMD-ONLY0:       if.then3787:
35043 // SIMD-ONLY0-NEXT:    [[TMP1950:%.*]] = load i64, ptr [[LE]], align 8
35044 // SIMD-ONLY0-NEXT:    store i64 [[TMP1950]], ptr [[LX]], align 8
35045 // SIMD-ONLY0-NEXT:    br label [[IF_END3788]]
35046 // SIMD-ONLY0:       if.end3788:
35047 // SIMD-ONLY0-NEXT:    [[TMP1951:%.*]] = load i64, ptr [[LX]], align 8
35048 // SIMD-ONLY0-NEXT:    [[TMP1952:%.*]] = load i64, ptr [[LE]], align 8
35049 // SIMD-ONLY0-NEXT:    [[CMP3789:%.*]] = icmp slt i64 [[TMP1951]], [[TMP1952]]
35050 // SIMD-ONLY0-NEXT:    br i1 [[CMP3789]], label [[IF_THEN3791:%.*]], label [[IF_END3792:%.*]]
35051 // SIMD-ONLY0:       if.then3791:
35052 // SIMD-ONLY0-NEXT:    [[TMP1953:%.*]] = load i64, ptr [[LE]], align 8
35053 // SIMD-ONLY0-NEXT:    store i64 [[TMP1953]], ptr [[LX]], align 8
35054 // SIMD-ONLY0-NEXT:    br label [[IF_END3792]]
35055 // SIMD-ONLY0:       if.end3792:
35056 // SIMD-ONLY0-NEXT:    [[TMP1954:%.*]] = load i64, ptr [[LE]], align 8
35057 // SIMD-ONLY0-NEXT:    [[TMP1955:%.*]] = load i64, ptr [[LX]], align 8
35058 // SIMD-ONLY0-NEXT:    [[CMP3793:%.*]] = icmp sgt i64 [[TMP1954]], [[TMP1955]]
35059 // SIMD-ONLY0-NEXT:    br i1 [[CMP3793]], label [[IF_THEN3795:%.*]], label [[IF_END3796:%.*]]
35060 // SIMD-ONLY0:       if.then3795:
35061 // SIMD-ONLY0-NEXT:    [[TMP1956:%.*]] = load i64, ptr [[LE]], align 8
35062 // SIMD-ONLY0-NEXT:    store i64 [[TMP1956]], ptr [[LX]], align 8
35063 // SIMD-ONLY0-NEXT:    br label [[IF_END3796]]
35064 // SIMD-ONLY0:       if.end3796:
35065 // SIMD-ONLY0-NEXT:    [[TMP1957:%.*]] = load i64, ptr [[LE]], align 8
35066 // SIMD-ONLY0-NEXT:    [[TMP1958:%.*]] = load i64, ptr [[LX]], align 8
35067 // SIMD-ONLY0-NEXT:    [[CMP3797:%.*]] = icmp slt i64 [[TMP1957]], [[TMP1958]]
35068 // SIMD-ONLY0-NEXT:    br i1 [[CMP3797]], label [[IF_THEN3799:%.*]], label [[IF_END3800:%.*]]
35069 // SIMD-ONLY0:       if.then3799:
35070 // SIMD-ONLY0-NEXT:    [[TMP1959:%.*]] = load i64, ptr [[LE]], align 8
35071 // SIMD-ONLY0-NEXT:    store i64 [[TMP1959]], ptr [[LX]], align 8
35072 // SIMD-ONLY0-NEXT:    br label [[IF_END3800]]
35073 // SIMD-ONLY0:       if.end3800:
35074 // SIMD-ONLY0-NEXT:    [[TMP1960:%.*]] = load i64, ptr [[LX]], align 8
35075 // SIMD-ONLY0-NEXT:    [[TMP1961:%.*]] = load i64, ptr [[LE]], align 8
35076 // SIMD-ONLY0-NEXT:    [[CMP3801:%.*]] = icmp eq i64 [[TMP1960]], [[TMP1961]]
35077 // SIMD-ONLY0-NEXT:    br i1 [[CMP3801]], label [[COND_TRUE3803:%.*]], label [[COND_FALSE3804:%.*]]
35078 // SIMD-ONLY0:       cond.true3803:
35079 // SIMD-ONLY0-NEXT:    [[TMP1962:%.*]] = load i64, ptr [[LD]], align 8
35080 // SIMD-ONLY0-NEXT:    br label [[COND_END3805:%.*]]
35081 // SIMD-ONLY0:       cond.false3804:
35082 // SIMD-ONLY0-NEXT:    [[TMP1963:%.*]] = load i64, ptr [[LX]], align 8
35083 // SIMD-ONLY0-NEXT:    br label [[COND_END3805]]
35084 // SIMD-ONLY0:       cond.end3805:
35085 // SIMD-ONLY0-NEXT:    [[COND3806:%.*]] = phi i64 [ [[TMP1962]], [[COND_TRUE3803]] ], [ [[TMP1963]], [[COND_FALSE3804]] ]
35086 // SIMD-ONLY0-NEXT:    store i64 [[COND3806]], ptr [[LX]], align 8
35087 // SIMD-ONLY0-NEXT:    [[TMP1964:%.*]] = load i64, ptr [[LE]], align 8
35088 // SIMD-ONLY0-NEXT:    [[TMP1965:%.*]] = load i64, ptr [[LX]], align 8
35089 // SIMD-ONLY0-NEXT:    [[CMP3807:%.*]] = icmp eq i64 [[TMP1964]], [[TMP1965]]
35090 // SIMD-ONLY0-NEXT:    br i1 [[CMP3807]], label [[COND_TRUE3809:%.*]], label [[COND_FALSE3810:%.*]]
35091 // SIMD-ONLY0:       cond.true3809:
35092 // SIMD-ONLY0-NEXT:    [[TMP1966:%.*]] = load i64, ptr [[LD]], align 8
35093 // SIMD-ONLY0-NEXT:    br label [[COND_END3811:%.*]]
35094 // SIMD-ONLY0:       cond.false3810:
35095 // SIMD-ONLY0-NEXT:    [[TMP1967:%.*]] = load i64, ptr [[LX]], align 8
35096 // SIMD-ONLY0-NEXT:    br label [[COND_END3811]]
35097 // SIMD-ONLY0:       cond.end3811:
35098 // SIMD-ONLY0-NEXT:    [[COND3812:%.*]] = phi i64 [ [[TMP1966]], [[COND_TRUE3809]] ], [ [[TMP1967]], [[COND_FALSE3810]] ]
35099 // SIMD-ONLY0-NEXT:    store i64 [[COND3812]], ptr [[LX]], align 8
35100 // SIMD-ONLY0-NEXT:    [[TMP1968:%.*]] = load i64, ptr [[LX]], align 8
35101 // SIMD-ONLY0-NEXT:    [[TMP1969:%.*]] = load i64, ptr [[LE]], align 8
35102 // SIMD-ONLY0-NEXT:    [[CMP3813:%.*]] = icmp eq i64 [[TMP1968]], [[TMP1969]]
35103 // SIMD-ONLY0-NEXT:    br i1 [[CMP3813]], label [[IF_THEN3815:%.*]], label [[IF_END3816:%.*]]
35104 // SIMD-ONLY0:       if.then3815:
35105 // SIMD-ONLY0-NEXT:    [[TMP1970:%.*]] = load i64, ptr [[LD]], align 8
35106 // SIMD-ONLY0-NEXT:    store i64 [[TMP1970]], ptr [[LX]], align 8
35107 // SIMD-ONLY0-NEXT:    br label [[IF_END3816]]
35108 // SIMD-ONLY0:       if.end3816:
35109 // SIMD-ONLY0-NEXT:    [[TMP1971:%.*]] = load i64, ptr [[LE]], align 8
35110 // SIMD-ONLY0-NEXT:    [[TMP1972:%.*]] = load i64, ptr [[LX]], align 8
35111 // SIMD-ONLY0-NEXT:    [[CMP3817:%.*]] = icmp eq i64 [[TMP1971]], [[TMP1972]]
35112 // SIMD-ONLY0-NEXT:    br i1 [[CMP3817]], label [[IF_THEN3819:%.*]], label [[IF_END3820:%.*]]
35113 // SIMD-ONLY0:       if.then3819:
35114 // SIMD-ONLY0-NEXT:    [[TMP1973:%.*]] = load i64, ptr [[LD]], align 8
35115 // SIMD-ONLY0-NEXT:    store i64 [[TMP1973]], ptr [[LX]], align 8
35116 // SIMD-ONLY0-NEXT:    br label [[IF_END3820]]
35117 // SIMD-ONLY0:       if.end3820:
35118 // SIMD-ONLY0-NEXT:    [[TMP1974:%.*]] = load i64, ptr [[ULX]], align 8
35119 // SIMD-ONLY0-NEXT:    [[TMP1975:%.*]] = load i64, ptr [[ULE]], align 8
35120 // SIMD-ONLY0-NEXT:    [[CMP3821:%.*]] = icmp ugt i64 [[TMP1974]], [[TMP1975]]
35121 // SIMD-ONLY0-NEXT:    br i1 [[CMP3821]], label [[COND_TRUE3823:%.*]], label [[COND_FALSE3824:%.*]]
35122 // SIMD-ONLY0:       cond.true3823:
35123 // SIMD-ONLY0-NEXT:    [[TMP1976:%.*]] = load i64, ptr [[ULE]], align 8
35124 // SIMD-ONLY0-NEXT:    br label [[COND_END3825:%.*]]
35125 // SIMD-ONLY0:       cond.false3824:
35126 // SIMD-ONLY0-NEXT:    [[TMP1977:%.*]] = load i64, ptr [[ULX]], align 8
35127 // SIMD-ONLY0-NEXT:    br label [[COND_END3825]]
35128 // SIMD-ONLY0:       cond.end3825:
35129 // SIMD-ONLY0-NEXT:    [[COND3826:%.*]] = phi i64 [ [[TMP1976]], [[COND_TRUE3823]] ], [ [[TMP1977]], [[COND_FALSE3824]] ]
35130 // SIMD-ONLY0-NEXT:    store i64 [[COND3826]], ptr [[ULX]], align 8
35131 // SIMD-ONLY0-NEXT:    [[TMP1978:%.*]] = load i64, ptr [[ULX]], align 8
35132 // SIMD-ONLY0-NEXT:    [[TMP1979:%.*]] = load i64, ptr [[ULE]], align 8
35133 // SIMD-ONLY0-NEXT:    [[CMP3827:%.*]] = icmp ult i64 [[TMP1978]], [[TMP1979]]
35134 // SIMD-ONLY0-NEXT:    br i1 [[CMP3827]], label [[COND_TRUE3829:%.*]], label [[COND_FALSE3830:%.*]]
35135 // SIMD-ONLY0:       cond.true3829:
35136 // SIMD-ONLY0-NEXT:    [[TMP1980:%.*]] = load i64, ptr [[ULE]], align 8
35137 // SIMD-ONLY0-NEXT:    br label [[COND_END3831:%.*]]
35138 // SIMD-ONLY0:       cond.false3830:
35139 // SIMD-ONLY0-NEXT:    [[TMP1981:%.*]] = load i64, ptr [[ULX]], align 8
35140 // SIMD-ONLY0-NEXT:    br label [[COND_END3831]]
35141 // SIMD-ONLY0:       cond.end3831:
35142 // SIMD-ONLY0-NEXT:    [[COND3832:%.*]] = phi i64 [ [[TMP1980]], [[COND_TRUE3829]] ], [ [[TMP1981]], [[COND_FALSE3830]] ]
35143 // SIMD-ONLY0-NEXT:    store i64 [[COND3832]], ptr [[ULX]], align 8
35144 // SIMD-ONLY0-NEXT:    [[TMP1982:%.*]] = load i64, ptr [[ULE]], align 8
35145 // SIMD-ONLY0-NEXT:    [[TMP1983:%.*]] = load i64, ptr [[ULX]], align 8
35146 // SIMD-ONLY0-NEXT:    [[CMP3833:%.*]] = icmp ugt i64 [[TMP1982]], [[TMP1983]]
35147 // SIMD-ONLY0-NEXT:    br i1 [[CMP3833]], label [[COND_TRUE3835:%.*]], label [[COND_FALSE3836:%.*]]
35148 // SIMD-ONLY0:       cond.true3835:
35149 // SIMD-ONLY0-NEXT:    [[TMP1984:%.*]] = load i64, ptr [[ULE]], align 8
35150 // SIMD-ONLY0-NEXT:    br label [[COND_END3837:%.*]]
35151 // SIMD-ONLY0:       cond.false3836:
35152 // SIMD-ONLY0-NEXT:    [[TMP1985:%.*]] = load i64, ptr [[ULX]], align 8
35153 // SIMD-ONLY0-NEXT:    br label [[COND_END3837]]
35154 // SIMD-ONLY0:       cond.end3837:
35155 // SIMD-ONLY0-NEXT:    [[COND3838:%.*]] = phi i64 [ [[TMP1984]], [[COND_TRUE3835]] ], [ [[TMP1985]], [[COND_FALSE3836]] ]
35156 // SIMD-ONLY0-NEXT:    store i64 [[COND3838]], ptr [[ULX]], align 8
35157 // SIMD-ONLY0-NEXT:    [[TMP1986:%.*]] = load i64, ptr [[ULE]], align 8
35158 // SIMD-ONLY0-NEXT:    [[TMP1987:%.*]] = load i64, ptr [[ULX]], align 8
35159 // SIMD-ONLY0-NEXT:    [[CMP3839:%.*]] = icmp ult i64 [[TMP1986]], [[TMP1987]]
35160 // SIMD-ONLY0-NEXT:    br i1 [[CMP3839]], label [[COND_TRUE3841:%.*]], label [[COND_FALSE3842:%.*]]
35161 // SIMD-ONLY0:       cond.true3841:
35162 // SIMD-ONLY0-NEXT:    [[TMP1988:%.*]] = load i64, ptr [[ULE]], align 8
35163 // SIMD-ONLY0-NEXT:    br label [[COND_END3843:%.*]]
35164 // SIMD-ONLY0:       cond.false3842:
35165 // SIMD-ONLY0-NEXT:    [[TMP1989:%.*]] = load i64, ptr [[ULX]], align 8
35166 // SIMD-ONLY0-NEXT:    br label [[COND_END3843]]
35167 // SIMD-ONLY0:       cond.end3843:
35168 // SIMD-ONLY0-NEXT:    [[COND3844:%.*]] = phi i64 [ [[TMP1988]], [[COND_TRUE3841]] ], [ [[TMP1989]], [[COND_FALSE3842]] ]
35169 // SIMD-ONLY0-NEXT:    store i64 [[COND3844]], ptr [[ULX]], align 8
35170 // SIMD-ONLY0-NEXT:    [[TMP1990:%.*]] = load i64, ptr [[ULX]], align 8
35171 // SIMD-ONLY0-NEXT:    [[TMP1991:%.*]] = load i64, ptr [[ULE]], align 8
35172 // SIMD-ONLY0-NEXT:    [[CMP3845:%.*]] = icmp ugt i64 [[TMP1990]], [[TMP1991]]
35173 // SIMD-ONLY0-NEXT:    br i1 [[CMP3845]], label [[IF_THEN3847:%.*]], label [[IF_END3848:%.*]]
35174 // SIMD-ONLY0:       if.then3847:
35175 // SIMD-ONLY0-NEXT:    [[TMP1992:%.*]] = load i64, ptr [[ULE]], align 8
35176 // SIMD-ONLY0-NEXT:    store i64 [[TMP1992]], ptr [[ULX]], align 8
35177 // SIMD-ONLY0-NEXT:    br label [[IF_END3848]]
35178 // SIMD-ONLY0:       if.end3848:
35179 // SIMD-ONLY0-NEXT:    [[TMP1993:%.*]] = load i64, ptr [[ULX]], align 8
35180 // SIMD-ONLY0-NEXT:    [[TMP1994:%.*]] = load i64, ptr [[ULE]], align 8
35181 // SIMD-ONLY0-NEXT:    [[CMP3849:%.*]] = icmp ult i64 [[TMP1993]], [[TMP1994]]
35182 // SIMD-ONLY0-NEXT:    br i1 [[CMP3849]], label [[IF_THEN3851:%.*]], label [[IF_END3852:%.*]]
35183 // SIMD-ONLY0:       if.then3851:
35184 // SIMD-ONLY0-NEXT:    [[TMP1995:%.*]] = load i64, ptr [[ULE]], align 8
35185 // SIMD-ONLY0-NEXT:    store i64 [[TMP1995]], ptr [[ULX]], align 8
35186 // SIMD-ONLY0-NEXT:    br label [[IF_END3852]]
35187 // SIMD-ONLY0:       if.end3852:
35188 // SIMD-ONLY0-NEXT:    [[TMP1996:%.*]] = load i64, ptr [[ULE]], align 8
35189 // SIMD-ONLY0-NEXT:    [[TMP1997:%.*]] = load i64, ptr [[ULX]], align 8
35190 // SIMD-ONLY0-NEXT:    [[CMP3853:%.*]] = icmp ugt i64 [[TMP1996]], [[TMP1997]]
35191 // SIMD-ONLY0-NEXT:    br i1 [[CMP3853]], label [[IF_THEN3855:%.*]], label [[IF_END3856:%.*]]
35192 // SIMD-ONLY0:       if.then3855:
35193 // SIMD-ONLY0-NEXT:    [[TMP1998:%.*]] = load i64, ptr [[ULE]], align 8
35194 // SIMD-ONLY0-NEXT:    store i64 [[TMP1998]], ptr [[ULX]], align 8
35195 // SIMD-ONLY0-NEXT:    br label [[IF_END3856]]
35196 // SIMD-ONLY0:       if.end3856:
35197 // SIMD-ONLY0-NEXT:    [[TMP1999:%.*]] = load i64, ptr [[ULE]], align 8
35198 // SIMD-ONLY0-NEXT:    [[TMP2000:%.*]] = load i64, ptr [[ULX]], align 8
35199 // SIMD-ONLY0-NEXT:    [[CMP3857:%.*]] = icmp ult i64 [[TMP1999]], [[TMP2000]]
35200 // SIMD-ONLY0-NEXT:    br i1 [[CMP3857]], label [[IF_THEN3859:%.*]], label [[IF_END3860:%.*]]
35201 // SIMD-ONLY0:       if.then3859:
35202 // SIMD-ONLY0-NEXT:    [[TMP2001:%.*]] = load i64, ptr [[ULE]], align 8
35203 // SIMD-ONLY0-NEXT:    store i64 [[TMP2001]], ptr [[ULX]], align 8
35204 // SIMD-ONLY0-NEXT:    br label [[IF_END3860]]
35205 // SIMD-ONLY0:       if.end3860:
35206 // SIMD-ONLY0-NEXT:    [[TMP2002:%.*]] = load i64, ptr [[ULX]], align 8
35207 // SIMD-ONLY0-NEXT:    [[TMP2003:%.*]] = load i64, ptr [[ULE]], align 8
35208 // SIMD-ONLY0-NEXT:    [[CMP3861:%.*]] = icmp eq i64 [[TMP2002]], [[TMP2003]]
35209 // SIMD-ONLY0-NEXT:    br i1 [[CMP3861]], label [[COND_TRUE3863:%.*]], label [[COND_FALSE3864:%.*]]
35210 // SIMD-ONLY0:       cond.true3863:
35211 // SIMD-ONLY0-NEXT:    [[TMP2004:%.*]] = load i64, ptr [[ULD]], align 8
35212 // SIMD-ONLY0-NEXT:    br label [[COND_END3865:%.*]]
35213 // SIMD-ONLY0:       cond.false3864:
35214 // SIMD-ONLY0-NEXT:    [[TMP2005:%.*]] = load i64, ptr [[ULX]], align 8
35215 // SIMD-ONLY0-NEXT:    br label [[COND_END3865]]
35216 // SIMD-ONLY0:       cond.end3865:
35217 // SIMD-ONLY0-NEXT:    [[COND3866:%.*]] = phi i64 [ [[TMP2004]], [[COND_TRUE3863]] ], [ [[TMP2005]], [[COND_FALSE3864]] ]
35218 // SIMD-ONLY0-NEXT:    store i64 [[COND3866]], ptr [[ULX]], align 8
35219 // SIMD-ONLY0-NEXT:    [[TMP2006:%.*]] = load i64, ptr [[ULE]], align 8
35220 // SIMD-ONLY0-NEXT:    [[TMP2007:%.*]] = load i64, ptr [[ULX]], align 8
35221 // SIMD-ONLY0-NEXT:    [[CMP3867:%.*]] = icmp eq i64 [[TMP2006]], [[TMP2007]]
35222 // SIMD-ONLY0-NEXT:    br i1 [[CMP3867]], label [[COND_TRUE3869:%.*]], label [[COND_FALSE3870:%.*]]
35223 // SIMD-ONLY0:       cond.true3869:
35224 // SIMD-ONLY0-NEXT:    [[TMP2008:%.*]] = load i64, ptr [[ULD]], align 8
35225 // SIMD-ONLY0-NEXT:    br label [[COND_END3871:%.*]]
35226 // SIMD-ONLY0:       cond.false3870:
35227 // SIMD-ONLY0-NEXT:    [[TMP2009:%.*]] = load i64, ptr [[ULX]], align 8
35228 // SIMD-ONLY0-NEXT:    br label [[COND_END3871]]
35229 // SIMD-ONLY0:       cond.end3871:
35230 // SIMD-ONLY0-NEXT:    [[COND3872:%.*]] = phi i64 [ [[TMP2008]], [[COND_TRUE3869]] ], [ [[TMP2009]], [[COND_FALSE3870]] ]
35231 // SIMD-ONLY0-NEXT:    store i64 [[COND3872]], ptr [[ULX]], align 8
35232 // SIMD-ONLY0-NEXT:    [[TMP2010:%.*]] = load i64, ptr [[ULX]], align 8
35233 // SIMD-ONLY0-NEXT:    [[TMP2011:%.*]] = load i64, ptr [[ULE]], align 8
35234 // SIMD-ONLY0-NEXT:    [[CMP3873:%.*]] = icmp eq i64 [[TMP2010]], [[TMP2011]]
35235 // SIMD-ONLY0-NEXT:    br i1 [[CMP3873]], label [[IF_THEN3875:%.*]], label [[IF_END3876:%.*]]
35236 // SIMD-ONLY0:       if.then3875:
35237 // SIMD-ONLY0-NEXT:    [[TMP2012:%.*]] = load i64, ptr [[ULD]], align 8
35238 // SIMD-ONLY0-NEXT:    store i64 [[TMP2012]], ptr [[ULX]], align 8
35239 // SIMD-ONLY0-NEXT:    br label [[IF_END3876]]
35240 // SIMD-ONLY0:       if.end3876:
35241 // SIMD-ONLY0-NEXT:    [[TMP2013:%.*]] = load i64, ptr [[ULE]], align 8
35242 // SIMD-ONLY0-NEXT:    [[TMP2014:%.*]] = load i64, ptr [[ULX]], align 8
35243 // SIMD-ONLY0-NEXT:    [[CMP3877:%.*]] = icmp eq i64 [[TMP2013]], [[TMP2014]]
35244 // SIMD-ONLY0-NEXT:    br i1 [[CMP3877]], label [[IF_THEN3879:%.*]], label [[IF_END3880:%.*]]
35245 // SIMD-ONLY0:       if.then3879:
35246 // SIMD-ONLY0-NEXT:    [[TMP2015:%.*]] = load i64, ptr [[ULD]], align 8
35247 // SIMD-ONLY0-NEXT:    store i64 [[TMP2015]], ptr [[ULX]], align 8
35248 // SIMD-ONLY0-NEXT:    br label [[IF_END3880]]
35249 // SIMD-ONLY0:       if.end3880:
35250 // SIMD-ONLY0-NEXT:    [[TMP2016:%.*]] = load i64, ptr [[LLX]], align 8
35251 // SIMD-ONLY0-NEXT:    [[TMP2017:%.*]] = load i64, ptr [[LLE]], align 8
35252 // SIMD-ONLY0-NEXT:    [[CMP3881:%.*]] = icmp sgt i64 [[TMP2016]], [[TMP2017]]
35253 // SIMD-ONLY0-NEXT:    br i1 [[CMP3881]], label [[COND_TRUE3883:%.*]], label [[COND_FALSE3884:%.*]]
35254 // SIMD-ONLY0:       cond.true3883:
35255 // SIMD-ONLY0-NEXT:    [[TMP2018:%.*]] = load i64, ptr [[LLE]], align 8
35256 // SIMD-ONLY0-NEXT:    br label [[COND_END3885:%.*]]
35257 // SIMD-ONLY0:       cond.false3884:
35258 // SIMD-ONLY0-NEXT:    [[TMP2019:%.*]] = load i64, ptr [[LLX]], align 8
35259 // SIMD-ONLY0-NEXT:    br label [[COND_END3885]]
35260 // SIMD-ONLY0:       cond.end3885:
35261 // SIMD-ONLY0-NEXT:    [[COND3886:%.*]] = phi i64 [ [[TMP2018]], [[COND_TRUE3883]] ], [ [[TMP2019]], [[COND_FALSE3884]] ]
35262 // SIMD-ONLY0-NEXT:    store i64 [[COND3886]], ptr [[LLX]], align 8
35263 // SIMD-ONLY0-NEXT:    [[TMP2020:%.*]] = load i64, ptr [[LLX]], align 8
35264 // SIMD-ONLY0-NEXT:    [[TMP2021:%.*]] = load i64, ptr [[LLE]], align 8
35265 // SIMD-ONLY0-NEXT:    [[CMP3887:%.*]] = icmp slt i64 [[TMP2020]], [[TMP2021]]
35266 // SIMD-ONLY0-NEXT:    br i1 [[CMP3887]], label [[COND_TRUE3889:%.*]], label [[COND_FALSE3890:%.*]]
35267 // SIMD-ONLY0:       cond.true3889:
35268 // SIMD-ONLY0-NEXT:    [[TMP2022:%.*]] = load i64, ptr [[LLE]], align 8
35269 // SIMD-ONLY0-NEXT:    br label [[COND_END3891:%.*]]
35270 // SIMD-ONLY0:       cond.false3890:
35271 // SIMD-ONLY0-NEXT:    [[TMP2023:%.*]] = load i64, ptr [[LLX]], align 8
35272 // SIMD-ONLY0-NEXT:    br label [[COND_END3891]]
35273 // SIMD-ONLY0:       cond.end3891:
35274 // SIMD-ONLY0-NEXT:    [[COND3892:%.*]] = phi i64 [ [[TMP2022]], [[COND_TRUE3889]] ], [ [[TMP2023]], [[COND_FALSE3890]] ]
35275 // SIMD-ONLY0-NEXT:    store i64 [[COND3892]], ptr [[LLX]], align 8
35276 // SIMD-ONLY0-NEXT:    [[TMP2024:%.*]] = load i64, ptr [[LLE]], align 8
35277 // SIMD-ONLY0-NEXT:    [[TMP2025:%.*]] = load i64, ptr [[LLX]], align 8
35278 // SIMD-ONLY0-NEXT:    [[CMP3893:%.*]] = icmp sgt i64 [[TMP2024]], [[TMP2025]]
35279 // SIMD-ONLY0-NEXT:    br i1 [[CMP3893]], label [[COND_TRUE3895:%.*]], label [[COND_FALSE3896:%.*]]
35280 // SIMD-ONLY0:       cond.true3895:
35281 // SIMD-ONLY0-NEXT:    [[TMP2026:%.*]] = load i64, ptr [[LLE]], align 8
35282 // SIMD-ONLY0-NEXT:    br label [[COND_END3897:%.*]]
35283 // SIMD-ONLY0:       cond.false3896:
35284 // SIMD-ONLY0-NEXT:    [[TMP2027:%.*]] = load i64, ptr [[LLX]], align 8
35285 // SIMD-ONLY0-NEXT:    br label [[COND_END3897]]
35286 // SIMD-ONLY0:       cond.end3897:
35287 // SIMD-ONLY0-NEXT:    [[COND3898:%.*]] = phi i64 [ [[TMP2026]], [[COND_TRUE3895]] ], [ [[TMP2027]], [[COND_FALSE3896]] ]
35288 // SIMD-ONLY0-NEXT:    store i64 [[COND3898]], ptr [[LLX]], align 8
35289 // SIMD-ONLY0-NEXT:    [[TMP2028:%.*]] = load i64, ptr [[LLE]], align 8
35290 // SIMD-ONLY0-NEXT:    [[TMP2029:%.*]] = load i64, ptr [[LLX]], align 8
35291 // SIMD-ONLY0-NEXT:    [[CMP3899:%.*]] = icmp slt i64 [[TMP2028]], [[TMP2029]]
35292 // SIMD-ONLY0-NEXT:    br i1 [[CMP3899]], label [[COND_TRUE3901:%.*]], label [[COND_FALSE3902:%.*]]
35293 // SIMD-ONLY0:       cond.true3901:
35294 // SIMD-ONLY0-NEXT:    [[TMP2030:%.*]] = load i64, ptr [[LLE]], align 8
35295 // SIMD-ONLY0-NEXT:    br label [[COND_END3903:%.*]]
35296 // SIMD-ONLY0:       cond.false3902:
35297 // SIMD-ONLY0-NEXT:    [[TMP2031:%.*]] = load i64, ptr [[LLX]], align 8
35298 // SIMD-ONLY0-NEXT:    br label [[COND_END3903]]
35299 // SIMD-ONLY0:       cond.end3903:
35300 // SIMD-ONLY0-NEXT:    [[COND3904:%.*]] = phi i64 [ [[TMP2030]], [[COND_TRUE3901]] ], [ [[TMP2031]], [[COND_FALSE3902]] ]
35301 // SIMD-ONLY0-NEXT:    store i64 [[COND3904]], ptr [[LLX]], align 8
35302 // SIMD-ONLY0-NEXT:    [[TMP2032:%.*]] = load i64, ptr [[LLX]], align 8
35303 // SIMD-ONLY0-NEXT:    [[TMP2033:%.*]] = load i64, ptr [[LLE]], align 8
35304 // SIMD-ONLY0-NEXT:    [[CMP3905:%.*]] = icmp sgt i64 [[TMP2032]], [[TMP2033]]
35305 // SIMD-ONLY0-NEXT:    br i1 [[CMP3905]], label [[IF_THEN3907:%.*]], label [[IF_END3908:%.*]]
35306 // SIMD-ONLY0:       if.then3907:
35307 // SIMD-ONLY0-NEXT:    [[TMP2034:%.*]] = load i64, ptr [[LLE]], align 8
35308 // SIMD-ONLY0-NEXT:    store i64 [[TMP2034]], ptr [[LLX]], align 8
35309 // SIMD-ONLY0-NEXT:    br label [[IF_END3908]]
35310 // SIMD-ONLY0:       if.end3908:
35311 // SIMD-ONLY0-NEXT:    [[TMP2035:%.*]] = load i64, ptr [[LLX]], align 8
35312 // SIMD-ONLY0-NEXT:    [[TMP2036:%.*]] = load i64, ptr [[LLE]], align 8
35313 // SIMD-ONLY0-NEXT:    [[CMP3909:%.*]] = icmp slt i64 [[TMP2035]], [[TMP2036]]
35314 // SIMD-ONLY0-NEXT:    br i1 [[CMP3909]], label [[IF_THEN3911:%.*]], label [[IF_END3912:%.*]]
35315 // SIMD-ONLY0:       if.then3911:
35316 // SIMD-ONLY0-NEXT:    [[TMP2037:%.*]] = load i64, ptr [[LLE]], align 8
35317 // SIMD-ONLY0-NEXT:    store i64 [[TMP2037]], ptr [[LLX]], align 8
35318 // SIMD-ONLY0-NEXT:    br label [[IF_END3912]]
35319 // SIMD-ONLY0:       if.end3912:
35320 // SIMD-ONLY0-NEXT:    [[TMP2038:%.*]] = load i64, ptr [[LLE]], align 8
35321 // SIMD-ONLY0-NEXT:    [[TMP2039:%.*]] = load i64, ptr [[LLX]], align 8
35322 // SIMD-ONLY0-NEXT:    [[CMP3913:%.*]] = icmp sgt i64 [[TMP2038]], [[TMP2039]]
35323 // SIMD-ONLY0-NEXT:    br i1 [[CMP3913]], label [[IF_THEN3915:%.*]], label [[IF_END3916:%.*]]
35324 // SIMD-ONLY0:       if.then3915:
35325 // SIMD-ONLY0-NEXT:    [[TMP2040:%.*]] = load i64, ptr [[LLE]], align 8
35326 // SIMD-ONLY0-NEXT:    store i64 [[TMP2040]], ptr [[LLX]], align 8
35327 // SIMD-ONLY0-NEXT:    br label [[IF_END3916]]
35328 // SIMD-ONLY0:       if.end3916:
35329 // SIMD-ONLY0-NEXT:    [[TMP2041:%.*]] = load i64, ptr [[LLE]], align 8
35330 // SIMD-ONLY0-NEXT:    [[TMP2042:%.*]] = load i64, ptr [[LLX]], align 8
35331 // SIMD-ONLY0-NEXT:    [[CMP3917:%.*]] = icmp slt i64 [[TMP2041]], [[TMP2042]]
35332 // SIMD-ONLY0-NEXT:    br i1 [[CMP3917]], label [[IF_THEN3919:%.*]], label [[IF_END3920:%.*]]
35333 // SIMD-ONLY0:       if.then3919:
35334 // SIMD-ONLY0-NEXT:    [[TMP2043:%.*]] = load i64, ptr [[LLE]], align 8
35335 // SIMD-ONLY0-NEXT:    store i64 [[TMP2043]], ptr [[LLX]], align 8
35336 // SIMD-ONLY0-NEXT:    br label [[IF_END3920]]
35337 // SIMD-ONLY0:       if.end3920:
35338 // SIMD-ONLY0-NEXT:    [[TMP2044:%.*]] = load i64, ptr [[LLX]], align 8
35339 // SIMD-ONLY0-NEXT:    [[TMP2045:%.*]] = load i64, ptr [[LLE]], align 8
35340 // SIMD-ONLY0-NEXT:    [[CMP3921:%.*]] = icmp eq i64 [[TMP2044]], [[TMP2045]]
35341 // SIMD-ONLY0-NEXT:    br i1 [[CMP3921]], label [[COND_TRUE3923:%.*]], label [[COND_FALSE3924:%.*]]
35342 // SIMD-ONLY0:       cond.true3923:
35343 // SIMD-ONLY0-NEXT:    [[TMP2046:%.*]] = load i64, ptr [[LLD]], align 8
35344 // SIMD-ONLY0-NEXT:    br label [[COND_END3925:%.*]]
35345 // SIMD-ONLY0:       cond.false3924:
35346 // SIMD-ONLY0-NEXT:    [[TMP2047:%.*]] = load i64, ptr [[LLX]], align 8
35347 // SIMD-ONLY0-NEXT:    br label [[COND_END3925]]
35348 // SIMD-ONLY0:       cond.end3925:
35349 // SIMD-ONLY0-NEXT:    [[COND3926:%.*]] = phi i64 [ [[TMP2046]], [[COND_TRUE3923]] ], [ [[TMP2047]], [[COND_FALSE3924]] ]
35350 // SIMD-ONLY0-NEXT:    store i64 [[COND3926]], ptr [[LLX]], align 8
35351 // SIMD-ONLY0-NEXT:    [[TMP2048:%.*]] = load i64, ptr [[LLE]], align 8
35352 // SIMD-ONLY0-NEXT:    [[TMP2049:%.*]] = load i64, ptr [[LLX]], align 8
35353 // SIMD-ONLY0-NEXT:    [[CMP3927:%.*]] = icmp eq i64 [[TMP2048]], [[TMP2049]]
35354 // SIMD-ONLY0-NEXT:    br i1 [[CMP3927]], label [[COND_TRUE3929:%.*]], label [[COND_FALSE3930:%.*]]
35355 // SIMD-ONLY0:       cond.true3929:
35356 // SIMD-ONLY0-NEXT:    [[TMP2050:%.*]] = load i64, ptr [[LLD]], align 8
35357 // SIMD-ONLY0-NEXT:    br label [[COND_END3931:%.*]]
35358 // SIMD-ONLY0:       cond.false3930:
35359 // SIMD-ONLY0-NEXT:    [[TMP2051:%.*]] = load i64, ptr [[LLX]], align 8
35360 // SIMD-ONLY0-NEXT:    br label [[COND_END3931]]
35361 // SIMD-ONLY0:       cond.end3931:
35362 // SIMD-ONLY0-NEXT:    [[COND3932:%.*]] = phi i64 [ [[TMP2050]], [[COND_TRUE3929]] ], [ [[TMP2051]], [[COND_FALSE3930]] ]
35363 // SIMD-ONLY0-NEXT:    store i64 [[COND3932]], ptr [[LLX]], align 8
35364 // SIMD-ONLY0-NEXT:    [[TMP2052:%.*]] = load i64, ptr [[LLX]], align 8
35365 // SIMD-ONLY0-NEXT:    [[TMP2053:%.*]] = load i64, ptr [[LLE]], align 8
35366 // SIMD-ONLY0-NEXT:    [[CMP3933:%.*]] = icmp eq i64 [[TMP2052]], [[TMP2053]]
35367 // SIMD-ONLY0-NEXT:    br i1 [[CMP3933]], label [[IF_THEN3935:%.*]], label [[IF_END3936:%.*]]
35368 // SIMD-ONLY0:       if.then3935:
35369 // SIMD-ONLY0-NEXT:    [[TMP2054:%.*]] = load i64, ptr [[LLD]], align 8
35370 // SIMD-ONLY0-NEXT:    store i64 [[TMP2054]], ptr [[LLX]], align 8
35371 // SIMD-ONLY0-NEXT:    br label [[IF_END3936]]
35372 // SIMD-ONLY0:       if.end3936:
35373 // SIMD-ONLY0-NEXT:    [[TMP2055:%.*]] = load i64, ptr [[LLE]], align 8
35374 // SIMD-ONLY0-NEXT:    [[TMP2056:%.*]] = load i64, ptr [[LLX]], align 8
35375 // SIMD-ONLY0-NEXT:    [[CMP3937:%.*]] = icmp eq i64 [[TMP2055]], [[TMP2056]]
35376 // SIMD-ONLY0-NEXT:    br i1 [[CMP3937]], label [[IF_THEN3939:%.*]], label [[IF_END3940:%.*]]
35377 // SIMD-ONLY0:       if.then3939:
35378 // SIMD-ONLY0-NEXT:    [[TMP2057:%.*]] = load i64, ptr [[LLD]], align 8
35379 // SIMD-ONLY0-NEXT:    store i64 [[TMP2057]], ptr [[LLX]], align 8
35380 // SIMD-ONLY0-NEXT:    br label [[IF_END3940]]
35381 // SIMD-ONLY0:       if.end3940:
35382 // SIMD-ONLY0-NEXT:    [[TMP2058:%.*]] = load i64, ptr [[ULLX]], align 8
35383 // SIMD-ONLY0-NEXT:    [[TMP2059:%.*]] = load i64, ptr [[ULLE]], align 8
35384 // SIMD-ONLY0-NEXT:    [[CMP3941:%.*]] = icmp ugt i64 [[TMP2058]], [[TMP2059]]
35385 // SIMD-ONLY0-NEXT:    br i1 [[CMP3941]], label [[COND_TRUE3943:%.*]], label [[COND_FALSE3944:%.*]]
35386 // SIMD-ONLY0:       cond.true3943:
35387 // SIMD-ONLY0-NEXT:    [[TMP2060:%.*]] = load i64, ptr [[ULLE]], align 8
35388 // SIMD-ONLY0-NEXT:    br label [[COND_END3945:%.*]]
35389 // SIMD-ONLY0:       cond.false3944:
35390 // SIMD-ONLY0-NEXT:    [[TMP2061:%.*]] = load i64, ptr [[ULLX]], align 8
35391 // SIMD-ONLY0-NEXT:    br label [[COND_END3945]]
35392 // SIMD-ONLY0:       cond.end3945:
35393 // SIMD-ONLY0-NEXT:    [[COND3946:%.*]] = phi i64 [ [[TMP2060]], [[COND_TRUE3943]] ], [ [[TMP2061]], [[COND_FALSE3944]] ]
35394 // SIMD-ONLY0-NEXT:    store i64 [[COND3946]], ptr [[ULLX]], align 8
35395 // SIMD-ONLY0-NEXT:    [[TMP2062:%.*]] = load i64, ptr [[ULLX]], align 8
35396 // SIMD-ONLY0-NEXT:    [[TMP2063:%.*]] = load i64, ptr [[ULLE]], align 8
35397 // SIMD-ONLY0-NEXT:    [[CMP3947:%.*]] = icmp ult i64 [[TMP2062]], [[TMP2063]]
35398 // SIMD-ONLY0-NEXT:    br i1 [[CMP3947]], label [[COND_TRUE3949:%.*]], label [[COND_FALSE3950:%.*]]
35399 // SIMD-ONLY0:       cond.true3949:
35400 // SIMD-ONLY0-NEXT:    [[TMP2064:%.*]] = load i64, ptr [[ULLE]], align 8
35401 // SIMD-ONLY0-NEXT:    br label [[COND_END3951:%.*]]
35402 // SIMD-ONLY0:       cond.false3950:
35403 // SIMD-ONLY0-NEXT:    [[TMP2065:%.*]] = load i64, ptr [[ULLX]], align 8
35404 // SIMD-ONLY0-NEXT:    br label [[COND_END3951]]
35405 // SIMD-ONLY0:       cond.end3951:
35406 // SIMD-ONLY0-NEXT:    [[COND3952:%.*]] = phi i64 [ [[TMP2064]], [[COND_TRUE3949]] ], [ [[TMP2065]], [[COND_FALSE3950]] ]
35407 // SIMD-ONLY0-NEXT:    store i64 [[COND3952]], ptr [[ULLX]], align 8
35408 // SIMD-ONLY0-NEXT:    [[TMP2066:%.*]] = load i64, ptr [[ULLE]], align 8
35409 // SIMD-ONLY0-NEXT:    [[TMP2067:%.*]] = load i64, ptr [[ULLX]], align 8
35410 // SIMD-ONLY0-NEXT:    [[CMP3953:%.*]] = icmp ugt i64 [[TMP2066]], [[TMP2067]]
35411 // SIMD-ONLY0-NEXT:    br i1 [[CMP3953]], label [[COND_TRUE3955:%.*]], label [[COND_FALSE3956:%.*]]
35412 // SIMD-ONLY0:       cond.true3955:
35413 // SIMD-ONLY0-NEXT:    [[TMP2068:%.*]] = load i64, ptr [[ULLE]], align 8
35414 // SIMD-ONLY0-NEXT:    br label [[COND_END3957:%.*]]
35415 // SIMD-ONLY0:       cond.false3956:
35416 // SIMD-ONLY0-NEXT:    [[TMP2069:%.*]] = load i64, ptr [[ULLX]], align 8
35417 // SIMD-ONLY0-NEXT:    br label [[COND_END3957]]
35418 // SIMD-ONLY0:       cond.end3957:
35419 // SIMD-ONLY0-NEXT:    [[COND3958:%.*]] = phi i64 [ [[TMP2068]], [[COND_TRUE3955]] ], [ [[TMP2069]], [[COND_FALSE3956]] ]
35420 // SIMD-ONLY0-NEXT:    store i64 [[COND3958]], ptr [[ULLX]], align 8
35421 // SIMD-ONLY0-NEXT:    [[TMP2070:%.*]] = load i64, ptr [[ULLE]], align 8
35422 // SIMD-ONLY0-NEXT:    [[TMP2071:%.*]] = load i64, ptr [[ULLX]], align 8
35423 // SIMD-ONLY0-NEXT:    [[CMP3959:%.*]] = icmp ult i64 [[TMP2070]], [[TMP2071]]
35424 // SIMD-ONLY0-NEXT:    br i1 [[CMP3959]], label [[COND_TRUE3961:%.*]], label [[COND_FALSE3962:%.*]]
35425 // SIMD-ONLY0:       cond.true3961:
35426 // SIMD-ONLY0-NEXT:    [[TMP2072:%.*]] = load i64, ptr [[ULLE]], align 8
35427 // SIMD-ONLY0-NEXT:    br label [[COND_END3963:%.*]]
35428 // SIMD-ONLY0:       cond.false3962:
35429 // SIMD-ONLY0-NEXT:    [[TMP2073:%.*]] = load i64, ptr [[ULLX]], align 8
35430 // SIMD-ONLY0-NEXT:    br label [[COND_END3963]]
35431 // SIMD-ONLY0:       cond.end3963:
35432 // SIMD-ONLY0-NEXT:    [[COND3964:%.*]] = phi i64 [ [[TMP2072]], [[COND_TRUE3961]] ], [ [[TMP2073]], [[COND_FALSE3962]] ]
35433 // SIMD-ONLY0-NEXT:    store i64 [[COND3964]], ptr [[ULLX]], align 8
35434 // SIMD-ONLY0-NEXT:    [[TMP2074:%.*]] = load i64, ptr [[ULLX]], align 8
35435 // SIMD-ONLY0-NEXT:    [[TMP2075:%.*]] = load i64, ptr [[ULLE]], align 8
35436 // SIMD-ONLY0-NEXT:    [[CMP3965:%.*]] = icmp ugt i64 [[TMP2074]], [[TMP2075]]
35437 // SIMD-ONLY0-NEXT:    br i1 [[CMP3965]], label [[IF_THEN3967:%.*]], label [[IF_END3968:%.*]]
35438 // SIMD-ONLY0:       if.then3967:
35439 // SIMD-ONLY0-NEXT:    [[TMP2076:%.*]] = load i64, ptr [[ULLE]], align 8
35440 // SIMD-ONLY0-NEXT:    store i64 [[TMP2076]], ptr [[ULLX]], align 8
35441 // SIMD-ONLY0-NEXT:    br label [[IF_END3968]]
35442 // SIMD-ONLY0:       if.end3968:
35443 // SIMD-ONLY0-NEXT:    [[TMP2077:%.*]] = load i64, ptr [[ULLX]], align 8
35444 // SIMD-ONLY0-NEXT:    [[TMP2078:%.*]] = load i64, ptr [[ULLE]], align 8
35445 // SIMD-ONLY0-NEXT:    [[CMP3969:%.*]] = icmp ult i64 [[TMP2077]], [[TMP2078]]
35446 // SIMD-ONLY0-NEXT:    br i1 [[CMP3969]], label [[IF_THEN3971:%.*]], label [[IF_END3972:%.*]]
35447 // SIMD-ONLY0:       if.then3971:
35448 // SIMD-ONLY0-NEXT:    [[TMP2079:%.*]] = load i64, ptr [[ULLE]], align 8
35449 // SIMD-ONLY0-NEXT:    store i64 [[TMP2079]], ptr [[ULLX]], align 8
35450 // SIMD-ONLY0-NEXT:    br label [[IF_END3972]]
35451 // SIMD-ONLY0:       if.end3972:
35452 // SIMD-ONLY0-NEXT:    [[TMP2080:%.*]] = load i64, ptr [[ULLE]], align 8
35453 // SIMD-ONLY0-NEXT:    [[TMP2081:%.*]] = load i64, ptr [[ULLX]], align 8
35454 // SIMD-ONLY0-NEXT:    [[CMP3973:%.*]] = icmp ugt i64 [[TMP2080]], [[TMP2081]]
35455 // SIMD-ONLY0-NEXT:    br i1 [[CMP3973]], label [[IF_THEN3975:%.*]], label [[IF_END3976:%.*]]
35456 // SIMD-ONLY0:       if.then3975:
35457 // SIMD-ONLY0-NEXT:    [[TMP2082:%.*]] = load i64, ptr [[ULLE]], align 8
35458 // SIMD-ONLY0-NEXT:    store i64 [[TMP2082]], ptr [[ULLX]], align 8
35459 // SIMD-ONLY0-NEXT:    br label [[IF_END3976]]
35460 // SIMD-ONLY0:       if.end3976:
35461 // SIMD-ONLY0-NEXT:    [[TMP2083:%.*]] = load i64, ptr [[ULLE]], align 8
35462 // SIMD-ONLY0-NEXT:    [[TMP2084:%.*]] = load i64, ptr [[ULLX]], align 8
35463 // SIMD-ONLY0-NEXT:    [[CMP3977:%.*]] = icmp ult i64 [[TMP2083]], [[TMP2084]]
35464 // SIMD-ONLY0-NEXT:    br i1 [[CMP3977]], label [[IF_THEN3979:%.*]], label [[IF_END3980:%.*]]
35465 // SIMD-ONLY0:       if.then3979:
35466 // SIMD-ONLY0-NEXT:    [[TMP2085:%.*]] = load i64, ptr [[ULLE]], align 8
35467 // SIMD-ONLY0-NEXT:    store i64 [[TMP2085]], ptr [[ULLX]], align 8
35468 // SIMD-ONLY0-NEXT:    br label [[IF_END3980]]
35469 // SIMD-ONLY0:       if.end3980:
35470 // SIMD-ONLY0-NEXT:    [[TMP2086:%.*]] = load i64, ptr [[ULLX]], align 8
35471 // SIMD-ONLY0-NEXT:    [[TMP2087:%.*]] = load i64, ptr [[ULLE]], align 8
35472 // SIMD-ONLY0-NEXT:    [[CMP3981:%.*]] = icmp eq i64 [[TMP2086]], [[TMP2087]]
35473 // SIMD-ONLY0-NEXT:    br i1 [[CMP3981]], label [[COND_TRUE3983:%.*]], label [[COND_FALSE3984:%.*]]
35474 // SIMD-ONLY0:       cond.true3983:
35475 // SIMD-ONLY0-NEXT:    [[TMP2088:%.*]] = load i64, ptr [[ULLD]], align 8
35476 // SIMD-ONLY0-NEXT:    br label [[COND_END3985:%.*]]
35477 // SIMD-ONLY0:       cond.false3984:
35478 // SIMD-ONLY0-NEXT:    [[TMP2089:%.*]] = load i64, ptr [[ULLX]], align 8
35479 // SIMD-ONLY0-NEXT:    br label [[COND_END3985]]
35480 // SIMD-ONLY0:       cond.end3985:
35481 // SIMD-ONLY0-NEXT:    [[COND3986:%.*]] = phi i64 [ [[TMP2088]], [[COND_TRUE3983]] ], [ [[TMP2089]], [[COND_FALSE3984]] ]
35482 // SIMD-ONLY0-NEXT:    store i64 [[COND3986]], ptr [[ULLX]], align 8
35483 // SIMD-ONLY0-NEXT:    [[TMP2090:%.*]] = load i64, ptr [[ULLE]], align 8
35484 // SIMD-ONLY0-NEXT:    [[TMP2091:%.*]] = load i64, ptr [[ULLX]], align 8
35485 // SIMD-ONLY0-NEXT:    [[CMP3987:%.*]] = icmp eq i64 [[TMP2090]], [[TMP2091]]
35486 // SIMD-ONLY0-NEXT:    br i1 [[CMP3987]], label [[COND_TRUE3989:%.*]], label [[COND_FALSE3990:%.*]]
35487 // SIMD-ONLY0:       cond.true3989:
35488 // SIMD-ONLY0-NEXT:    [[TMP2092:%.*]] = load i64, ptr [[ULLD]], align 8
35489 // SIMD-ONLY0-NEXT:    br label [[COND_END3991:%.*]]
35490 // SIMD-ONLY0:       cond.false3990:
35491 // SIMD-ONLY0-NEXT:    [[TMP2093:%.*]] = load i64, ptr [[ULLX]], align 8
35492 // SIMD-ONLY0-NEXT:    br label [[COND_END3991]]
35493 // SIMD-ONLY0:       cond.end3991:
35494 // SIMD-ONLY0-NEXT:    [[COND3992:%.*]] = phi i64 [ [[TMP2092]], [[COND_TRUE3989]] ], [ [[TMP2093]], [[COND_FALSE3990]] ]
35495 // SIMD-ONLY0-NEXT:    store i64 [[COND3992]], ptr [[ULLX]], align 8
35496 // SIMD-ONLY0-NEXT:    [[TMP2094:%.*]] = load i64, ptr [[ULLX]], align 8
35497 // SIMD-ONLY0-NEXT:    [[TMP2095:%.*]] = load i64, ptr [[ULLE]], align 8
35498 // SIMD-ONLY0-NEXT:    [[CMP3993:%.*]] = icmp eq i64 [[TMP2094]], [[TMP2095]]
35499 // SIMD-ONLY0-NEXT:    br i1 [[CMP3993]], label [[IF_THEN3995:%.*]], label [[IF_END3996:%.*]]
35500 // SIMD-ONLY0:       if.then3995:
35501 // SIMD-ONLY0-NEXT:    [[TMP2096:%.*]] = load i64, ptr [[ULLD]], align 8
35502 // SIMD-ONLY0-NEXT:    store i64 [[TMP2096]], ptr [[ULLX]], align 8
35503 // SIMD-ONLY0-NEXT:    br label [[IF_END3996]]
35504 // SIMD-ONLY0:       if.end3996:
35505 // SIMD-ONLY0-NEXT:    [[TMP2097:%.*]] = load i64, ptr [[ULLE]], align 8
35506 // SIMD-ONLY0-NEXT:    [[TMP2098:%.*]] = load i64, ptr [[ULLX]], align 8
35507 // SIMD-ONLY0-NEXT:    [[CMP3997:%.*]] = icmp eq i64 [[TMP2097]], [[TMP2098]]
35508 // SIMD-ONLY0-NEXT:    br i1 [[CMP3997]], label [[IF_THEN3999:%.*]], label [[IF_END4000:%.*]]
35509 // SIMD-ONLY0:       if.then3999:
35510 // SIMD-ONLY0-NEXT:    [[TMP2099:%.*]] = load i64, ptr [[ULLD]], align 8
35511 // SIMD-ONLY0-NEXT:    store i64 [[TMP2099]], ptr [[ULLX]], align 8
35512 // SIMD-ONLY0-NEXT:    br label [[IF_END4000]]
35513 // SIMD-ONLY0:       if.end4000:
35514 // SIMD-ONLY0-NEXT:    [[TMP2100:%.*]] = load i64, ptr [[LLX]], align 8
35515 // SIMD-ONLY0-NEXT:    [[TMP2101:%.*]] = load i64, ptr [[LLE]], align 8
35516 // SIMD-ONLY0-NEXT:    [[CMP4001:%.*]] = icmp sgt i64 [[TMP2100]], [[TMP2101]]
35517 // SIMD-ONLY0-NEXT:    br i1 [[CMP4001]], label [[COND_TRUE4003:%.*]], label [[COND_FALSE4004:%.*]]
35518 // SIMD-ONLY0:       cond.true4003:
35519 // SIMD-ONLY0-NEXT:    [[TMP2102:%.*]] = load i64, ptr [[LLE]], align 8
35520 // SIMD-ONLY0-NEXT:    br label [[COND_END4005:%.*]]
35521 // SIMD-ONLY0:       cond.false4004:
35522 // SIMD-ONLY0-NEXT:    [[TMP2103:%.*]] = load i64, ptr [[LLX]], align 8
35523 // SIMD-ONLY0-NEXT:    br label [[COND_END4005]]
35524 // SIMD-ONLY0:       cond.end4005:
35525 // SIMD-ONLY0-NEXT:    [[COND4006:%.*]] = phi i64 [ [[TMP2102]], [[COND_TRUE4003]] ], [ [[TMP2103]], [[COND_FALSE4004]] ]
35526 // SIMD-ONLY0-NEXT:    store i64 [[COND4006]], ptr [[LLX]], align 8
35527 // SIMD-ONLY0-NEXT:    [[TMP2104:%.*]] = load i64, ptr [[LLX]], align 8
35528 // SIMD-ONLY0-NEXT:    [[TMP2105:%.*]] = load i64, ptr [[LLE]], align 8
35529 // SIMD-ONLY0-NEXT:    [[CMP4007:%.*]] = icmp slt i64 [[TMP2104]], [[TMP2105]]
35530 // SIMD-ONLY0-NEXT:    br i1 [[CMP4007]], label [[COND_TRUE4009:%.*]], label [[COND_FALSE4010:%.*]]
35531 // SIMD-ONLY0:       cond.true4009:
35532 // SIMD-ONLY0-NEXT:    [[TMP2106:%.*]] = load i64, ptr [[LLE]], align 8
35533 // SIMD-ONLY0-NEXT:    br label [[COND_END4011:%.*]]
35534 // SIMD-ONLY0:       cond.false4010:
35535 // SIMD-ONLY0-NEXT:    [[TMP2107:%.*]] = load i64, ptr [[LLX]], align 8
35536 // SIMD-ONLY0-NEXT:    br label [[COND_END4011]]
35537 // SIMD-ONLY0:       cond.end4011:
35538 // SIMD-ONLY0-NEXT:    [[COND4012:%.*]] = phi i64 [ [[TMP2106]], [[COND_TRUE4009]] ], [ [[TMP2107]], [[COND_FALSE4010]] ]
35539 // SIMD-ONLY0-NEXT:    store i64 [[COND4012]], ptr [[LLX]], align 8
35540 // SIMD-ONLY0-NEXT:    [[TMP2108:%.*]] = load i64, ptr [[LLE]], align 8
35541 // SIMD-ONLY0-NEXT:    [[TMP2109:%.*]] = load i64, ptr [[LLX]], align 8
35542 // SIMD-ONLY0-NEXT:    [[CMP4013:%.*]] = icmp sgt i64 [[TMP2108]], [[TMP2109]]
35543 // SIMD-ONLY0-NEXT:    br i1 [[CMP4013]], label [[COND_TRUE4015:%.*]], label [[COND_FALSE4016:%.*]]
35544 // SIMD-ONLY0:       cond.true4015:
35545 // SIMD-ONLY0-NEXT:    [[TMP2110:%.*]] = load i64, ptr [[LLE]], align 8
35546 // SIMD-ONLY0-NEXT:    br label [[COND_END4017:%.*]]
35547 // SIMD-ONLY0:       cond.false4016:
35548 // SIMD-ONLY0-NEXT:    [[TMP2111:%.*]] = load i64, ptr [[LLX]], align 8
35549 // SIMD-ONLY0-NEXT:    br label [[COND_END4017]]
35550 // SIMD-ONLY0:       cond.end4017:
35551 // SIMD-ONLY0-NEXT:    [[COND4018:%.*]] = phi i64 [ [[TMP2110]], [[COND_TRUE4015]] ], [ [[TMP2111]], [[COND_FALSE4016]] ]
35552 // SIMD-ONLY0-NEXT:    store i64 [[COND4018]], ptr [[LLX]], align 8
35553 // SIMD-ONLY0-NEXT:    [[TMP2112:%.*]] = load i64, ptr [[LLE]], align 8
35554 // SIMD-ONLY0-NEXT:    [[TMP2113:%.*]] = load i64, ptr [[LLX]], align 8
35555 // SIMD-ONLY0-NEXT:    [[CMP4019:%.*]] = icmp slt i64 [[TMP2112]], [[TMP2113]]
35556 // SIMD-ONLY0-NEXT:    br i1 [[CMP4019]], label [[COND_TRUE4021:%.*]], label [[COND_FALSE4022:%.*]]
35557 // SIMD-ONLY0:       cond.true4021:
35558 // SIMD-ONLY0-NEXT:    [[TMP2114:%.*]] = load i64, ptr [[LLE]], align 8
35559 // SIMD-ONLY0-NEXT:    br label [[COND_END4023:%.*]]
35560 // SIMD-ONLY0:       cond.false4022:
35561 // SIMD-ONLY0-NEXT:    [[TMP2115:%.*]] = load i64, ptr [[LLX]], align 8
35562 // SIMD-ONLY0-NEXT:    br label [[COND_END4023]]
35563 // SIMD-ONLY0:       cond.end4023:
35564 // SIMD-ONLY0-NEXT:    [[COND4024:%.*]] = phi i64 [ [[TMP2114]], [[COND_TRUE4021]] ], [ [[TMP2115]], [[COND_FALSE4022]] ]
35565 // SIMD-ONLY0-NEXT:    store i64 [[COND4024]], ptr [[LLX]], align 8
35566 // SIMD-ONLY0-NEXT:    [[TMP2116:%.*]] = load i64, ptr [[LLX]], align 8
35567 // SIMD-ONLY0-NEXT:    [[TMP2117:%.*]] = load i64, ptr [[LLE]], align 8
35568 // SIMD-ONLY0-NEXT:    [[CMP4025:%.*]] = icmp sgt i64 [[TMP2116]], [[TMP2117]]
35569 // SIMD-ONLY0-NEXT:    br i1 [[CMP4025]], label [[IF_THEN4027:%.*]], label [[IF_END4028:%.*]]
35570 // SIMD-ONLY0:       if.then4027:
35571 // SIMD-ONLY0-NEXT:    [[TMP2118:%.*]] = load i64, ptr [[LLE]], align 8
35572 // SIMD-ONLY0-NEXT:    store i64 [[TMP2118]], ptr [[LLX]], align 8
35573 // SIMD-ONLY0-NEXT:    br label [[IF_END4028]]
35574 // SIMD-ONLY0:       if.end4028:
35575 // SIMD-ONLY0-NEXT:    [[TMP2119:%.*]] = load i64, ptr [[LLX]], align 8
35576 // SIMD-ONLY0-NEXT:    [[TMP2120:%.*]] = load i64, ptr [[LLE]], align 8
35577 // SIMD-ONLY0-NEXT:    [[CMP4029:%.*]] = icmp slt i64 [[TMP2119]], [[TMP2120]]
35578 // SIMD-ONLY0-NEXT:    br i1 [[CMP4029]], label [[IF_THEN4031:%.*]], label [[IF_END4032:%.*]]
35579 // SIMD-ONLY0:       if.then4031:
35580 // SIMD-ONLY0-NEXT:    [[TMP2121:%.*]] = load i64, ptr [[LLE]], align 8
35581 // SIMD-ONLY0-NEXT:    store i64 [[TMP2121]], ptr [[LLX]], align 8
35582 // SIMD-ONLY0-NEXT:    br label [[IF_END4032]]
35583 // SIMD-ONLY0:       if.end4032:
35584 // SIMD-ONLY0-NEXT:    [[TMP2122:%.*]] = load i64, ptr [[LLE]], align 8
35585 // SIMD-ONLY0-NEXT:    [[TMP2123:%.*]] = load i64, ptr [[LLX]], align 8
35586 // SIMD-ONLY0-NEXT:    [[CMP4033:%.*]] = icmp sgt i64 [[TMP2122]], [[TMP2123]]
35587 // SIMD-ONLY0-NEXT:    br i1 [[CMP4033]], label [[IF_THEN4035:%.*]], label [[IF_END4036:%.*]]
35588 // SIMD-ONLY0:       if.then4035:
35589 // SIMD-ONLY0-NEXT:    [[TMP2124:%.*]] = load i64, ptr [[LLE]], align 8
35590 // SIMD-ONLY0-NEXT:    store i64 [[TMP2124]], ptr [[LLX]], align 8
35591 // SIMD-ONLY0-NEXT:    br label [[IF_END4036]]
35592 // SIMD-ONLY0:       if.end4036:
35593 // SIMD-ONLY0-NEXT:    [[TMP2125:%.*]] = load i64, ptr [[LLE]], align 8
35594 // SIMD-ONLY0-NEXT:    [[TMP2126:%.*]] = load i64, ptr [[LLX]], align 8
35595 // SIMD-ONLY0-NEXT:    [[CMP4037:%.*]] = icmp slt i64 [[TMP2125]], [[TMP2126]]
35596 // SIMD-ONLY0-NEXT:    br i1 [[CMP4037]], label [[IF_THEN4039:%.*]], label [[IF_END4040:%.*]]
35597 // SIMD-ONLY0:       if.then4039:
35598 // SIMD-ONLY0-NEXT:    [[TMP2127:%.*]] = load i64, ptr [[LLE]], align 8
35599 // SIMD-ONLY0-NEXT:    store i64 [[TMP2127]], ptr [[LLX]], align 8
35600 // SIMD-ONLY0-NEXT:    br label [[IF_END4040]]
35601 // SIMD-ONLY0:       if.end4040:
35602 // SIMD-ONLY0-NEXT:    [[TMP2128:%.*]] = load i64, ptr [[LLX]], align 8
35603 // SIMD-ONLY0-NEXT:    [[TMP2129:%.*]] = load i64, ptr [[LLE]], align 8
35604 // SIMD-ONLY0-NEXT:    [[CMP4041:%.*]] = icmp eq i64 [[TMP2128]], [[TMP2129]]
35605 // SIMD-ONLY0-NEXT:    br i1 [[CMP4041]], label [[COND_TRUE4043:%.*]], label [[COND_FALSE4044:%.*]]
35606 // SIMD-ONLY0:       cond.true4043:
35607 // SIMD-ONLY0-NEXT:    [[TMP2130:%.*]] = load i64, ptr [[LLD]], align 8
35608 // SIMD-ONLY0-NEXT:    br label [[COND_END4045:%.*]]
35609 // SIMD-ONLY0:       cond.false4044:
35610 // SIMD-ONLY0-NEXT:    [[TMP2131:%.*]] = load i64, ptr [[LLX]], align 8
35611 // SIMD-ONLY0-NEXT:    br label [[COND_END4045]]
35612 // SIMD-ONLY0:       cond.end4045:
35613 // SIMD-ONLY0-NEXT:    [[COND4046:%.*]] = phi i64 [ [[TMP2130]], [[COND_TRUE4043]] ], [ [[TMP2131]], [[COND_FALSE4044]] ]
35614 // SIMD-ONLY0-NEXT:    store i64 [[COND4046]], ptr [[LLX]], align 8
35615 // SIMD-ONLY0-NEXT:    [[TMP2132:%.*]] = load i64, ptr [[LLE]], align 8
35616 // SIMD-ONLY0-NEXT:    [[TMP2133:%.*]] = load i64, ptr [[LLX]], align 8
35617 // SIMD-ONLY0-NEXT:    [[CMP4047:%.*]] = icmp eq i64 [[TMP2132]], [[TMP2133]]
35618 // SIMD-ONLY0-NEXT:    br i1 [[CMP4047]], label [[COND_TRUE4049:%.*]], label [[COND_FALSE4050:%.*]]
35619 // SIMD-ONLY0:       cond.true4049:
35620 // SIMD-ONLY0-NEXT:    [[TMP2134:%.*]] = load i64, ptr [[LLD]], align 8
35621 // SIMD-ONLY0-NEXT:    br label [[COND_END4051:%.*]]
35622 // SIMD-ONLY0:       cond.false4050:
35623 // SIMD-ONLY0-NEXT:    [[TMP2135:%.*]] = load i64, ptr [[LLX]], align 8
35624 // SIMD-ONLY0-NEXT:    br label [[COND_END4051]]
35625 // SIMD-ONLY0:       cond.end4051:
35626 // SIMD-ONLY0-NEXT:    [[COND4052:%.*]] = phi i64 [ [[TMP2134]], [[COND_TRUE4049]] ], [ [[TMP2135]], [[COND_FALSE4050]] ]
35627 // SIMD-ONLY0-NEXT:    store i64 [[COND4052]], ptr [[LLX]], align 8
35628 // SIMD-ONLY0-NEXT:    [[TMP2136:%.*]] = load i64, ptr [[LLX]], align 8
35629 // SIMD-ONLY0-NEXT:    [[TMP2137:%.*]] = load i64, ptr [[LLE]], align 8
35630 // SIMD-ONLY0-NEXT:    [[CMP4053:%.*]] = icmp eq i64 [[TMP2136]], [[TMP2137]]
35631 // SIMD-ONLY0-NEXT:    br i1 [[CMP4053]], label [[IF_THEN4055:%.*]], label [[IF_END4056:%.*]]
35632 // SIMD-ONLY0:       if.then4055:
35633 // SIMD-ONLY0-NEXT:    [[TMP2138:%.*]] = load i64, ptr [[LLD]], align 8
35634 // SIMD-ONLY0-NEXT:    store i64 [[TMP2138]], ptr [[LLX]], align 8
35635 // SIMD-ONLY0-NEXT:    br label [[IF_END4056]]
35636 // SIMD-ONLY0:       if.end4056:
35637 // SIMD-ONLY0-NEXT:    [[TMP2139:%.*]] = load i64, ptr [[LLE]], align 8
35638 // SIMD-ONLY0-NEXT:    [[TMP2140:%.*]] = load i64, ptr [[LLX]], align 8
35639 // SIMD-ONLY0-NEXT:    [[CMP4057:%.*]] = icmp eq i64 [[TMP2139]], [[TMP2140]]
35640 // SIMD-ONLY0-NEXT:    br i1 [[CMP4057]], label [[IF_THEN4059:%.*]], label [[IF_END4060:%.*]]
35641 // SIMD-ONLY0:       if.then4059:
35642 // SIMD-ONLY0-NEXT:    [[TMP2141:%.*]] = load i64, ptr [[LLD]], align 8
35643 // SIMD-ONLY0-NEXT:    store i64 [[TMP2141]], ptr [[LLX]], align 8
35644 // SIMD-ONLY0-NEXT:    br label [[IF_END4060]]
35645 // SIMD-ONLY0:       if.end4060:
35646 // SIMD-ONLY0-NEXT:    [[TMP2142:%.*]] = load i64, ptr [[ULLX]], align 8
35647 // SIMD-ONLY0-NEXT:    [[TMP2143:%.*]] = load i64, ptr [[ULLE]], align 8
35648 // SIMD-ONLY0-NEXT:    [[CMP4061:%.*]] = icmp ugt i64 [[TMP2142]], [[TMP2143]]
35649 // SIMD-ONLY0-NEXT:    br i1 [[CMP4061]], label [[COND_TRUE4063:%.*]], label [[COND_FALSE4064:%.*]]
35650 // SIMD-ONLY0:       cond.true4063:
35651 // SIMD-ONLY0-NEXT:    [[TMP2144:%.*]] = load i64, ptr [[ULLE]], align 8
35652 // SIMD-ONLY0-NEXT:    br label [[COND_END4065:%.*]]
35653 // SIMD-ONLY0:       cond.false4064:
35654 // SIMD-ONLY0-NEXT:    [[TMP2145:%.*]] = load i64, ptr [[ULLX]], align 8
35655 // SIMD-ONLY0-NEXT:    br label [[COND_END4065]]
35656 // SIMD-ONLY0:       cond.end4065:
35657 // SIMD-ONLY0-NEXT:    [[COND4066:%.*]] = phi i64 [ [[TMP2144]], [[COND_TRUE4063]] ], [ [[TMP2145]], [[COND_FALSE4064]] ]
35658 // SIMD-ONLY0-NEXT:    store i64 [[COND4066]], ptr [[ULLX]], align 8
35659 // SIMD-ONLY0-NEXT:    [[TMP2146:%.*]] = load i64, ptr [[ULLX]], align 8
35660 // SIMD-ONLY0-NEXT:    [[TMP2147:%.*]] = load i64, ptr [[ULLE]], align 8
35661 // SIMD-ONLY0-NEXT:    [[CMP4067:%.*]] = icmp ult i64 [[TMP2146]], [[TMP2147]]
35662 // SIMD-ONLY0-NEXT:    br i1 [[CMP4067]], label [[COND_TRUE4069:%.*]], label [[COND_FALSE4070:%.*]]
35663 // SIMD-ONLY0:       cond.true4069:
35664 // SIMD-ONLY0-NEXT:    [[TMP2148:%.*]] = load i64, ptr [[ULLE]], align 8
35665 // SIMD-ONLY0-NEXT:    br label [[COND_END4071:%.*]]
35666 // SIMD-ONLY0:       cond.false4070:
35667 // SIMD-ONLY0-NEXT:    [[TMP2149:%.*]] = load i64, ptr [[ULLX]], align 8
35668 // SIMD-ONLY0-NEXT:    br label [[COND_END4071]]
35669 // SIMD-ONLY0:       cond.end4071:
35670 // SIMD-ONLY0-NEXT:    [[COND4072:%.*]] = phi i64 [ [[TMP2148]], [[COND_TRUE4069]] ], [ [[TMP2149]], [[COND_FALSE4070]] ]
35671 // SIMD-ONLY0-NEXT:    store i64 [[COND4072]], ptr [[ULLX]], align 8
35672 // SIMD-ONLY0-NEXT:    [[TMP2150:%.*]] = load i64, ptr [[ULLE]], align 8
35673 // SIMD-ONLY0-NEXT:    [[TMP2151:%.*]] = load i64, ptr [[ULLX]], align 8
35674 // SIMD-ONLY0-NEXT:    [[CMP4073:%.*]] = icmp ugt i64 [[TMP2150]], [[TMP2151]]
35675 // SIMD-ONLY0-NEXT:    br i1 [[CMP4073]], label [[COND_TRUE4075:%.*]], label [[COND_FALSE4076:%.*]]
35676 // SIMD-ONLY0:       cond.true4075:
35677 // SIMD-ONLY0-NEXT:    [[TMP2152:%.*]] = load i64, ptr [[ULLE]], align 8
35678 // SIMD-ONLY0-NEXT:    br label [[COND_END4077:%.*]]
35679 // SIMD-ONLY0:       cond.false4076:
35680 // SIMD-ONLY0-NEXT:    [[TMP2153:%.*]] = load i64, ptr [[ULLX]], align 8
35681 // SIMD-ONLY0-NEXT:    br label [[COND_END4077]]
35682 // SIMD-ONLY0:       cond.end4077:
35683 // SIMD-ONLY0-NEXT:    [[COND4078:%.*]] = phi i64 [ [[TMP2152]], [[COND_TRUE4075]] ], [ [[TMP2153]], [[COND_FALSE4076]] ]
35684 // SIMD-ONLY0-NEXT:    store i64 [[COND4078]], ptr [[ULLX]], align 8
35685 // SIMD-ONLY0-NEXT:    [[TMP2154:%.*]] = load i64, ptr [[ULLE]], align 8
35686 // SIMD-ONLY0-NEXT:    [[TMP2155:%.*]] = load i64, ptr [[ULLX]], align 8
35687 // SIMD-ONLY0-NEXT:    [[CMP4079:%.*]] = icmp ult i64 [[TMP2154]], [[TMP2155]]
35688 // SIMD-ONLY0-NEXT:    br i1 [[CMP4079]], label [[COND_TRUE4081:%.*]], label [[COND_FALSE4082:%.*]]
35689 // SIMD-ONLY0:       cond.true4081:
35690 // SIMD-ONLY0-NEXT:    [[TMP2156:%.*]] = load i64, ptr [[ULLE]], align 8
35691 // SIMD-ONLY0-NEXT:    br label [[COND_END4083:%.*]]
35692 // SIMD-ONLY0:       cond.false4082:
35693 // SIMD-ONLY0-NEXT:    [[TMP2157:%.*]] = load i64, ptr [[ULLX]], align 8
35694 // SIMD-ONLY0-NEXT:    br label [[COND_END4083]]
35695 // SIMD-ONLY0:       cond.end4083:
35696 // SIMD-ONLY0-NEXT:    [[COND4084:%.*]] = phi i64 [ [[TMP2156]], [[COND_TRUE4081]] ], [ [[TMP2157]], [[COND_FALSE4082]] ]
35697 // SIMD-ONLY0-NEXT:    store i64 [[COND4084]], ptr [[ULLX]], align 8
35698 // SIMD-ONLY0-NEXT:    [[TMP2158:%.*]] = load i64, ptr [[ULLX]], align 8
35699 // SIMD-ONLY0-NEXT:    [[TMP2159:%.*]] = load i64, ptr [[ULLE]], align 8
35700 // SIMD-ONLY0-NEXT:    [[CMP4085:%.*]] = icmp ugt i64 [[TMP2158]], [[TMP2159]]
35701 // SIMD-ONLY0-NEXT:    br i1 [[CMP4085]], label [[IF_THEN4087:%.*]], label [[IF_END4088:%.*]]
35702 // SIMD-ONLY0:       if.then4087:
35703 // SIMD-ONLY0-NEXT:    [[TMP2160:%.*]] = load i64, ptr [[ULLE]], align 8
35704 // SIMD-ONLY0-NEXT:    store i64 [[TMP2160]], ptr [[ULLX]], align 8
35705 // SIMD-ONLY0-NEXT:    br label [[IF_END4088]]
35706 // SIMD-ONLY0:       if.end4088:
35707 // SIMD-ONLY0-NEXT:    [[TMP2161:%.*]] = load i64, ptr [[ULLX]], align 8
35708 // SIMD-ONLY0-NEXT:    [[TMP2162:%.*]] = load i64, ptr [[ULLE]], align 8
35709 // SIMD-ONLY0-NEXT:    [[CMP4089:%.*]] = icmp ult i64 [[TMP2161]], [[TMP2162]]
35710 // SIMD-ONLY0-NEXT:    br i1 [[CMP4089]], label [[IF_THEN4091:%.*]], label [[IF_END4092:%.*]]
35711 // SIMD-ONLY0:       if.then4091:
35712 // SIMD-ONLY0-NEXT:    [[TMP2163:%.*]] = load i64, ptr [[ULLE]], align 8
35713 // SIMD-ONLY0-NEXT:    store i64 [[TMP2163]], ptr [[ULLX]], align 8
35714 // SIMD-ONLY0-NEXT:    br label [[IF_END4092]]
35715 // SIMD-ONLY0:       if.end4092:
35716 // SIMD-ONLY0-NEXT:    [[TMP2164:%.*]] = load i64, ptr [[ULLE]], align 8
35717 // SIMD-ONLY0-NEXT:    [[TMP2165:%.*]] = load i64, ptr [[ULLX]], align 8
35718 // SIMD-ONLY0-NEXT:    [[CMP4093:%.*]] = icmp ugt i64 [[TMP2164]], [[TMP2165]]
35719 // SIMD-ONLY0-NEXT:    br i1 [[CMP4093]], label [[IF_THEN4095:%.*]], label [[IF_END4096:%.*]]
35720 // SIMD-ONLY0:       if.then4095:
35721 // SIMD-ONLY0-NEXT:    [[TMP2166:%.*]] = load i64, ptr [[ULLE]], align 8
35722 // SIMD-ONLY0-NEXT:    store i64 [[TMP2166]], ptr [[ULLX]], align 8
35723 // SIMD-ONLY0-NEXT:    br label [[IF_END4096]]
35724 // SIMD-ONLY0:       if.end4096:
35725 // SIMD-ONLY0-NEXT:    [[TMP2167:%.*]] = load i64, ptr [[ULLE]], align 8
35726 // SIMD-ONLY0-NEXT:    [[TMP2168:%.*]] = load i64, ptr [[ULLX]], align 8
35727 // SIMD-ONLY0-NEXT:    [[CMP4097:%.*]] = icmp ult i64 [[TMP2167]], [[TMP2168]]
35728 // SIMD-ONLY0-NEXT:    br i1 [[CMP4097]], label [[IF_THEN4099:%.*]], label [[IF_END4100:%.*]]
35729 // SIMD-ONLY0:       if.then4099:
35730 // SIMD-ONLY0-NEXT:    [[TMP2169:%.*]] = load i64, ptr [[ULLE]], align 8
35731 // SIMD-ONLY0-NEXT:    store i64 [[TMP2169]], ptr [[ULLX]], align 8
35732 // SIMD-ONLY0-NEXT:    br label [[IF_END4100]]
35733 // SIMD-ONLY0:       if.end4100:
35734 // SIMD-ONLY0-NEXT:    [[TMP2170:%.*]] = load i64, ptr [[ULLX]], align 8
35735 // SIMD-ONLY0-NEXT:    [[TMP2171:%.*]] = load i64, ptr [[ULLE]], align 8
35736 // SIMD-ONLY0-NEXT:    [[CMP4101:%.*]] = icmp eq i64 [[TMP2170]], [[TMP2171]]
35737 // SIMD-ONLY0-NEXT:    br i1 [[CMP4101]], label [[COND_TRUE4103:%.*]], label [[COND_FALSE4104:%.*]]
35738 // SIMD-ONLY0:       cond.true4103:
35739 // SIMD-ONLY0-NEXT:    [[TMP2172:%.*]] = load i64, ptr [[ULLD]], align 8
35740 // SIMD-ONLY0-NEXT:    br label [[COND_END4105:%.*]]
35741 // SIMD-ONLY0:       cond.false4104:
35742 // SIMD-ONLY0-NEXT:    [[TMP2173:%.*]] = load i64, ptr [[ULLX]], align 8
35743 // SIMD-ONLY0-NEXT:    br label [[COND_END4105]]
35744 // SIMD-ONLY0:       cond.end4105:
35745 // SIMD-ONLY0-NEXT:    [[COND4106:%.*]] = phi i64 [ [[TMP2172]], [[COND_TRUE4103]] ], [ [[TMP2173]], [[COND_FALSE4104]] ]
35746 // SIMD-ONLY0-NEXT:    store i64 [[COND4106]], ptr [[ULLX]], align 8
35747 // SIMD-ONLY0-NEXT:    [[TMP2174:%.*]] = load i64, ptr [[ULLE]], align 8
35748 // SIMD-ONLY0-NEXT:    [[TMP2175:%.*]] = load i64, ptr [[ULLX]], align 8
35749 // SIMD-ONLY0-NEXT:    [[CMP4107:%.*]] = icmp eq i64 [[TMP2174]], [[TMP2175]]
35750 // SIMD-ONLY0-NEXT:    br i1 [[CMP4107]], label [[COND_TRUE4109:%.*]], label [[COND_FALSE4110:%.*]]
35751 // SIMD-ONLY0:       cond.true4109:
35752 // SIMD-ONLY0-NEXT:    [[TMP2176:%.*]] = load i64, ptr [[ULLD]], align 8
35753 // SIMD-ONLY0-NEXT:    br label [[COND_END4111:%.*]]
35754 // SIMD-ONLY0:       cond.false4110:
35755 // SIMD-ONLY0-NEXT:    [[TMP2177:%.*]] = load i64, ptr [[ULLX]], align 8
35756 // SIMD-ONLY0-NEXT:    br label [[COND_END4111]]
35757 // SIMD-ONLY0:       cond.end4111:
35758 // SIMD-ONLY0-NEXT:    [[COND4112:%.*]] = phi i64 [ [[TMP2176]], [[COND_TRUE4109]] ], [ [[TMP2177]], [[COND_FALSE4110]] ]
35759 // SIMD-ONLY0-NEXT:    store i64 [[COND4112]], ptr [[ULLX]], align 8
35760 // SIMD-ONLY0-NEXT:    [[TMP2178:%.*]] = load i64, ptr [[ULLX]], align 8
35761 // SIMD-ONLY0-NEXT:    [[TMP2179:%.*]] = load i64, ptr [[ULLE]], align 8
35762 // SIMD-ONLY0-NEXT:    [[CMP4113:%.*]] = icmp eq i64 [[TMP2178]], [[TMP2179]]
35763 // SIMD-ONLY0-NEXT:    br i1 [[CMP4113]], label [[IF_THEN4115:%.*]], label [[IF_END4116:%.*]]
35764 // SIMD-ONLY0:       if.then4115:
35765 // SIMD-ONLY0-NEXT:    [[TMP2180:%.*]] = load i64, ptr [[ULLD]], align 8
35766 // SIMD-ONLY0-NEXT:    store i64 [[TMP2180]], ptr [[ULLX]], align 8
35767 // SIMD-ONLY0-NEXT:    br label [[IF_END4116]]
35768 // SIMD-ONLY0:       if.end4116:
35769 // SIMD-ONLY0-NEXT:    [[TMP2181:%.*]] = load i64, ptr [[ULLE]], align 8
35770 // SIMD-ONLY0-NEXT:    [[TMP2182:%.*]] = load i64, ptr [[ULLX]], align 8
35771 // SIMD-ONLY0-NEXT:    [[CMP4117:%.*]] = icmp eq i64 [[TMP2181]], [[TMP2182]]
35772 // SIMD-ONLY0-NEXT:    br i1 [[CMP4117]], label [[IF_THEN4119:%.*]], label [[IF_END4120:%.*]]
35773 // SIMD-ONLY0:       if.then4119:
35774 // SIMD-ONLY0-NEXT:    [[TMP2183:%.*]] = load i64, ptr [[ULLD]], align 8
35775 // SIMD-ONLY0-NEXT:    store i64 [[TMP2183]], ptr [[ULLX]], align 8
35776 // SIMD-ONLY0-NEXT:    br label [[IF_END4120]]
35777 // SIMD-ONLY0:       if.end4120:
35778 // SIMD-ONLY0-NEXT:    [[TMP2184:%.*]] = load i64, ptr [[LLX]], align 8
35779 // SIMD-ONLY0-NEXT:    [[TMP2185:%.*]] = load i64, ptr [[LLE]], align 8
35780 // SIMD-ONLY0-NEXT:    [[CMP4121:%.*]] = icmp sgt i64 [[TMP2184]], [[TMP2185]]
35781 // SIMD-ONLY0-NEXT:    br i1 [[CMP4121]], label [[COND_TRUE4123:%.*]], label [[COND_FALSE4124:%.*]]
35782 // SIMD-ONLY0:       cond.true4123:
35783 // SIMD-ONLY0-NEXT:    [[TMP2186:%.*]] = load i64, ptr [[LLE]], align 8
35784 // SIMD-ONLY0-NEXT:    br label [[COND_END4125:%.*]]
35785 // SIMD-ONLY0:       cond.false4124:
35786 // SIMD-ONLY0-NEXT:    [[TMP2187:%.*]] = load i64, ptr [[LLX]], align 8
35787 // SIMD-ONLY0-NEXT:    br label [[COND_END4125]]
35788 // SIMD-ONLY0:       cond.end4125:
35789 // SIMD-ONLY0-NEXT:    [[COND4126:%.*]] = phi i64 [ [[TMP2186]], [[COND_TRUE4123]] ], [ [[TMP2187]], [[COND_FALSE4124]] ]
35790 // SIMD-ONLY0-NEXT:    store i64 [[COND4126]], ptr [[LLX]], align 8
35791 // SIMD-ONLY0-NEXT:    [[TMP2188:%.*]] = load i64, ptr [[LLX]], align 8
35792 // SIMD-ONLY0-NEXT:    [[TMP2189:%.*]] = load i64, ptr [[LLE]], align 8
35793 // SIMD-ONLY0-NEXT:    [[CMP4127:%.*]] = icmp slt i64 [[TMP2188]], [[TMP2189]]
35794 // SIMD-ONLY0-NEXT:    br i1 [[CMP4127]], label [[COND_TRUE4129:%.*]], label [[COND_FALSE4130:%.*]]
35795 // SIMD-ONLY0:       cond.true4129:
35796 // SIMD-ONLY0-NEXT:    [[TMP2190:%.*]] = load i64, ptr [[LLE]], align 8
35797 // SIMD-ONLY0-NEXT:    br label [[COND_END4131:%.*]]
35798 // SIMD-ONLY0:       cond.false4130:
35799 // SIMD-ONLY0-NEXT:    [[TMP2191:%.*]] = load i64, ptr [[LLX]], align 8
35800 // SIMD-ONLY0-NEXT:    br label [[COND_END4131]]
35801 // SIMD-ONLY0:       cond.end4131:
35802 // SIMD-ONLY0-NEXT:    [[COND4132:%.*]] = phi i64 [ [[TMP2190]], [[COND_TRUE4129]] ], [ [[TMP2191]], [[COND_FALSE4130]] ]
35803 // SIMD-ONLY0-NEXT:    store i64 [[COND4132]], ptr [[LLX]], align 8
35804 // SIMD-ONLY0-NEXT:    [[TMP2192:%.*]] = load i64, ptr [[LLE]], align 8
35805 // SIMD-ONLY0-NEXT:    [[TMP2193:%.*]] = load i64, ptr [[LLX]], align 8
35806 // SIMD-ONLY0-NEXT:    [[CMP4133:%.*]] = icmp sgt i64 [[TMP2192]], [[TMP2193]]
35807 // SIMD-ONLY0-NEXT:    br i1 [[CMP4133]], label [[COND_TRUE4135:%.*]], label [[COND_FALSE4136:%.*]]
35808 // SIMD-ONLY0:       cond.true4135:
35809 // SIMD-ONLY0-NEXT:    [[TMP2194:%.*]] = load i64, ptr [[LLE]], align 8
35810 // SIMD-ONLY0-NEXT:    br label [[COND_END4137:%.*]]
35811 // SIMD-ONLY0:       cond.false4136:
35812 // SIMD-ONLY0-NEXT:    [[TMP2195:%.*]] = load i64, ptr [[LLX]], align 8
35813 // SIMD-ONLY0-NEXT:    br label [[COND_END4137]]
35814 // SIMD-ONLY0:       cond.end4137:
35815 // SIMD-ONLY0-NEXT:    [[COND4138:%.*]] = phi i64 [ [[TMP2194]], [[COND_TRUE4135]] ], [ [[TMP2195]], [[COND_FALSE4136]] ]
35816 // SIMD-ONLY0-NEXT:    store i64 [[COND4138]], ptr [[LLX]], align 8
35817 // SIMD-ONLY0-NEXT:    [[TMP2196:%.*]] = load i64, ptr [[LLE]], align 8
35818 // SIMD-ONLY0-NEXT:    [[TMP2197:%.*]] = load i64, ptr [[LLX]], align 8
35819 // SIMD-ONLY0-NEXT:    [[CMP4139:%.*]] = icmp slt i64 [[TMP2196]], [[TMP2197]]
35820 // SIMD-ONLY0-NEXT:    br i1 [[CMP4139]], label [[COND_TRUE4141:%.*]], label [[COND_FALSE4142:%.*]]
35821 // SIMD-ONLY0:       cond.true4141:
35822 // SIMD-ONLY0-NEXT:    [[TMP2198:%.*]] = load i64, ptr [[LLE]], align 8
35823 // SIMD-ONLY0-NEXT:    br label [[COND_END4143:%.*]]
35824 // SIMD-ONLY0:       cond.false4142:
35825 // SIMD-ONLY0-NEXT:    [[TMP2199:%.*]] = load i64, ptr [[LLX]], align 8
35826 // SIMD-ONLY0-NEXT:    br label [[COND_END4143]]
35827 // SIMD-ONLY0:       cond.end4143:
35828 // SIMD-ONLY0-NEXT:    [[COND4144:%.*]] = phi i64 [ [[TMP2198]], [[COND_TRUE4141]] ], [ [[TMP2199]], [[COND_FALSE4142]] ]
35829 // SIMD-ONLY0-NEXT:    store i64 [[COND4144]], ptr [[LLX]], align 8
35830 // SIMD-ONLY0-NEXT:    [[TMP2200:%.*]] = load i64, ptr [[LLX]], align 8
35831 // SIMD-ONLY0-NEXT:    [[TMP2201:%.*]] = load i64, ptr [[LLE]], align 8
35832 // SIMD-ONLY0-NEXT:    [[CMP4145:%.*]] = icmp sgt i64 [[TMP2200]], [[TMP2201]]
35833 // SIMD-ONLY0-NEXT:    br i1 [[CMP4145]], label [[IF_THEN4147:%.*]], label [[IF_END4148:%.*]]
35834 // SIMD-ONLY0:       if.then4147:
35835 // SIMD-ONLY0-NEXT:    [[TMP2202:%.*]] = load i64, ptr [[LLE]], align 8
35836 // SIMD-ONLY0-NEXT:    store i64 [[TMP2202]], ptr [[LLX]], align 8
35837 // SIMD-ONLY0-NEXT:    br label [[IF_END4148]]
35838 // SIMD-ONLY0:       if.end4148:
35839 // SIMD-ONLY0-NEXT:    [[TMP2203:%.*]] = load i64, ptr [[LLX]], align 8
35840 // SIMD-ONLY0-NEXT:    [[TMP2204:%.*]] = load i64, ptr [[LLE]], align 8
35841 // SIMD-ONLY0-NEXT:    [[CMP4149:%.*]] = icmp slt i64 [[TMP2203]], [[TMP2204]]
35842 // SIMD-ONLY0-NEXT:    br i1 [[CMP4149]], label [[IF_THEN4151:%.*]], label [[IF_END4152:%.*]]
35843 // SIMD-ONLY0:       if.then4151:
35844 // SIMD-ONLY0-NEXT:    [[TMP2205:%.*]] = load i64, ptr [[LLE]], align 8
35845 // SIMD-ONLY0-NEXT:    store i64 [[TMP2205]], ptr [[LLX]], align 8
35846 // SIMD-ONLY0-NEXT:    br label [[IF_END4152]]
35847 // SIMD-ONLY0:       if.end4152:
35848 // SIMD-ONLY0-NEXT:    [[TMP2206:%.*]] = load i64, ptr [[LLE]], align 8
35849 // SIMD-ONLY0-NEXT:    [[TMP2207:%.*]] = load i64, ptr [[LLX]], align 8
35850 // SIMD-ONLY0-NEXT:    [[CMP4153:%.*]] = icmp sgt i64 [[TMP2206]], [[TMP2207]]
35851 // SIMD-ONLY0-NEXT:    br i1 [[CMP4153]], label [[IF_THEN4155:%.*]], label [[IF_END4156:%.*]]
35852 // SIMD-ONLY0:       if.then4155:
35853 // SIMD-ONLY0-NEXT:    [[TMP2208:%.*]] = load i64, ptr [[LLE]], align 8
35854 // SIMD-ONLY0-NEXT:    store i64 [[TMP2208]], ptr [[LLX]], align 8
35855 // SIMD-ONLY0-NEXT:    br label [[IF_END4156]]
35856 // SIMD-ONLY0:       if.end4156:
35857 // SIMD-ONLY0-NEXT:    [[TMP2209:%.*]] = load i64, ptr [[LLE]], align 8
35858 // SIMD-ONLY0-NEXT:    [[TMP2210:%.*]] = load i64, ptr [[LLX]], align 8
35859 // SIMD-ONLY0-NEXT:    [[CMP4157:%.*]] = icmp slt i64 [[TMP2209]], [[TMP2210]]
35860 // SIMD-ONLY0-NEXT:    br i1 [[CMP4157]], label [[IF_THEN4159:%.*]], label [[IF_END4160:%.*]]
35861 // SIMD-ONLY0:       if.then4159:
35862 // SIMD-ONLY0-NEXT:    [[TMP2211:%.*]] = load i64, ptr [[LLE]], align 8
35863 // SIMD-ONLY0-NEXT:    store i64 [[TMP2211]], ptr [[LLX]], align 8
35864 // SIMD-ONLY0-NEXT:    br label [[IF_END4160]]
35865 // SIMD-ONLY0:       if.end4160:
35866 // SIMD-ONLY0-NEXT:    [[TMP2212:%.*]] = load i64, ptr [[LLX]], align 8
35867 // SIMD-ONLY0-NEXT:    [[TMP2213:%.*]] = load i64, ptr [[LLE]], align 8
35868 // SIMD-ONLY0-NEXT:    [[CMP4161:%.*]] = icmp eq i64 [[TMP2212]], [[TMP2213]]
35869 // SIMD-ONLY0-NEXT:    br i1 [[CMP4161]], label [[COND_TRUE4163:%.*]], label [[COND_FALSE4164:%.*]]
35870 // SIMD-ONLY0:       cond.true4163:
35871 // SIMD-ONLY0-NEXT:    [[TMP2214:%.*]] = load i64, ptr [[LLD]], align 8
35872 // SIMD-ONLY0-NEXT:    br label [[COND_END4165:%.*]]
35873 // SIMD-ONLY0:       cond.false4164:
35874 // SIMD-ONLY0-NEXT:    [[TMP2215:%.*]] = load i64, ptr [[LLX]], align 8
35875 // SIMD-ONLY0-NEXT:    br label [[COND_END4165]]
35876 // SIMD-ONLY0:       cond.end4165:
35877 // SIMD-ONLY0-NEXT:    [[COND4166:%.*]] = phi i64 [ [[TMP2214]], [[COND_TRUE4163]] ], [ [[TMP2215]], [[COND_FALSE4164]] ]
35878 // SIMD-ONLY0-NEXT:    store i64 [[COND4166]], ptr [[LLX]], align 8
35879 // SIMD-ONLY0-NEXT:    [[TMP2216:%.*]] = load i64, ptr [[LLE]], align 8
35880 // SIMD-ONLY0-NEXT:    [[TMP2217:%.*]] = load i64, ptr [[LLX]], align 8
35881 // SIMD-ONLY0-NEXT:    [[CMP4167:%.*]] = icmp eq i64 [[TMP2216]], [[TMP2217]]
35882 // SIMD-ONLY0-NEXT:    br i1 [[CMP4167]], label [[COND_TRUE4169:%.*]], label [[COND_FALSE4170:%.*]]
35883 // SIMD-ONLY0:       cond.true4169:
35884 // SIMD-ONLY0-NEXT:    [[TMP2218:%.*]] = load i64, ptr [[LLD]], align 8
35885 // SIMD-ONLY0-NEXT:    br label [[COND_END4171:%.*]]
35886 // SIMD-ONLY0:       cond.false4170:
35887 // SIMD-ONLY0-NEXT:    [[TMP2219:%.*]] = load i64, ptr [[LLX]], align 8
35888 // SIMD-ONLY0-NEXT:    br label [[COND_END4171]]
35889 // SIMD-ONLY0:       cond.end4171:
35890 // SIMD-ONLY0-NEXT:    [[COND4172:%.*]] = phi i64 [ [[TMP2218]], [[COND_TRUE4169]] ], [ [[TMP2219]], [[COND_FALSE4170]] ]
35891 // SIMD-ONLY0-NEXT:    store i64 [[COND4172]], ptr [[LLX]], align 8
35892 // SIMD-ONLY0-NEXT:    [[TMP2220:%.*]] = load i64, ptr [[LLX]], align 8
35893 // SIMD-ONLY0-NEXT:    [[TMP2221:%.*]] = load i64, ptr [[LLE]], align 8
35894 // SIMD-ONLY0-NEXT:    [[CMP4173:%.*]] = icmp eq i64 [[TMP2220]], [[TMP2221]]
35895 // SIMD-ONLY0-NEXT:    br i1 [[CMP4173]], label [[IF_THEN4175:%.*]], label [[IF_END4176:%.*]]
35896 // SIMD-ONLY0:       if.then4175:
35897 // SIMD-ONLY0-NEXT:    [[TMP2222:%.*]] = load i64, ptr [[LLD]], align 8
35898 // SIMD-ONLY0-NEXT:    store i64 [[TMP2222]], ptr [[LLX]], align 8
35899 // SIMD-ONLY0-NEXT:    br label [[IF_END4176]]
35900 // SIMD-ONLY0:       if.end4176:
35901 // SIMD-ONLY0-NEXT:    [[TMP2223:%.*]] = load i64, ptr [[LLE]], align 8
35902 // SIMD-ONLY0-NEXT:    [[TMP2224:%.*]] = load i64, ptr [[LLX]], align 8
35903 // SIMD-ONLY0-NEXT:    [[CMP4177:%.*]] = icmp eq i64 [[TMP2223]], [[TMP2224]]
35904 // SIMD-ONLY0-NEXT:    br i1 [[CMP4177]], label [[IF_THEN4179:%.*]], label [[IF_END4180:%.*]]
35905 // SIMD-ONLY0:       if.then4179:
35906 // SIMD-ONLY0-NEXT:    [[TMP2225:%.*]] = load i64, ptr [[LLD]], align 8
35907 // SIMD-ONLY0-NEXT:    store i64 [[TMP2225]], ptr [[LLX]], align 8
35908 // SIMD-ONLY0-NEXT:    br label [[IF_END4180]]
35909 // SIMD-ONLY0:       if.end4180:
35910 // SIMD-ONLY0-NEXT:    [[TMP2226:%.*]] = load i64, ptr [[ULLX]], align 8
35911 // SIMD-ONLY0-NEXT:    [[TMP2227:%.*]] = load i64, ptr [[ULLE]], align 8
35912 // SIMD-ONLY0-NEXT:    [[CMP4181:%.*]] = icmp ugt i64 [[TMP2226]], [[TMP2227]]
35913 // SIMD-ONLY0-NEXT:    br i1 [[CMP4181]], label [[COND_TRUE4183:%.*]], label [[COND_FALSE4184:%.*]]
35914 // SIMD-ONLY0:       cond.true4183:
35915 // SIMD-ONLY0-NEXT:    [[TMP2228:%.*]] = load i64, ptr [[ULLE]], align 8
35916 // SIMD-ONLY0-NEXT:    br label [[COND_END4185:%.*]]
35917 // SIMD-ONLY0:       cond.false4184:
35918 // SIMD-ONLY0-NEXT:    [[TMP2229:%.*]] = load i64, ptr [[ULLX]], align 8
35919 // SIMD-ONLY0-NEXT:    br label [[COND_END4185]]
35920 // SIMD-ONLY0:       cond.end4185:
35921 // SIMD-ONLY0-NEXT:    [[COND4186:%.*]] = phi i64 [ [[TMP2228]], [[COND_TRUE4183]] ], [ [[TMP2229]], [[COND_FALSE4184]] ]
35922 // SIMD-ONLY0-NEXT:    store i64 [[COND4186]], ptr [[ULLX]], align 8
35923 // SIMD-ONLY0-NEXT:    [[TMP2230:%.*]] = load i64, ptr [[ULLX]], align 8
35924 // SIMD-ONLY0-NEXT:    [[TMP2231:%.*]] = load i64, ptr [[ULLE]], align 8
35925 // SIMD-ONLY0-NEXT:    [[CMP4187:%.*]] = icmp ult i64 [[TMP2230]], [[TMP2231]]
35926 // SIMD-ONLY0-NEXT:    br i1 [[CMP4187]], label [[COND_TRUE4189:%.*]], label [[COND_FALSE4190:%.*]]
35927 // SIMD-ONLY0:       cond.true4189:
35928 // SIMD-ONLY0-NEXT:    [[TMP2232:%.*]] = load i64, ptr [[ULLE]], align 8
35929 // SIMD-ONLY0-NEXT:    br label [[COND_END4191:%.*]]
35930 // SIMD-ONLY0:       cond.false4190:
35931 // SIMD-ONLY0-NEXT:    [[TMP2233:%.*]] = load i64, ptr [[ULLX]], align 8
35932 // SIMD-ONLY0-NEXT:    br label [[COND_END4191]]
35933 // SIMD-ONLY0:       cond.end4191:
35934 // SIMD-ONLY0-NEXT:    [[COND4192:%.*]] = phi i64 [ [[TMP2232]], [[COND_TRUE4189]] ], [ [[TMP2233]], [[COND_FALSE4190]] ]
35935 // SIMD-ONLY0-NEXT:    store i64 [[COND4192]], ptr [[ULLX]], align 8
35936 // SIMD-ONLY0-NEXT:    [[TMP2234:%.*]] = load i64, ptr [[ULLE]], align 8
35937 // SIMD-ONLY0-NEXT:    [[TMP2235:%.*]] = load i64, ptr [[ULLX]], align 8
35938 // SIMD-ONLY0-NEXT:    [[CMP4193:%.*]] = icmp ugt i64 [[TMP2234]], [[TMP2235]]
35939 // SIMD-ONLY0-NEXT:    br i1 [[CMP4193]], label [[COND_TRUE4195:%.*]], label [[COND_FALSE4196:%.*]]
35940 // SIMD-ONLY0:       cond.true4195:
35941 // SIMD-ONLY0-NEXT:    [[TMP2236:%.*]] = load i64, ptr [[ULLE]], align 8
35942 // SIMD-ONLY0-NEXT:    br label [[COND_END4197:%.*]]
35943 // SIMD-ONLY0:       cond.false4196:
35944 // SIMD-ONLY0-NEXT:    [[TMP2237:%.*]] = load i64, ptr [[ULLX]], align 8
35945 // SIMD-ONLY0-NEXT:    br label [[COND_END4197]]
35946 // SIMD-ONLY0:       cond.end4197:
35947 // SIMD-ONLY0-NEXT:    [[COND4198:%.*]] = phi i64 [ [[TMP2236]], [[COND_TRUE4195]] ], [ [[TMP2237]], [[COND_FALSE4196]] ]
35948 // SIMD-ONLY0-NEXT:    store i64 [[COND4198]], ptr [[ULLX]], align 8
35949 // SIMD-ONLY0-NEXT:    [[TMP2238:%.*]] = load i64, ptr [[ULLE]], align 8
35950 // SIMD-ONLY0-NEXT:    [[TMP2239:%.*]] = load i64, ptr [[ULLX]], align 8
35951 // SIMD-ONLY0-NEXT:    [[CMP4199:%.*]] = icmp ult i64 [[TMP2238]], [[TMP2239]]
35952 // SIMD-ONLY0-NEXT:    br i1 [[CMP4199]], label [[COND_TRUE4201:%.*]], label [[COND_FALSE4202:%.*]]
35953 // SIMD-ONLY0:       cond.true4201:
35954 // SIMD-ONLY0-NEXT:    [[TMP2240:%.*]] = load i64, ptr [[ULLE]], align 8
35955 // SIMD-ONLY0-NEXT:    br label [[COND_END4203:%.*]]
35956 // SIMD-ONLY0:       cond.false4202:
35957 // SIMD-ONLY0-NEXT:    [[TMP2241:%.*]] = load i64, ptr [[ULLX]], align 8
35958 // SIMD-ONLY0-NEXT:    br label [[COND_END4203]]
35959 // SIMD-ONLY0:       cond.end4203:
35960 // SIMD-ONLY0-NEXT:    [[COND4204:%.*]] = phi i64 [ [[TMP2240]], [[COND_TRUE4201]] ], [ [[TMP2241]], [[COND_FALSE4202]] ]
35961 // SIMD-ONLY0-NEXT:    store i64 [[COND4204]], ptr [[ULLX]], align 8
35962 // SIMD-ONLY0-NEXT:    [[TMP2242:%.*]] = load i64, ptr [[ULLX]], align 8
35963 // SIMD-ONLY0-NEXT:    [[TMP2243:%.*]] = load i64, ptr [[ULLE]], align 8
35964 // SIMD-ONLY0-NEXT:    [[CMP4205:%.*]] = icmp ugt i64 [[TMP2242]], [[TMP2243]]
35965 // SIMD-ONLY0-NEXT:    br i1 [[CMP4205]], label [[IF_THEN4207:%.*]], label [[IF_END4208:%.*]]
35966 // SIMD-ONLY0:       if.then4207:
35967 // SIMD-ONLY0-NEXT:    [[TMP2244:%.*]] = load i64, ptr [[ULLE]], align 8
35968 // SIMD-ONLY0-NEXT:    store i64 [[TMP2244]], ptr [[ULLX]], align 8
35969 // SIMD-ONLY0-NEXT:    br label [[IF_END4208]]
35970 // SIMD-ONLY0:       if.end4208:
35971 // SIMD-ONLY0-NEXT:    [[TMP2245:%.*]] = load i64, ptr [[ULLX]], align 8
35972 // SIMD-ONLY0-NEXT:    [[TMP2246:%.*]] = load i64, ptr [[ULLE]], align 8
35973 // SIMD-ONLY0-NEXT:    [[CMP4209:%.*]] = icmp ult i64 [[TMP2245]], [[TMP2246]]
35974 // SIMD-ONLY0-NEXT:    br i1 [[CMP4209]], label [[IF_THEN4211:%.*]], label [[IF_END4212:%.*]]
35975 // SIMD-ONLY0:       if.then4211:
35976 // SIMD-ONLY0-NEXT:    [[TMP2247:%.*]] = load i64, ptr [[ULLE]], align 8
35977 // SIMD-ONLY0-NEXT:    store i64 [[TMP2247]], ptr [[ULLX]], align 8
35978 // SIMD-ONLY0-NEXT:    br label [[IF_END4212]]
35979 // SIMD-ONLY0:       if.end4212:
35980 // SIMD-ONLY0-NEXT:    [[TMP2248:%.*]] = load i64, ptr [[ULLE]], align 8
35981 // SIMD-ONLY0-NEXT:    [[TMP2249:%.*]] = load i64, ptr [[ULLX]], align 8
35982 // SIMD-ONLY0-NEXT:    [[CMP4213:%.*]] = icmp ugt i64 [[TMP2248]], [[TMP2249]]
35983 // SIMD-ONLY0-NEXT:    br i1 [[CMP4213]], label [[IF_THEN4215:%.*]], label [[IF_END4216:%.*]]
35984 // SIMD-ONLY0:       if.then4215:
35985 // SIMD-ONLY0-NEXT:    [[TMP2250:%.*]] = load i64, ptr [[ULLE]], align 8
35986 // SIMD-ONLY0-NEXT:    store i64 [[TMP2250]], ptr [[ULLX]], align 8
35987 // SIMD-ONLY0-NEXT:    br label [[IF_END4216]]
35988 // SIMD-ONLY0:       if.end4216:
35989 // SIMD-ONLY0-NEXT:    [[TMP2251:%.*]] = load i64, ptr [[ULLE]], align 8
35990 // SIMD-ONLY0-NEXT:    [[TMP2252:%.*]] = load i64, ptr [[ULLX]], align 8
35991 // SIMD-ONLY0-NEXT:    [[CMP4217:%.*]] = icmp ult i64 [[TMP2251]], [[TMP2252]]
35992 // SIMD-ONLY0-NEXT:    br i1 [[CMP4217]], label [[IF_THEN4219:%.*]], label [[IF_END4220:%.*]]
35993 // SIMD-ONLY0:       if.then4219:
35994 // SIMD-ONLY0-NEXT:    [[TMP2253:%.*]] = load i64, ptr [[ULLE]], align 8
35995 // SIMD-ONLY0-NEXT:    store i64 [[TMP2253]], ptr [[ULLX]], align 8
35996 // SIMD-ONLY0-NEXT:    br label [[IF_END4220]]
35997 // SIMD-ONLY0:       if.end4220:
35998 // SIMD-ONLY0-NEXT:    [[TMP2254:%.*]] = load i64, ptr [[ULLX]], align 8
35999 // SIMD-ONLY0-NEXT:    [[TMP2255:%.*]] = load i64, ptr [[ULLE]], align 8
36000 // SIMD-ONLY0-NEXT:    [[CMP4221:%.*]] = icmp eq i64 [[TMP2254]], [[TMP2255]]
36001 // SIMD-ONLY0-NEXT:    br i1 [[CMP4221]], label [[COND_TRUE4223:%.*]], label [[COND_FALSE4224:%.*]]
36002 // SIMD-ONLY0:       cond.true4223:
36003 // SIMD-ONLY0-NEXT:    [[TMP2256:%.*]] = load i64, ptr [[ULLD]], align 8
36004 // SIMD-ONLY0-NEXT:    br label [[COND_END4225:%.*]]
36005 // SIMD-ONLY0:       cond.false4224:
36006 // SIMD-ONLY0-NEXT:    [[TMP2257:%.*]] = load i64, ptr [[ULLX]], align 8
36007 // SIMD-ONLY0-NEXT:    br label [[COND_END4225]]
36008 // SIMD-ONLY0:       cond.end4225:
36009 // SIMD-ONLY0-NEXT:    [[COND4226:%.*]] = phi i64 [ [[TMP2256]], [[COND_TRUE4223]] ], [ [[TMP2257]], [[COND_FALSE4224]] ]
36010 // SIMD-ONLY0-NEXT:    store i64 [[COND4226]], ptr [[ULLX]], align 8
36011 // SIMD-ONLY0-NEXT:    [[TMP2258:%.*]] = load i64, ptr [[ULLE]], align 8
36012 // SIMD-ONLY0-NEXT:    [[TMP2259:%.*]] = load i64, ptr [[ULLX]], align 8
36013 // SIMD-ONLY0-NEXT:    [[CMP4227:%.*]] = icmp eq i64 [[TMP2258]], [[TMP2259]]
36014 // SIMD-ONLY0-NEXT:    br i1 [[CMP4227]], label [[COND_TRUE4229:%.*]], label [[COND_FALSE4230:%.*]]
36015 // SIMD-ONLY0:       cond.true4229:
36016 // SIMD-ONLY0-NEXT:    [[TMP2260:%.*]] = load i64, ptr [[ULLD]], align 8
36017 // SIMD-ONLY0-NEXT:    br label [[COND_END4231:%.*]]
36018 // SIMD-ONLY0:       cond.false4230:
36019 // SIMD-ONLY0-NEXT:    [[TMP2261:%.*]] = load i64, ptr [[ULLX]], align 8
36020 // SIMD-ONLY0-NEXT:    br label [[COND_END4231]]
36021 // SIMD-ONLY0:       cond.end4231:
36022 // SIMD-ONLY0-NEXT:    [[COND4232:%.*]] = phi i64 [ [[TMP2260]], [[COND_TRUE4229]] ], [ [[TMP2261]], [[COND_FALSE4230]] ]
36023 // SIMD-ONLY0-NEXT:    store i64 [[COND4232]], ptr [[ULLX]], align 8
36024 // SIMD-ONLY0-NEXT:    [[TMP2262:%.*]] = load i64, ptr [[ULLX]], align 8
36025 // SIMD-ONLY0-NEXT:    [[TMP2263:%.*]] = load i64, ptr [[ULLE]], align 8
36026 // SIMD-ONLY0-NEXT:    [[CMP4233:%.*]] = icmp eq i64 [[TMP2262]], [[TMP2263]]
36027 // SIMD-ONLY0-NEXT:    br i1 [[CMP4233]], label [[IF_THEN4235:%.*]], label [[IF_END4236:%.*]]
36028 // SIMD-ONLY0:       if.then4235:
36029 // SIMD-ONLY0-NEXT:    [[TMP2264:%.*]] = load i64, ptr [[ULLD]], align 8
36030 // SIMD-ONLY0-NEXT:    store i64 [[TMP2264]], ptr [[ULLX]], align 8
36031 // SIMD-ONLY0-NEXT:    br label [[IF_END4236]]
36032 // SIMD-ONLY0:       if.end4236:
36033 // SIMD-ONLY0-NEXT:    [[TMP2265:%.*]] = load i64, ptr [[ULLE]], align 8
36034 // SIMD-ONLY0-NEXT:    [[TMP2266:%.*]] = load i64, ptr [[ULLX]], align 8
36035 // SIMD-ONLY0-NEXT:    [[CMP4237:%.*]] = icmp eq i64 [[TMP2265]], [[TMP2266]]
36036 // SIMD-ONLY0-NEXT:    br i1 [[CMP4237]], label [[IF_THEN4239:%.*]], label [[IF_END4240:%.*]]
36037 // SIMD-ONLY0:       if.then4239:
36038 // SIMD-ONLY0-NEXT:    [[TMP2267:%.*]] = load i64, ptr [[ULLD]], align 8
36039 // SIMD-ONLY0-NEXT:    store i64 [[TMP2267]], ptr [[ULLX]], align 8
36040 // SIMD-ONLY0-NEXT:    br label [[IF_END4240]]
36041 // SIMD-ONLY0:       if.end4240:
36042 // SIMD-ONLY0-NEXT:    [[TMP2268:%.*]] = load i64, ptr [[LLX]], align 8
36043 // SIMD-ONLY0-NEXT:    [[TMP2269:%.*]] = load i64, ptr [[LLE]], align 8
36044 // SIMD-ONLY0-NEXT:    [[CMP4241:%.*]] = icmp sgt i64 [[TMP2268]], [[TMP2269]]
36045 // SIMD-ONLY0-NEXT:    br i1 [[CMP4241]], label [[COND_TRUE4243:%.*]], label [[COND_FALSE4244:%.*]]
36046 // SIMD-ONLY0:       cond.true4243:
36047 // SIMD-ONLY0-NEXT:    [[TMP2270:%.*]] = load i64, ptr [[LLE]], align 8
36048 // SIMD-ONLY0-NEXT:    br label [[COND_END4245:%.*]]
36049 // SIMD-ONLY0:       cond.false4244:
36050 // SIMD-ONLY0-NEXT:    [[TMP2271:%.*]] = load i64, ptr [[LLX]], align 8
36051 // SIMD-ONLY0-NEXT:    br label [[COND_END4245]]
36052 // SIMD-ONLY0:       cond.end4245:
36053 // SIMD-ONLY0-NEXT:    [[COND4246:%.*]] = phi i64 [ [[TMP2270]], [[COND_TRUE4243]] ], [ [[TMP2271]], [[COND_FALSE4244]] ]
36054 // SIMD-ONLY0-NEXT:    store i64 [[COND4246]], ptr [[LLX]], align 8
36055 // SIMD-ONLY0-NEXT:    [[TMP2272:%.*]] = load i64, ptr [[LLX]], align 8
36056 // SIMD-ONLY0-NEXT:    [[TMP2273:%.*]] = load i64, ptr [[LLE]], align 8
36057 // SIMD-ONLY0-NEXT:    [[CMP4247:%.*]] = icmp slt i64 [[TMP2272]], [[TMP2273]]
36058 // SIMD-ONLY0-NEXT:    br i1 [[CMP4247]], label [[COND_TRUE4249:%.*]], label [[COND_FALSE4250:%.*]]
36059 // SIMD-ONLY0:       cond.true4249:
36060 // SIMD-ONLY0-NEXT:    [[TMP2274:%.*]] = load i64, ptr [[LLE]], align 8
36061 // SIMD-ONLY0-NEXT:    br label [[COND_END4251:%.*]]
36062 // SIMD-ONLY0:       cond.false4250:
36063 // SIMD-ONLY0-NEXT:    [[TMP2275:%.*]] = load i64, ptr [[LLX]], align 8
36064 // SIMD-ONLY0-NEXT:    br label [[COND_END4251]]
36065 // SIMD-ONLY0:       cond.end4251:
36066 // SIMD-ONLY0-NEXT:    [[COND4252:%.*]] = phi i64 [ [[TMP2274]], [[COND_TRUE4249]] ], [ [[TMP2275]], [[COND_FALSE4250]] ]
36067 // SIMD-ONLY0-NEXT:    store i64 [[COND4252]], ptr [[LLX]], align 8
36068 // SIMD-ONLY0-NEXT:    [[TMP2276:%.*]] = load i64, ptr [[LLE]], align 8
36069 // SIMD-ONLY0-NEXT:    [[TMP2277:%.*]] = load i64, ptr [[LLX]], align 8
36070 // SIMD-ONLY0-NEXT:    [[CMP4253:%.*]] = icmp sgt i64 [[TMP2276]], [[TMP2277]]
36071 // SIMD-ONLY0-NEXT:    br i1 [[CMP4253]], label [[COND_TRUE4255:%.*]], label [[COND_FALSE4256:%.*]]
36072 // SIMD-ONLY0:       cond.true4255:
36073 // SIMD-ONLY0-NEXT:    [[TMP2278:%.*]] = load i64, ptr [[LLE]], align 8
36074 // SIMD-ONLY0-NEXT:    br label [[COND_END4257:%.*]]
36075 // SIMD-ONLY0:       cond.false4256:
36076 // SIMD-ONLY0-NEXT:    [[TMP2279:%.*]] = load i64, ptr [[LLX]], align 8
36077 // SIMD-ONLY0-NEXT:    br label [[COND_END4257]]
36078 // SIMD-ONLY0:       cond.end4257:
36079 // SIMD-ONLY0-NEXT:    [[COND4258:%.*]] = phi i64 [ [[TMP2278]], [[COND_TRUE4255]] ], [ [[TMP2279]], [[COND_FALSE4256]] ]
36080 // SIMD-ONLY0-NEXT:    store i64 [[COND4258]], ptr [[LLX]], align 8
36081 // SIMD-ONLY0-NEXT:    [[TMP2280:%.*]] = load i64, ptr [[LLE]], align 8
36082 // SIMD-ONLY0-NEXT:    [[TMP2281:%.*]] = load i64, ptr [[LLX]], align 8
36083 // SIMD-ONLY0-NEXT:    [[CMP4259:%.*]] = icmp slt i64 [[TMP2280]], [[TMP2281]]
36084 // SIMD-ONLY0-NEXT:    br i1 [[CMP4259]], label [[COND_TRUE4261:%.*]], label [[COND_FALSE4262:%.*]]
36085 // SIMD-ONLY0:       cond.true4261:
36086 // SIMD-ONLY0-NEXT:    [[TMP2282:%.*]] = load i64, ptr [[LLE]], align 8
36087 // SIMD-ONLY0-NEXT:    br label [[COND_END4263:%.*]]
36088 // SIMD-ONLY0:       cond.false4262:
36089 // SIMD-ONLY0-NEXT:    [[TMP2283:%.*]] = load i64, ptr [[LLX]], align 8
36090 // SIMD-ONLY0-NEXT:    br label [[COND_END4263]]
36091 // SIMD-ONLY0:       cond.end4263:
36092 // SIMD-ONLY0-NEXT:    [[COND4264:%.*]] = phi i64 [ [[TMP2282]], [[COND_TRUE4261]] ], [ [[TMP2283]], [[COND_FALSE4262]] ]
36093 // SIMD-ONLY0-NEXT:    store i64 [[COND4264]], ptr [[LLX]], align 8
36094 // SIMD-ONLY0-NEXT:    [[TMP2284:%.*]] = load i64, ptr [[LLX]], align 8
36095 // SIMD-ONLY0-NEXT:    [[TMP2285:%.*]] = load i64, ptr [[LLE]], align 8
36096 // SIMD-ONLY0-NEXT:    [[CMP4265:%.*]] = icmp sgt i64 [[TMP2284]], [[TMP2285]]
36097 // SIMD-ONLY0-NEXT:    br i1 [[CMP4265]], label [[IF_THEN4267:%.*]], label [[IF_END4268:%.*]]
36098 // SIMD-ONLY0:       if.then4267:
36099 // SIMD-ONLY0-NEXT:    [[TMP2286:%.*]] = load i64, ptr [[LLE]], align 8
36100 // SIMD-ONLY0-NEXT:    store i64 [[TMP2286]], ptr [[LLX]], align 8
36101 // SIMD-ONLY0-NEXT:    br label [[IF_END4268]]
36102 // SIMD-ONLY0:       if.end4268:
36103 // SIMD-ONLY0-NEXT:    [[TMP2287:%.*]] = load i64, ptr [[LLX]], align 8
36104 // SIMD-ONLY0-NEXT:    [[TMP2288:%.*]] = load i64, ptr [[LLE]], align 8
36105 // SIMD-ONLY0-NEXT:    [[CMP4269:%.*]] = icmp slt i64 [[TMP2287]], [[TMP2288]]
36106 // SIMD-ONLY0-NEXT:    br i1 [[CMP4269]], label [[IF_THEN4271:%.*]], label [[IF_END4272:%.*]]
36107 // SIMD-ONLY0:       if.then4271:
36108 // SIMD-ONLY0-NEXT:    [[TMP2289:%.*]] = load i64, ptr [[LLE]], align 8
36109 // SIMD-ONLY0-NEXT:    store i64 [[TMP2289]], ptr [[LLX]], align 8
36110 // SIMD-ONLY0-NEXT:    br label [[IF_END4272]]
36111 // SIMD-ONLY0:       if.end4272:
36112 // SIMD-ONLY0-NEXT:    [[TMP2290:%.*]] = load i64, ptr [[LLE]], align 8
36113 // SIMD-ONLY0-NEXT:    [[TMP2291:%.*]] = load i64, ptr [[LLX]], align 8
36114 // SIMD-ONLY0-NEXT:    [[CMP4273:%.*]] = icmp sgt i64 [[TMP2290]], [[TMP2291]]
36115 // SIMD-ONLY0-NEXT:    br i1 [[CMP4273]], label [[IF_THEN4275:%.*]], label [[IF_END4276:%.*]]
36116 // SIMD-ONLY0:       if.then4275:
36117 // SIMD-ONLY0-NEXT:    [[TMP2292:%.*]] = load i64, ptr [[LLE]], align 8
36118 // SIMD-ONLY0-NEXT:    store i64 [[TMP2292]], ptr [[LLX]], align 8
36119 // SIMD-ONLY0-NEXT:    br label [[IF_END4276]]
36120 // SIMD-ONLY0:       if.end4276:
36121 // SIMD-ONLY0-NEXT:    [[TMP2293:%.*]] = load i64, ptr [[LLE]], align 8
36122 // SIMD-ONLY0-NEXT:    [[TMP2294:%.*]] = load i64, ptr [[LLX]], align 8
36123 // SIMD-ONLY0-NEXT:    [[CMP4277:%.*]] = icmp slt i64 [[TMP2293]], [[TMP2294]]
36124 // SIMD-ONLY0-NEXT:    br i1 [[CMP4277]], label [[IF_THEN4279:%.*]], label [[IF_END4280:%.*]]
36125 // SIMD-ONLY0:       if.then4279:
36126 // SIMD-ONLY0-NEXT:    [[TMP2295:%.*]] = load i64, ptr [[LLE]], align 8
36127 // SIMD-ONLY0-NEXT:    store i64 [[TMP2295]], ptr [[LLX]], align 8
36128 // SIMD-ONLY0-NEXT:    br label [[IF_END4280]]
36129 // SIMD-ONLY0:       if.end4280:
36130 // SIMD-ONLY0-NEXT:    [[TMP2296:%.*]] = load i64, ptr [[LLX]], align 8
36131 // SIMD-ONLY0-NEXT:    [[TMP2297:%.*]] = load i64, ptr [[LLE]], align 8
36132 // SIMD-ONLY0-NEXT:    [[CMP4281:%.*]] = icmp eq i64 [[TMP2296]], [[TMP2297]]
36133 // SIMD-ONLY0-NEXT:    br i1 [[CMP4281]], label [[COND_TRUE4283:%.*]], label [[COND_FALSE4284:%.*]]
36134 // SIMD-ONLY0:       cond.true4283:
36135 // SIMD-ONLY0-NEXT:    [[TMP2298:%.*]] = load i64, ptr [[LLD]], align 8
36136 // SIMD-ONLY0-NEXT:    br label [[COND_END4285:%.*]]
36137 // SIMD-ONLY0:       cond.false4284:
36138 // SIMD-ONLY0-NEXT:    [[TMP2299:%.*]] = load i64, ptr [[LLX]], align 8
36139 // SIMD-ONLY0-NEXT:    br label [[COND_END4285]]
36140 // SIMD-ONLY0:       cond.end4285:
36141 // SIMD-ONLY0-NEXT:    [[COND4286:%.*]] = phi i64 [ [[TMP2298]], [[COND_TRUE4283]] ], [ [[TMP2299]], [[COND_FALSE4284]] ]
36142 // SIMD-ONLY0-NEXT:    store i64 [[COND4286]], ptr [[LLX]], align 8
36143 // SIMD-ONLY0-NEXT:    [[TMP2300:%.*]] = load i64, ptr [[LLE]], align 8
36144 // SIMD-ONLY0-NEXT:    [[TMP2301:%.*]] = load i64, ptr [[LLX]], align 8
36145 // SIMD-ONLY0-NEXT:    [[CMP4287:%.*]] = icmp eq i64 [[TMP2300]], [[TMP2301]]
36146 // SIMD-ONLY0-NEXT:    br i1 [[CMP4287]], label [[COND_TRUE4289:%.*]], label [[COND_FALSE4290:%.*]]
36147 // SIMD-ONLY0:       cond.true4289:
36148 // SIMD-ONLY0-NEXT:    [[TMP2302:%.*]] = load i64, ptr [[LLD]], align 8
36149 // SIMD-ONLY0-NEXT:    br label [[COND_END4291:%.*]]
36150 // SIMD-ONLY0:       cond.false4290:
36151 // SIMD-ONLY0-NEXT:    [[TMP2303:%.*]] = load i64, ptr [[LLX]], align 8
36152 // SIMD-ONLY0-NEXT:    br label [[COND_END4291]]
36153 // SIMD-ONLY0:       cond.end4291:
36154 // SIMD-ONLY0-NEXT:    [[COND4292:%.*]] = phi i64 [ [[TMP2302]], [[COND_TRUE4289]] ], [ [[TMP2303]], [[COND_FALSE4290]] ]
36155 // SIMD-ONLY0-NEXT:    store i64 [[COND4292]], ptr [[LLX]], align 8
36156 // SIMD-ONLY0-NEXT:    [[TMP2304:%.*]] = load i64, ptr [[LLX]], align 8
36157 // SIMD-ONLY0-NEXT:    [[TMP2305:%.*]] = load i64, ptr [[LLE]], align 8
36158 // SIMD-ONLY0-NEXT:    [[CMP4293:%.*]] = icmp eq i64 [[TMP2304]], [[TMP2305]]
36159 // SIMD-ONLY0-NEXT:    br i1 [[CMP4293]], label [[IF_THEN4295:%.*]], label [[IF_END4296:%.*]]
36160 // SIMD-ONLY0:       if.then4295:
36161 // SIMD-ONLY0-NEXT:    [[TMP2306:%.*]] = load i64, ptr [[LLD]], align 8
36162 // SIMD-ONLY0-NEXT:    store i64 [[TMP2306]], ptr [[LLX]], align 8
36163 // SIMD-ONLY0-NEXT:    br label [[IF_END4296]]
36164 // SIMD-ONLY0:       if.end4296:
36165 // SIMD-ONLY0-NEXT:    [[TMP2307:%.*]] = load i64, ptr [[LLE]], align 8
36166 // SIMD-ONLY0-NEXT:    [[TMP2308:%.*]] = load i64, ptr [[LLX]], align 8
36167 // SIMD-ONLY0-NEXT:    [[CMP4297:%.*]] = icmp eq i64 [[TMP2307]], [[TMP2308]]
36168 // SIMD-ONLY0-NEXT:    br i1 [[CMP4297]], label [[IF_THEN4299:%.*]], label [[IF_END4300:%.*]]
36169 // SIMD-ONLY0:       if.then4299:
36170 // SIMD-ONLY0-NEXT:    [[TMP2309:%.*]] = load i64, ptr [[LLD]], align 8
36171 // SIMD-ONLY0-NEXT:    store i64 [[TMP2309]], ptr [[LLX]], align 8
36172 // SIMD-ONLY0-NEXT:    br label [[IF_END4300]]
36173 // SIMD-ONLY0:       if.end4300:
36174 // SIMD-ONLY0-NEXT:    [[TMP2310:%.*]] = load i64, ptr [[ULLX]], align 8
36175 // SIMD-ONLY0-NEXT:    [[TMP2311:%.*]] = load i64, ptr [[ULLE]], align 8
36176 // SIMD-ONLY0-NEXT:    [[CMP4301:%.*]] = icmp ugt i64 [[TMP2310]], [[TMP2311]]
36177 // SIMD-ONLY0-NEXT:    br i1 [[CMP4301]], label [[COND_TRUE4303:%.*]], label [[COND_FALSE4304:%.*]]
36178 // SIMD-ONLY0:       cond.true4303:
36179 // SIMD-ONLY0-NEXT:    [[TMP2312:%.*]] = load i64, ptr [[ULLE]], align 8
36180 // SIMD-ONLY0-NEXT:    br label [[COND_END4305:%.*]]
36181 // SIMD-ONLY0:       cond.false4304:
36182 // SIMD-ONLY0-NEXT:    [[TMP2313:%.*]] = load i64, ptr [[ULLX]], align 8
36183 // SIMD-ONLY0-NEXT:    br label [[COND_END4305]]
36184 // SIMD-ONLY0:       cond.end4305:
36185 // SIMD-ONLY0-NEXT:    [[COND4306:%.*]] = phi i64 [ [[TMP2312]], [[COND_TRUE4303]] ], [ [[TMP2313]], [[COND_FALSE4304]] ]
36186 // SIMD-ONLY0-NEXT:    store i64 [[COND4306]], ptr [[ULLX]], align 8
36187 // SIMD-ONLY0-NEXT:    [[TMP2314:%.*]] = load i64, ptr [[ULLX]], align 8
36188 // SIMD-ONLY0-NEXT:    [[TMP2315:%.*]] = load i64, ptr [[ULLE]], align 8
36189 // SIMD-ONLY0-NEXT:    [[CMP4307:%.*]] = icmp ult i64 [[TMP2314]], [[TMP2315]]
36190 // SIMD-ONLY0-NEXT:    br i1 [[CMP4307]], label [[COND_TRUE4309:%.*]], label [[COND_FALSE4310:%.*]]
36191 // SIMD-ONLY0:       cond.true4309:
36192 // SIMD-ONLY0-NEXT:    [[TMP2316:%.*]] = load i64, ptr [[ULLE]], align 8
36193 // SIMD-ONLY0-NEXT:    br label [[COND_END4311:%.*]]
36194 // SIMD-ONLY0:       cond.false4310:
36195 // SIMD-ONLY0-NEXT:    [[TMP2317:%.*]] = load i64, ptr [[ULLX]], align 8
36196 // SIMD-ONLY0-NEXT:    br label [[COND_END4311]]
36197 // SIMD-ONLY0:       cond.end4311:
36198 // SIMD-ONLY0-NEXT:    [[COND4312:%.*]] = phi i64 [ [[TMP2316]], [[COND_TRUE4309]] ], [ [[TMP2317]], [[COND_FALSE4310]] ]
36199 // SIMD-ONLY0-NEXT:    store i64 [[COND4312]], ptr [[ULLX]], align 8
36200 // SIMD-ONLY0-NEXT:    [[TMP2318:%.*]] = load i64, ptr [[ULLE]], align 8
36201 // SIMD-ONLY0-NEXT:    [[TMP2319:%.*]] = load i64, ptr [[ULLX]], align 8
36202 // SIMD-ONLY0-NEXT:    [[CMP4313:%.*]] = icmp ugt i64 [[TMP2318]], [[TMP2319]]
36203 // SIMD-ONLY0-NEXT:    br i1 [[CMP4313]], label [[COND_TRUE4315:%.*]], label [[COND_FALSE4316:%.*]]
36204 // SIMD-ONLY0:       cond.true4315:
36205 // SIMD-ONLY0-NEXT:    [[TMP2320:%.*]] = load i64, ptr [[ULLE]], align 8
36206 // SIMD-ONLY0-NEXT:    br label [[COND_END4317:%.*]]
36207 // SIMD-ONLY0:       cond.false4316:
36208 // SIMD-ONLY0-NEXT:    [[TMP2321:%.*]] = load i64, ptr [[ULLX]], align 8
36209 // SIMD-ONLY0-NEXT:    br label [[COND_END4317]]
36210 // SIMD-ONLY0:       cond.end4317:
36211 // SIMD-ONLY0-NEXT:    [[COND4318:%.*]] = phi i64 [ [[TMP2320]], [[COND_TRUE4315]] ], [ [[TMP2321]], [[COND_FALSE4316]] ]
36212 // SIMD-ONLY0-NEXT:    store i64 [[COND4318]], ptr [[ULLX]], align 8
36213 // SIMD-ONLY0-NEXT:    [[TMP2322:%.*]] = load i64, ptr [[ULLE]], align 8
36214 // SIMD-ONLY0-NEXT:    [[TMP2323:%.*]] = load i64, ptr [[ULLX]], align 8
36215 // SIMD-ONLY0-NEXT:    [[CMP4319:%.*]] = icmp ult i64 [[TMP2322]], [[TMP2323]]
36216 // SIMD-ONLY0-NEXT:    br i1 [[CMP4319]], label [[COND_TRUE4321:%.*]], label [[COND_FALSE4322:%.*]]
36217 // SIMD-ONLY0:       cond.true4321:
36218 // SIMD-ONLY0-NEXT:    [[TMP2324:%.*]] = load i64, ptr [[ULLE]], align 8
36219 // SIMD-ONLY0-NEXT:    br label [[COND_END4323:%.*]]
36220 // SIMD-ONLY0:       cond.false4322:
36221 // SIMD-ONLY0-NEXT:    [[TMP2325:%.*]] = load i64, ptr [[ULLX]], align 8
36222 // SIMD-ONLY0-NEXT:    br label [[COND_END4323]]
36223 // SIMD-ONLY0:       cond.end4323:
36224 // SIMD-ONLY0-NEXT:    [[COND4324:%.*]] = phi i64 [ [[TMP2324]], [[COND_TRUE4321]] ], [ [[TMP2325]], [[COND_FALSE4322]] ]
36225 // SIMD-ONLY0-NEXT:    store i64 [[COND4324]], ptr [[ULLX]], align 8
36226 // SIMD-ONLY0-NEXT:    [[TMP2326:%.*]] = load i64, ptr [[ULLX]], align 8
36227 // SIMD-ONLY0-NEXT:    [[TMP2327:%.*]] = load i64, ptr [[ULLE]], align 8
36228 // SIMD-ONLY0-NEXT:    [[CMP4325:%.*]] = icmp ugt i64 [[TMP2326]], [[TMP2327]]
36229 // SIMD-ONLY0-NEXT:    br i1 [[CMP4325]], label [[IF_THEN4327:%.*]], label [[IF_END4328:%.*]]
36230 // SIMD-ONLY0:       if.then4327:
36231 // SIMD-ONLY0-NEXT:    [[TMP2328:%.*]] = load i64, ptr [[ULLE]], align 8
36232 // SIMD-ONLY0-NEXT:    store i64 [[TMP2328]], ptr [[ULLX]], align 8
36233 // SIMD-ONLY0-NEXT:    br label [[IF_END4328]]
36234 // SIMD-ONLY0:       if.end4328:
36235 // SIMD-ONLY0-NEXT:    [[TMP2329:%.*]] = load i64, ptr [[ULLX]], align 8
36236 // SIMD-ONLY0-NEXT:    [[TMP2330:%.*]] = load i64, ptr [[ULLE]], align 8
36237 // SIMD-ONLY0-NEXT:    [[CMP4329:%.*]] = icmp ult i64 [[TMP2329]], [[TMP2330]]
36238 // SIMD-ONLY0-NEXT:    br i1 [[CMP4329]], label [[IF_THEN4331:%.*]], label [[IF_END4332:%.*]]
36239 // SIMD-ONLY0:       if.then4331:
36240 // SIMD-ONLY0-NEXT:    [[TMP2331:%.*]] = load i64, ptr [[ULLE]], align 8
36241 // SIMD-ONLY0-NEXT:    store i64 [[TMP2331]], ptr [[ULLX]], align 8
36242 // SIMD-ONLY0-NEXT:    br label [[IF_END4332]]
36243 // SIMD-ONLY0:       if.end4332:
36244 // SIMD-ONLY0-NEXT:    [[TMP2332:%.*]] = load i64, ptr [[ULLE]], align 8
36245 // SIMD-ONLY0-NEXT:    [[TMP2333:%.*]] = load i64, ptr [[ULLX]], align 8
36246 // SIMD-ONLY0-NEXT:    [[CMP4333:%.*]] = icmp ugt i64 [[TMP2332]], [[TMP2333]]
36247 // SIMD-ONLY0-NEXT:    br i1 [[CMP4333]], label [[IF_THEN4335:%.*]], label [[IF_END4336:%.*]]
36248 // SIMD-ONLY0:       if.then4335:
36249 // SIMD-ONLY0-NEXT:    [[TMP2334:%.*]] = load i64, ptr [[ULLE]], align 8
36250 // SIMD-ONLY0-NEXT:    store i64 [[TMP2334]], ptr [[ULLX]], align 8
36251 // SIMD-ONLY0-NEXT:    br label [[IF_END4336]]
36252 // SIMD-ONLY0:       if.end4336:
36253 // SIMD-ONLY0-NEXT:    [[TMP2335:%.*]] = load i64, ptr [[ULLE]], align 8
36254 // SIMD-ONLY0-NEXT:    [[TMP2336:%.*]] = load i64, ptr [[ULLX]], align 8
36255 // SIMD-ONLY0-NEXT:    [[CMP4337:%.*]] = icmp ult i64 [[TMP2335]], [[TMP2336]]
36256 // SIMD-ONLY0-NEXT:    br i1 [[CMP4337]], label [[IF_THEN4339:%.*]], label [[IF_END4340:%.*]]
36257 // SIMD-ONLY0:       if.then4339:
36258 // SIMD-ONLY0-NEXT:    [[TMP2337:%.*]] = load i64, ptr [[ULLE]], align 8
36259 // SIMD-ONLY0-NEXT:    store i64 [[TMP2337]], ptr [[ULLX]], align 8
36260 // SIMD-ONLY0-NEXT:    br label [[IF_END4340]]
36261 // SIMD-ONLY0:       if.end4340:
36262 // SIMD-ONLY0-NEXT:    [[TMP2338:%.*]] = load i64, ptr [[ULLX]], align 8
36263 // SIMD-ONLY0-NEXT:    [[TMP2339:%.*]] = load i64, ptr [[ULLE]], align 8
36264 // SIMD-ONLY0-NEXT:    [[CMP4341:%.*]] = icmp eq i64 [[TMP2338]], [[TMP2339]]
36265 // SIMD-ONLY0-NEXT:    br i1 [[CMP4341]], label [[COND_TRUE4343:%.*]], label [[COND_FALSE4344:%.*]]
36266 // SIMD-ONLY0:       cond.true4343:
36267 // SIMD-ONLY0-NEXT:    [[TMP2340:%.*]] = load i64, ptr [[ULLD]], align 8
36268 // SIMD-ONLY0-NEXT:    br label [[COND_END4345:%.*]]
36269 // SIMD-ONLY0:       cond.false4344:
36270 // SIMD-ONLY0-NEXT:    [[TMP2341:%.*]] = load i64, ptr [[ULLX]], align 8
36271 // SIMD-ONLY0-NEXT:    br label [[COND_END4345]]
36272 // SIMD-ONLY0:       cond.end4345:
36273 // SIMD-ONLY0-NEXT:    [[COND4346:%.*]] = phi i64 [ [[TMP2340]], [[COND_TRUE4343]] ], [ [[TMP2341]], [[COND_FALSE4344]] ]
36274 // SIMD-ONLY0-NEXT:    store i64 [[COND4346]], ptr [[ULLX]], align 8
36275 // SIMD-ONLY0-NEXT:    [[TMP2342:%.*]] = load i64, ptr [[ULLE]], align 8
36276 // SIMD-ONLY0-NEXT:    [[TMP2343:%.*]] = load i64, ptr [[ULLX]], align 8
36277 // SIMD-ONLY0-NEXT:    [[CMP4347:%.*]] = icmp eq i64 [[TMP2342]], [[TMP2343]]
36278 // SIMD-ONLY0-NEXT:    br i1 [[CMP4347]], label [[COND_TRUE4349:%.*]], label [[COND_FALSE4350:%.*]]
36279 // SIMD-ONLY0:       cond.true4349:
36280 // SIMD-ONLY0-NEXT:    [[TMP2344:%.*]] = load i64, ptr [[ULLD]], align 8
36281 // SIMD-ONLY0-NEXT:    br label [[COND_END4351:%.*]]
36282 // SIMD-ONLY0:       cond.false4350:
36283 // SIMD-ONLY0-NEXT:    [[TMP2345:%.*]] = load i64, ptr [[ULLX]], align 8
36284 // SIMD-ONLY0-NEXT:    br label [[COND_END4351]]
36285 // SIMD-ONLY0:       cond.end4351:
36286 // SIMD-ONLY0-NEXT:    [[COND4352:%.*]] = phi i64 [ [[TMP2344]], [[COND_TRUE4349]] ], [ [[TMP2345]], [[COND_FALSE4350]] ]
36287 // SIMD-ONLY0-NEXT:    store i64 [[COND4352]], ptr [[ULLX]], align 8
36288 // SIMD-ONLY0-NEXT:    [[TMP2346:%.*]] = load i64, ptr [[ULLX]], align 8
36289 // SIMD-ONLY0-NEXT:    [[TMP2347:%.*]] = load i64, ptr [[ULLE]], align 8
36290 // SIMD-ONLY0-NEXT:    [[CMP4353:%.*]] = icmp eq i64 [[TMP2346]], [[TMP2347]]
36291 // SIMD-ONLY0-NEXT:    br i1 [[CMP4353]], label [[IF_THEN4355:%.*]], label [[IF_END4356:%.*]]
36292 // SIMD-ONLY0:       if.then4355:
36293 // SIMD-ONLY0-NEXT:    [[TMP2348:%.*]] = load i64, ptr [[ULLD]], align 8
36294 // SIMD-ONLY0-NEXT:    store i64 [[TMP2348]], ptr [[ULLX]], align 8
36295 // SIMD-ONLY0-NEXT:    br label [[IF_END4356]]
36296 // SIMD-ONLY0:       if.end4356:
36297 // SIMD-ONLY0-NEXT:    [[TMP2349:%.*]] = load i64, ptr [[ULLE]], align 8
36298 // SIMD-ONLY0-NEXT:    [[TMP2350:%.*]] = load i64, ptr [[ULLX]], align 8
36299 // SIMD-ONLY0-NEXT:    [[CMP4357:%.*]] = icmp eq i64 [[TMP2349]], [[TMP2350]]
36300 // SIMD-ONLY0-NEXT:    br i1 [[CMP4357]], label [[IF_THEN4359:%.*]], label [[IF_END4360:%.*]]
36301 // SIMD-ONLY0:       if.then4359:
36302 // SIMD-ONLY0-NEXT:    [[TMP2351:%.*]] = load i64, ptr [[ULLD]], align 8
36303 // SIMD-ONLY0-NEXT:    store i64 [[TMP2351]], ptr [[ULLX]], align 8
36304 // SIMD-ONLY0-NEXT:    br label [[IF_END4360]]
36305 // SIMD-ONLY0:       if.end4360:
36306 // SIMD-ONLY0-NEXT:    [[TMP2352:%.*]] = load i64, ptr [[LLX]], align 8
36307 // SIMD-ONLY0-NEXT:    [[TMP2353:%.*]] = load i64, ptr [[LLE]], align 8
36308 // SIMD-ONLY0-NEXT:    [[CMP4361:%.*]] = icmp sgt i64 [[TMP2352]], [[TMP2353]]
36309 // SIMD-ONLY0-NEXT:    br i1 [[CMP4361]], label [[COND_TRUE4363:%.*]], label [[COND_FALSE4364:%.*]]
36310 // SIMD-ONLY0:       cond.true4363:
36311 // SIMD-ONLY0-NEXT:    [[TMP2354:%.*]] = load i64, ptr [[LLE]], align 8
36312 // SIMD-ONLY0-NEXT:    br label [[COND_END4365:%.*]]
36313 // SIMD-ONLY0:       cond.false4364:
36314 // SIMD-ONLY0-NEXT:    [[TMP2355:%.*]] = load i64, ptr [[LLX]], align 8
36315 // SIMD-ONLY0-NEXT:    br label [[COND_END4365]]
36316 // SIMD-ONLY0:       cond.end4365:
36317 // SIMD-ONLY0-NEXT:    [[COND4366:%.*]] = phi i64 [ [[TMP2354]], [[COND_TRUE4363]] ], [ [[TMP2355]], [[COND_FALSE4364]] ]
36318 // SIMD-ONLY0-NEXT:    store i64 [[COND4366]], ptr [[LLX]], align 8
36319 // SIMD-ONLY0-NEXT:    [[TMP2356:%.*]] = load i64, ptr [[LLX]], align 8
36320 // SIMD-ONLY0-NEXT:    [[TMP2357:%.*]] = load i64, ptr [[LLE]], align 8
36321 // SIMD-ONLY0-NEXT:    [[CMP4367:%.*]] = icmp slt i64 [[TMP2356]], [[TMP2357]]
36322 // SIMD-ONLY0-NEXT:    br i1 [[CMP4367]], label [[COND_TRUE4369:%.*]], label [[COND_FALSE4370:%.*]]
36323 // SIMD-ONLY0:       cond.true4369:
36324 // SIMD-ONLY0-NEXT:    [[TMP2358:%.*]] = load i64, ptr [[LLE]], align 8
36325 // SIMD-ONLY0-NEXT:    br label [[COND_END4371:%.*]]
36326 // SIMD-ONLY0:       cond.false4370:
36327 // SIMD-ONLY0-NEXT:    [[TMP2359:%.*]] = load i64, ptr [[LLX]], align 8
36328 // SIMD-ONLY0-NEXT:    br label [[COND_END4371]]
36329 // SIMD-ONLY0:       cond.end4371:
36330 // SIMD-ONLY0-NEXT:    [[COND4372:%.*]] = phi i64 [ [[TMP2358]], [[COND_TRUE4369]] ], [ [[TMP2359]], [[COND_FALSE4370]] ]
36331 // SIMD-ONLY0-NEXT:    store i64 [[COND4372]], ptr [[LLX]], align 8
36332 // SIMD-ONLY0-NEXT:    [[TMP2360:%.*]] = load i64, ptr [[LLE]], align 8
36333 // SIMD-ONLY0-NEXT:    [[TMP2361:%.*]] = load i64, ptr [[LLX]], align 8
36334 // SIMD-ONLY0-NEXT:    [[CMP4373:%.*]] = icmp sgt i64 [[TMP2360]], [[TMP2361]]
36335 // SIMD-ONLY0-NEXT:    br i1 [[CMP4373]], label [[COND_TRUE4375:%.*]], label [[COND_FALSE4376:%.*]]
36336 // SIMD-ONLY0:       cond.true4375:
36337 // SIMD-ONLY0-NEXT:    [[TMP2362:%.*]] = load i64, ptr [[LLE]], align 8
36338 // SIMD-ONLY0-NEXT:    br label [[COND_END4377:%.*]]
36339 // SIMD-ONLY0:       cond.false4376:
36340 // SIMD-ONLY0-NEXT:    [[TMP2363:%.*]] = load i64, ptr [[LLX]], align 8
36341 // SIMD-ONLY0-NEXT:    br label [[COND_END4377]]
36342 // SIMD-ONLY0:       cond.end4377:
36343 // SIMD-ONLY0-NEXT:    [[COND4378:%.*]] = phi i64 [ [[TMP2362]], [[COND_TRUE4375]] ], [ [[TMP2363]], [[COND_FALSE4376]] ]
36344 // SIMD-ONLY0-NEXT:    store i64 [[COND4378]], ptr [[LLX]], align 8
36345 // SIMD-ONLY0-NEXT:    [[TMP2364:%.*]] = load i64, ptr [[LLE]], align 8
36346 // SIMD-ONLY0-NEXT:    [[TMP2365:%.*]] = load i64, ptr [[LLX]], align 8
36347 // SIMD-ONLY0-NEXT:    [[CMP4379:%.*]] = icmp slt i64 [[TMP2364]], [[TMP2365]]
36348 // SIMD-ONLY0-NEXT:    br i1 [[CMP4379]], label [[COND_TRUE4381:%.*]], label [[COND_FALSE4382:%.*]]
36349 // SIMD-ONLY0:       cond.true4381:
36350 // SIMD-ONLY0-NEXT:    [[TMP2366:%.*]] = load i64, ptr [[LLE]], align 8
36351 // SIMD-ONLY0-NEXT:    br label [[COND_END4383:%.*]]
36352 // SIMD-ONLY0:       cond.false4382:
36353 // SIMD-ONLY0-NEXT:    [[TMP2367:%.*]] = load i64, ptr [[LLX]], align 8
36354 // SIMD-ONLY0-NEXT:    br label [[COND_END4383]]
36355 // SIMD-ONLY0:       cond.end4383:
36356 // SIMD-ONLY0-NEXT:    [[COND4384:%.*]] = phi i64 [ [[TMP2366]], [[COND_TRUE4381]] ], [ [[TMP2367]], [[COND_FALSE4382]] ]
36357 // SIMD-ONLY0-NEXT:    store i64 [[COND4384]], ptr [[LLX]], align 8
36358 // SIMD-ONLY0-NEXT:    [[TMP2368:%.*]] = load i64, ptr [[LLX]], align 8
36359 // SIMD-ONLY0-NEXT:    [[TMP2369:%.*]] = load i64, ptr [[LLE]], align 8
36360 // SIMD-ONLY0-NEXT:    [[CMP4385:%.*]] = icmp sgt i64 [[TMP2368]], [[TMP2369]]
36361 // SIMD-ONLY0-NEXT:    br i1 [[CMP4385]], label [[IF_THEN4387:%.*]], label [[IF_END4388:%.*]]
36362 // SIMD-ONLY0:       if.then4387:
36363 // SIMD-ONLY0-NEXT:    [[TMP2370:%.*]] = load i64, ptr [[LLE]], align 8
36364 // SIMD-ONLY0-NEXT:    store i64 [[TMP2370]], ptr [[LLX]], align 8
36365 // SIMD-ONLY0-NEXT:    br label [[IF_END4388]]
36366 // SIMD-ONLY0:       if.end4388:
36367 // SIMD-ONLY0-NEXT:    [[TMP2371:%.*]] = load i64, ptr [[LLX]], align 8
36368 // SIMD-ONLY0-NEXT:    [[TMP2372:%.*]] = load i64, ptr [[LLE]], align 8
36369 // SIMD-ONLY0-NEXT:    [[CMP4389:%.*]] = icmp slt i64 [[TMP2371]], [[TMP2372]]
36370 // SIMD-ONLY0-NEXT:    br i1 [[CMP4389]], label [[IF_THEN4391:%.*]], label [[IF_END4392:%.*]]
36371 // SIMD-ONLY0:       if.then4391:
36372 // SIMD-ONLY0-NEXT:    [[TMP2373:%.*]] = load i64, ptr [[LLE]], align 8
36373 // SIMD-ONLY0-NEXT:    store i64 [[TMP2373]], ptr [[LLX]], align 8
36374 // SIMD-ONLY0-NEXT:    br label [[IF_END4392]]
36375 // SIMD-ONLY0:       if.end4392:
36376 // SIMD-ONLY0-NEXT:    [[TMP2374:%.*]] = load i64, ptr [[LLE]], align 8
36377 // SIMD-ONLY0-NEXT:    [[TMP2375:%.*]] = load i64, ptr [[LLX]], align 8
36378 // SIMD-ONLY0-NEXT:    [[CMP4393:%.*]] = icmp sgt i64 [[TMP2374]], [[TMP2375]]
36379 // SIMD-ONLY0-NEXT:    br i1 [[CMP4393]], label [[IF_THEN4395:%.*]], label [[IF_END4396:%.*]]
36380 // SIMD-ONLY0:       if.then4395:
36381 // SIMD-ONLY0-NEXT:    [[TMP2376:%.*]] = load i64, ptr [[LLE]], align 8
36382 // SIMD-ONLY0-NEXT:    store i64 [[TMP2376]], ptr [[LLX]], align 8
36383 // SIMD-ONLY0-NEXT:    br label [[IF_END4396]]
36384 // SIMD-ONLY0:       if.end4396:
36385 // SIMD-ONLY0-NEXT:    [[TMP2377:%.*]] = load i64, ptr [[LLE]], align 8
36386 // SIMD-ONLY0-NEXT:    [[TMP2378:%.*]] = load i64, ptr [[LLX]], align 8
36387 // SIMD-ONLY0-NEXT:    [[CMP4397:%.*]] = icmp slt i64 [[TMP2377]], [[TMP2378]]
36388 // SIMD-ONLY0-NEXT:    br i1 [[CMP4397]], label [[IF_THEN4399:%.*]], label [[IF_END4400:%.*]]
36389 // SIMD-ONLY0:       if.then4399:
36390 // SIMD-ONLY0-NEXT:    [[TMP2379:%.*]] = load i64, ptr [[LLE]], align 8
36391 // SIMD-ONLY0-NEXT:    store i64 [[TMP2379]], ptr [[LLX]], align 8
36392 // SIMD-ONLY0-NEXT:    br label [[IF_END4400]]
36393 // SIMD-ONLY0:       if.end4400:
36394 // SIMD-ONLY0-NEXT:    [[TMP2380:%.*]] = load i64, ptr [[LLX]], align 8
36395 // SIMD-ONLY0-NEXT:    [[TMP2381:%.*]] = load i64, ptr [[LLE]], align 8
36396 // SIMD-ONLY0-NEXT:    [[CMP4401:%.*]] = icmp eq i64 [[TMP2380]], [[TMP2381]]
36397 // SIMD-ONLY0-NEXT:    br i1 [[CMP4401]], label [[COND_TRUE4403:%.*]], label [[COND_FALSE4404:%.*]]
36398 // SIMD-ONLY0:       cond.true4403:
36399 // SIMD-ONLY0-NEXT:    [[TMP2382:%.*]] = load i64, ptr [[LLD]], align 8
36400 // SIMD-ONLY0-NEXT:    br label [[COND_END4405:%.*]]
36401 // SIMD-ONLY0:       cond.false4404:
36402 // SIMD-ONLY0-NEXT:    [[TMP2383:%.*]] = load i64, ptr [[LLX]], align 8
36403 // SIMD-ONLY0-NEXT:    br label [[COND_END4405]]
36404 // SIMD-ONLY0:       cond.end4405:
36405 // SIMD-ONLY0-NEXT:    [[COND4406:%.*]] = phi i64 [ [[TMP2382]], [[COND_TRUE4403]] ], [ [[TMP2383]], [[COND_FALSE4404]] ]
36406 // SIMD-ONLY0-NEXT:    store i64 [[COND4406]], ptr [[LLX]], align 8
36407 // SIMD-ONLY0-NEXT:    [[TMP2384:%.*]] = load i64, ptr [[LLE]], align 8
36408 // SIMD-ONLY0-NEXT:    [[TMP2385:%.*]] = load i64, ptr [[LLX]], align 8
36409 // SIMD-ONLY0-NEXT:    [[CMP4407:%.*]] = icmp eq i64 [[TMP2384]], [[TMP2385]]
36410 // SIMD-ONLY0-NEXT:    br i1 [[CMP4407]], label [[COND_TRUE4409:%.*]], label [[COND_FALSE4410:%.*]]
36411 // SIMD-ONLY0:       cond.true4409:
36412 // SIMD-ONLY0-NEXT:    [[TMP2386:%.*]] = load i64, ptr [[LLD]], align 8
36413 // SIMD-ONLY0-NEXT:    br label [[COND_END4411:%.*]]
36414 // SIMD-ONLY0:       cond.false4410:
36415 // SIMD-ONLY0-NEXT:    [[TMP2387:%.*]] = load i64, ptr [[LLX]], align 8
36416 // SIMD-ONLY0-NEXT:    br label [[COND_END4411]]
36417 // SIMD-ONLY0:       cond.end4411:
36418 // SIMD-ONLY0-NEXT:    [[COND4412:%.*]] = phi i64 [ [[TMP2386]], [[COND_TRUE4409]] ], [ [[TMP2387]], [[COND_FALSE4410]] ]
36419 // SIMD-ONLY0-NEXT:    store i64 [[COND4412]], ptr [[LLX]], align 8
36420 // SIMD-ONLY0-NEXT:    [[TMP2388:%.*]] = load i64, ptr [[LLX]], align 8
36421 // SIMD-ONLY0-NEXT:    [[TMP2389:%.*]] = load i64, ptr [[LLE]], align 8
36422 // SIMD-ONLY0-NEXT:    [[CMP4413:%.*]] = icmp eq i64 [[TMP2388]], [[TMP2389]]
36423 // SIMD-ONLY0-NEXT:    br i1 [[CMP4413]], label [[IF_THEN4415:%.*]], label [[IF_END4416:%.*]]
36424 // SIMD-ONLY0:       if.then4415:
36425 // SIMD-ONLY0-NEXT:    [[TMP2390:%.*]] = load i64, ptr [[LLD]], align 8
36426 // SIMD-ONLY0-NEXT:    store i64 [[TMP2390]], ptr [[LLX]], align 8
36427 // SIMD-ONLY0-NEXT:    br label [[IF_END4416]]
36428 // SIMD-ONLY0:       if.end4416:
36429 // SIMD-ONLY0-NEXT:    [[TMP2391:%.*]] = load i64, ptr [[LLE]], align 8
36430 // SIMD-ONLY0-NEXT:    [[TMP2392:%.*]] = load i64, ptr [[LLX]], align 8
36431 // SIMD-ONLY0-NEXT:    [[CMP4417:%.*]] = icmp eq i64 [[TMP2391]], [[TMP2392]]
36432 // SIMD-ONLY0-NEXT:    br i1 [[CMP4417]], label [[IF_THEN4419:%.*]], label [[IF_END4420:%.*]]
36433 // SIMD-ONLY0:       if.then4419:
36434 // SIMD-ONLY0-NEXT:    [[TMP2393:%.*]] = load i64, ptr [[LLD]], align 8
36435 // SIMD-ONLY0-NEXT:    store i64 [[TMP2393]], ptr [[LLX]], align 8
36436 // SIMD-ONLY0-NEXT:    br label [[IF_END4420]]
36437 // SIMD-ONLY0:       if.end4420:
36438 // SIMD-ONLY0-NEXT:    [[TMP2394:%.*]] = load i64, ptr [[ULLX]], align 8
36439 // SIMD-ONLY0-NEXT:    [[TMP2395:%.*]] = load i64, ptr [[ULLE]], align 8
36440 // SIMD-ONLY0-NEXT:    [[CMP4421:%.*]] = icmp ugt i64 [[TMP2394]], [[TMP2395]]
36441 // SIMD-ONLY0-NEXT:    br i1 [[CMP4421]], label [[COND_TRUE4423:%.*]], label [[COND_FALSE4424:%.*]]
36442 // SIMD-ONLY0:       cond.true4423:
36443 // SIMD-ONLY0-NEXT:    [[TMP2396:%.*]] = load i64, ptr [[ULLE]], align 8
36444 // SIMD-ONLY0-NEXT:    br label [[COND_END4425:%.*]]
36445 // SIMD-ONLY0:       cond.false4424:
36446 // SIMD-ONLY0-NEXT:    [[TMP2397:%.*]] = load i64, ptr [[ULLX]], align 8
36447 // SIMD-ONLY0-NEXT:    br label [[COND_END4425]]
36448 // SIMD-ONLY0:       cond.end4425:
36449 // SIMD-ONLY0-NEXT:    [[COND4426:%.*]] = phi i64 [ [[TMP2396]], [[COND_TRUE4423]] ], [ [[TMP2397]], [[COND_FALSE4424]] ]
36450 // SIMD-ONLY0-NEXT:    store i64 [[COND4426]], ptr [[ULLX]], align 8
36451 // SIMD-ONLY0-NEXT:    [[TMP2398:%.*]] = load i64, ptr [[ULLX]], align 8
36452 // SIMD-ONLY0-NEXT:    [[TMP2399:%.*]] = load i64, ptr [[ULLE]], align 8
36453 // SIMD-ONLY0-NEXT:    [[CMP4427:%.*]] = icmp ult i64 [[TMP2398]], [[TMP2399]]
36454 // SIMD-ONLY0-NEXT:    br i1 [[CMP4427]], label [[COND_TRUE4429:%.*]], label [[COND_FALSE4430:%.*]]
36455 // SIMD-ONLY0:       cond.true4429:
36456 // SIMD-ONLY0-NEXT:    [[TMP2400:%.*]] = load i64, ptr [[ULLE]], align 8
36457 // SIMD-ONLY0-NEXT:    br label [[COND_END4431:%.*]]
36458 // SIMD-ONLY0:       cond.false4430:
36459 // SIMD-ONLY0-NEXT:    [[TMP2401:%.*]] = load i64, ptr [[ULLX]], align 8
36460 // SIMD-ONLY0-NEXT:    br label [[COND_END4431]]
36461 // SIMD-ONLY0:       cond.end4431:
36462 // SIMD-ONLY0-NEXT:    [[COND4432:%.*]] = phi i64 [ [[TMP2400]], [[COND_TRUE4429]] ], [ [[TMP2401]], [[COND_FALSE4430]] ]
36463 // SIMD-ONLY0-NEXT:    store i64 [[COND4432]], ptr [[ULLX]], align 8
36464 // SIMD-ONLY0-NEXT:    [[TMP2402:%.*]] = load i64, ptr [[ULLE]], align 8
36465 // SIMD-ONLY0-NEXT:    [[TMP2403:%.*]] = load i64, ptr [[ULLX]], align 8
36466 // SIMD-ONLY0-NEXT:    [[CMP4433:%.*]] = icmp ugt i64 [[TMP2402]], [[TMP2403]]
36467 // SIMD-ONLY0-NEXT:    br i1 [[CMP4433]], label [[COND_TRUE4435:%.*]], label [[COND_FALSE4436:%.*]]
36468 // SIMD-ONLY0:       cond.true4435:
36469 // SIMD-ONLY0-NEXT:    [[TMP2404:%.*]] = load i64, ptr [[ULLE]], align 8
36470 // SIMD-ONLY0-NEXT:    br label [[COND_END4437:%.*]]
36471 // SIMD-ONLY0:       cond.false4436:
36472 // SIMD-ONLY0-NEXT:    [[TMP2405:%.*]] = load i64, ptr [[ULLX]], align 8
36473 // SIMD-ONLY0-NEXT:    br label [[COND_END4437]]
36474 // SIMD-ONLY0:       cond.end4437:
36475 // SIMD-ONLY0-NEXT:    [[COND4438:%.*]] = phi i64 [ [[TMP2404]], [[COND_TRUE4435]] ], [ [[TMP2405]], [[COND_FALSE4436]] ]
36476 // SIMD-ONLY0-NEXT:    store i64 [[COND4438]], ptr [[ULLX]], align 8
36477 // SIMD-ONLY0-NEXT:    [[TMP2406:%.*]] = load i64, ptr [[ULLE]], align 8
36478 // SIMD-ONLY0-NEXT:    [[TMP2407:%.*]] = load i64, ptr [[ULLX]], align 8
36479 // SIMD-ONLY0-NEXT:    [[CMP4439:%.*]] = icmp ult i64 [[TMP2406]], [[TMP2407]]
36480 // SIMD-ONLY0-NEXT:    br i1 [[CMP4439]], label [[COND_TRUE4441:%.*]], label [[COND_FALSE4442:%.*]]
36481 // SIMD-ONLY0:       cond.true4441:
36482 // SIMD-ONLY0-NEXT:    [[TMP2408:%.*]] = load i64, ptr [[ULLE]], align 8
36483 // SIMD-ONLY0-NEXT:    br label [[COND_END4443:%.*]]
36484 // SIMD-ONLY0:       cond.false4442:
36485 // SIMD-ONLY0-NEXT:    [[TMP2409:%.*]] = load i64, ptr [[ULLX]], align 8
36486 // SIMD-ONLY0-NEXT:    br label [[COND_END4443]]
36487 // SIMD-ONLY0:       cond.end4443:
36488 // SIMD-ONLY0-NEXT:    [[COND4444:%.*]] = phi i64 [ [[TMP2408]], [[COND_TRUE4441]] ], [ [[TMP2409]], [[COND_FALSE4442]] ]
36489 // SIMD-ONLY0-NEXT:    store i64 [[COND4444]], ptr [[ULLX]], align 8
36490 // SIMD-ONLY0-NEXT:    [[TMP2410:%.*]] = load i64, ptr [[ULLX]], align 8
36491 // SIMD-ONLY0-NEXT:    [[TMP2411:%.*]] = load i64, ptr [[ULLE]], align 8
36492 // SIMD-ONLY0-NEXT:    [[CMP4445:%.*]] = icmp ugt i64 [[TMP2410]], [[TMP2411]]
36493 // SIMD-ONLY0-NEXT:    br i1 [[CMP4445]], label [[IF_THEN4447:%.*]], label [[IF_END4448:%.*]]
36494 // SIMD-ONLY0:       if.then4447:
36495 // SIMD-ONLY0-NEXT:    [[TMP2412:%.*]] = load i64, ptr [[ULLE]], align 8
36496 // SIMD-ONLY0-NEXT:    store i64 [[TMP2412]], ptr [[ULLX]], align 8
36497 // SIMD-ONLY0-NEXT:    br label [[IF_END4448]]
36498 // SIMD-ONLY0:       if.end4448:
36499 // SIMD-ONLY0-NEXT:    [[TMP2413:%.*]] = load i64, ptr [[ULLX]], align 8
36500 // SIMD-ONLY0-NEXT:    [[TMP2414:%.*]] = load i64, ptr [[ULLE]], align 8
36501 // SIMD-ONLY0-NEXT:    [[CMP4449:%.*]] = icmp ult i64 [[TMP2413]], [[TMP2414]]
36502 // SIMD-ONLY0-NEXT:    br i1 [[CMP4449]], label [[IF_THEN4451:%.*]], label [[IF_END4452:%.*]]
36503 // SIMD-ONLY0:       if.then4451:
36504 // SIMD-ONLY0-NEXT:    [[TMP2415:%.*]] = load i64, ptr [[ULLE]], align 8
36505 // SIMD-ONLY0-NEXT:    store i64 [[TMP2415]], ptr [[ULLX]], align 8
36506 // SIMD-ONLY0-NEXT:    br label [[IF_END4452]]
36507 // SIMD-ONLY0:       if.end4452:
36508 // SIMD-ONLY0-NEXT:    [[TMP2416:%.*]] = load i64, ptr [[ULLE]], align 8
36509 // SIMD-ONLY0-NEXT:    [[TMP2417:%.*]] = load i64, ptr [[ULLX]], align 8
36510 // SIMD-ONLY0-NEXT:    [[CMP4453:%.*]] = icmp ugt i64 [[TMP2416]], [[TMP2417]]
36511 // SIMD-ONLY0-NEXT:    br i1 [[CMP4453]], label [[IF_THEN4455:%.*]], label [[IF_END4456:%.*]]
36512 // SIMD-ONLY0:       if.then4455:
36513 // SIMD-ONLY0-NEXT:    [[TMP2418:%.*]] = load i64, ptr [[ULLE]], align 8
36514 // SIMD-ONLY0-NEXT:    store i64 [[TMP2418]], ptr [[ULLX]], align 8
36515 // SIMD-ONLY0-NEXT:    br label [[IF_END4456]]
36516 // SIMD-ONLY0:       if.end4456:
36517 // SIMD-ONLY0-NEXT:    [[TMP2419:%.*]] = load i64, ptr [[ULLE]], align 8
36518 // SIMD-ONLY0-NEXT:    [[TMP2420:%.*]] = load i64, ptr [[ULLX]], align 8
36519 // SIMD-ONLY0-NEXT:    [[CMP4457:%.*]] = icmp ult i64 [[TMP2419]], [[TMP2420]]
36520 // SIMD-ONLY0-NEXT:    br i1 [[CMP4457]], label [[IF_THEN4459:%.*]], label [[IF_END4460:%.*]]
36521 // SIMD-ONLY0:       if.then4459:
36522 // SIMD-ONLY0-NEXT:    [[TMP2421:%.*]] = load i64, ptr [[ULLE]], align 8
36523 // SIMD-ONLY0-NEXT:    store i64 [[TMP2421]], ptr [[ULLX]], align 8
36524 // SIMD-ONLY0-NEXT:    br label [[IF_END4460]]
36525 // SIMD-ONLY0:       if.end4460:
36526 // SIMD-ONLY0-NEXT:    [[TMP2422:%.*]] = load i64, ptr [[ULLX]], align 8
36527 // SIMD-ONLY0-NEXT:    [[TMP2423:%.*]] = load i64, ptr [[ULLE]], align 8
36528 // SIMD-ONLY0-NEXT:    [[CMP4461:%.*]] = icmp eq i64 [[TMP2422]], [[TMP2423]]
36529 // SIMD-ONLY0-NEXT:    br i1 [[CMP4461]], label [[COND_TRUE4463:%.*]], label [[COND_FALSE4464:%.*]]
36530 // SIMD-ONLY0:       cond.true4463:
36531 // SIMD-ONLY0-NEXT:    [[TMP2424:%.*]] = load i64, ptr [[ULLD]], align 8
36532 // SIMD-ONLY0-NEXT:    br label [[COND_END4465:%.*]]
36533 // SIMD-ONLY0:       cond.false4464:
36534 // SIMD-ONLY0-NEXT:    [[TMP2425:%.*]] = load i64, ptr [[ULLX]], align 8
36535 // SIMD-ONLY0-NEXT:    br label [[COND_END4465]]
36536 // SIMD-ONLY0:       cond.end4465:
36537 // SIMD-ONLY0-NEXT:    [[COND4466:%.*]] = phi i64 [ [[TMP2424]], [[COND_TRUE4463]] ], [ [[TMP2425]], [[COND_FALSE4464]] ]
36538 // SIMD-ONLY0-NEXT:    store i64 [[COND4466]], ptr [[ULLX]], align 8
36539 // SIMD-ONLY0-NEXT:    [[TMP2426:%.*]] = load i64, ptr [[ULLE]], align 8
36540 // SIMD-ONLY0-NEXT:    [[TMP2427:%.*]] = load i64, ptr [[ULLX]], align 8
36541 // SIMD-ONLY0-NEXT:    [[CMP4467:%.*]] = icmp eq i64 [[TMP2426]], [[TMP2427]]
36542 // SIMD-ONLY0-NEXT:    br i1 [[CMP4467]], label [[COND_TRUE4469:%.*]], label [[COND_FALSE4470:%.*]]
36543 // SIMD-ONLY0:       cond.true4469:
36544 // SIMD-ONLY0-NEXT:    [[TMP2428:%.*]] = load i64, ptr [[ULLD]], align 8
36545 // SIMD-ONLY0-NEXT:    br label [[COND_END4471:%.*]]
36546 // SIMD-ONLY0:       cond.false4470:
36547 // SIMD-ONLY0-NEXT:    [[TMP2429:%.*]] = load i64, ptr [[ULLX]], align 8
36548 // SIMD-ONLY0-NEXT:    br label [[COND_END4471]]
36549 // SIMD-ONLY0:       cond.end4471:
36550 // SIMD-ONLY0-NEXT:    [[COND4472:%.*]] = phi i64 [ [[TMP2428]], [[COND_TRUE4469]] ], [ [[TMP2429]], [[COND_FALSE4470]] ]
36551 // SIMD-ONLY0-NEXT:    store i64 [[COND4472]], ptr [[ULLX]], align 8
36552 // SIMD-ONLY0-NEXT:    [[TMP2430:%.*]] = load i64, ptr [[ULLX]], align 8
36553 // SIMD-ONLY0-NEXT:    [[TMP2431:%.*]] = load i64, ptr [[ULLE]], align 8
36554 // SIMD-ONLY0-NEXT:    [[CMP4473:%.*]] = icmp eq i64 [[TMP2430]], [[TMP2431]]
36555 // SIMD-ONLY0-NEXT:    br i1 [[CMP4473]], label [[IF_THEN4475:%.*]], label [[IF_END4476:%.*]]
36556 // SIMD-ONLY0:       if.then4475:
36557 // SIMD-ONLY0-NEXT:    [[TMP2432:%.*]] = load i64, ptr [[ULLD]], align 8
36558 // SIMD-ONLY0-NEXT:    store i64 [[TMP2432]], ptr [[ULLX]], align 8
36559 // SIMD-ONLY0-NEXT:    br label [[IF_END4476]]
36560 // SIMD-ONLY0:       if.end4476:
36561 // SIMD-ONLY0-NEXT:    [[TMP2433:%.*]] = load i64, ptr [[ULLE]], align 8
36562 // SIMD-ONLY0-NEXT:    [[TMP2434:%.*]] = load i64, ptr [[ULLX]], align 8
36563 // SIMD-ONLY0-NEXT:    [[CMP4477:%.*]] = icmp eq i64 [[TMP2433]], [[TMP2434]]
36564 // SIMD-ONLY0-NEXT:    br i1 [[CMP4477]], label [[IF_THEN4479:%.*]], label [[IF_END4480:%.*]]
36565 // SIMD-ONLY0:       if.then4479:
36566 // SIMD-ONLY0-NEXT:    [[TMP2435:%.*]] = load i64, ptr [[ULLD]], align 8
36567 // SIMD-ONLY0-NEXT:    store i64 [[TMP2435]], ptr [[ULLX]], align 8
36568 // SIMD-ONLY0-NEXT:    br label [[IF_END4480]]
36569 // SIMD-ONLY0:       if.end4480:
36570 // SIMD-ONLY0-NEXT:    [[TMP2436:%.*]] = load i64, ptr [[LLX]], align 8
36571 // SIMD-ONLY0-NEXT:    [[TMP2437:%.*]] = load i64, ptr [[LLE]], align 8
36572 // SIMD-ONLY0-NEXT:    [[CMP4481:%.*]] = icmp sgt i64 [[TMP2436]], [[TMP2437]]
36573 // SIMD-ONLY0-NEXT:    br i1 [[CMP4481]], label [[COND_TRUE4483:%.*]], label [[COND_FALSE4484:%.*]]
36574 // SIMD-ONLY0:       cond.true4483:
36575 // SIMD-ONLY0-NEXT:    [[TMP2438:%.*]] = load i64, ptr [[LLE]], align 8
36576 // SIMD-ONLY0-NEXT:    br label [[COND_END4485:%.*]]
36577 // SIMD-ONLY0:       cond.false4484:
36578 // SIMD-ONLY0-NEXT:    [[TMP2439:%.*]] = load i64, ptr [[LLX]], align 8
36579 // SIMD-ONLY0-NEXT:    br label [[COND_END4485]]
36580 // SIMD-ONLY0:       cond.end4485:
36581 // SIMD-ONLY0-NEXT:    [[COND4486:%.*]] = phi i64 [ [[TMP2438]], [[COND_TRUE4483]] ], [ [[TMP2439]], [[COND_FALSE4484]] ]
36582 // SIMD-ONLY0-NEXT:    store i64 [[COND4486]], ptr [[LLX]], align 8
36583 // SIMD-ONLY0-NEXT:    [[TMP2440:%.*]] = load i64, ptr [[LLX]], align 8
36584 // SIMD-ONLY0-NEXT:    [[TMP2441:%.*]] = load i64, ptr [[LLE]], align 8
36585 // SIMD-ONLY0-NEXT:    [[CMP4487:%.*]] = icmp slt i64 [[TMP2440]], [[TMP2441]]
36586 // SIMD-ONLY0-NEXT:    br i1 [[CMP4487]], label [[COND_TRUE4489:%.*]], label [[COND_FALSE4490:%.*]]
36587 // SIMD-ONLY0:       cond.true4489:
36588 // SIMD-ONLY0-NEXT:    [[TMP2442:%.*]] = load i64, ptr [[LLE]], align 8
36589 // SIMD-ONLY0-NEXT:    br label [[COND_END4491:%.*]]
36590 // SIMD-ONLY0:       cond.false4490:
36591 // SIMD-ONLY0-NEXT:    [[TMP2443:%.*]] = load i64, ptr [[LLX]], align 8
36592 // SIMD-ONLY0-NEXT:    br label [[COND_END4491]]
36593 // SIMD-ONLY0:       cond.end4491:
36594 // SIMD-ONLY0-NEXT:    [[COND4492:%.*]] = phi i64 [ [[TMP2442]], [[COND_TRUE4489]] ], [ [[TMP2443]], [[COND_FALSE4490]] ]
36595 // SIMD-ONLY0-NEXT:    store i64 [[COND4492]], ptr [[LLX]], align 8
36596 // SIMD-ONLY0-NEXT:    [[TMP2444:%.*]] = load i64, ptr [[LLE]], align 8
36597 // SIMD-ONLY0-NEXT:    [[TMP2445:%.*]] = load i64, ptr [[LLX]], align 8
36598 // SIMD-ONLY0-NEXT:    [[CMP4493:%.*]] = icmp sgt i64 [[TMP2444]], [[TMP2445]]
36599 // SIMD-ONLY0-NEXT:    br i1 [[CMP4493]], label [[COND_TRUE4495:%.*]], label [[COND_FALSE4496:%.*]]
36600 // SIMD-ONLY0:       cond.true4495:
36601 // SIMD-ONLY0-NEXT:    [[TMP2446:%.*]] = load i64, ptr [[LLE]], align 8
36602 // SIMD-ONLY0-NEXT:    br label [[COND_END4497:%.*]]
36603 // SIMD-ONLY0:       cond.false4496:
36604 // SIMD-ONLY0-NEXT:    [[TMP2447:%.*]] = load i64, ptr [[LLX]], align 8
36605 // SIMD-ONLY0-NEXT:    br label [[COND_END4497]]
36606 // SIMD-ONLY0:       cond.end4497:
36607 // SIMD-ONLY0-NEXT:    [[COND4498:%.*]] = phi i64 [ [[TMP2446]], [[COND_TRUE4495]] ], [ [[TMP2447]], [[COND_FALSE4496]] ]
36608 // SIMD-ONLY0-NEXT:    store i64 [[COND4498]], ptr [[LLX]], align 8
36609 // SIMD-ONLY0-NEXT:    [[TMP2448:%.*]] = load i64, ptr [[LLE]], align 8
36610 // SIMD-ONLY0-NEXT:    [[TMP2449:%.*]] = load i64, ptr [[LLX]], align 8
36611 // SIMD-ONLY0-NEXT:    [[CMP4499:%.*]] = icmp slt i64 [[TMP2448]], [[TMP2449]]
36612 // SIMD-ONLY0-NEXT:    br i1 [[CMP4499]], label [[COND_TRUE4501:%.*]], label [[COND_FALSE4502:%.*]]
36613 // SIMD-ONLY0:       cond.true4501:
36614 // SIMD-ONLY0-NEXT:    [[TMP2450:%.*]] = load i64, ptr [[LLE]], align 8
36615 // SIMD-ONLY0-NEXT:    br label [[COND_END4503:%.*]]
36616 // SIMD-ONLY0:       cond.false4502:
36617 // SIMD-ONLY0-NEXT:    [[TMP2451:%.*]] = load i64, ptr [[LLX]], align 8
36618 // SIMD-ONLY0-NEXT:    br label [[COND_END4503]]
36619 // SIMD-ONLY0:       cond.end4503:
36620 // SIMD-ONLY0-NEXT:    [[COND4504:%.*]] = phi i64 [ [[TMP2450]], [[COND_TRUE4501]] ], [ [[TMP2451]], [[COND_FALSE4502]] ]
36621 // SIMD-ONLY0-NEXT:    store i64 [[COND4504]], ptr [[LLX]], align 8
36622 // SIMD-ONLY0-NEXT:    [[TMP2452:%.*]] = load i64, ptr [[LLX]], align 8
36623 // SIMD-ONLY0-NEXT:    [[TMP2453:%.*]] = load i64, ptr [[LLE]], align 8
36624 // SIMD-ONLY0-NEXT:    [[CMP4505:%.*]] = icmp sgt i64 [[TMP2452]], [[TMP2453]]
36625 // SIMD-ONLY0-NEXT:    br i1 [[CMP4505]], label [[IF_THEN4507:%.*]], label [[IF_END4508:%.*]]
36626 // SIMD-ONLY0:       if.then4507:
36627 // SIMD-ONLY0-NEXT:    [[TMP2454:%.*]] = load i64, ptr [[LLE]], align 8
36628 // SIMD-ONLY0-NEXT:    store i64 [[TMP2454]], ptr [[LLX]], align 8
36629 // SIMD-ONLY0-NEXT:    br label [[IF_END4508]]
36630 // SIMD-ONLY0:       if.end4508:
36631 // SIMD-ONLY0-NEXT:    [[TMP2455:%.*]] = load i64, ptr [[LLX]], align 8
36632 // SIMD-ONLY0-NEXT:    [[TMP2456:%.*]] = load i64, ptr [[LLE]], align 8
36633 // SIMD-ONLY0-NEXT:    [[CMP4509:%.*]] = icmp slt i64 [[TMP2455]], [[TMP2456]]
36634 // SIMD-ONLY0-NEXT:    br i1 [[CMP4509]], label [[IF_THEN4511:%.*]], label [[IF_END4512:%.*]]
36635 // SIMD-ONLY0:       if.then4511:
36636 // SIMD-ONLY0-NEXT:    [[TMP2457:%.*]] = load i64, ptr [[LLE]], align 8
36637 // SIMD-ONLY0-NEXT:    store i64 [[TMP2457]], ptr [[LLX]], align 8
36638 // SIMD-ONLY0-NEXT:    br label [[IF_END4512]]
36639 // SIMD-ONLY0:       if.end4512:
36640 // SIMD-ONLY0-NEXT:    [[TMP2458:%.*]] = load i64, ptr [[LLE]], align 8
36641 // SIMD-ONLY0-NEXT:    [[TMP2459:%.*]] = load i64, ptr [[LLX]], align 8
36642 // SIMD-ONLY0-NEXT:    [[CMP4513:%.*]] = icmp sgt i64 [[TMP2458]], [[TMP2459]]
36643 // SIMD-ONLY0-NEXT:    br i1 [[CMP4513]], label [[IF_THEN4515:%.*]], label [[IF_END4516:%.*]]
36644 // SIMD-ONLY0:       if.then4515:
36645 // SIMD-ONLY0-NEXT:    [[TMP2460:%.*]] = load i64, ptr [[LLE]], align 8
36646 // SIMD-ONLY0-NEXT:    store i64 [[TMP2460]], ptr [[LLX]], align 8
36647 // SIMD-ONLY0-NEXT:    br label [[IF_END4516]]
36648 // SIMD-ONLY0:       if.end4516:
36649 // SIMD-ONLY0-NEXT:    [[TMP2461:%.*]] = load i64, ptr [[LLE]], align 8
36650 // SIMD-ONLY0-NEXT:    [[TMP2462:%.*]] = load i64, ptr [[LLX]], align 8
36651 // SIMD-ONLY0-NEXT:    [[CMP4517:%.*]] = icmp slt i64 [[TMP2461]], [[TMP2462]]
36652 // SIMD-ONLY0-NEXT:    br i1 [[CMP4517]], label [[IF_THEN4519:%.*]], label [[IF_END4520:%.*]]
36653 // SIMD-ONLY0:       if.then4519:
36654 // SIMD-ONLY0-NEXT:    [[TMP2463:%.*]] = load i64, ptr [[LLE]], align 8
36655 // SIMD-ONLY0-NEXT:    store i64 [[TMP2463]], ptr [[LLX]], align 8
36656 // SIMD-ONLY0-NEXT:    br label [[IF_END4520]]
36657 // SIMD-ONLY0:       if.end4520:
36658 // SIMD-ONLY0-NEXT:    [[TMP2464:%.*]] = load i64, ptr [[LLX]], align 8
36659 // SIMD-ONLY0-NEXT:    [[TMP2465:%.*]] = load i64, ptr [[LLE]], align 8
36660 // SIMD-ONLY0-NEXT:    [[CMP4521:%.*]] = icmp eq i64 [[TMP2464]], [[TMP2465]]
36661 // SIMD-ONLY0-NEXT:    br i1 [[CMP4521]], label [[COND_TRUE4523:%.*]], label [[COND_FALSE4524:%.*]]
36662 // SIMD-ONLY0:       cond.true4523:
36663 // SIMD-ONLY0-NEXT:    [[TMP2466:%.*]] = load i64, ptr [[LLD]], align 8
36664 // SIMD-ONLY0-NEXT:    br label [[COND_END4525:%.*]]
36665 // SIMD-ONLY0:       cond.false4524:
36666 // SIMD-ONLY0-NEXT:    [[TMP2467:%.*]] = load i64, ptr [[LLX]], align 8
36667 // SIMD-ONLY0-NEXT:    br label [[COND_END4525]]
36668 // SIMD-ONLY0:       cond.end4525:
36669 // SIMD-ONLY0-NEXT:    [[COND4526:%.*]] = phi i64 [ [[TMP2466]], [[COND_TRUE4523]] ], [ [[TMP2467]], [[COND_FALSE4524]] ]
36670 // SIMD-ONLY0-NEXT:    store i64 [[COND4526]], ptr [[LLX]], align 8
36671 // SIMD-ONLY0-NEXT:    [[TMP2468:%.*]] = load i64, ptr [[LLE]], align 8
36672 // SIMD-ONLY0-NEXT:    [[TMP2469:%.*]] = load i64, ptr [[LLX]], align 8
36673 // SIMD-ONLY0-NEXT:    [[CMP4527:%.*]] = icmp eq i64 [[TMP2468]], [[TMP2469]]
36674 // SIMD-ONLY0-NEXT:    br i1 [[CMP4527]], label [[COND_TRUE4529:%.*]], label [[COND_FALSE4530:%.*]]
36675 // SIMD-ONLY0:       cond.true4529:
36676 // SIMD-ONLY0-NEXT:    [[TMP2470:%.*]] = load i64, ptr [[LLD]], align 8
36677 // SIMD-ONLY0-NEXT:    br label [[COND_END4531:%.*]]
36678 // SIMD-ONLY0:       cond.false4530:
36679 // SIMD-ONLY0-NEXT:    [[TMP2471:%.*]] = load i64, ptr [[LLX]], align 8
36680 // SIMD-ONLY0-NEXT:    br label [[COND_END4531]]
36681 // SIMD-ONLY0:       cond.end4531:
36682 // SIMD-ONLY0-NEXT:    [[COND4532:%.*]] = phi i64 [ [[TMP2470]], [[COND_TRUE4529]] ], [ [[TMP2471]], [[COND_FALSE4530]] ]
36683 // SIMD-ONLY0-NEXT:    store i64 [[COND4532]], ptr [[LLX]], align 8
36684 // SIMD-ONLY0-NEXT:    [[TMP2472:%.*]] = load i64, ptr [[LLX]], align 8
36685 // SIMD-ONLY0-NEXT:    [[TMP2473:%.*]] = load i64, ptr [[LLE]], align 8
36686 // SIMD-ONLY0-NEXT:    [[CMP4533:%.*]] = icmp eq i64 [[TMP2472]], [[TMP2473]]
36687 // SIMD-ONLY0-NEXT:    br i1 [[CMP4533]], label [[IF_THEN4535:%.*]], label [[IF_END4536:%.*]]
36688 // SIMD-ONLY0:       if.then4535:
36689 // SIMD-ONLY0-NEXT:    [[TMP2474:%.*]] = load i64, ptr [[LLD]], align 8
36690 // SIMD-ONLY0-NEXT:    store i64 [[TMP2474]], ptr [[LLX]], align 8
36691 // SIMD-ONLY0-NEXT:    br label [[IF_END4536]]
36692 // SIMD-ONLY0:       if.end4536:
36693 // SIMD-ONLY0-NEXT:    [[TMP2475:%.*]] = load i64, ptr [[LLE]], align 8
36694 // SIMD-ONLY0-NEXT:    [[TMP2476:%.*]] = load i64, ptr [[LLX]], align 8
36695 // SIMD-ONLY0-NEXT:    [[CMP4537:%.*]] = icmp eq i64 [[TMP2475]], [[TMP2476]]
36696 // SIMD-ONLY0-NEXT:    br i1 [[CMP4537]], label [[IF_THEN4539:%.*]], label [[IF_END4540:%.*]]
36697 // SIMD-ONLY0:       if.then4539:
36698 // SIMD-ONLY0-NEXT:    [[TMP2477:%.*]] = load i64, ptr [[LLD]], align 8
36699 // SIMD-ONLY0-NEXT:    store i64 [[TMP2477]], ptr [[LLX]], align 8
36700 // SIMD-ONLY0-NEXT:    br label [[IF_END4540]]
36701 // SIMD-ONLY0:       if.end4540:
36702 // SIMD-ONLY0-NEXT:    [[TMP2478:%.*]] = load i64, ptr [[ULLX]], align 8
36703 // SIMD-ONLY0-NEXT:    [[TMP2479:%.*]] = load i64, ptr [[ULLE]], align 8
36704 // SIMD-ONLY0-NEXT:    [[CMP4541:%.*]] = icmp ugt i64 [[TMP2478]], [[TMP2479]]
36705 // SIMD-ONLY0-NEXT:    br i1 [[CMP4541]], label [[COND_TRUE4543:%.*]], label [[COND_FALSE4544:%.*]]
36706 // SIMD-ONLY0:       cond.true4543:
36707 // SIMD-ONLY0-NEXT:    [[TMP2480:%.*]] = load i64, ptr [[ULLE]], align 8
36708 // SIMD-ONLY0-NEXT:    br label [[COND_END4545:%.*]]
36709 // SIMD-ONLY0:       cond.false4544:
36710 // SIMD-ONLY0-NEXT:    [[TMP2481:%.*]] = load i64, ptr [[ULLX]], align 8
36711 // SIMD-ONLY0-NEXT:    br label [[COND_END4545]]
36712 // SIMD-ONLY0:       cond.end4545:
36713 // SIMD-ONLY0-NEXT:    [[COND4546:%.*]] = phi i64 [ [[TMP2480]], [[COND_TRUE4543]] ], [ [[TMP2481]], [[COND_FALSE4544]] ]
36714 // SIMD-ONLY0-NEXT:    store i64 [[COND4546]], ptr [[ULLX]], align 8
36715 // SIMD-ONLY0-NEXT:    [[TMP2482:%.*]] = load i64, ptr [[ULLX]], align 8
36716 // SIMD-ONLY0-NEXT:    [[TMP2483:%.*]] = load i64, ptr [[ULLE]], align 8
36717 // SIMD-ONLY0-NEXT:    [[CMP4547:%.*]] = icmp ult i64 [[TMP2482]], [[TMP2483]]
36718 // SIMD-ONLY0-NEXT:    br i1 [[CMP4547]], label [[COND_TRUE4549:%.*]], label [[COND_FALSE4550:%.*]]
36719 // SIMD-ONLY0:       cond.true4549:
36720 // SIMD-ONLY0-NEXT:    [[TMP2484:%.*]] = load i64, ptr [[ULLE]], align 8
36721 // SIMD-ONLY0-NEXT:    br label [[COND_END4551:%.*]]
36722 // SIMD-ONLY0:       cond.false4550:
36723 // SIMD-ONLY0-NEXT:    [[TMP2485:%.*]] = load i64, ptr [[ULLX]], align 8
36724 // SIMD-ONLY0-NEXT:    br label [[COND_END4551]]
36725 // SIMD-ONLY0:       cond.end4551:
36726 // SIMD-ONLY0-NEXT:    [[COND4552:%.*]] = phi i64 [ [[TMP2484]], [[COND_TRUE4549]] ], [ [[TMP2485]], [[COND_FALSE4550]] ]
36727 // SIMD-ONLY0-NEXT:    store i64 [[COND4552]], ptr [[ULLX]], align 8
36728 // SIMD-ONLY0-NEXT:    [[TMP2486:%.*]] = load i64, ptr [[ULLE]], align 8
36729 // SIMD-ONLY0-NEXT:    [[TMP2487:%.*]] = load i64, ptr [[ULLX]], align 8
36730 // SIMD-ONLY0-NEXT:    [[CMP4553:%.*]] = icmp ugt i64 [[TMP2486]], [[TMP2487]]
36731 // SIMD-ONLY0-NEXT:    br i1 [[CMP4553]], label [[COND_TRUE4555:%.*]], label [[COND_FALSE4556:%.*]]
36732 // SIMD-ONLY0:       cond.true4555:
36733 // SIMD-ONLY0-NEXT:    [[TMP2488:%.*]] = load i64, ptr [[ULLE]], align 8
36734 // SIMD-ONLY0-NEXT:    br label [[COND_END4557:%.*]]
36735 // SIMD-ONLY0:       cond.false4556:
36736 // SIMD-ONLY0-NEXT:    [[TMP2489:%.*]] = load i64, ptr [[ULLX]], align 8
36737 // SIMD-ONLY0-NEXT:    br label [[COND_END4557]]
36738 // SIMD-ONLY0:       cond.end4557:
36739 // SIMD-ONLY0-NEXT:    [[COND4558:%.*]] = phi i64 [ [[TMP2488]], [[COND_TRUE4555]] ], [ [[TMP2489]], [[COND_FALSE4556]] ]
36740 // SIMD-ONLY0-NEXT:    store i64 [[COND4558]], ptr [[ULLX]], align 8
36741 // SIMD-ONLY0-NEXT:    [[TMP2490:%.*]] = load i64, ptr [[ULLE]], align 8
36742 // SIMD-ONLY0-NEXT:    [[TMP2491:%.*]] = load i64, ptr [[ULLX]], align 8
36743 // SIMD-ONLY0-NEXT:    [[CMP4559:%.*]] = icmp ult i64 [[TMP2490]], [[TMP2491]]
36744 // SIMD-ONLY0-NEXT:    br i1 [[CMP4559]], label [[COND_TRUE4561:%.*]], label [[COND_FALSE4562:%.*]]
36745 // SIMD-ONLY0:       cond.true4561:
36746 // SIMD-ONLY0-NEXT:    [[TMP2492:%.*]] = load i64, ptr [[ULLE]], align 8
36747 // SIMD-ONLY0-NEXT:    br label [[COND_END4563:%.*]]
36748 // SIMD-ONLY0:       cond.false4562:
36749 // SIMD-ONLY0-NEXT:    [[TMP2493:%.*]] = load i64, ptr [[ULLX]], align 8
36750 // SIMD-ONLY0-NEXT:    br label [[COND_END4563]]
36751 // SIMD-ONLY0:       cond.end4563:
36752 // SIMD-ONLY0-NEXT:    [[COND4564:%.*]] = phi i64 [ [[TMP2492]], [[COND_TRUE4561]] ], [ [[TMP2493]], [[COND_FALSE4562]] ]
36753 // SIMD-ONLY0-NEXT:    store i64 [[COND4564]], ptr [[ULLX]], align 8
36754 // SIMD-ONLY0-NEXT:    [[TMP2494:%.*]] = load i64, ptr [[ULLX]], align 8
36755 // SIMD-ONLY0-NEXT:    [[TMP2495:%.*]] = load i64, ptr [[ULLE]], align 8
36756 // SIMD-ONLY0-NEXT:    [[CMP4565:%.*]] = icmp ugt i64 [[TMP2494]], [[TMP2495]]
36757 // SIMD-ONLY0-NEXT:    br i1 [[CMP4565]], label [[IF_THEN4567:%.*]], label [[IF_END4568:%.*]]
36758 // SIMD-ONLY0:       if.then4567:
36759 // SIMD-ONLY0-NEXT:    [[TMP2496:%.*]] = load i64, ptr [[ULLE]], align 8
36760 // SIMD-ONLY0-NEXT:    store i64 [[TMP2496]], ptr [[ULLX]], align 8
36761 // SIMD-ONLY0-NEXT:    br label [[IF_END4568]]
36762 // SIMD-ONLY0:       if.end4568:
36763 // SIMD-ONLY0-NEXT:    [[TMP2497:%.*]] = load i64, ptr [[ULLX]], align 8
36764 // SIMD-ONLY0-NEXT:    [[TMP2498:%.*]] = load i64, ptr [[ULLE]], align 8
36765 // SIMD-ONLY0-NEXT:    [[CMP4569:%.*]] = icmp ult i64 [[TMP2497]], [[TMP2498]]
36766 // SIMD-ONLY0-NEXT:    br i1 [[CMP4569]], label [[IF_THEN4571:%.*]], label [[IF_END4572:%.*]]
36767 // SIMD-ONLY0:       if.then4571:
36768 // SIMD-ONLY0-NEXT:    [[TMP2499:%.*]] = load i64, ptr [[ULLE]], align 8
36769 // SIMD-ONLY0-NEXT:    store i64 [[TMP2499]], ptr [[ULLX]], align 8
36770 // SIMD-ONLY0-NEXT:    br label [[IF_END4572]]
36771 // SIMD-ONLY0:       if.end4572:
36772 // SIMD-ONLY0-NEXT:    [[TMP2500:%.*]] = load i64, ptr [[ULLE]], align 8
36773 // SIMD-ONLY0-NEXT:    [[TMP2501:%.*]] = load i64, ptr [[ULLX]], align 8
36774 // SIMD-ONLY0-NEXT:    [[CMP4573:%.*]] = icmp ugt i64 [[TMP2500]], [[TMP2501]]
36775 // SIMD-ONLY0-NEXT:    br i1 [[CMP4573]], label [[IF_THEN4575:%.*]], label [[IF_END4576:%.*]]
36776 // SIMD-ONLY0:       if.then4575:
36777 // SIMD-ONLY0-NEXT:    [[TMP2502:%.*]] = load i64, ptr [[ULLE]], align 8
36778 // SIMD-ONLY0-NEXT:    store i64 [[TMP2502]], ptr [[ULLX]], align 8
36779 // SIMD-ONLY0-NEXT:    br label [[IF_END4576]]
36780 // SIMD-ONLY0:       if.end4576:
36781 // SIMD-ONLY0-NEXT:    [[TMP2503:%.*]] = load i64, ptr [[ULLE]], align 8
36782 // SIMD-ONLY0-NEXT:    [[TMP2504:%.*]] = load i64, ptr [[ULLX]], align 8
36783 // SIMD-ONLY0-NEXT:    [[CMP4577:%.*]] = icmp ult i64 [[TMP2503]], [[TMP2504]]
36784 // SIMD-ONLY0-NEXT:    br i1 [[CMP4577]], label [[IF_THEN4579:%.*]], label [[IF_END4580:%.*]]
36785 // SIMD-ONLY0:       if.then4579:
36786 // SIMD-ONLY0-NEXT:    [[TMP2505:%.*]] = load i64, ptr [[ULLE]], align 8
36787 // SIMD-ONLY0-NEXT:    store i64 [[TMP2505]], ptr [[ULLX]], align 8
36788 // SIMD-ONLY0-NEXT:    br label [[IF_END4580]]
36789 // SIMD-ONLY0:       if.end4580:
36790 // SIMD-ONLY0-NEXT:    [[TMP2506:%.*]] = load i64, ptr [[ULLX]], align 8
36791 // SIMD-ONLY0-NEXT:    [[TMP2507:%.*]] = load i64, ptr [[ULLE]], align 8
36792 // SIMD-ONLY0-NEXT:    [[CMP4581:%.*]] = icmp eq i64 [[TMP2506]], [[TMP2507]]
36793 // SIMD-ONLY0-NEXT:    br i1 [[CMP4581]], label [[COND_TRUE4583:%.*]], label [[COND_FALSE4584:%.*]]
36794 // SIMD-ONLY0:       cond.true4583:
36795 // SIMD-ONLY0-NEXT:    [[TMP2508:%.*]] = load i64, ptr [[ULLD]], align 8
36796 // SIMD-ONLY0-NEXT:    br label [[COND_END4585:%.*]]
36797 // SIMD-ONLY0:       cond.false4584:
36798 // SIMD-ONLY0-NEXT:    [[TMP2509:%.*]] = load i64, ptr [[ULLX]], align 8
36799 // SIMD-ONLY0-NEXT:    br label [[COND_END4585]]
36800 // SIMD-ONLY0:       cond.end4585:
36801 // SIMD-ONLY0-NEXT:    [[COND4586:%.*]] = phi i64 [ [[TMP2508]], [[COND_TRUE4583]] ], [ [[TMP2509]], [[COND_FALSE4584]] ]
36802 // SIMD-ONLY0-NEXT:    store i64 [[COND4586]], ptr [[ULLX]], align 8
36803 // SIMD-ONLY0-NEXT:    [[TMP2510:%.*]] = load i64, ptr [[ULLE]], align 8
36804 // SIMD-ONLY0-NEXT:    [[TMP2511:%.*]] = load i64, ptr [[ULLX]], align 8
36805 // SIMD-ONLY0-NEXT:    [[CMP4587:%.*]] = icmp eq i64 [[TMP2510]], [[TMP2511]]
36806 // SIMD-ONLY0-NEXT:    br i1 [[CMP4587]], label [[COND_TRUE4589:%.*]], label [[COND_FALSE4590:%.*]]
36807 // SIMD-ONLY0:       cond.true4589:
36808 // SIMD-ONLY0-NEXT:    [[TMP2512:%.*]] = load i64, ptr [[ULLD]], align 8
36809 // SIMD-ONLY0-NEXT:    br label [[COND_END4591:%.*]]
36810 // SIMD-ONLY0:       cond.false4590:
36811 // SIMD-ONLY0-NEXT:    [[TMP2513:%.*]] = load i64, ptr [[ULLX]], align 8
36812 // SIMD-ONLY0-NEXT:    br label [[COND_END4591]]
36813 // SIMD-ONLY0:       cond.end4591:
36814 // SIMD-ONLY0-NEXT:    [[COND4592:%.*]] = phi i64 [ [[TMP2512]], [[COND_TRUE4589]] ], [ [[TMP2513]], [[COND_FALSE4590]] ]
36815 // SIMD-ONLY0-NEXT:    store i64 [[COND4592]], ptr [[ULLX]], align 8
36816 // SIMD-ONLY0-NEXT:    [[TMP2514:%.*]] = load i64, ptr [[ULLX]], align 8
36817 // SIMD-ONLY0-NEXT:    [[TMP2515:%.*]] = load i64, ptr [[ULLE]], align 8
36818 // SIMD-ONLY0-NEXT:    [[CMP4593:%.*]] = icmp eq i64 [[TMP2514]], [[TMP2515]]
36819 // SIMD-ONLY0-NEXT:    br i1 [[CMP4593]], label [[IF_THEN4595:%.*]], label [[IF_END4596:%.*]]
36820 // SIMD-ONLY0:       if.then4595:
36821 // SIMD-ONLY0-NEXT:    [[TMP2516:%.*]] = load i64, ptr [[ULLD]], align 8
36822 // SIMD-ONLY0-NEXT:    store i64 [[TMP2516]], ptr [[ULLX]], align 8
36823 // SIMD-ONLY0-NEXT:    br label [[IF_END4596]]
36824 // SIMD-ONLY0:       if.end4596:
36825 // SIMD-ONLY0-NEXT:    [[TMP2517:%.*]] = load i64, ptr [[ULLE]], align 8
36826 // SIMD-ONLY0-NEXT:    [[TMP2518:%.*]] = load i64, ptr [[ULLX]], align 8
36827 // SIMD-ONLY0-NEXT:    [[CMP4597:%.*]] = icmp eq i64 [[TMP2517]], [[TMP2518]]
36828 // SIMD-ONLY0-NEXT:    br i1 [[CMP4597]], label [[IF_THEN4599:%.*]], label [[IF_END4600:%.*]]
36829 // SIMD-ONLY0:       if.then4599:
36830 // SIMD-ONLY0-NEXT:    [[TMP2519:%.*]] = load i64, ptr [[ULLD]], align 8
36831 // SIMD-ONLY0-NEXT:    store i64 [[TMP2519]], ptr [[ULLX]], align 8
36832 // SIMD-ONLY0-NEXT:    br label [[IF_END4600]]
36833 // SIMD-ONLY0:       if.end4600:
36834 // SIMD-ONLY0-NEXT:    [[TMP2520:%.*]] = load float, ptr [[FX]], align 4
36835 // SIMD-ONLY0-NEXT:    [[TMP2521:%.*]] = load float, ptr [[FE]], align 4
36836 // SIMD-ONLY0-NEXT:    [[CMP4601:%.*]] = fcmp ogt float [[TMP2520]], [[TMP2521]]
36837 // SIMD-ONLY0-NEXT:    br i1 [[CMP4601]], label [[COND_TRUE4603:%.*]], label [[COND_FALSE4604:%.*]]
36838 // SIMD-ONLY0:       cond.true4603:
36839 // SIMD-ONLY0-NEXT:    [[TMP2522:%.*]] = load float, ptr [[FE]], align 4
36840 // SIMD-ONLY0-NEXT:    br label [[COND_END4605:%.*]]
36841 // SIMD-ONLY0:       cond.false4604:
36842 // SIMD-ONLY0-NEXT:    [[TMP2523:%.*]] = load float, ptr [[FX]], align 4
36843 // SIMD-ONLY0-NEXT:    br label [[COND_END4605]]
36844 // SIMD-ONLY0:       cond.end4605:
36845 // SIMD-ONLY0-NEXT:    [[COND4606:%.*]] = phi float [ [[TMP2522]], [[COND_TRUE4603]] ], [ [[TMP2523]], [[COND_FALSE4604]] ]
36846 // SIMD-ONLY0-NEXT:    store float [[COND4606]], ptr [[FX]], align 4
36847 // SIMD-ONLY0-NEXT:    [[TMP2524:%.*]] = load float, ptr [[FX]], align 4
36848 // SIMD-ONLY0-NEXT:    [[TMP2525:%.*]] = load float, ptr [[FE]], align 4
36849 // SIMD-ONLY0-NEXT:    [[CMP4607:%.*]] = fcmp olt float [[TMP2524]], [[TMP2525]]
36850 // SIMD-ONLY0-NEXT:    br i1 [[CMP4607]], label [[COND_TRUE4609:%.*]], label [[COND_FALSE4610:%.*]]
36851 // SIMD-ONLY0:       cond.true4609:
36852 // SIMD-ONLY0-NEXT:    [[TMP2526:%.*]] = load float, ptr [[FE]], align 4
36853 // SIMD-ONLY0-NEXT:    br label [[COND_END4611:%.*]]
36854 // SIMD-ONLY0:       cond.false4610:
36855 // SIMD-ONLY0-NEXT:    [[TMP2527:%.*]] = load float, ptr [[FX]], align 4
36856 // SIMD-ONLY0-NEXT:    br label [[COND_END4611]]
36857 // SIMD-ONLY0:       cond.end4611:
36858 // SIMD-ONLY0-NEXT:    [[COND4612:%.*]] = phi float [ [[TMP2526]], [[COND_TRUE4609]] ], [ [[TMP2527]], [[COND_FALSE4610]] ]
36859 // SIMD-ONLY0-NEXT:    store float [[COND4612]], ptr [[FX]], align 4
36860 // SIMD-ONLY0-NEXT:    [[TMP2528:%.*]] = load float, ptr [[FE]], align 4
36861 // SIMD-ONLY0-NEXT:    [[TMP2529:%.*]] = load float, ptr [[FX]], align 4
36862 // SIMD-ONLY0-NEXT:    [[CMP4613:%.*]] = fcmp ogt float [[TMP2528]], [[TMP2529]]
36863 // SIMD-ONLY0-NEXT:    br i1 [[CMP4613]], label [[COND_TRUE4615:%.*]], label [[COND_FALSE4616:%.*]]
36864 // SIMD-ONLY0:       cond.true4615:
36865 // SIMD-ONLY0-NEXT:    [[TMP2530:%.*]] = load float, ptr [[FE]], align 4
36866 // SIMD-ONLY0-NEXT:    br label [[COND_END4617:%.*]]
36867 // SIMD-ONLY0:       cond.false4616:
36868 // SIMD-ONLY0-NEXT:    [[TMP2531:%.*]] = load float, ptr [[FX]], align 4
36869 // SIMD-ONLY0-NEXT:    br label [[COND_END4617]]
36870 // SIMD-ONLY0:       cond.end4617:
36871 // SIMD-ONLY0-NEXT:    [[COND4618:%.*]] = phi float [ [[TMP2530]], [[COND_TRUE4615]] ], [ [[TMP2531]], [[COND_FALSE4616]] ]
36872 // SIMD-ONLY0-NEXT:    store float [[COND4618]], ptr [[FX]], align 4
36873 // SIMD-ONLY0-NEXT:    [[TMP2532:%.*]] = load float, ptr [[FE]], align 4
36874 // SIMD-ONLY0-NEXT:    [[TMP2533:%.*]] = load float, ptr [[FX]], align 4
36875 // SIMD-ONLY0-NEXT:    [[CMP4619:%.*]] = fcmp olt float [[TMP2532]], [[TMP2533]]
36876 // SIMD-ONLY0-NEXT:    br i1 [[CMP4619]], label [[COND_TRUE4621:%.*]], label [[COND_FALSE4622:%.*]]
36877 // SIMD-ONLY0:       cond.true4621:
36878 // SIMD-ONLY0-NEXT:    [[TMP2534:%.*]] = load float, ptr [[FE]], align 4
36879 // SIMD-ONLY0-NEXT:    br label [[COND_END4623:%.*]]
36880 // SIMD-ONLY0:       cond.false4622:
36881 // SIMD-ONLY0-NEXT:    [[TMP2535:%.*]] = load float, ptr [[FX]], align 4
36882 // SIMD-ONLY0-NEXT:    br label [[COND_END4623]]
36883 // SIMD-ONLY0:       cond.end4623:
36884 // SIMD-ONLY0-NEXT:    [[COND4624:%.*]] = phi float [ [[TMP2534]], [[COND_TRUE4621]] ], [ [[TMP2535]], [[COND_FALSE4622]] ]
36885 // SIMD-ONLY0-NEXT:    store float [[COND4624]], ptr [[FX]], align 4
36886 // SIMD-ONLY0-NEXT:    [[TMP2536:%.*]] = load float, ptr [[FX]], align 4
36887 // SIMD-ONLY0-NEXT:    [[TMP2537:%.*]] = load float, ptr [[FE]], align 4
36888 // SIMD-ONLY0-NEXT:    [[CMP4625:%.*]] = fcmp ogt float [[TMP2536]], [[TMP2537]]
36889 // SIMD-ONLY0-NEXT:    br i1 [[CMP4625]], label [[IF_THEN4627:%.*]], label [[IF_END4628:%.*]]
36890 // SIMD-ONLY0:       if.then4627:
36891 // SIMD-ONLY0-NEXT:    [[TMP2538:%.*]] = load float, ptr [[FE]], align 4
36892 // SIMD-ONLY0-NEXT:    store float [[TMP2538]], ptr [[FX]], align 4
36893 // SIMD-ONLY0-NEXT:    br label [[IF_END4628]]
36894 // SIMD-ONLY0:       if.end4628:
36895 // SIMD-ONLY0-NEXT:    [[TMP2539:%.*]] = load float, ptr [[FX]], align 4
36896 // SIMD-ONLY0-NEXT:    [[TMP2540:%.*]] = load float, ptr [[FE]], align 4
36897 // SIMD-ONLY0-NEXT:    [[CMP4629:%.*]] = fcmp olt float [[TMP2539]], [[TMP2540]]
36898 // SIMD-ONLY0-NEXT:    br i1 [[CMP4629]], label [[IF_THEN4631:%.*]], label [[IF_END4632:%.*]]
36899 // SIMD-ONLY0:       if.then4631:
36900 // SIMD-ONLY0-NEXT:    [[TMP2541:%.*]] = load float, ptr [[FE]], align 4
36901 // SIMD-ONLY0-NEXT:    store float [[TMP2541]], ptr [[FX]], align 4
36902 // SIMD-ONLY0-NEXT:    br label [[IF_END4632]]
36903 // SIMD-ONLY0:       if.end4632:
36904 // SIMD-ONLY0-NEXT:    [[TMP2542:%.*]] = load float, ptr [[FE]], align 4
36905 // SIMD-ONLY0-NEXT:    [[TMP2543:%.*]] = load float, ptr [[FX]], align 4
36906 // SIMD-ONLY0-NEXT:    [[CMP4633:%.*]] = fcmp ogt float [[TMP2542]], [[TMP2543]]
36907 // SIMD-ONLY0-NEXT:    br i1 [[CMP4633]], label [[IF_THEN4635:%.*]], label [[IF_END4636:%.*]]
36908 // SIMD-ONLY0:       if.then4635:
36909 // SIMD-ONLY0-NEXT:    [[TMP2544:%.*]] = load float, ptr [[FE]], align 4
36910 // SIMD-ONLY0-NEXT:    store float [[TMP2544]], ptr [[FX]], align 4
36911 // SIMD-ONLY0-NEXT:    br label [[IF_END4636]]
36912 // SIMD-ONLY0:       if.end4636:
36913 // SIMD-ONLY0-NEXT:    [[TMP2545:%.*]] = load float, ptr [[FE]], align 4
36914 // SIMD-ONLY0-NEXT:    [[TMP2546:%.*]] = load float, ptr [[FX]], align 4
36915 // SIMD-ONLY0-NEXT:    [[CMP4637:%.*]] = fcmp olt float [[TMP2545]], [[TMP2546]]
36916 // SIMD-ONLY0-NEXT:    br i1 [[CMP4637]], label [[IF_THEN4639:%.*]], label [[IF_END4640:%.*]]
36917 // SIMD-ONLY0:       if.then4639:
36918 // SIMD-ONLY0-NEXT:    [[TMP2547:%.*]] = load float, ptr [[FE]], align 4
36919 // SIMD-ONLY0-NEXT:    store float [[TMP2547]], ptr [[FX]], align 4
36920 // SIMD-ONLY0-NEXT:    br label [[IF_END4640]]
36921 // SIMD-ONLY0:       if.end4640:
36922 // SIMD-ONLY0-NEXT:    [[TMP2548:%.*]] = load float, ptr [[FX]], align 4
36923 // SIMD-ONLY0-NEXT:    [[TMP2549:%.*]] = load float, ptr [[FE]], align 4
36924 // SIMD-ONLY0-NEXT:    [[CMP4641:%.*]] = fcmp ogt float [[TMP2548]], [[TMP2549]]
36925 // SIMD-ONLY0-NEXT:    br i1 [[CMP4641]], label [[COND_TRUE4643:%.*]], label [[COND_FALSE4644:%.*]]
36926 // SIMD-ONLY0:       cond.true4643:
36927 // SIMD-ONLY0-NEXT:    [[TMP2550:%.*]] = load float, ptr [[FE]], align 4
36928 // SIMD-ONLY0-NEXT:    br label [[COND_END4645:%.*]]
36929 // SIMD-ONLY0:       cond.false4644:
36930 // SIMD-ONLY0-NEXT:    [[TMP2551:%.*]] = load float, ptr [[FX]], align 4
36931 // SIMD-ONLY0-NEXT:    br label [[COND_END4645]]
36932 // SIMD-ONLY0:       cond.end4645:
36933 // SIMD-ONLY0-NEXT:    [[COND4646:%.*]] = phi float [ [[TMP2550]], [[COND_TRUE4643]] ], [ [[TMP2551]], [[COND_FALSE4644]] ]
36934 // SIMD-ONLY0-NEXT:    store float [[COND4646]], ptr [[FX]], align 4
36935 // SIMD-ONLY0-NEXT:    [[TMP2552:%.*]] = load float, ptr [[FX]], align 4
36936 // SIMD-ONLY0-NEXT:    [[TMP2553:%.*]] = load float, ptr [[FE]], align 4
36937 // SIMD-ONLY0-NEXT:    [[CMP4647:%.*]] = fcmp olt float [[TMP2552]], [[TMP2553]]
36938 // SIMD-ONLY0-NEXT:    br i1 [[CMP4647]], label [[COND_TRUE4649:%.*]], label [[COND_FALSE4650:%.*]]
36939 // SIMD-ONLY0:       cond.true4649:
36940 // SIMD-ONLY0-NEXT:    [[TMP2554:%.*]] = load float, ptr [[FE]], align 4
36941 // SIMD-ONLY0-NEXT:    br label [[COND_END4651:%.*]]
36942 // SIMD-ONLY0:       cond.false4650:
36943 // SIMD-ONLY0-NEXT:    [[TMP2555:%.*]] = load float, ptr [[FX]], align 4
36944 // SIMD-ONLY0-NEXT:    br label [[COND_END4651]]
36945 // SIMD-ONLY0:       cond.end4651:
36946 // SIMD-ONLY0-NEXT:    [[COND4652:%.*]] = phi float [ [[TMP2554]], [[COND_TRUE4649]] ], [ [[TMP2555]], [[COND_FALSE4650]] ]
36947 // SIMD-ONLY0-NEXT:    store float [[COND4652]], ptr [[FX]], align 4
36948 // SIMD-ONLY0-NEXT:    [[TMP2556:%.*]] = load float, ptr [[FE]], align 4
36949 // SIMD-ONLY0-NEXT:    [[TMP2557:%.*]] = load float, ptr [[FX]], align 4
36950 // SIMD-ONLY0-NEXT:    [[CMP4653:%.*]] = fcmp ogt float [[TMP2556]], [[TMP2557]]
36951 // SIMD-ONLY0-NEXT:    br i1 [[CMP4653]], label [[COND_TRUE4655:%.*]], label [[COND_FALSE4656:%.*]]
36952 // SIMD-ONLY0:       cond.true4655:
36953 // SIMD-ONLY0-NEXT:    [[TMP2558:%.*]] = load float, ptr [[FE]], align 4
36954 // SIMD-ONLY0-NEXT:    br label [[COND_END4657:%.*]]
36955 // SIMD-ONLY0:       cond.false4656:
36956 // SIMD-ONLY0-NEXT:    [[TMP2559:%.*]] = load float, ptr [[FX]], align 4
36957 // SIMD-ONLY0-NEXT:    br label [[COND_END4657]]
36958 // SIMD-ONLY0:       cond.end4657:
36959 // SIMD-ONLY0-NEXT:    [[COND4658:%.*]] = phi float [ [[TMP2558]], [[COND_TRUE4655]] ], [ [[TMP2559]], [[COND_FALSE4656]] ]
36960 // SIMD-ONLY0-NEXT:    store float [[COND4658]], ptr [[FX]], align 4
36961 // SIMD-ONLY0-NEXT:    [[TMP2560:%.*]] = load float, ptr [[FE]], align 4
36962 // SIMD-ONLY0-NEXT:    [[TMP2561:%.*]] = load float, ptr [[FX]], align 4
36963 // SIMD-ONLY0-NEXT:    [[CMP4659:%.*]] = fcmp olt float [[TMP2560]], [[TMP2561]]
36964 // SIMD-ONLY0-NEXT:    br i1 [[CMP4659]], label [[COND_TRUE4661:%.*]], label [[COND_FALSE4662:%.*]]
36965 // SIMD-ONLY0:       cond.true4661:
36966 // SIMD-ONLY0-NEXT:    [[TMP2562:%.*]] = load float, ptr [[FE]], align 4
36967 // SIMD-ONLY0-NEXT:    br label [[COND_END4663:%.*]]
36968 // SIMD-ONLY0:       cond.false4662:
36969 // SIMD-ONLY0-NEXT:    [[TMP2563:%.*]] = load float, ptr [[FX]], align 4
36970 // SIMD-ONLY0-NEXT:    br label [[COND_END4663]]
36971 // SIMD-ONLY0:       cond.end4663:
36972 // SIMD-ONLY0-NEXT:    [[COND4664:%.*]] = phi float [ [[TMP2562]], [[COND_TRUE4661]] ], [ [[TMP2563]], [[COND_FALSE4662]] ]
36973 // SIMD-ONLY0-NEXT:    store float [[COND4664]], ptr [[FX]], align 4
36974 // SIMD-ONLY0-NEXT:    [[TMP2564:%.*]] = load float, ptr [[FX]], align 4
36975 // SIMD-ONLY0-NEXT:    [[TMP2565:%.*]] = load float, ptr [[FE]], align 4
36976 // SIMD-ONLY0-NEXT:    [[CMP4665:%.*]] = fcmp ogt float [[TMP2564]], [[TMP2565]]
36977 // SIMD-ONLY0-NEXT:    br i1 [[CMP4665]], label [[IF_THEN4667:%.*]], label [[IF_END4668:%.*]]
36978 // SIMD-ONLY0:       if.then4667:
36979 // SIMD-ONLY0-NEXT:    [[TMP2566:%.*]] = load float, ptr [[FE]], align 4
36980 // SIMD-ONLY0-NEXT:    store float [[TMP2566]], ptr [[FX]], align 4
36981 // SIMD-ONLY0-NEXT:    br label [[IF_END4668]]
36982 // SIMD-ONLY0:       if.end4668:
36983 // SIMD-ONLY0-NEXT:    [[TMP2567:%.*]] = load float, ptr [[FX]], align 4
36984 // SIMD-ONLY0-NEXT:    [[TMP2568:%.*]] = load float, ptr [[FE]], align 4
36985 // SIMD-ONLY0-NEXT:    [[CMP4669:%.*]] = fcmp olt float [[TMP2567]], [[TMP2568]]
36986 // SIMD-ONLY0-NEXT:    br i1 [[CMP4669]], label [[IF_THEN4671:%.*]], label [[IF_END4672:%.*]]
36987 // SIMD-ONLY0:       if.then4671:
36988 // SIMD-ONLY0-NEXT:    [[TMP2569:%.*]] = load float, ptr [[FE]], align 4
36989 // SIMD-ONLY0-NEXT:    store float [[TMP2569]], ptr [[FX]], align 4
36990 // SIMD-ONLY0-NEXT:    br label [[IF_END4672]]
36991 // SIMD-ONLY0:       if.end4672:
36992 // SIMD-ONLY0-NEXT:    [[TMP2570:%.*]] = load float, ptr [[FE]], align 4
36993 // SIMD-ONLY0-NEXT:    [[TMP2571:%.*]] = load float, ptr [[FX]], align 4
36994 // SIMD-ONLY0-NEXT:    [[CMP4673:%.*]] = fcmp ogt float [[TMP2570]], [[TMP2571]]
36995 // SIMD-ONLY0-NEXT:    br i1 [[CMP4673]], label [[IF_THEN4675:%.*]], label [[IF_END4676:%.*]]
36996 // SIMD-ONLY0:       if.then4675:
36997 // SIMD-ONLY0-NEXT:    [[TMP2572:%.*]] = load float, ptr [[FE]], align 4
36998 // SIMD-ONLY0-NEXT:    store float [[TMP2572]], ptr [[FX]], align 4
36999 // SIMD-ONLY0-NEXT:    br label [[IF_END4676]]
37000 // SIMD-ONLY0:       if.end4676:
37001 // SIMD-ONLY0-NEXT:    [[TMP2573:%.*]] = load float, ptr [[FE]], align 4
37002 // SIMD-ONLY0-NEXT:    [[TMP2574:%.*]] = load float, ptr [[FX]], align 4
37003 // SIMD-ONLY0-NEXT:    [[CMP4677:%.*]] = fcmp olt float [[TMP2573]], [[TMP2574]]
37004 // SIMD-ONLY0-NEXT:    br i1 [[CMP4677]], label [[IF_THEN4679:%.*]], label [[IF_END4680:%.*]]
37005 // SIMD-ONLY0:       if.then4679:
37006 // SIMD-ONLY0-NEXT:    [[TMP2575:%.*]] = load float, ptr [[FE]], align 4
37007 // SIMD-ONLY0-NEXT:    store float [[TMP2575]], ptr [[FX]], align 4
37008 // SIMD-ONLY0-NEXT:    br label [[IF_END4680]]
37009 // SIMD-ONLY0:       if.end4680:
37010 // SIMD-ONLY0-NEXT:    [[TMP2576:%.*]] = load float, ptr [[FX]], align 4
37011 // SIMD-ONLY0-NEXT:    [[TMP2577:%.*]] = load float, ptr [[FE]], align 4
37012 // SIMD-ONLY0-NEXT:    [[CMP4681:%.*]] = fcmp ogt float [[TMP2576]], [[TMP2577]]
37013 // SIMD-ONLY0-NEXT:    br i1 [[CMP4681]], label [[COND_TRUE4683:%.*]], label [[COND_FALSE4684:%.*]]
37014 // SIMD-ONLY0:       cond.true4683:
37015 // SIMD-ONLY0-NEXT:    [[TMP2578:%.*]] = load float, ptr [[FE]], align 4
37016 // SIMD-ONLY0-NEXT:    br label [[COND_END4685:%.*]]
37017 // SIMD-ONLY0:       cond.false4684:
37018 // SIMD-ONLY0-NEXT:    [[TMP2579:%.*]] = load float, ptr [[FX]], align 4
37019 // SIMD-ONLY0-NEXT:    br label [[COND_END4685]]
37020 // SIMD-ONLY0:       cond.end4685:
37021 // SIMD-ONLY0-NEXT:    [[COND4686:%.*]] = phi float [ [[TMP2578]], [[COND_TRUE4683]] ], [ [[TMP2579]], [[COND_FALSE4684]] ]
37022 // SIMD-ONLY0-NEXT:    store float [[COND4686]], ptr [[FX]], align 4
37023 // SIMD-ONLY0-NEXT:    [[TMP2580:%.*]] = load float, ptr [[FX]], align 4
37024 // SIMD-ONLY0-NEXT:    [[TMP2581:%.*]] = load float, ptr [[FE]], align 4
37025 // SIMD-ONLY0-NEXT:    [[CMP4687:%.*]] = fcmp olt float [[TMP2580]], [[TMP2581]]
37026 // SIMD-ONLY0-NEXT:    br i1 [[CMP4687]], label [[COND_TRUE4689:%.*]], label [[COND_FALSE4690:%.*]]
37027 // SIMD-ONLY0:       cond.true4689:
37028 // SIMD-ONLY0-NEXT:    [[TMP2582:%.*]] = load float, ptr [[FE]], align 4
37029 // SIMD-ONLY0-NEXT:    br label [[COND_END4691:%.*]]
37030 // SIMD-ONLY0:       cond.false4690:
37031 // SIMD-ONLY0-NEXT:    [[TMP2583:%.*]] = load float, ptr [[FX]], align 4
37032 // SIMD-ONLY0-NEXT:    br label [[COND_END4691]]
37033 // SIMD-ONLY0:       cond.end4691:
37034 // SIMD-ONLY0-NEXT:    [[COND4692:%.*]] = phi float [ [[TMP2582]], [[COND_TRUE4689]] ], [ [[TMP2583]], [[COND_FALSE4690]] ]
37035 // SIMD-ONLY0-NEXT:    store float [[COND4692]], ptr [[FX]], align 4
37036 // SIMD-ONLY0-NEXT:    [[TMP2584:%.*]] = load float, ptr [[FE]], align 4
37037 // SIMD-ONLY0-NEXT:    [[TMP2585:%.*]] = load float, ptr [[FX]], align 4
37038 // SIMD-ONLY0-NEXT:    [[CMP4693:%.*]] = fcmp ogt float [[TMP2584]], [[TMP2585]]
37039 // SIMD-ONLY0-NEXT:    br i1 [[CMP4693]], label [[COND_TRUE4695:%.*]], label [[COND_FALSE4696:%.*]]
37040 // SIMD-ONLY0:       cond.true4695:
37041 // SIMD-ONLY0-NEXT:    [[TMP2586:%.*]] = load float, ptr [[FE]], align 4
37042 // SIMD-ONLY0-NEXT:    br label [[COND_END4697:%.*]]
37043 // SIMD-ONLY0:       cond.false4696:
37044 // SIMD-ONLY0-NEXT:    [[TMP2587:%.*]] = load float, ptr [[FX]], align 4
37045 // SIMD-ONLY0-NEXT:    br label [[COND_END4697]]
37046 // SIMD-ONLY0:       cond.end4697:
37047 // SIMD-ONLY0-NEXT:    [[COND4698:%.*]] = phi float [ [[TMP2586]], [[COND_TRUE4695]] ], [ [[TMP2587]], [[COND_FALSE4696]] ]
37048 // SIMD-ONLY0-NEXT:    store float [[COND4698]], ptr [[FX]], align 4
37049 // SIMD-ONLY0-NEXT:    [[TMP2588:%.*]] = load float, ptr [[FE]], align 4
37050 // SIMD-ONLY0-NEXT:    [[TMP2589:%.*]] = load float, ptr [[FX]], align 4
37051 // SIMD-ONLY0-NEXT:    [[CMP4699:%.*]] = fcmp olt float [[TMP2588]], [[TMP2589]]
37052 // SIMD-ONLY0-NEXT:    br i1 [[CMP4699]], label [[COND_TRUE4701:%.*]], label [[COND_FALSE4702:%.*]]
37053 // SIMD-ONLY0:       cond.true4701:
37054 // SIMD-ONLY0-NEXT:    [[TMP2590:%.*]] = load float, ptr [[FE]], align 4
37055 // SIMD-ONLY0-NEXT:    br label [[COND_END4703:%.*]]
37056 // SIMD-ONLY0:       cond.false4702:
37057 // SIMD-ONLY0-NEXT:    [[TMP2591:%.*]] = load float, ptr [[FX]], align 4
37058 // SIMD-ONLY0-NEXT:    br label [[COND_END4703]]
37059 // SIMD-ONLY0:       cond.end4703:
37060 // SIMD-ONLY0-NEXT:    [[COND4704:%.*]] = phi float [ [[TMP2590]], [[COND_TRUE4701]] ], [ [[TMP2591]], [[COND_FALSE4702]] ]
37061 // SIMD-ONLY0-NEXT:    store float [[COND4704]], ptr [[FX]], align 4
37062 // SIMD-ONLY0-NEXT:    [[TMP2592:%.*]] = load float, ptr [[FX]], align 4
37063 // SIMD-ONLY0-NEXT:    [[TMP2593:%.*]] = load float, ptr [[FE]], align 4
37064 // SIMD-ONLY0-NEXT:    [[CMP4705:%.*]] = fcmp ogt float [[TMP2592]], [[TMP2593]]
37065 // SIMD-ONLY0-NEXT:    br i1 [[CMP4705]], label [[IF_THEN4707:%.*]], label [[IF_END4708:%.*]]
37066 // SIMD-ONLY0:       if.then4707:
37067 // SIMD-ONLY0-NEXT:    [[TMP2594:%.*]] = load float, ptr [[FE]], align 4
37068 // SIMD-ONLY0-NEXT:    store float [[TMP2594]], ptr [[FX]], align 4
37069 // SIMD-ONLY0-NEXT:    br label [[IF_END4708]]
37070 // SIMD-ONLY0:       if.end4708:
37071 // SIMD-ONLY0-NEXT:    [[TMP2595:%.*]] = load float, ptr [[FX]], align 4
37072 // SIMD-ONLY0-NEXT:    [[TMP2596:%.*]] = load float, ptr [[FE]], align 4
37073 // SIMD-ONLY0-NEXT:    [[CMP4709:%.*]] = fcmp olt float [[TMP2595]], [[TMP2596]]
37074 // SIMD-ONLY0-NEXT:    br i1 [[CMP4709]], label [[IF_THEN4711:%.*]], label [[IF_END4712:%.*]]
37075 // SIMD-ONLY0:       if.then4711:
37076 // SIMD-ONLY0-NEXT:    [[TMP2597:%.*]] = load float, ptr [[FE]], align 4
37077 // SIMD-ONLY0-NEXT:    store float [[TMP2597]], ptr [[FX]], align 4
37078 // SIMD-ONLY0-NEXT:    br label [[IF_END4712]]
37079 // SIMD-ONLY0:       if.end4712:
37080 // SIMD-ONLY0-NEXT:    [[TMP2598:%.*]] = load float, ptr [[FE]], align 4
37081 // SIMD-ONLY0-NEXT:    [[TMP2599:%.*]] = load float, ptr [[FX]], align 4
37082 // SIMD-ONLY0-NEXT:    [[CMP4713:%.*]] = fcmp ogt float [[TMP2598]], [[TMP2599]]
37083 // SIMD-ONLY0-NEXT:    br i1 [[CMP4713]], label [[IF_THEN4715:%.*]], label [[IF_END4716:%.*]]
37084 // SIMD-ONLY0:       if.then4715:
37085 // SIMD-ONLY0-NEXT:    [[TMP2600:%.*]] = load float, ptr [[FE]], align 4
37086 // SIMD-ONLY0-NEXT:    store float [[TMP2600]], ptr [[FX]], align 4
37087 // SIMD-ONLY0-NEXT:    br label [[IF_END4716]]
37088 // SIMD-ONLY0:       if.end4716:
37089 // SIMD-ONLY0-NEXT:    [[TMP2601:%.*]] = load float, ptr [[FE]], align 4
37090 // SIMD-ONLY0-NEXT:    [[TMP2602:%.*]] = load float, ptr [[FX]], align 4
37091 // SIMD-ONLY0-NEXT:    [[CMP4717:%.*]] = fcmp olt float [[TMP2601]], [[TMP2602]]
37092 // SIMD-ONLY0-NEXT:    br i1 [[CMP4717]], label [[IF_THEN4719:%.*]], label [[IF_END4720:%.*]]
37093 // SIMD-ONLY0:       if.then4719:
37094 // SIMD-ONLY0-NEXT:    [[TMP2603:%.*]] = load float, ptr [[FE]], align 4
37095 // SIMD-ONLY0-NEXT:    store float [[TMP2603]], ptr [[FX]], align 4
37096 // SIMD-ONLY0-NEXT:    br label [[IF_END4720]]
37097 // SIMD-ONLY0:       if.end4720:
37098 // SIMD-ONLY0-NEXT:    [[TMP2604:%.*]] = load float, ptr [[FX]], align 4
37099 // SIMD-ONLY0-NEXT:    [[TMP2605:%.*]] = load float, ptr [[FE]], align 4
37100 // SIMD-ONLY0-NEXT:    [[CMP4721:%.*]] = fcmp ogt float [[TMP2604]], [[TMP2605]]
37101 // SIMD-ONLY0-NEXT:    br i1 [[CMP4721]], label [[COND_TRUE4723:%.*]], label [[COND_FALSE4724:%.*]]
37102 // SIMD-ONLY0:       cond.true4723:
37103 // SIMD-ONLY0-NEXT:    [[TMP2606:%.*]] = load float, ptr [[FE]], align 4
37104 // SIMD-ONLY0-NEXT:    br label [[COND_END4725:%.*]]
37105 // SIMD-ONLY0:       cond.false4724:
37106 // SIMD-ONLY0-NEXT:    [[TMP2607:%.*]] = load float, ptr [[FX]], align 4
37107 // SIMD-ONLY0-NEXT:    br label [[COND_END4725]]
37108 // SIMD-ONLY0:       cond.end4725:
37109 // SIMD-ONLY0-NEXT:    [[COND4726:%.*]] = phi float [ [[TMP2606]], [[COND_TRUE4723]] ], [ [[TMP2607]], [[COND_FALSE4724]] ]
37110 // SIMD-ONLY0-NEXT:    store float [[COND4726]], ptr [[FX]], align 4
37111 // SIMD-ONLY0-NEXT:    [[TMP2608:%.*]] = load float, ptr [[FX]], align 4
37112 // SIMD-ONLY0-NEXT:    [[TMP2609:%.*]] = load float, ptr [[FE]], align 4
37113 // SIMD-ONLY0-NEXT:    [[CMP4727:%.*]] = fcmp olt float [[TMP2608]], [[TMP2609]]
37114 // SIMD-ONLY0-NEXT:    br i1 [[CMP4727]], label [[COND_TRUE4729:%.*]], label [[COND_FALSE4730:%.*]]
37115 // SIMD-ONLY0:       cond.true4729:
37116 // SIMD-ONLY0-NEXT:    [[TMP2610:%.*]] = load float, ptr [[FE]], align 4
37117 // SIMD-ONLY0-NEXT:    br label [[COND_END4731:%.*]]
37118 // SIMD-ONLY0:       cond.false4730:
37119 // SIMD-ONLY0-NEXT:    [[TMP2611:%.*]] = load float, ptr [[FX]], align 4
37120 // SIMD-ONLY0-NEXT:    br label [[COND_END4731]]
37121 // SIMD-ONLY0:       cond.end4731:
37122 // SIMD-ONLY0-NEXT:    [[COND4732:%.*]] = phi float [ [[TMP2610]], [[COND_TRUE4729]] ], [ [[TMP2611]], [[COND_FALSE4730]] ]
37123 // SIMD-ONLY0-NEXT:    store float [[COND4732]], ptr [[FX]], align 4
37124 // SIMD-ONLY0-NEXT:    [[TMP2612:%.*]] = load float, ptr [[FE]], align 4
37125 // SIMD-ONLY0-NEXT:    [[TMP2613:%.*]] = load float, ptr [[FX]], align 4
37126 // SIMD-ONLY0-NEXT:    [[CMP4733:%.*]] = fcmp ogt float [[TMP2612]], [[TMP2613]]
37127 // SIMD-ONLY0-NEXT:    br i1 [[CMP4733]], label [[COND_TRUE4735:%.*]], label [[COND_FALSE4736:%.*]]
37128 // SIMD-ONLY0:       cond.true4735:
37129 // SIMD-ONLY0-NEXT:    [[TMP2614:%.*]] = load float, ptr [[FE]], align 4
37130 // SIMD-ONLY0-NEXT:    br label [[COND_END4737:%.*]]
37131 // SIMD-ONLY0:       cond.false4736:
37132 // SIMD-ONLY0-NEXT:    [[TMP2615:%.*]] = load float, ptr [[FX]], align 4
37133 // SIMD-ONLY0-NEXT:    br label [[COND_END4737]]
37134 // SIMD-ONLY0:       cond.end4737:
37135 // SIMD-ONLY0-NEXT:    [[COND4738:%.*]] = phi float [ [[TMP2614]], [[COND_TRUE4735]] ], [ [[TMP2615]], [[COND_FALSE4736]] ]
37136 // SIMD-ONLY0-NEXT:    store float [[COND4738]], ptr [[FX]], align 4
37137 // SIMD-ONLY0-NEXT:    [[TMP2616:%.*]] = load float, ptr [[FE]], align 4
37138 // SIMD-ONLY0-NEXT:    [[TMP2617:%.*]] = load float, ptr [[FX]], align 4
37139 // SIMD-ONLY0-NEXT:    [[CMP4739:%.*]] = fcmp olt float [[TMP2616]], [[TMP2617]]
37140 // SIMD-ONLY0-NEXT:    br i1 [[CMP4739]], label [[COND_TRUE4741:%.*]], label [[COND_FALSE4742:%.*]]
37141 // SIMD-ONLY0:       cond.true4741:
37142 // SIMD-ONLY0-NEXT:    [[TMP2618:%.*]] = load float, ptr [[FE]], align 4
37143 // SIMD-ONLY0-NEXT:    br label [[COND_END4743:%.*]]
37144 // SIMD-ONLY0:       cond.false4742:
37145 // SIMD-ONLY0-NEXT:    [[TMP2619:%.*]] = load float, ptr [[FX]], align 4
37146 // SIMD-ONLY0-NEXT:    br label [[COND_END4743]]
37147 // SIMD-ONLY0:       cond.end4743:
37148 // SIMD-ONLY0-NEXT:    [[COND4744:%.*]] = phi float [ [[TMP2618]], [[COND_TRUE4741]] ], [ [[TMP2619]], [[COND_FALSE4742]] ]
37149 // SIMD-ONLY0-NEXT:    store float [[COND4744]], ptr [[FX]], align 4
37150 // SIMD-ONLY0-NEXT:    [[TMP2620:%.*]] = load float, ptr [[FX]], align 4
37151 // SIMD-ONLY0-NEXT:    [[TMP2621:%.*]] = load float, ptr [[FE]], align 4
37152 // SIMD-ONLY0-NEXT:    [[CMP4745:%.*]] = fcmp ogt float [[TMP2620]], [[TMP2621]]
37153 // SIMD-ONLY0-NEXT:    br i1 [[CMP4745]], label [[IF_THEN4747:%.*]], label [[IF_END4748:%.*]]
37154 // SIMD-ONLY0:       if.then4747:
37155 // SIMD-ONLY0-NEXT:    [[TMP2622:%.*]] = load float, ptr [[FE]], align 4
37156 // SIMD-ONLY0-NEXT:    store float [[TMP2622]], ptr [[FX]], align 4
37157 // SIMD-ONLY0-NEXT:    br label [[IF_END4748]]
37158 // SIMD-ONLY0:       if.end4748:
37159 // SIMD-ONLY0-NEXT:    [[TMP2623:%.*]] = load float, ptr [[FX]], align 4
37160 // SIMD-ONLY0-NEXT:    [[TMP2624:%.*]] = load float, ptr [[FE]], align 4
37161 // SIMD-ONLY0-NEXT:    [[CMP4749:%.*]] = fcmp olt float [[TMP2623]], [[TMP2624]]
37162 // SIMD-ONLY0-NEXT:    br i1 [[CMP4749]], label [[IF_THEN4751:%.*]], label [[IF_END4752:%.*]]
37163 // SIMD-ONLY0:       if.then4751:
37164 // SIMD-ONLY0-NEXT:    [[TMP2625:%.*]] = load float, ptr [[FE]], align 4
37165 // SIMD-ONLY0-NEXT:    store float [[TMP2625]], ptr [[FX]], align 4
37166 // SIMD-ONLY0-NEXT:    br label [[IF_END4752]]
37167 // SIMD-ONLY0:       if.end4752:
37168 // SIMD-ONLY0-NEXT:    [[TMP2626:%.*]] = load float, ptr [[FE]], align 4
37169 // SIMD-ONLY0-NEXT:    [[TMP2627:%.*]] = load float, ptr [[FX]], align 4
37170 // SIMD-ONLY0-NEXT:    [[CMP4753:%.*]] = fcmp ogt float [[TMP2626]], [[TMP2627]]
37171 // SIMD-ONLY0-NEXT:    br i1 [[CMP4753]], label [[IF_THEN4755:%.*]], label [[IF_END4756:%.*]]
37172 // SIMD-ONLY0:       if.then4755:
37173 // SIMD-ONLY0-NEXT:    [[TMP2628:%.*]] = load float, ptr [[FE]], align 4
37174 // SIMD-ONLY0-NEXT:    store float [[TMP2628]], ptr [[FX]], align 4
37175 // SIMD-ONLY0-NEXT:    br label [[IF_END4756]]
37176 // SIMD-ONLY0:       if.end4756:
37177 // SIMD-ONLY0-NEXT:    [[TMP2629:%.*]] = load float, ptr [[FE]], align 4
37178 // SIMD-ONLY0-NEXT:    [[TMP2630:%.*]] = load float, ptr [[FX]], align 4
37179 // SIMD-ONLY0-NEXT:    [[CMP4757:%.*]] = fcmp olt float [[TMP2629]], [[TMP2630]]
37180 // SIMD-ONLY0-NEXT:    br i1 [[CMP4757]], label [[IF_THEN4759:%.*]], label [[IF_END4760:%.*]]
37181 // SIMD-ONLY0:       if.then4759:
37182 // SIMD-ONLY0-NEXT:    [[TMP2631:%.*]] = load float, ptr [[FE]], align 4
37183 // SIMD-ONLY0-NEXT:    store float [[TMP2631]], ptr [[FX]], align 4
37184 // SIMD-ONLY0-NEXT:    br label [[IF_END4760]]
37185 // SIMD-ONLY0:       if.end4760:
37186 // SIMD-ONLY0-NEXT:    [[TMP2632:%.*]] = load float, ptr [[FX]], align 4
37187 // SIMD-ONLY0-NEXT:    [[TMP2633:%.*]] = load float, ptr [[FE]], align 4
37188 // SIMD-ONLY0-NEXT:    [[CMP4761:%.*]] = fcmp ogt float [[TMP2632]], [[TMP2633]]
37189 // SIMD-ONLY0-NEXT:    br i1 [[CMP4761]], label [[COND_TRUE4763:%.*]], label [[COND_FALSE4764:%.*]]
37190 // SIMD-ONLY0:       cond.true4763:
37191 // SIMD-ONLY0-NEXT:    [[TMP2634:%.*]] = load float, ptr [[FE]], align 4
37192 // SIMD-ONLY0-NEXT:    br label [[COND_END4765:%.*]]
37193 // SIMD-ONLY0:       cond.false4764:
37194 // SIMD-ONLY0-NEXT:    [[TMP2635:%.*]] = load float, ptr [[FX]], align 4
37195 // SIMD-ONLY0-NEXT:    br label [[COND_END4765]]
37196 // SIMD-ONLY0:       cond.end4765:
37197 // SIMD-ONLY0-NEXT:    [[COND4766:%.*]] = phi float [ [[TMP2634]], [[COND_TRUE4763]] ], [ [[TMP2635]], [[COND_FALSE4764]] ]
37198 // SIMD-ONLY0-NEXT:    store float [[COND4766]], ptr [[FX]], align 4
37199 // SIMD-ONLY0-NEXT:    [[TMP2636:%.*]] = load float, ptr [[FX]], align 4
37200 // SIMD-ONLY0-NEXT:    [[TMP2637:%.*]] = load float, ptr [[FE]], align 4
37201 // SIMD-ONLY0-NEXT:    [[CMP4767:%.*]] = fcmp olt float [[TMP2636]], [[TMP2637]]
37202 // SIMD-ONLY0-NEXT:    br i1 [[CMP4767]], label [[COND_TRUE4769:%.*]], label [[COND_FALSE4770:%.*]]
37203 // SIMD-ONLY0:       cond.true4769:
37204 // SIMD-ONLY0-NEXT:    [[TMP2638:%.*]] = load float, ptr [[FE]], align 4
37205 // SIMD-ONLY0-NEXT:    br label [[COND_END4771:%.*]]
37206 // SIMD-ONLY0:       cond.false4770:
37207 // SIMD-ONLY0-NEXT:    [[TMP2639:%.*]] = load float, ptr [[FX]], align 4
37208 // SIMD-ONLY0-NEXT:    br label [[COND_END4771]]
37209 // SIMD-ONLY0:       cond.end4771:
37210 // SIMD-ONLY0-NEXT:    [[COND4772:%.*]] = phi float [ [[TMP2638]], [[COND_TRUE4769]] ], [ [[TMP2639]], [[COND_FALSE4770]] ]
37211 // SIMD-ONLY0-NEXT:    store float [[COND4772]], ptr [[FX]], align 4
37212 // SIMD-ONLY0-NEXT:    [[TMP2640:%.*]] = load float, ptr [[FE]], align 4
37213 // SIMD-ONLY0-NEXT:    [[TMP2641:%.*]] = load float, ptr [[FX]], align 4
37214 // SIMD-ONLY0-NEXT:    [[CMP4773:%.*]] = fcmp ogt float [[TMP2640]], [[TMP2641]]
37215 // SIMD-ONLY0-NEXT:    br i1 [[CMP4773]], label [[COND_TRUE4775:%.*]], label [[COND_FALSE4776:%.*]]
37216 // SIMD-ONLY0:       cond.true4775:
37217 // SIMD-ONLY0-NEXT:    [[TMP2642:%.*]] = load float, ptr [[FE]], align 4
37218 // SIMD-ONLY0-NEXT:    br label [[COND_END4777:%.*]]
37219 // SIMD-ONLY0:       cond.false4776:
37220 // SIMD-ONLY0-NEXT:    [[TMP2643:%.*]] = load float, ptr [[FX]], align 4
37221 // SIMD-ONLY0-NEXT:    br label [[COND_END4777]]
37222 // SIMD-ONLY0:       cond.end4777:
37223 // SIMD-ONLY0-NEXT:    [[COND4778:%.*]] = phi float [ [[TMP2642]], [[COND_TRUE4775]] ], [ [[TMP2643]], [[COND_FALSE4776]] ]
37224 // SIMD-ONLY0-NEXT:    store float [[COND4778]], ptr [[FX]], align 4
37225 // SIMD-ONLY0-NEXT:    [[TMP2644:%.*]] = load float, ptr [[FE]], align 4
37226 // SIMD-ONLY0-NEXT:    [[TMP2645:%.*]] = load float, ptr [[FX]], align 4
37227 // SIMD-ONLY0-NEXT:    [[CMP4779:%.*]] = fcmp olt float [[TMP2644]], [[TMP2645]]
37228 // SIMD-ONLY0-NEXT:    br i1 [[CMP4779]], label [[COND_TRUE4781:%.*]], label [[COND_FALSE4782:%.*]]
37229 // SIMD-ONLY0:       cond.true4781:
37230 // SIMD-ONLY0-NEXT:    [[TMP2646:%.*]] = load float, ptr [[FE]], align 4
37231 // SIMD-ONLY0-NEXT:    br label [[COND_END4783:%.*]]
37232 // SIMD-ONLY0:       cond.false4782:
37233 // SIMD-ONLY0-NEXT:    [[TMP2647:%.*]] = load float, ptr [[FX]], align 4
37234 // SIMD-ONLY0-NEXT:    br label [[COND_END4783]]
37235 // SIMD-ONLY0:       cond.end4783:
37236 // SIMD-ONLY0-NEXT:    [[COND4784:%.*]] = phi float [ [[TMP2646]], [[COND_TRUE4781]] ], [ [[TMP2647]], [[COND_FALSE4782]] ]
37237 // SIMD-ONLY0-NEXT:    store float [[COND4784]], ptr [[FX]], align 4
37238 // SIMD-ONLY0-NEXT:    [[TMP2648:%.*]] = load float, ptr [[FX]], align 4
37239 // SIMD-ONLY0-NEXT:    [[TMP2649:%.*]] = load float, ptr [[FE]], align 4
37240 // SIMD-ONLY0-NEXT:    [[CMP4785:%.*]] = fcmp ogt float [[TMP2648]], [[TMP2649]]
37241 // SIMD-ONLY0-NEXT:    br i1 [[CMP4785]], label [[IF_THEN4787:%.*]], label [[IF_END4788:%.*]]
37242 // SIMD-ONLY0:       if.then4787:
37243 // SIMD-ONLY0-NEXT:    [[TMP2650:%.*]] = load float, ptr [[FE]], align 4
37244 // SIMD-ONLY0-NEXT:    store float [[TMP2650]], ptr [[FX]], align 4
37245 // SIMD-ONLY0-NEXT:    br label [[IF_END4788]]
37246 // SIMD-ONLY0:       if.end4788:
37247 // SIMD-ONLY0-NEXT:    [[TMP2651:%.*]] = load float, ptr [[FX]], align 4
37248 // SIMD-ONLY0-NEXT:    [[TMP2652:%.*]] = load float, ptr [[FE]], align 4
37249 // SIMD-ONLY0-NEXT:    [[CMP4789:%.*]] = fcmp olt float [[TMP2651]], [[TMP2652]]
37250 // SIMD-ONLY0-NEXT:    br i1 [[CMP4789]], label [[IF_THEN4791:%.*]], label [[IF_END4792:%.*]]
37251 // SIMD-ONLY0:       if.then4791:
37252 // SIMD-ONLY0-NEXT:    [[TMP2653:%.*]] = load float, ptr [[FE]], align 4
37253 // SIMD-ONLY0-NEXT:    store float [[TMP2653]], ptr [[FX]], align 4
37254 // SIMD-ONLY0-NEXT:    br label [[IF_END4792]]
37255 // SIMD-ONLY0:       if.end4792:
37256 // SIMD-ONLY0-NEXT:    [[TMP2654:%.*]] = load float, ptr [[FE]], align 4
37257 // SIMD-ONLY0-NEXT:    [[TMP2655:%.*]] = load float, ptr [[FX]], align 4
37258 // SIMD-ONLY0-NEXT:    [[CMP4793:%.*]] = fcmp ogt float [[TMP2654]], [[TMP2655]]
37259 // SIMD-ONLY0-NEXT:    br i1 [[CMP4793]], label [[IF_THEN4795:%.*]], label [[IF_END4796:%.*]]
37260 // SIMD-ONLY0:       if.then4795:
37261 // SIMD-ONLY0-NEXT:    [[TMP2656:%.*]] = load float, ptr [[FE]], align 4
37262 // SIMD-ONLY0-NEXT:    store float [[TMP2656]], ptr [[FX]], align 4
37263 // SIMD-ONLY0-NEXT:    br label [[IF_END4796]]
37264 // SIMD-ONLY0:       if.end4796:
37265 // SIMD-ONLY0-NEXT:    [[TMP2657:%.*]] = load float, ptr [[FE]], align 4
37266 // SIMD-ONLY0-NEXT:    [[TMP2658:%.*]] = load float, ptr [[FX]], align 4
37267 // SIMD-ONLY0-NEXT:    [[CMP4797:%.*]] = fcmp olt float [[TMP2657]], [[TMP2658]]
37268 // SIMD-ONLY0-NEXT:    br i1 [[CMP4797]], label [[IF_THEN4799:%.*]], label [[IF_END4800:%.*]]
37269 // SIMD-ONLY0:       if.then4799:
37270 // SIMD-ONLY0-NEXT:    [[TMP2659:%.*]] = load float, ptr [[FE]], align 4
37271 // SIMD-ONLY0-NEXT:    store float [[TMP2659]], ptr [[FX]], align 4
37272 // SIMD-ONLY0-NEXT:    br label [[IF_END4800]]
37273 // SIMD-ONLY0:       if.end4800:
37274 // SIMD-ONLY0-NEXT:    [[TMP2660:%.*]] = load float, ptr [[FX]], align 4
37275 // SIMD-ONLY0-NEXT:    [[TMP2661:%.*]] = load float, ptr [[FE]], align 4
37276 // SIMD-ONLY0-NEXT:    [[CMP4801:%.*]] = fcmp ogt float [[TMP2660]], [[TMP2661]]
37277 // SIMD-ONLY0-NEXT:    br i1 [[CMP4801]], label [[COND_TRUE4803:%.*]], label [[COND_FALSE4804:%.*]]
37278 // SIMD-ONLY0:       cond.true4803:
37279 // SIMD-ONLY0-NEXT:    [[TMP2662:%.*]] = load float, ptr [[FE]], align 4
37280 // SIMD-ONLY0-NEXT:    br label [[COND_END4805:%.*]]
37281 // SIMD-ONLY0:       cond.false4804:
37282 // SIMD-ONLY0-NEXT:    [[TMP2663:%.*]] = load float, ptr [[FX]], align 4
37283 // SIMD-ONLY0-NEXT:    br label [[COND_END4805]]
37284 // SIMD-ONLY0:       cond.end4805:
37285 // SIMD-ONLY0-NEXT:    [[COND4806:%.*]] = phi float [ [[TMP2662]], [[COND_TRUE4803]] ], [ [[TMP2663]], [[COND_FALSE4804]] ]
37286 // SIMD-ONLY0-NEXT:    store float [[COND4806]], ptr [[FX]], align 4
37287 // SIMD-ONLY0-NEXT:    [[TMP2664:%.*]] = load float, ptr [[FX]], align 4
37288 // SIMD-ONLY0-NEXT:    [[TMP2665:%.*]] = load float, ptr [[FE]], align 4
37289 // SIMD-ONLY0-NEXT:    [[CMP4807:%.*]] = fcmp olt float [[TMP2664]], [[TMP2665]]
37290 // SIMD-ONLY0-NEXT:    br i1 [[CMP4807]], label [[COND_TRUE4809:%.*]], label [[COND_FALSE4810:%.*]]
37291 // SIMD-ONLY0:       cond.true4809:
37292 // SIMD-ONLY0-NEXT:    [[TMP2666:%.*]] = load float, ptr [[FE]], align 4
37293 // SIMD-ONLY0-NEXT:    br label [[COND_END4811:%.*]]
37294 // SIMD-ONLY0:       cond.false4810:
37295 // SIMD-ONLY0-NEXT:    [[TMP2667:%.*]] = load float, ptr [[FX]], align 4
37296 // SIMD-ONLY0-NEXT:    br label [[COND_END4811]]
37297 // SIMD-ONLY0:       cond.end4811:
37298 // SIMD-ONLY0-NEXT:    [[COND4812:%.*]] = phi float [ [[TMP2666]], [[COND_TRUE4809]] ], [ [[TMP2667]], [[COND_FALSE4810]] ]
37299 // SIMD-ONLY0-NEXT:    store float [[COND4812]], ptr [[FX]], align 4
37300 // SIMD-ONLY0-NEXT:    [[TMP2668:%.*]] = load float, ptr [[FE]], align 4
37301 // SIMD-ONLY0-NEXT:    [[TMP2669:%.*]] = load float, ptr [[FX]], align 4
37302 // SIMD-ONLY0-NEXT:    [[CMP4813:%.*]] = fcmp ogt float [[TMP2668]], [[TMP2669]]
37303 // SIMD-ONLY0-NEXT:    br i1 [[CMP4813]], label [[COND_TRUE4815:%.*]], label [[COND_FALSE4816:%.*]]
37304 // SIMD-ONLY0:       cond.true4815:
37305 // SIMD-ONLY0-NEXT:    [[TMP2670:%.*]] = load float, ptr [[FE]], align 4
37306 // SIMD-ONLY0-NEXT:    br label [[COND_END4817:%.*]]
37307 // SIMD-ONLY0:       cond.false4816:
37308 // SIMD-ONLY0-NEXT:    [[TMP2671:%.*]] = load float, ptr [[FX]], align 4
37309 // SIMD-ONLY0-NEXT:    br label [[COND_END4817]]
37310 // SIMD-ONLY0:       cond.end4817:
37311 // SIMD-ONLY0-NEXT:    [[COND4818:%.*]] = phi float [ [[TMP2670]], [[COND_TRUE4815]] ], [ [[TMP2671]], [[COND_FALSE4816]] ]
37312 // SIMD-ONLY0-NEXT:    store float [[COND4818]], ptr [[FX]], align 4
37313 // SIMD-ONLY0-NEXT:    [[TMP2672:%.*]] = load float, ptr [[FE]], align 4
37314 // SIMD-ONLY0-NEXT:    [[TMP2673:%.*]] = load float, ptr [[FX]], align 4
37315 // SIMD-ONLY0-NEXT:    [[CMP4819:%.*]] = fcmp olt float [[TMP2672]], [[TMP2673]]
37316 // SIMD-ONLY0-NEXT:    br i1 [[CMP4819]], label [[COND_TRUE4821:%.*]], label [[COND_FALSE4822:%.*]]
37317 // SIMD-ONLY0:       cond.true4821:
37318 // SIMD-ONLY0-NEXT:    [[TMP2674:%.*]] = load float, ptr [[FE]], align 4
37319 // SIMD-ONLY0-NEXT:    br label [[COND_END4823:%.*]]
37320 // SIMD-ONLY0:       cond.false4822:
37321 // SIMD-ONLY0-NEXT:    [[TMP2675:%.*]] = load float, ptr [[FX]], align 4
37322 // SIMD-ONLY0-NEXT:    br label [[COND_END4823]]
37323 // SIMD-ONLY0:       cond.end4823:
37324 // SIMD-ONLY0-NEXT:    [[COND4824:%.*]] = phi float [ [[TMP2674]], [[COND_TRUE4821]] ], [ [[TMP2675]], [[COND_FALSE4822]] ]
37325 // SIMD-ONLY0-NEXT:    store float [[COND4824]], ptr [[FX]], align 4
37326 // SIMD-ONLY0-NEXT:    [[TMP2676:%.*]] = load float, ptr [[FX]], align 4
37327 // SIMD-ONLY0-NEXT:    [[TMP2677:%.*]] = load float, ptr [[FE]], align 4
37328 // SIMD-ONLY0-NEXT:    [[CMP4825:%.*]] = fcmp ogt float [[TMP2676]], [[TMP2677]]
37329 // SIMD-ONLY0-NEXT:    br i1 [[CMP4825]], label [[IF_THEN4827:%.*]], label [[IF_END4828:%.*]]
37330 // SIMD-ONLY0:       if.then4827:
37331 // SIMD-ONLY0-NEXT:    [[TMP2678:%.*]] = load float, ptr [[FE]], align 4
37332 // SIMD-ONLY0-NEXT:    store float [[TMP2678]], ptr [[FX]], align 4
37333 // SIMD-ONLY0-NEXT:    br label [[IF_END4828]]
37334 // SIMD-ONLY0:       if.end4828:
37335 // SIMD-ONLY0-NEXT:    [[TMP2679:%.*]] = load float, ptr [[FX]], align 4
37336 // SIMD-ONLY0-NEXT:    [[TMP2680:%.*]] = load float, ptr [[FE]], align 4
37337 // SIMD-ONLY0-NEXT:    [[CMP4829:%.*]] = fcmp olt float [[TMP2679]], [[TMP2680]]
37338 // SIMD-ONLY0-NEXT:    br i1 [[CMP4829]], label [[IF_THEN4831:%.*]], label [[IF_END4832:%.*]]
37339 // SIMD-ONLY0:       if.then4831:
37340 // SIMD-ONLY0-NEXT:    [[TMP2681:%.*]] = load float, ptr [[FE]], align 4
37341 // SIMD-ONLY0-NEXT:    store float [[TMP2681]], ptr [[FX]], align 4
37342 // SIMD-ONLY0-NEXT:    br label [[IF_END4832]]
37343 // SIMD-ONLY0:       if.end4832:
37344 // SIMD-ONLY0-NEXT:    [[TMP2682:%.*]] = load float, ptr [[FE]], align 4
37345 // SIMD-ONLY0-NEXT:    [[TMP2683:%.*]] = load float, ptr [[FX]], align 4
37346 // SIMD-ONLY0-NEXT:    [[CMP4833:%.*]] = fcmp ogt float [[TMP2682]], [[TMP2683]]
37347 // SIMD-ONLY0-NEXT:    br i1 [[CMP4833]], label [[IF_THEN4835:%.*]], label [[IF_END4836:%.*]]
37348 // SIMD-ONLY0:       if.then4835:
37349 // SIMD-ONLY0-NEXT:    [[TMP2684:%.*]] = load float, ptr [[FE]], align 4
37350 // SIMD-ONLY0-NEXT:    store float [[TMP2684]], ptr [[FX]], align 4
37351 // SIMD-ONLY0-NEXT:    br label [[IF_END4836]]
37352 // SIMD-ONLY0:       if.end4836:
37353 // SIMD-ONLY0-NEXT:    [[TMP2685:%.*]] = load float, ptr [[FE]], align 4
37354 // SIMD-ONLY0-NEXT:    [[TMP2686:%.*]] = load float, ptr [[FX]], align 4
37355 // SIMD-ONLY0-NEXT:    [[CMP4837:%.*]] = fcmp olt float [[TMP2685]], [[TMP2686]]
37356 // SIMD-ONLY0-NEXT:    br i1 [[CMP4837]], label [[IF_THEN4839:%.*]], label [[IF_END4840:%.*]]
37357 // SIMD-ONLY0:       if.then4839:
37358 // SIMD-ONLY0-NEXT:    [[TMP2687:%.*]] = load float, ptr [[FE]], align 4
37359 // SIMD-ONLY0-NEXT:    store float [[TMP2687]], ptr [[FX]], align 4
37360 // SIMD-ONLY0-NEXT:    br label [[IF_END4840]]
37361 // SIMD-ONLY0:       if.end4840:
37362 // SIMD-ONLY0-NEXT:    [[TMP2688:%.*]] = load double, ptr [[DX]], align 8
37363 // SIMD-ONLY0-NEXT:    [[TMP2689:%.*]] = load double, ptr [[DE]], align 8
37364 // SIMD-ONLY0-NEXT:    [[CMP4841:%.*]] = fcmp ogt double [[TMP2688]], [[TMP2689]]
37365 // SIMD-ONLY0-NEXT:    br i1 [[CMP4841]], label [[COND_TRUE4843:%.*]], label [[COND_FALSE4844:%.*]]
37366 // SIMD-ONLY0:       cond.true4843:
37367 // SIMD-ONLY0-NEXT:    [[TMP2690:%.*]] = load double, ptr [[DE]], align 8
37368 // SIMD-ONLY0-NEXT:    br label [[COND_END4845:%.*]]
37369 // SIMD-ONLY0:       cond.false4844:
37370 // SIMD-ONLY0-NEXT:    [[TMP2691:%.*]] = load double, ptr [[DX]], align 8
37371 // SIMD-ONLY0-NEXT:    br label [[COND_END4845]]
37372 // SIMD-ONLY0:       cond.end4845:
37373 // SIMD-ONLY0-NEXT:    [[COND4846:%.*]] = phi double [ [[TMP2690]], [[COND_TRUE4843]] ], [ [[TMP2691]], [[COND_FALSE4844]] ]
37374 // SIMD-ONLY0-NEXT:    store double [[COND4846]], ptr [[DX]], align 8
37375 // SIMD-ONLY0-NEXT:    [[TMP2692:%.*]] = load double, ptr [[DX]], align 8
37376 // SIMD-ONLY0-NEXT:    [[TMP2693:%.*]] = load double, ptr [[DE]], align 8
37377 // SIMD-ONLY0-NEXT:    [[CMP4847:%.*]] = fcmp olt double [[TMP2692]], [[TMP2693]]
37378 // SIMD-ONLY0-NEXT:    br i1 [[CMP4847]], label [[COND_TRUE4849:%.*]], label [[COND_FALSE4850:%.*]]
37379 // SIMD-ONLY0:       cond.true4849:
37380 // SIMD-ONLY0-NEXT:    [[TMP2694:%.*]] = load double, ptr [[DE]], align 8
37381 // SIMD-ONLY0-NEXT:    br label [[COND_END4851:%.*]]
37382 // SIMD-ONLY0:       cond.false4850:
37383 // SIMD-ONLY0-NEXT:    [[TMP2695:%.*]] = load double, ptr [[DX]], align 8
37384 // SIMD-ONLY0-NEXT:    br label [[COND_END4851]]
37385 // SIMD-ONLY0:       cond.end4851:
37386 // SIMD-ONLY0-NEXT:    [[COND4852:%.*]] = phi double [ [[TMP2694]], [[COND_TRUE4849]] ], [ [[TMP2695]], [[COND_FALSE4850]] ]
37387 // SIMD-ONLY0-NEXT:    store double [[COND4852]], ptr [[DX]], align 8
37388 // SIMD-ONLY0-NEXT:    [[TMP2696:%.*]] = load double, ptr [[DE]], align 8
37389 // SIMD-ONLY0-NEXT:    [[TMP2697:%.*]] = load double, ptr [[DX]], align 8
37390 // SIMD-ONLY0-NEXT:    [[CMP4853:%.*]] = fcmp ogt double [[TMP2696]], [[TMP2697]]
37391 // SIMD-ONLY0-NEXT:    br i1 [[CMP4853]], label [[COND_TRUE4855:%.*]], label [[COND_FALSE4856:%.*]]
37392 // SIMD-ONLY0:       cond.true4855:
37393 // SIMD-ONLY0-NEXT:    [[TMP2698:%.*]] = load double, ptr [[DE]], align 8
37394 // SIMD-ONLY0-NEXT:    br label [[COND_END4857:%.*]]
37395 // SIMD-ONLY0:       cond.false4856:
37396 // SIMD-ONLY0-NEXT:    [[TMP2699:%.*]] = load double, ptr [[DX]], align 8
37397 // SIMD-ONLY0-NEXT:    br label [[COND_END4857]]
37398 // SIMD-ONLY0:       cond.end4857:
37399 // SIMD-ONLY0-NEXT:    [[COND4858:%.*]] = phi double [ [[TMP2698]], [[COND_TRUE4855]] ], [ [[TMP2699]], [[COND_FALSE4856]] ]
37400 // SIMD-ONLY0-NEXT:    store double [[COND4858]], ptr [[DX]], align 8
37401 // SIMD-ONLY0-NEXT:    [[TMP2700:%.*]] = load double, ptr [[DE]], align 8
37402 // SIMD-ONLY0-NEXT:    [[TMP2701:%.*]] = load double, ptr [[DX]], align 8
37403 // SIMD-ONLY0-NEXT:    [[CMP4859:%.*]] = fcmp olt double [[TMP2700]], [[TMP2701]]
37404 // SIMD-ONLY0-NEXT:    br i1 [[CMP4859]], label [[COND_TRUE4861:%.*]], label [[COND_FALSE4862:%.*]]
37405 // SIMD-ONLY0:       cond.true4861:
37406 // SIMD-ONLY0-NEXT:    [[TMP2702:%.*]] = load double, ptr [[DE]], align 8
37407 // SIMD-ONLY0-NEXT:    br label [[COND_END4863:%.*]]
37408 // SIMD-ONLY0:       cond.false4862:
37409 // SIMD-ONLY0-NEXT:    [[TMP2703:%.*]] = load double, ptr [[DX]], align 8
37410 // SIMD-ONLY0-NEXT:    br label [[COND_END4863]]
37411 // SIMD-ONLY0:       cond.end4863:
37412 // SIMD-ONLY0-NEXT:    [[COND4864:%.*]] = phi double [ [[TMP2702]], [[COND_TRUE4861]] ], [ [[TMP2703]], [[COND_FALSE4862]] ]
37413 // SIMD-ONLY0-NEXT:    store double [[COND4864]], ptr [[DX]], align 8
37414 // SIMD-ONLY0-NEXT:    [[TMP2704:%.*]] = load double, ptr [[DX]], align 8
37415 // SIMD-ONLY0-NEXT:    [[TMP2705:%.*]] = load double, ptr [[DE]], align 8
37416 // SIMD-ONLY0-NEXT:    [[CMP4865:%.*]] = fcmp ogt double [[TMP2704]], [[TMP2705]]
37417 // SIMD-ONLY0-NEXT:    br i1 [[CMP4865]], label [[IF_THEN4867:%.*]], label [[IF_END4868:%.*]]
37418 // SIMD-ONLY0:       if.then4867:
37419 // SIMD-ONLY0-NEXT:    [[TMP2706:%.*]] = load double, ptr [[DE]], align 8
37420 // SIMD-ONLY0-NEXT:    store double [[TMP2706]], ptr [[DX]], align 8
37421 // SIMD-ONLY0-NEXT:    br label [[IF_END4868]]
37422 // SIMD-ONLY0:       if.end4868:
37423 // SIMD-ONLY0-NEXT:    [[TMP2707:%.*]] = load double, ptr [[DX]], align 8
37424 // SIMD-ONLY0-NEXT:    [[TMP2708:%.*]] = load double, ptr [[DE]], align 8
37425 // SIMD-ONLY0-NEXT:    [[CMP4869:%.*]] = fcmp olt double [[TMP2707]], [[TMP2708]]
37426 // SIMD-ONLY0-NEXT:    br i1 [[CMP4869]], label [[IF_THEN4871:%.*]], label [[IF_END4872:%.*]]
37427 // SIMD-ONLY0:       if.then4871:
37428 // SIMD-ONLY0-NEXT:    [[TMP2709:%.*]] = load double, ptr [[DE]], align 8
37429 // SIMD-ONLY0-NEXT:    store double [[TMP2709]], ptr [[DX]], align 8
37430 // SIMD-ONLY0-NEXT:    br label [[IF_END4872]]
37431 // SIMD-ONLY0:       if.end4872:
37432 // SIMD-ONLY0-NEXT:    [[TMP2710:%.*]] = load double, ptr [[DE]], align 8
37433 // SIMD-ONLY0-NEXT:    [[TMP2711:%.*]] = load double, ptr [[DX]], align 8
37434 // SIMD-ONLY0-NEXT:    [[CMP4873:%.*]] = fcmp ogt double [[TMP2710]], [[TMP2711]]
37435 // SIMD-ONLY0-NEXT:    br i1 [[CMP4873]], label [[IF_THEN4875:%.*]], label [[IF_END4876:%.*]]
37436 // SIMD-ONLY0:       if.then4875:
37437 // SIMD-ONLY0-NEXT:    [[TMP2712:%.*]] = load double, ptr [[DE]], align 8
37438 // SIMD-ONLY0-NEXT:    store double [[TMP2712]], ptr [[DX]], align 8
37439 // SIMD-ONLY0-NEXT:    br label [[IF_END4876]]
37440 // SIMD-ONLY0:       if.end4876:
37441 // SIMD-ONLY0-NEXT:    [[TMP2713:%.*]] = load double, ptr [[DE]], align 8
37442 // SIMD-ONLY0-NEXT:    [[TMP2714:%.*]] = load double, ptr [[DX]], align 8
37443 // SIMD-ONLY0-NEXT:    [[CMP4877:%.*]] = fcmp olt double [[TMP2713]], [[TMP2714]]
37444 // SIMD-ONLY0-NEXT:    br i1 [[CMP4877]], label [[IF_THEN4879:%.*]], label [[IF_END4880:%.*]]
37445 // SIMD-ONLY0:       if.then4879:
37446 // SIMD-ONLY0-NEXT:    [[TMP2715:%.*]] = load double, ptr [[DE]], align 8
37447 // SIMD-ONLY0-NEXT:    store double [[TMP2715]], ptr [[DX]], align 8
37448 // SIMD-ONLY0-NEXT:    br label [[IF_END4880]]
37449 // SIMD-ONLY0:       if.end4880:
37450 // SIMD-ONLY0-NEXT:    [[TMP2716:%.*]] = load double, ptr [[DX]], align 8
37451 // SIMD-ONLY0-NEXT:    [[TMP2717:%.*]] = load double, ptr [[DE]], align 8
37452 // SIMD-ONLY0-NEXT:    [[CMP4881:%.*]] = fcmp ogt double [[TMP2716]], [[TMP2717]]
37453 // SIMD-ONLY0-NEXT:    br i1 [[CMP4881]], label [[COND_TRUE4883:%.*]], label [[COND_FALSE4884:%.*]]
37454 // SIMD-ONLY0:       cond.true4883:
37455 // SIMD-ONLY0-NEXT:    [[TMP2718:%.*]] = load double, ptr [[DE]], align 8
37456 // SIMD-ONLY0-NEXT:    br label [[COND_END4885:%.*]]
37457 // SIMD-ONLY0:       cond.false4884:
37458 // SIMD-ONLY0-NEXT:    [[TMP2719:%.*]] = load double, ptr [[DX]], align 8
37459 // SIMD-ONLY0-NEXT:    br label [[COND_END4885]]
37460 // SIMD-ONLY0:       cond.end4885:
37461 // SIMD-ONLY0-NEXT:    [[COND4886:%.*]] = phi double [ [[TMP2718]], [[COND_TRUE4883]] ], [ [[TMP2719]], [[COND_FALSE4884]] ]
37462 // SIMD-ONLY0-NEXT:    store double [[COND4886]], ptr [[DX]], align 8
37463 // SIMD-ONLY0-NEXT:    [[TMP2720:%.*]] = load double, ptr [[DX]], align 8
37464 // SIMD-ONLY0-NEXT:    [[TMP2721:%.*]] = load double, ptr [[DE]], align 8
37465 // SIMD-ONLY0-NEXT:    [[CMP4887:%.*]] = fcmp olt double [[TMP2720]], [[TMP2721]]
37466 // SIMD-ONLY0-NEXT:    br i1 [[CMP4887]], label [[COND_TRUE4889:%.*]], label [[COND_FALSE4890:%.*]]
37467 // SIMD-ONLY0:       cond.true4889:
37468 // SIMD-ONLY0-NEXT:    [[TMP2722:%.*]] = load double, ptr [[DE]], align 8
37469 // SIMD-ONLY0-NEXT:    br label [[COND_END4891:%.*]]
37470 // SIMD-ONLY0:       cond.false4890:
37471 // SIMD-ONLY0-NEXT:    [[TMP2723:%.*]] = load double, ptr [[DX]], align 8
37472 // SIMD-ONLY0-NEXT:    br label [[COND_END4891]]
37473 // SIMD-ONLY0:       cond.end4891:
37474 // SIMD-ONLY0-NEXT:    [[COND4892:%.*]] = phi double [ [[TMP2722]], [[COND_TRUE4889]] ], [ [[TMP2723]], [[COND_FALSE4890]] ]
37475 // SIMD-ONLY0-NEXT:    store double [[COND4892]], ptr [[DX]], align 8
37476 // SIMD-ONLY0-NEXT:    [[TMP2724:%.*]] = load double, ptr [[DE]], align 8
37477 // SIMD-ONLY0-NEXT:    [[TMP2725:%.*]] = load double, ptr [[DX]], align 8
37478 // SIMD-ONLY0-NEXT:    [[CMP4893:%.*]] = fcmp ogt double [[TMP2724]], [[TMP2725]]
37479 // SIMD-ONLY0-NEXT:    br i1 [[CMP4893]], label [[COND_TRUE4895:%.*]], label [[COND_FALSE4896:%.*]]
37480 // SIMD-ONLY0:       cond.true4895:
37481 // SIMD-ONLY0-NEXT:    [[TMP2726:%.*]] = load double, ptr [[DE]], align 8
37482 // SIMD-ONLY0-NEXT:    br label [[COND_END4897:%.*]]
37483 // SIMD-ONLY0:       cond.false4896:
37484 // SIMD-ONLY0-NEXT:    [[TMP2727:%.*]] = load double, ptr [[DX]], align 8
37485 // SIMD-ONLY0-NEXT:    br label [[COND_END4897]]
37486 // SIMD-ONLY0:       cond.end4897:
37487 // SIMD-ONLY0-NEXT:    [[COND4898:%.*]] = phi double [ [[TMP2726]], [[COND_TRUE4895]] ], [ [[TMP2727]], [[COND_FALSE4896]] ]
37488 // SIMD-ONLY0-NEXT:    store double [[COND4898]], ptr [[DX]], align 8
37489 // SIMD-ONLY0-NEXT:    [[TMP2728:%.*]] = load double, ptr [[DE]], align 8
37490 // SIMD-ONLY0-NEXT:    [[TMP2729:%.*]] = load double, ptr [[DX]], align 8
37491 // SIMD-ONLY0-NEXT:    [[CMP4899:%.*]] = fcmp olt double [[TMP2728]], [[TMP2729]]
37492 // SIMD-ONLY0-NEXT:    br i1 [[CMP4899]], label [[COND_TRUE4901:%.*]], label [[COND_FALSE4902:%.*]]
37493 // SIMD-ONLY0:       cond.true4901:
37494 // SIMD-ONLY0-NEXT:    [[TMP2730:%.*]] = load double, ptr [[DE]], align 8
37495 // SIMD-ONLY0-NEXT:    br label [[COND_END4903:%.*]]
37496 // SIMD-ONLY0:       cond.false4902:
37497 // SIMD-ONLY0-NEXT:    [[TMP2731:%.*]] = load double, ptr [[DX]], align 8
37498 // SIMD-ONLY0-NEXT:    br label [[COND_END4903]]
37499 // SIMD-ONLY0:       cond.end4903:
37500 // SIMD-ONLY0-NEXT:    [[COND4904:%.*]] = phi double [ [[TMP2730]], [[COND_TRUE4901]] ], [ [[TMP2731]], [[COND_FALSE4902]] ]
37501 // SIMD-ONLY0-NEXT:    store double [[COND4904]], ptr [[DX]], align 8
37502 // SIMD-ONLY0-NEXT:    [[TMP2732:%.*]] = load double, ptr [[DX]], align 8
37503 // SIMD-ONLY0-NEXT:    [[TMP2733:%.*]] = load double, ptr [[DE]], align 8
37504 // SIMD-ONLY0-NEXT:    [[CMP4905:%.*]] = fcmp ogt double [[TMP2732]], [[TMP2733]]
37505 // SIMD-ONLY0-NEXT:    br i1 [[CMP4905]], label [[IF_THEN4907:%.*]], label [[IF_END4908:%.*]]
37506 // SIMD-ONLY0:       if.then4907:
37507 // SIMD-ONLY0-NEXT:    [[TMP2734:%.*]] = load double, ptr [[DE]], align 8
37508 // SIMD-ONLY0-NEXT:    store double [[TMP2734]], ptr [[DX]], align 8
37509 // SIMD-ONLY0-NEXT:    br label [[IF_END4908]]
37510 // SIMD-ONLY0:       if.end4908:
37511 // SIMD-ONLY0-NEXT:    [[TMP2735:%.*]] = load double, ptr [[DX]], align 8
37512 // SIMD-ONLY0-NEXT:    [[TMP2736:%.*]] = load double, ptr [[DE]], align 8
37513 // SIMD-ONLY0-NEXT:    [[CMP4909:%.*]] = fcmp olt double [[TMP2735]], [[TMP2736]]
37514 // SIMD-ONLY0-NEXT:    br i1 [[CMP4909]], label [[IF_THEN4911:%.*]], label [[IF_END4912:%.*]]
37515 // SIMD-ONLY0:       if.then4911:
37516 // SIMD-ONLY0-NEXT:    [[TMP2737:%.*]] = load double, ptr [[DE]], align 8
37517 // SIMD-ONLY0-NEXT:    store double [[TMP2737]], ptr [[DX]], align 8
37518 // SIMD-ONLY0-NEXT:    br label [[IF_END4912]]
37519 // SIMD-ONLY0:       if.end4912:
37520 // SIMD-ONLY0-NEXT:    [[TMP2738:%.*]] = load double, ptr [[DE]], align 8
37521 // SIMD-ONLY0-NEXT:    [[TMP2739:%.*]] = load double, ptr [[DX]], align 8
37522 // SIMD-ONLY0-NEXT:    [[CMP4913:%.*]] = fcmp ogt double [[TMP2738]], [[TMP2739]]
37523 // SIMD-ONLY0-NEXT:    br i1 [[CMP4913]], label [[IF_THEN4915:%.*]], label [[IF_END4916:%.*]]
37524 // SIMD-ONLY0:       if.then4915:
37525 // SIMD-ONLY0-NEXT:    [[TMP2740:%.*]] = load double, ptr [[DE]], align 8
37526 // SIMD-ONLY0-NEXT:    store double [[TMP2740]], ptr [[DX]], align 8
37527 // SIMD-ONLY0-NEXT:    br label [[IF_END4916]]
37528 // SIMD-ONLY0:       if.end4916:
37529 // SIMD-ONLY0-NEXT:    [[TMP2741:%.*]] = load double, ptr [[DE]], align 8
37530 // SIMD-ONLY0-NEXT:    [[TMP2742:%.*]] = load double, ptr [[DX]], align 8
37531 // SIMD-ONLY0-NEXT:    [[CMP4917:%.*]] = fcmp olt double [[TMP2741]], [[TMP2742]]
37532 // SIMD-ONLY0-NEXT:    br i1 [[CMP4917]], label [[IF_THEN4919:%.*]], label [[IF_END4920:%.*]]
37533 // SIMD-ONLY0:       if.then4919:
37534 // SIMD-ONLY0-NEXT:    [[TMP2743:%.*]] = load double, ptr [[DE]], align 8
37535 // SIMD-ONLY0-NEXT:    store double [[TMP2743]], ptr [[DX]], align 8
37536 // SIMD-ONLY0-NEXT:    br label [[IF_END4920]]
37537 // SIMD-ONLY0:       if.end4920:
37538 // SIMD-ONLY0-NEXT:    [[TMP2744:%.*]] = load double, ptr [[DX]], align 8
37539 // SIMD-ONLY0-NEXT:    [[TMP2745:%.*]] = load double, ptr [[DE]], align 8
37540 // SIMD-ONLY0-NEXT:    [[CMP4921:%.*]] = fcmp ogt double [[TMP2744]], [[TMP2745]]
37541 // SIMD-ONLY0-NEXT:    br i1 [[CMP4921]], label [[COND_TRUE4923:%.*]], label [[COND_FALSE4924:%.*]]
37542 // SIMD-ONLY0:       cond.true4923:
37543 // SIMD-ONLY0-NEXT:    [[TMP2746:%.*]] = load double, ptr [[DE]], align 8
37544 // SIMD-ONLY0-NEXT:    br label [[COND_END4925:%.*]]
37545 // SIMD-ONLY0:       cond.false4924:
37546 // SIMD-ONLY0-NEXT:    [[TMP2747:%.*]] = load double, ptr [[DX]], align 8
37547 // SIMD-ONLY0-NEXT:    br label [[COND_END4925]]
37548 // SIMD-ONLY0:       cond.end4925:
37549 // SIMD-ONLY0-NEXT:    [[COND4926:%.*]] = phi double [ [[TMP2746]], [[COND_TRUE4923]] ], [ [[TMP2747]], [[COND_FALSE4924]] ]
37550 // SIMD-ONLY0-NEXT:    store double [[COND4926]], ptr [[DX]], align 8
37551 // SIMD-ONLY0-NEXT:    [[TMP2748:%.*]] = load double, ptr [[DX]], align 8
37552 // SIMD-ONLY0-NEXT:    [[TMP2749:%.*]] = load double, ptr [[DE]], align 8
37553 // SIMD-ONLY0-NEXT:    [[CMP4927:%.*]] = fcmp olt double [[TMP2748]], [[TMP2749]]
37554 // SIMD-ONLY0-NEXT:    br i1 [[CMP4927]], label [[COND_TRUE4929:%.*]], label [[COND_FALSE4930:%.*]]
37555 // SIMD-ONLY0:       cond.true4929:
37556 // SIMD-ONLY0-NEXT:    [[TMP2750:%.*]] = load double, ptr [[DE]], align 8
37557 // SIMD-ONLY0-NEXT:    br label [[COND_END4931:%.*]]
37558 // SIMD-ONLY0:       cond.false4930:
37559 // SIMD-ONLY0-NEXT:    [[TMP2751:%.*]] = load double, ptr [[DX]], align 8
37560 // SIMD-ONLY0-NEXT:    br label [[COND_END4931]]
37561 // SIMD-ONLY0:       cond.end4931:
37562 // SIMD-ONLY0-NEXT:    [[COND4932:%.*]] = phi double [ [[TMP2750]], [[COND_TRUE4929]] ], [ [[TMP2751]], [[COND_FALSE4930]] ]
37563 // SIMD-ONLY0-NEXT:    store double [[COND4932]], ptr [[DX]], align 8
37564 // SIMD-ONLY0-NEXT:    [[TMP2752:%.*]] = load double, ptr [[DE]], align 8
37565 // SIMD-ONLY0-NEXT:    [[TMP2753:%.*]] = load double, ptr [[DX]], align 8
37566 // SIMD-ONLY0-NEXT:    [[CMP4933:%.*]] = fcmp ogt double [[TMP2752]], [[TMP2753]]
37567 // SIMD-ONLY0-NEXT:    br i1 [[CMP4933]], label [[COND_TRUE4935:%.*]], label [[COND_FALSE4936:%.*]]
37568 // SIMD-ONLY0:       cond.true4935:
37569 // SIMD-ONLY0-NEXT:    [[TMP2754:%.*]] = load double, ptr [[DE]], align 8
37570 // SIMD-ONLY0-NEXT:    br label [[COND_END4937:%.*]]
37571 // SIMD-ONLY0:       cond.false4936:
37572 // SIMD-ONLY0-NEXT:    [[TMP2755:%.*]] = load double, ptr [[DX]], align 8
37573 // SIMD-ONLY0-NEXT:    br label [[COND_END4937]]
37574 // SIMD-ONLY0:       cond.end4937:
37575 // SIMD-ONLY0-NEXT:    [[COND4938:%.*]] = phi double [ [[TMP2754]], [[COND_TRUE4935]] ], [ [[TMP2755]], [[COND_FALSE4936]] ]
37576 // SIMD-ONLY0-NEXT:    store double [[COND4938]], ptr [[DX]], align 8
37577 // SIMD-ONLY0-NEXT:    [[TMP2756:%.*]] = load double, ptr [[DE]], align 8
37578 // SIMD-ONLY0-NEXT:    [[TMP2757:%.*]] = load double, ptr [[DX]], align 8
37579 // SIMD-ONLY0-NEXT:    [[CMP4939:%.*]] = fcmp olt double [[TMP2756]], [[TMP2757]]
37580 // SIMD-ONLY0-NEXT:    br i1 [[CMP4939]], label [[COND_TRUE4941:%.*]], label [[COND_FALSE4942:%.*]]
37581 // SIMD-ONLY0:       cond.true4941:
37582 // SIMD-ONLY0-NEXT:    [[TMP2758:%.*]] = load double, ptr [[DE]], align 8
37583 // SIMD-ONLY0-NEXT:    br label [[COND_END4943:%.*]]
37584 // SIMD-ONLY0:       cond.false4942:
37585 // SIMD-ONLY0-NEXT:    [[TMP2759:%.*]] = load double, ptr [[DX]], align 8
37586 // SIMD-ONLY0-NEXT:    br label [[COND_END4943]]
37587 // SIMD-ONLY0:       cond.end4943:
37588 // SIMD-ONLY0-NEXT:    [[COND4944:%.*]] = phi double [ [[TMP2758]], [[COND_TRUE4941]] ], [ [[TMP2759]], [[COND_FALSE4942]] ]
37589 // SIMD-ONLY0-NEXT:    store double [[COND4944]], ptr [[DX]], align 8
37590 // SIMD-ONLY0-NEXT:    [[TMP2760:%.*]] = load double, ptr [[DX]], align 8
37591 // SIMD-ONLY0-NEXT:    [[TMP2761:%.*]] = load double, ptr [[DE]], align 8
37592 // SIMD-ONLY0-NEXT:    [[CMP4945:%.*]] = fcmp ogt double [[TMP2760]], [[TMP2761]]
37593 // SIMD-ONLY0-NEXT:    br i1 [[CMP4945]], label [[IF_THEN4947:%.*]], label [[IF_END4948:%.*]]
37594 // SIMD-ONLY0:       if.then4947:
37595 // SIMD-ONLY0-NEXT:    [[TMP2762:%.*]] = load double, ptr [[DE]], align 8
37596 // SIMD-ONLY0-NEXT:    store double [[TMP2762]], ptr [[DX]], align 8
37597 // SIMD-ONLY0-NEXT:    br label [[IF_END4948]]
37598 // SIMD-ONLY0:       if.end4948:
37599 // SIMD-ONLY0-NEXT:    [[TMP2763:%.*]] = load double, ptr [[DX]], align 8
37600 // SIMD-ONLY0-NEXT:    [[TMP2764:%.*]] = load double, ptr [[DE]], align 8
37601 // SIMD-ONLY0-NEXT:    [[CMP4949:%.*]] = fcmp olt double [[TMP2763]], [[TMP2764]]
37602 // SIMD-ONLY0-NEXT:    br i1 [[CMP4949]], label [[IF_THEN4951:%.*]], label [[IF_END4952:%.*]]
37603 // SIMD-ONLY0:       if.then4951:
37604 // SIMD-ONLY0-NEXT:    [[TMP2765:%.*]] = load double, ptr [[DE]], align 8
37605 // SIMD-ONLY0-NEXT:    store double [[TMP2765]], ptr [[DX]], align 8
37606 // SIMD-ONLY0-NEXT:    br label [[IF_END4952]]
37607 // SIMD-ONLY0:       if.end4952:
37608 // SIMD-ONLY0-NEXT:    [[TMP2766:%.*]] = load double, ptr [[DE]], align 8
37609 // SIMD-ONLY0-NEXT:    [[TMP2767:%.*]] = load double, ptr [[DX]], align 8
37610 // SIMD-ONLY0-NEXT:    [[CMP4953:%.*]] = fcmp ogt double [[TMP2766]], [[TMP2767]]
37611 // SIMD-ONLY0-NEXT:    br i1 [[CMP4953]], label [[IF_THEN4955:%.*]], label [[IF_END4956:%.*]]
37612 // SIMD-ONLY0:       if.then4955:
37613 // SIMD-ONLY0-NEXT:    [[TMP2768:%.*]] = load double, ptr [[DE]], align 8
37614 // SIMD-ONLY0-NEXT:    store double [[TMP2768]], ptr [[DX]], align 8
37615 // SIMD-ONLY0-NEXT:    br label [[IF_END4956]]
37616 // SIMD-ONLY0:       if.end4956:
37617 // SIMD-ONLY0-NEXT:    [[TMP2769:%.*]] = load double, ptr [[DE]], align 8
37618 // SIMD-ONLY0-NEXT:    [[TMP2770:%.*]] = load double, ptr [[DX]], align 8
37619 // SIMD-ONLY0-NEXT:    [[CMP4957:%.*]] = fcmp olt double [[TMP2769]], [[TMP2770]]
37620 // SIMD-ONLY0-NEXT:    br i1 [[CMP4957]], label [[IF_THEN4959:%.*]], label [[IF_END4960:%.*]]
37621 // SIMD-ONLY0:       if.then4959:
37622 // SIMD-ONLY0-NEXT:    [[TMP2771:%.*]] = load double, ptr [[DE]], align 8
37623 // SIMD-ONLY0-NEXT:    store double [[TMP2771]], ptr [[DX]], align 8
37624 // SIMD-ONLY0-NEXT:    br label [[IF_END4960]]
37625 // SIMD-ONLY0:       if.end4960:
37626 // SIMD-ONLY0-NEXT:    [[TMP2772:%.*]] = load double, ptr [[DX]], align 8
37627 // SIMD-ONLY0-NEXT:    [[TMP2773:%.*]] = load double, ptr [[DE]], align 8
37628 // SIMD-ONLY0-NEXT:    [[CMP4961:%.*]] = fcmp ogt double [[TMP2772]], [[TMP2773]]
37629 // SIMD-ONLY0-NEXT:    br i1 [[CMP4961]], label [[COND_TRUE4963:%.*]], label [[COND_FALSE4964:%.*]]
37630 // SIMD-ONLY0:       cond.true4963:
37631 // SIMD-ONLY0-NEXT:    [[TMP2774:%.*]] = load double, ptr [[DE]], align 8
37632 // SIMD-ONLY0-NEXT:    br label [[COND_END4965:%.*]]
37633 // SIMD-ONLY0:       cond.false4964:
37634 // SIMD-ONLY0-NEXT:    [[TMP2775:%.*]] = load double, ptr [[DX]], align 8
37635 // SIMD-ONLY0-NEXT:    br label [[COND_END4965]]
37636 // SIMD-ONLY0:       cond.end4965:
37637 // SIMD-ONLY0-NEXT:    [[COND4966:%.*]] = phi double [ [[TMP2774]], [[COND_TRUE4963]] ], [ [[TMP2775]], [[COND_FALSE4964]] ]
37638 // SIMD-ONLY0-NEXT:    store double [[COND4966]], ptr [[DX]], align 8
37639 // SIMD-ONLY0-NEXT:    [[TMP2776:%.*]] = load double, ptr [[DX]], align 8
37640 // SIMD-ONLY0-NEXT:    [[TMP2777:%.*]] = load double, ptr [[DE]], align 8
37641 // SIMD-ONLY0-NEXT:    [[CMP4967:%.*]] = fcmp olt double [[TMP2776]], [[TMP2777]]
37642 // SIMD-ONLY0-NEXT:    br i1 [[CMP4967]], label [[COND_TRUE4969:%.*]], label [[COND_FALSE4970:%.*]]
37643 // SIMD-ONLY0:       cond.true4969:
37644 // SIMD-ONLY0-NEXT:    [[TMP2778:%.*]] = load double, ptr [[DE]], align 8
37645 // SIMD-ONLY0-NEXT:    br label [[COND_END4971:%.*]]
37646 // SIMD-ONLY0:       cond.false4970:
37647 // SIMD-ONLY0-NEXT:    [[TMP2779:%.*]] = load double, ptr [[DX]], align 8
37648 // SIMD-ONLY0-NEXT:    br label [[COND_END4971]]
37649 // SIMD-ONLY0:       cond.end4971:
37650 // SIMD-ONLY0-NEXT:    [[COND4972:%.*]] = phi double [ [[TMP2778]], [[COND_TRUE4969]] ], [ [[TMP2779]], [[COND_FALSE4970]] ]
37651 // SIMD-ONLY0-NEXT:    store double [[COND4972]], ptr [[DX]], align 8
37652 // SIMD-ONLY0-NEXT:    [[TMP2780:%.*]] = load double, ptr [[DE]], align 8
37653 // SIMD-ONLY0-NEXT:    [[TMP2781:%.*]] = load double, ptr [[DX]], align 8
37654 // SIMD-ONLY0-NEXT:    [[CMP4973:%.*]] = fcmp ogt double [[TMP2780]], [[TMP2781]]
37655 // SIMD-ONLY0-NEXT:    br i1 [[CMP4973]], label [[COND_TRUE4975:%.*]], label [[COND_FALSE4976:%.*]]
37656 // SIMD-ONLY0:       cond.true4975:
37657 // SIMD-ONLY0-NEXT:    [[TMP2782:%.*]] = load double, ptr [[DE]], align 8
37658 // SIMD-ONLY0-NEXT:    br label [[COND_END4977:%.*]]
37659 // SIMD-ONLY0:       cond.false4976:
37660 // SIMD-ONLY0-NEXT:    [[TMP2783:%.*]] = load double, ptr [[DX]], align 8
37661 // SIMD-ONLY0-NEXT:    br label [[COND_END4977]]
37662 // SIMD-ONLY0:       cond.end4977:
37663 // SIMD-ONLY0-NEXT:    [[COND4978:%.*]] = phi double [ [[TMP2782]], [[COND_TRUE4975]] ], [ [[TMP2783]], [[COND_FALSE4976]] ]
37664 // SIMD-ONLY0-NEXT:    store double [[COND4978]], ptr [[DX]], align 8
37665 // SIMD-ONLY0-NEXT:    [[TMP2784:%.*]] = load double, ptr [[DE]], align 8
37666 // SIMD-ONLY0-NEXT:    [[TMP2785:%.*]] = load double, ptr [[DX]], align 8
37667 // SIMD-ONLY0-NEXT:    [[CMP4979:%.*]] = fcmp olt double [[TMP2784]], [[TMP2785]]
37668 // SIMD-ONLY0-NEXT:    br i1 [[CMP4979]], label [[COND_TRUE4981:%.*]], label [[COND_FALSE4982:%.*]]
37669 // SIMD-ONLY0:       cond.true4981:
37670 // SIMD-ONLY0-NEXT:    [[TMP2786:%.*]] = load double, ptr [[DE]], align 8
37671 // SIMD-ONLY0-NEXT:    br label [[COND_END4983:%.*]]
37672 // SIMD-ONLY0:       cond.false4982:
37673 // SIMD-ONLY0-NEXT:    [[TMP2787:%.*]] = load double, ptr [[DX]], align 8
37674 // SIMD-ONLY0-NEXT:    br label [[COND_END4983]]
37675 // SIMD-ONLY0:       cond.end4983:
37676 // SIMD-ONLY0-NEXT:    [[COND4984:%.*]] = phi double [ [[TMP2786]], [[COND_TRUE4981]] ], [ [[TMP2787]], [[COND_FALSE4982]] ]
37677 // SIMD-ONLY0-NEXT:    store double [[COND4984]], ptr [[DX]], align 8
37678 // SIMD-ONLY0-NEXT:    [[TMP2788:%.*]] = load double, ptr [[DX]], align 8
37679 // SIMD-ONLY0-NEXT:    [[TMP2789:%.*]] = load double, ptr [[DE]], align 8
37680 // SIMD-ONLY0-NEXT:    [[CMP4985:%.*]] = fcmp ogt double [[TMP2788]], [[TMP2789]]
37681 // SIMD-ONLY0-NEXT:    br i1 [[CMP4985]], label [[IF_THEN4987:%.*]], label [[IF_END4988:%.*]]
37682 // SIMD-ONLY0:       if.then4987:
37683 // SIMD-ONLY0-NEXT:    [[TMP2790:%.*]] = load double, ptr [[DE]], align 8
37684 // SIMD-ONLY0-NEXT:    store double [[TMP2790]], ptr [[DX]], align 8
37685 // SIMD-ONLY0-NEXT:    br label [[IF_END4988]]
37686 // SIMD-ONLY0:       if.end4988:
37687 // SIMD-ONLY0-NEXT:    [[TMP2791:%.*]] = load double, ptr [[DX]], align 8
37688 // SIMD-ONLY0-NEXT:    [[TMP2792:%.*]] = load double, ptr [[DE]], align 8
37689 // SIMD-ONLY0-NEXT:    [[CMP4989:%.*]] = fcmp olt double [[TMP2791]], [[TMP2792]]
37690 // SIMD-ONLY0-NEXT:    br i1 [[CMP4989]], label [[IF_THEN4991:%.*]], label [[IF_END4992:%.*]]
37691 // SIMD-ONLY0:       if.then4991:
37692 // SIMD-ONLY0-NEXT:    [[TMP2793:%.*]] = load double, ptr [[DE]], align 8
37693 // SIMD-ONLY0-NEXT:    store double [[TMP2793]], ptr [[DX]], align 8
37694 // SIMD-ONLY0-NEXT:    br label [[IF_END4992]]
37695 // SIMD-ONLY0:       if.end4992:
37696 // SIMD-ONLY0-NEXT:    [[TMP2794:%.*]] = load double, ptr [[DE]], align 8
37697 // SIMD-ONLY0-NEXT:    [[TMP2795:%.*]] = load double, ptr [[DX]], align 8
37698 // SIMD-ONLY0-NEXT:    [[CMP4993:%.*]] = fcmp ogt double [[TMP2794]], [[TMP2795]]
37699 // SIMD-ONLY0-NEXT:    br i1 [[CMP4993]], label [[IF_THEN4995:%.*]], label [[IF_END4996:%.*]]
37700 // SIMD-ONLY0:       if.then4995:
37701 // SIMD-ONLY0-NEXT:    [[TMP2796:%.*]] = load double, ptr [[DE]], align 8
37702 // SIMD-ONLY0-NEXT:    store double [[TMP2796]], ptr [[DX]], align 8
37703 // SIMD-ONLY0-NEXT:    br label [[IF_END4996]]
37704 // SIMD-ONLY0:       if.end4996:
37705 // SIMD-ONLY0-NEXT:    [[TMP2797:%.*]] = load double, ptr [[DE]], align 8
37706 // SIMD-ONLY0-NEXT:    [[TMP2798:%.*]] = load double, ptr [[DX]], align 8
37707 // SIMD-ONLY0-NEXT:    [[CMP4997:%.*]] = fcmp olt double [[TMP2797]], [[TMP2798]]
37708 // SIMD-ONLY0-NEXT:    br i1 [[CMP4997]], label [[IF_THEN4999:%.*]], label [[IF_END5000:%.*]]
37709 // SIMD-ONLY0:       if.then4999:
37710 // SIMD-ONLY0-NEXT:    [[TMP2799:%.*]] = load double, ptr [[DE]], align 8
37711 // SIMD-ONLY0-NEXT:    store double [[TMP2799]], ptr [[DX]], align 8
37712 // SIMD-ONLY0-NEXT:    br label [[IF_END5000]]
37713 // SIMD-ONLY0:       if.end5000:
37714 // SIMD-ONLY0-NEXT:    [[TMP2800:%.*]] = load double, ptr [[DX]], align 8
37715 // SIMD-ONLY0-NEXT:    [[TMP2801:%.*]] = load double, ptr [[DE]], align 8
37716 // SIMD-ONLY0-NEXT:    [[CMP5001:%.*]] = fcmp ogt double [[TMP2800]], [[TMP2801]]
37717 // SIMD-ONLY0-NEXT:    br i1 [[CMP5001]], label [[COND_TRUE5003:%.*]], label [[COND_FALSE5004:%.*]]
37718 // SIMD-ONLY0:       cond.true5003:
37719 // SIMD-ONLY0-NEXT:    [[TMP2802:%.*]] = load double, ptr [[DE]], align 8
37720 // SIMD-ONLY0-NEXT:    br label [[COND_END5005:%.*]]
37721 // SIMD-ONLY0:       cond.false5004:
37722 // SIMD-ONLY0-NEXT:    [[TMP2803:%.*]] = load double, ptr [[DX]], align 8
37723 // SIMD-ONLY0-NEXT:    br label [[COND_END5005]]
37724 // SIMD-ONLY0:       cond.end5005:
37725 // SIMD-ONLY0-NEXT:    [[COND5006:%.*]] = phi double [ [[TMP2802]], [[COND_TRUE5003]] ], [ [[TMP2803]], [[COND_FALSE5004]] ]
37726 // SIMD-ONLY0-NEXT:    store double [[COND5006]], ptr [[DX]], align 8
37727 // SIMD-ONLY0-NEXT:    [[TMP2804:%.*]] = load double, ptr [[DX]], align 8
37728 // SIMD-ONLY0-NEXT:    [[TMP2805:%.*]] = load double, ptr [[DE]], align 8
37729 // SIMD-ONLY0-NEXT:    [[CMP5007:%.*]] = fcmp olt double [[TMP2804]], [[TMP2805]]
37730 // SIMD-ONLY0-NEXT:    br i1 [[CMP5007]], label [[COND_TRUE5009:%.*]], label [[COND_FALSE5010:%.*]]
37731 // SIMD-ONLY0:       cond.true5009:
37732 // SIMD-ONLY0-NEXT:    [[TMP2806:%.*]] = load double, ptr [[DE]], align 8
37733 // SIMD-ONLY0-NEXT:    br label [[COND_END5011:%.*]]
37734 // SIMD-ONLY0:       cond.false5010:
37735 // SIMD-ONLY0-NEXT:    [[TMP2807:%.*]] = load double, ptr [[DX]], align 8
37736 // SIMD-ONLY0-NEXT:    br label [[COND_END5011]]
37737 // SIMD-ONLY0:       cond.end5011:
37738 // SIMD-ONLY0-NEXT:    [[COND5012:%.*]] = phi double [ [[TMP2806]], [[COND_TRUE5009]] ], [ [[TMP2807]], [[COND_FALSE5010]] ]
37739 // SIMD-ONLY0-NEXT:    store double [[COND5012]], ptr [[DX]], align 8
37740 // SIMD-ONLY0-NEXT:    [[TMP2808:%.*]] = load double, ptr [[DE]], align 8
37741 // SIMD-ONLY0-NEXT:    [[TMP2809:%.*]] = load double, ptr [[DX]], align 8
37742 // SIMD-ONLY0-NEXT:    [[CMP5013:%.*]] = fcmp ogt double [[TMP2808]], [[TMP2809]]
37743 // SIMD-ONLY0-NEXT:    br i1 [[CMP5013]], label [[COND_TRUE5015:%.*]], label [[COND_FALSE5016:%.*]]
37744 // SIMD-ONLY0:       cond.true5015:
37745 // SIMD-ONLY0-NEXT:    [[TMP2810:%.*]] = load double, ptr [[DE]], align 8
37746 // SIMD-ONLY0-NEXT:    br label [[COND_END5017:%.*]]
37747 // SIMD-ONLY0:       cond.false5016:
37748 // SIMD-ONLY0-NEXT:    [[TMP2811:%.*]] = load double, ptr [[DX]], align 8
37749 // SIMD-ONLY0-NEXT:    br label [[COND_END5017]]
37750 // SIMD-ONLY0:       cond.end5017:
37751 // SIMD-ONLY0-NEXT:    [[COND5018:%.*]] = phi double [ [[TMP2810]], [[COND_TRUE5015]] ], [ [[TMP2811]], [[COND_FALSE5016]] ]
37752 // SIMD-ONLY0-NEXT:    store double [[COND5018]], ptr [[DX]], align 8
37753 // SIMD-ONLY0-NEXT:    [[TMP2812:%.*]] = load double, ptr [[DE]], align 8
37754 // SIMD-ONLY0-NEXT:    [[TMP2813:%.*]] = load double, ptr [[DX]], align 8
37755 // SIMD-ONLY0-NEXT:    [[CMP5019:%.*]] = fcmp olt double [[TMP2812]], [[TMP2813]]
37756 // SIMD-ONLY0-NEXT:    br i1 [[CMP5019]], label [[COND_TRUE5021:%.*]], label [[COND_FALSE5022:%.*]]
37757 // SIMD-ONLY0:       cond.true5021:
37758 // SIMD-ONLY0-NEXT:    [[TMP2814:%.*]] = load double, ptr [[DE]], align 8
37759 // SIMD-ONLY0-NEXT:    br label [[COND_END5023:%.*]]
37760 // SIMD-ONLY0:       cond.false5022:
37761 // SIMD-ONLY0-NEXT:    [[TMP2815:%.*]] = load double, ptr [[DX]], align 8
37762 // SIMD-ONLY0-NEXT:    br label [[COND_END5023]]
37763 // SIMD-ONLY0:       cond.end5023:
37764 // SIMD-ONLY0-NEXT:    [[COND5024:%.*]] = phi double [ [[TMP2814]], [[COND_TRUE5021]] ], [ [[TMP2815]], [[COND_FALSE5022]] ]
37765 // SIMD-ONLY0-NEXT:    store double [[COND5024]], ptr [[DX]], align 8
37766 // SIMD-ONLY0-NEXT:    [[TMP2816:%.*]] = load double, ptr [[DX]], align 8
37767 // SIMD-ONLY0-NEXT:    [[TMP2817:%.*]] = load double, ptr [[DE]], align 8
37768 // SIMD-ONLY0-NEXT:    [[CMP5025:%.*]] = fcmp ogt double [[TMP2816]], [[TMP2817]]
37769 // SIMD-ONLY0-NEXT:    br i1 [[CMP5025]], label [[IF_THEN5027:%.*]], label [[IF_END5028:%.*]]
37770 // SIMD-ONLY0:       if.then5027:
37771 // SIMD-ONLY0-NEXT:    [[TMP2818:%.*]] = load double, ptr [[DE]], align 8
37772 // SIMD-ONLY0-NEXT:    store double [[TMP2818]], ptr [[DX]], align 8
37773 // SIMD-ONLY0-NEXT:    br label [[IF_END5028]]
37774 // SIMD-ONLY0:       if.end5028:
37775 // SIMD-ONLY0-NEXT:    [[TMP2819:%.*]] = load double, ptr [[DX]], align 8
37776 // SIMD-ONLY0-NEXT:    [[TMP2820:%.*]] = load double, ptr [[DE]], align 8
37777 // SIMD-ONLY0-NEXT:    [[CMP5029:%.*]] = fcmp olt double [[TMP2819]], [[TMP2820]]
37778 // SIMD-ONLY0-NEXT:    br i1 [[CMP5029]], label [[IF_THEN5031:%.*]], label [[IF_END5032:%.*]]
37779 // SIMD-ONLY0:       if.then5031:
37780 // SIMD-ONLY0-NEXT:    [[TMP2821:%.*]] = load double, ptr [[DE]], align 8
37781 // SIMD-ONLY0-NEXT:    store double [[TMP2821]], ptr [[DX]], align 8
37782 // SIMD-ONLY0-NEXT:    br label [[IF_END5032]]
37783 // SIMD-ONLY0:       if.end5032:
37784 // SIMD-ONLY0-NEXT:    [[TMP2822:%.*]] = load double, ptr [[DE]], align 8
37785 // SIMD-ONLY0-NEXT:    [[TMP2823:%.*]] = load double, ptr [[DX]], align 8
37786 // SIMD-ONLY0-NEXT:    [[CMP5033:%.*]] = fcmp ogt double [[TMP2822]], [[TMP2823]]
37787 // SIMD-ONLY0-NEXT:    br i1 [[CMP5033]], label [[IF_THEN5035:%.*]], label [[IF_END5036:%.*]]
37788 // SIMD-ONLY0:       if.then5035:
37789 // SIMD-ONLY0-NEXT:    [[TMP2824:%.*]] = load double, ptr [[DE]], align 8
37790 // SIMD-ONLY0-NEXT:    store double [[TMP2824]], ptr [[DX]], align 8
37791 // SIMD-ONLY0-NEXT:    br label [[IF_END5036]]
37792 // SIMD-ONLY0:       if.end5036:
37793 // SIMD-ONLY0-NEXT:    [[TMP2825:%.*]] = load double, ptr [[DE]], align 8
37794 // SIMD-ONLY0-NEXT:    [[TMP2826:%.*]] = load double, ptr [[DX]], align 8
37795 // SIMD-ONLY0-NEXT:    [[CMP5037:%.*]] = fcmp olt double [[TMP2825]], [[TMP2826]]
37796 // SIMD-ONLY0-NEXT:    br i1 [[CMP5037]], label [[IF_THEN5039:%.*]], label [[IF_END5040:%.*]]
37797 // SIMD-ONLY0:       if.then5039:
37798 // SIMD-ONLY0-NEXT:    [[TMP2827:%.*]] = load double, ptr [[DE]], align 8
37799 // SIMD-ONLY0-NEXT:    store double [[TMP2827]], ptr [[DX]], align 8
37800 // SIMD-ONLY0-NEXT:    br label [[IF_END5040]]
37801 // SIMD-ONLY0:       if.end5040:
37802 // SIMD-ONLY0-NEXT:    [[TMP2828:%.*]] = load double, ptr [[DX]], align 8
37803 // SIMD-ONLY0-NEXT:    [[TMP2829:%.*]] = load double, ptr [[DE]], align 8
37804 // SIMD-ONLY0-NEXT:    [[CMP5041:%.*]] = fcmp ogt double [[TMP2828]], [[TMP2829]]
37805 // SIMD-ONLY0-NEXT:    br i1 [[CMP5041]], label [[COND_TRUE5043:%.*]], label [[COND_FALSE5044:%.*]]
37806 // SIMD-ONLY0:       cond.true5043:
37807 // SIMD-ONLY0-NEXT:    [[TMP2830:%.*]] = load double, ptr [[DE]], align 8
37808 // SIMD-ONLY0-NEXT:    br label [[COND_END5045:%.*]]
37809 // SIMD-ONLY0:       cond.false5044:
37810 // SIMD-ONLY0-NEXT:    [[TMP2831:%.*]] = load double, ptr [[DX]], align 8
37811 // SIMD-ONLY0-NEXT:    br label [[COND_END5045]]
37812 // SIMD-ONLY0:       cond.end5045:
37813 // SIMD-ONLY0-NEXT:    [[COND5046:%.*]] = phi double [ [[TMP2830]], [[COND_TRUE5043]] ], [ [[TMP2831]], [[COND_FALSE5044]] ]
37814 // SIMD-ONLY0-NEXT:    store double [[COND5046]], ptr [[DX]], align 8
37815 // SIMD-ONLY0-NEXT:    [[TMP2832:%.*]] = load double, ptr [[DX]], align 8
37816 // SIMD-ONLY0-NEXT:    [[TMP2833:%.*]] = load double, ptr [[DE]], align 8
37817 // SIMD-ONLY0-NEXT:    [[CMP5047:%.*]] = fcmp olt double [[TMP2832]], [[TMP2833]]
37818 // SIMD-ONLY0-NEXT:    br i1 [[CMP5047]], label [[COND_TRUE5049:%.*]], label [[COND_FALSE5050:%.*]]
37819 // SIMD-ONLY0:       cond.true5049:
37820 // SIMD-ONLY0-NEXT:    [[TMP2834:%.*]] = load double, ptr [[DE]], align 8
37821 // SIMD-ONLY0-NEXT:    br label [[COND_END5051:%.*]]
37822 // SIMD-ONLY0:       cond.false5050:
37823 // SIMD-ONLY0-NEXT:    [[TMP2835:%.*]] = load double, ptr [[DX]], align 8
37824 // SIMD-ONLY0-NEXT:    br label [[COND_END5051]]
37825 // SIMD-ONLY0:       cond.end5051:
37826 // SIMD-ONLY0-NEXT:    [[COND5052:%.*]] = phi double [ [[TMP2834]], [[COND_TRUE5049]] ], [ [[TMP2835]], [[COND_FALSE5050]] ]
37827 // SIMD-ONLY0-NEXT:    store double [[COND5052]], ptr [[DX]], align 8
37828 // SIMD-ONLY0-NEXT:    [[TMP2836:%.*]] = load double, ptr [[DE]], align 8
37829 // SIMD-ONLY0-NEXT:    [[TMP2837:%.*]] = load double, ptr [[DX]], align 8
37830 // SIMD-ONLY0-NEXT:    [[CMP5053:%.*]] = fcmp ogt double [[TMP2836]], [[TMP2837]]
37831 // SIMD-ONLY0-NEXT:    br i1 [[CMP5053]], label [[COND_TRUE5055:%.*]], label [[COND_FALSE5056:%.*]]
37832 // SIMD-ONLY0:       cond.true5055:
37833 // SIMD-ONLY0-NEXT:    [[TMP2838:%.*]] = load double, ptr [[DE]], align 8
37834 // SIMD-ONLY0-NEXT:    br label [[COND_END5057:%.*]]
37835 // SIMD-ONLY0:       cond.false5056:
37836 // SIMD-ONLY0-NEXT:    [[TMP2839:%.*]] = load double, ptr [[DX]], align 8
37837 // SIMD-ONLY0-NEXT:    br label [[COND_END5057]]
37838 // SIMD-ONLY0:       cond.end5057:
37839 // SIMD-ONLY0-NEXT:    [[COND5058:%.*]] = phi double [ [[TMP2838]], [[COND_TRUE5055]] ], [ [[TMP2839]], [[COND_FALSE5056]] ]
37840 // SIMD-ONLY0-NEXT:    store double [[COND5058]], ptr [[DX]], align 8
37841 // SIMD-ONLY0-NEXT:    [[TMP2840:%.*]] = load double, ptr [[DE]], align 8
37842 // SIMD-ONLY0-NEXT:    [[TMP2841:%.*]] = load double, ptr [[DX]], align 8
37843 // SIMD-ONLY0-NEXT:    [[CMP5059:%.*]] = fcmp olt double [[TMP2840]], [[TMP2841]]
37844 // SIMD-ONLY0-NEXT:    br i1 [[CMP5059]], label [[COND_TRUE5061:%.*]], label [[COND_FALSE5062:%.*]]
37845 // SIMD-ONLY0:       cond.true5061:
37846 // SIMD-ONLY0-NEXT:    [[TMP2842:%.*]] = load double, ptr [[DE]], align 8
37847 // SIMD-ONLY0-NEXT:    br label [[COND_END5063:%.*]]
37848 // SIMD-ONLY0:       cond.false5062:
37849 // SIMD-ONLY0-NEXT:    [[TMP2843:%.*]] = load double, ptr [[DX]], align 8
37850 // SIMD-ONLY0-NEXT:    br label [[COND_END5063]]
37851 // SIMD-ONLY0:       cond.end5063:
37852 // SIMD-ONLY0-NEXT:    [[COND5064:%.*]] = phi double [ [[TMP2842]], [[COND_TRUE5061]] ], [ [[TMP2843]], [[COND_FALSE5062]] ]
37853 // SIMD-ONLY0-NEXT:    store double [[COND5064]], ptr [[DX]], align 8
37854 // SIMD-ONLY0-NEXT:    [[TMP2844:%.*]] = load double, ptr [[DX]], align 8
37855 // SIMD-ONLY0-NEXT:    [[TMP2845:%.*]] = load double, ptr [[DE]], align 8
37856 // SIMD-ONLY0-NEXT:    [[CMP5065:%.*]] = fcmp ogt double [[TMP2844]], [[TMP2845]]
37857 // SIMD-ONLY0-NEXT:    br i1 [[CMP5065]], label [[IF_THEN5067:%.*]], label [[IF_END5068:%.*]]
37858 // SIMD-ONLY0:       if.then5067:
37859 // SIMD-ONLY0-NEXT:    [[TMP2846:%.*]] = load double, ptr [[DE]], align 8
37860 // SIMD-ONLY0-NEXT:    store double [[TMP2846]], ptr [[DX]], align 8
37861 // SIMD-ONLY0-NEXT:    br label [[IF_END5068]]
37862 // SIMD-ONLY0:       if.end5068:
37863 // SIMD-ONLY0-NEXT:    [[TMP2847:%.*]] = load double, ptr [[DX]], align 8
37864 // SIMD-ONLY0-NEXT:    [[TMP2848:%.*]] = load double, ptr [[DE]], align 8
37865 // SIMD-ONLY0-NEXT:    [[CMP5069:%.*]] = fcmp olt double [[TMP2847]], [[TMP2848]]
37866 // SIMD-ONLY0-NEXT:    br i1 [[CMP5069]], label [[IF_THEN5071:%.*]], label [[IF_END5072:%.*]]
37867 // SIMD-ONLY0:       if.then5071:
37868 // SIMD-ONLY0-NEXT:    [[TMP2849:%.*]] = load double, ptr [[DE]], align 8
37869 // SIMD-ONLY0-NEXT:    store double [[TMP2849]], ptr [[DX]], align 8
37870 // SIMD-ONLY0-NEXT:    br label [[IF_END5072]]
37871 // SIMD-ONLY0:       if.end5072:
37872 // SIMD-ONLY0-NEXT:    [[TMP2850:%.*]] = load double, ptr [[DE]], align 8
37873 // SIMD-ONLY0-NEXT:    [[TMP2851:%.*]] = load double, ptr [[DX]], align 8
37874 // SIMD-ONLY0-NEXT:    [[CMP5073:%.*]] = fcmp ogt double [[TMP2850]], [[TMP2851]]
37875 // SIMD-ONLY0-NEXT:    br i1 [[CMP5073]], label [[IF_THEN5075:%.*]], label [[IF_END5076:%.*]]
37876 // SIMD-ONLY0:       if.then5075:
37877 // SIMD-ONLY0-NEXT:    [[TMP2852:%.*]] = load double, ptr [[DE]], align 8
37878 // SIMD-ONLY0-NEXT:    store double [[TMP2852]], ptr [[DX]], align 8
37879 // SIMD-ONLY0-NEXT:    br label [[IF_END5076]]
37880 // SIMD-ONLY0:       if.end5076:
37881 // SIMD-ONLY0-NEXT:    [[TMP2853:%.*]] = load double, ptr [[DE]], align 8
37882 // SIMD-ONLY0-NEXT:    [[TMP2854:%.*]] = load double, ptr [[DX]], align 8
37883 // SIMD-ONLY0-NEXT:    [[CMP5077:%.*]] = fcmp olt double [[TMP2853]], [[TMP2854]]
37884 // SIMD-ONLY0-NEXT:    br i1 [[CMP5077]], label [[IF_THEN5079:%.*]], label [[IF_END5080:%.*]]
37885 // SIMD-ONLY0:       if.then5079:
37886 // SIMD-ONLY0-NEXT:    [[TMP2855:%.*]] = load double, ptr [[DE]], align 8
37887 // SIMD-ONLY0-NEXT:    store double [[TMP2855]], ptr [[DX]], align 8
37888 // SIMD-ONLY0-NEXT:    br label [[IF_END5080]]
37889 // SIMD-ONLY0:       if.end5080:
37890 // SIMD-ONLY0-NEXT:    ret void
37891 //
37892 //
37893 // SIMD-ONLY0-LABEL: @bar(
37894 // SIMD-ONLY0-NEXT:  entry:
37895 // SIMD-ONLY0-NEXT:    [[CX:%.*]] = alloca i8, align 1
37896 // SIMD-ONLY0-NEXT:    [[CV:%.*]] = alloca i8, align 1
37897 // SIMD-ONLY0-NEXT:    [[CR:%.*]] = alloca i8, align 1
37898 // SIMD-ONLY0-NEXT:    [[CE:%.*]] = alloca i8, align 1
37899 // SIMD-ONLY0-NEXT:    [[CD:%.*]] = alloca i8, align 1
37900 // SIMD-ONLY0-NEXT:    [[UCX:%.*]] = alloca i8, align 1
37901 // SIMD-ONLY0-NEXT:    [[UCV:%.*]] = alloca i8, align 1
37902 // SIMD-ONLY0-NEXT:    [[UCR:%.*]] = alloca i8, align 1
37903 // SIMD-ONLY0-NEXT:    [[UCE:%.*]] = alloca i8, align 1
37904 // SIMD-ONLY0-NEXT:    [[UCD:%.*]] = alloca i8, align 1
37905 // SIMD-ONLY0-NEXT:    [[SX:%.*]] = alloca i16, align 2
37906 // SIMD-ONLY0-NEXT:    [[SV:%.*]] = alloca i16, align 2
37907 // SIMD-ONLY0-NEXT:    [[SR:%.*]] = alloca i16, align 2
37908 // SIMD-ONLY0-NEXT:    [[SE:%.*]] = alloca i16, align 2
37909 // SIMD-ONLY0-NEXT:    [[SD:%.*]] = alloca i16, align 2
37910 // SIMD-ONLY0-NEXT:    [[USX:%.*]] = alloca i16, align 2
37911 // SIMD-ONLY0-NEXT:    [[USV:%.*]] = alloca i16, align 2
37912 // SIMD-ONLY0-NEXT:    [[USR:%.*]] = alloca i16, align 2
37913 // SIMD-ONLY0-NEXT:    [[USE:%.*]] = alloca i16, align 2
37914 // SIMD-ONLY0-NEXT:    [[USD:%.*]] = alloca i16, align 2
37915 // SIMD-ONLY0-NEXT:    [[IX:%.*]] = alloca i32, align 4
37916 // SIMD-ONLY0-NEXT:    [[IV:%.*]] = alloca i32, align 4
37917 // SIMD-ONLY0-NEXT:    [[IR:%.*]] = alloca i32, align 4
37918 // SIMD-ONLY0-NEXT:    [[IE:%.*]] = alloca i32, align 4
37919 // SIMD-ONLY0-NEXT:    [[ID:%.*]] = alloca i32, align 4
37920 // SIMD-ONLY0-NEXT:    [[UIX:%.*]] = alloca i32, align 4
37921 // SIMD-ONLY0-NEXT:    [[UIV:%.*]] = alloca i32, align 4
37922 // SIMD-ONLY0-NEXT:    [[UIR:%.*]] = alloca i32, align 4
37923 // SIMD-ONLY0-NEXT:    [[UIE:%.*]] = alloca i32, align 4
37924 // SIMD-ONLY0-NEXT:    [[UID:%.*]] = alloca i32, align 4
37925 // SIMD-ONLY0-NEXT:    [[LX:%.*]] = alloca i64, align 8
37926 // SIMD-ONLY0-NEXT:    [[LV:%.*]] = alloca i64, align 8
37927 // SIMD-ONLY0-NEXT:    [[LR:%.*]] = alloca i64, align 8
37928 // SIMD-ONLY0-NEXT:    [[LE:%.*]] = alloca i64, align 8
37929 // SIMD-ONLY0-NEXT:    [[LD:%.*]] = alloca i64, align 8
37930 // SIMD-ONLY0-NEXT:    [[ULX:%.*]] = alloca i64, align 8
37931 // SIMD-ONLY0-NEXT:    [[ULV:%.*]] = alloca i64, align 8
37932 // SIMD-ONLY0-NEXT:    [[ULR:%.*]] = alloca i64, align 8
37933 // SIMD-ONLY0-NEXT:    [[ULE:%.*]] = alloca i64, align 8
37934 // SIMD-ONLY0-NEXT:    [[ULD:%.*]] = alloca i64, align 8
37935 // SIMD-ONLY0-NEXT:    [[LLX:%.*]] = alloca i64, align 8
37936 // SIMD-ONLY0-NEXT:    [[LLV:%.*]] = alloca i64, align 8
37937 // SIMD-ONLY0-NEXT:    [[LLR:%.*]] = alloca i64, align 8
37938 // SIMD-ONLY0-NEXT:    [[LLE:%.*]] = alloca i64, align 8
37939 // SIMD-ONLY0-NEXT:    [[LLD:%.*]] = alloca i64, align 8
37940 // SIMD-ONLY0-NEXT:    [[ULLX:%.*]] = alloca i64, align 8
37941 // SIMD-ONLY0-NEXT:    [[ULLV:%.*]] = alloca i64, align 8
37942 // SIMD-ONLY0-NEXT:    [[ULLR:%.*]] = alloca i64, align 8
37943 // SIMD-ONLY0-NEXT:    [[ULLE:%.*]] = alloca i64, align 8
37944 // SIMD-ONLY0-NEXT:    [[ULLD:%.*]] = alloca i64, align 8
37945 // SIMD-ONLY0-NEXT:    [[FX:%.*]] = alloca float, align 4
37946 // SIMD-ONLY0-NEXT:    [[FV:%.*]] = alloca float, align 4
37947 // SIMD-ONLY0-NEXT:    [[FE:%.*]] = alloca float, align 4
37948 // SIMD-ONLY0-NEXT:    [[FD:%.*]] = alloca float, align 4
37949 // SIMD-ONLY0-NEXT:    [[DX:%.*]] = alloca double, align 8
37950 // SIMD-ONLY0-NEXT:    [[DV:%.*]] = alloca double, align 8
37951 // SIMD-ONLY0-NEXT:    [[DE:%.*]] = alloca double, align 8
37952 // SIMD-ONLY0-NEXT:    [[DD:%.*]] = alloca double, align 8
37953 // SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = load i8, ptr [[CX]], align 1
37954 // SIMD-ONLY0-NEXT:    store i8 [[TMP0]], ptr [[CV]], align 1
37955 // SIMD-ONLY0-NEXT:    [[TMP1:%.*]] = load i8, ptr [[CE]], align 1
37956 // SIMD-ONLY0-NEXT:    [[CONV:%.*]] = sext i8 [[TMP1]] to i32
37957 // SIMD-ONLY0-NEXT:    [[TMP2:%.*]] = load i8, ptr [[CX]], align 1
37958 // SIMD-ONLY0-NEXT:    [[CONV1:%.*]] = sext i8 [[TMP2]] to i32
37959 // SIMD-ONLY0-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[CONV]], [[CONV1]]
37960 // SIMD-ONLY0-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
37961 // SIMD-ONLY0:       if.then:
37962 // SIMD-ONLY0-NEXT:    [[TMP3:%.*]] = load i8, ptr [[CE]], align 1
37963 // SIMD-ONLY0-NEXT:    store i8 [[TMP3]], ptr [[CX]], align 1
37964 // SIMD-ONLY0-NEXT:    br label [[IF_END]]
37965 // SIMD-ONLY0:       if.end:
37966 // SIMD-ONLY0-NEXT:    [[TMP4:%.*]] = load i8, ptr [[CX]], align 1
37967 // SIMD-ONLY0-NEXT:    store i8 [[TMP4]], ptr [[CV]], align 1
37968 // SIMD-ONLY0-NEXT:    [[TMP5:%.*]] = load i8, ptr [[CX]], align 1
37969 // SIMD-ONLY0-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
37970 // SIMD-ONLY0-NEXT:    [[TMP6:%.*]] = load i8, ptr [[CE]], align 1
37971 // SIMD-ONLY0-NEXT:    [[CONV4:%.*]] = sext i8 [[TMP6]] to i32
37972 // SIMD-ONLY0-NEXT:    [[CMP5:%.*]] = icmp sgt i32 [[CONV3]], [[CONV4]]
37973 // SIMD-ONLY0-NEXT:    br i1 [[CMP5]], label [[IF_THEN7:%.*]], label [[IF_END8:%.*]]
37974 // SIMD-ONLY0:       if.then7:
37975 // SIMD-ONLY0-NEXT:    [[TMP7:%.*]] = load i8, ptr [[CE]], align 1
37976 // SIMD-ONLY0-NEXT:    store i8 [[TMP7]], ptr [[CX]], align 1
37977 // SIMD-ONLY0-NEXT:    br label [[IF_END8]]
37978 // SIMD-ONLY0:       if.end8:
37979 // SIMD-ONLY0-NEXT:    [[TMP8:%.*]] = load i8, ptr [[CX]], align 1
37980 // SIMD-ONLY0-NEXT:    store i8 [[TMP8]], ptr [[CV]], align 1
37981 // SIMD-ONLY0-NEXT:    [[TMP9:%.*]] = load i8, ptr [[CE]], align 1
37982 // SIMD-ONLY0-NEXT:    [[CONV9:%.*]] = sext i8 [[TMP9]] to i32
37983 // SIMD-ONLY0-NEXT:    [[TMP10:%.*]] = load i8, ptr [[CX]], align 1
37984 // SIMD-ONLY0-NEXT:    [[CONV10:%.*]] = sext i8 [[TMP10]] to i32
37985 // SIMD-ONLY0-NEXT:    [[CMP11:%.*]] = icmp slt i32 [[CONV9]], [[CONV10]]
37986 // SIMD-ONLY0-NEXT:    br i1 [[CMP11]], label [[IF_THEN13:%.*]], label [[IF_END14:%.*]]
37987 // SIMD-ONLY0:       if.then13:
37988 // SIMD-ONLY0-NEXT:    [[TMP11:%.*]] = load i8, ptr [[CE]], align 1
37989 // SIMD-ONLY0-NEXT:    store i8 [[TMP11]], ptr [[CX]], align 1
37990 // SIMD-ONLY0-NEXT:    br label [[IF_END14]]
37991 // SIMD-ONLY0:       if.end14:
37992 // SIMD-ONLY0-NEXT:    [[TMP12:%.*]] = load i8, ptr [[CX]], align 1
37993 // SIMD-ONLY0-NEXT:    store i8 [[TMP12]], ptr [[CV]], align 1
37994 // SIMD-ONLY0-NEXT:    [[TMP13:%.*]] = load i8, ptr [[CX]], align 1
37995 // SIMD-ONLY0-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP13]] to i32
37996 // SIMD-ONLY0-NEXT:    [[TMP14:%.*]] = load i8, ptr [[CE]], align 1
37997 // SIMD-ONLY0-NEXT:    [[CONV16:%.*]] = sext i8 [[TMP14]] to i32
37998 // SIMD-ONLY0-NEXT:    [[CMP17:%.*]] = icmp slt i32 [[CONV15]], [[CONV16]]
37999 // SIMD-ONLY0-NEXT:    br i1 [[CMP17]], label [[IF_THEN19:%.*]], label [[IF_END20:%.*]]
38000 // SIMD-ONLY0:       if.then19:
38001 // SIMD-ONLY0-NEXT:    [[TMP15:%.*]] = load i8, ptr [[CE]], align 1
38002 // SIMD-ONLY0-NEXT:    store i8 [[TMP15]], ptr [[CX]], align 1
38003 // SIMD-ONLY0-NEXT:    br label [[IF_END20]]
38004 // SIMD-ONLY0:       if.end20:
38005 // SIMD-ONLY0-NEXT:    [[TMP16:%.*]] = load i8, ptr [[CX]], align 1
38006 // SIMD-ONLY0-NEXT:    store i8 [[TMP16]], ptr [[CV]], align 1
38007 // SIMD-ONLY0-NEXT:    [[TMP17:%.*]] = load i8, ptr [[CX]], align 1
38008 // SIMD-ONLY0-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP17]] to i32
38009 // SIMD-ONLY0-NEXT:    [[TMP18:%.*]] = load i8, ptr [[CE]], align 1
38010 // SIMD-ONLY0-NEXT:    [[CONV22:%.*]] = sext i8 [[TMP18]] to i32
38011 // SIMD-ONLY0-NEXT:    [[CMP23:%.*]] = icmp eq i32 [[CONV21]], [[CONV22]]
38012 // SIMD-ONLY0-NEXT:    br i1 [[CMP23]], label [[IF_THEN25:%.*]], label [[IF_END26:%.*]]
38013 // SIMD-ONLY0:       if.then25:
38014 // SIMD-ONLY0-NEXT:    [[TMP19:%.*]] = load i8, ptr [[CD]], align 1
38015 // SIMD-ONLY0-NEXT:    store i8 [[TMP19]], ptr [[CX]], align 1
38016 // SIMD-ONLY0-NEXT:    br label [[IF_END26]]
38017 // SIMD-ONLY0:       if.end26:
38018 // SIMD-ONLY0-NEXT:    [[TMP20:%.*]] = load i8, ptr [[CX]], align 1
38019 // SIMD-ONLY0-NEXT:    store i8 [[TMP20]], ptr [[CV]], align 1
38020 // SIMD-ONLY0-NEXT:    [[TMP21:%.*]] = load i8, ptr [[CE]], align 1
38021 // SIMD-ONLY0-NEXT:    [[CONV27:%.*]] = sext i8 [[TMP21]] to i32
38022 // SIMD-ONLY0-NEXT:    [[TMP22:%.*]] = load i8, ptr [[CX]], align 1
38023 // SIMD-ONLY0-NEXT:    [[CONV28:%.*]] = sext i8 [[TMP22]] to i32
38024 // SIMD-ONLY0-NEXT:    [[CMP29:%.*]] = icmp eq i32 [[CONV27]], [[CONV28]]
38025 // SIMD-ONLY0-NEXT:    br i1 [[CMP29]], label [[IF_THEN31:%.*]], label [[IF_END32:%.*]]
38026 // SIMD-ONLY0:       if.then31:
38027 // SIMD-ONLY0-NEXT:    [[TMP23:%.*]] = load i8, ptr [[CD]], align 1
38028 // SIMD-ONLY0-NEXT:    store i8 [[TMP23]], ptr [[CX]], align 1
38029 // SIMD-ONLY0-NEXT:    br label [[IF_END32]]
38030 // SIMD-ONLY0:       if.end32:
38031 // SIMD-ONLY0-NEXT:    [[TMP24:%.*]] = load i8, ptr [[CE]], align 1
38032 // SIMD-ONLY0-NEXT:    [[CONV33:%.*]] = sext i8 [[TMP24]] to i32
38033 // SIMD-ONLY0-NEXT:    [[TMP25:%.*]] = load i8, ptr [[CX]], align 1
38034 // SIMD-ONLY0-NEXT:    [[CONV34:%.*]] = sext i8 [[TMP25]] to i32
38035 // SIMD-ONLY0-NEXT:    [[CMP35:%.*]] = icmp sgt i32 [[CONV33]], [[CONV34]]
38036 // SIMD-ONLY0-NEXT:    br i1 [[CMP35]], label [[IF_THEN37:%.*]], label [[IF_END38:%.*]]
38037 // SIMD-ONLY0:       if.then37:
38038 // SIMD-ONLY0-NEXT:    [[TMP26:%.*]] = load i8, ptr [[CE]], align 1
38039 // SIMD-ONLY0-NEXT:    store i8 [[TMP26]], ptr [[CX]], align 1
38040 // SIMD-ONLY0-NEXT:    br label [[IF_END38]]
38041 // SIMD-ONLY0:       if.end38:
38042 // SIMD-ONLY0-NEXT:    [[TMP27:%.*]] = load i8, ptr [[CX]], align 1
38043 // SIMD-ONLY0-NEXT:    store i8 [[TMP27]], ptr [[CV]], align 1
38044 // SIMD-ONLY0-NEXT:    [[TMP28:%.*]] = load i8, ptr [[CX]], align 1
38045 // SIMD-ONLY0-NEXT:    [[CONV39:%.*]] = sext i8 [[TMP28]] to i32
38046 // SIMD-ONLY0-NEXT:    [[TMP29:%.*]] = load i8, ptr [[CE]], align 1
38047 // SIMD-ONLY0-NEXT:    [[CONV40:%.*]] = sext i8 [[TMP29]] to i32
38048 // SIMD-ONLY0-NEXT:    [[CMP41:%.*]] = icmp sgt i32 [[CONV39]], [[CONV40]]
38049 // SIMD-ONLY0-NEXT:    br i1 [[CMP41]], label [[IF_THEN43:%.*]], label [[IF_END44:%.*]]
38050 // SIMD-ONLY0:       if.then43:
38051 // SIMD-ONLY0-NEXT:    [[TMP30:%.*]] = load i8, ptr [[CE]], align 1
38052 // SIMD-ONLY0-NEXT:    store i8 [[TMP30]], ptr [[CX]], align 1
38053 // SIMD-ONLY0-NEXT:    br label [[IF_END44]]
38054 // SIMD-ONLY0:       if.end44:
38055 // SIMD-ONLY0-NEXT:    [[TMP31:%.*]] = load i8, ptr [[CX]], align 1
38056 // SIMD-ONLY0-NEXT:    store i8 [[TMP31]], ptr [[CV]], align 1
38057 // SIMD-ONLY0-NEXT:    [[TMP32:%.*]] = load i8, ptr [[CE]], align 1
38058 // SIMD-ONLY0-NEXT:    [[CONV45:%.*]] = sext i8 [[TMP32]] to i32
38059 // SIMD-ONLY0-NEXT:    [[TMP33:%.*]] = load i8, ptr [[CX]], align 1
38060 // SIMD-ONLY0-NEXT:    [[CONV46:%.*]] = sext i8 [[TMP33]] to i32
38061 // SIMD-ONLY0-NEXT:    [[CMP47:%.*]] = icmp slt i32 [[CONV45]], [[CONV46]]
38062 // SIMD-ONLY0-NEXT:    br i1 [[CMP47]], label [[IF_THEN49:%.*]], label [[IF_END50:%.*]]
38063 // SIMD-ONLY0:       if.then49:
38064 // SIMD-ONLY0-NEXT:    [[TMP34:%.*]] = load i8, ptr [[CE]], align 1
38065 // SIMD-ONLY0-NEXT:    store i8 [[TMP34]], ptr [[CX]], align 1
38066 // SIMD-ONLY0-NEXT:    br label [[IF_END50]]
38067 // SIMD-ONLY0:       if.end50:
38068 // SIMD-ONLY0-NEXT:    [[TMP35:%.*]] = load i8, ptr [[CX]], align 1
38069 // SIMD-ONLY0-NEXT:    store i8 [[TMP35]], ptr [[CV]], align 1
38070 // SIMD-ONLY0-NEXT:    [[TMP36:%.*]] = load i8, ptr [[CX]], align 1
38071 // SIMD-ONLY0-NEXT:    [[CONV51:%.*]] = sext i8 [[TMP36]] to i32
38072 // SIMD-ONLY0-NEXT:    [[TMP37:%.*]] = load i8, ptr [[CE]], align 1
38073 // SIMD-ONLY0-NEXT:    [[CONV52:%.*]] = sext i8 [[TMP37]] to i32
38074 // SIMD-ONLY0-NEXT:    [[CMP53:%.*]] = icmp slt i32 [[CONV51]], [[CONV52]]
38075 // SIMD-ONLY0-NEXT:    br i1 [[CMP53]], label [[IF_THEN55:%.*]], label [[IF_END56:%.*]]
38076 // SIMD-ONLY0:       if.then55:
38077 // SIMD-ONLY0-NEXT:    [[TMP38:%.*]] = load i8, ptr [[CE]], align 1
38078 // SIMD-ONLY0-NEXT:    store i8 [[TMP38]], ptr [[CX]], align 1
38079 // SIMD-ONLY0-NEXT:    br label [[IF_END56]]
38080 // SIMD-ONLY0:       if.end56:
38081 // SIMD-ONLY0-NEXT:    [[TMP39:%.*]] = load i8, ptr [[CX]], align 1
38082 // SIMD-ONLY0-NEXT:    store i8 [[TMP39]], ptr [[CV]], align 1
38083 // SIMD-ONLY0-NEXT:    [[TMP40:%.*]] = load i8, ptr [[CX]], align 1
38084 // SIMD-ONLY0-NEXT:    [[CONV57:%.*]] = sext i8 [[TMP40]] to i32
38085 // SIMD-ONLY0-NEXT:    [[TMP41:%.*]] = load i8, ptr [[CE]], align 1
38086 // SIMD-ONLY0-NEXT:    [[CONV58:%.*]] = sext i8 [[TMP41]] to i32
38087 // SIMD-ONLY0-NEXT:    [[CMP59:%.*]] = icmp eq i32 [[CONV57]], [[CONV58]]
38088 // SIMD-ONLY0-NEXT:    br i1 [[CMP59]], label [[IF_THEN61:%.*]], label [[IF_END62:%.*]]
38089 // SIMD-ONLY0:       if.then61:
38090 // SIMD-ONLY0-NEXT:    [[TMP42:%.*]] = load i8, ptr [[CD]], align 1
38091 // SIMD-ONLY0-NEXT:    store i8 [[TMP42]], ptr [[CX]], align 1
38092 // SIMD-ONLY0-NEXT:    br label [[IF_END62]]
38093 // SIMD-ONLY0:       if.end62:
38094 // SIMD-ONLY0-NEXT:    [[TMP43:%.*]] = load i8, ptr [[CX]], align 1
38095 // SIMD-ONLY0-NEXT:    store i8 [[TMP43]], ptr [[CV]], align 1
38096 // SIMD-ONLY0-NEXT:    [[TMP44:%.*]] = load i8, ptr [[CE]], align 1
38097 // SIMD-ONLY0-NEXT:    [[CONV63:%.*]] = sext i8 [[TMP44]] to i32
38098 // SIMD-ONLY0-NEXT:    [[TMP45:%.*]] = load i8, ptr [[CX]], align 1
38099 // SIMD-ONLY0-NEXT:    [[CONV64:%.*]] = sext i8 [[TMP45]] to i32
38100 // SIMD-ONLY0-NEXT:    [[CMP65:%.*]] = icmp eq i32 [[CONV63]], [[CONV64]]
38101 // SIMD-ONLY0-NEXT:    br i1 [[CMP65]], label [[IF_THEN67:%.*]], label [[IF_END68:%.*]]
38102 // SIMD-ONLY0:       if.then67:
38103 // SIMD-ONLY0-NEXT:    [[TMP46:%.*]] = load i8, ptr [[CD]], align 1
38104 // SIMD-ONLY0-NEXT:    store i8 [[TMP46]], ptr [[CX]], align 1
38105 // SIMD-ONLY0-NEXT:    br label [[IF_END68]]
38106 // SIMD-ONLY0:       if.end68:
38107 // SIMD-ONLY0-NEXT:    [[TMP47:%.*]] = load i8, ptr [[CX]], align 1
38108 // SIMD-ONLY0-NEXT:    store i8 [[TMP47]], ptr [[CV]], align 1
38109 // SIMD-ONLY0-NEXT:    [[TMP48:%.*]] = load i8, ptr [[CX]], align 1
38110 // SIMD-ONLY0-NEXT:    [[CONV69:%.*]] = sext i8 [[TMP48]] to i32
38111 // SIMD-ONLY0-NEXT:    [[TMP49:%.*]] = load i8, ptr [[CE]], align 1
38112 // SIMD-ONLY0-NEXT:    [[CONV70:%.*]] = sext i8 [[TMP49]] to i32
38113 // SIMD-ONLY0-NEXT:    [[CMP71:%.*]] = icmp eq i32 [[CONV69]], [[CONV70]]
38114 // SIMD-ONLY0-NEXT:    br i1 [[CMP71]], label [[IF_THEN73:%.*]], label [[IF_ELSE:%.*]]
38115 // SIMD-ONLY0:       if.then73:
38116 // SIMD-ONLY0-NEXT:    [[TMP50:%.*]] = load i8, ptr [[CD]], align 1
38117 // SIMD-ONLY0-NEXT:    store i8 [[TMP50]], ptr [[CX]], align 1
38118 // SIMD-ONLY0-NEXT:    br label [[IF_END74:%.*]]
38119 // SIMD-ONLY0:       if.else:
38120 // SIMD-ONLY0-NEXT:    [[TMP51:%.*]] = load i8, ptr [[CX]], align 1
38121 // SIMD-ONLY0-NEXT:    store i8 [[TMP51]], ptr [[CV]], align 1
38122 // SIMD-ONLY0-NEXT:    br label [[IF_END74]]
38123 // SIMD-ONLY0:       if.end74:
38124 // SIMD-ONLY0-NEXT:    [[TMP52:%.*]] = load i8, ptr [[CE]], align 1
38125 // SIMD-ONLY0-NEXT:    [[CONV75:%.*]] = sext i8 [[TMP52]] to i32
38126 // SIMD-ONLY0-NEXT:    [[TMP53:%.*]] = load i8, ptr [[CX]], align 1
38127 // SIMD-ONLY0-NEXT:    [[CONV76:%.*]] = sext i8 [[TMP53]] to i32
38128 // SIMD-ONLY0-NEXT:    [[CMP77:%.*]] = icmp eq i32 [[CONV75]], [[CONV76]]
38129 // SIMD-ONLY0-NEXT:    br i1 [[CMP77]], label [[IF_THEN79:%.*]], label [[IF_ELSE80:%.*]]
38130 // SIMD-ONLY0:       if.then79:
38131 // SIMD-ONLY0-NEXT:    [[TMP54:%.*]] = load i8, ptr [[CD]], align 1
38132 // SIMD-ONLY0-NEXT:    store i8 [[TMP54]], ptr [[CX]], align 1
38133 // SIMD-ONLY0-NEXT:    br label [[IF_END81:%.*]]
38134 // SIMD-ONLY0:       if.else80:
38135 // SIMD-ONLY0-NEXT:    [[TMP55:%.*]] = load i8, ptr [[CX]], align 1
38136 // SIMD-ONLY0-NEXT:    store i8 [[TMP55]], ptr [[CV]], align 1
38137 // SIMD-ONLY0-NEXT:    br label [[IF_END81]]
38138 // SIMD-ONLY0:       if.end81:
38139 // SIMD-ONLY0-NEXT:    [[TMP56:%.*]] = load i8, ptr [[CX]], align 1
38140 // SIMD-ONLY0-NEXT:    [[CONV82:%.*]] = sext i8 [[TMP56]] to i32
38141 // SIMD-ONLY0-NEXT:    [[TMP57:%.*]] = load i8, ptr [[CE]], align 1
38142 // SIMD-ONLY0-NEXT:    [[CONV83:%.*]] = sext i8 [[TMP57]] to i32
38143 // SIMD-ONLY0-NEXT:    [[CMP84:%.*]] = icmp eq i32 [[CONV82]], [[CONV83]]
38144 // SIMD-ONLY0-NEXT:    [[CONV85:%.*]] = zext i1 [[CMP84]] to i32
38145 // SIMD-ONLY0-NEXT:    [[CONV86:%.*]] = trunc i32 [[CONV85]] to i8
38146 // SIMD-ONLY0-NEXT:    store i8 [[CONV86]], ptr [[CR]], align 1
38147 // SIMD-ONLY0-NEXT:    [[TMP58:%.*]] = load i8, ptr [[CR]], align 1
38148 // SIMD-ONLY0-NEXT:    [[TOBOOL:%.*]] = icmp ne i8 [[TMP58]], 0
38149 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL]], label [[IF_THEN87:%.*]], label [[IF_END88:%.*]]
38150 // SIMD-ONLY0:       if.then87:
38151 // SIMD-ONLY0-NEXT:    [[TMP59:%.*]] = load i8, ptr [[CD]], align 1
38152 // SIMD-ONLY0-NEXT:    store i8 [[TMP59]], ptr [[CX]], align 1
38153 // SIMD-ONLY0-NEXT:    br label [[IF_END88]]
38154 // SIMD-ONLY0:       if.end88:
38155 // SIMD-ONLY0-NEXT:    [[TMP60:%.*]] = load i8, ptr [[CE]], align 1
38156 // SIMD-ONLY0-NEXT:    [[CONV89:%.*]] = sext i8 [[TMP60]] to i32
38157 // SIMD-ONLY0-NEXT:    [[TMP61:%.*]] = load i8, ptr [[CX]], align 1
38158 // SIMD-ONLY0-NEXT:    [[CONV90:%.*]] = sext i8 [[TMP61]] to i32
38159 // SIMD-ONLY0-NEXT:    [[CMP91:%.*]] = icmp eq i32 [[CONV89]], [[CONV90]]
38160 // SIMD-ONLY0-NEXT:    [[CONV92:%.*]] = zext i1 [[CMP91]] to i32
38161 // SIMD-ONLY0-NEXT:    [[CONV93:%.*]] = trunc i32 [[CONV92]] to i8
38162 // SIMD-ONLY0-NEXT:    store i8 [[CONV93]], ptr [[CR]], align 1
38163 // SIMD-ONLY0-NEXT:    [[TMP62:%.*]] = load i8, ptr [[CR]], align 1
38164 // SIMD-ONLY0-NEXT:    [[TOBOOL94:%.*]] = icmp ne i8 [[TMP62]], 0
38165 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL94]], label [[IF_THEN95:%.*]], label [[IF_END96:%.*]]
38166 // SIMD-ONLY0:       if.then95:
38167 // SIMD-ONLY0-NEXT:    [[TMP63:%.*]] = load i8, ptr [[CD]], align 1
38168 // SIMD-ONLY0-NEXT:    store i8 [[TMP63]], ptr [[CX]], align 1
38169 // SIMD-ONLY0-NEXT:    br label [[IF_END96]]
38170 // SIMD-ONLY0:       if.end96:
38171 // SIMD-ONLY0-NEXT:    [[TMP64:%.*]] = load i8, ptr [[CX]], align 1
38172 // SIMD-ONLY0-NEXT:    [[CONV97:%.*]] = sext i8 [[TMP64]] to i32
38173 // SIMD-ONLY0-NEXT:    [[TMP65:%.*]] = load i8, ptr [[CE]], align 1
38174 // SIMD-ONLY0-NEXT:    [[CONV98:%.*]] = sext i8 [[TMP65]] to i32
38175 // SIMD-ONLY0-NEXT:    [[CMP99:%.*]] = icmp eq i32 [[CONV97]], [[CONV98]]
38176 // SIMD-ONLY0-NEXT:    [[CONV100:%.*]] = zext i1 [[CMP99]] to i32
38177 // SIMD-ONLY0-NEXT:    [[CONV101:%.*]] = trunc i32 [[CONV100]] to i8
38178 // SIMD-ONLY0-NEXT:    store i8 [[CONV101]], ptr [[CR]], align 1
38179 // SIMD-ONLY0-NEXT:    [[TMP66:%.*]] = load i8, ptr [[CR]], align 1
38180 // SIMD-ONLY0-NEXT:    [[TOBOOL102:%.*]] = icmp ne i8 [[TMP66]], 0
38181 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL102]], label [[IF_THEN103:%.*]], label [[IF_ELSE104:%.*]]
38182 // SIMD-ONLY0:       if.then103:
38183 // SIMD-ONLY0-NEXT:    [[TMP67:%.*]] = load i8, ptr [[CD]], align 1
38184 // SIMD-ONLY0-NEXT:    store i8 [[TMP67]], ptr [[CX]], align 1
38185 // SIMD-ONLY0-NEXT:    br label [[IF_END105:%.*]]
38186 // SIMD-ONLY0:       if.else104:
38187 // SIMD-ONLY0-NEXT:    [[TMP68:%.*]] = load i8, ptr [[CX]], align 1
38188 // SIMD-ONLY0-NEXT:    store i8 [[TMP68]], ptr [[CV]], align 1
38189 // SIMD-ONLY0-NEXT:    br label [[IF_END105]]
38190 // SIMD-ONLY0:       if.end105:
38191 // SIMD-ONLY0-NEXT:    [[TMP69:%.*]] = load i8, ptr [[CE]], align 1
38192 // SIMD-ONLY0-NEXT:    [[CONV106:%.*]] = sext i8 [[TMP69]] to i32
38193 // SIMD-ONLY0-NEXT:    [[TMP70:%.*]] = load i8, ptr [[CX]], align 1
38194 // SIMD-ONLY0-NEXT:    [[CONV107:%.*]] = sext i8 [[TMP70]] to i32
38195 // SIMD-ONLY0-NEXT:    [[CMP108:%.*]] = icmp eq i32 [[CONV106]], [[CONV107]]
38196 // SIMD-ONLY0-NEXT:    [[CONV109:%.*]] = zext i1 [[CMP108]] to i32
38197 // SIMD-ONLY0-NEXT:    [[CONV110:%.*]] = trunc i32 [[CONV109]] to i8
38198 // SIMD-ONLY0-NEXT:    store i8 [[CONV110]], ptr [[CR]], align 1
38199 // SIMD-ONLY0-NEXT:    [[TMP71:%.*]] = load i8, ptr [[CR]], align 1
38200 // SIMD-ONLY0-NEXT:    [[TOBOOL111:%.*]] = icmp ne i8 [[TMP71]], 0
38201 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL111]], label [[IF_THEN112:%.*]], label [[IF_ELSE113:%.*]]
38202 // SIMD-ONLY0:       if.then112:
38203 // SIMD-ONLY0-NEXT:    [[TMP72:%.*]] = load i8, ptr [[CD]], align 1
38204 // SIMD-ONLY0-NEXT:    store i8 [[TMP72]], ptr [[CX]], align 1
38205 // SIMD-ONLY0-NEXT:    br label [[IF_END114:%.*]]
38206 // SIMD-ONLY0:       if.else113:
38207 // SIMD-ONLY0-NEXT:    [[TMP73:%.*]] = load i8, ptr [[CX]], align 1
38208 // SIMD-ONLY0-NEXT:    store i8 [[TMP73]], ptr [[CV]], align 1
38209 // SIMD-ONLY0-NEXT:    br label [[IF_END114]]
38210 // SIMD-ONLY0:       if.end114:
38211 // SIMD-ONLY0-NEXT:    [[TMP74:%.*]] = load i8, ptr [[CX]], align 1
38212 // SIMD-ONLY0-NEXT:    store i8 [[TMP74]], ptr [[CV]], align 1
38213 // SIMD-ONLY0-NEXT:    [[TMP75:%.*]] = load i8, ptr [[CE]], align 1
38214 // SIMD-ONLY0-NEXT:    [[CONV115:%.*]] = sext i8 [[TMP75]] to i32
38215 // SIMD-ONLY0-NEXT:    [[TMP76:%.*]] = load i8, ptr [[CX]], align 1
38216 // SIMD-ONLY0-NEXT:    [[CONV116:%.*]] = sext i8 [[TMP76]] to i32
38217 // SIMD-ONLY0-NEXT:    [[CMP117:%.*]] = icmp sgt i32 [[CONV115]], [[CONV116]]
38218 // SIMD-ONLY0-NEXT:    br i1 [[CMP117]], label [[IF_THEN119:%.*]], label [[IF_END120:%.*]]
38219 // SIMD-ONLY0:       if.then119:
38220 // SIMD-ONLY0-NEXT:    [[TMP77:%.*]] = load i8, ptr [[CE]], align 1
38221 // SIMD-ONLY0-NEXT:    store i8 [[TMP77]], ptr [[CX]], align 1
38222 // SIMD-ONLY0-NEXT:    br label [[IF_END120]]
38223 // SIMD-ONLY0:       if.end120:
38224 // SIMD-ONLY0-NEXT:    [[TMP78:%.*]] = load i8, ptr [[CX]], align 1
38225 // SIMD-ONLY0-NEXT:    store i8 [[TMP78]], ptr [[CV]], align 1
38226 // SIMD-ONLY0-NEXT:    [[TMP79:%.*]] = load i8, ptr [[CX]], align 1
38227 // SIMD-ONLY0-NEXT:    [[CONV121:%.*]] = sext i8 [[TMP79]] to i32
38228 // SIMD-ONLY0-NEXT:    [[TMP80:%.*]] = load i8, ptr [[CE]], align 1
38229 // SIMD-ONLY0-NEXT:    [[CONV122:%.*]] = sext i8 [[TMP80]] to i32
38230 // SIMD-ONLY0-NEXT:    [[CMP123:%.*]] = icmp sgt i32 [[CONV121]], [[CONV122]]
38231 // SIMD-ONLY0-NEXT:    br i1 [[CMP123]], label [[IF_THEN125:%.*]], label [[IF_END126:%.*]]
38232 // SIMD-ONLY0:       if.then125:
38233 // SIMD-ONLY0-NEXT:    [[TMP81:%.*]] = load i8, ptr [[CE]], align 1
38234 // SIMD-ONLY0-NEXT:    store i8 [[TMP81]], ptr [[CX]], align 1
38235 // SIMD-ONLY0-NEXT:    br label [[IF_END126]]
38236 // SIMD-ONLY0:       if.end126:
38237 // SIMD-ONLY0-NEXT:    [[TMP82:%.*]] = load i8, ptr [[CX]], align 1
38238 // SIMD-ONLY0-NEXT:    store i8 [[TMP82]], ptr [[CV]], align 1
38239 // SIMD-ONLY0-NEXT:    [[TMP83:%.*]] = load i8, ptr [[CE]], align 1
38240 // SIMD-ONLY0-NEXT:    [[CONV127:%.*]] = sext i8 [[TMP83]] to i32
38241 // SIMD-ONLY0-NEXT:    [[TMP84:%.*]] = load i8, ptr [[CX]], align 1
38242 // SIMD-ONLY0-NEXT:    [[CONV128:%.*]] = sext i8 [[TMP84]] to i32
38243 // SIMD-ONLY0-NEXT:    [[CMP129:%.*]] = icmp slt i32 [[CONV127]], [[CONV128]]
38244 // SIMD-ONLY0-NEXT:    br i1 [[CMP129]], label [[IF_THEN131:%.*]], label [[IF_END132:%.*]]
38245 // SIMD-ONLY0:       if.then131:
38246 // SIMD-ONLY0-NEXT:    [[TMP85:%.*]] = load i8, ptr [[CE]], align 1
38247 // SIMD-ONLY0-NEXT:    store i8 [[TMP85]], ptr [[CX]], align 1
38248 // SIMD-ONLY0-NEXT:    br label [[IF_END132]]
38249 // SIMD-ONLY0:       if.end132:
38250 // SIMD-ONLY0-NEXT:    [[TMP86:%.*]] = load i8, ptr [[CX]], align 1
38251 // SIMD-ONLY0-NEXT:    store i8 [[TMP86]], ptr [[CV]], align 1
38252 // SIMD-ONLY0-NEXT:    [[TMP87:%.*]] = load i8, ptr [[CX]], align 1
38253 // SIMD-ONLY0-NEXT:    [[CONV133:%.*]] = sext i8 [[TMP87]] to i32
38254 // SIMD-ONLY0-NEXT:    [[TMP88:%.*]] = load i8, ptr [[CE]], align 1
38255 // SIMD-ONLY0-NEXT:    [[CONV134:%.*]] = sext i8 [[TMP88]] to i32
38256 // SIMD-ONLY0-NEXT:    [[CMP135:%.*]] = icmp slt i32 [[CONV133]], [[CONV134]]
38257 // SIMD-ONLY0-NEXT:    br i1 [[CMP135]], label [[IF_THEN137:%.*]], label [[IF_END138:%.*]]
38258 // SIMD-ONLY0:       if.then137:
38259 // SIMD-ONLY0-NEXT:    [[TMP89:%.*]] = load i8, ptr [[CE]], align 1
38260 // SIMD-ONLY0-NEXT:    store i8 [[TMP89]], ptr [[CX]], align 1
38261 // SIMD-ONLY0-NEXT:    br label [[IF_END138]]
38262 // SIMD-ONLY0:       if.end138:
38263 // SIMD-ONLY0-NEXT:    [[TMP90:%.*]] = load i8, ptr [[CX]], align 1
38264 // SIMD-ONLY0-NEXT:    store i8 [[TMP90]], ptr [[CV]], align 1
38265 // SIMD-ONLY0-NEXT:    [[TMP91:%.*]] = load i8, ptr [[CX]], align 1
38266 // SIMD-ONLY0-NEXT:    [[CONV139:%.*]] = sext i8 [[TMP91]] to i32
38267 // SIMD-ONLY0-NEXT:    [[TMP92:%.*]] = load i8, ptr [[CE]], align 1
38268 // SIMD-ONLY0-NEXT:    [[CONV140:%.*]] = sext i8 [[TMP92]] to i32
38269 // SIMD-ONLY0-NEXT:    [[CMP141:%.*]] = icmp eq i32 [[CONV139]], [[CONV140]]
38270 // SIMD-ONLY0-NEXT:    br i1 [[CMP141]], label [[IF_THEN143:%.*]], label [[IF_END144:%.*]]
38271 // SIMD-ONLY0:       if.then143:
38272 // SIMD-ONLY0-NEXT:    [[TMP93:%.*]] = load i8, ptr [[CD]], align 1
38273 // SIMD-ONLY0-NEXT:    store i8 [[TMP93]], ptr [[CX]], align 1
38274 // SIMD-ONLY0-NEXT:    br label [[IF_END144]]
38275 // SIMD-ONLY0:       if.end144:
38276 // SIMD-ONLY0-NEXT:    [[TMP94:%.*]] = load i8, ptr [[CX]], align 1
38277 // SIMD-ONLY0-NEXT:    store i8 [[TMP94]], ptr [[CV]], align 1
38278 // SIMD-ONLY0-NEXT:    [[TMP95:%.*]] = load i8, ptr [[CE]], align 1
38279 // SIMD-ONLY0-NEXT:    [[CONV145:%.*]] = sext i8 [[TMP95]] to i32
38280 // SIMD-ONLY0-NEXT:    [[TMP96:%.*]] = load i8, ptr [[CX]], align 1
38281 // SIMD-ONLY0-NEXT:    [[CONV146:%.*]] = sext i8 [[TMP96]] to i32
38282 // SIMD-ONLY0-NEXT:    [[CMP147:%.*]] = icmp eq i32 [[CONV145]], [[CONV146]]
38283 // SIMD-ONLY0-NEXT:    br i1 [[CMP147]], label [[IF_THEN149:%.*]], label [[IF_END150:%.*]]
38284 // SIMD-ONLY0:       if.then149:
38285 // SIMD-ONLY0-NEXT:    [[TMP97:%.*]] = load i8, ptr [[CD]], align 1
38286 // SIMD-ONLY0-NEXT:    store i8 [[TMP97]], ptr [[CX]], align 1
38287 // SIMD-ONLY0-NEXT:    br label [[IF_END150]]
38288 // SIMD-ONLY0:       if.end150:
38289 // SIMD-ONLY0-NEXT:    [[TMP98:%.*]] = load i8, ptr [[CE]], align 1
38290 // SIMD-ONLY0-NEXT:    [[CONV151:%.*]] = sext i8 [[TMP98]] to i32
38291 // SIMD-ONLY0-NEXT:    [[TMP99:%.*]] = load i8, ptr [[CX]], align 1
38292 // SIMD-ONLY0-NEXT:    [[CONV152:%.*]] = sext i8 [[TMP99]] to i32
38293 // SIMD-ONLY0-NEXT:    [[CMP153:%.*]] = icmp sgt i32 [[CONV151]], [[CONV152]]
38294 // SIMD-ONLY0-NEXT:    br i1 [[CMP153]], label [[IF_THEN155:%.*]], label [[IF_END156:%.*]]
38295 // SIMD-ONLY0:       if.then155:
38296 // SIMD-ONLY0-NEXT:    [[TMP100:%.*]] = load i8, ptr [[CE]], align 1
38297 // SIMD-ONLY0-NEXT:    store i8 [[TMP100]], ptr [[CX]], align 1
38298 // SIMD-ONLY0-NEXT:    br label [[IF_END156]]
38299 // SIMD-ONLY0:       if.end156:
38300 // SIMD-ONLY0-NEXT:    [[TMP101:%.*]] = load i8, ptr [[CX]], align 1
38301 // SIMD-ONLY0-NEXT:    store i8 [[TMP101]], ptr [[CV]], align 1
38302 // SIMD-ONLY0-NEXT:    [[TMP102:%.*]] = load i8, ptr [[CX]], align 1
38303 // SIMD-ONLY0-NEXT:    [[CONV157:%.*]] = sext i8 [[TMP102]] to i32
38304 // SIMD-ONLY0-NEXT:    [[TMP103:%.*]] = load i8, ptr [[CE]], align 1
38305 // SIMD-ONLY0-NEXT:    [[CONV158:%.*]] = sext i8 [[TMP103]] to i32
38306 // SIMD-ONLY0-NEXT:    [[CMP159:%.*]] = icmp sgt i32 [[CONV157]], [[CONV158]]
38307 // SIMD-ONLY0-NEXT:    br i1 [[CMP159]], label [[IF_THEN161:%.*]], label [[IF_END162:%.*]]
38308 // SIMD-ONLY0:       if.then161:
38309 // SIMD-ONLY0-NEXT:    [[TMP104:%.*]] = load i8, ptr [[CE]], align 1
38310 // SIMD-ONLY0-NEXT:    store i8 [[TMP104]], ptr [[CX]], align 1
38311 // SIMD-ONLY0-NEXT:    br label [[IF_END162]]
38312 // SIMD-ONLY0:       if.end162:
38313 // SIMD-ONLY0-NEXT:    [[TMP105:%.*]] = load i8, ptr [[CX]], align 1
38314 // SIMD-ONLY0-NEXT:    store i8 [[TMP105]], ptr [[CV]], align 1
38315 // SIMD-ONLY0-NEXT:    [[TMP106:%.*]] = load i8, ptr [[CE]], align 1
38316 // SIMD-ONLY0-NEXT:    [[CONV163:%.*]] = sext i8 [[TMP106]] to i32
38317 // SIMD-ONLY0-NEXT:    [[TMP107:%.*]] = load i8, ptr [[CX]], align 1
38318 // SIMD-ONLY0-NEXT:    [[CONV164:%.*]] = sext i8 [[TMP107]] to i32
38319 // SIMD-ONLY0-NEXT:    [[CMP165:%.*]] = icmp slt i32 [[CONV163]], [[CONV164]]
38320 // SIMD-ONLY0-NEXT:    br i1 [[CMP165]], label [[IF_THEN167:%.*]], label [[IF_END168:%.*]]
38321 // SIMD-ONLY0:       if.then167:
38322 // SIMD-ONLY0-NEXT:    [[TMP108:%.*]] = load i8, ptr [[CE]], align 1
38323 // SIMD-ONLY0-NEXT:    store i8 [[TMP108]], ptr [[CX]], align 1
38324 // SIMD-ONLY0-NEXT:    br label [[IF_END168]]
38325 // SIMD-ONLY0:       if.end168:
38326 // SIMD-ONLY0-NEXT:    [[TMP109:%.*]] = load i8, ptr [[CX]], align 1
38327 // SIMD-ONLY0-NEXT:    store i8 [[TMP109]], ptr [[CV]], align 1
38328 // SIMD-ONLY0-NEXT:    [[TMP110:%.*]] = load i8, ptr [[CX]], align 1
38329 // SIMD-ONLY0-NEXT:    [[CONV169:%.*]] = sext i8 [[TMP110]] to i32
38330 // SIMD-ONLY0-NEXT:    [[TMP111:%.*]] = load i8, ptr [[CE]], align 1
38331 // SIMD-ONLY0-NEXT:    [[CONV170:%.*]] = sext i8 [[TMP111]] to i32
38332 // SIMD-ONLY0-NEXT:    [[CMP171:%.*]] = icmp slt i32 [[CONV169]], [[CONV170]]
38333 // SIMD-ONLY0-NEXT:    br i1 [[CMP171]], label [[IF_THEN173:%.*]], label [[IF_END174:%.*]]
38334 // SIMD-ONLY0:       if.then173:
38335 // SIMD-ONLY0-NEXT:    [[TMP112:%.*]] = load i8, ptr [[CE]], align 1
38336 // SIMD-ONLY0-NEXT:    store i8 [[TMP112]], ptr [[CX]], align 1
38337 // SIMD-ONLY0-NEXT:    br label [[IF_END174]]
38338 // SIMD-ONLY0:       if.end174:
38339 // SIMD-ONLY0-NEXT:    [[TMP113:%.*]] = load i8, ptr [[CX]], align 1
38340 // SIMD-ONLY0-NEXT:    store i8 [[TMP113]], ptr [[CV]], align 1
38341 // SIMD-ONLY0-NEXT:    [[TMP114:%.*]] = load i8, ptr [[CX]], align 1
38342 // SIMD-ONLY0-NEXT:    [[CONV175:%.*]] = sext i8 [[TMP114]] to i32
38343 // SIMD-ONLY0-NEXT:    [[TMP115:%.*]] = load i8, ptr [[CE]], align 1
38344 // SIMD-ONLY0-NEXT:    [[CONV176:%.*]] = sext i8 [[TMP115]] to i32
38345 // SIMD-ONLY0-NEXT:    [[CMP177:%.*]] = icmp eq i32 [[CONV175]], [[CONV176]]
38346 // SIMD-ONLY0-NEXT:    br i1 [[CMP177]], label [[IF_THEN179:%.*]], label [[IF_END180:%.*]]
38347 // SIMD-ONLY0:       if.then179:
38348 // SIMD-ONLY0-NEXT:    [[TMP116:%.*]] = load i8, ptr [[CD]], align 1
38349 // SIMD-ONLY0-NEXT:    store i8 [[TMP116]], ptr [[CX]], align 1
38350 // SIMD-ONLY0-NEXT:    br label [[IF_END180]]
38351 // SIMD-ONLY0:       if.end180:
38352 // SIMD-ONLY0-NEXT:    [[TMP117:%.*]] = load i8, ptr [[CX]], align 1
38353 // SIMD-ONLY0-NEXT:    store i8 [[TMP117]], ptr [[CV]], align 1
38354 // SIMD-ONLY0-NEXT:    [[TMP118:%.*]] = load i8, ptr [[CE]], align 1
38355 // SIMD-ONLY0-NEXT:    [[CONV181:%.*]] = sext i8 [[TMP118]] to i32
38356 // SIMD-ONLY0-NEXT:    [[TMP119:%.*]] = load i8, ptr [[CX]], align 1
38357 // SIMD-ONLY0-NEXT:    [[CONV182:%.*]] = sext i8 [[TMP119]] to i32
38358 // SIMD-ONLY0-NEXT:    [[CMP183:%.*]] = icmp eq i32 [[CONV181]], [[CONV182]]
38359 // SIMD-ONLY0-NEXT:    br i1 [[CMP183]], label [[IF_THEN185:%.*]], label [[IF_END186:%.*]]
38360 // SIMD-ONLY0:       if.then185:
38361 // SIMD-ONLY0-NEXT:    [[TMP120:%.*]] = load i8, ptr [[CD]], align 1
38362 // SIMD-ONLY0-NEXT:    store i8 [[TMP120]], ptr [[CX]], align 1
38363 // SIMD-ONLY0-NEXT:    br label [[IF_END186]]
38364 // SIMD-ONLY0:       if.end186:
38365 // SIMD-ONLY0-NEXT:    [[TMP121:%.*]] = load i8, ptr [[CX]], align 1
38366 // SIMD-ONLY0-NEXT:    store i8 [[TMP121]], ptr [[CV]], align 1
38367 // SIMD-ONLY0-NEXT:    [[TMP122:%.*]] = load i8, ptr [[CX]], align 1
38368 // SIMD-ONLY0-NEXT:    [[CONV187:%.*]] = sext i8 [[TMP122]] to i32
38369 // SIMD-ONLY0-NEXT:    [[TMP123:%.*]] = load i8, ptr [[CE]], align 1
38370 // SIMD-ONLY0-NEXT:    [[CONV188:%.*]] = sext i8 [[TMP123]] to i32
38371 // SIMD-ONLY0-NEXT:    [[CMP189:%.*]] = icmp eq i32 [[CONV187]], [[CONV188]]
38372 // SIMD-ONLY0-NEXT:    br i1 [[CMP189]], label [[IF_THEN191:%.*]], label [[IF_ELSE192:%.*]]
38373 // SIMD-ONLY0:       if.then191:
38374 // SIMD-ONLY0-NEXT:    [[TMP124:%.*]] = load i8, ptr [[CD]], align 1
38375 // SIMD-ONLY0-NEXT:    store i8 [[TMP124]], ptr [[CX]], align 1
38376 // SIMD-ONLY0-NEXT:    br label [[IF_END193:%.*]]
38377 // SIMD-ONLY0:       if.else192:
38378 // SIMD-ONLY0-NEXT:    [[TMP125:%.*]] = load i8, ptr [[CX]], align 1
38379 // SIMD-ONLY0-NEXT:    store i8 [[TMP125]], ptr [[CV]], align 1
38380 // SIMD-ONLY0-NEXT:    br label [[IF_END193]]
38381 // SIMD-ONLY0:       if.end193:
38382 // SIMD-ONLY0-NEXT:    [[TMP126:%.*]] = load i8, ptr [[CE]], align 1
38383 // SIMD-ONLY0-NEXT:    [[CONV194:%.*]] = sext i8 [[TMP126]] to i32
38384 // SIMD-ONLY0-NEXT:    [[TMP127:%.*]] = load i8, ptr [[CX]], align 1
38385 // SIMD-ONLY0-NEXT:    [[CONV195:%.*]] = sext i8 [[TMP127]] to i32
38386 // SIMD-ONLY0-NEXT:    [[CMP196:%.*]] = icmp eq i32 [[CONV194]], [[CONV195]]
38387 // SIMD-ONLY0-NEXT:    br i1 [[CMP196]], label [[IF_THEN198:%.*]], label [[IF_ELSE199:%.*]]
38388 // SIMD-ONLY0:       if.then198:
38389 // SIMD-ONLY0-NEXT:    [[TMP128:%.*]] = load i8, ptr [[CD]], align 1
38390 // SIMD-ONLY0-NEXT:    store i8 [[TMP128]], ptr [[CX]], align 1
38391 // SIMD-ONLY0-NEXT:    br label [[IF_END200:%.*]]
38392 // SIMD-ONLY0:       if.else199:
38393 // SIMD-ONLY0-NEXT:    [[TMP129:%.*]] = load i8, ptr [[CX]], align 1
38394 // SIMD-ONLY0-NEXT:    store i8 [[TMP129]], ptr [[CV]], align 1
38395 // SIMD-ONLY0-NEXT:    br label [[IF_END200]]
38396 // SIMD-ONLY0:       if.end200:
38397 // SIMD-ONLY0-NEXT:    [[TMP130:%.*]] = load i8, ptr [[CX]], align 1
38398 // SIMD-ONLY0-NEXT:    [[CONV201:%.*]] = sext i8 [[TMP130]] to i32
38399 // SIMD-ONLY0-NEXT:    [[TMP131:%.*]] = load i8, ptr [[CE]], align 1
38400 // SIMD-ONLY0-NEXT:    [[CONV202:%.*]] = sext i8 [[TMP131]] to i32
38401 // SIMD-ONLY0-NEXT:    [[CMP203:%.*]] = icmp eq i32 [[CONV201]], [[CONV202]]
38402 // SIMD-ONLY0-NEXT:    [[CONV204:%.*]] = zext i1 [[CMP203]] to i32
38403 // SIMD-ONLY0-NEXT:    [[CONV205:%.*]] = trunc i32 [[CONV204]] to i8
38404 // SIMD-ONLY0-NEXT:    store i8 [[CONV205]], ptr [[CR]], align 1
38405 // SIMD-ONLY0-NEXT:    [[TMP132:%.*]] = load i8, ptr [[CR]], align 1
38406 // SIMD-ONLY0-NEXT:    [[TOBOOL206:%.*]] = icmp ne i8 [[TMP132]], 0
38407 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL206]], label [[IF_THEN207:%.*]], label [[IF_END208:%.*]]
38408 // SIMD-ONLY0:       if.then207:
38409 // SIMD-ONLY0-NEXT:    [[TMP133:%.*]] = load i8, ptr [[CD]], align 1
38410 // SIMD-ONLY0-NEXT:    store i8 [[TMP133]], ptr [[CX]], align 1
38411 // SIMD-ONLY0-NEXT:    br label [[IF_END208]]
38412 // SIMD-ONLY0:       if.end208:
38413 // SIMD-ONLY0-NEXT:    [[TMP134:%.*]] = load i8, ptr [[CE]], align 1
38414 // SIMD-ONLY0-NEXT:    [[CONV209:%.*]] = sext i8 [[TMP134]] to i32
38415 // SIMD-ONLY0-NEXT:    [[TMP135:%.*]] = load i8, ptr [[CX]], align 1
38416 // SIMD-ONLY0-NEXT:    [[CONV210:%.*]] = sext i8 [[TMP135]] to i32
38417 // SIMD-ONLY0-NEXT:    [[CMP211:%.*]] = icmp eq i32 [[CONV209]], [[CONV210]]
38418 // SIMD-ONLY0-NEXT:    [[CONV212:%.*]] = zext i1 [[CMP211]] to i32
38419 // SIMD-ONLY0-NEXT:    [[CONV213:%.*]] = trunc i32 [[CONV212]] to i8
38420 // SIMD-ONLY0-NEXT:    store i8 [[CONV213]], ptr [[CR]], align 1
38421 // SIMD-ONLY0-NEXT:    [[TMP136:%.*]] = load i8, ptr [[CR]], align 1
38422 // SIMD-ONLY0-NEXT:    [[TOBOOL214:%.*]] = icmp ne i8 [[TMP136]], 0
38423 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL214]], label [[IF_THEN215:%.*]], label [[IF_END216:%.*]]
38424 // SIMD-ONLY0:       if.then215:
38425 // SIMD-ONLY0-NEXT:    [[TMP137:%.*]] = load i8, ptr [[CD]], align 1
38426 // SIMD-ONLY0-NEXT:    store i8 [[TMP137]], ptr [[CX]], align 1
38427 // SIMD-ONLY0-NEXT:    br label [[IF_END216]]
38428 // SIMD-ONLY0:       if.end216:
38429 // SIMD-ONLY0-NEXT:    [[TMP138:%.*]] = load i8, ptr [[CX]], align 1
38430 // SIMD-ONLY0-NEXT:    [[CONV217:%.*]] = sext i8 [[TMP138]] to i32
38431 // SIMD-ONLY0-NEXT:    [[TMP139:%.*]] = load i8, ptr [[CE]], align 1
38432 // SIMD-ONLY0-NEXT:    [[CONV218:%.*]] = sext i8 [[TMP139]] to i32
38433 // SIMD-ONLY0-NEXT:    [[CMP219:%.*]] = icmp eq i32 [[CONV217]], [[CONV218]]
38434 // SIMD-ONLY0-NEXT:    [[CONV220:%.*]] = zext i1 [[CMP219]] to i32
38435 // SIMD-ONLY0-NEXT:    [[CONV221:%.*]] = trunc i32 [[CONV220]] to i8
38436 // SIMD-ONLY0-NEXT:    store i8 [[CONV221]], ptr [[CR]], align 1
38437 // SIMD-ONLY0-NEXT:    [[TMP140:%.*]] = load i8, ptr [[CR]], align 1
38438 // SIMD-ONLY0-NEXT:    [[TOBOOL222:%.*]] = icmp ne i8 [[TMP140]], 0
38439 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL222]], label [[IF_THEN223:%.*]], label [[IF_ELSE224:%.*]]
38440 // SIMD-ONLY0:       if.then223:
38441 // SIMD-ONLY0-NEXT:    [[TMP141:%.*]] = load i8, ptr [[CD]], align 1
38442 // SIMD-ONLY0-NEXT:    store i8 [[TMP141]], ptr [[CX]], align 1
38443 // SIMD-ONLY0-NEXT:    br label [[IF_END225:%.*]]
38444 // SIMD-ONLY0:       if.else224:
38445 // SIMD-ONLY0-NEXT:    [[TMP142:%.*]] = load i8, ptr [[CX]], align 1
38446 // SIMD-ONLY0-NEXT:    store i8 [[TMP142]], ptr [[CV]], align 1
38447 // SIMD-ONLY0-NEXT:    br label [[IF_END225]]
38448 // SIMD-ONLY0:       if.end225:
38449 // SIMD-ONLY0-NEXT:    [[TMP143:%.*]] = load i8, ptr [[CE]], align 1
38450 // SIMD-ONLY0-NEXT:    [[CONV226:%.*]] = sext i8 [[TMP143]] to i32
38451 // SIMD-ONLY0-NEXT:    [[TMP144:%.*]] = load i8, ptr [[CX]], align 1
38452 // SIMD-ONLY0-NEXT:    [[CONV227:%.*]] = sext i8 [[TMP144]] to i32
38453 // SIMD-ONLY0-NEXT:    [[CMP228:%.*]] = icmp eq i32 [[CONV226]], [[CONV227]]
38454 // SIMD-ONLY0-NEXT:    [[CONV229:%.*]] = zext i1 [[CMP228]] to i32
38455 // SIMD-ONLY0-NEXT:    [[CONV230:%.*]] = trunc i32 [[CONV229]] to i8
38456 // SIMD-ONLY0-NEXT:    store i8 [[CONV230]], ptr [[CR]], align 1
38457 // SIMD-ONLY0-NEXT:    [[TMP145:%.*]] = load i8, ptr [[CR]], align 1
38458 // SIMD-ONLY0-NEXT:    [[TOBOOL231:%.*]] = icmp ne i8 [[TMP145]], 0
38459 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL231]], label [[IF_THEN232:%.*]], label [[IF_ELSE233:%.*]]
38460 // SIMD-ONLY0:       if.then232:
38461 // SIMD-ONLY0-NEXT:    [[TMP146:%.*]] = load i8, ptr [[CD]], align 1
38462 // SIMD-ONLY0-NEXT:    store i8 [[TMP146]], ptr [[CX]], align 1
38463 // SIMD-ONLY0-NEXT:    br label [[IF_END234:%.*]]
38464 // SIMD-ONLY0:       if.else233:
38465 // SIMD-ONLY0-NEXT:    [[TMP147:%.*]] = load i8, ptr [[CX]], align 1
38466 // SIMD-ONLY0-NEXT:    store i8 [[TMP147]], ptr [[CV]], align 1
38467 // SIMD-ONLY0-NEXT:    br label [[IF_END234]]
38468 // SIMD-ONLY0:       if.end234:
38469 // SIMD-ONLY0-NEXT:    [[TMP148:%.*]] = load i8, ptr [[CX]], align 1
38470 // SIMD-ONLY0-NEXT:    store i8 [[TMP148]], ptr [[CV]], align 1
38471 // SIMD-ONLY0-NEXT:    [[TMP149:%.*]] = load i8, ptr [[CE]], align 1
38472 // SIMD-ONLY0-NEXT:    [[CONV235:%.*]] = sext i8 [[TMP149]] to i32
38473 // SIMD-ONLY0-NEXT:    [[TMP150:%.*]] = load i8, ptr [[CX]], align 1
38474 // SIMD-ONLY0-NEXT:    [[CONV236:%.*]] = sext i8 [[TMP150]] to i32
38475 // SIMD-ONLY0-NEXT:    [[CMP237:%.*]] = icmp sgt i32 [[CONV235]], [[CONV236]]
38476 // SIMD-ONLY0-NEXT:    br i1 [[CMP237]], label [[IF_THEN239:%.*]], label [[IF_END240:%.*]]
38477 // SIMD-ONLY0:       if.then239:
38478 // SIMD-ONLY0-NEXT:    [[TMP151:%.*]] = load i8, ptr [[CE]], align 1
38479 // SIMD-ONLY0-NEXT:    store i8 [[TMP151]], ptr [[CX]], align 1
38480 // SIMD-ONLY0-NEXT:    br label [[IF_END240]]
38481 // SIMD-ONLY0:       if.end240:
38482 // SIMD-ONLY0-NEXT:    [[TMP152:%.*]] = load i8, ptr [[CX]], align 1
38483 // SIMD-ONLY0-NEXT:    store i8 [[TMP152]], ptr [[CV]], align 1
38484 // SIMD-ONLY0-NEXT:    [[TMP153:%.*]] = load i8, ptr [[CX]], align 1
38485 // SIMD-ONLY0-NEXT:    [[CONV241:%.*]] = sext i8 [[TMP153]] to i32
38486 // SIMD-ONLY0-NEXT:    [[TMP154:%.*]] = load i8, ptr [[CE]], align 1
38487 // SIMD-ONLY0-NEXT:    [[CONV242:%.*]] = sext i8 [[TMP154]] to i32
38488 // SIMD-ONLY0-NEXT:    [[CMP243:%.*]] = icmp sgt i32 [[CONV241]], [[CONV242]]
38489 // SIMD-ONLY0-NEXT:    br i1 [[CMP243]], label [[IF_THEN245:%.*]], label [[IF_END246:%.*]]
38490 // SIMD-ONLY0:       if.then245:
38491 // SIMD-ONLY0-NEXT:    [[TMP155:%.*]] = load i8, ptr [[CE]], align 1
38492 // SIMD-ONLY0-NEXT:    store i8 [[TMP155]], ptr [[CX]], align 1
38493 // SIMD-ONLY0-NEXT:    br label [[IF_END246]]
38494 // SIMD-ONLY0:       if.end246:
38495 // SIMD-ONLY0-NEXT:    [[TMP156:%.*]] = load i8, ptr [[CX]], align 1
38496 // SIMD-ONLY0-NEXT:    store i8 [[TMP156]], ptr [[CV]], align 1
38497 // SIMD-ONLY0-NEXT:    [[TMP157:%.*]] = load i8, ptr [[CE]], align 1
38498 // SIMD-ONLY0-NEXT:    [[CONV247:%.*]] = sext i8 [[TMP157]] to i32
38499 // SIMD-ONLY0-NEXT:    [[TMP158:%.*]] = load i8, ptr [[CX]], align 1
38500 // SIMD-ONLY0-NEXT:    [[CONV248:%.*]] = sext i8 [[TMP158]] to i32
38501 // SIMD-ONLY0-NEXT:    [[CMP249:%.*]] = icmp slt i32 [[CONV247]], [[CONV248]]
38502 // SIMD-ONLY0-NEXT:    br i1 [[CMP249]], label [[IF_THEN251:%.*]], label [[IF_END252:%.*]]
38503 // SIMD-ONLY0:       if.then251:
38504 // SIMD-ONLY0-NEXT:    [[TMP159:%.*]] = load i8, ptr [[CE]], align 1
38505 // SIMD-ONLY0-NEXT:    store i8 [[TMP159]], ptr [[CX]], align 1
38506 // SIMD-ONLY0-NEXT:    br label [[IF_END252]]
38507 // SIMD-ONLY0:       if.end252:
38508 // SIMD-ONLY0-NEXT:    [[TMP160:%.*]] = load i8, ptr [[CX]], align 1
38509 // SIMD-ONLY0-NEXT:    store i8 [[TMP160]], ptr [[CV]], align 1
38510 // SIMD-ONLY0-NEXT:    [[TMP161:%.*]] = load i8, ptr [[CX]], align 1
38511 // SIMD-ONLY0-NEXT:    [[CONV253:%.*]] = sext i8 [[TMP161]] to i32
38512 // SIMD-ONLY0-NEXT:    [[TMP162:%.*]] = load i8, ptr [[CE]], align 1
38513 // SIMD-ONLY0-NEXT:    [[CONV254:%.*]] = sext i8 [[TMP162]] to i32
38514 // SIMD-ONLY0-NEXT:    [[CMP255:%.*]] = icmp slt i32 [[CONV253]], [[CONV254]]
38515 // SIMD-ONLY0-NEXT:    br i1 [[CMP255]], label [[IF_THEN257:%.*]], label [[IF_END258:%.*]]
38516 // SIMD-ONLY0:       if.then257:
38517 // SIMD-ONLY0-NEXT:    [[TMP163:%.*]] = load i8, ptr [[CE]], align 1
38518 // SIMD-ONLY0-NEXT:    store i8 [[TMP163]], ptr [[CX]], align 1
38519 // SIMD-ONLY0-NEXT:    br label [[IF_END258]]
38520 // SIMD-ONLY0:       if.end258:
38521 // SIMD-ONLY0-NEXT:    [[TMP164:%.*]] = load i8, ptr [[CX]], align 1
38522 // SIMD-ONLY0-NEXT:    store i8 [[TMP164]], ptr [[CV]], align 1
38523 // SIMD-ONLY0-NEXT:    [[TMP165:%.*]] = load i8, ptr [[CX]], align 1
38524 // SIMD-ONLY0-NEXT:    [[CONV259:%.*]] = sext i8 [[TMP165]] to i32
38525 // SIMD-ONLY0-NEXT:    [[TMP166:%.*]] = load i8, ptr [[CE]], align 1
38526 // SIMD-ONLY0-NEXT:    [[CONV260:%.*]] = sext i8 [[TMP166]] to i32
38527 // SIMD-ONLY0-NEXT:    [[CMP261:%.*]] = icmp eq i32 [[CONV259]], [[CONV260]]
38528 // SIMD-ONLY0-NEXT:    br i1 [[CMP261]], label [[IF_THEN263:%.*]], label [[IF_END264:%.*]]
38529 // SIMD-ONLY0:       if.then263:
38530 // SIMD-ONLY0-NEXT:    [[TMP167:%.*]] = load i8, ptr [[CD]], align 1
38531 // SIMD-ONLY0-NEXT:    store i8 [[TMP167]], ptr [[CX]], align 1
38532 // SIMD-ONLY0-NEXT:    br label [[IF_END264]]
38533 // SIMD-ONLY0:       if.end264:
38534 // SIMD-ONLY0-NEXT:    [[TMP168:%.*]] = load i8, ptr [[CX]], align 1
38535 // SIMD-ONLY0-NEXT:    store i8 [[TMP168]], ptr [[CV]], align 1
38536 // SIMD-ONLY0-NEXT:    [[TMP169:%.*]] = load i8, ptr [[CE]], align 1
38537 // SIMD-ONLY0-NEXT:    [[CONV265:%.*]] = sext i8 [[TMP169]] to i32
38538 // SIMD-ONLY0-NEXT:    [[TMP170:%.*]] = load i8, ptr [[CX]], align 1
38539 // SIMD-ONLY0-NEXT:    [[CONV266:%.*]] = sext i8 [[TMP170]] to i32
38540 // SIMD-ONLY0-NEXT:    [[CMP267:%.*]] = icmp eq i32 [[CONV265]], [[CONV266]]
38541 // SIMD-ONLY0-NEXT:    br i1 [[CMP267]], label [[IF_THEN269:%.*]], label [[IF_END270:%.*]]
38542 // SIMD-ONLY0:       if.then269:
38543 // SIMD-ONLY0-NEXT:    [[TMP171:%.*]] = load i8, ptr [[CD]], align 1
38544 // SIMD-ONLY0-NEXT:    store i8 [[TMP171]], ptr [[CX]], align 1
38545 // SIMD-ONLY0-NEXT:    br label [[IF_END270]]
38546 // SIMD-ONLY0:       if.end270:
38547 // SIMD-ONLY0-NEXT:    [[TMP172:%.*]] = load i8, ptr [[CE]], align 1
38548 // SIMD-ONLY0-NEXT:    [[CONV271:%.*]] = sext i8 [[TMP172]] to i32
38549 // SIMD-ONLY0-NEXT:    [[TMP173:%.*]] = load i8, ptr [[CX]], align 1
38550 // SIMD-ONLY0-NEXT:    [[CONV272:%.*]] = sext i8 [[TMP173]] to i32
38551 // SIMD-ONLY0-NEXT:    [[CMP273:%.*]] = icmp sgt i32 [[CONV271]], [[CONV272]]
38552 // SIMD-ONLY0-NEXT:    br i1 [[CMP273]], label [[IF_THEN275:%.*]], label [[IF_END276:%.*]]
38553 // SIMD-ONLY0:       if.then275:
38554 // SIMD-ONLY0-NEXT:    [[TMP174:%.*]] = load i8, ptr [[CE]], align 1
38555 // SIMD-ONLY0-NEXT:    store i8 [[TMP174]], ptr [[CX]], align 1
38556 // SIMD-ONLY0-NEXT:    br label [[IF_END276]]
38557 // SIMD-ONLY0:       if.end276:
38558 // SIMD-ONLY0-NEXT:    [[TMP175:%.*]] = load i8, ptr [[CX]], align 1
38559 // SIMD-ONLY0-NEXT:    store i8 [[TMP175]], ptr [[CV]], align 1
38560 // SIMD-ONLY0-NEXT:    [[TMP176:%.*]] = load i8, ptr [[CX]], align 1
38561 // SIMD-ONLY0-NEXT:    [[CONV277:%.*]] = sext i8 [[TMP176]] to i32
38562 // SIMD-ONLY0-NEXT:    [[TMP177:%.*]] = load i8, ptr [[CE]], align 1
38563 // SIMD-ONLY0-NEXT:    [[CONV278:%.*]] = sext i8 [[TMP177]] to i32
38564 // SIMD-ONLY0-NEXT:    [[CMP279:%.*]] = icmp sgt i32 [[CONV277]], [[CONV278]]
38565 // SIMD-ONLY0-NEXT:    br i1 [[CMP279]], label [[IF_THEN281:%.*]], label [[IF_END282:%.*]]
38566 // SIMD-ONLY0:       if.then281:
38567 // SIMD-ONLY0-NEXT:    [[TMP178:%.*]] = load i8, ptr [[CE]], align 1
38568 // SIMD-ONLY0-NEXT:    store i8 [[TMP178]], ptr [[CX]], align 1
38569 // SIMD-ONLY0-NEXT:    br label [[IF_END282]]
38570 // SIMD-ONLY0:       if.end282:
38571 // SIMD-ONLY0-NEXT:    [[TMP179:%.*]] = load i8, ptr [[CX]], align 1
38572 // SIMD-ONLY0-NEXT:    store i8 [[TMP179]], ptr [[CV]], align 1
38573 // SIMD-ONLY0-NEXT:    [[TMP180:%.*]] = load i8, ptr [[CE]], align 1
38574 // SIMD-ONLY0-NEXT:    [[CONV283:%.*]] = sext i8 [[TMP180]] to i32
38575 // SIMD-ONLY0-NEXT:    [[TMP181:%.*]] = load i8, ptr [[CX]], align 1
38576 // SIMD-ONLY0-NEXT:    [[CONV284:%.*]] = sext i8 [[TMP181]] to i32
38577 // SIMD-ONLY0-NEXT:    [[CMP285:%.*]] = icmp slt i32 [[CONV283]], [[CONV284]]
38578 // SIMD-ONLY0-NEXT:    br i1 [[CMP285]], label [[IF_THEN287:%.*]], label [[IF_END288:%.*]]
38579 // SIMD-ONLY0:       if.then287:
38580 // SIMD-ONLY0-NEXT:    [[TMP182:%.*]] = load i8, ptr [[CE]], align 1
38581 // SIMD-ONLY0-NEXT:    store i8 [[TMP182]], ptr [[CX]], align 1
38582 // SIMD-ONLY0-NEXT:    br label [[IF_END288]]
38583 // SIMD-ONLY0:       if.end288:
38584 // SIMD-ONLY0-NEXT:    [[TMP183:%.*]] = load i8, ptr [[CX]], align 1
38585 // SIMD-ONLY0-NEXT:    store i8 [[TMP183]], ptr [[CV]], align 1
38586 // SIMD-ONLY0-NEXT:    [[TMP184:%.*]] = load i8, ptr [[CX]], align 1
38587 // SIMD-ONLY0-NEXT:    [[CONV289:%.*]] = sext i8 [[TMP184]] to i32
38588 // SIMD-ONLY0-NEXT:    [[TMP185:%.*]] = load i8, ptr [[CE]], align 1
38589 // SIMD-ONLY0-NEXT:    [[CONV290:%.*]] = sext i8 [[TMP185]] to i32
38590 // SIMD-ONLY0-NEXT:    [[CMP291:%.*]] = icmp slt i32 [[CONV289]], [[CONV290]]
38591 // SIMD-ONLY0-NEXT:    br i1 [[CMP291]], label [[IF_THEN293:%.*]], label [[IF_END294:%.*]]
38592 // SIMD-ONLY0:       if.then293:
38593 // SIMD-ONLY0-NEXT:    [[TMP186:%.*]] = load i8, ptr [[CE]], align 1
38594 // SIMD-ONLY0-NEXT:    store i8 [[TMP186]], ptr [[CX]], align 1
38595 // SIMD-ONLY0-NEXT:    br label [[IF_END294]]
38596 // SIMD-ONLY0:       if.end294:
38597 // SIMD-ONLY0-NEXT:    [[TMP187:%.*]] = load i8, ptr [[CX]], align 1
38598 // SIMD-ONLY0-NEXT:    store i8 [[TMP187]], ptr [[CV]], align 1
38599 // SIMD-ONLY0-NEXT:    [[TMP188:%.*]] = load i8, ptr [[CX]], align 1
38600 // SIMD-ONLY0-NEXT:    [[CONV295:%.*]] = sext i8 [[TMP188]] to i32
38601 // SIMD-ONLY0-NEXT:    [[TMP189:%.*]] = load i8, ptr [[CE]], align 1
38602 // SIMD-ONLY0-NEXT:    [[CONV296:%.*]] = sext i8 [[TMP189]] to i32
38603 // SIMD-ONLY0-NEXT:    [[CMP297:%.*]] = icmp eq i32 [[CONV295]], [[CONV296]]
38604 // SIMD-ONLY0-NEXT:    br i1 [[CMP297]], label [[IF_THEN299:%.*]], label [[IF_END300:%.*]]
38605 // SIMD-ONLY0:       if.then299:
38606 // SIMD-ONLY0-NEXT:    [[TMP190:%.*]] = load i8, ptr [[CD]], align 1
38607 // SIMD-ONLY0-NEXT:    store i8 [[TMP190]], ptr [[CX]], align 1
38608 // SIMD-ONLY0-NEXT:    br label [[IF_END300]]
38609 // SIMD-ONLY0:       if.end300:
38610 // SIMD-ONLY0-NEXT:    [[TMP191:%.*]] = load i8, ptr [[CX]], align 1
38611 // SIMD-ONLY0-NEXT:    store i8 [[TMP191]], ptr [[CV]], align 1
38612 // SIMD-ONLY0-NEXT:    [[TMP192:%.*]] = load i8, ptr [[CE]], align 1
38613 // SIMD-ONLY0-NEXT:    [[CONV301:%.*]] = sext i8 [[TMP192]] to i32
38614 // SIMD-ONLY0-NEXT:    [[TMP193:%.*]] = load i8, ptr [[CX]], align 1
38615 // SIMD-ONLY0-NEXT:    [[CONV302:%.*]] = sext i8 [[TMP193]] to i32
38616 // SIMD-ONLY0-NEXT:    [[CMP303:%.*]] = icmp eq i32 [[CONV301]], [[CONV302]]
38617 // SIMD-ONLY0-NEXT:    br i1 [[CMP303]], label [[IF_THEN305:%.*]], label [[IF_END306:%.*]]
38618 // SIMD-ONLY0:       if.then305:
38619 // SIMD-ONLY0-NEXT:    [[TMP194:%.*]] = load i8, ptr [[CD]], align 1
38620 // SIMD-ONLY0-NEXT:    store i8 [[TMP194]], ptr [[CX]], align 1
38621 // SIMD-ONLY0-NEXT:    br label [[IF_END306]]
38622 // SIMD-ONLY0:       if.end306:
38623 // SIMD-ONLY0-NEXT:    [[TMP195:%.*]] = load i8, ptr [[CX]], align 1
38624 // SIMD-ONLY0-NEXT:    store i8 [[TMP195]], ptr [[CV]], align 1
38625 // SIMD-ONLY0-NEXT:    [[TMP196:%.*]] = load i8, ptr [[CX]], align 1
38626 // SIMD-ONLY0-NEXT:    [[CONV307:%.*]] = sext i8 [[TMP196]] to i32
38627 // SIMD-ONLY0-NEXT:    [[TMP197:%.*]] = load i8, ptr [[CE]], align 1
38628 // SIMD-ONLY0-NEXT:    [[CONV308:%.*]] = sext i8 [[TMP197]] to i32
38629 // SIMD-ONLY0-NEXT:    [[CMP309:%.*]] = icmp eq i32 [[CONV307]], [[CONV308]]
38630 // SIMD-ONLY0-NEXT:    br i1 [[CMP309]], label [[IF_THEN311:%.*]], label [[IF_ELSE312:%.*]]
38631 // SIMD-ONLY0:       if.then311:
38632 // SIMD-ONLY0-NEXT:    [[TMP198:%.*]] = load i8, ptr [[CD]], align 1
38633 // SIMD-ONLY0-NEXT:    store i8 [[TMP198]], ptr [[CX]], align 1
38634 // SIMD-ONLY0-NEXT:    br label [[IF_END313:%.*]]
38635 // SIMD-ONLY0:       if.else312:
38636 // SIMD-ONLY0-NEXT:    [[TMP199:%.*]] = load i8, ptr [[CX]], align 1
38637 // SIMD-ONLY0-NEXT:    store i8 [[TMP199]], ptr [[CV]], align 1
38638 // SIMD-ONLY0-NEXT:    br label [[IF_END313]]
38639 // SIMD-ONLY0:       if.end313:
38640 // SIMD-ONLY0-NEXT:    [[TMP200:%.*]] = load i8, ptr [[CE]], align 1
38641 // SIMD-ONLY0-NEXT:    [[CONV314:%.*]] = sext i8 [[TMP200]] to i32
38642 // SIMD-ONLY0-NEXT:    [[TMP201:%.*]] = load i8, ptr [[CX]], align 1
38643 // SIMD-ONLY0-NEXT:    [[CONV315:%.*]] = sext i8 [[TMP201]] to i32
38644 // SIMD-ONLY0-NEXT:    [[CMP316:%.*]] = icmp eq i32 [[CONV314]], [[CONV315]]
38645 // SIMD-ONLY0-NEXT:    br i1 [[CMP316]], label [[IF_THEN318:%.*]], label [[IF_ELSE319:%.*]]
38646 // SIMD-ONLY0:       if.then318:
38647 // SIMD-ONLY0-NEXT:    [[TMP202:%.*]] = load i8, ptr [[CD]], align 1
38648 // SIMD-ONLY0-NEXT:    store i8 [[TMP202]], ptr [[CX]], align 1
38649 // SIMD-ONLY0-NEXT:    br label [[IF_END320:%.*]]
38650 // SIMD-ONLY0:       if.else319:
38651 // SIMD-ONLY0-NEXT:    [[TMP203:%.*]] = load i8, ptr [[CX]], align 1
38652 // SIMD-ONLY0-NEXT:    store i8 [[TMP203]], ptr [[CV]], align 1
38653 // SIMD-ONLY0-NEXT:    br label [[IF_END320]]
38654 // SIMD-ONLY0:       if.end320:
38655 // SIMD-ONLY0-NEXT:    [[TMP204:%.*]] = load i8, ptr [[CX]], align 1
38656 // SIMD-ONLY0-NEXT:    [[CONV321:%.*]] = sext i8 [[TMP204]] to i32
38657 // SIMD-ONLY0-NEXT:    [[TMP205:%.*]] = load i8, ptr [[CE]], align 1
38658 // SIMD-ONLY0-NEXT:    [[CONV322:%.*]] = sext i8 [[TMP205]] to i32
38659 // SIMD-ONLY0-NEXT:    [[CMP323:%.*]] = icmp eq i32 [[CONV321]], [[CONV322]]
38660 // SIMD-ONLY0-NEXT:    [[CONV324:%.*]] = zext i1 [[CMP323]] to i32
38661 // SIMD-ONLY0-NEXT:    [[CONV325:%.*]] = trunc i32 [[CONV324]] to i8
38662 // SIMD-ONLY0-NEXT:    store i8 [[CONV325]], ptr [[CR]], align 1
38663 // SIMD-ONLY0-NEXT:    [[TMP206:%.*]] = load i8, ptr [[CR]], align 1
38664 // SIMD-ONLY0-NEXT:    [[TOBOOL326:%.*]] = icmp ne i8 [[TMP206]], 0
38665 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL326]], label [[IF_THEN327:%.*]], label [[IF_END328:%.*]]
38666 // SIMD-ONLY0:       if.then327:
38667 // SIMD-ONLY0-NEXT:    [[TMP207:%.*]] = load i8, ptr [[CD]], align 1
38668 // SIMD-ONLY0-NEXT:    store i8 [[TMP207]], ptr [[CX]], align 1
38669 // SIMD-ONLY0-NEXT:    br label [[IF_END328]]
38670 // SIMD-ONLY0:       if.end328:
38671 // SIMD-ONLY0-NEXT:    [[TMP208:%.*]] = load i8, ptr [[CE]], align 1
38672 // SIMD-ONLY0-NEXT:    [[CONV329:%.*]] = sext i8 [[TMP208]] to i32
38673 // SIMD-ONLY0-NEXT:    [[TMP209:%.*]] = load i8, ptr [[CX]], align 1
38674 // SIMD-ONLY0-NEXT:    [[CONV330:%.*]] = sext i8 [[TMP209]] to i32
38675 // SIMD-ONLY0-NEXT:    [[CMP331:%.*]] = icmp eq i32 [[CONV329]], [[CONV330]]
38676 // SIMD-ONLY0-NEXT:    [[CONV332:%.*]] = zext i1 [[CMP331]] to i32
38677 // SIMD-ONLY0-NEXT:    [[CONV333:%.*]] = trunc i32 [[CONV332]] to i8
38678 // SIMD-ONLY0-NEXT:    store i8 [[CONV333]], ptr [[CR]], align 1
38679 // SIMD-ONLY0-NEXT:    [[TMP210:%.*]] = load i8, ptr [[CR]], align 1
38680 // SIMD-ONLY0-NEXT:    [[TOBOOL334:%.*]] = icmp ne i8 [[TMP210]], 0
38681 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL334]], label [[IF_THEN335:%.*]], label [[IF_END336:%.*]]
38682 // SIMD-ONLY0:       if.then335:
38683 // SIMD-ONLY0-NEXT:    [[TMP211:%.*]] = load i8, ptr [[CD]], align 1
38684 // SIMD-ONLY0-NEXT:    store i8 [[TMP211]], ptr [[CX]], align 1
38685 // SIMD-ONLY0-NEXT:    br label [[IF_END336]]
38686 // SIMD-ONLY0:       if.end336:
38687 // SIMD-ONLY0-NEXT:    [[TMP212:%.*]] = load i8, ptr [[CX]], align 1
38688 // SIMD-ONLY0-NEXT:    [[CONV337:%.*]] = sext i8 [[TMP212]] to i32
38689 // SIMD-ONLY0-NEXT:    [[TMP213:%.*]] = load i8, ptr [[CE]], align 1
38690 // SIMD-ONLY0-NEXT:    [[CONV338:%.*]] = sext i8 [[TMP213]] to i32
38691 // SIMD-ONLY0-NEXT:    [[CMP339:%.*]] = icmp eq i32 [[CONV337]], [[CONV338]]
38692 // SIMD-ONLY0-NEXT:    [[CONV340:%.*]] = zext i1 [[CMP339]] to i32
38693 // SIMD-ONLY0-NEXT:    [[CONV341:%.*]] = trunc i32 [[CONV340]] to i8
38694 // SIMD-ONLY0-NEXT:    store i8 [[CONV341]], ptr [[CR]], align 1
38695 // SIMD-ONLY0-NEXT:    [[TMP214:%.*]] = load i8, ptr [[CR]], align 1
38696 // SIMD-ONLY0-NEXT:    [[TOBOOL342:%.*]] = icmp ne i8 [[TMP214]], 0
38697 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL342]], label [[IF_THEN343:%.*]], label [[IF_ELSE344:%.*]]
38698 // SIMD-ONLY0:       if.then343:
38699 // SIMD-ONLY0-NEXT:    [[TMP215:%.*]] = load i8, ptr [[CD]], align 1
38700 // SIMD-ONLY0-NEXT:    store i8 [[TMP215]], ptr [[CX]], align 1
38701 // SIMD-ONLY0-NEXT:    br label [[IF_END345:%.*]]
38702 // SIMD-ONLY0:       if.else344:
38703 // SIMD-ONLY0-NEXT:    [[TMP216:%.*]] = load i8, ptr [[CX]], align 1
38704 // SIMD-ONLY0-NEXT:    store i8 [[TMP216]], ptr [[CV]], align 1
38705 // SIMD-ONLY0-NEXT:    br label [[IF_END345]]
38706 // SIMD-ONLY0:       if.end345:
38707 // SIMD-ONLY0-NEXT:    [[TMP217:%.*]] = load i8, ptr [[CE]], align 1
38708 // SIMD-ONLY0-NEXT:    [[CONV346:%.*]] = sext i8 [[TMP217]] to i32
38709 // SIMD-ONLY0-NEXT:    [[TMP218:%.*]] = load i8, ptr [[CX]], align 1
38710 // SIMD-ONLY0-NEXT:    [[CONV347:%.*]] = sext i8 [[TMP218]] to i32
38711 // SIMD-ONLY0-NEXT:    [[CMP348:%.*]] = icmp eq i32 [[CONV346]], [[CONV347]]
38712 // SIMD-ONLY0-NEXT:    [[CONV349:%.*]] = zext i1 [[CMP348]] to i32
38713 // SIMD-ONLY0-NEXT:    [[CONV350:%.*]] = trunc i32 [[CONV349]] to i8
38714 // SIMD-ONLY0-NEXT:    store i8 [[CONV350]], ptr [[CR]], align 1
38715 // SIMD-ONLY0-NEXT:    [[TMP219:%.*]] = load i8, ptr [[CR]], align 1
38716 // SIMD-ONLY0-NEXT:    [[TOBOOL351:%.*]] = icmp ne i8 [[TMP219]], 0
38717 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL351]], label [[IF_THEN352:%.*]], label [[IF_ELSE353:%.*]]
38718 // SIMD-ONLY0:       if.then352:
38719 // SIMD-ONLY0-NEXT:    [[TMP220:%.*]] = load i8, ptr [[CD]], align 1
38720 // SIMD-ONLY0-NEXT:    store i8 [[TMP220]], ptr [[CX]], align 1
38721 // SIMD-ONLY0-NEXT:    br label [[IF_END354:%.*]]
38722 // SIMD-ONLY0:       if.else353:
38723 // SIMD-ONLY0-NEXT:    [[TMP221:%.*]] = load i8, ptr [[CX]], align 1
38724 // SIMD-ONLY0-NEXT:    store i8 [[TMP221]], ptr [[CV]], align 1
38725 // SIMD-ONLY0-NEXT:    br label [[IF_END354]]
38726 // SIMD-ONLY0:       if.end354:
38727 // SIMD-ONLY0-NEXT:    [[TMP222:%.*]] = load i8, ptr [[CX]], align 1
38728 // SIMD-ONLY0-NEXT:    store i8 [[TMP222]], ptr [[CV]], align 1
38729 // SIMD-ONLY0-NEXT:    [[TMP223:%.*]] = load i8, ptr [[CE]], align 1
38730 // SIMD-ONLY0-NEXT:    [[CONV355:%.*]] = sext i8 [[TMP223]] to i32
38731 // SIMD-ONLY0-NEXT:    [[TMP224:%.*]] = load i8, ptr [[CX]], align 1
38732 // SIMD-ONLY0-NEXT:    [[CONV356:%.*]] = sext i8 [[TMP224]] to i32
38733 // SIMD-ONLY0-NEXT:    [[CMP357:%.*]] = icmp sgt i32 [[CONV355]], [[CONV356]]
38734 // SIMD-ONLY0-NEXT:    br i1 [[CMP357]], label [[IF_THEN359:%.*]], label [[IF_END360:%.*]]
38735 // SIMD-ONLY0:       if.then359:
38736 // SIMD-ONLY0-NEXT:    [[TMP225:%.*]] = load i8, ptr [[CE]], align 1
38737 // SIMD-ONLY0-NEXT:    store i8 [[TMP225]], ptr [[CX]], align 1
38738 // SIMD-ONLY0-NEXT:    br label [[IF_END360]]
38739 // SIMD-ONLY0:       if.end360:
38740 // SIMD-ONLY0-NEXT:    [[TMP226:%.*]] = load i8, ptr [[CX]], align 1
38741 // SIMD-ONLY0-NEXT:    store i8 [[TMP226]], ptr [[CV]], align 1
38742 // SIMD-ONLY0-NEXT:    [[TMP227:%.*]] = load i8, ptr [[CX]], align 1
38743 // SIMD-ONLY0-NEXT:    [[CONV361:%.*]] = sext i8 [[TMP227]] to i32
38744 // SIMD-ONLY0-NEXT:    [[TMP228:%.*]] = load i8, ptr [[CE]], align 1
38745 // SIMD-ONLY0-NEXT:    [[CONV362:%.*]] = sext i8 [[TMP228]] to i32
38746 // SIMD-ONLY0-NEXT:    [[CMP363:%.*]] = icmp sgt i32 [[CONV361]], [[CONV362]]
38747 // SIMD-ONLY0-NEXT:    br i1 [[CMP363]], label [[IF_THEN365:%.*]], label [[IF_END366:%.*]]
38748 // SIMD-ONLY0:       if.then365:
38749 // SIMD-ONLY0-NEXT:    [[TMP229:%.*]] = load i8, ptr [[CE]], align 1
38750 // SIMD-ONLY0-NEXT:    store i8 [[TMP229]], ptr [[CX]], align 1
38751 // SIMD-ONLY0-NEXT:    br label [[IF_END366]]
38752 // SIMD-ONLY0:       if.end366:
38753 // SIMD-ONLY0-NEXT:    [[TMP230:%.*]] = load i8, ptr [[CX]], align 1
38754 // SIMD-ONLY0-NEXT:    store i8 [[TMP230]], ptr [[CV]], align 1
38755 // SIMD-ONLY0-NEXT:    [[TMP231:%.*]] = load i8, ptr [[CE]], align 1
38756 // SIMD-ONLY0-NEXT:    [[CONV367:%.*]] = sext i8 [[TMP231]] to i32
38757 // SIMD-ONLY0-NEXT:    [[TMP232:%.*]] = load i8, ptr [[CX]], align 1
38758 // SIMD-ONLY0-NEXT:    [[CONV368:%.*]] = sext i8 [[TMP232]] to i32
38759 // SIMD-ONLY0-NEXT:    [[CMP369:%.*]] = icmp slt i32 [[CONV367]], [[CONV368]]
38760 // SIMD-ONLY0-NEXT:    br i1 [[CMP369]], label [[IF_THEN371:%.*]], label [[IF_END372:%.*]]
38761 // SIMD-ONLY0:       if.then371:
38762 // SIMD-ONLY0-NEXT:    [[TMP233:%.*]] = load i8, ptr [[CE]], align 1
38763 // SIMD-ONLY0-NEXT:    store i8 [[TMP233]], ptr [[CX]], align 1
38764 // SIMD-ONLY0-NEXT:    br label [[IF_END372]]
38765 // SIMD-ONLY0:       if.end372:
38766 // SIMD-ONLY0-NEXT:    [[TMP234:%.*]] = load i8, ptr [[CX]], align 1
38767 // SIMD-ONLY0-NEXT:    store i8 [[TMP234]], ptr [[CV]], align 1
38768 // SIMD-ONLY0-NEXT:    [[TMP235:%.*]] = load i8, ptr [[CX]], align 1
38769 // SIMD-ONLY0-NEXT:    [[CONV373:%.*]] = sext i8 [[TMP235]] to i32
38770 // SIMD-ONLY0-NEXT:    [[TMP236:%.*]] = load i8, ptr [[CE]], align 1
38771 // SIMD-ONLY0-NEXT:    [[CONV374:%.*]] = sext i8 [[TMP236]] to i32
38772 // SIMD-ONLY0-NEXT:    [[CMP375:%.*]] = icmp slt i32 [[CONV373]], [[CONV374]]
38773 // SIMD-ONLY0-NEXT:    br i1 [[CMP375]], label [[IF_THEN377:%.*]], label [[IF_END378:%.*]]
38774 // SIMD-ONLY0:       if.then377:
38775 // SIMD-ONLY0-NEXT:    [[TMP237:%.*]] = load i8, ptr [[CE]], align 1
38776 // SIMD-ONLY0-NEXT:    store i8 [[TMP237]], ptr [[CX]], align 1
38777 // SIMD-ONLY0-NEXT:    br label [[IF_END378]]
38778 // SIMD-ONLY0:       if.end378:
38779 // SIMD-ONLY0-NEXT:    [[TMP238:%.*]] = load i8, ptr [[CX]], align 1
38780 // SIMD-ONLY0-NEXT:    store i8 [[TMP238]], ptr [[CV]], align 1
38781 // SIMD-ONLY0-NEXT:    [[TMP239:%.*]] = load i8, ptr [[CX]], align 1
38782 // SIMD-ONLY0-NEXT:    [[CONV379:%.*]] = sext i8 [[TMP239]] to i32
38783 // SIMD-ONLY0-NEXT:    [[TMP240:%.*]] = load i8, ptr [[CE]], align 1
38784 // SIMD-ONLY0-NEXT:    [[CONV380:%.*]] = sext i8 [[TMP240]] to i32
38785 // SIMD-ONLY0-NEXT:    [[CMP381:%.*]] = icmp eq i32 [[CONV379]], [[CONV380]]
38786 // SIMD-ONLY0-NEXT:    br i1 [[CMP381]], label [[IF_THEN383:%.*]], label [[IF_END384:%.*]]
38787 // SIMD-ONLY0:       if.then383:
38788 // SIMD-ONLY0-NEXT:    [[TMP241:%.*]] = load i8, ptr [[CD]], align 1
38789 // SIMD-ONLY0-NEXT:    store i8 [[TMP241]], ptr [[CX]], align 1
38790 // SIMD-ONLY0-NEXT:    br label [[IF_END384]]
38791 // SIMD-ONLY0:       if.end384:
38792 // SIMD-ONLY0-NEXT:    [[TMP242:%.*]] = load i8, ptr [[CX]], align 1
38793 // SIMD-ONLY0-NEXT:    store i8 [[TMP242]], ptr [[CV]], align 1
38794 // SIMD-ONLY0-NEXT:    [[TMP243:%.*]] = load i8, ptr [[CE]], align 1
38795 // SIMD-ONLY0-NEXT:    [[CONV385:%.*]] = sext i8 [[TMP243]] to i32
38796 // SIMD-ONLY0-NEXT:    [[TMP244:%.*]] = load i8, ptr [[CX]], align 1
38797 // SIMD-ONLY0-NEXT:    [[CONV386:%.*]] = sext i8 [[TMP244]] to i32
38798 // SIMD-ONLY0-NEXT:    [[CMP387:%.*]] = icmp eq i32 [[CONV385]], [[CONV386]]
38799 // SIMD-ONLY0-NEXT:    br i1 [[CMP387]], label [[IF_THEN389:%.*]], label [[IF_END390:%.*]]
38800 // SIMD-ONLY0:       if.then389:
38801 // SIMD-ONLY0-NEXT:    [[TMP245:%.*]] = load i8, ptr [[CD]], align 1
38802 // SIMD-ONLY0-NEXT:    store i8 [[TMP245]], ptr [[CX]], align 1
38803 // SIMD-ONLY0-NEXT:    br label [[IF_END390]]
38804 // SIMD-ONLY0:       if.end390:
38805 // SIMD-ONLY0-NEXT:    [[TMP246:%.*]] = load i8, ptr [[CE]], align 1
38806 // SIMD-ONLY0-NEXT:    [[CONV391:%.*]] = sext i8 [[TMP246]] to i32
38807 // SIMD-ONLY0-NEXT:    [[TMP247:%.*]] = load i8, ptr [[CX]], align 1
38808 // SIMD-ONLY0-NEXT:    [[CONV392:%.*]] = sext i8 [[TMP247]] to i32
38809 // SIMD-ONLY0-NEXT:    [[CMP393:%.*]] = icmp sgt i32 [[CONV391]], [[CONV392]]
38810 // SIMD-ONLY0-NEXT:    br i1 [[CMP393]], label [[IF_THEN395:%.*]], label [[IF_END396:%.*]]
38811 // SIMD-ONLY0:       if.then395:
38812 // SIMD-ONLY0-NEXT:    [[TMP248:%.*]] = load i8, ptr [[CE]], align 1
38813 // SIMD-ONLY0-NEXT:    store i8 [[TMP248]], ptr [[CX]], align 1
38814 // SIMD-ONLY0-NEXT:    br label [[IF_END396]]
38815 // SIMD-ONLY0:       if.end396:
38816 // SIMD-ONLY0-NEXT:    [[TMP249:%.*]] = load i8, ptr [[CX]], align 1
38817 // SIMD-ONLY0-NEXT:    store i8 [[TMP249]], ptr [[CV]], align 1
38818 // SIMD-ONLY0-NEXT:    [[TMP250:%.*]] = load i8, ptr [[CX]], align 1
38819 // SIMD-ONLY0-NEXT:    [[CONV397:%.*]] = sext i8 [[TMP250]] to i32
38820 // SIMD-ONLY0-NEXT:    [[TMP251:%.*]] = load i8, ptr [[CE]], align 1
38821 // SIMD-ONLY0-NEXT:    [[CONV398:%.*]] = sext i8 [[TMP251]] to i32
38822 // SIMD-ONLY0-NEXT:    [[CMP399:%.*]] = icmp sgt i32 [[CONV397]], [[CONV398]]
38823 // SIMD-ONLY0-NEXT:    br i1 [[CMP399]], label [[IF_THEN401:%.*]], label [[IF_END402:%.*]]
38824 // SIMD-ONLY0:       if.then401:
38825 // SIMD-ONLY0-NEXT:    [[TMP252:%.*]] = load i8, ptr [[CE]], align 1
38826 // SIMD-ONLY0-NEXT:    store i8 [[TMP252]], ptr [[CX]], align 1
38827 // SIMD-ONLY0-NEXT:    br label [[IF_END402]]
38828 // SIMD-ONLY0:       if.end402:
38829 // SIMD-ONLY0-NEXT:    [[TMP253:%.*]] = load i8, ptr [[CX]], align 1
38830 // SIMD-ONLY0-NEXT:    store i8 [[TMP253]], ptr [[CV]], align 1
38831 // SIMD-ONLY0-NEXT:    [[TMP254:%.*]] = load i8, ptr [[CE]], align 1
38832 // SIMD-ONLY0-NEXT:    [[CONV403:%.*]] = sext i8 [[TMP254]] to i32
38833 // SIMD-ONLY0-NEXT:    [[TMP255:%.*]] = load i8, ptr [[CX]], align 1
38834 // SIMD-ONLY0-NEXT:    [[CONV404:%.*]] = sext i8 [[TMP255]] to i32
38835 // SIMD-ONLY0-NEXT:    [[CMP405:%.*]] = icmp slt i32 [[CONV403]], [[CONV404]]
38836 // SIMD-ONLY0-NEXT:    br i1 [[CMP405]], label [[IF_THEN407:%.*]], label [[IF_END408:%.*]]
38837 // SIMD-ONLY0:       if.then407:
38838 // SIMD-ONLY0-NEXT:    [[TMP256:%.*]] = load i8, ptr [[CE]], align 1
38839 // SIMD-ONLY0-NEXT:    store i8 [[TMP256]], ptr [[CX]], align 1
38840 // SIMD-ONLY0-NEXT:    br label [[IF_END408]]
38841 // SIMD-ONLY0:       if.end408:
38842 // SIMD-ONLY0-NEXT:    [[TMP257:%.*]] = load i8, ptr [[CX]], align 1
38843 // SIMD-ONLY0-NEXT:    store i8 [[TMP257]], ptr [[CV]], align 1
38844 // SIMD-ONLY0-NEXT:    [[TMP258:%.*]] = load i8, ptr [[CX]], align 1
38845 // SIMD-ONLY0-NEXT:    [[CONV409:%.*]] = sext i8 [[TMP258]] to i32
38846 // SIMD-ONLY0-NEXT:    [[TMP259:%.*]] = load i8, ptr [[CE]], align 1
38847 // SIMD-ONLY0-NEXT:    [[CONV410:%.*]] = sext i8 [[TMP259]] to i32
38848 // SIMD-ONLY0-NEXT:    [[CMP411:%.*]] = icmp slt i32 [[CONV409]], [[CONV410]]
38849 // SIMD-ONLY0-NEXT:    br i1 [[CMP411]], label [[IF_THEN413:%.*]], label [[IF_END414:%.*]]
38850 // SIMD-ONLY0:       if.then413:
38851 // SIMD-ONLY0-NEXT:    [[TMP260:%.*]] = load i8, ptr [[CE]], align 1
38852 // SIMD-ONLY0-NEXT:    store i8 [[TMP260]], ptr [[CX]], align 1
38853 // SIMD-ONLY0-NEXT:    br label [[IF_END414]]
38854 // SIMD-ONLY0:       if.end414:
38855 // SIMD-ONLY0-NEXT:    [[TMP261:%.*]] = load i8, ptr [[CX]], align 1
38856 // SIMD-ONLY0-NEXT:    store i8 [[TMP261]], ptr [[CV]], align 1
38857 // SIMD-ONLY0-NEXT:    [[TMP262:%.*]] = load i8, ptr [[CX]], align 1
38858 // SIMD-ONLY0-NEXT:    [[CONV415:%.*]] = sext i8 [[TMP262]] to i32
38859 // SIMD-ONLY0-NEXT:    [[TMP263:%.*]] = load i8, ptr [[CE]], align 1
38860 // SIMD-ONLY0-NEXT:    [[CONV416:%.*]] = sext i8 [[TMP263]] to i32
38861 // SIMD-ONLY0-NEXT:    [[CMP417:%.*]] = icmp eq i32 [[CONV415]], [[CONV416]]
38862 // SIMD-ONLY0-NEXT:    br i1 [[CMP417]], label [[IF_THEN419:%.*]], label [[IF_END420:%.*]]
38863 // SIMD-ONLY0:       if.then419:
38864 // SIMD-ONLY0-NEXT:    [[TMP264:%.*]] = load i8, ptr [[CD]], align 1
38865 // SIMD-ONLY0-NEXT:    store i8 [[TMP264]], ptr [[CX]], align 1
38866 // SIMD-ONLY0-NEXT:    br label [[IF_END420]]
38867 // SIMD-ONLY0:       if.end420:
38868 // SIMD-ONLY0-NEXT:    [[TMP265:%.*]] = load i8, ptr [[CX]], align 1
38869 // SIMD-ONLY0-NEXT:    store i8 [[TMP265]], ptr [[CV]], align 1
38870 // SIMD-ONLY0-NEXT:    [[TMP266:%.*]] = load i8, ptr [[CE]], align 1
38871 // SIMD-ONLY0-NEXT:    [[CONV421:%.*]] = sext i8 [[TMP266]] to i32
38872 // SIMD-ONLY0-NEXT:    [[TMP267:%.*]] = load i8, ptr [[CX]], align 1
38873 // SIMD-ONLY0-NEXT:    [[CONV422:%.*]] = sext i8 [[TMP267]] to i32
38874 // SIMD-ONLY0-NEXT:    [[CMP423:%.*]] = icmp eq i32 [[CONV421]], [[CONV422]]
38875 // SIMD-ONLY0-NEXT:    br i1 [[CMP423]], label [[IF_THEN425:%.*]], label [[IF_END426:%.*]]
38876 // SIMD-ONLY0:       if.then425:
38877 // SIMD-ONLY0-NEXT:    [[TMP268:%.*]] = load i8, ptr [[CD]], align 1
38878 // SIMD-ONLY0-NEXT:    store i8 [[TMP268]], ptr [[CX]], align 1
38879 // SIMD-ONLY0-NEXT:    br label [[IF_END426]]
38880 // SIMD-ONLY0:       if.end426:
38881 // SIMD-ONLY0-NEXT:    [[TMP269:%.*]] = load i8, ptr [[CX]], align 1
38882 // SIMD-ONLY0-NEXT:    store i8 [[TMP269]], ptr [[CV]], align 1
38883 // SIMD-ONLY0-NEXT:    [[TMP270:%.*]] = load i8, ptr [[CX]], align 1
38884 // SIMD-ONLY0-NEXT:    [[CONV427:%.*]] = sext i8 [[TMP270]] to i32
38885 // SIMD-ONLY0-NEXT:    [[TMP271:%.*]] = load i8, ptr [[CE]], align 1
38886 // SIMD-ONLY0-NEXT:    [[CONV428:%.*]] = sext i8 [[TMP271]] to i32
38887 // SIMD-ONLY0-NEXT:    [[CMP429:%.*]] = icmp eq i32 [[CONV427]], [[CONV428]]
38888 // SIMD-ONLY0-NEXT:    br i1 [[CMP429]], label [[IF_THEN431:%.*]], label [[IF_ELSE432:%.*]]
38889 // SIMD-ONLY0:       if.then431:
38890 // SIMD-ONLY0-NEXT:    [[TMP272:%.*]] = load i8, ptr [[CD]], align 1
38891 // SIMD-ONLY0-NEXT:    store i8 [[TMP272]], ptr [[CX]], align 1
38892 // SIMD-ONLY0-NEXT:    br label [[IF_END433:%.*]]
38893 // SIMD-ONLY0:       if.else432:
38894 // SIMD-ONLY0-NEXT:    [[TMP273:%.*]] = load i8, ptr [[CX]], align 1
38895 // SIMD-ONLY0-NEXT:    store i8 [[TMP273]], ptr [[CV]], align 1
38896 // SIMD-ONLY0-NEXT:    br label [[IF_END433]]
38897 // SIMD-ONLY0:       if.end433:
38898 // SIMD-ONLY0-NEXT:    [[TMP274:%.*]] = load i8, ptr [[CE]], align 1
38899 // SIMD-ONLY0-NEXT:    [[CONV434:%.*]] = sext i8 [[TMP274]] to i32
38900 // SIMD-ONLY0-NEXT:    [[TMP275:%.*]] = load i8, ptr [[CX]], align 1
38901 // SIMD-ONLY0-NEXT:    [[CONV435:%.*]] = sext i8 [[TMP275]] to i32
38902 // SIMD-ONLY0-NEXT:    [[CMP436:%.*]] = icmp eq i32 [[CONV434]], [[CONV435]]
38903 // SIMD-ONLY0-NEXT:    br i1 [[CMP436]], label [[IF_THEN438:%.*]], label [[IF_ELSE439:%.*]]
38904 // SIMD-ONLY0:       if.then438:
38905 // SIMD-ONLY0-NEXT:    [[TMP276:%.*]] = load i8, ptr [[CD]], align 1
38906 // SIMD-ONLY0-NEXT:    store i8 [[TMP276]], ptr [[CX]], align 1
38907 // SIMD-ONLY0-NEXT:    br label [[IF_END440:%.*]]
38908 // SIMD-ONLY0:       if.else439:
38909 // SIMD-ONLY0-NEXT:    [[TMP277:%.*]] = load i8, ptr [[CX]], align 1
38910 // SIMD-ONLY0-NEXT:    store i8 [[TMP277]], ptr [[CV]], align 1
38911 // SIMD-ONLY0-NEXT:    br label [[IF_END440]]
38912 // SIMD-ONLY0:       if.end440:
38913 // SIMD-ONLY0-NEXT:    [[TMP278:%.*]] = load i8, ptr [[CX]], align 1
38914 // SIMD-ONLY0-NEXT:    [[CONV441:%.*]] = sext i8 [[TMP278]] to i32
38915 // SIMD-ONLY0-NEXT:    [[TMP279:%.*]] = load i8, ptr [[CE]], align 1
38916 // SIMD-ONLY0-NEXT:    [[CONV442:%.*]] = sext i8 [[TMP279]] to i32
38917 // SIMD-ONLY0-NEXT:    [[CMP443:%.*]] = icmp eq i32 [[CONV441]], [[CONV442]]
38918 // SIMD-ONLY0-NEXT:    [[CONV444:%.*]] = zext i1 [[CMP443]] to i32
38919 // SIMD-ONLY0-NEXT:    [[CONV445:%.*]] = trunc i32 [[CONV444]] to i8
38920 // SIMD-ONLY0-NEXT:    store i8 [[CONV445]], ptr [[CR]], align 1
38921 // SIMD-ONLY0-NEXT:    [[TMP280:%.*]] = load i8, ptr [[CR]], align 1
38922 // SIMD-ONLY0-NEXT:    [[TOBOOL446:%.*]] = icmp ne i8 [[TMP280]], 0
38923 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL446]], label [[IF_THEN447:%.*]], label [[IF_END448:%.*]]
38924 // SIMD-ONLY0:       if.then447:
38925 // SIMD-ONLY0-NEXT:    [[TMP281:%.*]] = load i8, ptr [[CD]], align 1
38926 // SIMD-ONLY0-NEXT:    store i8 [[TMP281]], ptr [[CX]], align 1
38927 // SIMD-ONLY0-NEXT:    br label [[IF_END448]]
38928 // SIMD-ONLY0:       if.end448:
38929 // SIMD-ONLY0-NEXT:    [[TMP282:%.*]] = load i8, ptr [[CE]], align 1
38930 // SIMD-ONLY0-NEXT:    [[CONV449:%.*]] = sext i8 [[TMP282]] to i32
38931 // SIMD-ONLY0-NEXT:    [[TMP283:%.*]] = load i8, ptr [[CX]], align 1
38932 // SIMD-ONLY0-NEXT:    [[CONV450:%.*]] = sext i8 [[TMP283]] to i32
38933 // SIMD-ONLY0-NEXT:    [[CMP451:%.*]] = icmp eq i32 [[CONV449]], [[CONV450]]
38934 // SIMD-ONLY0-NEXT:    [[CONV452:%.*]] = zext i1 [[CMP451]] to i32
38935 // SIMD-ONLY0-NEXT:    [[CONV453:%.*]] = trunc i32 [[CONV452]] to i8
38936 // SIMD-ONLY0-NEXT:    store i8 [[CONV453]], ptr [[CR]], align 1
38937 // SIMD-ONLY0-NEXT:    [[TMP284:%.*]] = load i8, ptr [[CR]], align 1
38938 // SIMD-ONLY0-NEXT:    [[TOBOOL454:%.*]] = icmp ne i8 [[TMP284]], 0
38939 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL454]], label [[IF_THEN455:%.*]], label [[IF_END456:%.*]]
38940 // SIMD-ONLY0:       if.then455:
38941 // SIMD-ONLY0-NEXT:    [[TMP285:%.*]] = load i8, ptr [[CD]], align 1
38942 // SIMD-ONLY0-NEXT:    store i8 [[TMP285]], ptr [[CX]], align 1
38943 // SIMD-ONLY0-NEXT:    br label [[IF_END456]]
38944 // SIMD-ONLY0:       if.end456:
38945 // SIMD-ONLY0-NEXT:    [[TMP286:%.*]] = load i8, ptr [[CX]], align 1
38946 // SIMD-ONLY0-NEXT:    [[CONV457:%.*]] = sext i8 [[TMP286]] to i32
38947 // SIMD-ONLY0-NEXT:    [[TMP287:%.*]] = load i8, ptr [[CE]], align 1
38948 // SIMD-ONLY0-NEXT:    [[CONV458:%.*]] = sext i8 [[TMP287]] to i32
38949 // SIMD-ONLY0-NEXT:    [[CMP459:%.*]] = icmp eq i32 [[CONV457]], [[CONV458]]
38950 // SIMD-ONLY0-NEXT:    [[CONV460:%.*]] = zext i1 [[CMP459]] to i32
38951 // SIMD-ONLY0-NEXT:    [[CONV461:%.*]] = trunc i32 [[CONV460]] to i8
38952 // SIMD-ONLY0-NEXT:    store i8 [[CONV461]], ptr [[CR]], align 1
38953 // SIMD-ONLY0-NEXT:    [[TMP288:%.*]] = load i8, ptr [[CR]], align 1
38954 // SIMD-ONLY0-NEXT:    [[TOBOOL462:%.*]] = icmp ne i8 [[TMP288]], 0
38955 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL462]], label [[IF_THEN463:%.*]], label [[IF_ELSE464:%.*]]
38956 // SIMD-ONLY0:       if.then463:
38957 // SIMD-ONLY0-NEXT:    [[TMP289:%.*]] = load i8, ptr [[CD]], align 1
38958 // SIMD-ONLY0-NEXT:    store i8 [[TMP289]], ptr [[CX]], align 1
38959 // SIMD-ONLY0-NEXT:    br label [[IF_END465:%.*]]
38960 // SIMD-ONLY0:       if.else464:
38961 // SIMD-ONLY0-NEXT:    [[TMP290:%.*]] = load i8, ptr [[CX]], align 1
38962 // SIMD-ONLY0-NEXT:    store i8 [[TMP290]], ptr [[CV]], align 1
38963 // SIMD-ONLY0-NEXT:    br label [[IF_END465]]
38964 // SIMD-ONLY0:       if.end465:
38965 // SIMD-ONLY0-NEXT:    [[TMP291:%.*]] = load i8, ptr [[CE]], align 1
38966 // SIMD-ONLY0-NEXT:    [[CONV466:%.*]] = sext i8 [[TMP291]] to i32
38967 // SIMD-ONLY0-NEXT:    [[TMP292:%.*]] = load i8, ptr [[CX]], align 1
38968 // SIMD-ONLY0-NEXT:    [[CONV467:%.*]] = sext i8 [[TMP292]] to i32
38969 // SIMD-ONLY0-NEXT:    [[CMP468:%.*]] = icmp eq i32 [[CONV466]], [[CONV467]]
38970 // SIMD-ONLY0-NEXT:    [[CONV469:%.*]] = zext i1 [[CMP468]] to i32
38971 // SIMD-ONLY0-NEXT:    [[CONV470:%.*]] = trunc i32 [[CONV469]] to i8
38972 // SIMD-ONLY0-NEXT:    store i8 [[CONV470]], ptr [[CR]], align 1
38973 // SIMD-ONLY0-NEXT:    [[TMP293:%.*]] = load i8, ptr [[CR]], align 1
38974 // SIMD-ONLY0-NEXT:    [[TOBOOL471:%.*]] = icmp ne i8 [[TMP293]], 0
38975 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL471]], label [[IF_THEN472:%.*]], label [[IF_ELSE473:%.*]]
38976 // SIMD-ONLY0:       if.then472:
38977 // SIMD-ONLY0-NEXT:    [[TMP294:%.*]] = load i8, ptr [[CD]], align 1
38978 // SIMD-ONLY0-NEXT:    store i8 [[TMP294]], ptr [[CX]], align 1
38979 // SIMD-ONLY0-NEXT:    br label [[IF_END474:%.*]]
38980 // SIMD-ONLY0:       if.else473:
38981 // SIMD-ONLY0-NEXT:    [[TMP295:%.*]] = load i8, ptr [[CX]], align 1
38982 // SIMD-ONLY0-NEXT:    store i8 [[TMP295]], ptr [[CV]], align 1
38983 // SIMD-ONLY0-NEXT:    br label [[IF_END474]]
38984 // SIMD-ONLY0:       if.end474:
38985 // SIMD-ONLY0-NEXT:    [[TMP296:%.*]] = load i8, ptr [[CX]], align 1
38986 // SIMD-ONLY0-NEXT:    store i8 [[TMP296]], ptr [[CV]], align 1
38987 // SIMD-ONLY0-NEXT:    [[TMP297:%.*]] = load i8, ptr [[CE]], align 1
38988 // SIMD-ONLY0-NEXT:    [[CONV475:%.*]] = sext i8 [[TMP297]] to i32
38989 // SIMD-ONLY0-NEXT:    [[TMP298:%.*]] = load i8, ptr [[CX]], align 1
38990 // SIMD-ONLY0-NEXT:    [[CONV476:%.*]] = sext i8 [[TMP298]] to i32
38991 // SIMD-ONLY0-NEXT:    [[CMP477:%.*]] = icmp sgt i32 [[CONV475]], [[CONV476]]
38992 // SIMD-ONLY0-NEXT:    br i1 [[CMP477]], label [[IF_THEN479:%.*]], label [[IF_END480:%.*]]
38993 // SIMD-ONLY0:       if.then479:
38994 // SIMD-ONLY0-NEXT:    [[TMP299:%.*]] = load i8, ptr [[CE]], align 1
38995 // SIMD-ONLY0-NEXT:    store i8 [[TMP299]], ptr [[CX]], align 1
38996 // SIMD-ONLY0-NEXT:    br label [[IF_END480]]
38997 // SIMD-ONLY0:       if.end480:
38998 // SIMD-ONLY0-NEXT:    [[TMP300:%.*]] = load i8, ptr [[CX]], align 1
38999 // SIMD-ONLY0-NEXT:    store i8 [[TMP300]], ptr [[CV]], align 1
39000 // SIMD-ONLY0-NEXT:    [[TMP301:%.*]] = load i8, ptr [[CX]], align 1
39001 // SIMD-ONLY0-NEXT:    [[CONV481:%.*]] = sext i8 [[TMP301]] to i32
39002 // SIMD-ONLY0-NEXT:    [[TMP302:%.*]] = load i8, ptr [[CE]], align 1
39003 // SIMD-ONLY0-NEXT:    [[CONV482:%.*]] = sext i8 [[TMP302]] to i32
39004 // SIMD-ONLY0-NEXT:    [[CMP483:%.*]] = icmp sgt i32 [[CONV481]], [[CONV482]]
39005 // SIMD-ONLY0-NEXT:    br i1 [[CMP483]], label [[IF_THEN485:%.*]], label [[IF_END486:%.*]]
39006 // SIMD-ONLY0:       if.then485:
39007 // SIMD-ONLY0-NEXT:    [[TMP303:%.*]] = load i8, ptr [[CE]], align 1
39008 // SIMD-ONLY0-NEXT:    store i8 [[TMP303]], ptr [[CX]], align 1
39009 // SIMD-ONLY0-NEXT:    br label [[IF_END486]]
39010 // SIMD-ONLY0:       if.end486:
39011 // SIMD-ONLY0-NEXT:    [[TMP304:%.*]] = load i8, ptr [[CX]], align 1
39012 // SIMD-ONLY0-NEXT:    store i8 [[TMP304]], ptr [[CV]], align 1
39013 // SIMD-ONLY0-NEXT:    [[TMP305:%.*]] = load i8, ptr [[CE]], align 1
39014 // SIMD-ONLY0-NEXT:    [[CONV487:%.*]] = sext i8 [[TMP305]] to i32
39015 // SIMD-ONLY0-NEXT:    [[TMP306:%.*]] = load i8, ptr [[CX]], align 1
39016 // SIMD-ONLY0-NEXT:    [[CONV488:%.*]] = sext i8 [[TMP306]] to i32
39017 // SIMD-ONLY0-NEXT:    [[CMP489:%.*]] = icmp slt i32 [[CONV487]], [[CONV488]]
39018 // SIMD-ONLY0-NEXT:    br i1 [[CMP489]], label [[IF_THEN491:%.*]], label [[IF_END492:%.*]]
39019 // SIMD-ONLY0:       if.then491:
39020 // SIMD-ONLY0-NEXT:    [[TMP307:%.*]] = load i8, ptr [[CE]], align 1
39021 // SIMD-ONLY0-NEXT:    store i8 [[TMP307]], ptr [[CX]], align 1
39022 // SIMD-ONLY0-NEXT:    br label [[IF_END492]]
39023 // SIMD-ONLY0:       if.end492:
39024 // SIMD-ONLY0-NEXT:    [[TMP308:%.*]] = load i8, ptr [[CX]], align 1
39025 // SIMD-ONLY0-NEXT:    store i8 [[TMP308]], ptr [[CV]], align 1
39026 // SIMD-ONLY0-NEXT:    [[TMP309:%.*]] = load i8, ptr [[CX]], align 1
39027 // SIMD-ONLY0-NEXT:    [[CONV493:%.*]] = sext i8 [[TMP309]] to i32
39028 // SIMD-ONLY0-NEXT:    [[TMP310:%.*]] = load i8, ptr [[CE]], align 1
39029 // SIMD-ONLY0-NEXT:    [[CONV494:%.*]] = sext i8 [[TMP310]] to i32
39030 // SIMD-ONLY0-NEXT:    [[CMP495:%.*]] = icmp slt i32 [[CONV493]], [[CONV494]]
39031 // SIMD-ONLY0-NEXT:    br i1 [[CMP495]], label [[IF_THEN497:%.*]], label [[IF_END498:%.*]]
39032 // SIMD-ONLY0:       if.then497:
39033 // SIMD-ONLY0-NEXT:    [[TMP311:%.*]] = load i8, ptr [[CE]], align 1
39034 // SIMD-ONLY0-NEXT:    store i8 [[TMP311]], ptr [[CX]], align 1
39035 // SIMD-ONLY0-NEXT:    br label [[IF_END498]]
39036 // SIMD-ONLY0:       if.end498:
39037 // SIMD-ONLY0-NEXT:    [[TMP312:%.*]] = load i8, ptr [[CX]], align 1
39038 // SIMD-ONLY0-NEXT:    store i8 [[TMP312]], ptr [[CV]], align 1
39039 // SIMD-ONLY0-NEXT:    [[TMP313:%.*]] = load i8, ptr [[CX]], align 1
39040 // SIMD-ONLY0-NEXT:    [[CONV499:%.*]] = sext i8 [[TMP313]] to i32
39041 // SIMD-ONLY0-NEXT:    [[TMP314:%.*]] = load i8, ptr [[CE]], align 1
39042 // SIMD-ONLY0-NEXT:    [[CONV500:%.*]] = sext i8 [[TMP314]] to i32
39043 // SIMD-ONLY0-NEXT:    [[CMP501:%.*]] = icmp eq i32 [[CONV499]], [[CONV500]]
39044 // SIMD-ONLY0-NEXT:    br i1 [[CMP501]], label [[IF_THEN503:%.*]], label [[IF_END504:%.*]]
39045 // SIMD-ONLY0:       if.then503:
39046 // SIMD-ONLY0-NEXT:    [[TMP315:%.*]] = load i8, ptr [[CD]], align 1
39047 // SIMD-ONLY0-NEXT:    store i8 [[TMP315]], ptr [[CX]], align 1
39048 // SIMD-ONLY0-NEXT:    br label [[IF_END504]]
39049 // SIMD-ONLY0:       if.end504:
39050 // SIMD-ONLY0-NEXT:    [[TMP316:%.*]] = load i8, ptr [[CX]], align 1
39051 // SIMD-ONLY0-NEXT:    store i8 [[TMP316]], ptr [[CV]], align 1
39052 // SIMD-ONLY0-NEXT:    [[TMP317:%.*]] = load i8, ptr [[CE]], align 1
39053 // SIMD-ONLY0-NEXT:    [[CONV505:%.*]] = sext i8 [[TMP317]] to i32
39054 // SIMD-ONLY0-NEXT:    [[TMP318:%.*]] = load i8, ptr [[CX]], align 1
39055 // SIMD-ONLY0-NEXT:    [[CONV506:%.*]] = sext i8 [[TMP318]] to i32
39056 // SIMD-ONLY0-NEXT:    [[CMP507:%.*]] = icmp eq i32 [[CONV505]], [[CONV506]]
39057 // SIMD-ONLY0-NEXT:    br i1 [[CMP507]], label [[IF_THEN509:%.*]], label [[IF_END510:%.*]]
39058 // SIMD-ONLY0:       if.then509:
39059 // SIMD-ONLY0-NEXT:    [[TMP319:%.*]] = load i8, ptr [[CD]], align 1
39060 // SIMD-ONLY0-NEXT:    store i8 [[TMP319]], ptr [[CX]], align 1
39061 // SIMD-ONLY0-NEXT:    br label [[IF_END510]]
39062 // SIMD-ONLY0:       if.end510:
39063 // SIMD-ONLY0-NEXT:    [[TMP320:%.*]] = load i8, ptr [[CE]], align 1
39064 // SIMD-ONLY0-NEXT:    [[CONV511:%.*]] = sext i8 [[TMP320]] to i32
39065 // SIMD-ONLY0-NEXT:    [[TMP321:%.*]] = load i8, ptr [[CX]], align 1
39066 // SIMD-ONLY0-NEXT:    [[CONV512:%.*]] = sext i8 [[TMP321]] to i32
39067 // SIMD-ONLY0-NEXT:    [[CMP513:%.*]] = icmp sgt i32 [[CONV511]], [[CONV512]]
39068 // SIMD-ONLY0-NEXT:    br i1 [[CMP513]], label [[IF_THEN515:%.*]], label [[IF_END516:%.*]]
39069 // SIMD-ONLY0:       if.then515:
39070 // SIMD-ONLY0-NEXT:    [[TMP322:%.*]] = load i8, ptr [[CE]], align 1
39071 // SIMD-ONLY0-NEXT:    store i8 [[TMP322]], ptr [[CX]], align 1
39072 // SIMD-ONLY0-NEXT:    br label [[IF_END516]]
39073 // SIMD-ONLY0:       if.end516:
39074 // SIMD-ONLY0-NEXT:    [[TMP323:%.*]] = load i8, ptr [[CX]], align 1
39075 // SIMD-ONLY0-NEXT:    store i8 [[TMP323]], ptr [[CV]], align 1
39076 // SIMD-ONLY0-NEXT:    [[TMP324:%.*]] = load i8, ptr [[CX]], align 1
39077 // SIMD-ONLY0-NEXT:    [[CONV517:%.*]] = sext i8 [[TMP324]] to i32
39078 // SIMD-ONLY0-NEXT:    [[TMP325:%.*]] = load i8, ptr [[CE]], align 1
39079 // SIMD-ONLY0-NEXT:    [[CONV518:%.*]] = sext i8 [[TMP325]] to i32
39080 // SIMD-ONLY0-NEXT:    [[CMP519:%.*]] = icmp sgt i32 [[CONV517]], [[CONV518]]
39081 // SIMD-ONLY0-NEXT:    br i1 [[CMP519]], label [[IF_THEN521:%.*]], label [[IF_END522:%.*]]
39082 // SIMD-ONLY0:       if.then521:
39083 // SIMD-ONLY0-NEXT:    [[TMP326:%.*]] = load i8, ptr [[CE]], align 1
39084 // SIMD-ONLY0-NEXT:    store i8 [[TMP326]], ptr [[CX]], align 1
39085 // SIMD-ONLY0-NEXT:    br label [[IF_END522]]
39086 // SIMD-ONLY0:       if.end522:
39087 // SIMD-ONLY0-NEXT:    [[TMP327:%.*]] = load i8, ptr [[CX]], align 1
39088 // SIMD-ONLY0-NEXT:    store i8 [[TMP327]], ptr [[CV]], align 1
39089 // SIMD-ONLY0-NEXT:    [[TMP328:%.*]] = load i8, ptr [[CE]], align 1
39090 // SIMD-ONLY0-NEXT:    [[CONV523:%.*]] = sext i8 [[TMP328]] to i32
39091 // SIMD-ONLY0-NEXT:    [[TMP329:%.*]] = load i8, ptr [[CX]], align 1
39092 // SIMD-ONLY0-NEXT:    [[CONV524:%.*]] = sext i8 [[TMP329]] to i32
39093 // SIMD-ONLY0-NEXT:    [[CMP525:%.*]] = icmp slt i32 [[CONV523]], [[CONV524]]
39094 // SIMD-ONLY0-NEXT:    br i1 [[CMP525]], label [[IF_THEN527:%.*]], label [[IF_END528:%.*]]
39095 // SIMD-ONLY0:       if.then527:
39096 // SIMD-ONLY0-NEXT:    [[TMP330:%.*]] = load i8, ptr [[CE]], align 1
39097 // SIMD-ONLY0-NEXT:    store i8 [[TMP330]], ptr [[CX]], align 1
39098 // SIMD-ONLY0-NEXT:    br label [[IF_END528]]
39099 // SIMD-ONLY0:       if.end528:
39100 // SIMD-ONLY0-NEXT:    [[TMP331:%.*]] = load i8, ptr [[CX]], align 1
39101 // SIMD-ONLY0-NEXT:    store i8 [[TMP331]], ptr [[CV]], align 1
39102 // SIMD-ONLY0-NEXT:    [[TMP332:%.*]] = load i8, ptr [[CX]], align 1
39103 // SIMD-ONLY0-NEXT:    [[CONV529:%.*]] = sext i8 [[TMP332]] to i32
39104 // SIMD-ONLY0-NEXT:    [[TMP333:%.*]] = load i8, ptr [[CE]], align 1
39105 // SIMD-ONLY0-NEXT:    [[CONV530:%.*]] = sext i8 [[TMP333]] to i32
39106 // SIMD-ONLY0-NEXT:    [[CMP531:%.*]] = icmp slt i32 [[CONV529]], [[CONV530]]
39107 // SIMD-ONLY0-NEXT:    br i1 [[CMP531]], label [[IF_THEN533:%.*]], label [[IF_END534:%.*]]
39108 // SIMD-ONLY0:       if.then533:
39109 // SIMD-ONLY0-NEXT:    [[TMP334:%.*]] = load i8, ptr [[CE]], align 1
39110 // SIMD-ONLY0-NEXT:    store i8 [[TMP334]], ptr [[CX]], align 1
39111 // SIMD-ONLY0-NEXT:    br label [[IF_END534]]
39112 // SIMD-ONLY0:       if.end534:
39113 // SIMD-ONLY0-NEXT:    [[TMP335:%.*]] = load i8, ptr [[CX]], align 1
39114 // SIMD-ONLY0-NEXT:    store i8 [[TMP335]], ptr [[CV]], align 1
39115 // SIMD-ONLY0-NEXT:    [[TMP336:%.*]] = load i8, ptr [[CX]], align 1
39116 // SIMD-ONLY0-NEXT:    [[CONV535:%.*]] = sext i8 [[TMP336]] to i32
39117 // SIMD-ONLY0-NEXT:    [[TMP337:%.*]] = load i8, ptr [[CE]], align 1
39118 // SIMD-ONLY0-NEXT:    [[CONV536:%.*]] = sext i8 [[TMP337]] to i32
39119 // SIMD-ONLY0-NEXT:    [[CMP537:%.*]] = icmp eq i32 [[CONV535]], [[CONV536]]
39120 // SIMD-ONLY0-NEXT:    br i1 [[CMP537]], label [[IF_THEN539:%.*]], label [[IF_END540:%.*]]
39121 // SIMD-ONLY0:       if.then539:
39122 // SIMD-ONLY0-NEXT:    [[TMP338:%.*]] = load i8, ptr [[CD]], align 1
39123 // SIMD-ONLY0-NEXT:    store i8 [[TMP338]], ptr [[CX]], align 1
39124 // SIMD-ONLY0-NEXT:    br label [[IF_END540]]
39125 // SIMD-ONLY0:       if.end540:
39126 // SIMD-ONLY0-NEXT:    [[TMP339:%.*]] = load i8, ptr [[CX]], align 1
39127 // SIMD-ONLY0-NEXT:    store i8 [[TMP339]], ptr [[CV]], align 1
39128 // SIMD-ONLY0-NEXT:    [[TMP340:%.*]] = load i8, ptr [[CE]], align 1
39129 // SIMD-ONLY0-NEXT:    [[CONV541:%.*]] = sext i8 [[TMP340]] to i32
39130 // SIMD-ONLY0-NEXT:    [[TMP341:%.*]] = load i8, ptr [[CX]], align 1
39131 // SIMD-ONLY0-NEXT:    [[CONV542:%.*]] = sext i8 [[TMP341]] to i32
39132 // SIMD-ONLY0-NEXT:    [[CMP543:%.*]] = icmp eq i32 [[CONV541]], [[CONV542]]
39133 // SIMD-ONLY0-NEXT:    br i1 [[CMP543]], label [[IF_THEN545:%.*]], label [[IF_END546:%.*]]
39134 // SIMD-ONLY0:       if.then545:
39135 // SIMD-ONLY0-NEXT:    [[TMP342:%.*]] = load i8, ptr [[CD]], align 1
39136 // SIMD-ONLY0-NEXT:    store i8 [[TMP342]], ptr [[CX]], align 1
39137 // SIMD-ONLY0-NEXT:    br label [[IF_END546]]
39138 // SIMD-ONLY0:       if.end546:
39139 // SIMD-ONLY0-NEXT:    [[TMP343:%.*]] = load i8, ptr [[CX]], align 1
39140 // SIMD-ONLY0-NEXT:    store i8 [[TMP343]], ptr [[CV]], align 1
39141 // SIMD-ONLY0-NEXT:    [[TMP344:%.*]] = load i8, ptr [[CX]], align 1
39142 // SIMD-ONLY0-NEXT:    [[CONV547:%.*]] = sext i8 [[TMP344]] to i32
39143 // SIMD-ONLY0-NEXT:    [[TMP345:%.*]] = load i8, ptr [[CE]], align 1
39144 // SIMD-ONLY0-NEXT:    [[CONV548:%.*]] = sext i8 [[TMP345]] to i32
39145 // SIMD-ONLY0-NEXT:    [[CMP549:%.*]] = icmp eq i32 [[CONV547]], [[CONV548]]
39146 // SIMD-ONLY0-NEXT:    br i1 [[CMP549]], label [[IF_THEN551:%.*]], label [[IF_ELSE552:%.*]]
39147 // SIMD-ONLY0:       if.then551:
39148 // SIMD-ONLY0-NEXT:    [[TMP346:%.*]] = load i8, ptr [[CD]], align 1
39149 // SIMD-ONLY0-NEXT:    store i8 [[TMP346]], ptr [[CX]], align 1
39150 // SIMD-ONLY0-NEXT:    br label [[IF_END553:%.*]]
39151 // SIMD-ONLY0:       if.else552:
39152 // SIMD-ONLY0-NEXT:    [[TMP347:%.*]] = load i8, ptr [[CX]], align 1
39153 // SIMD-ONLY0-NEXT:    store i8 [[TMP347]], ptr [[CV]], align 1
39154 // SIMD-ONLY0-NEXT:    br label [[IF_END553]]
39155 // SIMD-ONLY0:       if.end553:
39156 // SIMD-ONLY0-NEXT:    [[TMP348:%.*]] = load i8, ptr [[CE]], align 1
39157 // SIMD-ONLY0-NEXT:    [[CONV554:%.*]] = sext i8 [[TMP348]] to i32
39158 // SIMD-ONLY0-NEXT:    [[TMP349:%.*]] = load i8, ptr [[CX]], align 1
39159 // SIMD-ONLY0-NEXT:    [[CONV555:%.*]] = sext i8 [[TMP349]] to i32
39160 // SIMD-ONLY0-NEXT:    [[CMP556:%.*]] = icmp eq i32 [[CONV554]], [[CONV555]]
39161 // SIMD-ONLY0-NEXT:    br i1 [[CMP556]], label [[IF_THEN558:%.*]], label [[IF_ELSE559:%.*]]
39162 // SIMD-ONLY0:       if.then558:
39163 // SIMD-ONLY0-NEXT:    [[TMP350:%.*]] = load i8, ptr [[CD]], align 1
39164 // SIMD-ONLY0-NEXT:    store i8 [[TMP350]], ptr [[CX]], align 1
39165 // SIMD-ONLY0-NEXT:    br label [[IF_END560:%.*]]
39166 // SIMD-ONLY0:       if.else559:
39167 // SIMD-ONLY0-NEXT:    [[TMP351:%.*]] = load i8, ptr [[CX]], align 1
39168 // SIMD-ONLY0-NEXT:    store i8 [[TMP351]], ptr [[CV]], align 1
39169 // SIMD-ONLY0-NEXT:    br label [[IF_END560]]
39170 // SIMD-ONLY0:       if.end560:
39171 // SIMD-ONLY0-NEXT:    [[TMP352:%.*]] = load i8, ptr [[CX]], align 1
39172 // SIMD-ONLY0-NEXT:    [[CONV561:%.*]] = sext i8 [[TMP352]] to i32
39173 // SIMD-ONLY0-NEXT:    [[TMP353:%.*]] = load i8, ptr [[CE]], align 1
39174 // SIMD-ONLY0-NEXT:    [[CONV562:%.*]] = sext i8 [[TMP353]] to i32
39175 // SIMD-ONLY0-NEXT:    [[CMP563:%.*]] = icmp eq i32 [[CONV561]], [[CONV562]]
39176 // SIMD-ONLY0-NEXT:    [[CONV564:%.*]] = zext i1 [[CMP563]] to i32
39177 // SIMD-ONLY0-NEXT:    [[CONV565:%.*]] = trunc i32 [[CONV564]] to i8
39178 // SIMD-ONLY0-NEXT:    store i8 [[CONV565]], ptr [[CR]], align 1
39179 // SIMD-ONLY0-NEXT:    [[TMP354:%.*]] = load i8, ptr [[CR]], align 1
39180 // SIMD-ONLY0-NEXT:    [[TOBOOL566:%.*]] = icmp ne i8 [[TMP354]], 0
39181 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL566]], label [[IF_THEN567:%.*]], label [[IF_END568:%.*]]
39182 // SIMD-ONLY0:       if.then567:
39183 // SIMD-ONLY0-NEXT:    [[TMP355:%.*]] = load i8, ptr [[CD]], align 1
39184 // SIMD-ONLY0-NEXT:    store i8 [[TMP355]], ptr [[CX]], align 1
39185 // SIMD-ONLY0-NEXT:    br label [[IF_END568]]
39186 // SIMD-ONLY0:       if.end568:
39187 // SIMD-ONLY0-NEXT:    [[TMP356:%.*]] = load i8, ptr [[CE]], align 1
39188 // SIMD-ONLY0-NEXT:    [[CONV569:%.*]] = sext i8 [[TMP356]] to i32
39189 // SIMD-ONLY0-NEXT:    [[TMP357:%.*]] = load i8, ptr [[CX]], align 1
39190 // SIMD-ONLY0-NEXT:    [[CONV570:%.*]] = sext i8 [[TMP357]] to i32
39191 // SIMD-ONLY0-NEXT:    [[CMP571:%.*]] = icmp eq i32 [[CONV569]], [[CONV570]]
39192 // SIMD-ONLY0-NEXT:    [[CONV572:%.*]] = zext i1 [[CMP571]] to i32
39193 // SIMD-ONLY0-NEXT:    [[CONV573:%.*]] = trunc i32 [[CONV572]] to i8
39194 // SIMD-ONLY0-NEXT:    store i8 [[CONV573]], ptr [[CR]], align 1
39195 // SIMD-ONLY0-NEXT:    [[TMP358:%.*]] = load i8, ptr [[CR]], align 1
39196 // SIMD-ONLY0-NEXT:    [[TOBOOL574:%.*]] = icmp ne i8 [[TMP358]], 0
39197 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL574]], label [[IF_THEN575:%.*]], label [[IF_END576:%.*]]
39198 // SIMD-ONLY0:       if.then575:
39199 // SIMD-ONLY0-NEXT:    [[TMP359:%.*]] = load i8, ptr [[CD]], align 1
39200 // SIMD-ONLY0-NEXT:    store i8 [[TMP359]], ptr [[CX]], align 1
39201 // SIMD-ONLY0-NEXT:    br label [[IF_END576]]
39202 // SIMD-ONLY0:       if.end576:
39203 // SIMD-ONLY0-NEXT:    [[TMP360:%.*]] = load i8, ptr [[CX]], align 1
39204 // SIMD-ONLY0-NEXT:    [[CONV577:%.*]] = sext i8 [[TMP360]] to i32
39205 // SIMD-ONLY0-NEXT:    [[TMP361:%.*]] = load i8, ptr [[CE]], align 1
39206 // SIMD-ONLY0-NEXT:    [[CONV578:%.*]] = sext i8 [[TMP361]] to i32
39207 // SIMD-ONLY0-NEXT:    [[CMP579:%.*]] = icmp eq i32 [[CONV577]], [[CONV578]]
39208 // SIMD-ONLY0-NEXT:    [[CONV580:%.*]] = zext i1 [[CMP579]] to i32
39209 // SIMD-ONLY0-NEXT:    [[CONV581:%.*]] = trunc i32 [[CONV580]] to i8
39210 // SIMD-ONLY0-NEXT:    store i8 [[CONV581]], ptr [[CR]], align 1
39211 // SIMD-ONLY0-NEXT:    [[TMP362:%.*]] = load i8, ptr [[CR]], align 1
39212 // SIMD-ONLY0-NEXT:    [[TOBOOL582:%.*]] = icmp ne i8 [[TMP362]], 0
39213 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL582]], label [[IF_THEN583:%.*]], label [[IF_ELSE584:%.*]]
39214 // SIMD-ONLY0:       if.then583:
39215 // SIMD-ONLY0-NEXT:    [[TMP363:%.*]] = load i8, ptr [[CD]], align 1
39216 // SIMD-ONLY0-NEXT:    store i8 [[TMP363]], ptr [[CX]], align 1
39217 // SIMD-ONLY0-NEXT:    br label [[IF_END585:%.*]]
39218 // SIMD-ONLY0:       if.else584:
39219 // SIMD-ONLY0-NEXT:    [[TMP364:%.*]] = load i8, ptr [[CX]], align 1
39220 // SIMD-ONLY0-NEXT:    store i8 [[TMP364]], ptr [[CV]], align 1
39221 // SIMD-ONLY0-NEXT:    br label [[IF_END585]]
39222 // SIMD-ONLY0:       if.end585:
39223 // SIMD-ONLY0-NEXT:    [[TMP365:%.*]] = load i8, ptr [[CE]], align 1
39224 // SIMD-ONLY0-NEXT:    [[CONV586:%.*]] = sext i8 [[TMP365]] to i32
39225 // SIMD-ONLY0-NEXT:    [[TMP366:%.*]] = load i8, ptr [[CX]], align 1
39226 // SIMD-ONLY0-NEXT:    [[CONV587:%.*]] = sext i8 [[TMP366]] to i32
39227 // SIMD-ONLY0-NEXT:    [[CMP588:%.*]] = icmp eq i32 [[CONV586]], [[CONV587]]
39228 // SIMD-ONLY0-NEXT:    [[CONV589:%.*]] = zext i1 [[CMP588]] to i32
39229 // SIMD-ONLY0-NEXT:    [[CONV590:%.*]] = trunc i32 [[CONV589]] to i8
39230 // SIMD-ONLY0-NEXT:    store i8 [[CONV590]], ptr [[CR]], align 1
39231 // SIMD-ONLY0-NEXT:    [[TMP367:%.*]] = load i8, ptr [[CR]], align 1
39232 // SIMD-ONLY0-NEXT:    [[TOBOOL591:%.*]] = icmp ne i8 [[TMP367]], 0
39233 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL591]], label [[IF_THEN592:%.*]], label [[IF_ELSE593:%.*]]
39234 // SIMD-ONLY0:       if.then592:
39235 // SIMD-ONLY0-NEXT:    [[TMP368:%.*]] = load i8, ptr [[CD]], align 1
39236 // SIMD-ONLY0-NEXT:    store i8 [[TMP368]], ptr [[CX]], align 1
39237 // SIMD-ONLY0-NEXT:    br label [[IF_END594:%.*]]
39238 // SIMD-ONLY0:       if.else593:
39239 // SIMD-ONLY0-NEXT:    [[TMP369:%.*]] = load i8, ptr [[CX]], align 1
39240 // SIMD-ONLY0-NEXT:    store i8 [[TMP369]], ptr [[CV]], align 1
39241 // SIMD-ONLY0-NEXT:    br label [[IF_END594]]
39242 // SIMD-ONLY0:       if.end594:
39243 // SIMD-ONLY0-NEXT:    [[TMP370:%.*]] = load i8, ptr [[CX]], align 1
39244 // SIMD-ONLY0-NEXT:    store i8 [[TMP370]], ptr [[CV]], align 1
39245 // SIMD-ONLY0-NEXT:    [[TMP371:%.*]] = load i8, ptr [[CE]], align 1
39246 // SIMD-ONLY0-NEXT:    [[CONV595:%.*]] = sext i8 [[TMP371]] to i32
39247 // SIMD-ONLY0-NEXT:    [[TMP372:%.*]] = load i8, ptr [[CX]], align 1
39248 // SIMD-ONLY0-NEXT:    [[CONV596:%.*]] = sext i8 [[TMP372]] to i32
39249 // SIMD-ONLY0-NEXT:    [[CMP597:%.*]] = icmp sgt i32 [[CONV595]], [[CONV596]]
39250 // SIMD-ONLY0-NEXT:    br i1 [[CMP597]], label [[IF_THEN599:%.*]], label [[IF_END600:%.*]]
39251 // SIMD-ONLY0:       if.then599:
39252 // SIMD-ONLY0-NEXT:    [[TMP373:%.*]] = load i8, ptr [[CE]], align 1
39253 // SIMD-ONLY0-NEXT:    store i8 [[TMP373]], ptr [[CX]], align 1
39254 // SIMD-ONLY0-NEXT:    br label [[IF_END600]]
39255 // SIMD-ONLY0:       if.end600:
39256 // SIMD-ONLY0-NEXT:    [[TMP374:%.*]] = load i8, ptr [[CX]], align 1
39257 // SIMD-ONLY0-NEXT:    store i8 [[TMP374]], ptr [[CV]], align 1
39258 // SIMD-ONLY0-NEXT:    [[TMP375:%.*]] = load i8, ptr [[CX]], align 1
39259 // SIMD-ONLY0-NEXT:    [[CONV601:%.*]] = sext i8 [[TMP375]] to i32
39260 // SIMD-ONLY0-NEXT:    [[TMP376:%.*]] = load i8, ptr [[CE]], align 1
39261 // SIMD-ONLY0-NEXT:    [[CONV602:%.*]] = sext i8 [[TMP376]] to i32
39262 // SIMD-ONLY0-NEXT:    [[CMP603:%.*]] = icmp sgt i32 [[CONV601]], [[CONV602]]
39263 // SIMD-ONLY0-NEXT:    br i1 [[CMP603]], label [[IF_THEN605:%.*]], label [[IF_END606:%.*]]
39264 // SIMD-ONLY0:       if.then605:
39265 // SIMD-ONLY0-NEXT:    [[TMP377:%.*]] = load i8, ptr [[CE]], align 1
39266 // SIMD-ONLY0-NEXT:    store i8 [[TMP377]], ptr [[CX]], align 1
39267 // SIMD-ONLY0-NEXT:    br label [[IF_END606]]
39268 // SIMD-ONLY0:       if.end606:
39269 // SIMD-ONLY0-NEXT:    [[TMP378:%.*]] = load i8, ptr [[CX]], align 1
39270 // SIMD-ONLY0-NEXT:    store i8 [[TMP378]], ptr [[CV]], align 1
39271 // SIMD-ONLY0-NEXT:    [[TMP379:%.*]] = load i8, ptr [[CE]], align 1
39272 // SIMD-ONLY0-NEXT:    [[CONV607:%.*]] = sext i8 [[TMP379]] to i32
39273 // SIMD-ONLY0-NEXT:    [[TMP380:%.*]] = load i8, ptr [[CX]], align 1
39274 // SIMD-ONLY0-NEXT:    [[CONV608:%.*]] = sext i8 [[TMP380]] to i32
39275 // SIMD-ONLY0-NEXT:    [[CMP609:%.*]] = icmp slt i32 [[CONV607]], [[CONV608]]
39276 // SIMD-ONLY0-NEXT:    br i1 [[CMP609]], label [[IF_THEN611:%.*]], label [[IF_END612:%.*]]
39277 // SIMD-ONLY0:       if.then611:
39278 // SIMD-ONLY0-NEXT:    [[TMP381:%.*]] = load i8, ptr [[CE]], align 1
39279 // SIMD-ONLY0-NEXT:    store i8 [[TMP381]], ptr [[CX]], align 1
39280 // SIMD-ONLY0-NEXT:    br label [[IF_END612]]
39281 // SIMD-ONLY0:       if.end612:
39282 // SIMD-ONLY0-NEXT:    [[TMP382:%.*]] = load i8, ptr [[CX]], align 1
39283 // SIMD-ONLY0-NEXT:    store i8 [[TMP382]], ptr [[CV]], align 1
39284 // SIMD-ONLY0-NEXT:    [[TMP383:%.*]] = load i8, ptr [[CX]], align 1
39285 // SIMD-ONLY0-NEXT:    [[CONV613:%.*]] = sext i8 [[TMP383]] to i32
39286 // SIMD-ONLY0-NEXT:    [[TMP384:%.*]] = load i8, ptr [[CE]], align 1
39287 // SIMD-ONLY0-NEXT:    [[CONV614:%.*]] = sext i8 [[TMP384]] to i32
39288 // SIMD-ONLY0-NEXT:    [[CMP615:%.*]] = icmp slt i32 [[CONV613]], [[CONV614]]
39289 // SIMD-ONLY0-NEXT:    br i1 [[CMP615]], label [[IF_THEN617:%.*]], label [[IF_END618:%.*]]
39290 // SIMD-ONLY0:       if.then617:
39291 // SIMD-ONLY0-NEXT:    [[TMP385:%.*]] = load i8, ptr [[CE]], align 1
39292 // SIMD-ONLY0-NEXT:    store i8 [[TMP385]], ptr [[CX]], align 1
39293 // SIMD-ONLY0-NEXT:    br label [[IF_END618]]
39294 // SIMD-ONLY0:       if.end618:
39295 // SIMD-ONLY0-NEXT:    [[TMP386:%.*]] = load i8, ptr [[CX]], align 1
39296 // SIMD-ONLY0-NEXT:    store i8 [[TMP386]], ptr [[CV]], align 1
39297 // SIMD-ONLY0-NEXT:    [[TMP387:%.*]] = load i8, ptr [[CX]], align 1
39298 // SIMD-ONLY0-NEXT:    [[CONV619:%.*]] = sext i8 [[TMP387]] to i32
39299 // SIMD-ONLY0-NEXT:    [[TMP388:%.*]] = load i8, ptr [[CE]], align 1
39300 // SIMD-ONLY0-NEXT:    [[CONV620:%.*]] = sext i8 [[TMP388]] to i32
39301 // SIMD-ONLY0-NEXT:    [[CMP621:%.*]] = icmp eq i32 [[CONV619]], [[CONV620]]
39302 // SIMD-ONLY0-NEXT:    br i1 [[CMP621]], label [[IF_THEN623:%.*]], label [[IF_END624:%.*]]
39303 // SIMD-ONLY0:       if.then623:
39304 // SIMD-ONLY0-NEXT:    [[TMP389:%.*]] = load i8, ptr [[CD]], align 1
39305 // SIMD-ONLY0-NEXT:    store i8 [[TMP389]], ptr [[CX]], align 1
39306 // SIMD-ONLY0-NEXT:    br label [[IF_END624]]
39307 // SIMD-ONLY0:       if.end624:
39308 // SIMD-ONLY0-NEXT:    [[TMP390:%.*]] = load i8, ptr [[CX]], align 1
39309 // SIMD-ONLY0-NEXT:    store i8 [[TMP390]], ptr [[CV]], align 1
39310 // SIMD-ONLY0-NEXT:    [[TMP391:%.*]] = load i8, ptr [[CE]], align 1
39311 // SIMD-ONLY0-NEXT:    [[CONV625:%.*]] = sext i8 [[TMP391]] to i32
39312 // SIMD-ONLY0-NEXT:    [[TMP392:%.*]] = load i8, ptr [[CX]], align 1
39313 // SIMD-ONLY0-NEXT:    [[CONV626:%.*]] = sext i8 [[TMP392]] to i32
39314 // SIMD-ONLY0-NEXT:    [[CMP627:%.*]] = icmp eq i32 [[CONV625]], [[CONV626]]
39315 // SIMD-ONLY0-NEXT:    br i1 [[CMP627]], label [[IF_THEN629:%.*]], label [[IF_END630:%.*]]
39316 // SIMD-ONLY0:       if.then629:
39317 // SIMD-ONLY0-NEXT:    [[TMP393:%.*]] = load i8, ptr [[CD]], align 1
39318 // SIMD-ONLY0-NEXT:    store i8 [[TMP393]], ptr [[CX]], align 1
39319 // SIMD-ONLY0-NEXT:    br label [[IF_END630]]
39320 // SIMD-ONLY0:       if.end630:
39321 // SIMD-ONLY0-NEXT:    [[TMP394:%.*]] = load i8, ptr [[CE]], align 1
39322 // SIMD-ONLY0-NEXT:    [[CONV631:%.*]] = sext i8 [[TMP394]] to i32
39323 // SIMD-ONLY0-NEXT:    [[TMP395:%.*]] = load i8, ptr [[CX]], align 1
39324 // SIMD-ONLY0-NEXT:    [[CONV632:%.*]] = sext i8 [[TMP395]] to i32
39325 // SIMD-ONLY0-NEXT:    [[CMP633:%.*]] = icmp sgt i32 [[CONV631]], [[CONV632]]
39326 // SIMD-ONLY0-NEXT:    br i1 [[CMP633]], label [[IF_THEN635:%.*]], label [[IF_END636:%.*]]
39327 // SIMD-ONLY0:       if.then635:
39328 // SIMD-ONLY0-NEXT:    [[TMP396:%.*]] = load i8, ptr [[CE]], align 1
39329 // SIMD-ONLY0-NEXT:    store i8 [[TMP396]], ptr [[CX]], align 1
39330 // SIMD-ONLY0-NEXT:    br label [[IF_END636]]
39331 // SIMD-ONLY0:       if.end636:
39332 // SIMD-ONLY0-NEXT:    [[TMP397:%.*]] = load i8, ptr [[CX]], align 1
39333 // SIMD-ONLY0-NEXT:    store i8 [[TMP397]], ptr [[CV]], align 1
39334 // SIMD-ONLY0-NEXT:    [[TMP398:%.*]] = load i8, ptr [[CX]], align 1
39335 // SIMD-ONLY0-NEXT:    [[CONV637:%.*]] = sext i8 [[TMP398]] to i32
39336 // SIMD-ONLY0-NEXT:    [[TMP399:%.*]] = load i8, ptr [[CE]], align 1
39337 // SIMD-ONLY0-NEXT:    [[CONV638:%.*]] = sext i8 [[TMP399]] to i32
39338 // SIMD-ONLY0-NEXT:    [[CMP639:%.*]] = icmp sgt i32 [[CONV637]], [[CONV638]]
39339 // SIMD-ONLY0-NEXT:    br i1 [[CMP639]], label [[IF_THEN641:%.*]], label [[IF_END642:%.*]]
39340 // SIMD-ONLY0:       if.then641:
39341 // SIMD-ONLY0-NEXT:    [[TMP400:%.*]] = load i8, ptr [[CE]], align 1
39342 // SIMD-ONLY0-NEXT:    store i8 [[TMP400]], ptr [[CX]], align 1
39343 // SIMD-ONLY0-NEXT:    br label [[IF_END642]]
39344 // SIMD-ONLY0:       if.end642:
39345 // SIMD-ONLY0-NEXT:    [[TMP401:%.*]] = load i8, ptr [[CX]], align 1
39346 // SIMD-ONLY0-NEXT:    store i8 [[TMP401]], ptr [[CV]], align 1
39347 // SIMD-ONLY0-NEXT:    [[TMP402:%.*]] = load i8, ptr [[CE]], align 1
39348 // SIMD-ONLY0-NEXT:    [[CONV643:%.*]] = sext i8 [[TMP402]] to i32
39349 // SIMD-ONLY0-NEXT:    [[TMP403:%.*]] = load i8, ptr [[CX]], align 1
39350 // SIMD-ONLY0-NEXT:    [[CONV644:%.*]] = sext i8 [[TMP403]] to i32
39351 // SIMD-ONLY0-NEXT:    [[CMP645:%.*]] = icmp slt i32 [[CONV643]], [[CONV644]]
39352 // SIMD-ONLY0-NEXT:    br i1 [[CMP645]], label [[IF_THEN647:%.*]], label [[IF_END648:%.*]]
39353 // SIMD-ONLY0:       if.then647:
39354 // SIMD-ONLY0-NEXT:    [[TMP404:%.*]] = load i8, ptr [[CE]], align 1
39355 // SIMD-ONLY0-NEXT:    store i8 [[TMP404]], ptr [[CX]], align 1
39356 // SIMD-ONLY0-NEXT:    br label [[IF_END648]]
39357 // SIMD-ONLY0:       if.end648:
39358 // SIMD-ONLY0-NEXT:    [[TMP405:%.*]] = load i8, ptr [[CX]], align 1
39359 // SIMD-ONLY0-NEXT:    store i8 [[TMP405]], ptr [[CV]], align 1
39360 // SIMD-ONLY0-NEXT:    [[TMP406:%.*]] = load i8, ptr [[CX]], align 1
39361 // SIMD-ONLY0-NEXT:    [[CONV649:%.*]] = sext i8 [[TMP406]] to i32
39362 // SIMD-ONLY0-NEXT:    [[TMP407:%.*]] = load i8, ptr [[CE]], align 1
39363 // SIMD-ONLY0-NEXT:    [[CONV650:%.*]] = sext i8 [[TMP407]] to i32
39364 // SIMD-ONLY0-NEXT:    [[CMP651:%.*]] = icmp slt i32 [[CONV649]], [[CONV650]]
39365 // SIMD-ONLY0-NEXT:    br i1 [[CMP651]], label [[IF_THEN653:%.*]], label [[IF_END654:%.*]]
39366 // SIMD-ONLY0:       if.then653:
39367 // SIMD-ONLY0-NEXT:    [[TMP408:%.*]] = load i8, ptr [[CE]], align 1
39368 // SIMD-ONLY0-NEXT:    store i8 [[TMP408]], ptr [[CX]], align 1
39369 // SIMD-ONLY0-NEXT:    br label [[IF_END654]]
39370 // SIMD-ONLY0:       if.end654:
39371 // SIMD-ONLY0-NEXT:    [[TMP409:%.*]] = load i8, ptr [[CX]], align 1
39372 // SIMD-ONLY0-NEXT:    store i8 [[TMP409]], ptr [[CV]], align 1
39373 // SIMD-ONLY0-NEXT:    [[TMP410:%.*]] = load i8, ptr [[CX]], align 1
39374 // SIMD-ONLY0-NEXT:    [[CONV655:%.*]] = sext i8 [[TMP410]] to i32
39375 // SIMD-ONLY0-NEXT:    [[TMP411:%.*]] = load i8, ptr [[CE]], align 1
39376 // SIMD-ONLY0-NEXT:    [[CONV656:%.*]] = sext i8 [[TMP411]] to i32
39377 // SIMD-ONLY0-NEXT:    [[CMP657:%.*]] = icmp eq i32 [[CONV655]], [[CONV656]]
39378 // SIMD-ONLY0-NEXT:    br i1 [[CMP657]], label [[IF_THEN659:%.*]], label [[IF_END660:%.*]]
39379 // SIMD-ONLY0:       if.then659:
39380 // SIMD-ONLY0-NEXT:    [[TMP412:%.*]] = load i8, ptr [[CD]], align 1
39381 // SIMD-ONLY0-NEXT:    store i8 [[TMP412]], ptr [[CX]], align 1
39382 // SIMD-ONLY0-NEXT:    br label [[IF_END660]]
39383 // SIMD-ONLY0:       if.end660:
39384 // SIMD-ONLY0-NEXT:    [[TMP413:%.*]] = load i8, ptr [[CX]], align 1
39385 // SIMD-ONLY0-NEXT:    store i8 [[TMP413]], ptr [[CV]], align 1
39386 // SIMD-ONLY0-NEXT:    [[TMP414:%.*]] = load i8, ptr [[CE]], align 1
39387 // SIMD-ONLY0-NEXT:    [[CONV661:%.*]] = sext i8 [[TMP414]] to i32
39388 // SIMD-ONLY0-NEXT:    [[TMP415:%.*]] = load i8, ptr [[CX]], align 1
39389 // SIMD-ONLY0-NEXT:    [[CONV662:%.*]] = sext i8 [[TMP415]] to i32
39390 // SIMD-ONLY0-NEXT:    [[CMP663:%.*]] = icmp eq i32 [[CONV661]], [[CONV662]]
39391 // SIMD-ONLY0-NEXT:    br i1 [[CMP663]], label [[IF_THEN665:%.*]], label [[IF_END666:%.*]]
39392 // SIMD-ONLY0:       if.then665:
39393 // SIMD-ONLY0-NEXT:    [[TMP416:%.*]] = load i8, ptr [[CD]], align 1
39394 // SIMD-ONLY0-NEXT:    store i8 [[TMP416]], ptr [[CX]], align 1
39395 // SIMD-ONLY0-NEXT:    br label [[IF_END666]]
39396 // SIMD-ONLY0:       if.end666:
39397 // SIMD-ONLY0-NEXT:    [[TMP417:%.*]] = load i8, ptr [[CX]], align 1
39398 // SIMD-ONLY0-NEXT:    store i8 [[TMP417]], ptr [[CV]], align 1
39399 // SIMD-ONLY0-NEXT:    [[TMP418:%.*]] = load i8, ptr [[CX]], align 1
39400 // SIMD-ONLY0-NEXT:    [[CONV667:%.*]] = sext i8 [[TMP418]] to i32
39401 // SIMD-ONLY0-NEXT:    [[TMP419:%.*]] = load i8, ptr [[CE]], align 1
39402 // SIMD-ONLY0-NEXT:    [[CONV668:%.*]] = sext i8 [[TMP419]] to i32
39403 // SIMD-ONLY0-NEXT:    [[CMP669:%.*]] = icmp eq i32 [[CONV667]], [[CONV668]]
39404 // SIMD-ONLY0-NEXT:    br i1 [[CMP669]], label [[IF_THEN671:%.*]], label [[IF_ELSE672:%.*]]
39405 // SIMD-ONLY0:       if.then671:
39406 // SIMD-ONLY0-NEXT:    [[TMP420:%.*]] = load i8, ptr [[CD]], align 1
39407 // SIMD-ONLY0-NEXT:    store i8 [[TMP420]], ptr [[CX]], align 1
39408 // SIMD-ONLY0-NEXT:    br label [[IF_END673:%.*]]
39409 // SIMD-ONLY0:       if.else672:
39410 // SIMD-ONLY0-NEXT:    [[TMP421:%.*]] = load i8, ptr [[CX]], align 1
39411 // SIMD-ONLY0-NEXT:    store i8 [[TMP421]], ptr [[CV]], align 1
39412 // SIMD-ONLY0-NEXT:    br label [[IF_END673]]
39413 // SIMD-ONLY0:       if.end673:
39414 // SIMD-ONLY0-NEXT:    [[TMP422:%.*]] = load i8, ptr [[CE]], align 1
39415 // SIMD-ONLY0-NEXT:    [[CONV674:%.*]] = sext i8 [[TMP422]] to i32
39416 // SIMD-ONLY0-NEXT:    [[TMP423:%.*]] = load i8, ptr [[CX]], align 1
39417 // SIMD-ONLY0-NEXT:    [[CONV675:%.*]] = sext i8 [[TMP423]] to i32
39418 // SIMD-ONLY0-NEXT:    [[CMP676:%.*]] = icmp eq i32 [[CONV674]], [[CONV675]]
39419 // SIMD-ONLY0-NEXT:    br i1 [[CMP676]], label [[IF_THEN678:%.*]], label [[IF_ELSE679:%.*]]
39420 // SIMD-ONLY0:       if.then678:
39421 // SIMD-ONLY0-NEXT:    [[TMP424:%.*]] = load i8, ptr [[CD]], align 1
39422 // SIMD-ONLY0-NEXT:    store i8 [[TMP424]], ptr [[CX]], align 1
39423 // SIMD-ONLY0-NEXT:    br label [[IF_END680:%.*]]
39424 // SIMD-ONLY0:       if.else679:
39425 // SIMD-ONLY0-NEXT:    [[TMP425:%.*]] = load i8, ptr [[CX]], align 1
39426 // SIMD-ONLY0-NEXT:    store i8 [[TMP425]], ptr [[CV]], align 1
39427 // SIMD-ONLY0-NEXT:    br label [[IF_END680]]
39428 // SIMD-ONLY0:       if.end680:
39429 // SIMD-ONLY0-NEXT:    [[TMP426:%.*]] = load i8, ptr [[CX]], align 1
39430 // SIMD-ONLY0-NEXT:    [[CONV681:%.*]] = sext i8 [[TMP426]] to i32
39431 // SIMD-ONLY0-NEXT:    [[TMP427:%.*]] = load i8, ptr [[CE]], align 1
39432 // SIMD-ONLY0-NEXT:    [[CONV682:%.*]] = sext i8 [[TMP427]] to i32
39433 // SIMD-ONLY0-NEXT:    [[CMP683:%.*]] = icmp eq i32 [[CONV681]], [[CONV682]]
39434 // SIMD-ONLY0-NEXT:    [[CONV684:%.*]] = zext i1 [[CMP683]] to i32
39435 // SIMD-ONLY0-NEXT:    [[CONV685:%.*]] = trunc i32 [[CONV684]] to i8
39436 // SIMD-ONLY0-NEXT:    store i8 [[CONV685]], ptr [[CR]], align 1
39437 // SIMD-ONLY0-NEXT:    [[TMP428:%.*]] = load i8, ptr [[CR]], align 1
39438 // SIMD-ONLY0-NEXT:    [[TOBOOL686:%.*]] = icmp ne i8 [[TMP428]], 0
39439 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL686]], label [[IF_THEN687:%.*]], label [[IF_END688:%.*]]
39440 // SIMD-ONLY0:       if.then687:
39441 // SIMD-ONLY0-NEXT:    [[TMP429:%.*]] = load i8, ptr [[CD]], align 1
39442 // SIMD-ONLY0-NEXT:    store i8 [[TMP429]], ptr [[CX]], align 1
39443 // SIMD-ONLY0-NEXT:    br label [[IF_END688]]
39444 // SIMD-ONLY0:       if.end688:
39445 // SIMD-ONLY0-NEXT:    [[TMP430:%.*]] = load i8, ptr [[CE]], align 1
39446 // SIMD-ONLY0-NEXT:    [[CONV689:%.*]] = sext i8 [[TMP430]] to i32
39447 // SIMD-ONLY0-NEXT:    [[TMP431:%.*]] = load i8, ptr [[CX]], align 1
39448 // SIMD-ONLY0-NEXT:    [[CONV690:%.*]] = sext i8 [[TMP431]] to i32
39449 // SIMD-ONLY0-NEXT:    [[CMP691:%.*]] = icmp eq i32 [[CONV689]], [[CONV690]]
39450 // SIMD-ONLY0-NEXT:    [[CONV692:%.*]] = zext i1 [[CMP691]] to i32
39451 // SIMD-ONLY0-NEXT:    [[CONV693:%.*]] = trunc i32 [[CONV692]] to i8
39452 // SIMD-ONLY0-NEXT:    store i8 [[CONV693]], ptr [[CR]], align 1
39453 // SIMD-ONLY0-NEXT:    [[TMP432:%.*]] = load i8, ptr [[CR]], align 1
39454 // SIMD-ONLY0-NEXT:    [[TOBOOL694:%.*]] = icmp ne i8 [[TMP432]], 0
39455 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL694]], label [[IF_THEN695:%.*]], label [[IF_END696:%.*]]
39456 // SIMD-ONLY0:       if.then695:
39457 // SIMD-ONLY0-NEXT:    [[TMP433:%.*]] = load i8, ptr [[CD]], align 1
39458 // SIMD-ONLY0-NEXT:    store i8 [[TMP433]], ptr [[CX]], align 1
39459 // SIMD-ONLY0-NEXT:    br label [[IF_END696]]
39460 // SIMD-ONLY0:       if.end696:
39461 // SIMD-ONLY0-NEXT:    [[TMP434:%.*]] = load i8, ptr [[CX]], align 1
39462 // SIMD-ONLY0-NEXT:    [[CONV697:%.*]] = sext i8 [[TMP434]] to i32
39463 // SIMD-ONLY0-NEXT:    [[TMP435:%.*]] = load i8, ptr [[CE]], align 1
39464 // SIMD-ONLY0-NEXT:    [[CONV698:%.*]] = sext i8 [[TMP435]] to i32
39465 // SIMD-ONLY0-NEXT:    [[CMP699:%.*]] = icmp eq i32 [[CONV697]], [[CONV698]]
39466 // SIMD-ONLY0-NEXT:    [[CONV700:%.*]] = zext i1 [[CMP699]] to i32
39467 // SIMD-ONLY0-NEXT:    [[CONV701:%.*]] = trunc i32 [[CONV700]] to i8
39468 // SIMD-ONLY0-NEXT:    store i8 [[CONV701]], ptr [[CR]], align 1
39469 // SIMD-ONLY0-NEXT:    [[TMP436:%.*]] = load i8, ptr [[CR]], align 1
39470 // SIMD-ONLY0-NEXT:    [[TOBOOL702:%.*]] = icmp ne i8 [[TMP436]], 0
39471 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL702]], label [[IF_THEN703:%.*]], label [[IF_ELSE704:%.*]]
39472 // SIMD-ONLY0:       if.then703:
39473 // SIMD-ONLY0-NEXT:    [[TMP437:%.*]] = load i8, ptr [[CD]], align 1
39474 // SIMD-ONLY0-NEXT:    store i8 [[TMP437]], ptr [[CX]], align 1
39475 // SIMD-ONLY0-NEXT:    br label [[IF_END705:%.*]]
39476 // SIMD-ONLY0:       if.else704:
39477 // SIMD-ONLY0-NEXT:    [[TMP438:%.*]] = load i8, ptr [[CX]], align 1
39478 // SIMD-ONLY0-NEXT:    store i8 [[TMP438]], ptr [[CV]], align 1
39479 // SIMD-ONLY0-NEXT:    br label [[IF_END705]]
39480 // SIMD-ONLY0:       if.end705:
39481 // SIMD-ONLY0-NEXT:    [[TMP439:%.*]] = load i8, ptr [[CE]], align 1
39482 // SIMD-ONLY0-NEXT:    [[CONV706:%.*]] = sext i8 [[TMP439]] to i32
39483 // SIMD-ONLY0-NEXT:    [[TMP440:%.*]] = load i8, ptr [[CX]], align 1
39484 // SIMD-ONLY0-NEXT:    [[CONV707:%.*]] = sext i8 [[TMP440]] to i32
39485 // SIMD-ONLY0-NEXT:    [[CMP708:%.*]] = icmp eq i32 [[CONV706]], [[CONV707]]
39486 // SIMD-ONLY0-NEXT:    [[CONV709:%.*]] = zext i1 [[CMP708]] to i32
39487 // SIMD-ONLY0-NEXT:    [[CONV710:%.*]] = trunc i32 [[CONV709]] to i8
39488 // SIMD-ONLY0-NEXT:    store i8 [[CONV710]], ptr [[CR]], align 1
39489 // SIMD-ONLY0-NEXT:    [[TMP441:%.*]] = load i8, ptr [[CR]], align 1
39490 // SIMD-ONLY0-NEXT:    [[TOBOOL711:%.*]] = icmp ne i8 [[TMP441]], 0
39491 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL711]], label [[IF_THEN712:%.*]], label [[IF_ELSE713:%.*]]
39492 // SIMD-ONLY0:       if.then712:
39493 // SIMD-ONLY0-NEXT:    [[TMP442:%.*]] = load i8, ptr [[CD]], align 1
39494 // SIMD-ONLY0-NEXT:    store i8 [[TMP442]], ptr [[CX]], align 1
39495 // SIMD-ONLY0-NEXT:    br label [[IF_END714:%.*]]
39496 // SIMD-ONLY0:       if.else713:
39497 // SIMD-ONLY0-NEXT:    [[TMP443:%.*]] = load i8, ptr [[CX]], align 1
39498 // SIMD-ONLY0-NEXT:    store i8 [[TMP443]], ptr [[CV]], align 1
39499 // SIMD-ONLY0-NEXT:    br label [[IF_END714]]
39500 // SIMD-ONLY0:       if.end714:
39501 // SIMD-ONLY0-NEXT:    [[TMP444:%.*]] = load i8, ptr [[UCX]], align 1
39502 // SIMD-ONLY0-NEXT:    store i8 [[TMP444]], ptr [[UCV]], align 1
39503 // SIMD-ONLY0-NEXT:    [[TMP445:%.*]] = load i8, ptr [[UCE]], align 1
39504 // SIMD-ONLY0-NEXT:    [[CONV715:%.*]] = zext i8 [[TMP445]] to i32
39505 // SIMD-ONLY0-NEXT:    [[TMP446:%.*]] = load i8, ptr [[UCX]], align 1
39506 // SIMD-ONLY0-NEXT:    [[CONV716:%.*]] = zext i8 [[TMP446]] to i32
39507 // SIMD-ONLY0-NEXT:    [[CMP717:%.*]] = icmp sgt i32 [[CONV715]], [[CONV716]]
39508 // SIMD-ONLY0-NEXT:    br i1 [[CMP717]], label [[IF_THEN719:%.*]], label [[IF_END720:%.*]]
39509 // SIMD-ONLY0:       if.then719:
39510 // SIMD-ONLY0-NEXT:    [[TMP447:%.*]] = load i8, ptr [[UCE]], align 1
39511 // SIMD-ONLY0-NEXT:    store i8 [[TMP447]], ptr [[UCX]], align 1
39512 // SIMD-ONLY0-NEXT:    br label [[IF_END720]]
39513 // SIMD-ONLY0:       if.end720:
39514 // SIMD-ONLY0-NEXT:    [[TMP448:%.*]] = load i8, ptr [[UCX]], align 1
39515 // SIMD-ONLY0-NEXT:    store i8 [[TMP448]], ptr [[UCV]], align 1
39516 // SIMD-ONLY0-NEXT:    [[TMP449:%.*]] = load i8, ptr [[UCX]], align 1
39517 // SIMD-ONLY0-NEXT:    [[CONV721:%.*]] = zext i8 [[TMP449]] to i32
39518 // SIMD-ONLY0-NEXT:    [[TMP450:%.*]] = load i8, ptr [[UCE]], align 1
39519 // SIMD-ONLY0-NEXT:    [[CONV722:%.*]] = zext i8 [[TMP450]] to i32
39520 // SIMD-ONLY0-NEXT:    [[CMP723:%.*]] = icmp sgt i32 [[CONV721]], [[CONV722]]
39521 // SIMD-ONLY0-NEXT:    br i1 [[CMP723]], label [[IF_THEN725:%.*]], label [[IF_END726:%.*]]
39522 // SIMD-ONLY0:       if.then725:
39523 // SIMD-ONLY0-NEXT:    [[TMP451:%.*]] = load i8, ptr [[UCE]], align 1
39524 // SIMD-ONLY0-NEXT:    store i8 [[TMP451]], ptr [[UCX]], align 1
39525 // SIMD-ONLY0-NEXT:    br label [[IF_END726]]
39526 // SIMD-ONLY0:       if.end726:
39527 // SIMD-ONLY0-NEXT:    [[TMP452:%.*]] = load i8, ptr [[UCX]], align 1
39528 // SIMD-ONLY0-NEXT:    store i8 [[TMP452]], ptr [[UCV]], align 1
39529 // SIMD-ONLY0-NEXT:    [[TMP453:%.*]] = load i8, ptr [[UCE]], align 1
39530 // SIMD-ONLY0-NEXT:    [[CONV727:%.*]] = zext i8 [[TMP453]] to i32
39531 // SIMD-ONLY0-NEXT:    [[TMP454:%.*]] = load i8, ptr [[UCX]], align 1
39532 // SIMD-ONLY0-NEXT:    [[CONV728:%.*]] = zext i8 [[TMP454]] to i32
39533 // SIMD-ONLY0-NEXT:    [[CMP729:%.*]] = icmp slt i32 [[CONV727]], [[CONV728]]
39534 // SIMD-ONLY0-NEXT:    br i1 [[CMP729]], label [[IF_THEN731:%.*]], label [[IF_END732:%.*]]
39535 // SIMD-ONLY0:       if.then731:
39536 // SIMD-ONLY0-NEXT:    [[TMP455:%.*]] = load i8, ptr [[UCE]], align 1
39537 // SIMD-ONLY0-NEXT:    store i8 [[TMP455]], ptr [[UCX]], align 1
39538 // SIMD-ONLY0-NEXT:    br label [[IF_END732]]
39539 // SIMD-ONLY0:       if.end732:
39540 // SIMD-ONLY0-NEXT:    [[TMP456:%.*]] = load i8, ptr [[UCX]], align 1
39541 // SIMD-ONLY0-NEXT:    store i8 [[TMP456]], ptr [[UCV]], align 1
39542 // SIMD-ONLY0-NEXT:    [[TMP457:%.*]] = load i8, ptr [[UCX]], align 1
39543 // SIMD-ONLY0-NEXT:    [[CONV733:%.*]] = zext i8 [[TMP457]] to i32
39544 // SIMD-ONLY0-NEXT:    [[TMP458:%.*]] = load i8, ptr [[UCE]], align 1
39545 // SIMD-ONLY0-NEXT:    [[CONV734:%.*]] = zext i8 [[TMP458]] to i32
39546 // SIMD-ONLY0-NEXT:    [[CMP735:%.*]] = icmp slt i32 [[CONV733]], [[CONV734]]
39547 // SIMD-ONLY0-NEXT:    br i1 [[CMP735]], label [[IF_THEN737:%.*]], label [[IF_END738:%.*]]
39548 // SIMD-ONLY0:       if.then737:
39549 // SIMD-ONLY0-NEXT:    [[TMP459:%.*]] = load i8, ptr [[UCE]], align 1
39550 // SIMD-ONLY0-NEXT:    store i8 [[TMP459]], ptr [[UCX]], align 1
39551 // SIMD-ONLY0-NEXT:    br label [[IF_END738]]
39552 // SIMD-ONLY0:       if.end738:
39553 // SIMD-ONLY0-NEXT:    [[TMP460:%.*]] = load i8, ptr [[UCX]], align 1
39554 // SIMD-ONLY0-NEXT:    store i8 [[TMP460]], ptr [[UCV]], align 1
39555 // SIMD-ONLY0-NEXT:    [[TMP461:%.*]] = load i8, ptr [[UCX]], align 1
39556 // SIMD-ONLY0-NEXT:    [[CONV739:%.*]] = zext i8 [[TMP461]] to i32
39557 // SIMD-ONLY0-NEXT:    [[TMP462:%.*]] = load i8, ptr [[UCE]], align 1
39558 // SIMD-ONLY0-NEXT:    [[CONV740:%.*]] = zext i8 [[TMP462]] to i32
39559 // SIMD-ONLY0-NEXT:    [[CMP741:%.*]] = icmp eq i32 [[CONV739]], [[CONV740]]
39560 // SIMD-ONLY0-NEXT:    br i1 [[CMP741]], label [[IF_THEN743:%.*]], label [[IF_END744:%.*]]
39561 // SIMD-ONLY0:       if.then743:
39562 // SIMD-ONLY0-NEXT:    [[TMP463:%.*]] = load i8, ptr [[UCD]], align 1
39563 // SIMD-ONLY0-NEXT:    store i8 [[TMP463]], ptr [[UCX]], align 1
39564 // SIMD-ONLY0-NEXT:    br label [[IF_END744]]
39565 // SIMD-ONLY0:       if.end744:
39566 // SIMD-ONLY0-NEXT:    [[TMP464:%.*]] = load i8, ptr [[UCX]], align 1
39567 // SIMD-ONLY0-NEXT:    store i8 [[TMP464]], ptr [[UCV]], align 1
39568 // SIMD-ONLY0-NEXT:    [[TMP465:%.*]] = load i8, ptr [[UCE]], align 1
39569 // SIMD-ONLY0-NEXT:    [[CONV745:%.*]] = zext i8 [[TMP465]] to i32
39570 // SIMD-ONLY0-NEXT:    [[TMP466:%.*]] = load i8, ptr [[UCX]], align 1
39571 // SIMD-ONLY0-NEXT:    [[CONV746:%.*]] = zext i8 [[TMP466]] to i32
39572 // SIMD-ONLY0-NEXT:    [[CMP747:%.*]] = icmp eq i32 [[CONV745]], [[CONV746]]
39573 // SIMD-ONLY0-NEXT:    br i1 [[CMP747]], label [[IF_THEN749:%.*]], label [[IF_END750:%.*]]
39574 // SIMD-ONLY0:       if.then749:
39575 // SIMD-ONLY0-NEXT:    [[TMP467:%.*]] = load i8, ptr [[UCD]], align 1
39576 // SIMD-ONLY0-NEXT:    store i8 [[TMP467]], ptr [[UCX]], align 1
39577 // SIMD-ONLY0-NEXT:    br label [[IF_END750]]
39578 // SIMD-ONLY0:       if.end750:
39579 // SIMD-ONLY0-NEXT:    [[TMP468:%.*]] = load i8, ptr [[UCE]], align 1
39580 // SIMD-ONLY0-NEXT:    [[CONV751:%.*]] = zext i8 [[TMP468]] to i32
39581 // SIMD-ONLY0-NEXT:    [[TMP469:%.*]] = load i8, ptr [[UCX]], align 1
39582 // SIMD-ONLY0-NEXT:    [[CONV752:%.*]] = zext i8 [[TMP469]] to i32
39583 // SIMD-ONLY0-NEXT:    [[CMP753:%.*]] = icmp sgt i32 [[CONV751]], [[CONV752]]
39584 // SIMD-ONLY0-NEXT:    br i1 [[CMP753]], label [[IF_THEN755:%.*]], label [[IF_END756:%.*]]
39585 // SIMD-ONLY0:       if.then755:
39586 // SIMD-ONLY0-NEXT:    [[TMP470:%.*]] = load i8, ptr [[UCE]], align 1
39587 // SIMD-ONLY0-NEXT:    store i8 [[TMP470]], ptr [[UCX]], align 1
39588 // SIMD-ONLY0-NEXT:    br label [[IF_END756]]
39589 // SIMD-ONLY0:       if.end756:
39590 // SIMD-ONLY0-NEXT:    [[TMP471:%.*]] = load i8, ptr [[UCX]], align 1
39591 // SIMD-ONLY0-NEXT:    store i8 [[TMP471]], ptr [[UCV]], align 1
39592 // SIMD-ONLY0-NEXT:    [[TMP472:%.*]] = load i8, ptr [[UCX]], align 1
39593 // SIMD-ONLY0-NEXT:    [[CONV757:%.*]] = zext i8 [[TMP472]] to i32
39594 // SIMD-ONLY0-NEXT:    [[TMP473:%.*]] = load i8, ptr [[UCE]], align 1
39595 // SIMD-ONLY0-NEXT:    [[CONV758:%.*]] = zext i8 [[TMP473]] to i32
39596 // SIMD-ONLY0-NEXT:    [[CMP759:%.*]] = icmp sgt i32 [[CONV757]], [[CONV758]]
39597 // SIMD-ONLY0-NEXT:    br i1 [[CMP759]], label [[IF_THEN761:%.*]], label [[IF_END762:%.*]]
39598 // SIMD-ONLY0:       if.then761:
39599 // SIMD-ONLY0-NEXT:    [[TMP474:%.*]] = load i8, ptr [[UCE]], align 1
39600 // SIMD-ONLY0-NEXT:    store i8 [[TMP474]], ptr [[UCX]], align 1
39601 // SIMD-ONLY0-NEXT:    br label [[IF_END762]]
39602 // SIMD-ONLY0:       if.end762:
39603 // SIMD-ONLY0-NEXT:    [[TMP475:%.*]] = load i8, ptr [[UCX]], align 1
39604 // SIMD-ONLY0-NEXT:    store i8 [[TMP475]], ptr [[UCV]], align 1
39605 // SIMD-ONLY0-NEXT:    [[TMP476:%.*]] = load i8, ptr [[UCE]], align 1
39606 // SIMD-ONLY0-NEXT:    [[CONV763:%.*]] = zext i8 [[TMP476]] to i32
39607 // SIMD-ONLY0-NEXT:    [[TMP477:%.*]] = load i8, ptr [[UCX]], align 1
39608 // SIMD-ONLY0-NEXT:    [[CONV764:%.*]] = zext i8 [[TMP477]] to i32
39609 // SIMD-ONLY0-NEXT:    [[CMP765:%.*]] = icmp slt i32 [[CONV763]], [[CONV764]]
39610 // SIMD-ONLY0-NEXT:    br i1 [[CMP765]], label [[IF_THEN767:%.*]], label [[IF_END768:%.*]]
39611 // SIMD-ONLY0:       if.then767:
39612 // SIMD-ONLY0-NEXT:    [[TMP478:%.*]] = load i8, ptr [[UCE]], align 1
39613 // SIMD-ONLY0-NEXT:    store i8 [[TMP478]], ptr [[UCX]], align 1
39614 // SIMD-ONLY0-NEXT:    br label [[IF_END768]]
39615 // SIMD-ONLY0:       if.end768:
39616 // SIMD-ONLY0-NEXT:    [[TMP479:%.*]] = load i8, ptr [[UCX]], align 1
39617 // SIMD-ONLY0-NEXT:    store i8 [[TMP479]], ptr [[UCV]], align 1
39618 // SIMD-ONLY0-NEXT:    [[TMP480:%.*]] = load i8, ptr [[UCX]], align 1
39619 // SIMD-ONLY0-NEXT:    [[CONV769:%.*]] = zext i8 [[TMP480]] to i32
39620 // SIMD-ONLY0-NEXT:    [[TMP481:%.*]] = load i8, ptr [[UCE]], align 1
39621 // SIMD-ONLY0-NEXT:    [[CONV770:%.*]] = zext i8 [[TMP481]] to i32
39622 // SIMD-ONLY0-NEXT:    [[CMP771:%.*]] = icmp slt i32 [[CONV769]], [[CONV770]]
39623 // SIMD-ONLY0-NEXT:    br i1 [[CMP771]], label [[IF_THEN773:%.*]], label [[IF_END774:%.*]]
39624 // SIMD-ONLY0:       if.then773:
39625 // SIMD-ONLY0-NEXT:    [[TMP482:%.*]] = load i8, ptr [[UCE]], align 1
39626 // SIMD-ONLY0-NEXT:    store i8 [[TMP482]], ptr [[UCX]], align 1
39627 // SIMD-ONLY0-NEXT:    br label [[IF_END774]]
39628 // SIMD-ONLY0:       if.end774:
39629 // SIMD-ONLY0-NEXT:    [[TMP483:%.*]] = load i8, ptr [[UCX]], align 1
39630 // SIMD-ONLY0-NEXT:    store i8 [[TMP483]], ptr [[UCV]], align 1
39631 // SIMD-ONLY0-NEXT:    [[TMP484:%.*]] = load i8, ptr [[UCX]], align 1
39632 // SIMD-ONLY0-NEXT:    [[CONV775:%.*]] = zext i8 [[TMP484]] to i32
39633 // SIMD-ONLY0-NEXT:    [[TMP485:%.*]] = load i8, ptr [[UCE]], align 1
39634 // SIMD-ONLY0-NEXT:    [[CONV776:%.*]] = zext i8 [[TMP485]] to i32
39635 // SIMD-ONLY0-NEXT:    [[CMP777:%.*]] = icmp eq i32 [[CONV775]], [[CONV776]]
39636 // SIMD-ONLY0-NEXT:    br i1 [[CMP777]], label [[IF_THEN779:%.*]], label [[IF_END780:%.*]]
39637 // SIMD-ONLY0:       if.then779:
39638 // SIMD-ONLY0-NEXT:    [[TMP486:%.*]] = load i8, ptr [[UCD]], align 1
39639 // SIMD-ONLY0-NEXT:    store i8 [[TMP486]], ptr [[UCX]], align 1
39640 // SIMD-ONLY0-NEXT:    br label [[IF_END780]]
39641 // SIMD-ONLY0:       if.end780:
39642 // SIMD-ONLY0-NEXT:    [[TMP487:%.*]] = load i8, ptr [[UCX]], align 1
39643 // SIMD-ONLY0-NEXT:    store i8 [[TMP487]], ptr [[UCV]], align 1
39644 // SIMD-ONLY0-NEXT:    [[TMP488:%.*]] = load i8, ptr [[UCE]], align 1
39645 // SIMD-ONLY0-NEXT:    [[CONV781:%.*]] = zext i8 [[TMP488]] to i32
39646 // SIMD-ONLY0-NEXT:    [[TMP489:%.*]] = load i8, ptr [[UCX]], align 1
39647 // SIMD-ONLY0-NEXT:    [[CONV782:%.*]] = zext i8 [[TMP489]] to i32
39648 // SIMD-ONLY0-NEXT:    [[CMP783:%.*]] = icmp eq i32 [[CONV781]], [[CONV782]]
39649 // SIMD-ONLY0-NEXT:    br i1 [[CMP783]], label [[IF_THEN785:%.*]], label [[IF_END786:%.*]]
39650 // SIMD-ONLY0:       if.then785:
39651 // SIMD-ONLY0-NEXT:    [[TMP490:%.*]] = load i8, ptr [[UCD]], align 1
39652 // SIMD-ONLY0-NEXT:    store i8 [[TMP490]], ptr [[UCX]], align 1
39653 // SIMD-ONLY0-NEXT:    br label [[IF_END786]]
39654 // SIMD-ONLY0:       if.end786:
39655 // SIMD-ONLY0-NEXT:    [[TMP491:%.*]] = load i8, ptr [[UCX]], align 1
39656 // SIMD-ONLY0-NEXT:    store i8 [[TMP491]], ptr [[UCV]], align 1
39657 // SIMD-ONLY0-NEXT:    [[TMP492:%.*]] = load i8, ptr [[UCX]], align 1
39658 // SIMD-ONLY0-NEXT:    [[CONV787:%.*]] = zext i8 [[TMP492]] to i32
39659 // SIMD-ONLY0-NEXT:    [[TMP493:%.*]] = load i8, ptr [[UCE]], align 1
39660 // SIMD-ONLY0-NEXT:    [[CONV788:%.*]] = zext i8 [[TMP493]] to i32
39661 // SIMD-ONLY0-NEXT:    [[CMP789:%.*]] = icmp eq i32 [[CONV787]], [[CONV788]]
39662 // SIMD-ONLY0-NEXT:    br i1 [[CMP789]], label [[IF_THEN791:%.*]], label [[IF_ELSE792:%.*]]
39663 // SIMD-ONLY0:       if.then791:
39664 // SIMD-ONLY0-NEXT:    [[TMP494:%.*]] = load i8, ptr [[UCD]], align 1
39665 // SIMD-ONLY0-NEXT:    store i8 [[TMP494]], ptr [[UCX]], align 1
39666 // SIMD-ONLY0-NEXT:    br label [[IF_END793:%.*]]
39667 // SIMD-ONLY0:       if.else792:
39668 // SIMD-ONLY0-NEXT:    [[TMP495:%.*]] = load i8, ptr [[UCX]], align 1
39669 // SIMD-ONLY0-NEXT:    store i8 [[TMP495]], ptr [[UCV]], align 1
39670 // SIMD-ONLY0-NEXT:    br label [[IF_END793]]
39671 // SIMD-ONLY0:       if.end793:
39672 // SIMD-ONLY0-NEXT:    [[TMP496:%.*]] = load i8, ptr [[UCE]], align 1
39673 // SIMD-ONLY0-NEXT:    [[CONV794:%.*]] = zext i8 [[TMP496]] to i32
39674 // SIMD-ONLY0-NEXT:    [[TMP497:%.*]] = load i8, ptr [[UCX]], align 1
39675 // SIMD-ONLY0-NEXT:    [[CONV795:%.*]] = zext i8 [[TMP497]] to i32
39676 // SIMD-ONLY0-NEXT:    [[CMP796:%.*]] = icmp eq i32 [[CONV794]], [[CONV795]]
39677 // SIMD-ONLY0-NEXT:    br i1 [[CMP796]], label [[IF_THEN798:%.*]], label [[IF_ELSE799:%.*]]
39678 // SIMD-ONLY0:       if.then798:
39679 // SIMD-ONLY0-NEXT:    [[TMP498:%.*]] = load i8, ptr [[UCD]], align 1
39680 // SIMD-ONLY0-NEXT:    store i8 [[TMP498]], ptr [[UCX]], align 1
39681 // SIMD-ONLY0-NEXT:    br label [[IF_END800:%.*]]
39682 // SIMD-ONLY0:       if.else799:
39683 // SIMD-ONLY0-NEXT:    [[TMP499:%.*]] = load i8, ptr [[UCX]], align 1
39684 // SIMD-ONLY0-NEXT:    store i8 [[TMP499]], ptr [[UCV]], align 1
39685 // SIMD-ONLY0-NEXT:    br label [[IF_END800]]
39686 // SIMD-ONLY0:       if.end800:
39687 // SIMD-ONLY0-NEXT:    [[TMP500:%.*]] = load i8, ptr [[UCX]], align 1
39688 // SIMD-ONLY0-NEXT:    [[CONV801:%.*]] = zext i8 [[TMP500]] to i32
39689 // SIMD-ONLY0-NEXT:    [[TMP501:%.*]] = load i8, ptr [[UCE]], align 1
39690 // SIMD-ONLY0-NEXT:    [[CONV802:%.*]] = zext i8 [[TMP501]] to i32
39691 // SIMD-ONLY0-NEXT:    [[CMP803:%.*]] = icmp eq i32 [[CONV801]], [[CONV802]]
39692 // SIMD-ONLY0-NEXT:    [[CONV804:%.*]] = zext i1 [[CMP803]] to i32
39693 // SIMD-ONLY0-NEXT:    [[CONV805:%.*]] = trunc i32 [[CONV804]] to i8
39694 // SIMD-ONLY0-NEXT:    store i8 [[CONV805]], ptr [[UCR]], align 1
39695 // SIMD-ONLY0-NEXT:    [[TMP502:%.*]] = load i8, ptr [[UCR]], align 1
39696 // SIMD-ONLY0-NEXT:    [[TOBOOL806:%.*]] = icmp ne i8 [[TMP502]], 0
39697 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL806]], label [[IF_THEN807:%.*]], label [[IF_END808:%.*]]
39698 // SIMD-ONLY0:       if.then807:
39699 // SIMD-ONLY0-NEXT:    [[TMP503:%.*]] = load i8, ptr [[UCD]], align 1
39700 // SIMD-ONLY0-NEXT:    store i8 [[TMP503]], ptr [[UCX]], align 1
39701 // SIMD-ONLY0-NEXT:    br label [[IF_END808]]
39702 // SIMD-ONLY0:       if.end808:
39703 // SIMD-ONLY0-NEXT:    [[TMP504:%.*]] = load i8, ptr [[UCE]], align 1
39704 // SIMD-ONLY0-NEXT:    [[CONV809:%.*]] = zext i8 [[TMP504]] to i32
39705 // SIMD-ONLY0-NEXT:    [[TMP505:%.*]] = load i8, ptr [[UCX]], align 1
39706 // SIMD-ONLY0-NEXT:    [[CONV810:%.*]] = zext i8 [[TMP505]] to i32
39707 // SIMD-ONLY0-NEXT:    [[CMP811:%.*]] = icmp eq i32 [[CONV809]], [[CONV810]]
39708 // SIMD-ONLY0-NEXT:    [[CONV812:%.*]] = zext i1 [[CMP811]] to i32
39709 // SIMD-ONLY0-NEXT:    [[CONV813:%.*]] = trunc i32 [[CONV812]] to i8
39710 // SIMD-ONLY0-NEXT:    store i8 [[CONV813]], ptr [[UCR]], align 1
39711 // SIMD-ONLY0-NEXT:    [[TMP506:%.*]] = load i8, ptr [[UCR]], align 1
39712 // SIMD-ONLY0-NEXT:    [[TOBOOL814:%.*]] = icmp ne i8 [[TMP506]], 0
39713 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL814]], label [[IF_THEN815:%.*]], label [[IF_END816:%.*]]
39714 // SIMD-ONLY0:       if.then815:
39715 // SIMD-ONLY0-NEXT:    [[TMP507:%.*]] = load i8, ptr [[UCD]], align 1
39716 // SIMD-ONLY0-NEXT:    store i8 [[TMP507]], ptr [[UCX]], align 1
39717 // SIMD-ONLY0-NEXT:    br label [[IF_END816]]
39718 // SIMD-ONLY0:       if.end816:
39719 // SIMD-ONLY0-NEXT:    [[TMP508:%.*]] = load i8, ptr [[UCX]], align 1
39720 // SIMD-ONLY0-NEXT:    [[CONV817:%.*]] = zext i8 [[TMP508]] to i32
39721 // SIMD-ONLY0-NEXT:    [[TMP509:%.*]] = load i8, ptr [[UCE]], align 1
39722 // SIMD-ONLY0-NEXT:    [[CONV818:%.*]] = zext i8 [[TMP509]] to i32
39723 // SIMD-ONLY0-NEXT:    [[CMP819:%.*]] = icmp eq i32 [[CONV817]], [[CONV818]]
39724 // SIMD-ONLY0-NEXT:    [[CONV820:%.*]] = zext i1 [[CMP819]] to i32
39725 // SIMD-ONLY0-NEXT:    [[CONV821:%.*]] = trunc i32 [[CONV820]] to i8
39726 // SIMD-ONLY0-NEXT:    store i8 [[CONV821]], ptr [[UCR]], align 1
39727 // SIMD-ONLY0-NEXT:    [[TMP510:%.*]] = load i8, ptr [[UCR]], align 1
39728 // SIMD-ONLY0-NEXT:    [[TOBOOL822:%.*]] = icmp ne i8 [[TMP510]], 0
39729 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL822]], label [[IF_THEN823:%.*]], label [[IF_ELSE824:%.*]]
39730 // SIMD-ONLY0:       if.then823:
39731 // SIMD-ONLY0-NEXT:    [[TMP511:%.*]] = load i8, ptr [[UCD]], align 1
39732 // SIMD-ONLY0-NEXT:    store i8 [[TMP511]], ptr [[UCX]], align 1
39733 // SIMD-ONLY0-NEXT:    br label [[IF_END825:%.*]]
39734 // SIMD-ONLY0:       if.else824:
39735 // SIMD-ONLY0-NEXT:    [[TMP512:%.*]] = load i8, ptr [[UCX]], align 1
39736 // SIMD-ONLY0-NEXT:    store i8 [[TMP512]], ptr [[UCV]], align 1
39737 // SIMD-ONLY0-NEXT:    br label [[IF_END825]]
39738 // SIMD-ONLY0:       if.end825:
39739 // SIMD-ONLY0-NEXT:    [[TMP513:%.*]] = load i8, ptr [[UCE]], align 1
39740 // SIMD-ONLY0-NEXT:    [[CONV826:%.*]] = zext i8 [[TMP513]] to i32
39741 // SIMD-ONLY0-NEXT:    [[TMP514:%.*]] = load i8, ptr [[UCX]], align 1
39742 // SIMD-ONLY0-NEXT:    [[CONV827:%.*]] = zext i8 [[TMP514]] to i32
39743 // SIMD-ONLY0-NEXT:    [[CMP828:%.*]] = icmp eq i32 [[CONV826]], [[CONV827]]
39744 // SIMD-ONLY0-NEXT:    [[CONV829:%.*]] = zext i1 [[CMP828]] to i32
39745 // SIMD-ONLY0-NEXT:    [[CONV830:%.*]] = trunc i32 [[CONV829]] to i8
39746 // SIMD-ONLY0-NEXT:    store i8 [[CONV830]], ptr [[UCR]], align 1
39747 // SIMD-ONLY0-NEXT:    [[TMP515:%.*]] = load i8, ptr [[UCR]], align 1
39748 // SIMD-ONLY0-NEXT:    [[TOBOOL831:%.*]] = icmp ne i8 [[TMP515]], 0
39749 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL831]], label [[IF_THEN832:%.*]], label [[IF_ELSE833:%.*]]
39750 // SIMD-ONLY0:       if.then832:
39751 // SIMD-ONLY0-NEXT:    [[TMP516:%.*]] = load i8, ptr [[UCD]], align 1
39752 // SIMD-ONLY0-NEXT:    store i8 [[TMP516]], ptr [[UCX]], align 1
39753 // SIMD-ONLY0-NEXT:    br label [[IF_END834:%.*]]
39754 // SIMD-ONLY0:       if.else833:
39755 // SIMD-ONLY0-NEXT:    [[TMP517:%.*]] = load i8, ptr [[UCX]], align 1
39756 // SIMD-ONLY0-NEXT:    store i8 [[TMP517]], ptr [[UCV]], align 1
39757 // SIMD-ONLY0-NEXT:    br label [[IF_END834]]
39758 // SIMD-ONLY0:       if.end834:
39759 // SIMD-ONLY0-NEXT:    [[TMP518:%.*]] = load i8, ptr [[UCX]], align 1
39760 // SIMD-ONLY0-NEXT:    store i8 [[TMP518]], ptr [[UCV]], align 1
39761 // SIMD-ONLY0-NEXT:    [[TMP519:%.*]] = load i8, ptr [[UCE]], align 1
39762 // SIMD-ONLY0-NEXT:    [[CONV835:%.*]] = zext i8 [[TMP519]] to i32
39763 // SIMD-ONLY0-NEXT:    [[TMP520:%.*]] = load i8, ptr [[UCX]], align 1
39764 // SIMD-ONLY0-NEXT:    [[CONV836:%.*]] = zext i8 [[TMP520]] to i32
39765 // SIMD-ONLY0-NEXT:    [[CMP837:%.*]] = icmp sgt i32 [[CONV835]], [[CONV836]]
39766 // SIMD-ONLY0-NEXT:    br i1 [[CMP837]], label [[IF_THEN839:%.*]], label [[IF_END840:%.*]]
39767 // SIMD-ONLY0:       if.then839:
39768 // SIMD-ONLY0-NEXT:    [[TMP521:%.*]] = load i8, ptr [[UCE]], align 1
39769 // SIMD-ONLY0-NEXT:    store i8 [[TMP521]], ptr [[UCX]], align 1
39770 // SIMD-ONLY0-NEXT:    br label [[IF_END840]]
39771 // SIMD-ONLY0:       if.end840:
39772 // SIMD-ONLY0-NEXT:    [[TMP522:%.*]] = load i8, ptr [[UCX]], align 1
39773 // SIMD-ONLY0-NEXT:    store i8 [[TMP522]], ptr [[UCV]], align 1
39774 // SIMD-ONLY0-NEXT:    [[TMP523:%.*]] = load i8, ptr [[UCX]], align 1
39775 // SIMD-ONLY0-NEXT:    [[CONV841:%.*]] = zext i8 [[TMP523]] to i32
39776 // SIMD-ONLY0-NEXT:    [[TMP524:%.*]] = load i8, ptr [[UCE]], align 1
39777 // SIMD-ONLY0-NEXT:    [[CONV842:%.*]] = zext i8 [[TMP524]] to i32
39778 // SIMD-ONLY0-NEXT:    [[CMP843:%.*]] = icmp sgt i32 [[CONV841]], [[CONV842]]
39779 // SIMD-ONLY0-NEXT:    br i1 [[CMP843]], label [[IF_THEN845:%.*]], label [[IF_END846:%.*]]
39780 // SIMD-ONLY0:       if.then845:
39781 // SIMD-ONLY0-NEXT:    [[TMP525:%.*]] = load i8, ptr [[UCE]], align 1
39782 // SIMD-ONLY0-NEXT:    store i8 [[TMP525]], ptr [[UCX]], align 1
39783 // SIMD-ONLY0-NEXT:    br label [[IF_END846]]
39784 // SIMD-ONLY0:       if.end846:
39785 // SIMD-ONLY0-NEXT:    [[TMP526:%.*]] = load i8, ptr [[UCX]], align 1
39786 // SIMD-ONLY0-NEXT:    store i8 [[TMP526]], ptr [[UCV]], align 1
39787 // SIMD-ONLY0-NEXT:    [[TMP527:%.*]] = load i8, ptr [[UCE]], align 1
39788 // SIMD-ONLY0-NEXT:    [[CONV847:%.*]] = zext i8 [[TMP527]] to i32
39789 // SIMD-ONLY0-NEXT:    [[TMP528:%.*]] = load i8, ptr [[UCX]], align 1
39790 // SIMD-ONLY0-NEXT:    [[CONV848:%.*]] = zext i8 [[TMP528]] to i32
39791 // SIMD-ONLY0-NEXT:    [[CMP849:%.*]] = icmp slt i32 [[CONV847]], [[CONV848]]
39792 // SIMD-ONLY0-NEXT:    br i1 [[CMP849]], label [[IF_THEN851:%.*]], label [[IF_END852:%.*]]
39793 // SIMD-ONLY0:       if.then851:
39794 // SIMD-ONLY0-NEXT:    [[TMP529:%.*]] = load i8, ptr [[UCE]], align 1
39795 // SIMD-ONLY0-NEXT:    store i8 [[TMP529]], ptr [[UCX]], align 1
39796 // SIMD-ONLY0-NEXT:    br label [[IF_END852]]
39797 // SIMD-ONLY0:       if.end852:
39798 // SIMD-ONLY0-NEXT:    [[TMP530:%.*]] = load i8, ptr [[UCX]], align 1
39799 // SIMD-ONLY0-NEXT:    store i8 [[TMP530]], ptr [[UCV]], align 1
39800 // SIMD-ONLY0-NEXT:    [[TMP531:%.*]] = load i8, ptr [[UCX]], align 1
39801 // SIMD-ONLY0-NEXT:    [[CONV853:%.*]] = zext i8 [[TMP531]] to i32
39802 // SIMD-ONLY0-NEXT:    [[TMP532:%.*]] = load i8, ptr [[UCE]], align 1
39803 // SIMD-ONLY0-NEXT:    [[CONV854:%.*]] = zext i8 [[TMP532]] to i32
39804 // SIMD-ONLY0-NEXT:    [[CMP855:%.*]] = icmp slt i32 [[CONV853]], [[CONV854]]
39805 // SIMD-ONLY0-NEXT:    br i1 [[CMP855]], label [[IF_THEN857:%.*]], label [[IF_END858:%.*]]
39806 // SIMD-ONLY0:       if.then857:
39807 // SIMD-ONLY0-NEXT:    [[TMP533:%.*]] = load i8, ptr [[UCE]], align 1
39808 // SIMD-ONLY0-NEXT:    store i8 [[TMP533]], ptr [[UCX]], align 1
39809 // SIMD-ONLY0-NEXT:    br label [[IF_END858]]
39810 // SIMD-ONLY0:       if.end858:
39811 // SIMD-ONLY0-NEXT:    [[TMP534:%.*]] = load i8, ptr [[UCX]], align 1
39812 // SIMD-ONLY0-NEXT:    store i8 [[TMP534]], ptr [[UCV]], align 1
39813 // SIMD-ONLY0-NEXT:    [[TMP535:%.*]] = load i8, ptr [[UCX]], align 1
39814 // SIMD-ONLY0-NEXT:    [[CONV859:%.*]] = zext i8 [[TMP535]] to i32
39815 // SIMD-ONLY0-NEXT:    [[TMP536:%.*]] = load i8, ptr [[UCE]], align 1
39816 // SIMD-ONLY0-NEXT:    [[CONV860:%.*]] = zext i8 [[TMP536]] to i32
39817 // SIMD-ONLY0-NEXT:    [[CMP861:%.*]] = icmp eq i32 [[CONV859]], [[CONV860]]
39818 // SIMD-ONLY0-NEXT:    br i1 [[CMP861]], label [[IF_THEN863:%.*]], label [[IF_END864:%.*]]
39819 // SIMD-ONLY0:       if.then863:
39820 // SIMD-ONLY0-NEXT:    [[TMP537:%.*]] = load i8, ptr [[UCD]], align 1
39821 // SIMD-ONLY0-NEXT:    store i8 [[TMP537]], ptr [[UCX]], align 1
39822 // SIMD-ONLY0-NEXT:    br label [[IF_END864]]
39823 // SIMD-ONLY0:       if.end864:
39824 // SIMD-ONLY0-NEXT:    [[TMP538:%.*]] = load i8, ptr [[UCX]], align 1
39825 // SIMD-ONLY0-NEXT:    store i8 [[TMP538]], ptr [[UCV]], align 1
39826 // SIMD-ONLY0-NEXT:    [[TMP539:%.*]] = load i8, ptr [[UCE]], align 1
39827 // SIMD-ONLY0-NEXT:    [[CONV865:%.*]] = zext i8 [[TMP539]] to i32
39828 // SIMD-ONLY0-NEXT:    [[TMP540:%.*]] = load i8, ptr [[UCX]], align 1
39829 // SIMD-ONLY0-NEXT:    [[CONV866:%.*]] = zext i8 [[TMP540]] to i32
39830 // SIMD-ONLY0-NEXT:    [[CMP867:%.*]] = icmp eq i32 [[CONV865]], [[CONV866]]
39831 // SIMD-ONLY0-NEXT:    br i1 [[CMP867]], label [[IF_THEN869:%.*]], label [[IF_END870:%.*]]
39832 // SIMD-ONLY0:       if.then869:
39833 // SIMD-ONLY0-NEXT:    [[TMP541:%.*]] = load i8, ptr [[UCD]], align 1
39834 // SIMD-ONLY0-NEXT:    store i8 [[TMP541]], ptr [[UCX]], align 1
39835 // SIMD-ONLY0-NEXT:    br label [[IF_END870]]
39836 // SIMD-ONLY0:       if.end870:
39837 // SIMD-ONLY0-NEXT:    [[TMP542:%.*]] = load i8, ptr [[UCE]], align 1
39838 // SIMD-ONLY0-NEXT:    [[CONV871:%.*]] = zext i8 [[TMP542]] to i32
39839 // SIMD-ONLY0-NEXT:    [[TMP543:%.*]] = load i8, ptr [[UCX]], align 1
39840 // SIMD-ONLY0-NEXT:    [[CONV872:%.*]] = zext i8 [[TMP543]] to i32
39841 // SIMD-ONLY0-NEXT:    [[CMP873:%.*]] = icmp sgt i32 [[CONV871]], [[CONV872]]
39842 // SIMD-ONLY0-NEXT:    br i1 [[CMP873]], label [[IF_THEN875:%.*]], label [[IF_END876:%.*]]
39843 // SIMD-ONLY0:       if.then875:
39844 // SIMD-ONLY0-NEXT:    [[TMP544:%.*]] = load i8, ptr [[UCE]], align 1
39845 // SIMD-ONLY0-NEXT:    store i8 [[TMP544]], ptr [[UCX]], align 1
39846 // SIMD-ONLY0-NEXT:    br label [[IF_END876]]
39847 // SIMD-ONLY0:       if.end876:
39848 // SIMD-ONLY0-NEXT:    [[TMP545:%.*]] = load i8, ptr [[UCX]], align 1
39849 // SIMD-ONLY0-NEXT:    store i8 [[TMP545]], ptr [[UCV]], align 1
39850 // SIMD-ONLY0-NEXT:    [[TMP546:%.*]] = load i8, ptr [[UCX]], align 1
39851 // SIMD-ONLY0-NEXT:    [[CONV877:%.*]] = zext i8 [[TMP546]] to i32
39852 // SIMD-ONLY0-NEXT:    [[TMP547:%.*]] = load i8, ptr [[UCE]], align 1
39853 // SIMD-ONLY0-NEXT:    [[CONV878:%.*]] = zext i8 [[TMP547]] to i32
39854 // SIMD-ONLY0-NEXT:    [[CMP879:%.*]] = icmp sgt i32 [[CONV877]], [[CONV878]]
39855 // SIMD-ONLY0-NEXT:    br i1 [[CMP879]], label [[IF_THEN881:%.*]], label [[IF_END882:%.*]]
39856 // SIMD-ONLY0:       if.then881:
39857 // SIMD-ONLY0-NEXT:    [[TMP548:%.*]] = load i8, ptr [[UCE]], align 1
39858 // SIMD-ONLY0-NEXT:    store i8 [[TMP548]], ptr [[UCX]], align 1
39859 // SIMD-ONLY0-NEXT:    br label [[IF_END882]]
39860 // SIMD-ONLY0:       if.end882:
39861 // SIMD-ONLY0-NEXT:    [[TMP549:%.*]] = load i8, ptr [[UCX]], align 1
39862 // SIMD-ONLY0-NEXT:    store i8 [[TMP549]], ptr [[UCV]], align 1
39863 // SIMD-ONLY0-NEXT:    [[TMP550:%.*]] = load i8, ptr [[UCE]], align 1
39864 // SIMD-ONLY0-NEXT:    [[CONV883:%.*]] = zext i8 [[TMP550]] to i32
39865 // SIMD-ONLY0-NEXT:    [[TMP551:%.*]] = load i8, ptr [[UCX]], align 1
39866 // SIMD-ONLY0-NEXT:    [[CONV884:%.*]] = zext i8 [[TMP551]] to i32
39867 // SIMD-ONLY0-NEXT:    [[CMP885:%.*]] = icmp slt i32 [[CONV883]], [[CONV884]]
39868 // SIMD-ONLY0-NEXT:    br i1 [[CMP885]], label [[IF_THEN887:%.*]], label [[IF_END888:%.*]]
39869 // SIMD-ONLY0:       if.then887:
39870 // SIMD-ONLY0-NEXT:    [[TMP552:%.*]] = load i8, ptr [[UCE]], align 1
39871 // SIMD-ONLY0-NEXT:    store i8 [[TMP552]], ptr [[UCX]], align 1
39872 // SIMD-ONLY0-NEXT:    br label [[IF_END888]]
39873 // SIMD-ONLY0:       if.end888:
39874 // SIMD-ONLY0-NEXT:    [[TMP553:%.*]] = load i8, ptr [[UCX]], align 1
39875 // SIMD-ONLY0-NEXT:    store i8 [[TMP553]], ptr [[UCV]], align 1
39876 // SIMD-ONLY0-NEXT:    [[TMP554:%.*]] = load i8, ptr [[UCX]], align 1
39877 // SIMD-ONLY0-NEXT:    [[CONV889:%.*]] = zext i8 [[TMP554]] to i32
39878 // SIMD-ONLY0-NEXT:    [[TMP555:%.*]] = load i8, ptr [[UCE]], align 1
39879 // SIMD-ONLY0-NEXT:    [[CONV890:%.*]] = zext i8 [[TMP555]] to i32
39880 // SIMD-ONLY0-NEXT:    [[CMP891:%.*]] = icmp slt i32 [[CONV889]], [[CONV890]]
39881 // SIMD-ONLY0-NEXT:    br i1 [[CMP891]], label [[IF_THEN893:%.*]], label [[IF_END894:%.*]]
39882 // SIMD-ONLY0:       if.then893:
39883 // SIMD-ONLY0-NEXT:    [[TMP556:%.*]] = load i8, ptr [[UCE]], align 1
39884 // SIMD-ONLY0-NEXT:    store i8 [[TMP556]], ptr [[UCX]], align 1
39885 // SIMD-ONLY0-NEXT:    br label [[IF_END894]]
39886 // SIMD-ONLY0:       if.end894:
39887 // SIMD-ONLY0-NEXT:    [[TMP557:%.*]] = load i8, ptr [[UCX]], align 1
39888 // SIMD-ONLY0-NEXT:    store i8 [[TMP557]], ptr [[UCV]], align 1
39889 // SIMD-ONLY0-NEXT:    [[TMP558:%.*]] = load i8, ptr [[UCX]], align 1
39890 // SIMD-ONLY0-NEXT:    [[CONV895:%.*]] = zext i8 [[TMP558]] to i32
39891 // SIMD-ONLY0-NEXT:    [[TMP559:%.*]] = load i8, ptr [[UCE]], align 1
39892 // SIMD-ONLY0-NEXT:    [[CONV896:%.*]] = zext i8 [[TMP559]] to i32
39893 // SIMD-ONLY0-NEXT:    [[CMP897:%.*]] = icmp eq i32 [[CONV895]], [[CONV896]]
39894 // SIMD-ONLY0-NEXT:    br i1 [[CMP897]], label [[IF_THEN899:%.*]], label [[IF_END900:%.*]]
39895 // SIMD-ONLY0:       if.then899:
39896 // SIMD-ONLY0-NEXT:    [[TMP560:%.*]] = load i8, ptr [[UCD]], align 1
39897 // SIMD-ONLY0-NEXT:    store i8 [[TMP560]], ptr [[UCX]], align 1
39898 // SIMD-ONLY0-NEXT:    br label [[IF_END900]]
39899 // SIMD-ONLY0:       if.end900:
39900 // SIMD-ONLY0-NEXT:    [[TMP561:%.*]] = load i8, ptr [[UCX]], align 1
39901 // SIMD-ONLY0-NEXT:    store i8 [[TMP561]], ptr [[UCV]], align 1
39902 // SIMD-ONLY0-NEXT:    [[TMP562:%.*]] = load i8, ptr [[UCE]], align 1
39903 // SIMD-ONLY0-NEXT:    [[CONV901:%.*]] = zext i8 [[TMP562]] to i32
39904 // SIMD-ONLY0-NEXT:    [[TMP563:%.*]] = load i8, ptr [[UCX]], align 1
39905 // SIMD-ONLY0-NEXT:    [[CONV902:%.*]] = zext i8 [[TMP563]] to i32
39906 // SIMD-ONLY0-NEXT:    [[CMP903:%.*]] = icmp eq i32 [[CONV901]], [[CONV902]]
39907 // SIMD-ONLY0-NEXT:    br i1 [[CMP903]], label [[IF_THEN905:%.*]], label [[IF_END906:%.*]]
39908 // SIMD-ONLY0:       if.then905:
39909 // SIMD-ONLY0-NEXT:    [[TMP564:%.*]] = load i8, ptr [[UCD]], align 1
39910 // SIMD-ONLY0-NEXT:    store i8 [[TMP564]], ptr [[UCX]], align 1
39911 // SIMD-ONLY0-NEXT:    br label [[IF_END906]]
39912 // SIMD-ONLY0:       if.end906:
39913 // SIMD-ONLY0-NEXT:    [[TMP565:%.*]] = load i8, ptr [[UCX]], align 1
39914 // SIMD-ONLY0-NEXT:    store i8 [[TMP565]], ptr [[UCV]], align 1
39915 // SIMD-ONLY0-NEXT:    [[TMP566:%.*]] = load i8, ptr [[UCX]], align 1
39916 // SIMD-ONLY0-NEXT:    [[CONV907:%.*]] = zext i8 [[TMP566]] to i32
39917 // SIMD-ONLY0-NEXT:    [[TMP567:%.*]] = load i8, ptr [[UCE]], align 1
39918 // SIMD-ONLY0-NEXT:    [[CONV908:%.*]] = zext i8 [[TMP567]] to i32
39919 // SIMD-ONLY0-NEXT:    [[CMP909:%.*]] = icmp eq i32 [[CONV907]], [[CONV908]]
39920 // SIMD-ONLY0-NEXT:    br i1 [[CMP909]], label [[IF_THEN911:%.*]], label [[IF_ELSE912:%.*]]
39921 // SIMD-ONLY0:       if.then911:
39922 // SIMD-ONLY0-NEXT:    [[TMP568:%.*]] = load i8, ptr [[UCD]], align 1
39923 // SIMD-ONLY0-NEXT:    store i8 [[TMP568]], ptr [[UCX]], align 1
39924 // SIMD-ONLY0-NEXT:    br label [[IF_END913:%.*]]
39925 // SIMD-ONLY0:       if.else912:
39926 // SIMD-ONLY0-NEXT:    [[TMP569:%.*]] = load i8, ptr [[UCX]], align 1
39927 // SIMD-ONLY0-NEXT:    store i8 [[TMP569]], ptr [[UCV]], align 1
39928 // SIMD-ONLY0-NEXT:    br label [[IF_END913]]
39929 // SIMD-ONLY0:       if.end913:
39930 // SIMD-ONLY0-NEXT:    [[TMP570:%.*]] = load i8, ptr [[UCE]], align 1
39931 // SIMD-ONLY0-NEXT:    [[CONV914:%.*]] = zext i8 [[TMP570]] to i32
39932 // SIMD-ONLY0-NEXT:    [[TMP571:%.*]] = load i8, ptr [[UCX]], align 1
39933 // SIMD-ONLY0-NEXT:    [[CONV915:%.*]] = zext i8 [[TMP571]] to i32
39934 // SIMD-ONLY0-NEXT:    [[CMP916:%.*]] = icmp eq i32 [[CONV914]], [[CONV915]]
39935 // SIMD-ONLY0-NEXT:    br i1 [[CMP916]], label [[IF_THEN918:%.*]], label [[IF_ELSE919:%.*]]
39936 // SIMD-ONLY0:       if.then918:
39937 // SIMD-ONLY0-NEXT:    [[TMP572:%.*]] = load i8, ptr [[UCD]], align 1
39938 // SIMD-ONLY0-NEXT:    store i8 [[TMP572]], ptr [[UCX]], align 1
39939 // SIMD-ONLY0-NEXT:    br label [[IF_END920:%.*]]
39940 // SIMD-ONLY0:       if.else919:
39941 // SIMD-ONLY0-NEXT:    [[TMP573:%.*]] = load i8, ptr [[UCX]], align 1
39942 // SIMD-ONLY0-NEXT:    store i8 [[TMP573]], ptr [[UCV]], align 1
39943 // SIMD-ONLY0-NEXT:    br label [[IF_END920]]
39944 // SIMD-ONLY0:       if.end920:
39945 // SIMD-ONLY0-NEXT:    [[TMP574:%.*]] = load i8, ptr [[UCX]], align 1
39946 // SIMD-ONLY0-NEXT:    [[CONV921:%.*]] = zext i8 [[TMP574]] to i32
39947 // SIMD-ONLY0-NEXT:    [[TMP575:%.*]] = load i8, ptr [[UCE]], align 1
39948 // SIMD-ONLY0-NEXT:    [[CONV922:%.*]] = zext i8 [[TMP575]] to i32
39949 // SIMD-ONLY0-NEXT:    [[CMP923:%.*]] = icmp eq i32 [[CONV921]], [[CONV922]]
39950 // SIMD-ONLY0-NEXT:    [[CONV924:%.*]] = zext i1 [[CMP923]] to i32
39951 // SIMD-ONLY0-NEXT:    [[CONV925:%.*]] = trunc i32 [[CONV924]] to i8
39952 // SIMD-ONLY0-NEXT:    store i8 [[CONV925]], ptr [[UCR]], align 1
39953 // SIMD-ONLY0-NEXT:    [[TMP576:%.*]] = load i8, ptr [[UCR]], align 1
39954 // SIMD-ONLY0-NEXT:    [[TOBOOL926:%.*]] = icmp ne i8 [[TMP576]], 0
39955 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL926]], label [[IF_THEN927:%.*]], label [[IF_END928:%.*]]
39956 // SIMD-ONLY0:       if.then927:
39957 // SIMD-ONLY0-NEXT:    [[TMP577:%.*]] = load i8, ptr [[UCD]], align 1
39958 // SIMD-ONLY0-NEXT:    store i8 [[TMP577]], ptr [[UCX]], align 1
39959 // SIMD-ONLY0-NEXT:    br label [[IF_END928]]
39960 // SIMD-ONLY0:       if.end928:
39961 // SIMD-ONLY0-NEXT:    [[TMP578:%.*]] = load i8, ptr [[UCE]], align 1
39962 // SIMD-ONLY0-NEXT:    [[CONV929:%.*]] = zext i8 [[TMP578]] to i32
39963 // SIMD-ONLY0-NEXT:    [[TMP579:%.*]] = load i8, ptr [[UCX]], align 1
39964 // SIMD-ONLY0-NEXT:    [[CONV930:%.*]] = zext i8 [[TMP579]] to i32
39965 // SIMD-ONLY0-NEXT:    [[CMP931:%.*]] = icmp eq i32 [[CONV929]], [[CONV930]]
39966 // SIMD-ONLY0-NEXT:    [[CONV932:%.*]] = zext i1 [[CMP931]] to i32
39967 // SIMD-ONLY0-NEXT:    [[CONV933:%.*]] = trunc i32 [[CONV932]] to i8
39968 // SIMD-ONLY0-NEXT:    store i8 [[CONV933]], ptr [[UCR]], align 1
39969 // SIMD-ONLY0-NEXT:    [[TMP580:%.*]] = load i8, ptr [[UCR]], align 1
39970 // SIMD-ONLY0-NEXT:    [[TOBOOL934:%.*]] = icmp ne i8 [[TMP580]], 0
39971 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL934]], label [[IF_THEN935:%.*]], label [[IF_END936:%.*]]
39972 // SIMD-ONLY0:       if.then935:
39973 // SIMD-ONLY0-NEXT:    [[TMP581:%.*]] = load i8, ptr [[UCD]], align 1
39974 // SIMD-ONLY0-NEXT:    store i8 [[TMP581]], ptr [[UCX]], align 1
39975 // SIMD-ONLY0-NEXT:    br label [[IF_END936]]
39976 // SIMD-ONLY0:       if.end936:
39977 // SIMD-ONLY0-NEXT:    [[TMP582:%.*]] = load i8, ptr [[UCX]], align 1
39978 // SIMD-ONLY0-NEXT:    [[CONV937:%.*]] = zext i8 [[TMP582]] to i32
39979 // SIMD-ONLY0-NEXT:    [[TMP583:%.*]] = load i8, ptr [[UCE]], align 1
39980 // SIMD-ONLY0-NEXT:    [[CONV938:%.*]] = zext i8 [[TMP583]] to i32
39981 // SIMD-ONLY0-NEXT:    [[CMP939:%.*]] = icmp eq i32 [[CONV937]], [[CONV938]]
39982 // SIMD-ONLY0-NEXT:    [[CONV940:%.*]] = zext i1 [[CMP939]] to i32
39983 // SIMD-ONLY0-NEXT:    [[CONV941:%.*]] = trunc i32 [[CONV940]] to i8
39984 // SIMD-ONLY0-NEXT:    store i8 [[CONV941]], ptr [[UCR]], align 1
39985 // SIMD-ONLY0-NEXT:    [[TMP584:%.*]] = load i8, ptr [[UCR]], align 1
39986 // SIMD-ONLY0-NEXT:    [[TOBOOL942:%.*]] = icmp ne i8 [[TMP584]], 0
39987 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL942]], label [[IF_THEN943:%.*]], label [[IF_ELSE944:%.*]]
39988 // SIMD-ONLY0:       if.then943:
39989 // SIMD-ONLY0-NEXT:    [[TMP585:%.*]] = load i8, ptr [[UCD]], align 1
39990 // SIMD-ONLY0-NEXT:    store i8 [[TMP585]], ptr [[UCX]], align 1
39991 // SIMD-ONLY0-NEXT:    br label [[IF_END945:%.*]]
39992 // SIMD-ONLY0:       if.else944:
39993 // SIMD-ONLY0-NEXT:    [[TMP586:%.*]] = load i8, ptr [[UCX]], align 1
39994 // SIMD-ONLY0-NEXT:    store i8 [[TMP586]], ptr [[UCV]], align 1
39995 // SIMD-ONLY0-NEXT:    br label [[IF_END945]]
39996 // SIMD-ONLY0:       if.end945:
39997 // SIMD-ONLY0-NEXT:    [[TMP587:%.*]] = load i8, ptr [[UCE]], align 1
39998 // SIMD-ONLY0-NEXT:    [[CONV946:%.*]] = zext i8 [[TMP587]] to i32
39999 // SIMD-ONLY0-NEXT:    [[TMP588:%.*]] = load i8, ptr [[UCX]], align 1
40000 // SIMD-ONLY0-NEXT:    [[CONV947:%.*]] = zext i8 [[TMP588]] to i32
40001 // SIMD-ONLY0-NEXT:    [[CMP948:%.*]] = icmp eq i32 [[CONV946]], [[CONV947]]
40002 // SIMD-ONLY0-NEXT:    [[CONV949:%.*]] = zext i1 [[CMP948]] to i32
40003 // SIMD-ONLY0-NEXT:    [[CONV950:%.*]] = trunc i32 [[CONV949]] to i8
40004 // SIMD-ONLY0-NEXT:    store i8 [[CONV950]], ptr [[UCR]], align 1
40005 // SIMD-ONLY0-NEXT:    [[TMP589:%.*]] = load i8, ptr [[UCR]], align 1
40006 // SIMD-ONLY0-NEXT:    [[TOBOOL951:%.*]] = icmp ne i8 [[TMP589]], 0
40007 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL951]], label [[IF_THEN952:%.*]], label [[IF_ELSE953:%.*]]
40008 // SIMD-ONLY0:       if.then952:
40009 // SIMD-ONLY0-NEXT:    [[TMP590:%.*]] = load i8, ptr [[UCD]], align 1
40010 // SIMD-ONLY0-NEXT:    store i8 [[TMP590]], ptr [[UCX]], align 1
40011 // SIMD-ONLY0-NEXT:    br label [[IF_END954:%.*]]
40012 // SIMD-ONLY0:       if.else953:
40013 // SIMD-ONLY0-NEXT:    [[TMP591:%.*]] = load i8, ptr [[UCX]], align 1
40014 // SIMD-ONLY0-NEXT:    store i8 [[TMP591]], ptr [[UCV]], align 1
40015 // SIMD-ONLY0-NEXT:    br label [[IF_END954]]
40016 // SIMD-ONLY0:       if.end954:
40017 // SIMD-ONLY0-NEXT:    [[TMP592:%.*]] = load i8, ptr [[UCX]], align 1
40018 // SIMD-ONLY0-NEXT:    store i8 [[TMP592]], ptr [[UCV]], align 1
40019 // SIMD-ONLY0-NEXT:    [[TMP593:%.*]] = load i8, ptr [[UCE]], align 1
40020 // SIMD-ONLY0-NEXT:    [[CONV955:%.*]] = zext i8 [[TMP593]] to i32
40021 // SIMD-ONLY0-NEXT:    [[TMP594:%.*]] = load i8, ptr [[UCX]], align 1
40022 // SIMD-ONLY0-NEXT:    [[CONV956:%.*]] = zext i8 [[TMP594]] to i32
40023 // SIMD-ONLY0-NEXT:    [[CMP957:%.*]] = icmp sgt i32 [[CONV955]], [[CONV956]]
40024 // SIMD-ONLY0-NEXT:    br i1 [[CMP957]], label [[IF_THEN959:%.*]], label [[IF_END960:%.*]]
40025 // SIMD-ONLY0:       if.then959:
40026 // SIMD-ONLY0-NEXT:    [[TMP595:%.*]] = load i8, ptr [[UCE]], align 1
40027 // SIMD-ONLY0-NEXT:    store i8 [[TMP595]], ptr [[UCX]], align 1
40028 // SIMD-ONLY0-NEXT:    br label [[IF_END960]]
40029 // SIMD-ONLY0:       if.end960:
40030 // SIMD-ONLY0-NEXT:    [[TMP596:%.*]] = load i8, ptr [[UCX]], align 1
40031 // SIMD-ONLY0-NEXT:    store i8 [[TMP596]], ptr [[UCV]], align 1
40032 // SIMD-ONLY0-NEXT:    [[TMP597:%.*]] = load i8, ptr [[UCX]], align 1
40033 // SIMD-ONLY0-NEXT:    [[CONV961:%.*]] = zext i8 [[TMP597]] to i32
40034 // SIMD-ONLY0-NEXT:    [[TMP598:%.*]] = load i8, ptr [[UCE]], align 1
40035 // SIMD-ONLY0-NEXT:    [[CONV962:%.*]] = zext i8 [[TMP598]] to i32
40036 // SIMD-ONLY0-NEXT:    [[CMP963:%.*]] = icmp sgt i32 [[CONV961]], [[CONV962]]
40037 // SIMD-ONLY0-NEXT:    br i1 [[CMP963]], label [[IF_THEN965:%.*]], label [[IF_END966:%.*]]
40038 // SIMD-ONLY0:       if.then965:
40039 // SIMD-ONLY0-NEXT:    [[TMP599:%.*]] = load i8, ptr [[UCE]], align 1
40040 // SIMD-ONLY0-NEXT:    store i8 [[TMP599]], ptr [[UCX]], align 1
40041 // SIMD-ONLY0-NEXT:    br label [[IF_END966]]
40042 // SIMD-ONLY0:       if.end966:
40043 // SIMD-ONLY0-NEXT:    [[TMP600:%.*]] = load i8, ptr [[UCX]], align 1
40044 // SIMD-ONLY0-NEXT:    store i8 [[TMP600]], ptr [[UCV]], align 1
40045 // SIMD-ONLY0-NEXT:    [[TMP601:%.*]] = load i8, ptr [[UCE]], align 1
40046 // SIMD-ONLY0-NEXT:    [[CONV967:%.*]] = zext i8 [[TMP601]] to i32
40047 // SIMD-ONLY0-NEXT:    [[TMP602:%.*]] = load i8, ptr [[UCX]], align 1
40048 // SIMD-ONLY0-NEXT:    [[CONV968:%.*]] = zext i8 [[TMP602]] to i32
40049 // SIMD-ONLY0-NEXT:    [[CMP969:%.*]] = icmp slt i32 [[CONV967]], [[CONV968]]
40050 // SIMD-ONLY0-NEXT:    br i1 [[CMP969]], label [[IF_THEN971:%.*]], label [[IF_END972:%.*]]
40051 // SIMD-ONLY0:       if.then971:
40052 // SIMD-ONLY0-NEXT:    [[TMP603:%.*]] = load i8, ptr [[UCE]], align 1
40053 // SIMD-ONLY0-NEXT:    store i8 [[TMP603]], ptr [[UCX]], align 1
40054 // SIMD-ONLY0-NEXT:    br label [[IF_END972]]
40055 // SIMD-ONLY0:       if.end972:
40056 // SIMD-ONLY0-NEXT:    [[TMP604:%.*]] = load i8, ptr [[UCX]], align 1
40057 // SIMD-ONLY0-NEXT:    store i8 [[TMP604]], ptr [[UCV]], align 1
40058 // SIMD-ONLY0-NEXT:    [[TMP605:%.*]] = load i8, ptr [[UCX]], align 1
40059 // SIMD-ONLY0-NEXT:    [[CONV973:%.*]] = zext i8 [[TMP605]] to i32
40060 // SIMD-ONLY0-NEXT:    [[TMP606:%.*]] = load i8, ptr [[UCE]], align 1
40061 // SIMD-ONLY0-NEXT:    [[CONV974:%.*]] = zext i8 [[TMP606]] to i32
40062 // SIMD-ONLY0-NEXT:    [[CMP975:%.*]] = icmp slt i32 [[CONV973]], [[CONV974]]
40063 // SIMD-ONLY0-NEXT:    br i1 [[CMP975]], label [[IF_THEN977:%.*]], label [[IF_END978:%.*]]
40064 // SIMD-ONLY0:       if.then977:
40065 // SIMD-ONLY0-NEXT:    [[TMP607:%.*]] = load i8, ptr [[UCE]], align 1
40066 // SIMD-ONLY0-NEXT:    store i8 [[TMP607]], ptr [[UCX]], align 1
40067 // SIMD-ONLY0-NEXT:    br label [[IF_END978]]
40068 // SIMD-ONLY0:       if.end978:
40069 // SIMD-ONLY0-NEXT:    [[TMP608:%.*]] = load i8, ptr [[UCX]], align 1
40070 // SIMD-ONLY0-NEXT:    store i8 [[TMP608]], ptr [[UCV]], align 1
40071 // SIMD-ONLY0-NEXT:    [[TMP609:%.*]] = load i8, ptr [[UCX]], align 1
40072 // SIMD-ONLY0-NEXT:    [[CONV979:%.*]] = zext i8 [[TMP609]] to i32
40073 // SIMD-ONLY0-NEXT:    [[TMP610:%.*]] = load i8, ptr [[UCE]], align 1
40074 // SIMD-ONLY0-NEXT:    [[CONV980:%.*]] = zext i8 [[TMP610]] to i32
40075 // SIMD-ONLY0-NEXT:    [[CMP981:%.*]] = icmp eq i32 [[CONV979]], [[CONV980]]
40076 // SIMD-ONLY0-NEXT:    br i1 [[CMP981]], label [[IF_THEN983:%.*]], label [[IF_END984:%.*]]
40077 // SIMD-ONLY0:       if.then983:
40078 // SIMD-ONLY0-NEXT:    [[TMP611:%.*]] = load i8, ptr [[UCD]], align 1
40079 // SIMD-ONLY0-NEXT:    store i8 [[TMP611]], ptr [[UCX]], align 1
40080 // SIMD-ONLY0-NEXT:    br label [[IF_END984]]
40081 // SIMD-ONLY0:       if.end984:
40082 // SIMD-ONLY0-NEXT:    [[TMP612:%.*]] = load i8, ptr [[UCX]], align 1
40083 // SIMD-ONLY0-NEXT:    store i8 [[TMP612]], ptr [[UCV]], align 1
40084 // SIMD-ONLY0-NEXT:    [[TMP613:%.*]] = load i8, ptr [[UCE]], align 1
40085 // SIMD-ONLY0-NEXT:    [[CONV985:%.*]] = zext i8 [[TMP613]] to i32
40086 // SIMD-ONLY0-NEXT:    [[TMP614:%.*]] = load i8, ptr [[UCX]], align 1
40087 // SIMD-ONLY0-NEXT:    [[CONV986:%.*]] = zext i8 [[TMP614]] to i32
40088 // SIMD-ONLY0-NEXT:    [[CMP987:%.*]] = icmp eq i32 [[CONV985]], [[CONV986]]
40089 // SIMD-ONLY0-NEXT:    br i1 [[CMP987]], label [[IF_THEN989:%.*]], label [[IF_END990:%.*]]
40090 // SIMD-ONLY0:       if.then989:
40091 // SIMD-ONLY0-NEXT:    [[TMP615:%.*]] = load i8, ptr [[UCD]], align 1
40092 // SIMD-ONLY0-NEXT:    store i8 [[TMP615]], ptr [[UCX]], align 1
40093 // SIMD-ONLY0-NEXT:    br label [[IF_END990]]
40094 // SIMD-ONLY0:       if.end990:
40095 // SIMD-ONLY0-NEXT:    [[TMP616:%.*]] = load i8, ptr [[UCE]], align 1
40096 // SIMD-ONLY0-NEXT:    [[CONV991:%.*]] = zext i8 [[TMP616]] to i32
40097 // SIMD-ONLY0-NEXT:    [[TMP617:%.*]] = load i8, ptr [[UCX]], align 1
40098 // SIMD-ONLY0-NEXT:    [[CONV992:%.*]] = zext i8 [[TMP617]] to i32
40099 // SIMD-ONLY0-NEXT:    [[CMP993:%.*]] = icmp sgt i32 [[CONV991]], [[CONV992]]
40100 // SIMD-ONLY0-NEXT:    br i1 [[CMP993]], label [[IF_THEN995:%.*]], label [[IF_END996:%.*]]
40101 // SIMD-ONLY0:       if.then995:
40102 // SIMD-ONLY0-NEXT:    [[TMP618:%.*]] = load i8, ptr [[UCE]], align 1
40103 // SIMD-ONLY0-NEXT:    store i8 [[TMP618]], ptr [[UCX]], align 1
40104 // SIMD-ONLY0-NEXT:    br label [[IF_END996]]
40105 // SIMD-ONLY0:       if.end996:
40106 // SIMD-ONLY0-NEXT:    [[TMP619:%.*]] = load i8, ptr [[UCX]], align 1
40107 // SIMD-ONLY0-NEXT:    store i8 [[TMP619]], ptr [[UCV]], align 1
40108 // SIMD-ONLY0-NEXT:    [[TMP620:%.*]] = load i8, ptr [[UCX]], align 1
40109 // SIMD-ONLY0-NEXT:    [[CONV997:%.*]] = zext i8 [[TMP620]] to i32
40110 // SIMD-ONLY0-NEXT:    [[TMP621:%.*]] = load i8, ptr [[UCE]], align 1
40111 // SIMD-ONLY0-NEXT:    [[CONV998:%.*]] = zext i8 [[TMP621]] to i32
40112 // SIMD-ONLY0-NEXT:    [[CMP999:%.*]] = icmp sgt i32 [[CONV997]], [[CONV998]]
40113 // SIMD-ONLY0-NEXT:    br i1 [[CMP999]], label [[IF_THEN1001:%.*]], label [[IF_END1002:%.*]]
40114 // SIMD-ONLY0:       if.then1001:
40115 // SIMD-ONLY0-NEXT:    [[TMP622:%.*]] = load i8, ptr [[UCE]], align 1
40116 // SIMD-ONLY0-NEXT:    store i8 [[TMP622]], ptr [[UCX]], align 1
40117 // SIMD-ONLY0-NEXT:    br label [[IF_END1002]]
40118 // SIMD-ONLY0:       if.end1002:
40119 // SIMD-ONLY0-NEXT:    [[TMP623:%.*]] = load i8, ptr [[UCX]], align 1
40120 // SIMD-ONLY0-NEXT:    store i8 [[TMP623]], ptr [[UCV]], align 1
40121 // SIMD-ONLY0-NEXT:    [[TMP624:%.*]] = load i8, ptr [[UCE]], align 1
40122 // SIMD-ONLY0-NEXT:    [[CONV1003:%.*]] = zext i8 [[TMP624]] to i32
40123 // SIMD-ONLY0-NEXT:    [[TMP625:%.*]] = load i8, ptr [[UCX]], align 1
40124 // SIMD-ONLY0-NEXT:    [[CONV1004:%.*]] = zext i8 [[TMP625]] to i32
40125 // SIMD-ONLY0-NEXT:    [[CMP1005:%.*]] = icmp slt i32 [[CONV1003]], [[CONV1004]]
40126 // SIMD-ONLY0-NEXT:    br i1 [[CMP1005]], label [[IF_THEN1007:%.*]], label [[IF_END1008:%.*]]
40127 // SIMD-ONLY0:       if.then1007:
40128 // SIMD-ONLY0-NEXT:    [[TMP626:%.*]] = load i8, ptr [[UCE]], align 1
40129 // SIMD-ONLY0-NEXT:    store i8 [[TMP626]], ptr [[UCX]], align 1
40130 // SIMD-ONLY0-NEXT:    br label [[IF_END1008]]
40131 // SIMD-ONLY0:       if.end1008:
40132 // SIMD-ONLY0-NEXT:    [[TMP627:%.*]] = load i8, ptr [[UCX]], align 1
40133 // SIMD-ONLY0-NEXT:    store i8 [[TMP627]], ptr [[UCV]], align 1
40134 // SIMD-ONLY0-NEXT:    [[TMP628:%.*]] = load i8, ptr [[UCX]], align 1
40135 // SIMD-ONLY0-NEXT:    [[CONV1009:%.*]] = zext i8 [[TMP628]] to i32
40136 // SIMD-ONLY0-NEXT:    [[TMP629:%.*]] = load i8, ptr [[UCE]], align 1
40137 // SIMD-ONLY0-NEXT:    [[CONV1010:%.*]] = zext i8 [[TMP629]] to i32
40138 // SIMD-ONLY0-NEXT:    [[CMP1011:%.*]] = icmp slt i32 [[CONV1009]], [[CONV1010]]
40139 // SIMD-ONLY0-NEXT:    br i1 [[CMP1011]], label [[IF_THEN1013:%.*]], label [[IF_END1014:%.*]]
40140 // SIMD-ONLY0:       if.then1013:
40141 // SIMD-ONLY0-NEXT:    [[TMP630:%.*]] = load i8, ptr [[UCE]], align 1
40142 // SIMD-ONLY0-NEXT:    store i8 [[TMP630]], ptr [[UCX]], align 1
40143 // SIMD-ONLY0-NEXT:    br label [[IF_END1014]]
40144 // SIMD-ONLY0:       if.end1014:
40145 // SIMD-ONLY0-NEXT:    [[TMP631:%.*]] = load i8, ptr [[UCX]], align 1
40146 // SIMD-ONLY0-NEXT:    store i8 [[TMP631]], ptr [[UCV]], align 1
40147 // SIMD-ONLY0-NEXT:    [[TMP632:%.*]] = load i8, ptr [[UCX]], align 1
40148 // SIMD-ONLY0-NEXT:    [[CONV1015:%.*]] = zext i8 [[TMP632]] to i32
40149 // SIMD-ONLY0-NEXT:    [[TMP633:%.*]] = load i8, ptr [[UCE]], align 1
40150 // SIMD-ONLY0-NEXT:    [[CONV1016:%.*]] = zext i8 [[TMP633]] to i32
40151 // SIMD-ONLY0-NEXT:    [[CMP1017:%.*]] = icmp eq i32 [[CONV1015]], [[CONV1016]]
40152 // SIMD-ONLY0-NEXT:    br i1 [[CMP1017]], label [[IF_THEN1019:%.*]], label [[IF_END1020:%.*]]
40153 // SIMD-ONLY0:       if.then1019:
40154 // SIMD-ONLY0-NEXT:    [[TMP634:%.*]] = load i8, ptr [[UCD]], align 1
40155 // SIMD-ONLY0-NEXT:    store i8 [[TMP634]], ptr [[UCX]], align 1
40156 // SIMD-ONLY0-NEXT:    br label [[IF_END1020]]
40157 // SIMD-ONLY0:       if.end1020:
40158 // SIMD-ONLY0-NEXT:    [[TMP635:%.*]] = load i8, ptr [[UCX]], align 1
40159 // SIMD-ONLY0-NEXT:    store i8 [[TMP635]], ptr [[UCV]], align 1
40160 // SIMD-ONLY0-NEXT:    [[TMP636:%.*]] = load i8, ptr [[UCE]], align 1
40161 // SIMD-ONLY0-NEXT:    [[CONV1021:%.*]] = zext i8 [[TMP636]] to i32
40162 // SIMD-ONLY0-NEXT:    [[TMP637:%.*]] = load i8, ptr [[UCX]], align 1
40163 // SIMD-ONLY0-NEXT:    [[CONV1022:%.*]] = zext i8 [[TMP637]] to i32
40164 // SIMD-ONLY0-NEXT:    [[CMP1023:%.*]] = icmp eq i32 [[CONV1021]], [[CONV1022]]
40165 // SIMD-ONLY0-NEXT:    br i1 [[CMP1023]], label [[IF_THEN1025:%.*]], label [[IF_END1026:%.*]]
40166 // SIMD-ONLY0:       if.then1025:
40167 // SIMD-ONLY0-NEXT:    [[TMP638:%.*]] = load i8, ptr [[UCD]], align 1
40168 // SIMD-ONLY0-NEXT:    store i8 [[TMP638]], ptr [[UCX]], align 1
40169 // SIMD-ONLY0-NEXT:    br label [[IF_END1026]]
40170 // SIMD-ONLY0:       if.end1026:
40171 // SIMD-ONLY0-NEXT:    [[TMP639:%.*]] = load i8, ptr [[UCX]], align 1
40172 // SIMD-ONLY0-NEXT:    store i8 [[TMP639]], ptr [[UCV]], align 1
40173 // SIMD-ONLY0-NEXT:    [[TMP640:%.*]] = load i8, ptr [[UCX]], align 1
40174 // SIMD-ONLY0-NEXT:    [[CONV1027:%.*]] = zext i8 [[TMP640]] to i32
40175 // SIMD-ONLY0-NEXT:    [[TMP641:%.*]] = load i8, ptr [[UCE]], align 1
40176 // SIMD-ONLY0-NEXT:    [[CONV1028:%.*]] = zext i8 [[TMP641]] to i32
40177 // SIMD-ONLY0-NEXT:    [[CMP1029:%.*]] = icmp eq i32 [[CONV1027]], [[CONV1028]]
40178 // SIMD-ONLY0-NEXT:    br i1 [[CMP1029]], label [[IF_THEN1031:%.*]], label [[IF_ELSE1032:%.*]]
40179 // SIMD-ONLY0:       if.then1031:
40180 // SIMD-ONLY0-NEXT:    [[TMP642:%.*]] = load i8, ptr [[UCD]], align 1
40181 // SIMD-ONLY0-NEXT:    store i8 [[TMP642]], ptr [[UCX]], align 1
40182 // SIMD-ONLY0-NEXT:    br label [[IF_END1033:%.*]]
40183 // SIMD-ONLY0:       if.else1032:
40184 // SIMD-ONLY0-NEXT:    [[TMP643:%.*]] = load i8, ptr [[UCX]], align 1
40185 // SIMD-ONLY0-NEXT:    store i8 [[TMP643]], ptr [[UCV]], align 1
40186 // SIMD-ONLY0-NEXT:    br label [[IF_END1033]]
40187 // SIMD-ONLY0:       if.end1033:
40188 // SIMD-ONLY0-NEXT:    [[TMP644:%.*]] = load i8, ptr [[UCE]], align 1
40189 // SIMD-ONLY0-NEXT:    [[CONV1034:%.*]] = zext i8 [[TMP644]] to i32
40190 // SIMD-ONLY0-NEXT:    [[TMP645:%.*]] = load i8, ptr [[UCX]], align 1
40191 // SIMD-ONLY0-NEXT:    [[CONV1035:%.*]] = zext i8 [[TMP645]] to i32
40192 // SIMD-ONLY0-NEXT:    [[CMP1036:%.*]] = icmp eq i32 [[CONV1034]], [[CONV1035]]
40193 // SIMD-ONLY0-NEXT:    br i1 [[CMP1036]], label [[IF_THEN1038:%.*]], label [[IF_ELSE1039:%.*]]
40194 // SIMD-ONLY0:       if.then1038:
40195 // SIMD-ONLY0-NEXT:    [[TMP646:%.*]] = load i8, ptr [[UCD]], align 1
40196 // SIMD-ONLY0-NEXT:    store i8 [[TMP646]], ptr [[UCX]], align 1
40197 // SIMD-ONLY0-NEXT:    br label [[IF_END1040:%.*]]
40198 // SIMD-ONLY0:       if.else1039:
40199 // SIMD-ONLY0-NEXT:    [[TMP647:%.*]] = load i8, ptr [[UCX]], align 1
40200 // SIMD-ONLY0-NEXT:    store i8 [[TMP647]], ptr [[UCV]], align 1
40201 // SIMD-ONLY0-NEXT:    br label [[IF_END1040]]
40202 // SIMD-ONLY0:       if.end1040:
40203 // SIMD-ONLY0-NEXT:    [[TMP648:%.*]] = load i8, ptr [[UCX]], align 1
40204 // SIMD-ONLY0-NEXT:    [[CONV1041:%.*]] = zext i8 [[TMP648]] to i32
40205 // SIMD-ONLY0-NEXT:    [[TMP649:%.*]] = load i8, ptr [[UCE]], align 1
40206 // SIMD-ONLY0-NEXT:    [[CONV1042:%.*]] = zext i8 [[TMP649]] to i32
40207 // SIMD-ONLY0-NEXT:    [[CMP1043:%.*]] = icmp eq i32 [[CONV1041]], [[CONV1042]]
40208 // SIMD-ONLY0-NEXT:    [[CONV1044:%.*]] = zext i1 [[CMP1043]] to i32
40209 // SIMD-ONLY0-NEXT:    [[CONV1045:%.*]] = trunc i32 [[CONV1044]] to i8
40210 // SIMD-ONLY0-NEXT:    store i8 [[CONV1045]], ptr [[UCR]], align 1
40211 // SIMD-ONLY0-NEXT:    [[TMP650:%.*]] = load i8, ptr [[UCR]], align 1
40212 // SIMD-ONLY0-NEXT:    [[TOBOOL1046:%.*]] = icmp ne i8 [[TMP650]], 0
40213 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1046]], label [[IF_THEN1047:%.*]], label [[IF_END1048:%.*]]
40214 // SIMD-ONLY0:       if.then1047:
40215 // SIMD-ONLY0-NEXT:    [[TMP651:%.*]] = load i8, ptr [[UCD]], align 1
40216 // SIMD-ONLY0-NEXT:    store i8 [[TMP651]], ptr [[UCX]], align 1
40217 // SIMD-ONLY0-NEXT:    br label [[IF_END1048]]
40218 // SIMD-ONLY0:       if.end1048:
40219 // SIMD-ONLY0-NEXT:    [[TMP652:%.*]] = load i8, ptr [[UCE]], align 1
40220 // SIMD-ONLY0-NEXT:    [[CONV1049:%.*]] = zext i8 [[TMP652]] to i32
40221 // SIMD-ONLY0-NEXT:    [[TMP653:%.*]] = load i8, ptr [[UCX]], align 1
40222 // SIMD-ONLY0-NEXT:    [[CONV1050:%.*]] = zext i8 [[TMP653]] to i32
40223 // SIMD-ONLY0-NEXT:    [[CMP1051:%.*]] = icmp eq i32 [[CONV1049]], [[CONV1050]]
40224 // SIMD-ONLY0-NEXT:    [[CONV1052:%.*]] = zext i1 [[CMP1051]] to i32
40225 // SIMD-ONLY0-NEXT:    [[CONV1053:%.*]] = trunc i32 [[CONV1052]] to i8
40226 // SIMD-ONLY0-NEXT:    store i8 [[CONV1053]], ptr [[UCR]], align 1
40227 // SIMD-ONLY0-NEXT:    [[TMP654:%.*]] = load i8, ptr [[UCR]], align 1
40228 // SIMD-ONLY0-NEXT:    [[TOBOOL1054:%.*]] = icmp ne i8 [[TMP654]], 0
40229 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1054]], label [[IF_THEN1055:%.*]], label [[IF_END1056:%.*]]
40230 // SIMD-ONLY0:       if.then1055:
40231 // SIMD-ONLY0-NEXT:    [[TMP655:%.*]] = load i8, ptr [[UCD]], align 1
40232 // SIMD-ONLY0-NEXT:    store i8 [[TMP655]], ptr [[UCX]], align 1
40233 // SIMD-ONLY0-NEXT:    br label [[IF_END1056]]
40234 // SIMD-ONLY0:       if.end1056:
40235 // SIMD-ONLY0-NEXT:    [[TMP656:%.*]] = load i8, ptr [[UCX]], align 1
40236 // SIMD-ONLY0-NEXT:    [[CONV1057:%.*]] = zext i8 [[TMP656]] to i32
40237 // SIMD-ONLY0-NEXT:    [[TMP657:%.*]] = load i8, ptr [[UCE]], align 1
40238 // SIMD-ONLY0-NEXT:    [[CONV1058:%.*]] = zext i8 [[TMP657]] to i32
40239 // SIMD-ONLY0-NEXT:    [[CMP1059:%.*]] = icmp eq i32 [[CONV1057]], [[CONV1058]]
40240 // SIMD-ONLY0-NEXT:    [[CONV1060:%.*]] = zext i1 [[CMP1059]] to i32
40241 // SIMD-ONLY0-NEXT:    [[CONV1061:%.*]] = trunc i32 [[CONV1060]] to i8
40242 // SIMD-ONLY0-NEXT:    store i8 [[CONV1061]], ptr [[UCR]], align 1
40243 // SIMD-ONLY0-NEXT:    [[TMP658:%.*]] = load i8, ptr [[UCR]], align 1
40244 // SIMD-ONLY0-NEXT:    [[TOBOOL1062:%.*]] = icmp ne i8 [[TMP658]], 0
40245 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1062]], label [[IF_THEN1063:%.*]], label [[IF_ELSE1064:%.*]]
40246 // SIMD-ONLY0:       if.then1063:
40247 // SIMD-ONLY0-NEXT:    [[TMP659:%.*]] = load i8, ptr [[UCD]], align 1
40248 // SIMD-ONLY0-NEXT:    store i8 [[TMP659]], ptr [[UCX]], align 1
40249 // SIMD-ONLY0-NEXT:    br label [[IF_END1065:%.*]]
40250 // SIMD-ONLY0:       if.else1064:
40251 // SIMD-ONLY0-NEXT:    [[TMP660:%.*]] = load i8, ptr [[UCX]], align 1
40252 // SIMD-ONLY0-NEXT:    store i8 [[TMP660]], ptr [[UCV]], align 1
40253 // SIMD-ONLY0-NEXT:    br label [[IF_END1065]]
40254 // SIMD-ONLY0:       if.end1065:
40255 // SIMD-ONLY0-NEXT:    [[TMP661:%.*]] = load i8, ptr [[UCE]], align 1
40256 // SIMD-ONLY0-NEXT:    [[CONV1066:%.*]] = zext i8 [[TMP661]] to i32
40257 // SIMD-ONLY0-NEXT:    [[TMP662:%.*]] = load i8, ptr [[UCX]], align 1
40258 // SIMD-ONLY0-NEXT:    [[CONV1067:%.*]] = zext i8 [[TMP662]] to i32
40259 // SIMD-ONLY0-NEXT:    [[CMP1068:%.*]] = icmp eq i32 [[CONV1066]], [[CONV1067]]
40260 // SIMD-ONLY0-NEXT:    [[CONV1069:%.*]] = zext i1 [[CMP1068]] to i32
40261 // SIMD-ONLY0-NEXT:    [[CONV1070:%.*]] = trunc i32 [[CONV1069]] to i8
40262 // SIMD-ONLY0-NEXT:    store i8 [[CONV1070]], ptr [[UCR]], align 1
40263 // SIMD-ONLY0-NEXT:    [[TMP663:%.*]] = load i8, ptr [[UCR]], align 1
40264 // SIMD-ONLY0-NEXT:    [[TOBOOL1071:%.*]] = icmp ne i8 [[TMP663]], 0
40265 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1071]], label [[IF_THEN1072:%.*]], label [[IF_ELSE1073:%.*]]
40266 // SIMD-ONLY0:       if.then1072:
40267 // SIMD-ONLY0-NEXT:    [[TMP664:%.*]] = load i8, ptr [[UCD]], align 1
40268 // SIMD-ONLY0-NEXT:    store i8 [[TMP664]], ptr [[UCX]], align 1
40269 // SIMD-ONLY0-NEXT:    br label [[IF_END1074:%.*]]
40270 // SIMD-ONLY0:       if.else1073:
40271 // SIMD-ONLY0-NEXT:    [[TMP665:%.*]] = load i8, ptr [[UCX]], align 1
40272 // SIMD-ONLY0-NEXT:    store i8 [[TMP665]], ptr [[UCV]], align 1
40273 // SIMD-ONLY0-NEXT:    br label [[IF_END1074]]
40274 // SIMD-ONLY0:       if.end1074:
40275 // SIMD-ONLY0-NEXT:    [[TMP666:%.*]] = load i8, ptr [[UCX]], align 1
40276 // SIMD-ONLY0-NEXT:    store i8 [[TMP666]], ptr [[UCV]], align 1
40277 // SIMD-ONLY0-NEXT:    [[TMP667:%.*]] = load i8, ptr [[UCE]], align 1
40278 // SIMD-ONLY0-NEXT:    [[CONV1075:%.*]] = zext i8 [[TMP667]] to i32
40279 // SIMD-ONLY0-NEXT:    [[TMP668:%.*]] = load i8, ptr [[UCX]], align 1
40280 // SIMD-ONLY0-NEXT:    [[CONV1076:%.*]] = zext i8 [[TMP668]] to i32
40281 // SIMD-ONLY0-NEXT:    [[CMP1077:%.*]] = icmp sgt i32 [[CONV1075]], [[CONV1076]]
40282 // SIMD-ONLY0-NEXT:    br i1 [[CMP1077]], label [[IF_THEN1079:%.*]], label [[IF_END1080:%.*]]
40283 // SIMD-ONLY0:       if.then1079:
40284 // SIMD-ONLY0-NEXT:    [[TMP669:%.*]] = load i8, ptr [[UCE]], align 1
40285 // SIMD-ONLY0-NEXT:    store i8 [[TMP669]], ptr [[UCX]], align 1
40286 // SIMD-ONLY0-NEXT:    br label [[IF_END1080]]
40287 // SIMD-ONLY0:       if.end1080:
40288 // SIMD-ONLY0-NEXT:    [[TMP670:%.*]] = load i8, ptr [[UCX]], align 1
40289 // SIMD-ONLY0-NEXT:    store i8 [[TMP670]], ptr [[UCV]], align 1
40290 // SIMD-ONLY0-NEXT:    [[TMP671:%.*]] = load i8, ptr [[UCX]], align 1
40291 // SIMD-ONLY0-NEXT:    [[CONV1081:%.*]] = zext i8 [[TMP671]] to i32
40292 // SIMD-ONLY0-NEXT:    [[TMP672:%.*]] = load i8, ptr [[UCE]], align 1
40293 // SIMD-ONLY0-NEXT:    [[CONV1082:%.*]] = zext i8 [[TMP672]] to i32
40294 // SIMD-ONLY0-NEXT:    [[CMP1083:%.*]] = icmp sgt i32 [[CONV1081]], [[CONV1082]]
40295 // SIMD-ONLY0-NEXT:    br i1 [[CMP1083]], label [[IF_THEN1085:%.*]], label [[IF_END1086:%.*]]
40296 // SIMD-ONLY0:       if.then1085:
40297 // SIMD-ONLY0-NEXT:    [[TMP673:%.*]] = load i8, ptr [[UCE]], align 1
40298 // SIMD-ONLY0-NEXT:    store i8 [[TMP673]], ptr [[UCX]], align 1
40299 // SIMD-ONLY0-NEXT:    br label [[IF_END1086]]
40300 // SIMD-ONLY0:       if.end1086:
40301 // SIMD-ONLY0-NEXT:    [[TMP674:%.*]] = load i8, ptr [[UCX]], align 1
40302 // SIMD-ONLY0-NEXT:    store i8 [[TMP674]], ptr [[UCV]], align 1
40303 // SIMD-ONLY0-NEXT:    [[TMP675:%.*]] = load i8, ptr [[UCE]], align 1
40304 // SIMD-ONLY0-NEXT:    [[CONV1087:%.*]] = zext i8 [[TMP675]] to i32
40305 // SIMD-ONLY0-NEXT:    [[TMP676:%.*]] = load i8, ptr [[UCX]], align 1
40306 // SIMD-ONLY0-NEXT:    [[CONV1088:%.*]] = zext i8 [[TMP676]] to i32
40307 // SIMD-ONLY0-NEXT:    [[CMP1089:%.*]] = icmp slt i32 [[CONV1087]], [[CONV1088]]
40308 // SIMD-ONLY0-NEXT:    br i1 [[CMP1089]], label [[IF_THEN1091:%.*]], label [[IF_END1092:%.*]]
40309 // SIMD-ONLY0:       if.then1091:
40310 // SIMD-ONLY0-NEXT:    [[TMP677:%.*]] = load i8, ptr [[UCE]], align 1
40311 // SIMD-ONLY0-NEXT:    store i8 [[TMP677]], ptr [[UCX]], align 1
40312 // SIMD-ONLY0-NEXT:    br label [[IF_END1092]]
40313 // SIMD-ONLY0:       if.end1092:
40314 // SIMD-ONLY0-NEXT:    [[TMP678:%.*]] = load i8, ptr [[UCX]], align 1
40315 // SIMD-ONLY0-NEXT:    store i8 [[TMP678]], ptr [[UCV]], align 1
40316 // SIMD-ONLY0-NEXT:    [[TMP679:%.*]] = load i8, ptr [[UCX]], align 1
40317 // SIMD-ONLY0-NEXT:    [[CONV1093:%.*]] = zext i8 [[TMP679]] to i32
40318 // SIMD-ONLY0-NEXT:    [[TMP680:%.*]] = load i8, ptr [[UCE]], align 1
40319 // SIMD-ONLY0-NEXT:    [[CONV1094:%.*]] = zext i8 [[TMP680]] to i32
40320 // SIMD-ONLY0-NEXT:    [[CMP1095:%.*]] = icmp slt i32 [[CONV1093]], [[CONV1094]]
40321 // SIMD-ONLY0-NEXT:    br i1 [[CMP1095]], label [[IF_THEN1097:%.*]], label [[IF_END1098:%.*]]
40322 // SIMD-ONLY0:       if.then1097:
40323 // SIMD-ONLY0-NEXT:    [[TMP681:%.*]] = load i8, ptr [[UCE]], align 1
40324 // SIMD-ONLY0-NEXT:    store i8 [[TMP681]], ptr [[UCX]], align 1
40325 // SIMD-ONLY0-NEXT:    br label [[IF_END1098]]
40326 // SIMD-ONLY0:       if.end1098:
40327 // SIMD-ONLY0-NEXT:    [[TMP682:%.*]] = load i8, ptr [[UCX]], align 1
40328 // SIMD-ONLY0-NEXT:    store i8 [[TMP682]], ptr [[UCV]], align 1
40329 // SIMD-ONLY0-NEXT:    [[TMP683:%.*]] = load i8, ptr [[UCX]], align 1
40330 // SIMD-ONLY0-NEXT:    [[CONV1099:%.*]] = zext i8 [[TMP683]] to i32
40331 // SIMD-ONLY0-NEXT:    [[TMP684:%.*]] = load i8, ptr [[UCE]], align 1
40332 // SIMD-ONLY0-NEXT:    [[CONV1100:%.*]] = zext i8 [[TMP684]] to i32
40333 // SIMD-ONLY0-NEXT:    [[CMP1101:%.*]] = icmp eq i32 [[CONV1099]], [[CONV1100]]
40334 // SIMD-ONLY0-NEXT:    br i1 [[CMP1101]], label [[IF_THEN1103:%.*]], label [[IF_END1104:%.*]]
40335 // SIMD-ONLY0:       if.then1103:
40336 // SIMD-ONLY0-NEXT:    [[TMP685:%.*]] = load i8, ptr [[UCD]], align 1
40337 // SIMD-ONLY0-NEXT:    store i8 [[TMP685]], ptr [[UCX]], align 1
40338 // SIMD-ONLY0-NEXT:    br label [[IF_END1104]]
40339 // SIMD-ONLY0:       if.end1104:
40340 // SIMD-ONLY0-NEXT:    [[TMP686:%.*]] = load i8, ptr [[UCX]], align 1
40341 // SIMD-ONLY0-NEXT:    store i8 [[TMP686]], ptr [[UCV]], align 1
40342 // SIMD-ONLY0-NEXT:    [[TMP687:%.*]] = load i8, ptr [[UCE]], align 1
40343 // SIMD-ONLY0-NEXT:    [[CONV1105:%.*]] = zext i8 [[TMP687]] to i32
40344 // SIMD-ONLY0-NEXT:    [[TMP688:%.*]] = load i8, ptr [[UCX]], align 1
40345 // SIMD-ONLY0-NEXT:    [[CONV1106:%.*]] = zext i8 [[TMP688]] to i32
40346 // SIMD-ONLY0-NEXT:    [[CMP1107:%.*]] = icmp eq i32 [[CONV1105]], [[CONV1106]]
40347 // SIMD-ONLY0-NEXT:    br i1 [[CMP1107]], label [[IF_THEN1109:%.*]], label [[IF_END1110:%.*]]
40348 // SIMD-ONLY0:       if.then1109:
40349 // SIMD-ONLY0-NEXT:    [[TMP689:%.*]] = load i8, ptr [[UCD]], align 1
40350 // SIMD-ONLY0-NEXT:    store i8 [[TMP689]], ptr [[UCX]], align 1
40351 // SIMD-ONLY0-NEXT:    br label [[IF_END1110]]
40352 // SIMD-ONLY0:       if.end1110:
40353 // SIMD-ONLY0-NEXT:    [[TMP690:%.*]] = load i8, ptr [[UCE]], align 1
40354 // SIMD-ONLY0-NEXT:    [[CONV1111:%.*]] = zext i8 [[TMP690]] to i32
40355 // SIMD-ONLY0-NEXT:    [[TMP691:%.*]] = load i8, ptr [[UCX]], align 1
40356 // SIMD-ONLY0-NEXT:    [[CONV1112:%.*]] = zext i8 [[TMP691]] to i32
40357 // SIMD-ONLY0-NEXT:    [[CMP1113:%.*]] = icmp sgt i32 [[CONV1111]], [[CONV1112]]
40358 // SIMD-ONLY0-NEXT:    br i1 [[CMP1113]], label [[IF_THEN1115:%.*]], label [[IF_END1116:%.*]]
40359 // SIMD-ONLY0:       if.then1115:
40360 // SIMD-ONLY0-NEXT:    [[TMP692:%.*]] = load i8, ptr [[UCE]], align 1
40361 // SIMD-ONLY0-NEXT:    store i8 [[TMP692]], ptr [[UCX]], align 1
40362 // SIMD-ONLY0-NEXT:    br label [[IF_END1116]]
40363 // SIMD-ONLY0:       if.end1116:
40364 // SIMD-ONLY0-NEXT:    [[TMP693:%.*]] = load i8, ptr [[UCX]], align 1
40365 // SIMD-ONLY0-NEXT:    store i8 [[TMP693]], ptr [[UCV]], align 1
40366 // SIMD-ONLY0-NEXT:    [[TMP694:%.*]] = load i8, ptr [[UCX]], align 1
40367 // SIMD-ONLY0-NEXT:    [[CONV1117:%.*]] = zext i8 [[TMP694]] to i32
40368 // SIMD-ONLY0-NEXT:    [[TMP695:%.*]] = load i8, ptr [[UCE]], align 1
40369 // SIMD-ONLY0-NEXT:    [[CONV1118:%.*]] = zext i8 [[TMP695]] to i32
40370 // SIMD-ONLY0-NEXT:    [[CMP1119:%.*]] = icmp sgt i32 [[CONV1117]], [[CONV1118]]
40371 // SIMD-ONLY0-NEXT:    br i1 [[CMP1119]], label [[IF_THEN1121:%.*]], label [[IF_END1122:%.*]]
40372 // SIMD-ONLY0:       if.then1121:
40373 // SIMD-ONLY0-NEXT:    [[TMP696:%.*]] = load i8, ptr [[UCE]], align 1
40374 // SIMD-ONLY0-NEXT:    store i8 [[TMP696]], ptr [[UCX]], align 1
40375 // SIMD-ONLY0-NEXT:    br label [[IF_END1122]]
40376 // SIMD-ONLY0:       if.end1122:
40377 // SIMD-ONLY0-NEXT:    [[TMP697:%.*]] = load i8, ptr [[UCX]], align 1
40378 // SIMD-ONLY0-NEXT:    store i8 [[TMP697]], ptr [[UCV]], align 1
40379 // SIMD-ONLY0-NEXT:    [[TMP698:%.*]] = load i8, ptr [[UCE]], align 1
40380 // SIMD-ONLY0-NEXT:    [[CONV1123:%.*]] = zext i8 [[TMP698]] to i32
40381 // SIMD-ONLY0-NEXT:    [[TMP699:%.*]] = load i8, ptr [[UCX]], align 1
40382 // SIMD-ONLY0-NEXT:    [[CONV1124:%.*]] = zext i8 [[TMP699]] to i32
40383 // SIMD-ONLY0-NEXT:    [[CMP1125:%.*]] = icmp slt i32 [[CONV1123]], [[CONV1124]]
40384 // SIMD-ONLY0-NEXT:    br i1 [[CMP1125]], label [[IF_THEN1127:%.*]], label [[IF_END1128:%.*]]
40385 // SIMD-ONLY0:       if.then1127:
40386 // SIMD-ONLY0-NEXT:    [[TMP700:%.*]] = load i8, ptr [[UCE]], align 1
40387 // SIMD-ONLY0-NEXT:    store i8 [[TMP700]], ptr [[UCX]], align 1
40388 // SIMD-ONLY0-NEXT:    br label [[IF_END1128]]
40389 // SIMD-ONLY0:       if.end1128:
40390 // SIMD-ONLY0-NEXT:    [[TMP701:%.*]] = load i8, ptr [[UCX]], align 1
40391 // SIMD-ONLY0-NEXT:    store i8 [[TMP701]], ptr [[UCV]], align 1
40392 // SIMD-ONLY0-NEXT:    [[TMP702:%.*]] = load i8, ptr [[UCX]], align 1
40393 // SIMD-ONLY0-NEXT:    [[CONV1129:%.*]] = zext i8 [[TMP702]] to i32
40394 // SIMD-ONLY0-NEXT:    [[TMP703:%.*]] = load i8, ptr [[UCE]], align 1
40395 // SIMD-ONLY0-NEXT:    [[CONV1130:%.*]] = zext i8 [[TMP703]] to i32
40396 // SIMD-ONLY0-NEXT:    [[CMP1131:%.*]] = icmp slt i32 [[CONV1129]], [[CONV1130]]
40397 // SIMD-ONLY0-NEXT:    br i1 [[CMP1131]], label [[IF_THEN1133:%.*]], label [[IF_END1134:%.*]]
40398 // SIMD-ONLY0:       if.then1133:
40399 // SIMD-ONLY0-NEXT:    [[TMP704:%.*]] = load i8, ptr [[UCE]], align 1
40400 // SIMD-ONLY0-NEXT:    store i8 [[TMP704]], ptr [[UCX]], align 1
40401 // SIMD-ONLY0-NEXT:    br label [[IF_END1134]]
40402 // SIMD-ONLY0:       if.end1134:
40403 // SIMD-ONLY0-NEXT:    [[TMP705:%.*]] = load i8, ptr [[UCX]], align 1
40404 // SIMD-ONLY0-NEXT:    store i8 [[TMP705]], ptr [[UCV]], align 1
40405 // SIMD-ONLY0-NEXT:    [[TMP706:%.*]] = load i8, ptr [[UCX]], align 1
40406 // SIMD-ONLY0-NEXT:    [[CONV1135:%.*]] = zext i8 [[TMP706]] to i32
40407 // SIMD-ONLY0-NEXT:    [[TMP707:%.*]] = load i8, ptr [[UCE]], align 1
40408 // SIMD-ONLY0-NEXT:    [[CONV1136:%.*]] = zext i8 [[TMP707]] to i32
40409 // SIMD-ONLY0-NEXT:    [[CMP1137:%.*]] = icmp eq i32 [[CONV1135]], [[CONV1136]]
40410 // SIMD-ONLY0-NEXT:    br i1 [[CMP1137]], label [[IF_THEN1139:%.*]], label [[IF_END1140:%.*]]
40411 // SIMD-ONLY0:       if.then1139:
40412 // SIMD-ONLY0-NEXT:    [[TMP708:%.*]] = load i8, ptr [[UCD]], align 1
40413 // SIMD-ONLY0-NEXT:    store i8 [[TMP708]], ptr [[UCX]], align 1
40414 // SIMD-ONLY0-NEXT:    br label [[IF_END1140]]
40415 // SIMD-ONLY0:       if.end1140:
40416 // SIMD-ONLY0-NEXT:    [[TMP709:%.*]] = load i8, ptr [[UCX]], align 1
40417 // SIMD-ONLY0-NEXT:    store i8 [[TMP709]], ptr [[UCV]], align 1
40418 // SIMD-ONLY0-NEXT:    [[TMP710:%.*]] = load i8, ptr [[UCE]], align 1
40419 // SIMD-ONLY0-NEXT:    [[CONV1141:%.*]] = zext i8 [[TMP710]] to i32
40420 // SIMD-ONLY0-NEXT:    [[TMP711:%.*]] = load i8, ptr [[UCX]], align 1
40421 // SIMD-ONLY0-NEXT:    [[CONV1142:%.*]] = zext i8 [[TMP711]] to i32
40422 // SIMD-ONLY0-NEXT:    [[CMP1143:%.*]] = icmp eq i32 [[CONV1141]], [[CONV1142]]
40423 // SIMD-ONLY0-NEXT:    br i1 [[CMP1143]], label [[IF_THEN1145:%.*]], label [[IF_END1146:%.*]]
40424 // SIMD-ONLY0:       if.then1145:
40425 // SIMD-ONLY0-NEXT:    [[TMP712:%.*]] = load i8, ptr [[UCD]], align 1
40426 // SIMD-ONLY0-NEXT:    store i8 [[TMP712]], ptr [[UCX]], align 1
40427 // SIMD-ONLY0-NEXT:    br label [[IF_END1146]]
40428 // SIMD-ONLY0:       if.end1146:
40429 // SIMD-ONLY0-NEXT:    [[TMP713:%.*]] = load i8, ptr [[UCX]], align 1
40430 // SIMD-ONLY0-NEXT:    store i8 [[TMP713]], ptr [[UCV]], align 1
40431 // SIMD-ONLY0-NEXT:    [[TMP714:%.*]] = load i8, ptr [[UCX]], align 1
40432 // SIMD-ONLY0-NEXT:    [[CONV1147:%.*]] = zext i8 [[TMP714]] to i32
40433 // SIMD-ONLY0-NEXT:    [[TMP715:%.*]] = load i8, ptr [[UCE]], align 1
40434 // SIMD-ONLY0-NEXT:    [[CONV1148:%.*]] = zext i8 [[TMP715]] to i32
40435 // SIMD-ONLY0-NEXT:    [[CMP1149:%.*]] = icmp eq i32 [[CONV1147]], [[CONV1148]]
40436 // SIMD-ONLY0-NEXT:    br i1 [[CMP1149]], label [[IF_THEN1151:%.*]], label [[IF_ELSE1152:%.*]]
40437 // SIMD-ONLY0:       if.then1151:
40438 // SIMD-ONLY0-NEXT:    [[TMP716:%.*]] = load i8, ptr [[UCD]], align 1
40439 // SIMD-ONLY0-NEXT:    store i8 [[TMP716]], ptr [[UCX]], align 1
40440 // SIMD-ONLY0-NEXT:    br label [[IF_END1153:%.*]]
40441 // SIMD-ONLY0:       if.else1152:
40442 // SIMD-ONLY0-NEXT:    [[TMP717:%.*]] = load i8, ptr [[UCX]], align 1
40443 // SIMD-ONLY0-NEXT:    store i8 [[TMP717]], ptr [[UCV]], align 1
40444 // SIMD-ONLY0-NEXT:    br label [[IF_END1153]]
40445 // SIMD-ONLY0:       if.end1153:
40446 // SIMD-ONLY0-NEXT:    [[TMP718:%.*]] = load i8, ptr [[UCE]], align 1
40447 // SIMD-ONLY0-NEXT:    [[CONV1154:%.*]] = zext i8 [[TMP718]] to i32
40448 // SIMD-ONLY0-NEXT:    [[TMP719:%.*]] = load i8, ptr [[UCX]], align 1
40449 // SIMD-ONLY0-NEXT:    [[CONV1155:%.*]] = zext i8 [[TMP719]] to i32
40450 // SIMD-ONLY0-NEXT:    [[CMP1156:%.*]] = icmp eq i32 [[CONV1154]], [[CONV1155]]
40451 // SIMD-ONLY0-NEXT:    br i1 [[CMP1156]], label [[IF_THEN1158:%.*]], label [[IF_ELSE1159:%.*]]
40452 // SIMD-ONLY0:       if.then1158:
40453 // SIMD-ONLY0-NEXT:    [[TMP720:%.*]] = load i8, ptr [[UCD]], align 1
40454 // SIMD-ONLY0-NEXT:    store i8 [[TMP720]], ptr [[UCX]], align 1
40455 // SIMD-ONLY0-NEXT:    br label [[IF_END1160:%.*]]
40456 // SIMD-ONLY0:       if.else1159:
40457 // SIMD-ONLY0-NEXT:    [[TMP721:%.*]] = load i8, ptr [[UCX]], align 1
40458 // SIMD-ONLY0-NEXT:    store i8 [[TMP721]], ptr [[UCV]], align 1
40459 // SIMD-ONLY0-NEXT:    br label [[IF_END1160]]
40460 // SIMD-ONLY0:       if.end1160:
40461 // SIMD-ONLY0-NEXT:    [[TMP722:%.*]] = load i8, ptr [[UCX]], align 1
40462 // SIMD-ONLY0-NEXT:    [[CONV1161:%.*]] = zext i8 [[TMP722]] to i32
40463 // SIMD-ONLY0-NEXT:    [[TMP723:%.*]] = load i8, ptr [[UCE]], align 1
40464 // SIMD-ONLY0-NEXT:    [[CONV1162:%.*]] = zext i8 [[TMP723]] to i32
40465 // SIMD-ONLY0-NEXT:    [[CMP1163:%.*]] = icmp eq i32 [[CONV1161]], [[CONV1162]]
40466 // SIMD-ONLY0-NEXT:    [[CONV1164:%.*]] = zext i1 [[CMP1163]] to i32
40467 // SIMD-ONLY0-NEXT:    [[CONV1165:%.*]] = trunc i32 [[CONV1164]] to i8
40468 // SIMD-ONLY0-NEXT:    store i8 [[CONV1165]], ptr [[UCR]], align 1
40469 // SIMD-ONLY0-NEXT:    [[TMP724:%.*]] = load i8, ptr [[UCR]], align 1
40470 // SIMD-ONLY0-NEXT:    [[TOBOOL1166:%.*]] = icmp ne i8 [[TMP724]], 0
40471 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1166]], label [[IF_THEN1167:%.*]], label [[IF_END1168:%.*]]
40472 // SIMD-ONLY0:       if.then1167:
40473 // SIMD-ONLY0-NEXT:    [[TMP725:%.*]] = load i8, ptr [[UCD]], align 1
40474 // SIMD-ONLY0-NEXT:    store i8 [[TMP725]], ptr [[UCX]], align 1
40475 // SIMD-ONLY0-NEXT:    br label [[IF_END1168]]
40476 // SIMD-ONLY0:       if.end1168:
40477 // SIMD-ONLY0-NEXT:    [[TMP726:%.*]] = load i8, ptr [[UCE]], align 1
40478 // SIMD-ONLY0-NEXT:    [[CONV1169:%.*]] = zext i8 [[TMP726]] to i32
40479 // SIMD-ONLY0-NEXT:    [[TMP727:%.*]] = load i8, ptr [[UCX]], align 1
40480 // SIMD-ONLY0-NEXT:    [[CONV1170:%.*]] = zext i8 [[TMP727]] to i32
40481 // SIMD-ONLY0-NEXT:    [[CMP1171:%.*]] = icmp eq i32 [[CONV1169]], [[CONV1170]]
40482 // SIMD-ONLY0-NEXT:    [[CONV1172:%.*]] = zext i1 [[CMP1171]] to i32
40483 // SIMD-ONLY0-NEXT:    [[CONV1173:%.*]] = trunc i32 [[CONV1172]] to i8
40484 // SIMD-ONLY0-NEXT:    store i8 [[CONV1173]], ptr [[UCR]], align 1
40485 // SIMD-ONLY0-NEXT:    [[TMP728:%.*]] = load i8, ptr [[UCR]], align 1
40486 // SIMD-ONLY0-NEXT:    [[TOBOOL1174:%.*]] = icmp ne i8 [[TMP728]], 0
40487 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1174]], label [[IF_THEN1175:%.*]], label [[IF_END1176:%.*]]
40488 // SIMD-ONLY0:       if.then1175:
40489 // SIMD-ONLY0-NEXT:    [[TMP729:%.*]] = load i8, ptr [[UCD]], align 1
40490 // SIMD-ONLY0-NEXT:    store i8 [[TMP729]], ptr [[UCX]], align 1
40491 // SIMD-ONLY0-NEXT:    br label [[IF_END1176]]
40492 // SIMD-ONLY0:       if.end1176:
40493 // SIMD-ONLY0-NEXT:    [[TMP730:%.*]] = load i8, ptr [[UCX]], align 1
40494 // SIMD-ONLY0-NEXT:    [[CONV1177:%.*]] = zext i8 [[TMP730]] to i32
40495 // SIMD-ONLY0-NEXT:    [[TMP731:%.*]] = load i8, ptr [[UCE]], align 1
40496 // SIMD-ONLY0-NEXT:    [[CONV1178:%.*]] = zext i8 [[TMP731]] to i32
40497 // SIMD-ONLY0-NEXT:    [[CMP1179:%.*]] = icmp eq i32 [[CONV1177]], [[CONV1178]]
40498 // SIMD-ONLY0-NEXT:    [[CONV1180:%.*]] = zext i1 [[CMP1179]] to i32
40499 // SIMD-ONLY0-NEXT:    [[CONV1181:%.*]] = trunc i32 [[CONV1180]] to i8
40500 // SIMD-ONLY0-NEXT:    store i8 [[CONV1181]], ptr [[UCR]], align 1
40501 // SIMD-ONLY0-NEXT:    [[TMP732:%.*]] = load i8, ptr [[UCR]], align 1
40502 // SIMD-ONLY0-NEXT:    [[TOBOOL1182:%.*]] = icmp ne i8 [[TMP732]], 0
40503 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1182]], label [[IF_THEN1183:%.*]], label [[IF_ELSE1184:%.*]]
40504 // SIMD-ONLY0:       if.then1183:
40505 // SIMD-ONLY0-NEXT:    [[TMP733:%.*]] = load i8, ptr [[UCD]], align 1
40506 // SIMD-ONLY0-NEXT:    store i8 [[TMP733]], ptr [[UCX]], align 1
40507 // SIMD-ONLY0-NEXT:    br label [[IF_END1185:%.*]]
40508 // SIMD-ONLY0:       if.else1184:
40509 // SIMD-ONLY0-NEXT:    [[TMP734:%.*]] = load i8, ptr [[UCX]], align 1
40510 // SIMD-ONLY0-NEXT:    store i8 [[TMP734]], ptr [[UCV]], align 1
40511 // SIMD-ONLY0-NEXT:    br label [[IF_END1185]]
40512 // SIMD-ONLY0:       if.end1185:
40513 // SIMD-ONLY0-NEXT:    [[TMP735:%.*]] = load i8, ptr [[UCE]], align 1
40514 // SIMD-ONLY0-NEXT:    [[CONV1186:%.*]] = zext i8 [[TMP735]] to i32
40515 // SIMD-ONLY0-NEXT:    [[TMP736:%.*]] = load i8, ptr [[UCX]], align 1
40516 // SIMD-ONLY0-NEXT:    [[CONV1187:%.*]] = zext i8 [[TMP736]] to i32
40517 // SIMD-ONLY0-NEXT:    [[CMP1188:%.*]] = icmp eq i32 [[CONV1186]], [[CONV1187]]
40518 // SIMD-ONLY0-NEXT:    [[CONV1189:%.*]] = zext i1 [[CMP1188]] to i32
40519 // SIMD-ONLY0-NEXT:    [[CONV1190:%.*]] = trunc i32 [[CONV1189]] to i8
40520 // SIMD-ONLY0-NEXT:    store i8 [[CONV1190]], ptr [[UCR]], align 1
40521 // SIMD-ONLY0-NEXT:    [[TMP737:%.*]] = load i8, ptr [[UCR]], align 1
40522 // SIMD-ONLY0-NEXT:    [[TOBOOL1191:%.*]] = icmp ne i8 [[TMP737]], 0
40523 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1191]], label [[IF_THEN1192:%.*]], label [[IF_ELSE1193:%.*]]
40524 // SIMD-ONLY0:       if.then1192:
40525 // SIMD-ONLY0-NEXT:    [[TMP738:%.*]] = load i8, ptr [[UCD]], align 1
40526 // SIMD-ONLY0-NEXT:    store i8 [[TMP738]], ptr [[UCX]], align 1
40527 // SIMD-ONLY0-NEXT:    br label [[IF_END1194:%.*]]
40528 // SIMD-ONLY0:       if.else1193:
40529 // SIMD-ONLY0-NEXT:    [[TMP739:%.*]] = load i8, ptr [[UCX]], align 1
40530 // SIMD-ONLY0-NEXT:    store i8 [[TMP739]], ptr [[UCV]], align 1
40531 // SIMD-ONLY0-NEXT:    br label [[IF_END1194]]
40532 // SIMD-ONLY0:       if.end1194:
40533 // SIMD-ONLY0-NEXT:    [[TMP740:%.*]] = load i8, ptr [[UCX]], align 1
40534 // SIMD-ONLY0-NEXT:    store i8 [[TMP740]], ptr [[UCV]], align 1
40535 // SIMD-ONLY0-NEXT:    [[TMP741:%.*]] = load i8, ptr [[UCE]], align 1
40536 // SIMD-ONLY0-NEXT:    [[CONV1195:%.*]] = zext i8 [[TMP741]] to i32
40537 // SIMD-ONLY0-NEXT:    [[TMP742:%.*]] = load i8, ptr [[UCX]], align 1
40538 // SIMD-ONLY0-NEXT:    [[CONV1196:%.*]] = zext i8 [[TMP742]] to i32
40539 // SIMD-ONLY0-NEXT:    [[CMP1197:%.*]] = icmp sgt i32 [[CONV1195]], [[CONV1196]]
40540 // SIMD-ONLY0-NEXT:    br i1 [[CMP1197]], label [[IF_THEN1199:%.*]], label [[IF_END1200:%.*]]
40541 // SIMD-ONLY0:       if.then1199:
40542 // SIMD-ONLY0-NEXT:    [[TMP743:%.*]] = load i8, ptr [[UCE]], align 1
40543 // SIMD-ONLY0-NEXT:    store i8 [[TMP743]], ptr [[UCX]], align 1
40544 // SIMD-ONLY0-NEXT:    br label [[IF_END1200]]
40545 // SIMD-ONLY0:       if.end1200:
40546 // SIMD-ONLY0-NEXT:    [[TMP744:%.*]] = load i8, ptr [[UCX]], align 1
40547 // SIMD-ONLY0-NEXT:    store i8 [[TMP744]], ptr [[UCV]], align 1
40548 // SIMD-ONLY0-NEXT:    [[TMP745:%.*]] = load i8, ptr [[UCX]], align 1
40549 // SIMD-ONLY0-NEXT:    [[CONV1201:%.*]] = zext i8 [[TMP745]] to i32
40550 // SIMD-ONLY0-NEXT:    [[TMP746:%.*]] = load i8, ptr [[UCE]], align 1
40551 // SIMD-ONLY0-NEXT:    [[CONV1202:%.*]] = zext i8 [[TMP746]] to i32
40552 // SIMD-ONLY0-NEXT:    [[CMP1203:%.*]] = icmp sgt i32 [[CONV1201]], [[CONV1202]]
40553 // SIMD-ONLY0-NEXT:    br i1 [[CMP1203]], label [[IF_THEN1205:%.*]], label [[IF_END1206:%.*]]
40554 // SIMD-ONLY0:       if.then1205:
40555 // SIMD-ONLY0-NEXT:    [[TMP747:%.*]] = load i8, ptr [[UCE]], align 1
40556 // SIMD-ONLY0-NEXT:    store i8 [[TMP747]], ptr [[UCX]], align 1
40557 // SIMD-ONLY0-NEXT:    br label [[IF_END1206]]
40558 // SIMD-ONLY0:       if.end1206:
40559 // SIMD-ONLY0-NEXT:    [[TMP748:%.*]] = load i8, ptr [[UCX]], align 1
40560 // SIMD-ONLY0-NEXT:    store i8 [[TMP748]], ptr [[UCV]], align 1
40561 // SIMD-ONLY0-NEXT:    [[TMP749:%.*]] = load i8, ptr [[UCE]], align 1
40562 // SIMD-ONLY0-NEXT:    [[CONV1207:%.*]] = zext i8 [[TMP749]] to i32
40563 // SIMD-ONLY0-NEXT:    [[TMP750:%.*]] = load i8, ptr [[UCX]], align 1
40564 // SIMD-ONLY0-NEXT:    [[CONV1208:%.*]] = zext i8 [[TMP750]] to i32
40565 // SIMD-ONLY0-NEXT:    [[CMP1209:%.*]] = icmp slt i32 [[CONV1207]], [[CONV1208]]
40566 // SIMD-ONLY0-NEXT:    br i1 [[CMP1209]], label [[IF_THEN1211:%.*]], label [[IF_END1212:%.*]]
40567 // SIMD-ONLY0:       if.then1211:
40568 // SIMD-ONLY0-NEXT:    [[TMP751:%.*]] = load i8, ptr [[UCE]], align 1
40569 // SIMD-ONLY0-NEXT:    store i8 [[TMP751]], ptr [[UCX]], align 1
40570 // SIMD-ONLY0-NEXT:    br label [[IF_END1212]]
40571 // SIMD-ONLY0:       if.end1212:
40572 // SIMD-ONLY0-NEXT:    [[TMP752:%.*]] = load i8, ptr [[UCX]], align 1
40573 // SIMD-ONLY0-NEXT:    store i8 [[TMP752]], ptr [[UCV]], align 1
40574 // SIMD-ONLY0-NEXT:    [[TMP753:%.*]] = load i8, ptr [[UCX]], align 1
40575 // SIMD-ONLY0-NEXT:    [[CONV1213:%.*]] = zext i8 [[TMP753]] to i32
40576 // SIMD-ONLY0-NEXT:    [[TMP754:%.*]] = load i8, ptr [[UCE]], align 1
40577 // SIMD-ONLY0-NEXT:    [[CONV1214:%.*]] = zext i8 [[TMP754]] to i32
40578 // SIMD-ONLY0-NEXT:    [[CMP1215:%.*]] = icmp slt i32 [[CONV1213]], [[CONV1214]]
40579 // SIMD-ONLY0-NEXT:    br i1 [[CMP1215]], label [[IF_THEN1217:%.*]], label [[IF_END1218:%.*]]
40580 // SIMD-ONLY0:       if.then1217:
40581 // SIMD-ONLY0-NEXT:    [[TMP755:%.*]] = load i8, ptr [[UCE]], align 1
40582 // SIMD-ONLY0-NEXT:    store i8 [[TMP755]], ptr [[UCX]], align 1
40583 // SIMD-ONLY0-NEXT:    br label [[IF_END1218]]
40584 // SIMD-ONLY0:       if.end1218:
40585 // SIMD-ONLY0-NEXT:    [[TMP756:%.*]] = load i8, ptr [[UCX]], align 1
40586 // SIMD-ONLY0-NEXT:    store i8 [[TMP756]], ptr [[UCV]], align 1
40587 // SIMD-ONLY0-NEXT:    [[TMP757:%.*]] = load i8, ptr [[UCX]], align 1
40588 // SIMD-ONLY0-NEXT:    [[CONV1219:%.*]] = zext i8 [[TMP757]] to i32
40589 // SIMD-ONLY0-NEXT:    [[TMP758:%.*]] = load i8, ptr [[UCE]], align 1
40590 // SIMD-ONLY0-NEXT:    [[CONV1220:%.*]] = zext i8 [[TMP758]] to i32
40591 // SIMD-ONLY0-NEXT:    [[CMP1221:%.*]] = icmp eq i32 [[CONV1219]], [[CONV1220]]
40592 // SIMD-ONLY0-NEXT:    br i1 [[CMP1221]], label [[IF_THEN1223:%.*]], label [[IF_END1224:%.*]]
40593 // SIMD-ONLY0:       if.then1223:
40594 // SIMD-ONLY0-NEXT:    [[TMP759:%.*]] = load i8, ptr [[UCD]], align 1
40595 // SIMD-ONLY0-NEXT:    store i8 [[TMP759]], ptr [[UCX]], align 1
40596 // SIMD-ONLY0-NEXT:    br label [[IF_END1224]]
40597 // SIMD-ONLY0:       if.end1224:
40598 // SIMD-ONLY0-NEXT:    [[TMP760:%.*]] = load i8, ptr [[UCX]], align 1
40599 // SIMD-ONLY0-NEXT:    store i8 [[TMP760]], ptr [[UCV]], align 1
40600 // SIMD-ONLY0-NEXT:    [[TMP761:%.*]] = load i8, ptr [[UCE]], align 1
40601 // SIMD-ONLY0-NEXT:    [[CONV1225:%.*]] = zext i8 [[TMP761]] to i32
40602 // SIMD-ONLY0-NEXT:    [[TMP762:%.*]] = load i8, ptr [[UCX]], align 1
40603 // SIMD-ONLY0-NEXT:    [[CONV1226:%.*]] = zext i8 [[TMP762]] to i32
40604 // SIMD-ONLY0-NEXT:    [[CMP1227:%.*]] = icmp eq i32 [[CONV1225]], [[CONV1226]]
40605 // SIMD-ONLY0-NEXT:    br i1 [[CMP1227]], label [[IF_THEN1229:%.*]], label [[IF_END1230:%.*]]
40606 // SIMD-ONLY0:       if.then1229:
40607 // SIMD-ONLY0-NEXT:    [[TMP763:%.*]] = load i8, ptr [[UCD]], align 1
40608 // SIMD-ONLY0-NEXT:    store i8 [[TMP763]], ptr [[UCX]], align 1
40609 // SIMD-ONLY0-NEXT:    br label [[IF_END1230]]
40610 // SIMD-ONLY0:       if.end1230:
40611 // SIMD-ONLY0-NEXT:    [[TMP764:%.*]] = load i8, ptr [[UCE]], align 1
40612 // SIMD-ONLY0-NEXT:    [[CONV1231:%.*]] = zext i8 [[TMP764]] to i32
40613 // SIMD-ONLY0-NEXT:    [[TMP765:%.*]] = load i8, ptr [[UCX]], align 1
40614 // SIMD-ONLY0-NEXT:    [[CONV1232:%.*]] = zext i8 [[TMP765]] to i32
40615 // SIMD-ONLY0-NEXT:    [[CMP1233:%.*]] = icmp sgt i32 [[CONV1231]], [[CONV1232]]
40616 // SIMD-ONLY0-NEXT:    br i1 [[CMP1233]], label [[IF_THEN1235:%.*]], label [[IF_END1236:%.*]]
40617 // SIMD-ONLY0:       if.then1235:
40618 // SIMD-ONLY0-NEXT:    [[TMP766:%.*]] = load i8, ptr [[UCE]], align 1
40619 // SIMD-ONLY0-NEXT:    store i8 [[TMP766]], ptr [[UCX]], align 1
40620 // SIMD-ONLY0-NEXT:    br label [[IF_END1236]]
40621 // SIMD-ONLY0:       if.end1236:
40622 // SIMD-ONLY0-NEXT:    [[TMP767:%.*]] = load i8, ptr [[UCX]], align 1
40623 // SIMD-ONLY0-NEXT:    store i8 [[TMP767]], ptr [[UCV]], align 1
40624 // SIMD-ONLY0-NEXT:    [[TMP768:%.*]] = load i8, ptr [[UCX]], align 1
40625 // SIMD-ONLY0-NEXT:    [[CONV1237:%.*]] = zext i8 [[TMP768]] to i32
40626 // SIMD-ONLY0-NEXT:    [[TMP769:%.*]] = load i8, ptr [[UCE]], align 1
40627 // SIMD-ONLY0-NEXT:    [[CONV1238:%.*]] = zext i8 [[TMP769]] to i32
40628 // SIMD-ONLY0-NEXT:    [[CMP1239:%.*]] = icmp sgt i32 [[CONV1237]], [[CONV1238]]
40629 // SIMD-ONLY0-NEXT:    br i1 [[CMP1239]], label [[IF_THEN1241:%.*]], label [[IF_END1242:%.*]]
40630 // SIMD-ONLY0:       if.then1241:
40631 // SIMD-ONLY0-NEXT:    [[TMP770:%.*]] = load i8, ptr [[UCE]], align 1
40632 // SIMD-ONLY0-NEXT:    store i8 [[TMP770]], ptr [[UCX]], align 1
40633 // SIMD-ONLY0-NEXT:    br label [[IF_END1242]]
40634 // SIMD-ONLY0:       if.end1242:
40635 // SIMD-ONLY0-NEXT:    [[TMP771:%.*]] = load i8, ptr [[UCX]], align 1
40636 // SIMD-ONLY0-NEXT:    store i8 [[TMP771]], ptr [[UCV]], align 1
40637 // SIMD-ONLY0-NEXT:    [[TMP772:%.*]] = load i8, ptr [[UCE]], align 1
40638 // SIMD-ONLY0-NEXT:    [[CONV1243:%.*]] = zext i8 [[TMP772]] to i32
40639 // SIMD-ONLY0-NEXT:    [[TMP773:%.*]] = load i8, ptr [[UCX]], align 1
40640 // SIMD-ONLY0-NEXT:    [[CONV1244:%.*]] = zext i8 [[TMP773]] to i32
40641 // SIMD-ONLY0-NEXT:    [[CMP1245:%.*]] = icmp slt i32 [[CONV1243]], [[CONV1244]]
40642 // SIMD-ONLY0-NEXT:    br i1 [[CMP1245]], label [[IF_THEN1247:%.*]], label [[IF_END1248:%.*]]
40643 // SIMD-ONLY0:       if.then1247:
40644 // SIMD-ONLY0-NEXT:    [[TMP774:%.*]] = load i8, ptr [[UCE]], align 1
40645 // SIMD-ONLY0-NEXT:    store i8 [[TMP774]], ptr [[UCX]], align 1
40646 // SIMD-ONLY0-NEXT:    br label [[IF_END1248]]
40647 // SIMD-ONLY0:       if.end1248:
40648 // SIMD-ONLY0-NEXT:    [[TMP775:%.*]] = load i8, ptr [[UCX]], align 1
40649 // SIMD-ONLY0-NEXT:    store i8 [[TMP775]], ptr [[UCV]], align 1
40650 // SIMD-ONLY0-NEXT:    [[TMP776:%.*]] = load i8, ptr [[UCX]], align 1
40651 // SIMD-ONLY0-NEXT:    [[CONV1249:%.*]] = zext i8 [[TMP776]] to i32
40652 // SIMD-ONLY0-NEXT:    [[TMP777:%.*]] = load i8, ptr [[UCE]], align 1
40653 // SIMD-ONLY0-NEXT:    [[CONV1250:%.*]] = zext i8 [[TMP777]] to i32
40654 // SIMD-ONLY0-NEXT:    [[CMP1251:%.*]] = icmp slt i32 [[CONV1249]], [[CONV1250]]
40655 // SIMD-ONLY0-NEXT:    br i1 [[CMP1251]], label [[IF_THEN1253:%.*]], label [[IF_END1254:%.*]]
40656 // SIMD-ONLY0:       if.then1253:
40657 // SIMD-ONLY0-NEXT:    [[TMP778:%.*]] = load i8, ptr [[UCE]], align 1
40658 // SIMD-ONLY0-NEXT:    store i8 [[TMP778]], ptr [[UCX]], align 1
40659 // SIMD-ONLY0-NEXT:    br label [[IF_END1254]]
40660 // SIMD-ONLY0:       if.end1254:
40661 // SIMD-ONLY0-NEXT:    [[TMP779:%.*]] = load i8, ptr [[UCX]], align 1
40662 // SIMD-ONLY0-NEXT:    store i8 [[TMP779]], ptr [[UCV]], align 1
40663 // SIMD-ONLY0-NEXT:    [[TMP780:%.*]] = load i8, ptr [[UCX]], align 1
40664 // SIMD-ONLY0-NEXT:    [[CONV1255:%.*]] = zext i8 [[TMP780]] to i32
40665 // SIMD-ONLY0-NEXT:    [[TMP781:%.*]] = load i8, ptr [[UCE]], align 1
40666 // SIMD-ONLY0-NEXT:    [[CONV1256:%.*]] = zext i8 [[TMP781]] to i32
40667 // SIMD-ONLY0-NEXT:    [[CMP1257:%.*]] = icmp eq i32 [[CONV1255]], [[CONV1256]]
40668 // SIMD-ONLY0-NEXT:    br i1 [[CMP1257]], label [[IF_THEN1259:%.*]], label [[IF_END1260:%.*]]
40669 // SIMD-ONLY0:       if.then1259:
40670 // SIMD-ONLY0-NEXT:    [[TMP782:%.*]] = load i8, ptr [[UCD]], align 1
40671 // SIMD-ONLY0-NEXT:    store i8 [[TMP782]], ptr [[UCX]], align 1
40672 // SIMD-ONLY0-NEXT:    br label [[IF_END1260]]
40673 // SIMD-ONLY0:       if.end1260:
40674 // SIMD-ONLY0-NEXT:    [[TMP783:%.*]] = load i8, ptr [[UCX]], align 1
40675 // SIMD-ONLY0-NEXT:    store i8 [[TMP783]], ptr [[UCV]], align 1
40676 // SIMD-ONLY0-NEXT:    [[TMP784:%.*]] = load i8, ptr [[UCE]], align 1
40677 // SIMD-ONLY0-NEXT:    [[CONV1261:%.*]] = zext i8 [[TMP784]] to i32
40678 // SIMD-ONLY0-NEXT:    [[TMP785:%.*]] = load i8, ptr [[UCX]], align 1
40679 // SIMD-ONLY0-NEXT:    [[CONV1262:%.*]] = zext i8 [[TMP785]] to i32
40680 // SIMD-ONLY0-NEXT:    [[CMP1263:%.*]] = icmp eq i32 [[CONV1261]], [[CONV1262]]
40681 // SIMD-ONLY0-NEXT:    br i1 [[CMP1263]], label [[IF_THEN1265:%.*]], label [[IF_END1266:%.*]]
40682 // SIMD-ONLY0:       if.then1265:
40683 // SIMD-ONLY0-NEXT:    [[TMP786:%.*]] = load i8, ptr [[UCD]], align 1
40684 // SIMD-ONLY0-NEXT:    store i8 [[TMP786]], ptr [[UCX]], align 1
40685 // SIMD-ONLY0-NEXT:    br label [[IF_END1266]]
40686 // SIMD-ONLY0:       if.end1266:
40687 // SIMD-ONLY0-NEXT:    [[TMP787:%.*]] = load i8, ptr [[UCX]], align 1
40688 // SIMD-ONLY0-NEXT:    store i8 [[TMP787]], ptr [[UCV]], align 1
40689 // SIMD-ONLY0-NEXT:    [[TMP788:%.*]] = load i8, ptr [[UCX]], align 1
40690 // SIMD-ONLY0-NEXT:    [[CONV1267:%.*]] = zext i8 [[TMP788]] to i32
40691 // SIMD-ONLY0-NEXT:    [[TMP789:%.*]] = load i8, ptr [[UCE]], align 1
40692 // SIMD-ONLY0-NEXT:    [[CONV1268:%.*]] = zext i8 [[TMP789]] to i32
40693 // SIMD-ONLY0-NEXT:    [[CMP1269:%.*]] = icmp eq i32 [[CONV1267]], [[CONV1268]]
40694 // SIMD-ONLY0-NEXT:    br i1 [[CMP1269]], label [[IF_THEN1271:%.*]], label [[IF_ELSE1272:%.*]]
40695 // SIMD-ONLY0:       if.then1271:
40696 // SIMD-ONLY0-NEXT:    [[TMP790:%.*]] = load i8, ptr [[UCD]], align 1
40697 // SIMD-ONLY0-NEXT:    store i8 [[TMP790]], ptr [[UCX]], align 1
40698 // SIMD-ONLY0-NEXT:    br label [[IF_END1273:%.*]]
40699 // SIMD-ONLY0:       if.else1272:
40700 // SIMD-ONLY0-NEXT:    [[TMP791:%.*]] = load i8, ptr [[UCX]], align 1
40701 // SIMD-ONLY0-NEXT:    store i8 [[TMP791]], ptr [[UCV]], align 1
40702 // SIMD-ONLY0-NEXT:    br label [[IF_END1273]]
40703 // SIMD-ONLY0:       if.end1273:
40704 // SIMD-ONLY0-NEXT:    [[TMP792:%.*]] = load i8, ptr [[UCE]], align 1
40705 // SIMD-ONLY0-NEXT:    [[CONV1274:%.*]] = zext i8 [[TMP792]] to i32
40706 // SIMD-ONLY0-NEXT:    [[TMP793:%.*]] = load i8, ptr [[UCX]], align 1
40707 // SIMD-ONLY0-NEXT:    [[CONV1275:%.*]] = zext i8 [[TMP793]] to i32
40708 // SIMD-ONLY0-NEXT:    [[CMP1276:%.*]] = icmp eq i32 [[CONV1274]], [[CONV1275]]
40709 // SIMD-ONLY0-NEXT:    br i1 [[CMP1276]], label [[IF_THEN1278:%.*]], label [[IF_ELSE1279:%.*]]
40710 // SIMD-ONLY0:       if.then1278:
40711 // SIMD-ONLY0-NEXT:    [[TMP794:%.*]] = load i8, ptr [[UCD]], align 1
40712 // SIMD-ONLY0-NEXT:    store i8 [[TMP794]], ptr [[UCX]], align 1
40713 // SIMD-ONLY0-NEXT:    br label [[IF_END1280:%.*]]
40714 // SIMD-ONLY0:       if.else1279:
40715 // SIMD-ONLY0-NEXT:    [[TMP795:%.*]] = load i8, ptr [[UCX]], align 1
40716 // SIMD-ONLY0-NEXT:    store i8 [[TMP795]], ptr [[UCV]], align 1
40717 // SIMD-ONLY0-NEXT:    br label [[IF_END1280]]
40718 // SIMD-ONLY0:       if.end1280:
40719 // SIMD-ONLY0-NEXT:    [[TMP796:%.*]] = load i8, ptr [[UCX]], align 1
40720 // SIMD-ONLY0-NEXT:    [[CONV1281:%.*]] = zext i8 [[TMP796]] to i32
40721 // SIMD-ONLY0-NEXT:    [[TMP797:%.*]] = load i8, ptr [[UCE]], align 1
40722 // SIMD-ONLY0-NEXT:    [[CONV1282:%.*]] = zext i8 [[TMP797]] to i32
40723 // SIMD-ONLY0-NEXT:    [[CMP1283:%.*]] = icmp eq i32 [[CONV1281]], [[CONV1282]]
40724 // SIMD-ONLY0-NEXT:    [[CONV1284:%.*]] = zext i1 [[CMP1283]] to i32
40725 // SIMD-ONLY0-NEXT:    [[CONV1285:%.*]] = trunc i32 [[CONV1284]] to i8
40726 // SIMD-ONLY0-NEXT:    store i8 [[CONV1285]], ptr [[UCR]], align 1
40727 // SIMD-ONLY0-NEXT:    [[TMP798:%.*]] = load i8, ptr [[UCR]], align 1
40728 // SIMD-ONLY0-NEXT:    [[TOBOOL1286:%.*]] = icmp ne i8 [[TMP798]], 0
40729 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1286]], label [[IF_THEN1287:%.*]], label [[IF_END1288:%.*]]
40730 // SIMD-ONLY0:       if.then1287:
40731 // SIMD-ONLY0-NEXT:    [[TMP799:%.*]] = load i8, ptr [[UCD]], align 1
40732 // SIMD-ONLY0-NEXT:    store i8 [[TMP799]], ptr [[UCX]], align 1
40733 // SIMD-ONLY0-NEXT:    br label [[IF_END1288]]
40734 // SIMD-ONLY0:       if.end1288:
40735 // SIMD-ONLY0-NEXT:    [[TMP800:%.*]] = load i8, ptr [[UCE]], align 1
40736 // SIMD-ONLY0-NEXT:    [[CONV1289:%.*]] = zext i8 [[TMP800]] to i32
40737 // SIMD-ONLY0-NEXT:    [[TMP801:%.*]] = load i8, ptr [[UCX]], align 1
40738 // SIMD-ONLY0-NEXT:    [[CONV1290:%.*]] = zext i8 [[TMP801]] to i32
40739 // SIMD-ONLY0-NEXT:    [[CMP1291:%.*]] = icmp eq i32 [[CONV1289]], [[CONV1290]]
40740 // SIMD-ONLY0-NEXT:    [[CONV1292:%.*]] = zext i1 [[CMP1291]] to i32
40741 // SIMD-ONLY0-NEXT:    [[CONV1293:%.*]] = trunc i32 [[CONV1292]] to i8
40742 // SIMD-ONLY0-NEXT:    store i8 [[CONV1293]], ptr [[UCR]], align 1
40743 // SIMD-ONLY0-NEXT:    [[TMP802:%.*]] = load i8, ptr [[UCR]], align 1
40744 // SIMD-ONLY0-NEXT:    [[TOBOOL1294:%.*]] = icmp ne i8 [[TMP802]], 0
40745 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1294]], label [[IF_THEN1295:%.*]], label [[IF_END1296:%.*]]
40746 // SIMD-ONLY0:       if.then1295:
40747 // SIMD-ONLY0-NEXT:    [[TMP803:%.*]] = load i8, ptr [[UCD]], align 1
40748 // SIMD-ONLY0-NEXT:    store i8 [[TMP803]], ptr [[UCX]], align 1
40749 // SIMD-ONLY0-NEXT:    br label [[IF_END1296]]
40750 // SIMD-ONLY0:       if.end1296:
40751 // SIMD-ONLY0-NEXT:    [[TMP804:%.*]] = load i8, ptr [[UCX]], align 1
40752 // SIMD-ONLY0-NEXT:    [[CONV1297:%.*]] = zext i8 [[TMP804]] to i32
40753 // SIMD-ONLY0-NEXT:    [[TMP805:%.*]] = load i8, ptr [[UCE]], align 1
40754 // SIMD-ONLY0-NEXT:    [[CONV1298:%.*]] = zext i8 [[TMP805]] to i32
40755 // SIMD-ONLY0-NEXT:    [[CMP1299:%.*]] = icmp eq i32 [[CONV1297]], [[CONV1298]]
40756 // SIMD-ONLY0-NEXT:    [[CONV1300:%.*]] = zext i1 [[CMP1299]] to i32
40757 // SIMD-ONLY0-NEXT:    [[CONV1301:%.*]] = trunc i32 [[CONV1300]] to i8
40758 // SIMD-ONLY0-NEXT:    store i8 [[CONV1301]], ptr [[UCR]], align 1
40759 // SIMD-ONLY0-NEXT:    [[TMP806:%.*]] = load i8, ptr [[UCR]], align 1
40760 // SIMD-ONLY0-NEXT:    [[TOBOOL1302:%.*]] = icmp ne i8 [[TMP806]], 0
40761 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1302]], label [[IF_THEN1303:%.*]], label [[IF_ELSE1304:%.*]]
40762 // SIMD-ONLY0:       if.then1303:
40763 // SIMD-ONLY0-NEXT:    [[TMP807:%.*]] = load i8, ptr [[UCD]], align 1
40764 // SIMD-ONLY0-NEXT:    store i8 [[TMP807]], ptr [[UCX]], align 1
40765 // SIMD-ONLY0-NEXT:    br label [[IF_END1305:%.*]]
40766 // SIMD-ONLY0:       if.else1304:
40767 // SIMD-ONLY0-NEXT:    [[TMP808:%.*]] = load i8, ptr [[UCX]], align 1
40768 // SIMD-ONLY0-NEXT:    store i8 [[TMP808]], ptr [[UCV]], align 1
40769 // SIMD-ONLY0-NEXT:    br label [[IF_END1305]]
40770 // SIMD-ONLY0:       if.end1305:
40771 // SIMD-ONLY0-NEXT:    [[TMP809:%.*]] = load i8, ptr [[UCE]], align 1
40772 // SIMD-ONLY0-NEXT:    [[CONV1306:%.*]] = zext i8 [[TMP809]] to i32
40773 // SIMD-ONLY0-NEXT:    [[TMP810:%.*]] = load i8, ptr [[UCX]], align 1
40774 // SIMD-ONLY0-NEXT:    [[CONV1307:%.*]] = zext i8 [[TMP810]] to i32
40775 // SIMD-ONLY0-NEXT:    [[CMP1308:%.*]] = icmp eq i32 [[CONV1306]], [[CONV1307]]
40776 // SIMD-ONLY0-NEXT:    [[CONV1309:%.*]] = zext i1 [[CMP1308]] to i32
40777 // SIMD-ONLY0-NEXT:    [[CONV1310:%.*]] = trunc i32 [[CONV1309]] to i8
40778 // SIMD-ONLY0-NEXT:    store i8 [[CONV1310]], ptr [[UCR]], align 1
40779 // SIMD-ONLY0-NEXT:    [[TMP811:%.*]] = load i8, ptr [[UCR]], align 1
40780 // SIMD-ONLY0-NEXT:    [[TOBOOL1311:%.*]] = icmp ne i8 [[TMP811]], 0
40781 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1311]], label [[IF_THEN1312:%.*]], label [[IF_ELSE1313:%.*]]
40782 // SIMD-ONLY0:       if.then1312:
40783 // SIMD-ONLY0-NEXT:    [[TMP812:%.*]] = load i8, ptr [[UCD]], align 1
40784 // SIMD-ONLY0-NEXT:    store i8 [[TMP812]], ptr [[UCX]], align 1
40785 // SIMD-ONLY0-NEXT:    br label [[IF_END1314:%.*]]
40786 // SIMD-ONLY0:       if.else1313:
40787 // SIMD-ONLY0-NEXT:    [[TMP813:%.*]] = load i8, ptr [[UCX]], align 1
40788 // SIMD-ONLY0-NEXT:    store i8 [[TMP813]], ptr [[UCV]], align 1
40789 // SIMD-ONLY0-NEXT:    br label [[IF_END1314]]
40790 // SIMD-ONLY0:       if.end1314:
40791 // SIMD-ONLY0-NEXT:    [[TMP814:%.*]] = load i8, ptr [[UCX]], align 1
40792 // SIMD-ONLY0-NEXT:    store i8 [[TMP814]], ptr [[UCV]], align 1
40793 // SIMD-ONLY0-NEXT:    [[TMP815:%.*]] = load i8, ptr [[UCE]], align 1
40794 // SIMD-ONLY0-NEXT:    [[CONV1315:%.*]] = zext i8 [[TMP815]] to i32
40795 // SIMD-ONLY0-NEXT:    [[TMP816:%.*]] = load i8, ptr [[UCX]], align 1
40796 // SIMD-ONLY0-NEXT:    [[CONV1316:%.*]] = zext i8 [[TMP816]] to i32
40797 // SIMD-ONLY0-NEXT:    [[CMP1317:%.*]] = icmp sgt i32 [[CONV1315]], [[CONV1316]]
40798 // SIMD-ONLY0-NEXT:    br i1 [[CMP1317]], label [[IF_THEN1319:%.*]], label [[IF_END1320:%.*]]
40799 // SIMD-ONLY0:       if.then1319:
40800 // SIMD-ONLY0-NEXT:    [[TMP817:%.*]] = load i8, ptr [[UCE]], align 1
40801 // SIMD-ONLY0-NEXT:    store i8 [[TMP817]], ptr [[UCX]], align 1
40802 // SIMD-ONLY0-NEXT:    br label [[IF_END1320]]
40803 // SIMD-ONLY0:       if.end1320:
40804 // SIMD-ONLY0-NEXT:    [[TMP818:%.*]] = load i8, ptr [[UCX]], align 1
40805 // SIMD-ONLY0-NEXT:    store i8 [[TMP818]], ptr [[UCV]], align 1
40806 // SIMD-ONLY0-NEXT:    [[TMP819:%.*]] = load i8, ptr [[UCX]], align 1
40807 // SIMD-ONLY0-NEXT:    [[CONV1321:%.*]] = zext i8 [[TMP819]] to i32
40808 // SIMD-ONLY0-NEXT:    [[TMP820:%.*]] = load i8, ptr [[UCE]], align 1
40809 // SIMD-ONLY0-NEXT:    [[CONV1322:%.*]] = zext i8 [[TMP820]] to i32
40810 // SIMD-ONLY0-NEXT:    [[CMP1323:%.*]] = icmp sgt i32 [[CONV1321]], [[CONV1322]]
40811 // SIMD-ONLY0-NEXT:    br i1 [[CMP1323]], label [[IF_THEN1325:%.*]], label [[IF_END1326:%.*]]
40812 // SIMD-ONLY0:       if.then1325:
40813 // SIMD-ONLY0-NEXT:    [[TMP821:%.*]] = load i8, ptr [[UCE]], align 1
40814 // SIMD-ONLY0-NEXT:    store i8 [[TMP821]], ptr [[UCX]], align 1
40815 // SIMD-ONLY0-NEXT:    br label [[IF_END1326]]
40816 // SIMD-ONLY0:       if.end1326:
40817 // SIMD-ONLY0-NEXT:    [[TMP822:%.*]] = load i8, ptr [[UCX]], align 1
40818 // SIMD-ONLY0-NEXT:    store i8 [[TMP822]], ptr [[UCV]], align 1
40819 // SIMD-ONLY0-NEXT:    [[TMP823:%.*]] = load i8, ptr [[UCE]], align 1
40820 // SIMD-ONLY0-NEXT:    [[CONV1327:%.*]] = zext i8 [[TMP823]] to i32
40821 // SIMD-ONLY0-NEXT:    [[TMP824:%.*]] = load i8, ptr [[UCX]], align 1
40822 // SIMD-ONLY0-NEXT:    [[CONV1328:%.*]] = zext i8 [[TMP824]] to i32
40823 // SIMD-ONLY0-NEXT:    [[CMP1329:%.*]] = icmp slt i32 [[CONV1327]], [[CONV1328]]
40824 // SIMD-ONLY0-NEXT:    br i1 [[CMP1329]], label [[IF_THEN1331:%.*]], label [[IF_END1332:%.*]]
40825 // SIMD-ONLY0:       if.then1331:
40826 // SIMD-ONLY0-NEXT:    [[TMP825:%.*]] = load i8, ptr [[UCE]], align 1
40827 // SIMD-ONLY0-NEXT:    store i8 [[TMP825]], ptr [[UCX]], align 1
40828 // SIMD-ONLY0-NEXT:    br label [[IF_END1332]]
40829 // SIMD-ONLY0:       if.end1332:
40830 // SIMD-ONLY0-NEXT:    [[TMP826:%.*]] = load i8, ptr [[UCX]], align 1
40831 // SIMD-ONLY0-NEXT:    store i8 [[TMP826]], ptr [[UCV]], align 1
40832 // SIMD-ONLY0-NEXT:    [[TMP827:%.*]] = load i8, ptr [[UCX]], align 1
40833 // SIMD-ONLY0-NEXT:    [[CONV1333:%.*]] = zext i8 [[TMP827]] to i32
40834 // SIMD-ONLY0-NEXT:    [[TMP828:%.*]] = load i8, ptr [[UCE]], align 1
40835 // SIMD-ONLY0-NEXT:    [[CONV1334:%.*]] = zext i8 [[TMP828]] to i32
40836 // SIMD-ONLY0-NEXT:    [[CMP1335:%.*]] = icmp slt i32 [[CONV1333]], [[CONV1334]]
40837 // SIMD-ONLY0-NEXT:    br i1 [[CMP1335]], label [[IF_THEN1337:%.*]], label [[IF_END1338:%.*]]
40838 // SIMD-ONLY0:       if.then1337:
40839 // SIMD-ONLY0-NEXT:    [[TMP829:%.*]] = load i8, ptr [[UCE]], align 1
40840 // SIMD-ONLY0-NEXT:    store i8 [[TMP829]], ptr [[UCX]], align 1
40841 // SIMD-ONLY0-NEXT:    br label [[IF_END1338]]
40842 // SIMD-ONLY0:       if.end1338:
40843 // SIMD-ONLY0-NEXT:    [[TMP830:%.*]] = load i8, ptr [[UCX]], align 1
40844 // SIMD-ONLY0-NEXT:    store i8 [[TMP830]], ptr [[UCV]], align 1
40845 // SIMD-ONLY0-NEXT:    [[TMP831:%.*]] = load i8, ptr [[UCX]], align 1
40846 // SIMD-ONLY0-NEXT:    [[CONV1339:%.*]] = zext i8 [[TMP831]] to i32
40847 // SIMD-ONLY0-NEXT:    [[TMP832:%.*]] = load i8, ptr [[UCE]], align 1
40848 // SIMD-ONLY0-NEXT:    [[CONV1340:%.*]] = zext i8 [[TMP832]] to i32
40849 // SIMD-ONLY0-NEXT:    [[CMP1341:%.*]] = icmp eq i32 [[CONV1339]], [[CONV1340]]
40850 // SIMD-ONLY0-NEXT:    br i1 [[CMP1341]], label [[IF_THEN1343:%.*]], label [[IF_END1344:%.*]]
40851 // SIMD-ONLY0:       if.then1343:
40852 // SIMD-ONLY0-NEXT:    [[TMP833:%.*]] = load i8, ptr [[UCD]], align 1
40853 // SIMD-ONLY0-NEXT:    store i8 [[TMP833]], ptr [[UCX]], align 1
40854 // SIMD-ONLY0-NEXT:    br label [[IF_END1344]]
40855 // SIMD-ONLY0:       if.end1344:
40856 // SIMD-ONLY0-NEXT:    [[TMP834:%.*]] = load i8, ptr [[UCX]], align 1
40857 // SIMD-ONLY0-NEXT:    store i8 [[TMP834]], ptr [[UCV]], align 1
40858 // SIMD-ONLY0-NEXT:    [[TMP835:%.*]] = load i8, ptr [[UCE]], align 1
40859 // SIMD-ONLY0-NEXT:    [[CONV1345:%.*]] = zext i8 [[TMP835]] to i32
40860 // SIMD-ONLY0-NEXT:    [[TMP836:%.*]] = load i8, ptr [[UCX]], align 1
40861 // SIMD-ONLY0-NEXT:    [[CONV1346:%.*]] = zext i8 [[TMP836]] to i32
40862 // SIMD-ONLY0-NEXT:    [[CMP1347:%.*]] = icmp eq i32 [[CONV1345]], [[CONV1346]]
40863 // SIMD-ONLY0-NEXT:    br i1 [[CMP1347]], label [[IF_THEN1349:%.*]], label [[IF_END1350:%.*]]
40864 // SIMD-ONLY0:       if.then1349:
40865 // SIMD-ONLY0-NEXT:    [[TMP837:%.*]] = load i8, ptr [[UCD]], align 1
40866 // SIMD-ONLY0-NEXT:    store i8 [[TMP837]], ptr [[UCX]], align 1
40867 // SIMD-ONLY0-NEXT:    br label [[IF_END1350]]
40868 // SIMD-ONLY0:       if.end1350:
40869 // SIMD-ONLY0-NEXT:    [[TMP838:%.*]] = load i8, ptr [[UCE]], align 1
40870 // SIMD-ONLY0-NEXT:    [[CONV1351:%.*]] = zext i8 [[TMP838]] to i32
40871 // SIMD-ONLY0-NEXT:    [[TMP839:%.*]] = load i8, ptr [[UCX]], align 1
40872 // SIMD-ONLY0-NEXT:    [[CONV1352:%.*]] = zext i8 [[TMP839]] to i32
40873 // SIMD-ONLY0-NEXT:    [[CMP1353:%.*]] = icmp sgt i32 [[CONV1351]], [[CONV1352]]
40874 // SIMD-ONLY0-NEXT:    br i1 [[CMP1353]], label [[IF_THEN1355:%.*]], label [[IF_END1356:%.*]]
40875 // SIMD-ONLY0:       if.then1355:
40876 // SIMD-ONLY0-NEXT:    [[TMP840:%.*]] = load i8, ptr [[UCE]], align 1
40877 // SIMD-ONLY0-NEXT:    store i8 [[TMP840]], ptr [[UCX]], align 1
40878 // SIMD-ONLY0-NEXT:    br label [[IF_END1356]]
40879 // SIMD-ONLY0:       if.end1356:
40880 // SIMD-ONLY0-NEXT:    [[TMP841:%.*]] = load i8, ptr [[UCX]], align 1
40881 // SIMD-ONLY0-NEXT:    store i8 [[TMP841]], ptr [[UCV]], align 1
40882 // SIMD-ONLY0-NEXT:    [[TMP842:%.*]] = load i8, ptr [[UCX]], align 1
40883 // SIMD-ONLY0-NEXT:    [[CONV1357:%.*]] = zext i8 [[TMP842]] to i32
40884 // SIMD-ONLY0-NEXT:    [[TMP843:%.*]] = load i8, ptr [[UCE]], align 1
40885 // SIMD-ONLY0-NEXT:    [[CONV1358:%.*]] = zext i8 [[TMP843]] to i32
40886 // SIMD-ONLY0-NEXT:    [[CMP1359:%.*]] = icmp sgt i32 [[CONV1357]], [[CONV1358]]
40887 // SIMD-ONLY0-NEXT:    br i1 [[CMP1359]], label [[IF_THEN1361:%.*]], label [[IF_END1362:%.*]]
40888 // SIMD-ONLY0:       if.then1361:
40889 // SIMD-ONLY0-NEXT:    [[TMP844:%.*]] = load i8, ptr [[UCE]], align 1
40890 // SIMD-ONLY0-NEXT:    store i8 [[TMP844]], ptr [[UCX]], align 1
40891 // SIMD-ONLY0-NEXT:    br label [[IF_END1362]]
40892 // SIMD-ONLY0:       if.end1362:
40893 // SIMD-ONLY0-NEXT:    [[TMP845:%.*]] = load i8, ptr [[UCX]], align 1
40894 // SIMD-ONLY0-NEXT:    store i8 [[TMP845]], ptr [[UCV]], align 1
40895 // SIMD-ONLY0-NEXT:    [[TMP846:%.*]] = load i8, ptr [[UCE]], align 1
40896 // SIMD-ONLY0-NEXT:    [[CONV1363:%.*]] = zext i8 [[TMP846]] to i32
40897 // SIMD-ONLY0-NEXT:    [[TMP847:%.*]] = load i8, ptr [[UCX]], align 1
40898 // SIMD-ONLY0-NEXT:    [[CONV1364:%.*]] = zext i8 [[TMP847]] to i32
40899 // SIMD-ONLY0-NEXT:    [[CMP1365:%.*]] = icmp slt i32 [[CONV1363]], [[CONV1364]]
40900 // SIMD-ONLY0-NEXT:    br i1 [[CMP1365]], label [[IF_THEN1367:%.*]], label [[IF_END1368:%.*]]
40901 // SIMD-ONLY0:       if.then1367:
40902 // SIMD-ONLY0-NEXT:    [[TMP848:%.*]] = load i8, ptr [[UCE]], align 1
40903 // SIMD-ONLY0-NEXT:    store i8 [[TMP848]], ptr [[UCX]], align 1
40904 // SIMD-ONLY0-NEXT:    br label [[IF_END1368]]
40905 // SIMD-ONLY0:       if.end1368:
40906 // SIMD-ONLY0-NEXT:    [[TMP849:%.*]] = load i8, ptr [[UCX]], align 1
40907 // SIMD-ONLY0-NEXT:    store i8 [[TMP849]], ptr [[UCV]], align 1
40908 // SIMD-ONLY0-NEXT:    [[TMP850:%.*]] = load i8, ptr [[UCX]], align 1
40909 // SIMD-ONLY0-NEXT:    [[CONV1369:%.*]] = zext i8 [[TMP850]] to i32
40910 // SIMD-ONLY0-NEXT:    [[TMP851:%.*]] = load i8, ptr [[UCE]], align 1
40911 // SIMD-ONLY0-NEXT:    [[CONV1370:%.*]] = zext i8 [[TMP851]] to i32
40912 // SIMD-ONLY0-NEXT:    [[CMP1371:%.*]] = icmp slt i32 [[CONV1369]], [[CONV1370]]
40913 // SIMD-ONLY0-NEXT:    br i1 [[CMP1371]], label [[IF_THEN1373:%.*]], label [[IF_END1374:%.*]]
40914 // SIMD-ONLY0:       if.then1373:
40915 // SIMD-ONLY0-NEXT:    [[TMP852:%.*]] = load i8, ptr [[UCE]], align 1
40916 // SIMD-ONLY0-NEXT:    store i8 [[TMP852]], ptr [[UCX]], align 1
40917 // SIMD-ONLY0-NEXT:    br label [[IF_END1374]]
40918 // SIMD-ONLY0:       if.end1374:
40919 // SIMD-ONLY0-NEXT:    [[TMP853:%.*]] = load i8, ptr [[UCX]], align 1
40920 // SIMD-ONLY0-NEXT:    store i8 [[TMP853]], ptr [[UCV]], align 1
40921 // SIMD-ONLY0-NEXT:    [[TMP854:%.*]] = load i8, ptr [[UCX]], align 1
40922 // SIMD-ONLY0-NEXT:    [[CONV1375:%.*]] = zext i8 [[TMP854]] to i32
40923 // SIMD-ONLY0-NEXT:    [[TMP855:%.*]] = load i8, ptr [[UCE]], align 1
40924 // SIMD-ONLY0-NEXT:    [[CONV1376:%.*]] = zext i8 [[TMP855]] to i32
40925 // SIMD-ONLY0-NEXT:    [[CMP1377:%.*]] = icmp eq i32 [[CONV1375]], [[CONV1376]]
40926 // SIMD-ONLY0-NEXT:    br i1 [[CMP1377]], label [[IF_THEN1379:%.*]], label [[IF_END1380:%.*]]
40927 // SIMD-ONLY0:       if.then1379:
40928 // SIMD-ONLY0-NEXT:    [[TMP856:%.*]] = load i8, ptr [[UCD]], align 1
40929 // SIMD-ONLY0-NEXT:    store i8 [[TMP856]], ptr [[UCX]], align 1
40930 // SIMD-ONLY0-NEXT:    br label [[IF_END1380]]
40931 // SIMD-ONLY0:       if.end1380:
40932 // SIMD-ONLY0-NEXT:    [[TMP857:%.*]] = load i8, ptr [[UCX]], align 1
40933 // SIMD-ONLY0-NEXT:    store i8 [[TMP857]], ptr [[UCV]], align 1
40934 // SIMD-ONLY0-NEXT:    [[TMP858:%.*]] = load i8, ptr [[UCE]], align 1
40935 // SIMD-ONLY0-NEXT:    [[CONV1381:%.*]] = zext i8 [[TMP858]] to i32
40936 // SIMD-ONLY0-NEXT:    [[TMP859:%.*]] = load i8, ptr [[UCX]], align 1
40937 // SIMD-ONLY0-NEXT:    [[CONV1382:%.*]] = zext i8 [[TMP859]] to i32
40938 // SIMD-ONLY0-NEXT:    [[CMP1383:%.*]] = icmp eq i32 [[CONV1381]], [[CONV1382]]
40939 // SIMD-ONLY0-NEXT:    br i1 [[CMP1383]], label [[IF_THEN1385:%.*]], label [[IF_END1386:%.*]]
40940 // SIMD-ONLY0:       if.then1385:
40941 // SIMD-ONLY0-NEXT:    [[TMP860:%.*]] = load i8, ptr [[UCD]], align 1
40942 // SIMD-ONLY0-NEXT:    store i8 [[TMP860]], ptr [[UCX]], align 1
40943 // SIMD-ONLY0-NEXT:    br label [[IF_END1386]]
40944 // SIMD-ONLY0:       if.end1386:
40945 // SIMD-ONLY0-NEXT:    [[TMP861:%.*]] = load i8, ptr [[UCX]], align 1
40946 // SIMD-ONLY0-NEXT:    store i8 [[TMP861]], ptr [[UCV]], align 1
40947 // SIMD-ONLY0-NEXT:    [[TMP862:%.*]] = load i8, ptr [[UCX]], align 1
40948 // SIMD-ONLY0-NEXT:    [[CONV1387:%.*]] = zext i8 [[TMP862]] to i32
40949 // SIMD-ONLY0-NEXT:    [[TMP863:%.*]] = load i8, ptr [[UCE]], align 1
40950 // SIMD-ONLY0-NEXT:    [[CONV1388:%.*]] = zext i8 [[TMP863]] to i32
40951 // SIMD-ONLY0-NEXT:    [[CMP1389:%.*]] = icmp eq i32 [[CONV1387]], [[CONV1388]]
40952 // SIMD-ONLY0-NEXT:    br i1 [[CMP1389]], label [[IF_THEN1391:%.*]], label [[IF_ELSE1392:%.*]]
40953 // SIMD-ONLY0:       if.then1391:
40954 // SIMD-ONLY0-NEXT:    [[TMP864:%.*]] = load i8, ptr [[UCD]], align 1
40955 // SIMD-ONLY0-NEXT:    store i8 [[TMP864]], ptr [[UCX]], align 1
40956 // SIMD-ONLY0-NEXT:    br label [[IF_END1393:%.*]]
40957 // SIMD-ONLY0:       if.else1392:
40958 // SIMD-ONLY0-NEXT:    [[TMP865:%.*]] = load i8, ptr [[UCX]], align 1
40959 // SIMD-ONLY0-NEXT:    store i8 [[TMP865]], ptr [[UCV]], align 1
40960 // SIMD-ONLY0-NEXT:    br label [[IF_END1393]]
40961 // SIMD-ONLY0:       if.end1393:
40962 // SIMD-ONLY0-NEXT:    [[TMP866:%.*]] = load i8, ptr [[UCE]], align 1
40963 // SIMD-ONLY0-NEXT:    [[CONV1394:%.*]] = zext i8 [[TMP866]] to i32
40964 // SIMD-ONLY0-NEXT:    [[TMP867:%.*]] = load i8, ptr [[UCX]], align 1
40965 // SIMD-ONLY0-NEXT:    [[CONV1395:%.*]] = zext i8 [[TMP867]] to i32
40966 // SIMD-ONLY0-NEXT:    [[CMP1396:%.*]] = icmp eq i32 [[CONV1394]], [[CONV1395]]
40967 // SIMD-ONLY0-NEXT:    br i1 [[CMP1396]], label [[IF_THEN1398:%.*]], label [[IF_ELSE1399:%.*]]
40968 // SIMD-ONLY0:       if.then1398:
40969 // SIMD-ONLY0-NEXT:    [[TMP868:%.*]] = load i8, ptr [[UCD]], align 1
40970 // SIMD-ONLY0-NEXT:    store i8 [[TMP868]], ptr [[UCX]], align 1
40971 // SIMD-ONLY0-NEXT:    br label [[IF_END1400:%.*]]
40972 // SIMD-ONLY0:       if.else1399:
40973 // SIMD-ONLY0-NEXT:    [[TMP869:%.*]] = load i8, ptr [[UCX]], align 1
40974 // SIMD-ONLY0-NEXT:    store i8 [[TMP869]], ptr [[UCV]], align 1
40975 // SIMD-ONLY0-NEXT:    br label [[IF_END1400]]
40976 // SIMD-ONLY0:       if.end1400:
40977 // SIMD-ONLY0-NEXT:    [[TMP870:%.*]] = load i8, ptr [[UCX]], align 1
40978 // SIMD-ONLY0-NEXT:    [[CONV1401:%.*]] = zext i8 [[TMP870]] to i32
40979 // SIMD-ONLY0-NEXT:    [[TMP871:%.*]] = load i8, ptr [[UCE]], align 1
40980 // SIMD-ONLY0-NEXT:    [[CONV1402:%.*]] = zext i8 [[TMP871]] to i32
40981 // SIMD-ONLY0-NEXT:    [[CMP1403:%.*]] = icmp eq i32 [[CONV1401]], [[CONV1402]]
40982 // SIMD-ONLY0-NEXT:    [[CONV1404:%.*]] = zext i1 [[CMP1403]] to i32
40983 // SIMD-ONLY0-NEXT:    [[CONV1405:%.*]] = trunc i32 [[CONV1404]] to i8
40984 // SIMD-ONLY0-NEXT:    store i8 [[CONV1405]], ptr [[UCR]], align 1
40985 // SIMD-ONLY0-NEXT:    [[TMP872:%.*]] = load i8, ptr [[UCR]], align 1
40986 // SIMD-ONLY0-NEXT:    [[TOBOOL1406:%.*]] = icmp ne i8 [[TMP872]], 0
40987 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1406]], label [[IF_THEN1407:%.*]], label [[IF_END1408:%.*]]
40988 // SIMD-ONLY0:       if.then1407:
40989 // SIMD-ONLY0-NEXT:    [[TMP873:%.*]] = load i8, ptr [[UCD]], align 1
40990 // SIMD-ONLY0-NEXT:    store i8 [[TMP873]], ptr [[UCX]], align 1
40991 // SIMD-ONLY0-NEXT:    br label [[IF_END1408]]
40992 // SIMD-ONLY0:       if.end1408:
40993 // SIMD-ONLY0-NEXT:    [[TMP874:%.*]] = load i8, ptr [[UCE]], align 1
40994 // SIMD-ONLY0-NEXT:    [[CONV1409:%.*]] = zext i8 [[TMP874]] to i32
40995 // SIMD-ONLY0-NEXT:    [[TMP875:%.*]] = load i8, ptr [[UCX]], align 1
40996 // SIMD-ONLY0-NEXT:    [[CONV1410:%.*]] = zext i8 [[TMP875]] to i32
40997 // SIMD-ONLY0-NEXT:    [[CMP1411:%.*]] = icmp eq i32 [[CONV1409]], [[CONV1410]]
40998 // SIMD-ONLY0-NEXT:    [[CONV1412:%.*]] = zext i1 [[CMP1411]] to i32
40999 // SIMD-ONLY0-NEXT:    [[CONV1413:%.*]] = trunc i32 [[CONV1412]] to i8
41000 // SIMD-ONLY0-NEXT:    store i8 [[CONV1413]], ptr [[UCR]], align 1
41001 // SIMD-ONLY0-NEXT:    [[TMP876:%.*]] = load i8, ptr [[UCR]], align 1
41002 // SIMD-ONLY0-NEXT:    [[TOBOOL1414:%.*]] = icmp ne i8 [[TMP876]], 0
41003 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1414]], label [[IF_THEN1415:%.*]], label [[IF_END1416:%.*]]
41004 // SIMD-ONLY0:       if.then1415:
41005 // SIMD-ONLY0-NEXT:    [[TMP877:%.*]] = load i8, ptr [[UCD]], align 1
41006 // SIMD-ONLY0-NEXT:    store i8 [[TMP877]], ptr [[UCX]], align 1
41007 // SIMD-ONLY0-NEXT:    br label [[IF_END1416]]
41008 // SIMD-ONLY0:       if.end1416:
41009 // SIMD-ONLY0-NEXT:    [[TMP878:%.*]] = load i8, ptr [[UCX]], align 1
41010 // SIMD-ONLY0-NEXT:    [[CONV1417:%.*]] = zext i8 [[TMP878]] to i32
41011 // SIMD-ONLY0-NEXT:    [[TMP879:%.*]] = load i8, ptr [[UCE]], align 1
41012 // SIMD-ONLY0-NEXT:    [[CONV1418:%.*]] = zext i8 [[TMP879]] to i32
41013 // SIMD-ONLY0-NEXT:    [[CMP1419:%.*]] = icmp eq i32 [[CONV1417]], [[CONV1418]]
41014 // SIMD-ONLY0-NEXT:    [[CONV1420:%.*]] = zext i1 [[CMP1419]] to i32
41015 // SIMD-ONLY0-NEXT:    [[CONV1421:%.*]] = trunc i32 [[CONV1420]] to i8
41016 // SIMD-ONLY0-NEXT:    store i8 [[CONV1421]], ptr [[UCR]], align 1
41017 // SIMD-ONLY0-NEXT:    [[TMP880:%.*]] = load i8, ptr [[UCR]], align 1
41018 // SIMD-ONLY0-NEXT:    [[TOBOOL1422:%.*]] = icmp ne i8 [[TMP880]], 0
41019 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1422]], label [[IF_THEN1423:%.*]], label [[IF_ELSE1424:%.*]]
41020 // SIMD-ONLY0:       if.then1423:
41021 // SIMD-ONLY0-NEXT:    [[TMP881:%.*]] = load i8, ptr [[UCD]], align 1
41022 // SIMD-ONLY0-NEXT:    store i8 [[TMP881]], ptr [[UCX]], align 1
41023 // SIMD-ONLY0-NEXT:    br label [[IF_END1425:%.*]]
41024 // SIMD-ONLY0:       if.else1424:
41025 // SIMD-ONLY0-NEXT:    [[TMP882:%.*]] = load i8, ptr [[UCX]], align 1
41026 // SIMD-ONLY0-NEXT:    store i8 [[TMP882]], ptr [[UCV]], align 1
41027 // SIMD-ONLY0-NEXT:    br label [[IF_END1425]]
41028 // SIMD-ONLY0:       if.end1425:
41029 // SIMD-ONLY0-NEXT:    [[TMP883:%.*]] = load i8, ptr [[UCE]], align 1
41030 // SIMD-ONLY0-NEXT:    [[CONV1426:%.*]] = zext i8 [[TMP883]] to i32
41031 // SIMD-ONLY0-NEXT:    [[TMP884:%.*]] = load i8, ptr [[UCX]], align 1
41032 // SIMD-ONLY0-NEXT:    [[CONV1427:%.*]] = zext i8 [[TMP884]] to i32
41033 // SIMD-ONLY0-NEXT:    [[CMP1428:%.*]] = icmp eq i32 [[CONV1426]], [[CONV1427]]
41034 // SIMD-ONLY0-NEXT:    [[CONV1429:%.*]] = zext i1 [[CMP1428]] to i32
41035 // SIMD-ONLY0-NEXT:    [[CONV1430:%.*]] = trunc i32 [[CONV1429]] to i8
41036 // SIMD-ONLY0-NEXT:    store i8 [[CONV1430]], ptr [[UCR]], align 1
41037 // SIMD-ONLY0-NEXT:    [[TMP885:%.*]] = load i8, ptr [[UCR]], align 1
41038 // SIMD-ONLY0-NEXT:    [[TOBOOL1431:%.*]] = icmp ne i8 [[TMP885]], 0
41039 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1431]], label [[IF_THEN1432:%.*]], label [[IF_ELSE1433:%.*]]
41040 // SIMD-ONLY0:       if.then1432:
41041 // SIMD-ONLY0-NEXT:    [[TMP886:%.*]] = load i8, ptr [[UCD]], align 1
41042 // SIMD-ONLY0-NEXT:    store i8 [[TMP886]], ptr [[UCX]], align 1
41043 // SIMD-ONLY0-NEXT:    br label [[IF_END1434:%.*]]
41044 // SIMD-ONLY0:       if.else1433:
41045 // SIMD-ONLY0-NEXT:    [[TMP887:%.*]] = load i8, ptr [[UCX]], align 1
41046 // SIMD-ONLY0-NEXT:    store i8 [[TMP887]], ptr [[UCV]], align 1
41047 // SIMD-ONLY0-NEXT:    br label [[IF_END1434]]
41048 // SIMD-ONLY0:       if.end1434:
41049 // SIMD-ONLY0-NEXT:    [[TMP888:%.*]] = load i16, ptr [[SX]], align 2
41050 // SIMD-ONLY0-NEXT:    store i16 [[TMP888]], ptr [[SV]], align 2
41051 // SIMD-ONLY0-NEXT:    [[TMP889:%.*]] = load i16, ptr [[SE]], align 2
41052 // SIMD-ONLY0-NEXT:    [[CONV1435:%.*]] = sext i16 [[TMP889]] to i32
41053 // SIMD-ONLY0-NEXT:    [[TMP890:%.*]] = load i16, ptr [[SX]], align 2
41054 // SIMD-ONLY0-NEXT:    [[CONV1436:%.*]] = sext i16 [[TMP890]] to i32
41055 // SIMD-ONLY0-NEXT:    [[CMP1437:%.*]] = icmp sgt i32 [[CONV1435]], [[CONV1436]]
41056 // SIMD-ONLY0-NEXT:    br i1 [[CMP1437]], label [[IF_THEN1439:%.*]], label [[IF_END1440:%.*]]
41057 // SIMD-ONLY0:       if.then1439:
41058 // SIMD-ONLY0-NEXT:    [[TMP891:%.*]] = load i16, ptr [[SE]], align 2
41059 // SIMD-ONLY0-NEXT:    store i16 [[TMP891]], ptr [[SX]], align 2
41060 // SIMD-ONLY0-NEXT:    br label [[IF_END1440]]
41061 // SIMD-ONLY0:       if.end1440:
41062 // SIMD-ONLY0-NEXT:    [[TMP892:%.*]] = load i16, ptr [[SX]], align 2
41063 // SIMD-ONLY0-NEXT:    store i16 [[TMP892]], ptr [[SV]], align 2
41064 // SIMD-ONLY0-NEXT:    [[TMP893:%.*]] = load i16, ptr [[SX]], align 2
41065 // SIMD-ONLY0-NEXT:    [[CONV1441:%.*]] = sext i16 [[TMP893]] to i32
41066 // SIMD-ONLY0-NEXT:    [[TMP894:%.*]] = load i16, ptr [[SE]], align 2
41067 // SIMD-ONLY0-NEXT:    [[CONV1442:%.*]] = sext i16 [[TMP894]] to i32
41068 // SIMD-ONLY0-NEXT:    [[CMP1443:%.*]] = icmp sgt i32 [[CONV1441]], [[CONV1442]]
41069 // SIMD-ONLY0-NEXT:    br i1 [[CMP1443]], label [[IF_THEN1445:%.*]], label [[IF_END1446:%.*]]
41070 // SIMD-ONLY0:       if.then1445:
41071 // SIMD-ONLY0-NEXT:    [[TMP895:%.*]] = load i16, ptr [[SE]], align 2
41072 // SIMD-ONLY0-NEXT:    store i16 [[TMP895]], ptr [[SX]], align 2
41073 // SIMD-ONLY0-NEXT:    br label [[IF_END1446]]
41074 // SIMD-ONLY0:       if.end1446:
41075 // SIMD-ONLY0-NEXT:    [[TMP896:%.*]] = load i16, ptr [[SX]], align 2
41076 // SIMD-ONLY0-NEXT:    store i16 [[TMP896]], ptr [[SV]], align 2
41077 // SIMD-ONLY0-NEXT:    [[TMP897:%.*]] = load i16, ptr [[SE]], align 2
41078 // SIMD-ONLY0-NEXT:    [[CONV1447:%.*]] = sext i16 [[TMP897]] to i32
41079 // SIMD-ONLY0-NEXT:    [[TMP898:%.*]] = load i16, ptr [[SX]], align 2
41080 // SIMD-ONLY0-NEXT:    [[CONV1448:%.*]] = sext i16 [[TMP898]] to i32
41081 // SIMD-ONLY0-NEXT:    [[CMP1449:%.*]] = icmp slt i32 [[CONV1447]], [[CONV1448]]
41082 // SIMD-ONLY0-NEXT:    br i1 [[CMP1449]], label [[IF_THEN1451:%.*]], label [[IF_END1452:%.*]]
41083 // SIMD-ONLY0:       if.then1451:
41084 // SIMD-ONLY0-NEXT:    [[TMP899:%.*]] = load i16, ptr [[SE]], align 2
41085 // SIMD-ONLY0-NEXT:    store i16 [[TMP899]], ptr [[SX]], align 2
41086 // SIMD-ONLY0-NEXT:    br label [[IF_END1452]]
41087 // SIMD-ONLY0:       if.end1452:
41088 // SIMD-ONLY0-NEXT:    [[TMP900:%.*]] = load i16, ptr [[SX]], align 2
41089 // SIMD-ONLY0-NEXT:    store i16 [[TMP900]], ptr [[SV]], align 2
41090 // SIMD-ONLY0-NEXT:    [[TMP901:%.*]] = load i16, ptr [[SX]], align 2
41091 // SIMD-ONLY0-NEXT:    [[CONV1453:%.*]] = sext i16 [[TMP901]] to i32
41092 // SIMD-ONLY0-NEXT:    [[TMP902:%.*]] = load i16, ptr [[SE]], align 2
41093 // SIMD-ONLY0-NEXT:    [[CONV1454:%.*]] = sext i16 [[TMP902]] to i32
41094 // SIMD-ONLY0-NEXT:    [[CMP1455:%.*]] = icmp slt i32 [[CONV1453]], [[CONV1454]]
41095 // SIMD-ONLY0-NEXT:    br i1 [[CMP1455]], label [[IF_THEN1457:%.*]], label [[IF_END1458:%.*]]
41096 // SIMD-ONLY0:       if.then1457:
41097 // SIMD-ONLY0-NEXT:    [[TMP903:%.*]] = load i16, ptr [[SE]], align 2
41098 // SIMD-ONLY0-NEXT:    store i16 [[TMP903]], ptr [[SX]], align 2
41099 // SIMD-ONLY0-NEXT:    br label [[IF_END1458]]
41100 // SIMD-ONLY0:       if.end1458:
41101 // SIMD-ONLY0-NEXT:    [[TMP904:%.*]] = load i16, ptr [[SX]], align 2
41102 // SIMD-ONLY0-NEXT:    store i16 [[TMP904]], ptr [[SV]], align 2
41103 // SIMD-ONLY0-NEXT:    [[TMP905:%.*]] = load i16, ptr [[SX]], align 2
41104 // SIMD-ONLY0-NEXT:    [[CONV1459:%.*]] = sext i16 [[TMP905]] to i32
41105 // SIMD-ONLY0-NEXT:    [[TMP906:%.*]] = load i16, ptr [[SE]], align 2
41106 // SIMD-ONLY0-NEXT:    [[CONV1460:%.*]] = sext i16 [[TMP906]] to i32
41107 // SIMD-ONLY0-NEXT:    [[CMP1461:%.*]] = icmp eq i32 [[CONV1459]], [[CONV1460]]
41108 // SIMD-ONLY0-NEXT:    br i1 [[CMP1461]], label [[IF_THEN1463:%.*]], label [[IF_END1464:%.*]]
41109 // SIMD-ONLY0:       if.then1463:
41110 // SIMD-ONLY0-NEXT:    [[TMP907:%.*]] = load i16, ptr [[SD]], align 2
41111 // SIMD-ONLY0-NEXT:    store i16 [[TMP907]], ptr [[SX]], align 2
41112 // SIMD-ONLY0-NEXT:    br label [[IF_END1464]]
41113 // SIMD-ONLY0:       if.end1464:
41114 // SIMD-ONLY0-NEXT:    [[TMP908:%.*]] = load i16, ptr [[SX]], align 2
41115 // SIMD-ONLY0-NEXT:    store i16 [[TMP908]], ptr [[SV]], align 2
41116 // SIMD-ONLY0-NEXT:    [[TMP909:%.*]] = load i16, ptr [[SE]], align 2
41117 // SIMD-ONLY0-NEXT:    [[CONV1465:%.*]] = sext i16 [[TMP909]] to i32
41118 // SIMD-ONLY0-NEXT:    [[TMP910:%.*]] = load i16, ptr [[SX]], align 2
41119 // SIMD-ONLY0-NEXT:    [[CONV1466:%.*]] = sext i16 [[TMP910]] to i32
41120 // SIMD-ONLY0-NEXT:    [[CMP1467:%.*]] = icmp eq i32 [[CONV1465]], [[CONV1466]]
41121 // SIMD-ONLY0-NEXT:    br i1 [[CMP1467]], label [[IF_THEN1469:%.*]], label [[IF_END1470:%.*]]
41122 // SIMD-ONLY0:       if.then1469:
41123 // SIMD-ONLY0-NEXT:    [[TMP911:%.*]] = load i16, ptr [[SD]], align 2
41124 // SIMD-ONLY0-NEXT:    store i16 [[TMP911]], ptr [[SX]], align 2
41125 // SIMD-ONLY0-NEXT:    br label [[IF_END1470]]
41126 // SIMD-ONLY0:       if.end1470:
41127 // SIMD-ONLY0-NEXT:    [[TMP912:%.*]] = load i16, ptr [[SE]], align 2
41128 // SIMD-ONLY0-NEXT:    [[CONV1471:%.*]] = sext i16 [[TMP912]] to i32
41129 // SIMD-ONLY0-NEXT:    [[TMP913:%.*]] = load i16, ptr [[SX]], align 2
41130 // SIMD-ONLY0-NEXT:    [[CONV1472:%.*]] = sext i16 [[TMP913]] to i32
41131 // SIMD-ONLY0-NEXT:    [[CMP1473:%.*]] = icmp sgt i32 [[CONV1471]], [[CONV1472]]
41132 // SIMD-ONLY0-NEXT:    br i1 [[CMP1473]], label [[IF_THEN1475:%.*]], label [[IF_END1476:%.*]]
41133 // SIMD-ONLY0:       if.then1475:
41134 // SIMD-ONLY0-NEXT:    [[TMP914:%.*]] = load i16, ptr [[SE]], align 2
41135 // SIMD-ONLY0-NEXT:    store i16 [[TMP914]], ptr [[SX]], align 2
41136 // SIMD-ONLY0-NEXT:    br label [[IF_END1476]]
41137 // SIMD-ONLY0:       if.end1476:
41138 // SIMD-ONLY0-NEXT:    [[TMP915:%.*]] = load i16, ptr [[SX]], align 2
41139 // SIMD-ONLY0-NEXT:    store i16 [[TMP915]], ptr [[SV]], align 2
41140 // SIMD-ONLY0-NEXT:    [[TMP916:%.*]] = load i16, ptr [[SX]], align 2
41141 // SIMD-ONLY0-NEXT:    [[CONV1477:%.*]] = sext i16 [[TMP916]] to i32
41142 // SIMD-ONLY0-NEXT:    [[TMP917:%.*]] = load i16, ptr [[SE]], align 2
41143 // SIMD-ONLY0-NEXT:    [[CONV1478:%.*]] = sext i16 [[TMP917]] to i32
41144 // SIMD-ONLY0-NEXT:    [[CMP1479:%.*]] = icmp sgt i32 [[CONV1477]], [[CONV1478]]
41145 // SIMD-ONLY0-NEXT:    br i1 [[CMP1479]], label [[IF_THEN1481:%.*]], label [[IF_END1482:%.*]]
41146 // SIMD-ONLY0:       if.then1481:
41147 // SIMD-ONLY0-NEXT:    [[TMP918:%.*]] = load i16, ptr [[SE]], align 2
41148 // SIMD-ONLY0-NEXT:    store i16 [[TMP918]], ptr [[SX]], align 2
41149 // SIMD-ONLY0-NEXT:    br label [[IF_END1482]]
41150 // SIMD-ONLY0:       if.end1482:
41151 // SIMD-ONLY0-NEXT:    [[TMP919:%.*]] = load i16, ptr [[SX]], align 2
41152 // SIMD-ONLY0-NEXT:    store i16 [[TMP919]], ptr [[SV]], align 2
41153 // SIMD-ONLY0-NEXT:    [[TMP920:%.*]] = load i16, ptr [[SE]], align 2
41154 // SIMD-ONLY0-NEXT:    [[CONV1483:%.*]] = sext i16 [[TMP920]] to i32
41155 // SIMD-ONLY0-NEXT:    [[TMP921:%.*]] = load i16, ptr [[SX]], align 2
41156 // SIMD-ONLY0-NEXT:    [[CONV1484:%.*]] = sext i16 [[TMP921]] to i32
41157 // SIMD-ONLY0-NEXT:    [[CMP1485:%.*]] = icmp slt i32 [[CONV1483]], [[CONV1484]]
41158 // SIMD-ONLY0-NEXT:    br i1 [[CMP1485]], label [[IF_THEN1487:%.*]], label [[IF_END1488:%.*]]
41159 // SIMD-ONLY0:       if.then1487:
41160 // SIMD-ONLY0-NEXT:    [[TMP922:%.*]] = load i16, ptr [[SE]], align 2
41161 // SIMD-ONLY0-NEXT:    store i16 [[TMP922]], ptr [[SX]], align 2
41162 // SIMD-ONLY0-NEXT:    br label [[IF_END1488]]
41163 // SIMD-ONLY0:       if.end1488:
41164 // SIMD-ONLY0-NEXT:    [[TMP923:%.*]] = load i16, ptr [[SX]], align 2
41165 // SIMD-ONLY0-NEXT:    store i16 [[TMP923]], ptr [[SV]], align 2
41166 // SIMD-ONLY0-NEXT:    [[TMP924:%.*]] = load i16, ptr [[SX]], align 2
41167 // SIMD-ONLY0-NEXT:    [[CONV1489:%.*]] = sext i16 [[TMP924]] to i32
41168 // SIMD-ONLY0-NEXT:    [[TMP925:%.*]] = load i16, ptr [[SE]], align 2
41169 // SIMD-ONLY0-NEXT:    [[CONV1490:%.*]] = sext i16 [[TMP925]] to i32
41170 // SIMD-ONLY0-NEXT:    [[CMP1491:%.*]] = icmp slt i32 [[CONV1489]], [[CONV1490]]
41171 // SIMD-ONLY0-NEXT:    br i1 [[CMP1491]], label [[IF_THEN1493:%.*]], label [[IF_END1494:%.*]]
41172 // SIMD-ONLY0:       if.then1493:
41173 // SIMD-ONLY0-NEXT:    [[TMP926:%.*]] = load i16, ptr [[SE]], align 2
41174 // SIMD-ONLY0-NEXT:    store i16 [[TMP926]], ptr [[SX]], align 2
41175 // SIMD-ONLY0-NEXT:    br label [[IF_END1494]]
41176 // SIMD-ONLY0:       if.end1494:
41177 // SIMD-ONLY0-NEXT:    [[TMP927:%.*]] = load i16, ptr [[SX]], align 2
41178 // SIMD-ONLY0-NEXT:    store i16 [[TMP927]], ptr [[SV]], align 2
41179 // SIMD-ONLY0-NEXT:    [[TMP928:%.*]] = load i16, ptr [[SX]], align 2
41180 // SIMD-ONLY0-NEXT:    [[CONV1495:%.*]] = sext i16 [[TMP928]] to i32
41181 // SIMD-ONLY0-NEXT:    [[TMP929:%.*]] = load i16, ptr [[SE]], align 2
41182 // SIMD-ONLY0-NEXT:    [[CONV1496:%.*]] = sext i16 [[TMP929]] to i32
41183 // SIMD-ONLY0-NEXT:    [[CMP1497:%.*]] = icmp eq i32 [[CONV1495]], [[CONV1496]]
41184 // SIMD-ONLY0-NEXT:    br i1 [[CMP1497]], label [[IF_THEN1499:%.*]], label [[IF_END1500:%.*]]
41185 // SIMD-ONLY0:       if.then1499:
41186 // SIMD-ONLY0-NEXT:    [[TMP930:%.*]] = load i16, ptr [[SD]], align 2
41187 // SIMD-ONLY0-NEXT:    store i16 [[TMP930]], ptr [[SX]], align 2
41188 // SIMD-ONLY0-NEXT:    br label [[IF_END1500]]
41189 // SIMD-ONLY0:       if.end1500:
41190 // SIMD-ONLY0-NEXT:    [[TMP931:%.*]] = load i16, ptr [[SX]], align 2
41191 // SIMD-ONLY0-NEXT:    store i16 [[TMP931]], ptr [[SV]], align 2
41192 // SIMD-ONLY0-NEXT:    [[TMP932:%.*]] = load i16, ptr [[SE]], align 2
41193 // SIMD-ONLY0-NEXT:    [[CONV1501:%.*]] = sext i16 [[TMP932]] to i32
41194 // SIMD-ONLY0-NEXT:    [[TMP933:%.*]] = load i16, ptr [[SX]], align 2
41195 // SIMD-ONLY0-NEXT:    [[CONV1502:%.*]] = sext i16 [[TMP933]] to i32
41196 // SIMD-ONLY0-NEXT:    [[CMP1503:%.*]] = icmp eq i32 [[CONV1501]], [[CONV1502]]
41197 // SIMD-ONLY0-NEXT:    br i1 [[CMP1503]], label [[IF_THEN1505:%.*]], label [[IF_END1506:%.*]]
41198 // SIMD-ONLY0:       if.then1505:
41199 // SIMD-ONLY0-NEXT:    [[TMP934:%.*]] = load i16, ptr [[SD]], align 2
41200 // SIMD-ONLY0-NEXT:    store i16 [[TMP934]], ptr [[SX]], align 2
41201 // SIMD-ONLY0-NEXT:    br label [[IF_END1506]]
41202 // SIMD-ONLY0:       if.end1506:
41203 // SIMD-ONLY0-NEXT:    [[TMP935:%.*]] = load i16, ptr [[SX]], align 2
41204 // SIMD-ONLY0-NEXT:    store i16 [[TMP935]], ptr [[SV]], align 2
41205 // SIMD-ONLY0-NEXT:    [[TMP936:%.*]] = load i16, ptr [[SX]], align 2
41206 // SIMD-ONLY0-NEXT:    [[CONV1507:%.*]] = sext i16 [[TMP936]] to i32
41207 // SIMD-ONLY0-NEXT:    [[TMP937:%.*]] = load i16, ptr [[SE]], align 2
41208 // SIMD-ONLY0-NEXT:    [[CONV1508:%.*]] = sext i16 [[TMP937]] to i32
41209 // SIMD-ONLY0-NEXT:    [[CMP1509:%.*]] = icmp eq i32 [[CONV1507]], [[CONV1508]]
41210 // SIMD-ONLY0-NEXT:    br i1 [[CMP1509]], label [[IF_THEN1511:%.*]], label [[IF_ELSE1512:%.*]]
41211 // SIMD-ONLY0:       if.then1511:
41212 // SIMD-ONLY0-NEXT:    [[TMP938:%.*]] = load i16, ptr [[SD]], align 2
41213 // SIMD-ONLY0-NEXT:    store i16 [[TMP938]], ptr [[SX]], align 2
41214 // SIMD-ONLY0-NEXT:    br label [[IF_END1513:%.*]]
41215 // SIMD-ONLY0:       if.else1512:
41216 // SIMD-ONLY0-NEXT:    [[TMP939:%.*]] = load i16, ptr [[SX]], align 2
41217 // SIMD-ONLY0-NEXT:    store i16 [[TMP939]], ptr [[SV]], align 2
41218 // SIMD-ONLY0-NEXT:    br label [[IF_END1513]]
41219 // SIMD-ONLY0:       if.end1513:
41220 // SIMD-ONLY0-NEXT:    [[TMP940:%.*]] = load i16, ptr [[SE]], align 2
41221 // SIMD-ONLY0-NEXT:    [[CONV1514:%.*]] = sext i16 [[TMP940]] to i32
41222 // SIMD-ONLY0-NEXT:    [[TMP941:%.*]] = load i16, ptr [[SX]], align 2
41223 // SIMD-ONLY0-NEXT:    [[CONV1515:%.*]] = sext i16 [[TMP941]] to i32
41224 // SIMD-ONLY0-NEXT:    [[CMP1516:%.*]] = icmp eq i32 [[CONV1514]], [[CONV1515]]
41225 // SIMD-ONLY0-NEXT:    br i1 [[CMP1516]], label [[IF_THEN1518:%.*]], label [[IF_ELSE1519:%.*]]
41226 // SIMD-ONLY0:       if.then1518:
41227 // SIMD-ONLY0-NEXT:    [[TMP942:%.*]] = load i16, ptr [[SD]], align 2
41228 // SIMD-ONLY0-NEXT:    store i16 [[TMP942]], ptr [[SX]], align 2
41229 // SIMD-ONLY0-NEXT:    br label [[IF_END1520:%.*]]
41230 // SIMD-ONLY0:       if.else1519:
41231 // SIMD-ONLY0-NEXT:    [[TMP943:%.*]] = load i16, ptr [[SX]], align 2
41232 // SIMD-ONLY0-NEXT:    store i16 [[TMP943]], ptr [[SV]], align 2
41233 // SIMD-ONLY0-NEXT:    br label [[IF_END1520]]
41234 // SIMD-ONLY0:       if.end1520:
41235 // SIMD-ONLY0-NEXT:    [[TMP944:%.*]] = load i16, ptr [[SX]], align 2
41236 // SIMD-ONLY0-NEXT:    [[CONV1521:%.*]] = sext i16 [[TMP944]] to i32
41237 // SIMD-ONLY0-NEXT:    [[TMP945:%.*]] = load i16, ptr [[SE]], align 2
41238 // SIMD-ONLY0-NEXT:    [[CONV1522:%.*]] = sext i16 [[TMP945]] to i32
41239 // SIMD-ONLY0-NEXT:    [[CMP1523:%.*]] = icmp eq i32 [[CONV1521]], [[CONV1522]]
41240 // SIMD-ONLY0-NEXT:    [[CONV1524:%.*]] = zext i1 [[CMP1523]] to i32
41241 // SIMD-ONLY0-NEXT:    [[CONV1525:%.*]] = trunc i32 [[CONV1524]] to i16
41242 // SIMD-ONLY0-NEXT:    store i16 [[CONV1525]], ptr [[SR]], align 2
41243 // SIMD-ONLY0-NEXT:    [[TMP946:%.*]] = load i16, ptr [[SR]], align 2
41244 // SIMD-ONLY0-NEXT:    [[TOBOOL1526:%.*]] = icmp ne i16 [[TMP946]], 0
41245 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1526]], label [[IF_THEN1527:%.*]], label [[IF_END1528:%.*]]
41246 // SIMD-ONLY0:       if.then1527:
41247 // SIMD-ONLY0-NEXT:    [[TMP947:%.*]] = load i16, ptr [[SD]], align 2
41248 // SIMD-ONLY0-NEXT:    store i16 [[TMP947]], ptr [[SX]], align 2
41249 // SIMD-ONLY0-NEXT:    br label [[IF_END1528]]
41250 // SIMD-ONLY0:       if.end1528:
41251 // SIMD-ONLY0-NEXT:    [[TMP948:%.*]] = load i16, ptr [[SE]], align 2
41252 // SIMD-ONLY0-NEXT:    [[CONV1529:%.*]] = sext i16 [[TMP948]] to i32
41253 // SIMD-ONLY0-NEXT:    [[TMP949:%.*]] = load i16, ptr [[SX]], align 2
41254 // SIMD-ONLY0-NEXT:    [[CONV1530:%.*]] = sext i16 [[TMP949]] to i32
41255 // SIMD-ONLY0-NEXT:    [[CMP1531:%.*]] = icmp eq i32 [[CONV1529]], [[CONV1530]]
41256 // SIMD-ONLY0-NEXT:    [[CONV1532:%.*]] = zext i1 [[CMP1531]] to i32
41257 // SIMD-ONLY0-NEXT:    [[CONV1533:%.*]] = trunc i32 [[CONV1532]] to i16
41258 // SIMD-ONLY0-NEXT:    store i16 [[CONV1533]], ptr [[SR]], align 2
41259 // SIMD-ONLY0-NEXT:    [[TMP950:%.*]] = load i16, ptr [[SR]], align 2
41260 // SIMD-ONLY0-NEXT:    [[TOBOOL1534:%.*]] = icmp ne i16 [[TMP950]], 0
41261 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1534]], label [[IF_THEN1535:%.*]], label [[IF_END1536:%.*]]
41262 // SIMD-ONLY0:       if.then1535:
41263 // SIMD-ONLY0-NEXT:    [[TMP951:%.*]] = load i16, ptr [[SD]], align 2
41264 // SIMD-ONLY0-NEXT:    store i16 [[TMP951]], ptr [[SX]], align 2
41265 // SIMD-ONLY0-NEXT:    br label [[IF_END1536]]
41266 // SIMD-ONLY0:       if.end1536:
41267 // SIMD-ONLY0-NEXT:    [[TMP952:%.*]] = load i16, ptr [[SX]], align 2
41268 // SIMD-ONLY0-NEXT:    [[CONV1537:%.*]] = sext i16 [[TMP952]] to i32
41269 // SIMD-ONLY0-NEXT:    [[TMP953:%.*]] = load i16, ptr [[SE]], align 2
41270 // SIMD-ONLY0-NEXT:    [[CONV1538:%.*]] = sext i16 [[TMP953]] to i32
41271 // SIMD-ONLY0-NEXT:    [[CMP1539:%.*]] = icmp eq i32 [[CONV1537]], [[CONV1538]]
41272 // SIMD-ONLY0-NEXT:    [[CONV1540:%.*]] = zext i1 [[CMP1539]] to i32
41273 // SIMD-ONLY0-NEXT:    [[CONV1541:%.*]] = trunc i32 [[CONV1540]] to i16
41274 // SIMD-ONLY0-NEXT:    store i16 [[CONV1541]], ptr [[SR]], align 2
41275 // SIMD-ONLY0-NEXT:    [[TMP954:%.*]] = load i16, ptr [[SR]], align 2
41276 // SIMD-ONLY0-NEXT:    [[TOBOOL1542:%.*]] = icmp ne i16 [[TMP954]], 0
41277 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1542]], label [[IF_THEN1543:%.*]], label [[IF_ELSE1544:%.*]]
41278 // SIMD-ONLY0:       if.then1543:
41279 // SIMD-ONLY0-NEXT:    [[TMP955:%.*]] = load i16, ptr [[SD]], align 2
41280 // SIMD-ONLY0-NEXT:    store i16 [[TMP955]], ptr [[SX]], align 2
41281 // SIMD-ONLY0-NEXT:    br label [[IF_END1545:%.*]]
41282 // SIMD-ONLY0:       if.else1544:
41283 // SIMD-ONLY0-NEXT:    [[TMP956:%.*]] = load i16, ptr [[SX]], align 2
41284 // SIMD-ONLY0-NEXT:    store i16 [[TMP956]], ptr [[SV]], align 2
41285 // SIMD-ONLY0-NEXT:    br label [[IF_END1545]]
41286 // SIMD-ONLY0:       if.end1545:
41287 // SIMD-ONLY0-NEXT:    [[TMP957:%.*]] = load i16, ptr [[SE]], align 2
41288 // SIMD-ONLY0-NEXT:    [[CONV1546:%.*]] = sext i16 [[TMP957]] to i32
41289 // SIMD-ONLY0-NEXT:    [[TMP958:%.*]] = load i16, ptr [[SX]], align 2
41290 // SIMD-ONLY0-NEXT:    [[CONV1547:%.*]] = sext i16 [[TMP958]] to i32
41291 // SIMD-ONLY0-NEXT:    [[CMP1548:%.*]] = icmp eq i32 [[CONV1546]], [[CONV1547]]
41292 // SIMD-ONLY0-NEXT:    [[CONV1549:%.*]] = zext i1 [[CMP1548]] to i32
41293 // SIMD-ONLY0-NEXT:    [[CONV1550:%.*]] = trunc i32 [[CONV1549]] to i16
41294 // SIMD-ONLY0-NEXT:    store i16 [[CONV1550]], ptr [[SR]], align 2
41295 // SIMD-ONLY0-NEXT:    [[TMP959:%.*]] = load i16, ptr [[SR]], align 2
41296 // SIMD-ONLY0-NEXT:    [[TOBOOL1551:%.*]] = icmp ne i16 [[TMP959]], 0
41297 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1551]], label [[IF_THEN1552:%.*]], label [[IF_ELSE1553:%.*]]
41298 // SIMD-ONLY0:       if.then1552:
41299 // SIMD-ONLY0-NEXT:    [[TMP960:%.*]] = load i16, ptr [[SD]], align 2
41300 // SIMD-ONLY0-NEXT:    store i16 [[TMP960]], ptr [[SX]], align 2
41301 // SIMD-ONLY0-NEXT:    br label [[IF_END1554:%.*]]
41302 // SIMD-ONLY0:       if.else1553:
41303 // SIMD-ONLY0-NEXT:    [[TMP961:%.*]] = load i16, ptr [[SX]], align 2
41304 // SIMD-ONLY0-NEXT:    store i16 [[TMP961]], ptr [[SV]], align 2
41305 // SIMD-ONLY0-NEXT:    br label [[IF_END1554]]
41306 // SIMD-ONLY0:       if.end1554:
41307 // SIMD-ONLY0-NEXT:    [[TMP962:%.*]] = load i16, ptr [[SX]], align 2
41308 // SIMD-ONLY0-NEXT:    store i16 [[TMP962]], ptr [[SV]], align 2
41309 // SIMD-ONLY0-NEXT:    [[TMP963:%.*]] = load i16, ptr [[SE]], align 2
41310 // SIMD-ONLY0-NEXT:    [[CONV1555:%.*]] = sext i16 [[TMP963]] to i32
41311 // SIMD-ONLY0-NEXT:    [[TMP964:%.*]] = load i16, ptr [[SX]], align 2
41312 // SIMD-ONLY0-NEXT:    [[CONV1556:%.*]] = sext i16 [[TMP964]] to i32
41313 // SIMD-ONLY0-NEXT:    [[CMP1557:%.*]] = icmp sgt i32 [[CONV1555]], [[CONV1556]]
41314 // SIMD-ONLY0-NEXT:    br i1 [[CMP1557]], label [[IF_THEN1559:%.*]], label [[IF_END1560:%.*]]
41315 // SIMD-ONLY0:       if.then1559:
41316 // SIMD-ONLY0-NEXT:    [[TMP965:%.*]] = load i16, ptr [[SE]], align 2
41317 // SIMD-ONLY0-NEXT:    store i16 [[TMP965]], ptr [[SX]], align 2
41318 // SIMD-ONLY0-NEXT:    br label [[IF_END1560]]
41319 // SIMD-ONLY0:       if.end1560:
41320 // SIMD-ONLY0-NEXT:    [[TMP966:%.*]] = load i16, ptr [[SX]], align 2
41321 // SIMD-ONLY0-NEXT:    store i16 [[TMP966]], ptr [[SV]], align 2
41322 // SIMD-ONLY0-NEXT:    [[TMP967:%.*]] = load i16, ptr [[SX]], align 2
41323 // SIMD-ONLY0-NEXT:    [[CONV1561:%.*]] = sext i16 [[TMP967]] to i32
41324 // SIMD-ONLY0-NEXT:    [[TMP968:%.*]] = load i16, ptr [[SE]], align 2
41325 // SIMD-ONLY0-NEXT:    [[CONV1562:%.*]] = sext i16 [[TMP968]] to i32
41326 // SIMD-ONLY0-NEXT:    [[CMP1563:%.*]] = icmp sgt i32 [[CONV1561]], [[CONV1562]]
41327 // SIMD-ONLY0-NEXT:    br i1 [[CMP1563]], label [[IF_THEN1565:%.*]], label [[IF_END1566:%.*]]
41328 // SIMD-ONLY0:       if.then1565:
41329 // SIMD-ONLY0-NEXT:    [[TMP969:%.*]] = load i16, ptr [[SE]], align 2
41330 // SIMD-ONLY0-NEXT:    store i16 [[TMP969]], ptr [[SX]], align 2
41331 // SIMD-ONLY0-NEXT:    br label [[IF_END1566]]
41332 // SIMD-ONLY0:       if.end1566:
41333 // SIMD-ONLY0-NEXT:    [[TMP970:%.*]] = load i16, ptr [[SX]], align 2
41334 // SIMD-ONLY0-NEXT:    store i16 [[TMP970]], ptr [[SV]], align 2
41335 // SIMD-ONLY0-NEXT:    [[TMP971:%.*]] = load i16, ptr [[SE]], align 2
41336 // SIMD-ONLY0-NEXT:    [[CONV1567:%.*]] = sext i16 [[TMP971]] to i32
41337 // SIMD-ONLY0-NEXT:    [[TMP972:%.*]] = load i16, ptr [[SX]], align 2
41338 // SIMD-ONLY0-NEXT:    [[CONV1568:%.*]] = sext i16 [[TMP972]] to i32
41339 // SIMD-ONLY0-NEXT:    [[CMP1569:%.*]] = icmp slt i32 [[CONV1567]], [[CONV1568]]
41340 // SIMD-ONLY0-NEXT:    br i1 [[CMP1569]], label [[IF_THEN1571:%.*]], label [[IF_END1572:%.*]]
41341 // SIMD-ONLY0:       if.then1571:
41342 // SIMD-ONLY0-NEXT:    [[TMP973:%.*]] = load i16, ptr [[SE]], align 2
41343 // SIMD-ONLY0-NEXT:    store i16 [[TMP973]], ptr [[SX]], align 2
41344 // SIMD-ONLY0-NEXT:    br label [[IF_END1572]]
41345 // SIMD-ONLY0:       if.end1572:
41346 // SIMD-ONLY0-NEXT:    [[TMP974:%.*]] = load i16, ptr [[SX]], align 2
41347 // SIMD-ONLY0-NEXT:    store i16 [[TMP974]], ptr [[SV]], align 2
41348 // SIMD-ONLY0-NEXT:    [[TMP975:%.*]] = load i16, ptr [[SX]], align 2
41349 // SIMD-ONLY0-NEXT:    [[CONV1573:%.*]] = sext i16 [[TMP975]] to i32
41350 // SIMD-ONLY0-NEXT:    [[TMP976:%.*]] = load i16, ptr [[SE]], align 2
41351 // SIMD-ONLY0-NEXT:    [[CONV1574:%.*]] = sext i16 [[TMP976]] to i32
41352 // SIMD-ONLY0-NEXT:    [[CMP1575:%.*]] = icmp slt i32 [[CONV1573]], [[CONV1574]]
41353 // SIMD-ONLY0-NEXT:    br i1 [[CMP1575]], label [[IF_THEN1577:%.*]], label [[IF_END1578:%.*]]
41354 // SIMD-ONLY0:       if.then1577:
41355 // SIMD-ONLY0-NEXT:    [[TMP977:%.*]] = load i16, ptr [[SE]], align 2
41356 // SIMD-ONLY0-NEXT:    store i16 [[TMP977]], ptr [[SX]], align 2
41357 // SIMD-ONLY0-NEXT:    br label [[IF_END1578]]
41358 // SIMD-ONLY0:       if.end1578:
41359 // SIMD-ONLY0-NEXT:    [[TMP978:%.*]] = load i16, ptr [[SX]], align 2
41360 // SIMD-ONLY0-NEXT:    store i16 [[TMP978]], ptr [[SV]], align 2
41361 // SIMD-ONLY0-NEXT:    [[TMP979:%.*]] = load i16, ptr [[SX]], align 2
41362 // SIMD-ONLY0-NEXT:    [[CONV1579:%.*]] = sext i16 [[TMP979]] to i32
41363 // SIMD-ONLY0-NEXT:    [[TMP980:%.*]] = load i16, ptr [[SE]], align 2
41364 // SIMD-ONLY0-NEXT:    [[CONV1580:%.*]] = sext i16 [[TMP980]] to i32
41365 // SIMD-ONLY0-NEXT:    [[CMP1581:%.*]] = icmp eq i32 [[CONV1579]], [[CONV1580]]
41366 // SIMD-ONLY0-NEXT:    br i1 [[CMP1581]], label [[IF_THEN1583:%.*]], label [[IF_END1584:%.*]]
41367 // SIMD-ONLY0:       if.then1583:
41368 // SIMD-ONLY0-NEXT:    [[TMP981:%.*]] = load i16, ptr [[SD]], align 2
41369 // SIMD-ONLY0-NEXT:    store i16 [[TMP981]], ptr [[SX]], align 2
41370 // SIMD-ONLY0-NEXT:    br label [[IF_END1584]]
41371 // SIMD-ONLY0:       if.end1584:
41372 // SIMD-ONLY0-NEXT:    [[TMP982:%.*]] = load i16, ptr [[SX]], align 2
41373 // SIMD-ONLY0-NEXT:    store i16 [[TMP982]], ptr [[SV]], align 2
41374 // SIMD-ONLY0-NEXT:    [[TMP983:%.*]] = load i16, ptr [[SE]], align 2
41375 // SIMD-ONLY0-NEXT:    [[CONV1585:%.*]] = sext i16 [[TMP983]] to i32
41376 // SIMD-ONLY0-NEXT:    [[TMP984:%.*]] = load i16, ptr [[SX]], align 2
41377 // SIMD-ONLY0-NEXT:    [[CONV1586:%.*]] = sext i16 [[TMP984]] to i32
41378 // SIMD-ONLY0-NEXT:    [[CMP1587:%.*]] = icmp eq i32 [[CONV1585]], [[CONV1586]]
41379 // SIMD-ONLY0-NEXT:    br i1 [[CMP1587]], label [[IF_THEN1589:%.*]], label [[IF_END1590:%.*]]
41380 // SIMD-ONLY0:       if.then1589:
41381 // SIMD-ONLY0-NEXT:    [[TMP985:%.*]] = load i16, ptr [[SD]], align 2
41382 // SIMD-ONLY0-NEXT:    store i16 [[TMP985]], ptr [[SX]], align 2
41383 // SIMD-ONLY0-NEXT:    br label [[IF_END1590]]
41384 // SIMD-ONLY0:       if.end1590:
41385 // SIMD-ONLY0-NEXT:    [[TMP986:%.*]] = load i16, ptr [[SE]], align 2
41386 // SIMD-ONLY0-NEXT:    [[CONV1591:%.*]] = sext i16 [[TMP986]] to i32
41387 // SIMD-ONLY0-NEXT:    [[TMP987:%.*]] = load i16, ptr [[SX]], align 2
41388 // SIMD-ONLY0-NEXT:    [[CONV1592:%.*]] = sext i16 [[TMP987]] to i32
41389 // SIMD-ONLY0-NEXT:    [[CMP1593:%.*]] = icmp sgt i32 [[CONV1591]], [[CONV1592]]
41390 // SIMD-ONLY0-NEXT:    br i1 [[CMP1593]], label [[IF_THEN1595:%.*]], label [[IF_END1596:%.*]]
41391 // SIMD-ONLY0:       if.then1595:
41392 // SIMD-ONLY0-NEXT:    [[TMP988:%.*]] = load i16, ptr [[SE]], align 2
41393 // SIMD-ONLY0-NEXT:    store i16 [[TMP988]], ptr [[SX]], align 2
41394 // SIMD-ONLY0-NEXT:    br label [[IF_END1596]]
41395 // SIMD-ONLY0:       if.end1596:
41396 // SIMD-ONLY0-NEXT:    [[TMP989:%.*]] = load i16, ptr [[SX]], align 2
41397 // SIMD-ONLY0-NEXT:    store i16 [[TMP989]], ptr [[SV]], align 2
41398 // SIMD-ONLY0-NEXT:    [[TMP990:%.*]] = load i16, ptr [[SX]], align 2
41399 // SIMD-ONLY0-NEXT:    [[CONV1597:%.*]] = sext i16 [[TMP990]] to i32
41400 // SIMD-ONLY0-NEXT:    [[TMP991:%.*]] = load i16, ptr [[SE]], align 2
41401 // SIMD-ONLY0-NEXT:    [[CONV1598:%.*]] = sext i16 [[TMP991]] to i32
41402 // SIMD-ONLY0-NEXT:    [[CMP1599:%.*]] = icmp sgt i32 [[CONV1597]], [[CONV1598]]
41403 // SIMD-ONLY0-NEXT:    br i1 [[CMP1599]], label [[IF_THEN1601:%.*]], label [[IF_END1602:%.*]]
41404 // SIMD-ONLY0:       if.then1601:
41405 // SIMD-ONLY0-NEXT:    [[TMP992:%.*]] = load i16, ptr [[SE]], align 2
41406 // SIMD-ONLY0-NEXT:    store i16 [[TMP992]], ptr [[SX]], align 2
41407 // SIMD-ONLY0-NEXT:    br label [[IF_END1602]]
41408 // SIMD-ONLY0:       if.end1602:
41409 // SIMD-ONLY0-NEXT:    [[TMP993:%.*]] = load i16, ptr [[SX]], align 2
41410 // SIMD-ONLY0-NEXT:    store i16 [[TMP993]], ptr [[SV]], align 2
41411 // SIMD-ONLY0-NEXT:    [[TMP994:%.*]] = load i16, ptr [[SE]], align 2
41412 // SIMD-ONLY0-NEXT:    [[CONV1603:%.*]] = sext i16 [[TMP994]] to i32
41413 // SIMD-ONLY0-NEXT:    [[TMP995:%.*]] = load i16, ptr [[SX]], align 2
41414 // SIMD-ONLY0-NEXT:    [[CONV1604:%.*]] = sext i16 [[TMP995]] to i32
41415 // SIMD-ONLY0-NEXT:    [[CMP1605:%.*]] = icmp slt i32 [[CONV1603]], [[CONV1604]]
41416 // SIMD-ONLY0-NEXT:    br i1 [[CMP1605]], label [[IF_THEN1607:%.*]], label [[IF_END1608:%.*]]
41417 // SIMD-ONLY0:       if.then1607:
41418 // SIMD-ONLY0-NEXT:    [[TMP996:%.*]] = load i16, ptr [[SE]], align 2
41419 // SIMD-ONLY0-NEXT:    store i16 [[TMP996]], ptr [[SX]], align 2
41420 // SIMD-ONLY0-NEXT:    br label [[IF_END1608]]
41421 // SIMD-ONLY0:       if.end1608:
41422 // SIMD-ONLY0-NEXT:    [[TMP997:%.*]] = load i16, ptr [[SX]], align 2
41423 // SIMD-ONLY0-NEXT:    store i16 [[TMP997]], ptr [[SV]], align 2
41424 // SIMD-ONLY0-NEXT:    [[TMP998:%.*]] = load i16, ptr [[SX]], align 2
41425 // SIMD-ONLY0-NEXT:    [[CONV1609:%.*]] = sext i16 [[TMP998]] to i32
41426 // SIMD-ONLY0-NEXT:    [[TMP999:%.*]] = load i16, ptr [[SE]], align 2
41427 // SIMD-ONLY0-NEXT:    [[CONV1610:%.*]] = sext i16 [[TMP999]] to i32
41428 // SIMD-ONLY0-NEXT:    [[CMP1611:%.*]] = icmp slt i32 [[CONV1609]], [[CONV1610]]
41429 // SIMD-ONLY0-NEXT:    br i1 [[CMP1611]], label [[IF_THEN1613:%.*]], label [[IF_END1614:%.*]]
41430 // SIMD-ONLY0:       if.then1613:
41431 // SIMD-ONLY0-NEXT:    [[TMP1000:%.*]] = load i16, ptr [[SE]], align 2
41432 // SIMD-ONLY0-NEXT:    store i16 [[TMP1000]], ptr [[SX]], align 2
41433 // SIMD-ONLY0-NEXT:    br label [[IF_END1614]]
41434 // SIMD-ONLY0:       if.end1614:
41435 // SIMD-ONLY0-NEXT:    [[TMP1001:%.*]] = load i16, ptr [[SX]], align 2
41436 // SIMD-ONLY0-NEXT:    store i16 [[TMP1001]], ptr [[SV]], align 2
41437 // SIMD-ONLY0-NEXT:    [[TMP1002:%.*]] = load i16, ptr [[SX]], align 2
41438 // SIMD-ONLY0-NEXT:    [[CONV1615:%.*]] = sext i16 [[TMP1002]] to i32
41439 // SIMD-ONLY0-NEXT:    [[TMP1003:%.*]] = load i16, ptr [[SE]], align 2
41440 // SIMD-ONLY0-NEXT:    [[CONV1616:%.*]] = sext i16 [[TMP1003]] to i32
41441 // SIMD-ONLY0-NEXT:    [[CMP1617:%.*]] = icmp eq i32 [[CONV1615]], [[CONV1616]]
41442 // SIMD-ONLY0-NEXT:    br i1 [[CMP1617]], label [[IF_THEN1619:%.*]], label [[IF_END1620:%.*]]
41443 // SIMD-ONLY0:       if.then1619:
41444 // SIMD-ONLY0-NEXT:    [[TMP1004:%.*]] = load i16, ptr [[SD]], align 2
41445 // SIMD-ONLY0-NEXT:    store i16 [[TMP1004]], ptr [[SX]], align 2
41446 // SIMD-ONLY0-NEXT:    br label [[IF_END1620]]
41447 // SIMD-ONLY0:       if.end1620:
41448 // SIMD-ONLY0-NEXT:    [[TMP1005:%.*]] = load i16, ptr [[SX]], align 2
41449 // SIMD-ONLY0-NEXT:    store i16 [[TMP1005]], ptr [[SV]], align 2
41450 // SIMD-ONLY0-NEXT:    [[TMP1006:%.*]] = load i16, ptr [[SE]], align 2
41451 // SIMD-ONLY0-NEXT:    [[CONV1621:%.*]] = sext i16 [[TMP1006]] to i32
41452 // SIMD-ONLY0-NEXT:    [[TMP1007:%.*]] = load i16, ptr [[SX]], align 2
41453 // SIMD-ONLY0-NEXT:    [[CONV1622:%.*]] = sext i16 [[TMP1007]] to i32
41454 // SIMD-ONLY0-NEXT:    [[CMP1623:%.*]] = icmp eq i32 [[CONV1621]], [[CONV1622]]
41455 // SIMD-ONLY0-NEXT:    br i1 [[CMP1623]], label [[IF_THEN1625:%.*]], label [[IF_END1626:%.*]]
41456 // SIMD-ONLY0:       if.then1625:
41457 // SIMD-ONLY0-NEXT:    [[TMP1008:%.*]] = load i16, ptr [[SD]], align 2
41458 // SIMD-ONLY0-NEXT:    store i16 [[TMP1008]], ptr [[SX]], align 2
41459 // SIMD-ONLY0-NEXT:    br label [[IF_END1626]]
41460 // SIMD-ONLY0:       if.end1626:
41461 // SIMD-ONLY0-NEXT:    [[TMP1009:%.*]] = load i16, ptr [[SX]], align 2
41462 // SIMD-ONLY0-NEXT:    store i16 [[TMP1009]], ptr [[SV]], align 2
41463 // SIMD-ONLY0-NEXT:    [[TMP1010:%.*]] = load i16, ptr [[SX]], align 2
41464 // SIMD-ONLY0-NEXT:    [[CONV1627:%.*]] = sext i16 [[TMP1010]] to i32
41465 // SIMD-ONLY0-NEXT:    [[TMP1011:%.*]] = load i16, ptr [[SE]], align 2
41466 // SIMD-ONLY0-NEXT:    [[CONV1628:%.*]] = sext i16 [[TMP1011]] to i32
41467 // SIMD-ONLY0-NEXT:    [[CMP1629:%.*]] = icmp eq i32 [[CONV1627]], [[CONV1628]]
41468 // SIMD-ONLY0-NEXT:    br i1 [[CMP1629]], label [[IF_THEN1631:%.*]], label [[IF_ELSE1632:%.*]]
41469 // SIMD-ONLY0:       if.then1631:
41470 // SIMD-ONLY0-NEXT:    [[TMP1012:%.*]] = load i16, ptr [[SD]], align 2
41471 // SIMD-ONLY0-NEXT:    store i16 [[TMP1012]], ptr [[SX]], align 2
41472 // SIMD-ONLY0-NEXT:    br label [[IF_END1633:%.*]]
41473 // SIMD-ONLY0:       if.else1632:
41474 // SIMD-ONLY0-NEXT:    [[TMP1013:%.*]] = load i16, ptr [[SX]], align 2
41475 // SIMD-ONLY0-NEXT:    store i16 [[TMP1013]], ptr [[SV]], align 2
41476 // SIMD-ONLY0-NEXT:    br label [[IF_END1633]]
41477 // SIMD-ONLY0:       if.end1633:
41478 // SIMD-ONLY0-NEXT:    [[TMP1014:%.*]] = load i16, ptr [[SE]], align 2
41479 // SIMD-ONLY0-NEXT:    [[CONV1634:%.*]] = sext i16 [[TMP1014]] to i32
41480 // SIMD-ONLY0-NEXT:    [[TMP1015:%.*]] = load i16, ptr [[SX]], align 2
41481 // SIMD-ONLY0-NEXT:    [[CONV1635:%.*]] = sext i16 [[TMP1015]] to i32
41482 // SIMD-ONLY0-NEXT:    [[CMP1636:%.*]] = icmp eq i32 [[CONV1634]], [[CONV1635]]
41483 // SIMD-ONLY0-NEXT:    br i1 [[CMP1636]], label [[IF_THEN1638:%.*]], label [[IF_ELSE1639:%.*]]
41484 // SIMD-ONLY0:       if.then1638:
41485 // SIMD-ONLY0-NEXT:    [[TMP1016:%.*]] = load i16, ptr [[SD]], align 2
41486 // SIMD-ONLY0-NEXT:    store i16 [[TMP1016]], ptr [[SX]], align 2
41487 // SIMD-ONLY0-NEXT:    br label [[IF_END1640:%.*]]
41488 // SIMD-ONLY0:       if.else1639:
41489 // SIMD-ONLY0-NEXT:    [[TMP1017:%.*]] = load i16, ptr [[SX]], align 2
41490 // SIMD-ONLY0-NEXT:    store i16 [[TMP1017]], ptr [[SV]], align 2
41491 // SIMD-ONLY0-NEXT:    br label [[IF_END1640]]
41492 // SIMD-ONLY0:       if.end1640:
41493 // SIMD-ONLY0-NEXT:    [[TMP1018:%.*]] = load i16, ptr [[SX]], align 2
41494 // SIMD-ONLY0-NEXT:    [[CONV1641:%.*]] = sext i16 [[TMP1018]] to i32
41495 // SIMD-ONLY0-NEXT:    [[TMP1019:%.*]] = load i16, ptr [[SE]], align 2
41496 // SIMD-ONLY0-NEXT:    [[CONV1642:%.*]] = sext i16 [[TMP1019]] to i32
41497 // SIMD-ONLY0-NEXT:    [[CMP1643:%.*]] = icmp eq i32 [[CONV1641]], [[CONV1642]]
41498 // SIMD-ONLY0-NEXT:    [[CONV1644:%.*]] = zext i1 [[CMP1643]] to i32
41499 // SIMD-ONLY0-NEXT:    [[CONV1645:%.*]] = trunc i32 [[CONV1644]] to i16
41500 // SIMD-ONLY0-NEXT:    store i16 [[CONV1645]], ptr [[SR]], align 2
41501 // SIMD-ONLY0-NEXT:    [[TMP1020:%.*]] = load i16, ptr [[SR]], align 2
41502 // SIMD-ONLY0-NEXT:    [[TOBOOL1646:%.*]] = icmp ne i16 [[TMP1020]], 0
41503 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1646]], label [[IF_THEN1647:%.*]], label [[IF_END1648:%.*]]
41504 // SIMD-ONLY0:       if.then1647:
41505 // SIMD-ONLY0-NEXT:    [[TMP1021:%.*]] = load i16, ptr [[SD]], align 2
41506 // SIMD-ONLY0-NEXT:    store i16 [[TMP1021]], ptr [[SX]], align 2
41507 // SIMD-ONLY0-NEXT:    br label [[IF_END1648]]
41508 // SIMD-ONLY0:       if.end1648:
41509 // SIMD-ONLY0-NEXT:    [[TMP1022:%.*]] = load i16, ptr [[SE]], align 2
41510 // SIMD-ONLY0-NEXT:    [[CONV1649:%.*]] = sext i16 [[TMP1022]] to i32
41511 // SIMD-ONLY0-NEXT:    [[TMP1023:%.*]] = load i16, ptr [[SX]], align 2
41512 // SIMD-ONLY0-NEXT:    [[CONV1650:%.*]] = sext i16 [[TMP1023]] to i32
41513 // SIMD-ONLY0-NEXT:    [[CMP1651:%.*]] = icmp eq i32 [[CONV1649]], [[CONV1650]]
41514 // SIMD-ONLY0-NEXT:    [[CONV1652:%.*]] = zext i1 [[CMP1651]] to i32
41515 // SIMD-ONLY0-NEXT:    [[CONV1653:%.*]] = trunc i32 [[CONV1652]] to i16
41516 // SIMD-ONLY0-NEXT:    store i16 [[CONV1653]], ptr [[SR]], align 2
41517 // SIMD-ONLY0-NEXT:    [[TMP1024:%.*]] = load i16, ptr [[SR]], align 2
41518 // SIMD-ONLY0-NEXT:    [[TOBOOL1654:%.*]] = icmp ne i16 [[TMP1024]], 0
41519 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1654]], label [[IF_THEN1655:%.*]], label [[IF_END1656:%.*]]
41520 // SIMD-ONLY0:       if.then1655:
41521 // SIMD-ONLY0-NEXT:    [[TMP1025:%.*]] = load i16, ptr [[SD]], align 2
41522 // SIMD-ONLY0-NEXT:    store i16 [[TMP1025]], ptr [[SX]], align 2
41523 // SIMD-ONLY0-NEXT:    br label [[IF_END1656]]
41524 // SIMD-ONLY0:       if.end1656:
41525 // SIMD-ONLY0-NEXT:    [[TMP1026:%.*]] = load i16, ptr [[SX]], align 2
41526 // SIMD-ONLY0-NEXT:    [[CONV1657:%.*]] = sext i16 [[TMP1026]] to i32
41527 // SIMD-ONLY0-NEXT:    [[TMP1027:%.*]] = load i16, ptr [[SE]], align 2
41528 // SIMD-ONLY0-NEXT:    [[CONV1658:%.*]] = sext i16 [[TMP1027]] to i32
41529 // SIMD-ONLY0-NEXT:    [[CMP1659:%.*]] = icmp eq i32 [[CONV1657]], [[CONV1658]]
41530 // SIMD-ONLY0-NEXT:    [[CONV1660:%.*]] = zext i1 [[CMP1659]] to i32
41531 // SIMD-ONLY0-NEXT:    [[CONV1661:%.*]] = trunc i32 [[CONV1660]] to i16
41532 // SIMD-ONLY0-NEXT:    store i16 [[CONV1661]], ptr [[SR]], align 2
41533 // SIMD-ONLY0-NEXT:    [[TMP1028:%.*]] = load i16, ptr [[SR]], align 2
41534 // SIMD-ONLY0-NEXT:    [[TOBOOL1662:%.*]] = icmp ne i16 [[TMP1028]], 0
41535 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1662]], label [[IF_THEN1663:%.*]], label [[IF_ELSE1664:%.*]]
41536 // SIMD-ONLY0:       if.then1663:
41537 // SIMD-ONLY0-NEXT:    [[TMP1029:%.*]] = load i16, ptr [[SD]], align 2
41538 // SIMD-ONLY0-NEXT:    store i16 [[TMP1029]], ptr [[SX]], align 2
41539 // SIMD-ONLY0-NEXT:    br label [[IF_END1665:%.*]]
41540 // SIMD-ONLY0:       if.else1664:
41541 // SIMD-ONLY0-NEXT:    [[TMP1030:%.*]] = load i16, ptr [[SX]], align 2
41542 // SIMD-ONLY0-NEXT:    store i16 [[TMP1030]], ptr [[SV]], align 2
41543 // SIMD-ONLY0-NEXT:    br label [[IF_END1665]]
41544 // SIMD-ONLY0:       if.end1665:
41545 // SIMD-ONLY0-NEXT:    [[TMP1031:%.*]] = load i16, ptr [[SE]], align 2
41546 // SIMD-ONLY0-NEXT:    [[CONV1666:%.*]] = sext i16 [[TMP1031]] to i32
41547 // SIMD-ONLY0-NEXT:    [[TMP1032:%.*]] = load i16, ptr [[SX]], align 2
41548 // SIMD-ONLY0-NEXT:    [[CONV1667:%.*]] = sext i16 [[TMP1032]] to i32
41549 // SIMD-ONLY0-NEXT:    [[CMP1668:%.*]] = icmp eq i32 [[CONV1666]], [[CONV1667]]
41550 // SIMD-ONLY0-NEXT:    [[CONV1669:%.*]] = zext i1 [[CMP1668]] to i32
41551 // SIMD-ONLY0-NEXT:    [[CONV1670:%.*]] = trunc i32 [[CONV1669]] to i16
41552 // SIMD-ONLY0-NEXT:    store i16 [[CONV1670]], ptr [[SR]], align 2
41553 // SIMD-ONLY0-NEXT:    [[TMP1033:%.*]] = load i16, ptr [[SR]], align 2
41554 // SIMD-ONLY0-NEXT:    [[TOBOOL1671:%.*]] = icmp ne i16 [[TMP1033]], 0
41555 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1671]], label [[IF_THEN1672:%.*]], label [[IF_ELSE1673:%.*]]
41556 // SIMD-ONLY0:       if.then1672:
41557 // SIMD-ONLY0-NEXT:    [[TMP1034:%.*]] = load i16, ptr [[SD]], align 2
41558 // SIMD-ONLY0-NEXT:    store i16 [[TMP1034]], ptr [[SX]], align 2
41559 // SIMD-ONLY0-NEXT:    br label [[IF_END1674:%.*]]
41560 // SIMD-ONLY0:       if.else1673:
41561 // SIMD-ONLY0-NEXT:    [[TMP1035:%.*]] = load i16, ptr [[SX]], align 2
41562 // SIMD-ONLY0-NEXT:    store i16 [[TMP1035]], ptr [[SV]], align 2
41563 // SIMD-ONLY0-NEXT:    br label [[IF_END1674]]
41564 // SIMD-ONLY0:       if.end1674:
41565 // SIMD-ONLY0-NEXT:    [[TMP1036:%.*]] = load i16, ptr [[SX]], align 2
41566 // SIMD-ONLY0-NEXT:    store i16 [[TMP1036]], ptr [[SV]], align 2
41567 // SIMD-ONLY0-NEXT:    [[TMP1037:%.*]] = load i16, ptr [[SE]], align 2
41568 // SIMD-ONLY0-NEXT:    [[CONV1675:%.*]] = sext i16 [[TMP1037]] to i32
41569 // SIMD-ONLY0-NEXT:    [[TMP1038:%.*]] = load i16, ptr [[SX]], align 2
41570 // SIMD-ONLY0-NEXT:    [[CONV1676:%.*]] = sext i16 [[TMP1038]] to i32
41571 // SIMD-ONLY0-NEXT:    [[CMP1677:%.*]] = icmp sgt i32 [[CONV1675]], [[CONV1676]]
41572 // SIMD-ONLY0-NEXT:    br i1 [[CMP1677]], label [[IF_THEN1679:%.*]], label [[IF_END1680:%.*]]
41573 // SIMD-ONLY0:       if.then1679:
41574 // SIMD-ONLY0-NEXT:    [[TMP1039:%.*]] = load i16, ptr [[SE]], align 2
41575 // SIMD-ONLY0-NEXT:    store i16 [[TMP1039]], ptr [[SX]], align 2
41576 // SIMD-ONLY0-NEXT:    br label [[IF_END1680]]
41577 // SIMD-ONLY0:       if.end1680:
41578 // SIMD-ONLY0-NEXT:    [[TMP1040:%.*]] = load i16, ptr [[SX]], align 2
41579 // SIMD-ONLY0-NEXT:    store i16 [[TMP1040]], ptr [[SV]], align 2
41580 // SIMD-ONLY0-NEXT:    [[TMP1041:%.*]] = load i16, ptr [[SX]], align 2
41581 // SIMD-ONLY0-NEXT:    [[CONV1681:%.*]] = sext i16 [[TMP1041]] to i32
41582 // SIMD-ONLY0-NEXT:    [[TMP1042:%.*]] = load i16, ptr [[SE]], align 2
41583 // SIMD-ONLY0-NEXT:    [[CONV1682:%.*]] = sext i16 [[TMP1042]] to i32
41584 // SIMD-ONLY0-NEXT:    [[CMP1683:%.*]] = icmp sgt i32 [[CONV1681]], [[CONV1682]]
41585 // SIMD-ONLY0-NEXT:    br i1 [[CMP1683]], label [[IF_THEN1685:%.*]], label [[IF_END1686:%.*]]
41586 // SIMD-ONLY0:       if.then1685:
41587 // SIMD-ONLY0-NEXT:    [[TMP1043:%.*]] = load i16, ptr [[SE]], align 2
41588 // SIMD-ONLY0-NEXT:    store i16 [[TMP1043]], ptr [[SX]], align 2
41589 // SIMD-ONLY0-NEXT:    br label [[IF_END1686]]
41590 // SIMD-ONLY0:       if.end1686:
41591 // SIMD-ONLY0-NEXT:    [[TMP1044:%.*]] = load i16, ptr [[SX]], align 2
41592 // SIMD-ONLY0-NEXT:    store i16 [[TMP1044]], ptr [[SV]], align 2
41593 // SIMD-ONLY0-NEXT:    [[TMP1045:%.*]] = load i16, ptr [[SE]], align 2
41594 // SIMD-ONLY0-NEXT:    [[CONV1687:%.*]] = sext i16 [[TMP1045]] to i32
41595 // SIMD-ONLY0-NEXT:    [[TMP1046:%.*]] = load i16, ptr [[SX]], align 2
41596 // SIMD-ONLY0-NEXT:    [[CONV1688:%.*]] = sext i16 [[TMP1046]] to i32
41597 // SIMD-ONLY0-NEXT:    [[CMP1689:%.*]] = icmp slt i32 [[CONV1687]], [[CONV1688]]
41598 // SIMD-ONLY0-NEXT:    br i1 [[CMP1689]], label [[IF_THEN1691:%.*]], label [[IF_END1692:%.*]]
41599 // SIMD-ONLY0:       if.then1691:
41600 // SIMD-ONLY0-NEXT:    [[TMP1047:%.*]] = load i16, ptr [[SE]], align 2
41601 // SIMD-ONLY0-NEXT:    store i16 [[TMP1047]], ptr [[SX]], align 2
41602 // SIMD-ONLY0-NEXT:    br label [[IF_END1692]]
41603 // SIMD-ONLY0:       if.end1692:
41604 // SIMD-ONLY0-NEXT:    [[TMP1048:%.*]] = load i16, ptr [[SX]], align 2
41605 // SIMD-ONLY0-NEXT:    store i16 [[TMP1048]], ptr [[SV]], align 2
41606 // SIMD-ONLY0-NEXT:    [[TMP1049:%.*]] = load i16, ptr [[SX]], align 2
41607 // SIMD-ONLY0-NEXT:    [[CONV1693:%.*]] = sext i16 [[TMP1049]] to i32
41608 // SIMD-ONLY0-NEXT:    [[TMP1050:%.*]] = load i16, ptr [[SE]], align 2
41609 // SIMD-ONLY0-NEXT:    [[CONV1694:%.*]] = sext i16 [[TMP1050]] to i32
41610 // SIMD-ONLY0-NEXT:    [[CMP1695:%.*]] = icmp slt i32 [[CONV1693]], [[CONV1694]]
41611 // SIMD-ONLY0-NEXT:    br i1 [[CMP1695]], label [[IF_THEN1697:%.*]], label [[IF_END1698:%.*]]
41612 // SIMD-ONLY0:       if.then1697:
41613 // SIMD-ONLY0-NEXT:    [[TMP1051:%.*]] = load i16, ptr [[SE]], align 2
41614 // SIMD-ONLY0-NEXT:    store i16 [[TMP1051]], ptr [[SX]], align 2
41615 // SIMD-ONLY0-NEXT:    br label [[IF_END1698]]
41616 // SIMD-ONLY0:       if.end1698:
41617 // SIMD-ONLY0-NEXT:    [[TMP1052:%.*]] = load i16, ptr [[SX]], align 2
41618 // SIMD-ONLY0-NEXT:    store i16 [[TMP1052]], ptr [[SV]], align 2
41619 // SIMD-ONLY0-NEXT:    [[TMP1053:%.*]] = load i16, ptr [[SX]], align 2
41620 // SIMD-ONLY0-NEXT:    [[CONV1699:%.*]] = sext i16 [[TMP1053]] to i32
41621 // SIMD-ONLY0-NEXT:    [[TMP1054:%.*]] = load i16, ptr [[SE]], align 2
41622 // SIMD-ONLY0-NEXT:    [[CONV1700:%.*]] = sext i16 [[TMP1054]] to i32
41623 // SIMD-ONLY0-NEXT:    [[CMP1701:%.*]] = icmp eq i32 [[CONV1699]], [[CONV1700]]
41624 // SIMD-ONLY0-NEXT:    br i1 [[CMP1701]], label [[IF_THEN1703:%.*]], label [[IF_END1704:%.*]]
41625 // SIMD-ONLY0:       if.then1703:
41626 // SIMD-ONLY0-NEXT:    [[TMP1055:%.*]] = load i16, ptr [[SD]], align 2
41627 // SIMD-ONLY0-NEXT:    store i16 [[TMP1055]], ptr [[SX]], align 2
41628 // SIMD-ONLY0-NEXT:    br label [[IF_END1704]]
41629 // SIMD-ONLY0:       if.end1704:
41630 // SIMD-ONLY0-NEXT:    [[TMP1056:%.*]] = load i16, ptr [[SX]], align 2
41631 // SIMD-ONLY0-NEXT:    store i16 [[TMP1056]], ptr [[SV]], align 2
41632 // SIMD-ONLY0-NEXT:    [[TMP1057:%.*]] = load i16, ptr [[SE]], align 2
41633 // SIMD-ONLY0-NEXT:    [[CONV1705:%.*]] = sext i16 [[TMP1057]] to i32
41634 // SIMD-ONLY0-NEXT:    [[TMP1058:%.*]] = load i16, ptr [[SX]], align 2
41635 // SIMD-ONLY0-NEXT:    [[CONV1706:%.*]] = sext i16 [[TMP1058]] to i32
41636 // SIMD-ONLY0-NEXT:    [[CMP1707:%.*]] = icmp eq i32 [[CONV1705]], [[CONV1706]]
41637 // SIMD-ONLY0-NEXT:    br i1 [[CMP1707]], label [[IF_THEN1709:%.*]], label [[IF_END1710:%.*]]
41638 // SIMD-ONLY0:       if.then1709:
41639 // SIMD-ONLY0-NEXT:    [[TMP1059:%.*]] = load i16, ptr [[SD]], align 2
41640 // SIMD-ONLY0-NEXT:    store i16 [[TMP1059]], ptr [[SX]], align 2
41641 // SIMD-ONLY0-NEXT:    br label [[IF_END1710]]
41642 // SIMD-ONLY0:       if.end1710:
41643 // SIMD-ONLY0-NEXT:    [[TMP1060:%.*]] = load i16, ptr [[SE]], align 2
41644 // SIMD-ONLY0-NEXT:    [[CONV1711:%.*]] = sext i16 [[TMP1060]] to i32
41645 // SIMD-ONLY0-NEXT:    [[TMP1061:%.*]] = load i16, ptr [[SX]], align 2
41646 // SIMD-ONLY0-NEXT:    [[CONV1712:%.*]] = sext i16 [[TMP1061]] to i32
41647 // SIMD-ONLY0-NEXT:    [[CMP1713:%.*]] = icmp sgt i32 [[CONV1711]], [[CONV1712]]
41648 // SIMD-ONLY0-NEXT:    br i1 [[CMP1713]], label [[IF_THEN1715:%.*]], label [[IF_END1716:%.*]]
41649 // SIMD-ONLY0:       if.then1715:
41650 // SIMD-ONLY0-NEXT:    [[TMP1062:%.*]] = load i16, ptr [[SE]], align 2
41651 // SIMD-ONLY0-NEXT:    store i16 [[TMP1062]], ptr [[SX]], align 2
41652 // SIMD-ONLY0-NEXT:    br label [[IF_END1716]]
41653 // SIMD-ONLY0:       if.end1716:
41654 // SIMD-ONLY0-NEXT:    [[TMP1063:%.*]] = load i16, ptr [[SX]], align 2
41655 // SIMD-ONLY0-NEXT:    store i16 [[TMP1063]], ptr [[SV]], align 2
41656 // SIMD-ONLY0-NEXT:    [[TMP1064:%.*]] = load i16, ptr [[SX]], align 2
41657 // SIMD-ONLY0-NEXT:    [[CONV1717:%.*]] = sext i16 [[TMP1064]] to i32
41658 // SIMD-ONLY0-NEXT:    [[TMP1065:%.*]] = load i16, ptr [[SE]], align 2
41659 // SIMD-ONLY0-NEXT:    [[CONV1718:%.*]] = sext i16 [[TMP1065]] to i32
41660 // SIMD-ONLY0-NEXT:    [[CMP1719:%.*]] = icmp sgt i32 [[CONV1717]], [[CONV1718]]
41661 // SIMD-ONLY0-NEXT:    br i1 [[CMP1719]], label [[IF_THEN1721:%.*]], label [[IF_END1722:%.*]]
41662 // SIMD-ONLY0:       if.then1721:
41663 // SIMD-ONLY0-NEXT:    [[TMP1066:%.*]] = load i16, ptr [[SE]], align 2
41664 // SIMD-ONLY0-NEXT:    store i16 [[TMP1066]], ptr [[SX]], align 2
41665 // SIMD-ONLY0-NEXT:    br label [[IF_END1722]]
41666 // SIMD-ONLY0:       if.end1722:
41667 // SIMD-ONLY0-NEXT:    [[TMP1067:%.*]] = load i16, ptr [[SX]], align 2
41668 // SIMD-ONLY0-NEXT:    store i16 [[TMP1067]], ptr [[SV]], align 2
41669 // SIMD-ONLY0-NEXT:    [[TMP1068:%.*]] = load i16, ptr [[SE]], align 2
41670 // SIMD-ONLY0-NEXT:    [[CONV1723:%.*]] = sext i16 [[TMP1068]] to i32
41671 // SIMD-ONLY0-NEXT:    [[TMP1069:%.*]] = load i16, ptr [[SX]], align 2
41672 // SIMD-ONLY0-NEXT:    [[CONV1724:%.*]] = sext i16 [[TMP1069]] to i32
41673 // SIMD-ONLY0-NEXT:    [[CMP1725:%.*]] = icmp slt i32 [[CONV1723]], [[CONV1724]]
41674 // SIMD-ONLY0-NEXT:    br i1 [[CMP1725]], label [[IF_THEN1727:%.*]], label [[IF_END1728:%.*]]
41675 // SIMD-ONLY0:       if.then1727:
41676 // SIMD-ONLY0-NEXT:    [[TMP1070:%.*]] = load i16, ptr [[SE]], align 2
41677 // SIMD-ONLY0-NEXT:    store i16 [[TMP1070]], ptr [[SX]], align 2
41678 // SIMD-ONLY0-NEXT:    br label [[IF_END1728]]
41679 // SIMD-ONLY0:       if.end1728:
41680 // SIMD-ONLY0-NEXT:    [[TMP1071:%.*]] = load i16, ptr [[SX]], align 2
41681 // SIMD-ONLY0-NEXT:    store i16 [[TMP1071]], ptr [[SV]], align 2
41682 // SIMD-ONLY0-NEXT:    [[TMP1072:%.*]] = load i16, ptr [[SX]], align 2
41683 // SIMD-ONLY0-NEXT:    [[CONV1729:%.*]] = sext i16 [[TMP1072]] to i32
41684 // SIMD-ONLY0-NEXT:    [[TMP1073:%.*]] = load i16, ptr [[SE]], align 2
41685 // SIMD-ONLY0-NEXT:    [[CONV1730:%.*]] = sext i16 [[TMP1073]] to i32
41686 // SIMD-ONLY0-NEXT:    [[CMP1731:%.*]] = icmp slt i32 [[CONV1729]], [[CONV1730]]
41687 // SIMD-ONLY0-NEXT:    br i1 [[CMP1731]], label [[IF_THEN1733:%.*]], label [[IF_END1734:%.*]]
41688 // SIMD-ONLY0:       if.then1733:
41689 // SIMD-ONLY0-NEXT:    [[TMP1074:%.*]] = load i16, ptr [[SE]], align 2
41690 // SIMD-ONLY0-NEXT:    store i16 [[TMP1074]], ptr [[SX]], align 2
41691 // SIMD-ONLY0-NEXT:    br label [[IF_END1734]]
41692 // SIMD-ONLY0:       if.end1734:
41693 // SIMD-ONLY0-NEXT:    [[TMP1075:%.*]] = load i16, ptr [[SX]], align 2
41694 // SIMD-ONLY0-NEXT:    store i16 [[TMP1075]], ptr [[SV]], align 2
41695 // SIMD-ONLY0-NEXT:    [[TMP1076:%.*]] = load i16, ptr [[SX]], align 2
41696 // SIMD-ONLY0-NEXT:    [[CONV1735:%.*]] = sext i16 [[TMP1076]] to i32
41697 // SIMD-ONLY0-NEXT:    [[TMP1077:%.*]] = load i16, ptr [[SE]], align 2
41698 // SIMD-ONLY0-NEXT:    [[CONV1736:%.*]] = sext i16 [[TMP1077]] to i32
41699 // SIMD-ONLY0-NEXT:    [[CMP1737:%.*]] = icmp eq i32 [[CONV1735]], [[CONV1736]]
41700 // SIMD-ONLY0-NEXT:    br i1 [[CMP1737]], label [[IF_THEN1739:%.*]], label [[IF_END1740:%.*]]
41701 // SIMD-ONLY0:       if.then1739:
41702 // SIMD-ONLY0-NEXT:    [[TMP1078:%.*]] = load i16, ptr [[SD]], align 2
41703 // SIMD-ONLY0-NEXT:    store i16 [[TMP1078]], ptr [[SX]], align 2
41704 // SIMD-ONLY0-NEXT:    br label [[IF_END1740]]
41705 // SIMD-ONLY0:       if.end1740:
41706 // SIMD-ONLY0-NEXT:    [[TMP1079:%.*]] = load i16, ptr [[SX]], align 2
41707 // SIMD-ONLY0-NEXT:    store i16 [[TMP1079]], ptr [[SV]], align 2
41708 // SIMD-ONLY0-NEXT:    [[TMP1080:%.*]] = load i16, ptr [[SE]], align 2
41709 // SIMD-ONLY0-NEXT:    [[CONV1741:%.*]] = sext i16 [[TMP1080]] to i32
41710 // SIMD-ONLY0-NEXT:    [[TMP1081:%.*]] = load i16, ptr [[SX]], align 2
41711 // SIMD-ONLY0-NEXT:    [[CONV1742:%.*]] = sext i16 [[TMP1081]] to i32
41712 // SIMD-ONLY0-NEXT:    [[CMP1743:%.*]] = icmp eq i32 [[CONV1741]], [[CONV1742]]
41713 // SIMD-ONLY0-NEXT:    br i1 [[CMP1743]], label [[IF_THEN1745:%.*]], label [[IF_END1746:%.*]]
41714 // SIMD-ONLY0:       if.then1745:
41715 // SIMD-ONLY0-NEXT:    [[TMP1082:%.*]] = load i16, ptr [[SD]], align 2
41716 // SIMD-ONLY0-NEXT:    store i16 [[TMP1082]], ptr [[SX]], align 2
41717 // SIMD-ONLY0-NEXT:    br label [[IF_END1746]]
41718 // SIMD-ONLY0:       if.end1746:
41719 // SIMD-ONLY0-NEXT:    [[TMP1083:%.*]] = load i16, ptr [[SX]], align 2
41720 // SIMD-ONLY0-NEXT:    store i16 [[TMP1083]], ptr [[SV]], align 2
41721 // SIMD-ONLY0-NEXT:    [[TMP1084:%.*]] = load i16, ptr [[SX]], align 2
41722 // SIMD-ONLY0-NEXT:    [[CONV1747:%.*]] = sext i16 [[TMP1084]] to i32
41723 // SIMD-ONLY0-NEXT:    [[TMP1085:%.*]] = load i16, ptr [[SE]], align 2
41724 // SIMD-ONLY0-NEXT:    [[CONV1748:%.*]] = sext i16 [[TMP1085]] to i32
41725 // SIMD-ONLY0-NEXT:    [[CMP1749:%.*]] = icmp eq i32 [[CONV1747]], [[CONV1748]]
41726 // SIMD-ONLY0-NEXT:    br i1 [[CMP1749]], label [[IF_THEN1751:%.*]], label [[IF_ELSE1752:%.*]]
41727 // SIMD-ONLY0:       if.then1751:
41728 // SIMD-ONLY0-NEXT:    [[TMP1086:%.*]] = load i16, ptr [[SD]], align 2
41729 // SIMD-ONLY0-NEXT:    store i16 [[TMP1086]], ptr [[SX]], align 2
41730 // SIMD-ONLY0-NEXT:    br label [[IF_END1753:%.*]]
41731 // SIMD-ONLY0:       if.else1752:
41732 // SIMD-ONLY0-NEXT:    [[TMP1087:%.*]] = load i16, ptr [[SX]], align 2
41733 // SIMD-ONLY0-NEXT:    store i16 [[TMP1087]], ptr [[SV]], align 2
41734 // SIMD-ONLY0-NEXT:    br label [[IF_END1753]]
41735 // SIMD-ONLY0:       if.end1753:
41736 // SIMD-ONLY0-NEXT:    [[TMP1088:%.*]] = load i16, ptr [[SE]], align 2
41737 // SIMD-ONLY0-NEXT:    [[CONV1754:%.*]] = sext i16 [[TMP1088]] to i32
41738 // SIMD-ONLY0-NEXT:    [[TMP1089:%.*]] = load i16, ptr [[SX]], align 2
41739 // SIMD-ONLY0-NEXT:    [[CONV1755:%.*]] = sext i16 [[TMP1089]] to i32
41740 // SIMD-ONLY0-NEXT:    [[CMP1756:%.*]] = icmp eq i32 [[CONV1754]], [[CONV1755]]
41741 // SIMD-ONLY0-NEXT:    br i1 [[CMP1756]], label [[IF_THEN1758:%.*]], label [[IF_ELSE1759:%.*]]
41742 // SIMD-ONLY0:       if.then1758:
41743 // SIMD-ONLY0-NEXT:    [[TMP1090:%.*]] = load i16, ptr [[SD]], align 2
41744 // SIMD-ONLY0-NEXT:    store i16 [[TMP1090]], ptr [[SX]], align 2
41745 // SIMD-ONLY0-NEXT:    br label [[IF_END1760:%.*]]
41746 // SIMD-ONLY0:       if.else1759:
41747 // SIMD-ONLY0-NEXT:    [[TMP1091:%.*]] = load i16, ptr [[SX]], align 2
41748 // SIMD-ONLY0-NEXT:    store i16 [[TMP1091]], ptr [[SV]], align 2
41749 // SIMD-ONLY0-NEXT:    br label [[IF_END1760]]
41750 // SIMD-ONLY0:       if.end1760:
41751 // SIMD-ONLY0-NEXT:    [[TMP1092:%.*]] = load i16, ptr [[SX]], align 2
41752 // SIMD-ONLY0-NEXT:    [[CONV1761:%.*]] = sext i16 [[TMP1092]] to i32
41753 // SIMD-ONLY0-NEXT:    [[TMP1093:%.*]] = load i16, ptr [[SE]], align 2
41754 // SIMD-ONLY0-NEXT:    [[CONV1762:%.*]] = sext i16 [[TMP1093]] to i32
41755 // SIMD-ONLY0-NEXT:    [[CMP1763:%.*]] = icmp eq i32 [[CONV1761]], [[CONV1762]]
41756 // SIMD-ONLY0-NEXT:    [[CONV1764:%.*]] = zext i1 [[CMP1763]] to i32
41757 // SIMD-ONLY0-NEXT:    [[CONV1765:%.*]] = trunc i32 [[CONV1764]] to i16
41758 // SIMD-ONLY0-NEXT:    store i16 [[CONV1765]], ptr [[SR]], align 2
41759 // SIMD-ONLY0-NEXT:    [[TMP1094:%.*]] = load i16, ptr [[SR]], align 2
41760 // SIMD-ONLY0-NEXT:    [[TOBOOL1766:%.*]] = icmp ne i16 [[TMP1094]], 0
41761 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1766]], label [[IF_THEN1767:%.*]], label [[IF_END1768:%.*]]
41762 // SIMD-ONLY0:       if.then1767:
41763 // SIMD-ONLY0-NEXT:    [[TMP1095:%.*]] = load i16, ptr [[SD]], align 2
41764 // SIMD-ONLY0-NEXT:    store i16 [[TMP1095]], ptr [[SX]], align 2
41765 // SIMD-ONLY0-NEXT:    br label [[IF_END1768]]
41766 // SIMD-ONLY0:       if.end1768:
41767 // SIMD-ONLY0-NEXT:    [[TMP1096:%.*]] = load i16, ptr [[SE]], align 2
41768 // SIMD-ONLY0-NEXT:    [[CONV1769:%.*]] = sext i16 [[TMP1096]] to i32
41769 // SIMD-ONLY0-NEXT:    [[TMP1097:%.*]] = load i16, ptr [[SX]], align 2
41770 // SIMD-ONLY0-NEXT:    [[CONV1770:%.*]] = sext i16 [[TMP1097]] to i32
41771 // SIMD-ONLY0-NEXT:    [[CMP1771:%.*]] = icmp eq i32 [[CONV1769]], [[CONV1770]]
41772 // SIMD-ONLY0-NEXT:    [[CONV1772:%.*]] = zext i1 [[CMP1771]] to i32
41773 // SIMD-ONLY0-NEXT:    [[CONV1773:%.*]] = trunc i32 [[CONV1772]] to i16
41774 // SIMD-ONLY0-NEXT:    store i16 [[CONV1773]], ptr [[SR]], align 2
41775 // SIMD-ONLY0-NEXT:    [[TMP1098:%.*]] = load i16, ptr [[SR]], align 2
41776 // SIMD-ONLY0-NEXT:    [[TOBOOL1774:%.*]] = icmp ne i16 [[TMP1098]], 0
41777 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1774]], label [[IF_THEN1775:%.*]], label [[IF_END1776:%.*]]
41778 // SIMD-ONLY0:       if.then1775:
41779 // SIMD-ONLY0-NEXT:    [[TMP1099:%.*]] = load i16, ptr [[SD]], align 2
41780 // SIMD-ONLY0-NEXT:    store i16 [[TMP1099]], ptr [[SX]], align 2
41781 // SIMD-ONLY0-NEXT:    br label [[IF_END1776]]
41782 // SIMD-ONLY0:       if.end1776:
41783 // SIMD-ONLY0-NEXT:    [[TMP1100:%.*]] = load i16, ptr [[SX]], align 2
41784 // SIMD-ONLY0-NEXT:    [[CONV1777:%.*]] = sext i16 [[TMP1100]] to i32
41785 // SIMD-ONLY0-NEXT:    [[TMP1101:%.*]] = load i16, ptr [[SE]], align 2
41786 // SIMD-ONLY0-NEXT:    [[CONV1778:%.*]] = sext i16 [[TMP1101]] to i32
41787 // SIMD-ONLY0-NEXT:    [[CMP1779:%.*]] = icmp eq i32 [[CONV1777]], [[CONV1778]]
41788 // SIMD-ONLY0-NEXT:    [[CONV1780:%.*]] = zext i1 [[CMP1779]] to i32
41789 // SIMD-ONLY0-NEXT:    [[CONV1781:%.*]] = trunc i32 [[CONV1780]] to i16
41790 // SIMD-ONLY0-NEXT:    store i16 [[CONV1781]], ptr [[SR]], align 2
41791 // SIMD-ONLY0-NEXT:    [[TMP1102:%.*]] = load i16, ptr [[SR]], align 2
41792 // SIMD-ONLY0-NEXT:    [[TOBOOL1782:%.*]] = icmp ne i16 [[TMP1102]], 0
41793 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1782]], label [[IF_THEN1783:%.*]], label [[IF_ELSE1784:%.*]]
41794 // SIMD-ONLY0:       if.then1783:
41795 // SIMD-ONLY0-NEXT:    [[TMP1103:%.*]] = load i16, ptr [[SD]], align 2
41796 // SIMD-ONLY0-NEXT:    store i16 [[TMP1103]], ptr [[SX]], align 2
41797 // SIMD-ONLY0-NEXT:    br label [[IF_END1785:%.*]]
41798 // SIMD-ONLY0:       if.else1784:
41799 // SIMD-ONLY0-NEXT:    [[TMP1104:%.*]] = load i16, ptr [[SX]], align 2
41800 // SIMD-ONLY0-NEXT:    store i16 [[TMP1104]], ptr [[SV]], align 2
41801 // SIMD-ONLY0-NEXT:    br label [[IF_END1785]]
41802 // SIMD-ONLY0:       if.end1785:
41803 // SIMD-ONLY0-NEXT:    [[TMP1105:%.*]] = load i16, ptr [[SE]], align 2
41804 // SIMD-ONLY0-NEXT:    [[CONV1786:%.*]] = sext i16 [[TMP1105]] to i32
41805 // SIMD-ONLY0-NEXT:    [[TMP1106:%.*]] = load i16, ptr [[SX]], align 2
41806 // SIMD-ONLY0-NEXT:    [[CONV1787:%.*]] = sext i16 [[TMP1106]] to i32
41807 // SIMD-ONLY0-NEXT:    [[CMP1788:%.*]] = icmp eq i32 [[CONV1786]], [[CONV1787]]
41808 // SIMD-ONLY0-NEXT:    [[CONV1789:%.*]] = zext i1 [[CMP1788]] to i32
41809 // SIMD-ONLY0-NEXT:    [[CONV1790:%.*]] = trunc i32 [[CONV1789]] to i16
41810 // SIMD-ONLY0-NEXT:    store i16 [[CONV1790]], ptr [[SR]], align 2
41811 // SIMD-ONLY0-NEXT:    [[TMP1107:%.*]] = load i16, ptr [[SR]], align 2
41812 // SIMD-ONLY0-NEXT:    [[TOBOOL1791:%.*]] = icmp ne i16 [[TMP1107]], 0
41813 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1791]], label [[IF_THEN1792:%.*]], label [[IF_ELSE1793:%.*]]
41814 // SIMD-ONLY0:       if.then1792:
41815 // SIMD-ONLY0-NEXT:    [[TMP1108:%.*]] = load i16, ptr [[SD]], align 2
41816 // SIMD-ONLY0-NEXT:    store i16 [[TMP1108]], ptr [[SX]], align 2
41817 // SIMD-ONLY0-NEXT:    br label [[IF_END1794:%.*]]
41818 // SIMD-ONLY0:       if.else1793:
41819 // SIMD-ONLY0-NEXT:    [[TMP1109:%.*]] = load i16, ptr [[SX]], align 2
41820 // SIMD-ONLY0-NEXT:    store i16 [[TMP1109]], ptr [[SV]], align 2
41821 // SIMD-ONLY0-NEXT:    br label [[IF_END1794]]
41822 // SIMD-ONLY0:       if.end1794:
41823 // SIMD-ONLY0-NEXT:    [[TMP1110:%.*]] = load i16, ptr [[SX]], align 2
41824 // SIMD-ONLY0-NEXT:    store i16 [[TMP1110]], ptr [[SV]], align 2
41825 // SIMD-ONLY0-NEXT:    [[TMP1111:%.*]] = load i16, ptr [[SE]], align 2
41826 // SIMD-ONLY0-NEXT:    [[CONV1795:%.*]] = sext i16 [[TMP1111]] to i32
41827 // SIMD-ONLY0-NEXT:    [[TMP1112:%.*]] = load i16, ptr [[SX]], align 2
41828 // SIMD-ONLY0-NEXT:    [[CONV1796:%.*]] = sext i16 [[TMP1112]] to i32
41829 // SIMD-ONLY0-NEXT:    [[CMP1797:%.*]] = icmp sgt i32 [[CONV1795]], [[CONV1796]]
41830 // SIMD-ONLY0-NEXT:    br i1 [[CMP1797]], label [[IF_THEN1799:%.*]], label [[IF_END1800:%.*]]
41831 // SIMD-ONLY0:       if.then1799:
41832 // SIMD-ONLY0-NEXT:    [[TMP1113:%.*]] = load i16, ptr [[SE]], align 2
41833 // SIMD-ONLY0-NEXT:    store i16 [[TMP1113]], ptr [[SX]], align 2
41834 // SIMD-ONLY0-NEXT:    br label [[IF_END1800]]
41835 // SIMD-ONLY0:       if.end1800:
41836 // SIMD-ONLY0-NEXT:    [[TMP1114:%.*]] = load i16, ptr [[SX]], align 2
41837 // SIMD-ONLY0-NEXT:    store i16 [[TMP1114]], ptr [[SV]], align 2
41838 // SIMD-ONLY0-NEXT:    [[TMP1115:%.*]] = load i16, ptr [[SX]], align 2
41839 // SIMD-ONLY0-NEXT:    [[CONV1801:%.*]] = sext i16 [[TMP1115]] to i32
41840 // SIMD-ONLY0-NEXT:    [[TMP1116:%.*]] = load i16, ptr [[SE]], align 2
41841 // SIMD-ONLY0-NEXT:    [[CONV1802:%.*]] = sext i16 [[TMP1116]] to i32
41842 // SIMD-ONLY0-NEXT:    [[CMP1803:%.*]] = icmp sgt i32 [[CONV1801]], [[CONV1802]]
41843 // SIMD-ONLY0-NEXT:    br i1 [[CMP1803]], label [[IF_THEN1805:%.*]], label [[IF_END1806:%.*]]
41844 // SIMD-ONLY0:       if.then1805:
41845 // SIMD-ONLY0-NEXT:    [[TMP1117:%.*]] = load i16, ptr [[SE]], align 2
41846 // SIMD-ONLY0-NEXT:    store i16 [[TMP1117]], ptr [[SX]], align 2
41847 // SIMD-ONLY0-NEXT:    br label [[IF_END1806]]
41848 // SIMD-ONLY0:       if.end1806:
41849 // SIMD-ONLY0-NEXT:    [[TMP1118:%.*]] = load i16, ptr [[SX]], align 2
41850 // SIMD-ONLY0-NEXT:    store i16 [[TMP1118]], ptr [[SV]], align 2
41851 // SIMD-ONLY0-NEXT:    [[TMP1119:%.*]] = load i16, ptr [[SE]], align 2
41852 // SIMD-ONLY0-NEXT:    [[CONV1807:%.*]] = sext i16 [[TMP1119]] to i32
41853 // SIMD-ONLY0-NEXT:    [[TMP1120:%.*]] = load i16, ptr [[SX]], align 2
41854 // SIMD-ONLY0-NEXT:    [[CONV1808:%.*]] = sext i16 [[TMP1120]] to i32
41855 // SIMD-ONLY0-NEXT:    [[CMP1809:%.*]] = icmp slt i32 [[CONV1807]], [[CONV1808]]
41856 // SIMD-ONLY0-NEXT:    br i1 [[CMP1809]], label [[IF_THEN1811:%.*]], label [[IF_END1812:%.*]]
41857 // SIMD-ONLY0:       if.then1811:
41858 // SIMD-ONLY0-NEXT:    [[TMP1121:%.*]] = load i16, ptr [[SE]], align 2
41859 // SIMD-ONLY0-NEXT:    store i16 [[TMP1121]], ptr [[SX]], align 2
41860 // SIMD-ONLY0-NEXT:    br label [[IF_END1812]]
41861 // SIMD-ONLY0:       if.end1812:
41862 // SIMD-ONLY0-NEXT:    [[TMP1122:%.*]] = load i16, ptr [[SX]], align 2
41863 // SIMD-ONLY0-NEXT:    store i16 [[TMP1122]], ptr [[SV]], align 2
41864 // SIMD-ONLY0-NEXT:    [[TMP1123:%.*]] = load i16, ptr [[SX]], align 2
41865 // SIMD-ONLY0-NEXT:    [[CONV1813:%.*]] = sext i16 [[TMP1123]] to i32
41866 // SIMD-ONLY0-NEXT:    [[TMP1124:%.*]] = load i16, ptr [[SE]], align 2
41867 // SIMD-ONLY0-NEXT:    [[CONV1814:%.*]] = sext i16 [[TMP1124]] to i32
41868 // SIMD-ONLY0-NEXT:    [[CMP1815:%.*]] = icmp slt i32 [[CONV1813]], [[CONV1814]]
41869 // SIMD-ONLY0-NEXT:    br i1 [[CMP1815]], label [[IF_THEN1817:%.*]], label [[IF_END1818:%.*]]
41870 // SIMD-ONLY0:       if.then1817:
41871 // SIMD-ONLY0-NEXT:    [[TMP1125:%.*]] = load i16, ptr [[SE]], align 2
41872 // SIMD-ONLY0-NEXT:    store i16 [[TMP1125]], ptr [[SX]], align 2
41873 // SIMD-ONLY0-NEXT:    br label [[IF_END1818]]
41874 // SIMD-ONLY0:       if.end1818:
41875 // SIMD-ONLY0-NEXT:    [[TMP1126:%.*]] = load i16, ptr [[SX]], align 2
41876 // SIMD-ONLY0-NEXT:    store i16 [[TMP1126]], ptr [[SV]], align 2
41877 // SIMD-ONLY0-NEXT:    [[TMP1127:%.*]] = load i16, ptr [[SX]], align 2
41878 // SIMD-ONLY0-NEXT:    [[CONV1819:%.*]] = sext i16 [[TMP1127]] to i32
41879 // SIMD-ONLY0-NEXT:    [[TMP1128:%.*]] = load i16, ptr [[SE]], align 2
41880 // SIMD-ONLY0-NEXT:    [[CONV1820:%.*]] = sext i16 [[TMP1128]] to i32
41881 // SIMD-ONLY0-NEXT:    [[CMP1821:%.*]] = icmp eq i32 [[CONV1819]], [[CONV1820]]
41882 // SIMD-ONLY0-NEXT:    br i1 [[CMP1821]], label [[IF_THEN1823:%.*]], label [[IF_END1824:%.*]]
41883 // SIMD-ONLY0:       if.then1823:
41884 // SIMD-ONLY0-NEXT:    [[TMP1129:%.*]] = load i16, ptr [[SD]], align 2
41885 // SIMD-ONLY0-NEXT:    store i16 [[TMP1129]], ptr [[SX]], align 2
41886 // SIMD-ONLY0-NEXT:    br label [[IF_END1824]]
41887 // SIMD-ONLY0:       if.end1824:
41888 // SIMD-ONLY0-NEXT:    [[TMP1130:%.*]] = load i16, ptr [[SX]], align 2
41889 // SIMD-ONLY0-NEXT:    store i16 [[TMP1130]], ptr [[SV]], align 2
41890 // SIMD-ONLY0-NEXT:    [[TMP1131:%.*]] = load i16, ptr [[SE]], align 2
41891 // SIMD-ONLY0-NEXT:    [[CONV1825:%.*]] = sext i16 [[TMP1131]] to i32
41892 // SIMD-ONLY0-NEXT:    [[TMP1132:%.*]] = load i16, ptr [[SX]], align 2
41893 // SIMD-ONLY0-NEXT:    [[CONV1826:%.*]] = sext i16 [[TMP1132]] to i32
41894 // SIMD-ONLY0-NEXT:    [[CMP1827:%.*]] = icmp eq i32 [[CONV1825]], [[CONV1826]]
41895 // SIMD-ONLY0-NEXT:    br i1 [[CMP1827]], label [[IF_THEN1829:%.*]], label [[IF_END1830:%.*]]
41896 // SIMD-ONLY0:       if.then1829:
41897 // SIMD-ONLY0-NEXT:    [[TMP1133:%.*]] = load i16, ptr [[SD]], align 2
41898 // SIMD-ONLY0-NEXT:    store i16 [[TMP1133]], ptr [[SX]], align 2
41899 // SIMD-ONLY0-NEXT:    br label [[IF_END1830]]
41900 // SIMD-ONLY0:       if.end1830:
41901 // SIMD-ONLY0-NEXT:    [[TMP1134:%.*]] = load i16, ptr [[SE]], align 2
41902 // SIMD-ONLY0-NEXT:    [[CONV1831:%.*]] = sext i16 [[TMP1134]] to i32
41903 // SIMD-ONLY0-NEXT:    [[TMP1135:%.*]] = load i16, ptr [[SX]], align 2
41904 // SIMD-ONLY0-NEXT:    [[CONV1832:%.*]] = sext i16 [[TMP1135]] to i32
41905 // SIMD-ONLY0-NEXT:    [[CMP1833:%.*]] = icmp sgt i32 [[CONV1831]], [[CONV1832]]
41906 // SIMD-ONLY0-NEXT:    br i1 [[CMP1833]], label [[IF_THEN1835:%.*]], label [[IF_END1836:%.*]]
41907 // SIMD-ONLY0:       if.then1835:
41908 // SIMD-ONLY0-NEXT:    [[TMP1136:%.*]] = load i16, ptr [[SE]], align 2
41909 // SIMD-ONLY0-NEXT:    store i16 [[TMP1136]], ptr [[SX]], align 2
41910 // SIMD-ONLY0-NEXT:    br label [[IF_END1836]]
41911 // SIMD-ONLY0:       if.end1836:
41912 // SIMD-ONLY0-NEXT:    [[TMP1137:%.*]] = load i16, ptr [[SX]], align 2
41913 // SIMD-ONLY0-NEXT:    store i16 [[TMP1137]], ptr [[SV]], align 2
41914 // SIMD-ONLY0-NEXT:    [[TMP1138:%.*]] = load i16, ptr [[SX]], align 2
41915 // SIMD-ONLY0-NEXT:    [[CONV1837:%.*]] = sext i16 [[TMP1138]] to i32
41916 // SIMD-ONLY0-NEXT:    [[TMP1139:%.*]] = load i16, ptr [[SE]], align 2
41917 // SIMD-ONLY0-NEXT:    [[CONV1838:%.*]] = sext i16 [[TMP1139]] to i32
41918 // SIMD-ONLY0-NEXT:    [[CMP1839:%.*]] = icmp sgt i32 [[CONV1837]], [[CONV1838]]
41919 // SIMD-ONLY0-NEXT:    br i1 [[CMP1839]], label [[IF_THEN1841:%.*]], label [[IF_END1842:%.*]]
41920 // SIMD-ONLY0:       if.then1841:
41921 // SIMD-ONLY0-NEXT:    [[TMP1140:%.*]] = load i16, ptr [[SE]], align 2
41922 // SIMD-ONLY0-NEXT:    store i16 [[TMP1140]], ptr [[SX]], align 2
41923 // SIMD-ONLY0-NEXT:    br label [[IF_END1842]]
41924 // SIMD-ONLY0:       if.end1842:
41925 // SIMD-ONLY0-NEXT:    [[TMP1141:%.*]] = load i16, ptr [[SX]], align 2
41926 // SIMD-ONLY0-NEXT:    store i16 [[TMP1141]], ptr [[SV]], align 2
41927 // SIMD-ONLY0-NEXT:    [[TMP1142:%.*]] = load i16, ptr [[SE]], align 2
41928 // SIMD-ONLY0-NEXT:    [[CONV1843:%.*]] = sext i16 [[TMP1142]] to i32
41929 // SIMD-ONLY0-NEXT:    [[TMP1143:%.*]] = load i16, ptr [[SX]], align 2
41930 // SIMD-ONLY0-NEXT:    [[CONV1844:%.*]] = sext i16 [[TMP1143]] to i32
41931 // SIMD-ONLY0-NEXT:    [[CMP1845:%.*]] = icmp slt i32 [[CONV1843]], [[CONV1844]]
41932 // SIMD-ONLY0-NEXT:    br i1 [[CMP1845]], label [[IF_THEN1847:%.*]], label [[IF_END1848:%.*]]
41933 // SIMD-ONLY0:       if.then1847:
41934 // SIMD-ONLY0-NEXT:    [[TMP1144:%.*]] = load i16, ptr [[SE]], align 2
41935 // SIMD-ONLY0-NEXT:    store i16 [[TMP1144]], ptr [[SX]], align 2
41936 // SIMD-ONLY0-NEXT:    br label [[IF_END1848]]
41937 // SIMD-ONLY0:       if.end1848:
41938 // SIMD-ONLY0-NEXT:    [[TMP1145:%.*]] = load i16, ptr [[SX]], align 2
41939 // SIMD-ONLY0-NEXT:    store i16 [[TMP1145]], ptr [[SV]], align 2
41940 // SIMD-ONLY0-NEXT:    [[TMP1146:%.*]] = load i16, ptr [[SX]], align 2
41941 // SIMD-ONLY0-NEXT:    [[CONV1849:%.*]] = sext i16 [[TMP1146]] to i32
41942 // SIMD-ONLY0-NEXT:    [[TMP1147:%.*]] = load i16, ptr [[SE]], align 2
41943 // SIMD-ONLY0-NEXT:    [[CONV1850:%.*]] = sext i16 [[TMP1147]] to i32
41944 // SIMD-ONLY0-NEXT:    [[CMP1851:%.*]] = icmp slt i32 [[CONV1849]], [[CONV1850]]
41945 // SIMD-ONLY0-NEXT:    br i1 [[CMP1851]], label [[IF_THEN1853:%.*]], label [[IF_END1854:%.*]]
41946 // SIMD-ONLY0:       if.then1853:
41947 // SIMD-ONLY0-NEXT:    [[TMP1148:%.*]] = load i16, ptr [[SE]], align 2
41948 // SIMD-ONLY0-NEXT:    store i16 [[TMP1148]], ptr [[SX]], align 2
41949 // SIMD-ONLY0-NEXT:    br label [[IF_END1854]]
41950 // SIMD-ONLY0:       if.end1854:
41951 // SIMD-ONLY0-NEXT:    [[TMP1149:%.*]] = load i16, ptr [[SX]], align 2
41952 // SIMD-ONLY0-NEXT:    store i16 [[TMP1149]], ptr [[SV]], align 2
41953 // SIMD-ONLY0-NEXT:    [[TMP1150:%.*]] = load i16, ptr [[SX]], align 2
41954 // SIMD-ONLY0-NEXT:    [[CONV1855:%.*]] = sext i16 [[TMP1150]] to i32
41955 // SIMD-ONLY0-NEXT:    [[TMP1151:%.*]] = load i16, ptr [[SE]], align 2
41956 // SIMD-ONLY0-NEXT:    [[CONV1856:%.*]] = sext i16 [[TMP1151]] to i32
41957 // SIMD-ONLY0-NEXT:    [[CMP1857:%.*]] = icmp eq i32 [[CONV1855]], [[CONV1856]]
41958 // SIMD-ONLY0-NEXT:    br i1 [[CMP1857]], label [[IF_THEN1859:%.*]], label [[IF_END1860:%.*]]
41959 // SIMD-ONLY0:       if.then1859:
41960 // SIMD-ONLY0-NEXT:    [[TMP1152:%.*]] = load i16, ptr [[SD]], align 2
41961 // SIMD-ONLY0-NEXT:    store i16 [[TMP1152]], ptr [[SX]], align 2
41962 // SIMD-ONLY0-NEXT:    br label [[IF_END1860]]
41963 // SIMD-ONLY0:       if.end1860:
41964 // SIMD-ONLY0-NEXT:    [[TMP1153:%.*]] = load i16, ptr [[SX]], align 2
41965 // SIMD-ONLY0-NEXT:    store i16 [[TMP1153]], ptr [[SV]], align 2
41966 // SIMD-ONLY0-NEXT:    [[TMP1154:%.*]] = load i16, ptr [[SE]], align 2
41967 // SIMD-ONLY0-NEXT:    [[CONV1861:%.*]] = sext i16 [[TMP1154]] to i32
41968 // SIMD-ONLY0-NEXT:    [[TMP1155:%.*]] = load i16, ptr [[SX]], align 2
41969 // SIMD-ONLY0-NEXT:    [[CONV1862:%.*]] = sext i16 [[TMP1155]] to i32
41970 // SIMD-ONLY0-NEXT:    [[CMP1863:%.*]] = icmp eq i32 [[CONV1861]], [[CONV1862]]
41971 // SIMD-ONLY0-NEXT:    br i1 [[CMP1863]], label [[IF_THEN1865:%.*]], label [[IF_END1866:%.*]]
41972 // SIMD-ONLY0:       if.then1865:
41973 // SIMD-ONLY0-NEXT:    [[TMP1156:%.*]] = load i16, ptr [[SD]], align 2
41974 // SIMD-ONLY0-NEXT:    store i16 [[TMP1156]], ptr [[SX]], align 2
41975 // SIMD-ONLY0-NEXT:    br label [[IF_END1866]]
41976 // SIMD-ONLY0:       if.end1866:
41977 // SIMD-ONLY0-NEXT:    [[TMP1157:%.*]] = load i16, ptr [[SX]], align 2
41978 // SIMD-ONLY0-NEXT:    store i16 [[TMP1157]], ptr [[SV]], align 2
41979 // SIMD-ONLY0-NEXT:    [[TMP1158:%.*]] = load i16, ptr [[SX]], align 2
41980 // SIMD-ONLY0-NEXT:    [[CONV1867:%.*]] = sext i16 [[TMP1158]] to i32
41981 // SIMD-ONLY0-NEXT:    [[TMP1159:%.*]] = load i16, ptr [[SE]], align 2
41982 // SIMD-ONLY0-NEXT:    [[CONV1868:%.*]] = sext i16 [[TMP1159]] to i32
41983 // SIMD-ONLY0-NEXT:    [[CMP1869:%.*]] = icmp eq i32 [[CONV1867]], [[CONV1868]]
41984 // SIMD-ONLY0-NEXT:    br i1 [[CMP1869]], label [[IF_THEN1871:%.*]], label [[IF_ELSE1872:%.*]]
41985 // SIMD-ONLY0:       if.then1871:
41986 // SIMD-ONLY0-NEXT:    [[TMP1160:%.*]] = load i16, ptr [[SD]], align 2
41987 // SIMD-ONLY0-NEXT:    store i16 [[TMP1160]], ptr [[SX]], align 2
41988 // SIMD-ONLY0-NEXT:    br label [[IF_END1873:%.*]]
41989 // SIMD-ONLY0:       if.else1872:
41990 // SIMD-ONLY0-NEXT:    [[TMP1161:%.*]] = load i16, ptr [[SX]], align 2
41991 // SIMD-ONLY0-NEXT:    store i16 [[TMP1161]], ptr [[SV]], align 2
41992 // SIMD-ONLY0-NEXT:    br label [[IF_END1873]]
41993 // SIMD-ONLY0:       if.end1873:
41994 // SIMD-ONLY0-NEXT:    [[TMP1162:%.*]] = load i16, ptr [[SE]], align 2
41995 // SIMD-ONLY0-NEXT:    [[CONV1874:%.*]] = sext i16 [[TMP1162]] to i32
41996 // SIMD-ONLY0-NEXT:    [[TMP1163:%.*]] = load i16, ptr [[SX]], align 2
41997 // SIMD-ONLY0-NEXT:    [[CONV1875:%.*]] = sext i16 [[TMP1163]] to i32
41998 // SIMD-ONLY0-NEXT:    [[CMP1876:%.*]] = icmp eq i32 [[CONV1874]], [[CONV1875]]
41999 // SIMD-ONLY0-NEXT:    br i1 [[CMP1876]], label [[IF_THEN1878:%.*]], label [[IF_ELSE1879:%.*]]
42000 // SIMD-ONLY0:       if.then1878:
42001 // SIMD-ONLY0-NEXT:    [[TMP1164:%.*]] = load i16, ptr [[SD]], align 2
42002 // SIMD-ONLY0-NEXT:    store i16 [[TMP1164]], ptr [[SX]], align 2
42003 // SIMD-ONLY0-NEXT:    br label [[IF_END1880:%.*]]
42004 // SIMD-ONLY0:       if.else1879:
42005 // SIMD-ONLY0-NEXT:    [[TMP1165:%.*]] = load i16, ptr [[SX]], align 2
42006 // SIMD-ONLY0-NEXT:    store i16 [[TMP1165]], ptr [[SV]], align 2
42007 // SIMD-ONLY0-NEXT:    br label [[IF_END1880]]
42008 // SIMD-ONLY0:       if.end1880:
42009 // SIMD-ONLY0-NEXT:    [[TMP1166:%.*]] = load i16, ptr [[SX]], align 2
42010 // SIMD-ONLY0-NEXT:    [[CONV1881:%.*]] = sext i16 [[TMP1166]] to i32
42011 // SIMD-ONLY0-NEXT:    [[TMP1167:%.*]] = load i16, ptr [[SE]], align 2
42012 // SIMD-ONLY0-NEXT:    [[CONV1882:%.*]] = sext i16 [[TMP1167]] to i32
42013 // SIMD-ONLY0-NEXT:    [[CMP1883:%.*]] = icmp eq i32 [[CONV1881]], [[CONV1882]]
42014 // SIMD-ONLY0-NEXT:    [[CONV1884:%.*]] = zext i1 [[CMP1883]] to i32
42015 // SIMD-ONLY0-NEXT:    [[CONV1885:%.*]] = trunc i32 [[CONV1884]] to i16
42016 // SIMD-ONLY0-NEXT:    store i16 [[CONV1885]], ptr [[SR]], align 2
42017 // SIMD-ONLY0-NEXT:    [[TMP1168:%.*]] = load i16, ptr [[SR]], align 2
42018 // SIMD-ONLY0-NEXT:    [[TOBOOL1886:%.*]] = icmp ne i16 [[TMP1168]], 0
42019 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1886]], label [[IF_THEN1887:%.*]], label [[IF_END1888:%.*]]
42020 // SIMD-ONLY0:       if.then1887:
42021 // SIMD-ONLY0-NEXT:    [[TMP1169:%.*]] = load i16, ptr [[SD]], align 2
42022 // SIMD-ONLY0-NEXT:    store i16 [[TMP1169]], ptr [[SX]], align 2
42023 // SIMD-ONLY0-NEXT:    br label [[IF_END1888]]
42024 // SIMD-ONLY0:       if.end1888:
42025 // SIMD-ONLY0-NEXT:    [[TMP1170:%.*]] = load i16, ptr [[SE]], align 2
42026 // SIMD-ONLY0-NEXT:    [[CONV1889:%.*]] = sext i16 [[TMP1170]] to i32
42027 // SIMD-ONLY0-NEXT:    [[TMP1171:%.*]] = load i16, ptr [[SX]], align 2
42028 // SIMD-ONLY0-NEXT:    [[CONV1890:%.*]] = sext i16 [[TMP1171]] to i32
42029 // SIMD-ONLY0-NEXT:    [[CMP1891:%.*]] = icmp eq i32 [[CONV1889]], [[CONV1890]]
42030 // SIMD-ONLY0-NEXT:    [[CONV1892:%.*]] = zext i1 [[CMP1891]] to i32
42031 // SIMD-ONLY0-NEXT:    [[CONV1893:%.*]] = trunc i32 [[CONV1892]] to i16
42032 // SIMD-ONLY0-NEXT:    store i16 [[CONV1893]], ptr [[SR]], align 2
42033 // SIMD-ONLY0-NEXT:    [[TMP1172:%.*]] = load i16, ptr [[SR]], align 2
42034 // SIMD-ONLY0-NEXT:    [[TOBOOL1894:%.*]] = icmp ne i16 [[TMP1172]], 0
42035 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1894]], label [[IF_THEN1895:%.*]], label [[IF_END1896:%.*]]
42036 // SIMD-ONLY0:       if.then1895:
42037 // SIMD-ONLY0-NEXT:    [[TMP1173:%.*]] = load i16, ptr [[SD]], align 2
42038 // SIMD-ONLY0-NEXT:    store i16 [[TMP1173]], ptr [[SX]], align 2
42039 // SIMD-ONLY0-NEXT:    br label [[IF_END1896]]
42040 // SIMD-ONLY0:       if.end1896:
42041 // SIMD-ONLY0-NEXT:    [[TMP1174:%.*]] = load i16, ptr [[SX]], align 2
42042 // SIMD-ONLY0-NEXT:    [[CONV1897:%.*]] = sext i16 [[TMP1174]] to i32
42043 // SIMD-ONLY0-NEXT:    [[TMP1175:%.*]] = load i16, ptr [[SE]], align 2
42044 // SIMD-ONLY0-NEXT:    [[CONV1898:%.*]] = sext i16 [[TMP1175]] to i32
42045 // SIMD-ONLY0-NEXT:    [[CMP1899:%.*]] = icmp eq i32 [[CONV1897]], [[CONV1898]]
42046 // SIMD-ONLY0-NEXT:    [[CONV1900:%.*]] = zext i1 [[CMP1899]] to i32
42047 // SIMD-ONLY0-NEXT:    [[CONV1901:%.*]] = trunc i32 [[CONV1900]] to i16
42048 // SIMD-ONLY0-NEXT:    store i16 [[CONV1901]], ptr [[SR]], align 2
42049 // SIMD-ONLY0-NEXT:    [[TMP1176:%.*]] = load i16, ptr [[SR]], align 2
42050 // SIMD-ONLY0-NEXT:    [[TOBOOL1902:%.*]] = icmp ne i16 [[TMP1176]], 0
42051 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1902]], label [[IF_THEN1903:%.*]], label [[IF_ELSE1904:%.*]]
42052 // SIMD-ONLY0:       if.then1903:
42053 // SIMD-ONLY0-NEXT:    [[TMP1177:%.*]] = load i16, ptr [[SD]], align 2
42054 // SIMD-ONLY0-NEXT:    store i16 [[TMP1177]], ptr [[SX]], align 2
42055 // SIMD-ONLY0-NEXT:    br label [[IF_END1905:%.*]]
42056 // SIMD-ONLY0:       if.else1904:
42057 // SIMD-ONLY0-NEXT:    [[TMP1178:%.*]] = load i16, ptr [[SX]], align 2
42058 // SIMD-ONLY0-NEXT:    store i16 [[TMP1178]], ptr [[SV]], align 2
42059 // SIMD-ONLY0-NEXT:    br label [[IF_END1905]]
42060 // SIMD-ONLY0:       if.end1905:
42061 // SIMD-ONLY0-NEXT:    [[TMP1179:%.*]] = load i16, ptr [[SE]], align 2
42062 // SIMD-ONLY0-NEXT:    [[CONV1906:%.*]] = sext i16 [[TMP1179]] to i32
42063 // SIMD-ONLY0-NEXT:    [[TMP1180:%.*]] = load i16, ptr [[SX]], align 2
42064 // SIMD-ONLY0-NEXT:    [[CONV1907:%.*]] = sext i16 [[TMP1180]] to i32
42065 // SIMD-ONLY0-NEXT:    [[CMP1908:%.*]] = icmp eq i32 [[CONV1906]], [[CONV1907]]
42066 // SIMD-ONLY0-NEXT:    [[CONV1909:%.*]] = zext i1 [[CMP1908]] to i32
42067 // SIMD-ONLY0-NEXT:    [[CONV1910:%.*]] = trunc i32 [[CONV1909]] to i16
42068 // SIMD-ONLY0-NEXT:    store i16 [[CONV1910]], ptr [[SR]], align 2
42069 // SIMD-ONLY0-NEXT:    [[TMP1181:%.*]] = load i16, ptr [[SR]], align 2
42070 // SIMD-ONLY0-NEXT:    [[TOBOOL1911:%.*]] = icmp ne i16 [[TMP1181]], 0
42071 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL1911]], label [[IF_THEN1912:%.*]], label [[IF_ELSE1913:%.*]]
42072 // SIMD-ONLY0:       if.then1912:
42073 // SIMD-ONLY0-NEXT:    [[TMP1182:%.*]] = load i16, ptr [[SD]], align 2
42074 // SIMD-ONLY0-NEXT:    store i16 [[TMP1182]], ptr [[SX]], align 2
42075 // SIMD-ONLY0-NEXT:    br label [[IF_END1914:%.*]]
42076 // SIMD-ONLY0:       if.else1913:
42077 // SIMD-ONLY0-NEXT:    [[TMP1183:%.*]] = load i16, ptr [[SX]], align 2
42078 // SIMD-ONLY0-NEXT:    store i16 [[TMP1183]], ptr [[SV]], align 2
42079 // SIMD-ONLY0-NEXT:    br label [[IF_END1914]]
42080 // SIMD-ONLY0:       if.end1914:
42081 // SIMD-ONLY0-NEXT:    [[TMP1184:%.*]] = load i16, ptr [[SX]], align 2
42082 // SIMD-ONLY0-NEXT:    store i16 [[TMP1184]], ptr [[SV]], align 2
42083 // SIMD-ONLY0-NEXT:    [[TMP1185:%.*]] = load i16, ptr [[SE]], align 2
42084 // SIMD-ONLY0-NEXT:    [[CONV1915:%.*]] = sext i16 [[TMP1185]] to i32
42085 // SIMD-ONLY0-NEXT:    [[TMP1186:%.*]] = load i16, ptr [[SX]], align 2
42086 // SIMD-ONLY0-NEXT:    [[CONV1916:%.*]] = sext i16 [[TMP1186]] to i32
42087 // SIMD-ONLY0-NEXT:    [[CMP1917:%.*]] = icmp sgt i32 [[CONV1915]], [[CONV1916]]
42088 // SIMD-ONLY0-NEXT:    br i1 [[CMP1917]], label [[IF_THEN1919:%.*]], label [[IF_END1920:%.*]]
42089 // SIMD-ONLY0:       if.then1919:
42090 // SIMD-ONLY0-NEXT:    [[TMP1187:%.*]] = load i16, ptr [[SE]], align 2
42091 // SIMD-ONLY0-NEXT:    store i16 [[TMP1187]], ptr [[SX]], align 2
42092 // SIMD-ONLY0-NEXT:    br label [[IF_END1920]]
42093 // SIMD-ONLY0:       if.end1920:
42094 // SIMD-ONLY0-NEXT:    [[TMP1188:%.*]] = load i16, ptr [[SX]], align 2
42095 // SIMD-ONLY0-NEXT:    store i16 [[TMP1188]], ptr [[SV]], align 2
42096 // SIMD-ONLY0-NEXT:    [[TMP1189:%.*]] = load i16, ptr [[SX]], align 2
42097 // SIMD-ONLY0-NEXT:    [[CONV1921:%.*]] = sext i16 [[TMP1189]] to i32
42098 // SIMD-ONLY0-NEXT:    [[TMP1190:%.*]] = load i16, ptr [[SE]], align 2
42099 // SIMD-ONLY0-NEXT:    [[CONV1922:%.*]] = sext i16 [[TMP1190]] to i32
42100 // SIMD-ONLY0-NEXT:    [[CMP1923:%.*]] = icmp sgt i32 [[CONV1921]], [[CONV1922]]
42101 // SIMD-ONLY0-NEXT:    br i1 [[CMP1923]], label [[IF_THEN1925:%.*]], label [[IF_END1926:%.*]]
42102 // SIMD-ONLY0:       if.then1925:
42103 // SIMD-ONLY0-NEXT:    [[TMP1191:%.*]] = load i16, ptr [[SE]], align 2
42104 // SIMD-ONLY0-NEXT:    store i16 [[TMP1191]], ptr [[SX]], align 2
42105 // SIMD-ONLY0-NEXT:    br label [[IF_END1926]]
42106 // SIMD-ONLY0:       if.end1926:
42107 // SIMD-ONLY0-NEXT:    [[TMP1192:%.*]] = load i16, ptr [[SX]], align 2
42108 // SIMD-ONLY0-NEXT:    store i16 [[TMP1192]], ptr [[SV]], align 2
42109 // SIMD-ONLY0-NEXT:    [[TMP1193:%.*]] = load i16, ptr [[SE]], align 2
42110 // SIMD-ONLY0-NEXT:    [[CONV1927:%.*]] = sext i16 [[TMP1193]] to i32
42111 // SIMD-ONLY0-NEXT:    [[TMP1194:%.*]] = load i16, ptr [[SX]], align 2
42112 // SIMD-ONLY0-NEXT:    [[CONV1928:%.*]] = sext i16 [[TMP1194]] to i32
42113 // SIMD-ONLY0-NEXT:    [[CMP1929:%.*]] = icmp slt i32 [[CONV1927]], [[CONV1928]]
42114 // SIMD-ONLY0-NEXT:    br i1 [[CMP1929]], label [[IF_THEN1931:%.*]], label [[IF_END1932:%.*]]
42115 // SIMD-ONLY0:       if.then1931:
42116 // SIMD-ONLY0-NEXT:    [[TMP1195:%.*]] = load i16, ptr [[SE]], align 2
42117 // SIMD-ONLY0-NEXT:    store i16 [[TMP1195]], ptr [[SX]], align 2
42118 // SIMD-ONLY0-NEXT:    br label [[IF_END1932]]
42119 // SIMD-ONLY0:       if.end1932:
42120 // SIMD-ONLY0-NEXT:    [[TMP1196:%.*]] = load i16, ptr [[SX]], align 2
42121 // SIMD-ONLY0-NEXT:    store i16 [[TMP1196]], ptr [[SV]], align 2
42122 // SIMD-ONLY0-NEXT:    [[TMP1197:%.*]] = load i16, ptr [[SX]], align 2
42123 // SIMD-ONLY0-NEXT:    [[CONV1933:%.*]] = sext i16 [[TMP1197]] to i32
42124 // SIMD-ONLY0-NEXT:    [[TMP1198:%.*]] = load i16, ptr [[SE]], align 2
42125 // SIMD-ONLY0-NEXT:    [[CONV1934:%.*]] = sext i16 [[TMP1198]] to i32
42126 // SIMD-ONLY0-NEXT:    [[CMP1935:%.*]] = icmp slt i32 [[CONV1933]], [[CONV1934]]
42127 // SIMD-ONLY0-NEXT:    br i1 [[CMP1935]], label [[IF_THEN1937:%.*]], label [[IF_END1938:%.*]]
42128 // SIMD-ONLY0:       if.then1937:
42129 // SIMD-ONLY0-NEXT:    [[TMP1199:%.*]] = load i16, ptr [[SE]], align 2
42130 // SIMD-ONLY0-NEXT:    store i16 [[TMP1199]], ptr [[SX]], align 2
42131 // SIMD-ONLY0-NEXT:    br label [[IF_END1938]]
42132 // SIMD-ONLY0:       if.end1938:
42133 // SIMD-ONLY0-NEXT:    [[TMP1200:%.*]] = load i16, ptr [[SX]], align 2
42134 // SIMD-ONLY0-NEXT:    store i16 [[TMP1200]], ptr [[SV]], align 2
42135 // SIMD-ONLY0-NEXT:    [[TMP1201:%.*]] = load i16, ptr [[SX]], align 2
42136 // SIMD-ONLY0-NEXT:    [[CONV1939:%.*]] = sext i16 [[TMP1201]] to i32
42137 // SIMD-ONLY0-NEXT:    [[TMP1202:%.*]] = load i16, ptr [[SE]], align 2
42138 // SIMD-ONLY0-NEXT:    [[CONV1940:%.*]] = sext i16 [[TMP1202]] to i32
42139 // SIMD-ONLY0-NEXT:    [[CMP1941:%.*]] = icmp eq i32 [[CONV1939]], [[CONV1940]]
42140 // SIMD-ONLY0-NEXT:    br i1 [[CMP1941]], label [[IF_THEN1943:%.*]], label [[IF_END1944:%.*]]
42141 // SIMD-ONLY0:       if.then1943:
42142 // SIMD-ONLY0-NEXT:    [[TMP1203:%.*]] = load i16, ptr [[SD]], align 2
42143 // SIMD-ONLY0-NEXT:    store i16 [[TMP1203]], ptr [[SX]], align 2
42144 // SIMD-ONLY0-NEXT:    br label [[IF_END1944]]
42145 // SIMD-ONLY0:       if.end1944:
42146 // SIMD-ONLY0-NEXT:    [[TMP1204:%.*]] = load i16, ptr [[SX]], align 2
42147 // SIMD-ONLY0-NEXT:    store i16 [[TMP1204]], ptr [[SV]], align 2
42148 // SIMD-ONLY0-NEXT:    [[TMP1205:%.*]] = load i16, ptr [[SE]], align 2
42149 // SIMD-ONLY0-NEXT:    [[CONV1945:%.*]] = sext i16 [[TMP1205]] to i32
42150 // SIMD-ONLY0-NEXT:    [[TMP1206:%.*]] = load i16, ptr [[SX]], align 2
42151 // SIMD-ONLY0-NEXT:    [[CONV1946:%.*]] = sext i16 [[TMP1206]] to i32
42152 // SIMD-ONLY0-NEXT:    [[CMP1947:%.*]] = icmp eq i32 [[CONV1945]], [[CONV1946]]
42153 // SIMD-ONLY0-NEXT:    br i1 [[CMP1947]], label [[IF_THEN1949:%.*]], label [[IF_END1950:%.*]]
42154 // SIMD-ONLY0:       if.then1949:
42155 // SIMD-ONLY0-NEXT:    [[TMP1207:%.*]] = load i16, ptr [[SD]], align 2
42156 // SIMD-ONLY0-NEXT:    store i16 [[TMP1207]], ptr [[SX]], align 2
42157 // SIMD-ONLY0-NEXT:    br label [[IF_END1950]]
42158 // SIMD-ONLY0:       if.end1950:
42159 // SIMD-ONLY0-NEXT:    [[TMP1208:%.*]] = load i16, ptr [[SE]], align 2
42160 // SIMD-ONLY0-NEXT:    [[CONV1951:%.*]] = sext i16 [[TMP1208]] to i32
42161 // SIMD-ONLY0-NEXT:    [[TMP1209:%.*]] = load i16, ptr [[SX]], align 2
42162 // SIMD-ONLY0-NEXT:    [[CONV1952:%.*]] = sext i16 [[TMP1209]] to i32
42163 // SIMD-ONLY0-NEXT:    [[CMP1953:%.*]] = icmp sgt i32 [[CONV1951]], [[CONV1952]]
42164 // SIMD-ONLY0-NEXT:    br i1 [[CMP1953]], label [[IF_THEN1955:%.*]], label [[IF_END1956:%.*]]
42165 // SIMD-ONLY0:       if.then1955:
42166 // SIMD-ONLY0-NEXT:    [[TMP1210:%.*]] = load i16, ptr [[SE]], align 2
42167 // SIMD-ONLY0-NEXT:    store i16 [[TMP1210]], ptr [[SX]], align 2
42168 // SIMD-ONLY0-NEXT:    br label [[IF_END1956]]
42169 // SIMD-ONLY0:       if.end1956:
42170 // SIMD-ONLY0-NEXT:    [[TMP1211:%.*]] = load i16, ptr [[SX]], align 2
42171 // SIMD-ONLY0-NEXT:    store i16 [[TMP1211]], ptr [[SV]], align 2
42172 // SIMD-ONLY0-NEXT:    [[TMP1212:%.*]] = load i16, ptr [[SX]], align 2
42173 // SIMD-ONLY0-NEXT:    [[CONV1957:%.*]] = sext i16 [[TMP1212]] to i32
42174 // SIMD-ONLY0-NEXT:    [[TMP1213:%.*]] = load i16, ptr [[SE]], align 2
42175 // SIMD-ONLY0-NEXT:    [[CONV1958:%.*]] = sext i16 [[TMP1213]] to i32
42176 // SIMD-ONLY0-NEXT:    [[CMP1959:%.*]] = icmp sgt i32 [[CONV1957]], [[CONV1958]]
42177 // SIMD-ONLY0-NEXT:    br i1 [[CMP1959]], label [[IF_THEN1961:%.*]], label [[IF_END1962:%.*]]
42178 // SIMD-ONLY0:       if.then1961:
42179 // SIMD-ONLY0-NEXT:    [[TMP1214:%.*]] = load i16, ptr [[SE]], align 2
42180 // SIMD-ONLY0-NEXT:    store i16 [[TMP1214]], ptr [[SX]], align 2
42181 // SIMD-ONLY0-NEXT:    br label [[IF_END1962]]
42182 // SIMD-ONLY0:       if.end1962:
42183 // SIMD-ONLY0-NEXT:    [[TMP1215:%.*]] = load i16, ptr [[SX]], align 2
42184 // SIMD-ONLY0-NEXT:    store i16 [[TMP1215]], ptr [[SV]], align 2
42185 // SIMD-ONLY0-NEXT:    [[TMP1216:%.*]] = load i16, ptr [[SE]], align 2
42186 // SIMD-ONLY0-NEXT:    [[CONV1963:%.*]] = sext i16 [[TMP1216]] to i32
42187 // SIMD-ONLY0-NEXT:    [[TMP1217:%.*]] = load i16, ptr [[SX]], align 2
42188 // SIMD-ONLY0-NEXT:    [[CONV1964:%.*]] = sext i16 [[TMP1217]] to i32
42189 // SIMD-ONLY0-NEXT:    [[CMP1965:%.*]] = icmp slt i32 [[CONV1963]], [[CONV1964]]
42190 // SIMD-ONLY0-NEXT:    br i1 [[CMP1965]], label [[IF_THEN1967:%.*]], label [[IF_END1968:%.*]]
42191 // SIMD-ONLY0:       if.then1967:
42192 // SIMD-ONLY0-NEXT:    [[TMP1218:%.*]] = load i16, ptr [[SE]], align 2
42193 // SIMD-ONLY0-NEXT:    store i16 [[TMP1218]], ptr [[SX]], align 2
42194 // SIMD-ONLY0-NEXT:    br label [[IF_END1968]]
42195 // SIMD-ONLY0:       if.end1968:
42196 // SIMD-ONLY0-NEXT:    [[TMP1219:%.*]] = load i16, ptr [[SX]], align 2
42197 // SIMD-ONLY0-NEXT:    store i16 [[TMP1219]], ptr [[SV]], align 2
42198 // SIMD-ONLY0-NEXT:    [[TMP1220:%.*]] = load i16, ptr [[SX]], align 2
42199 // SIMD-ONLY0-NEXT:    [[CONV1969:%.*]] = sext i16 [[TMP1220]] to i32
42200 // SIMD-ONLY0-NEXT:    [[TMP1221:%.*]] = load i16, ptr [[SE]], align 2
42201 // SIMD-ONLY0-NEXT:    [[CONV1970:%.*]] = sext i16 [[TMP1221]] to i32
42202 // SIMD-ONLY0-NEXT:    [[CMP1971:%.*]] = icmp slt i32 [[CONV1969]], [[CONV1970]]
42203 // SIMD-ONLY0-NEXT:    br i1 [[CMP1971]], label [[IF_THEN1973:%.*]], label [[IF_END1974:%.*]]
42204 // SIMD-ONLY0:       if.then1973:
42205 // SIMD-ONLY0-NEXT:    [[TMP1222:%.*]] = load i16, ptr [[SE]], align 2
42206 // SIMD-ONLY0-NEXT:    store i16 [[TMP1222]], ptr [[SX]], align 2
42207 // SIMD-ONLY0-NEXT:    br label [[IF_END1974]]
42208 // SIMD-ONLY0:       if.end1974:
42209 // SIMD-ONLY0-NEXT:    [[TMP1223:%.*]] = load i16, ptr [[SX]], align 2
42210 // SIMD-ONLY0-NEXT:    store i16 [[TMP1223]], ptr [[SV]], align 2
42211 // SIMD-ONLY0-NEXT:    [[TMP1224:%.*]] = load i16, ptr [[SX]], align 2
42212 // SIMD-ONLY0-NEXT:    [[CONV1975:%.*]] = sext i16 [[TMP1224]] to i32
42213 // SIMD-ONLY0-NEXT:    [[TMP1225:%.*]] = load i16, ptr [[SE]], align 2
42214 // SIMD-ONLY0-NEXT:    [[CONV1976:%.*]] = sext i16 [[TMP1225]] to i32
42215 // SIMD-ONLY0-NEXT:    [[CMP1977:%.*]] = icmp eq i32 [[CONV1975]], [[CONV1976]]
42216 // SIMD-ONLY0-NEXT:    br i1 [[CMP1977]], label [[IF_THEN1979:%.*]], label [[IF_END1980:%.*]]
42217 // SIMD-ONLY0:       if.then1979:
42218 // SIMD-ONLY0-NEXT:    [[TMP1226:%.*]] = load i16, ptr [[SD]], align 2
42219 // SIMD-ONLY0-NEXT:    store i16 [[TMP1226]], ptr [[SX]], align 2
42220 // SIMD-ONLY0-NEXT:    br label [[IF_END1980]]
42221 // SIMD-ONLY0:       if.end1980:
42222 // SIMD-ONLY0-NEXT:    [[TMP1227:%.*]] = load i16, ptr [[SX]], align 2
42223 // SIMD-ONLY0-NEXT:    store i16 [[TMP1227]], ptr [[SV]], align 2
42224 // SIMD-ONLY0-NEXT:    [[TMP1228:%.*]] = load i16, ptr [[SE]], align 2
42225 // SIMD-ONLY0-NEXT:    [[CONV1981:%.*]] = sext i16 [[TMP1228]] to i32
42226 // SIMD-ONLY0-NEXT:    [[TMP1229:%.*]] = load i16, ptr [[SX]], align 2
42227 // SIMD-ONLY0-NEXT:    [[CONV1982:%.*]] = sext i16 [[TMP1229]] to i32
42228 // SIMD-ONLY0-NEXT:    [[CMP1983:%.*]] = icmp eq i32 [[CONV1981]], [[CONV1982]]
42229 // SIMD-ONLY0-NEXT:    br i1 [[CMP1983]], label [[IF_THEN1985:%.*]], label [[IF_END1986:%.*]]
42230 // SIMD-ONLY0:       if.then1985:
42231 // SIMD-ONLY0-NEXT:    [[TMP1230:%.*]] = load i16, ptr [[SD]], align 2
42232 // SIMD-ONLY0-NEXT:    store i16 [[TMP1230]], ptr [[SX]], align 2
42233 // SIMD-ONLY0-NEXT:    br label [[IF_END1986]]
42234 // SIMD-ONLY0:       if.end1986:
42235 // SIMD-ONLY0-NEXT:    [[TMP1231:%.*]] = load i16, ptr [[SX]], align 2
42236 // SIMD-ONLY0-NEXT:    store i16 [[TMP1231]], ptr [[SV]], align 2
42237 // SIMD-ONLY0-NEXT:    [[TMP1232:%.*]] = load i16, ptr [[SX]], align 2
42238 // SIMD-ONLY0-NEXT:    [[CONV1987:%.*]] = sext i16 [[TMP1232]] to i32
42239 // SIMD-ONLY0-NEXT:    [[TMP1233:%.*]] = load i16, ptr [[SE]], align 2
42240 // SIMD-ONLY0-NEXT:    [[CONV1988:%.*]] = sext i16 [[TMP1233]] to i32
42241 // SIMD-ONLY0-NEXT:    [[CMP1989:%.*]] = icmp eq i32 [[CONV1987]], [[CONV1988]]
42242 // SIMD-ONLY0-NEXT:    br i1 [[CMP1989]], label [[IF_THEN1991:%.*]], label [[IF_ELSE1992:%.*]]
42243 // SIMD-ONLY0:       if.then1991:
42244 // SIMD-ONLY0-NEXT:    [[TMP1234:%.*]] = load i16, ptr [[SD]], align 2
42245 // SIMD-ONLY0-NEXT:    store i16 [[TMP1234]], ptr [[SX]], align 2
42246 // SIMD-ONLY0-NEXT:    br label [[IF_END1993:%.*]]
42247 // SIMD-ONLY0:       if.else1992:
42248 // SIMD-ONLY0-NEXT:    [[TMP1235:%.*]] = load i16, ptr [[SX]], align 2
42249 // SIMD-ONLY0-NEXT:    store i16 [[TMP1235]], ptr [[SV]], align 2
42250 // SIMD-ONLY0-NEXT:    br label [[IF_END1993]]
42251 // SIMD-ONLY0:       if.end1993:
42252 // SIMD-ONLY0-NEXT:    [[TMP1236:%.*]] = load i16, ptr [[SE]], align 2
42253 // SIMD-ONLY0-NEXT:    [[CONV1994:%.*]] = sext i16 [[TMP1236]] to i32
42254 // SIMD-ONLY0-NEXT:    [[TMP1237:%.*]] = load i16, ptr [[SX]], align 2
42255 // SIMD-ONLY0-NEXT:    [[CONV1995:%.*]] = sext i16 [[TMP1237]] to i32
42256 // SIMD-ONLY0-NEXT:    [[CMP1996:%.*]] = icmp eq i32 [[CONV1994]], [[CONV1995]]
42257 // SIMD-ONLY0-NEXT:    br i1 [[CMP1996]], label [[IF_THEN1998:%.*]], label [[IF_ELSE1999:%.*]]
42258 // SIMD-ONLY0:       if.then1998:
42259 // SIMD-ONLY0-NEXT:    [[TMP1238:%.*]] = load i16, ptr [[SD]], align 2
42260 // SIMD-ONLY0-NEXT:    store i16 [[TMP1238]], ptr [[SX]], align 2
42261 // SIMD-ONLY0-NEXT:    br label [[IF_END2000:%.*]]
42262 // SIMD-ONLY0:       if.else1999:
42263 // SIMD-ONLY0-NEXT:    [[TMP1239:%.*]] = load i16, ptr [[SX]], align 2
42264 // SIMD-ONLY0-NEXT:    store i16 [[TMP1239]], ptr [[SV]], align 2
42265 // SIMD-ONLY0-NEXT:    br label [[IF_END2000]]
42266 // SIMD-ONLY0:       if.end2000:
42267 // SIMD-ONLY0-NEXT:    [[TMP1240:%.*]] = load i16, ptr [[SX]], align 2
42268 // SIMD-ONLY0-NEXT:    [[CONV2001:%.*]] = sext i16 [[TMP1240]] to i32
42269 // SIMD-ONLY0-NEXT:    [[TMP1241:%.*]] = load i16, ptr [[SE]], align 2
42270 // SIMD-ONLY0-NEXT:    [[CONV2002:%.*]] = sext i16 [[TMP1241]] to i32
42271 // SIMD-ONLY0-NEXT:    [[CMP2003:%.*]] = icmp eq i32 [[CONV2001]], [[CONV2002]]
42272 // SIMD-ONLY0-NEXT:    [[CONV2004:%.*]] = zext i1 [[CMP2003]] to i32
42273 // SIMD-ONLY0-NEXT:    [[CONV2005:%.*]] = trunc i32 [[CONV2004]] to i16
42274 // SIMD-ONLY0-NEXT:    store i16 [[CONV2005]], ptr [[SR]], align 2
42275 // SIMD-ONLY0-NEXT:    [[TMP1242:%.*]] = load i16, ptr [[SR]], align 2
42276 // SIMD-ONLY0-NEXT:    [[TOBOOL2006:%.*]] = icmp ne i16 [[TMP1242]], 0
42277 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2006]], label [[IF_THEN2007:%.*]], label [[IF_END2008:%.*]]
42278 // SIMD-ONLY0:       if.then2007:
42279 // SIMD-ONLY0-NEXT:    [[TMP1243:%.*]] = load i16, ptr [[SD]], align 2
42280 // SIMD-ONLY0-NEXT:    store i16 [[TMP1243]], ptr [[SX]], align 2
42281 // SIMD-ONLY0-NEXT:    br label [[IF_END2008]]
42282 // SIMD-ONLY0:       if.end2008:
42283 // SIMD-ONLY0-NEXT:    [[TMP1244:%.*]] = load i16, ptr [[SE]], align 2
42284 // SIMD-ONLY0-NEXT:    [[CONV2009:%.*]] = sext i16 [[TMP1244]] to i32
42285 // SIMD-ONLY0-NEXT:    [[TMP1245:%.*]] = load i16, ptr [[SX]], align 2
42286 // SIMD-ONLY0-NEXT:    [[CONV2010:%.*]] = sext i16 [[TMP1245]] to i32
42287 // SIMD-ONLY0-NEXT:    [[CMP2011:%.*]] = icmp eq i32 [[CONV2009]], [[CONV2010]]
42288 // SIMD-ONLY0-NEXT:    [[CONV2012:%.*]] = zext i1 [[CMP2011]] to i32
42289 // SIMD-ONLY0-NEXT:    [[CONV2013:%.*]] = trunc i32 [[CONV2012]] to i16
42290 // SIMD-ONLY0-NEXT:    store i16 [[CONV2013]], ptr [[SR]], align 2
42291 // SIMD-ONLY0-NEXT:    [[TMP1246:%.*]] = load i16, ptr [[SR]], align 2
42292 // SIMD-ONLY0-NEXT:    [[TOBOOL2014:%.*]] = icmp ne i16 [[TMP1246]], 0
42293 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2014]], label [[IF_THEN2015:%.*]], label [[IF_END2016:%.*]]
42294 // SIMD-ONLY0:       if.then2015:
42295 // SIMD-ONLY0-NEXT:    [[TMP1247:%.*]] = load i16, ptr [[SD]], align 2
42296 // SIMD-ONLY0-NEXT:    store i16 [[TMP1247]], ptr [[SX]], align 2
42297 // SIMD-ONLY0-NEXT:    br label [[IF_END2016]]
42298 // SIMD-ONLY0:       if.end2016:
42299 // SIMD-ONLY0-NEXT:    [[TMP1248:%.*]] = load i16, ptr [[SX]], align 2
42300 // SIMD-ONLY0-NEXT:    [[CONV2017:%.*]] = sext i16 [[TMP1248]] to i32
42301 // SIMD-ONLY0-NEXT:    [[TMP1249:%.*]] = load i16, ptr [[SE]], align 2
42302 // SIMD-ONLY0-NEXT:    [[CONV2018:%.*]] = sext i16 [[TMP1249]] to i32
42303 // SIMD-ONLY0-NEXT:    [[CMP2019:%.*]] = icmp eq i32 [[CONV2017]], [[CONV2018]]
42304 // SIMD-ONLY0-NEXT:    [[CONV2020:%.*]] = zext i1 [[CMP2019]] to i32
42305 // SIMD-ONLY0-NEXT:    [[CONV2021:%.*]] = trunc i32 [[CONV2020]] to i16
42306 // SIMD-ONLY0-NEXT:    store i16 [[CONV2021]], ptr [[SR]], align 2
42307 // SIMD-ONLY0-NEXT:    [[TMP1250:%.*]] = load i16, ptr [[SR]], align 2
42308 // SIMD-ONLY0-NEXT:    [[TOBOOL2022:%.*]] = icmp ne i16 [[TMP1250]], 0
42309 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2022]], label [[IF_THEN2023:%.*]], label [[IF_ELSE2024:%.*]]
42310 // SIMD-ONLY0:       if.then2023:
42311 // SIMD-ONLY0-NEXT:    [[TMP1251:%.*]] = load i16, ptr [[SD]], align 2
42312 // SIMD-ONLY0-NEXT:    store i16 [[TMP1251]], ptr [[SX]], align 2
42313 // SIMD-ONLY0-NEXT:    br label [[IF_END2025:%.*]]
42314 // SIMD-ONLY0:       if.else2024:
42315 // SIMD-ONLY0-NEXT:    [[TMP1252:%.*]] = load i16, ptr [[SX]], align 2
42316 // SIMD-ONLY0-NEXT:    store i16 [[TMP1252]], ptr [[SV]], align 2
42317 // SIMD-ONLY0-NEXT:    br label [[IF_END2025]]
42318 // SIMD-ONLY0:       if.end2025:
42319 // SIMD-ONLY0-NEXT:    [[TMP1253:%.*]] = load i16, ptr [[SE]], align 2
42320 // SIMD-ONLY0-NEXT:    [[CONV2026:%.*]] = sext i16 [[TMP1253]] to i32
42321 // SIMD-ONLY0-NEXT:    [[TMP1254:%.*]] = load i16, ptr [[SX]], align 2
42322 // SIMD-ONLY0-NEXT:    [[CONV2027:%.*]] = sext i16 [[TMP1254]] to i32
42323 // SIMD-ONLY0-NEXT:    [[CMP2028:%.*]] = icmp eq i32 [[CONV2026]], [[CONV2027]]
42324 // SIMD-ONLY0-NEXT:    [[CONV2029:%.*]] = zext i1 [[CMP2028]] to i32
42325 // SIMD-ONLY0-NEXT:    [[CONV2030:%.*]] = trunc i32 [[CONV2029]] to i16
42326 // SIMD-ONLY0-NEXT:    store i16 [[CONV2030]], ptr [[SR]], align 2
42327 // SIMD-ONLY0-NEXT:    [[TMP1255:%.*]] = load i16, ptr [[SR]], align 2
42328 // SIMD-ONLY0-NEXT:    [[TOBOOL2031:%.*]] = icmp ne i16 [[TMP1255]], 0
42329 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2031]], label [[IF_THEN2032:%.*]], label [[IF_ELSE2033:%.*]]
42330 // SIMD-ONLY0:       if.then2032:
42331 // SIMD-ONLY0-NEXT:    [[TMP1256:%.*]] = load i16, ptr [[SD]], align 2
42332 // SIMD-ONLY0-NEXT:    store i16 [[TMP1256]], ptr [[SX]], align 2
42333 // SIMD-ONLY0-NEXT:    br label [[IF_END2034:%.*]]
42334 // SIMD-ONLY0:       if.else2033:
42335 // SIMD-ONLY0-NEXT:    [[TMP1257:%.*]] = load i16, ptr [[SX]], align 2
42336 // SIMD-ONLY0-NEXT:    store i16 [[TMP1257]], ptr [[SV]], align 2
42337 // SIMD-ONLY0-NEXT:    br label [[IF_END2034]]
42338 // SIMD-ONLY0:       if.end2034:
42339 // SIMD-ONLY0-NEXT:    [[TMP1258:%.*]] = load i16, ptr [[SX]], align 2
42340 // SIMD-ONLY0-NEXT:    store i16 [[TMP1258]], ptr [[SV]], align 2
42341 // SIMD-ONLY0-NEXT:    [[TMP1259:%.*]] = load i16, ptr [[SE]], align 2
42342 // SIMD-ONLY0-NEXT:    [[CONV2035:%.*]] = sext i16 [[TMP1259]] to i32
42343 // SIMD-ONLY0-NEXT:    [[TMP1260:%.*]] = load i16, ptr [[SX]], align 2
42344 // SIMD-ONLY0-NEXT:    [[CONV2036:%.*]] = sext i16 [[TMP1260]] to i32
42345 // SIMD-ONLY0-NEXT:    [[CMP2037:%.*]] = icmp sgt i32 [[CONV2035]], [[CONV2036]]
42346 // SIMD-ONLY0-NEXT:    br i1 [[CMP2037]], label [[IF_THEN2039:%.*]], label [[IF_END2040:%.*]]
42347 // SIMD-ONLY0:       if.then2039:
42348 // SIMD-ONLY0-NEXT:    [[TMP1261:%.*]] = load i16, ptr [[SE]], align 2
42349 // SIMD-ONLY0-NEXT:    store i16 [[TMP1261]], ptr [[SX]], align 2
42350 // SIMD-ONLY0-NEXT:    br label [[IF_END2040]]
42351 // SIMD-ONLY0:       if.end2040:
42352 // SIMD-ONLY0-NEXT:    [[TMP1262:%.*]] = load i16, ptr [[SX]], align 2
42353 // SIMD-ONLY0-NEXT:    store i16 [[TMP1262]], ptr [[SV]], align 2
42354 // SIMD-ONLY0-NEXT:    [[TMP1263:%.*]] = load i16, ptr [[SX]], align 2
42355 // SIMD-ONLY0-NEXT:    [[CONV2041:%.*]] = sext i16 [[TMP1263]] to i32
42356 // SIMD-ONLY0-NEXT:    [[TMP1264:%.*]] = load i16, ptr [[SE]], align 2
42357 // SIMD-ONLY0-NEXT:    [[CONV2042:%.*]] = sext i16 [[TMP1264]] to i32
42358 // SIMD-ONLY0-NEXT:    [[CMP2043:%.*]] = icmp sgt i32 [[CONV2041]], [[CONV2042]]
42359 // SIMD-ONLY0-NEXT:    br i1 [[CMP2043]], label [[IF_THEN2045:%.*]], label [[IF_END2046:%.*]]
42360 // SIMD-ONLY0:       if.then2045:
42361 // SIMD-ONLY0-NEXT:    [[TMP1265:%.*]] = load i16, ptr [[SE]], align 2
42362 // SIMD-ONLY0-NEXT:    store i16 [[TMP1265]], ptr [[SX]], align 2
42363 // SIMD-ONLY0-NEXT:    br label [[IF_END2046]]
42364 // SIMD-ONLY0:       if.end2046:
42365 // SIMD-ONLY0-NEXT:    [[TMP1266:%.*]] = load i16, ptr [[SX]], align 2
42366 // SIMD-ONLY0-NEXT:    store i16 [[TMP1266]], ptr [[SV]], align 2
42367 // SIMD-ONLY0-NEXT:    [[TMP1267:%.*]] = load i16, ptr [[SE]], align 2
42368 // SIMD-ONLY0-NEXT:    [[CONV2047:%.*]] = sext i16 [[TMP1267]] to i32
42369 // SIMD-ONLY0-NEXT:    [[TMP1268:%.*]] = load i16, ptr [[SX]], align 2
42370 // SIMD-ONLY0-NEXT:    [[CONV2048:%.*]] = sext i16 [[TMP1268]] to i32
42371 // SIMD-ONLY0-NEXT:    [[CMP2049:%.*]] = icmp slt i32 [[CONV2047]], [[CONV2048]]
42372 // SIMD-ONLY0-NEXT:    br i1 [[CMP2049]], label [[IF_THEN2051:%.*]], label [[IF_END2052:%.*]]
42373 // SIMD-ONLY0:       if.then2051:
42374 // SIMD-ONLY0-NEXT:    [[TMP1269:%.*]] = load i16, ptr [[SE]], align 2
42375 // SIMD-ONLY0-NEXT:    store i16 [[TMP1269]], ptr [[SX]], align 2
42376 // SIMD-ONLY0-NEXT:    br label [[IF_END2052]]
42377 // SIMD-ONLY0:       if.end2052:
42378 // SIMD-ONLY0-NEXT:    [[TMP1270:%.*]] = load i16, ptr [[SX]], align 2
42379 // SIMD-ONLY0-NEXT:    store i16 [[TMP1270]], ptr [[SV]], align 2
42380 // SIMD-ONLY0-NEXT:    [[TMP1271:%.*]] = load i16, ptr [[SX]], align 2
42381 // SIMD-ONLY0-NEXT:    [[CONV2053:%.*]] = sext i16 [[TMP1271]] to i32
42382 // SIMD-ONLY0-NEXT:    [[TMP1272:%.*]] = load i16, ptr [[SE]], align 2
42383 // SIMD-ONLY0-NEXT:    [[CONV2054:%.*]] = sext i16 [[TMP1272]] to i32
42384 // SIMD-ONLY0-NEXT:    [[CMP2055:%.*]] = icmp slt i32 [[CONV2053]], [[CONV2054]]
42385 // SIMD-ONLY0-NEXT:    br i1 [[CMP2055]], label [[IF_THEN2057:%.*]], label [[IF_END2058:%.*]]
42386 // SIMD-ONLY0:       if.then2057:
42387 // SIMD-ONLY0-NEXT:    [[TMP1273:%.*]] = load i16, ptr [[SE]], align 2
42388 // SIMD-ONLY0-NEXT:    store i16 [[TMP1273]], ptr [[SX]], align 2
42389 // SIMD-ONLY0-NEXT:    br label [[IF_END2058]]
42390 // SIMD-ONLY0:       if.end2058:
42391 // SIMD-ONLY0-NEXT:    [[TMP1274:%.*]] = load i16, ptr [[SX]], align 2
42392 // SIMD-ONLY0-NEXT:    store i16 [[TMP1274]], ptr [[SV]], align 2
42393 // SIMD-ONLY0-NEXT:    [[TMP1275:%.*]] = load i16, ptr [[SX]], align 2
42394 // SIMD-ONLY0-NEXT:    [[CONV2059:%.*]] = sext i16 [[TMP1275]] to i32
42395 // SIMD-ONLY0-NEXT:    [[TMP1276:%.*]] = load i16, ptr [[SE]], align 2
42396 // SIMD-ONLY0-NEXT:    [[CONV2060:%.*]] = sext i16 [[TMP1276]] to i32
42397 // SIMD-ONLY0-NEXT:    [[CMP2061:%.*]] = icmp eq i32 [[CONV2059]], [[CONV2060]]
42398 // SIMD-ONLY0-NEXT:    br i1 [[CMP2061]], label [[IF_THEN2063:%.*]], label [[IF_END2064:%.*]]
42399 // SIMD-ONLY0:       if.then2063:
42400 // SIMD-ONLY0-NEXT:    [[TMP1277:%.*]] = load i16, ptr [[SD]], align 2
42401 // SIMD-ONLY0-NEXT:    store i16 [[TMP1277]], ptr [[SX]], align 2
42402 // SIMD-ONLY0-NEXT:    br label [[IF_END2064]]
42403 // SIMD-ONLY0:       if.end2064:
42404 // SIMD-ONLY0-NEXT:    [[TMP1278:%.*]] = load i16, ptr [[SX]], align 2
42405 // SIMD-ONLY0-NEXT:    store i16 [[TMP1278]], ptr [[SV]], align 2
42406 // SIMD-ONLY0-NEXT:    [[TMP1279:%.*]] = load i16, ptr [[SE]], align 2
42407 // SIMD-ONLY0-NEXT:    [[CONV2065:%.*]] = sext i16 [[TMP1279]] to i32
42408 // SIMD-ONLY0-NEXT:    [[TMP1280:%.*]] = load i16, ptr [[SX]], align 2
42409 // SIMD-ONLY0-NEXT:    [[CONV2066:%.*]] = sext i16 [[TMP1280]] to i32
42410 // SIMD-ONLY0-NEXT:    [[CMP2067:%.*]] = icmp eq i32 [[CONV2065]], [[CONV2066]]
42411 // SIMD-ONLY0-NEXT:    br i1 [[CMP2067]], label [[IF_THEN2069:%.*]], label [[IF_END2070:%.*]]
42412 // SIMD-ONLY0:       if.then2069:
42413 // SIMD-ONLY0-NEXT:    [[TMP1281:%.*]] = load i16, ptr [[SD]], align 2
42414 // SIMD-ONLY0-NEXT:    store i16 [[TMP1281]], ptr [[SX]], align 2
42415 // SIMD-ONLY0-NEXT:    br label [[IF_END2070]]
42416 // SIMD-ONLY0:       if.end2070:
42417 // SIMD-ONLY0-NEXT:    [[TMP1282:%.*]] = load i16, ptr [[SE]], align 2
42418 // SIMD-ONLY0-NEXT:    [[CONV2071:%.*]] = sext i16 [[TMP1282]] to i32
42419 // SIMD-ONLY0-NEXT:    [[TMP1283:%.*]] = load i16, ptr [[SX]], align 2
42420 // SIMD-ONLY0-NEXT:    [[CONV2072:%.*]] = sext i16 [[TMP1283]] to i32
42421 // SIMD-ONLY0-NEXT:    [[CMP2073:%.*]] = icmp sgt i32 [[CONV2071]], [[CONV2072]]
42422 // SIMD-ONLY0-NEXT:    br i1 [[CMP2073]], label [[IF_THEN2075:%.*]], label [[IF_END2076:%.*]]
42423 // SIMD-ONLY0:       if.then2075:
42424 // SIMD-ONLY0-NEXT:    [[TMP1284:%.*]] = load i16, ptr [[SE]], align 2
42425 // SIMD-ONLY0-NEXT:    store i16 [[TMP1284]], ptr [[SX]], align 2
42426 // SIMD-ONLY0-NEXT:    br label [[IF_END2076]]
42427 // SIMD-ONLY0:       if.end2076:
42428 // SIMD-ONLY0-NEXT:    [[TMP1285:%.*]] = load i16, ptr [[SX]], align 2
42429 // SIMD-ONLY0-NEXT:    store i16 [[TMP1285]], ptr [[SV]], align 2
42430 // SIMD-ONLY0-NEXT:    [[TMP1286:%.*]] = load i16, ptr [[SX]], align 2
42431 // SIMD-ONLY0-NEXT:    [[CONV2077:%.*]] = sext i16 [[TMP1286]] to i32
42432 // SIMD-ONLY0-NEXT:    [[TMP1287:%.*]] = load i16, ptr [[SE]], align 2
42433 // SIMD-ONLY0-NEXT:    [[CONV2078:%.*]] = sext i16 [[TMP1287]] to i32
42434 // SIMD-ONLY0-NEXT:    [[CMP2079:%.*]] = icmp sgt i32 [[CONV2077]], [[CONV2078]]
42435 // SIMD-ONLY0-NEXT:    br i1 [[CMP2079]], label [[IF_THEN2081:%.*]], label [[IF_END2082:%.*]]
42436 // SIMD-ONLY0:       if.then2081:
42437 // SIMD-ONLY0-NEXT:    [[TMP1288:%.*]] = load i16, ptr [[SE]], align 2
42438 // SIMD-ONLY0-NEXT:    store i16 [[TMP1288]], ptr [[SX]], align 2
42439 // SIMD-ONLY0-NEXT:    br label [[IF_END2082]]
42440 // SIMD-ONLY0:       if.end2082:
42441 // SIMD-ONLY0-NEXT:    [[TMP1289:%.*]] = load i16, ptr [[SX]], align 2
42442 // SIMD-ONLY0-NEXT:    store i16 [[TMP1289]], ptr [[SV]], align 2
42443 // SIMD-ONLY0-NEXT:    [[TMP1290:%.*]] = load i16, ptr [[SE]], align 2
42444 // SIMD-ONLY0-NEXT:    [[CONV2083:%.*]] = sext i16 [[TMP1290]] to i32
42445 // SIMD-ONLY0-NEXT:    [[TMP1291:%.*]] = load i16, ptr [[SX]], align 2
42446 // SIMD-ONLY0-NEXT:    [[CONV2084:%.*]] = sext i16 [[TMP1291]] to i32
42447 // SIMD-ONLY0-NEXT:    [[CMP2085:%.*]] = icmp slt i32 [[CONV2083]], [[CONV2084]]
42448 // SIMD-ONLY0-NEXT:    br i1 [[CMP2085]], label [[IF_THEN2087:%.*]], label [[IF_END2088:%.*]]
42449 // SIMD-ONLY0:       if.then2087:
42450 // SIMD-ONLY0-NEXT:    [[TMP1292:%.*]] = load i16, ptr [[SE]], align 2
42451 // SIMD-ONLY0-NEXT:    store i16 [[TMP1292]], ptr [[SX]], align 2
42452 // SIMD-ONLY0-NEXT:    br label [[IF_END2088]]
42453 // SIMD-ONLY0:       if.end2088:
42454 // SIMD-ONLY0-NEXT:    [[TMP1293:%.*]] = load i16, ptr [[SX]], align 2
42455 // SIMD-ONLY0-NEXT:    store i16 [[TMP1293]], ptr [[SV]], align 2
42456 // SIMD-ONLY0-NEXT:    [[TMP1294:%.*]] = load i16, ptr [[SX]], align 2
42457 // SIMD-ONLY0-NEXT:    [[CONV2089:%.*]] = sext i16 [[TMP1294]] to i32
42458 // SIMD-ONLY0-NEXT:    [[TMP1295:%.*]] = load i16, ptr [[SE]], align 2
42459 // SIMD-ONLY0-NEXT:    [[CONV2090:%.*]] = sext i16 [[TMP1295]] to i32
42460 // SIMD-ONLY0-NEXT:    [[CMP2091:%.*]] = icmp slt i32 [[CONV2089]], [[CONV2090]]
42461 // SIMD-ONLY0-NEXT:    br i1 [[CMP2091]], label [[IF_THEN2093:%.*]], label [[IF_END2094:%.*]]
42462 // SIMD-ONLY0:       if.then2093:
42463 // SIMD-ONLY0-NEXT:    [[TMP1296:%.*]] = load i16, ptr [[SE]], align 2
42464 // SIMD-ONLY0-NEXT:    store i16 [[TMP1296]], ptr [[SX]], align 2
42465 // SIMD-ONLY0-NEXT:    br label [[IF_END2094]]
42466 // SIMD-ONLY0:       if.end2094:
42467 // SIMD-ONLY0-NEXT:    [[TMP1297:%.*]] = load i16, ptr [[SX]], align 2
42468 // SIMD-ONLY0-NEXT:    store i16 [[TMP1297]], ptr [[SV]], align 2
42469 // SIMD-ONLY0-NEXT:    [[TMP1298:%.*]] = load i16, ptr [[SX]], align 2
42470 // SIMD-ONLY0-NEXT:    [[CONV2095:%.*]] = sext i16 [[TMP1298]] to i32
42471 // SIMD-ONLY0-NEXT:    [[TMP1299:%.*]] = load i16, ptr [[SE]], align 2
42472 // SIMD-ONLY0-NEXT:    [[CONV2096:%.*]] = sext i16 [[TMP1299]] to i32
42473 // SIMD-ONLY0-NEXT:    [[CMP2097:%.*]] = icmp eq i32 [[CONV2095]], [[CONV2096]]
42474 // SIMD-ONLY0-NEXT:    br i1 [[CMP2097]], label [[IF_THEN2099:%.*]], label [[IF_END2100:%.*]]
42475 // SIMD-ONLY0:       if.then2099:
42476 // SIMD-ONLY0-NEXT:    [[TMP1300:%.*]] = load i16, ptr [[SD]], align 2
42477 // SIMD-ONLY0-NEXT:    store i16 [[TMP1300]], ptr [[SX]], align 2
42478 // SIMD-ONLY0-NEXT:    br label [[IF_END2100]]
42479 // SIMD-ONLY0:       if.end2100:
42480 // SIMD-ONLY0-NEXT:    [[TMP1301:%.*]] = load i16, ptr [[SX]], align 2
42481 // SIMD-ONLY0-NEXT:    store i16 [[TMP1301]], ptr [[SV]], align 2
42482 // SIMD-ONLY0-NEXT:    [[TMP1302:%.*]] = load i16, ptr [[SE]], align 2
42483 // SIMD-ONLY0-NEXT:    [[CONV2101:%.*]] = sext i16 [[TMP1302]] to i32
42484 // SIMD-ONLY0-NEXT:    [[TMP1303:%.*]] = load i16, ptr [[SX]], align 2
42485 // SIMD-ONLY0-NEXT:    [[CONV2102:%.*]] = sext i16 [[TMP1303]] to i32
42486 // SIMD-ONLY0-NEXT:    [[CMP2103:%.*]] = icmp eq i32 [[CONV2101]], [[CONV2102]]
42487 // SIMD-ONLY0-NEXT:    br i1 [[CMP2103]], label [[IF_THEN2105:%.*]], label [[IF_END2106:%.*]]
42488 // SIMD-ONLY0:       if.then2105:
42489 // SIMD-ONLY0-NEXT:    [[TMP1304:%.*]] = load i16, ptr [[SD]], align 2
42490 // SIMD-ONLY0-NEXT:    store i16 [[TMP1304]], ptr [[SX]], align 2
42491 // SIMD-ONLY0-NEXT:    br label [[IF_END2106]]
42492 // SIMD-ONLY0:       if.end2106:
42493 // SIMD-ONLY0-NEXT:    [[TMP1305:%.*]] = load i16, ptr [[SX]], align 2
42494 // SIMD-ONLY0-NEXT:    store i16 [[TMP1305]], ptr [[SV]], align 2
42495 // SIMD-ONLY0-NEXT:    [[TMP1306:%.*]] = load i16, ptr [[SX]], align 2
42496 // SIMD-ONLY0-NEXT:    [[CONV2107:%.*]] = sext i16 [[TMP1306]] to i32
42497 // SIMD-ONLY0-NEXT:    [[TMP1307:%.*]] = load i16, ptr [[SE]], align 2
42498 // SIMD-ONLY0-NEXT:    [[CONV2108:%.*]] = sext i16 [[TMP1307]] to i32
42499 // SIMD-ONLY0-NEXT:    [[CMP2109:%.*]] = icmp eq i32 [[CONV2107]], [[CONV2108]]
42500 // SIMD-ONLY0-NEXT:    br i1 [[CMP2109]], label [[IF_THEN2111:%.*]], label [[IF_ELSE2112:%.*]]
42501 // SIMD-ONLY0:       if.then2111:
42502 // SIMD-ONLY0-NEXT:    [[TMP1308:%.*]] = load i16, ptr [[SD]], align 2
42503 // SIMD-ONLY0-NEXT:    store i16 [[TMP1308]], ptr [[SX]], align 2
42504 // SIMD-ONLY0-NEXT:    br label [[IF_END2113:%.*]]
42505 // SIMD-ONLY0:       if.else2112:
42506 // SIMD-ONLY0-NEXT:    [[TMP1309:%.*]] = load i16, ptr [[SX]], align 2
42507 // SIMD-ONLY0-NEXT:    store i16 [[TMP1309]], ptr [[SV]], align 2
42508 // SIMD-ONLY0-NEXT:    br label [[IF_END2113]]
42509 // SIMD-ONLY0:       if.end2113:
42510 // SIMD-ONLY0-NEXT:    [[TMP1310:%.*]] = load i16, ptr [[SE]], align 2
42511 // SIMD-ONLY0-NEXT:    [[CONV2114:%.*]] = sext i16 [[TMP1310]] to i32
42512 // SIMD-ONLY0-NEXT:    [[TMP1311:%.*]] = load i16, ptr [[SX]], align 2
42513 // SIMD-ONLY0-NEXT:    [[CONV2115:%.*]] = sext i16 [[TMP1311]] to i32
42514 // SIMD-ONLY0-NEXT:    [[CMP2116:%.*]] = icmp eq i32 [[CONV2114]], [[CONV2115]]
42515 // SIMD-ONLY0-NEXT:    br i1 [[CMP2116]], label [[IF_THEN2118:%.*]], label [[IF_ELSE2119:%.*]]
42516 // SIMD-ONLY0:       if.then2118:
42517 // SIMD-ONLY0-NEXT:    [[TMP1312:%.*]] = load i16, ptr [[SD]], align 2
42518 // SIMD-ONLY0-NEXT:    store i16 [[TMP1312]], ptr [[SX]], align 2
42519 // SIMD-ONLY0-NEXT:    br label [[IF_END2120:%.*]]
42520 // SIMD-ONLY0:       if.else2119:
42521 // SIMD-ONLY0-NEXT:    [[TMP1313:%.*]] = load i16, ptr [[SX]], align 2
42522 // SIMD-ONLY0-NEXT:    store i16 [[TMP1313]], ptr [[SV]], align 2
42523 // SIMD-ONLY0-NEXT:    br label [[IF_END2120]]
42524 // SIMD-ONLY0:       if.end2120:
42525 // SIMD-ONLY0-NEXT:    [[TMP1314:%.*]] = load i16, ptr [[SX]], align 2
42526 // SIMD-ONLY0-NEXT:    [[CONV2121:%.*]] = sext i16 [[TMP1314]] to i32
42527 // SIMD-ONLY0-NEXT:    [[TMP1315:%.*]] = load i16, ptr [[SE]], align 2
42528 // SIMD-ONLY0-NEXT:    [[CONV2122:%.*]] = sext i16 [[TMP1315]] to i32
42529 // SIMD-ONLY0-NEXT:    [[CMP2123:%.*]] = icmp eq i32 [[CONV2121]], [[CONV2122]]
42530 // SIMD-ONLY0-NEXT:    [[CONV2124:%.*]] = zext i1 [[CMP2123]] to i32
42531 // SIMD-ONLY0-NEXT:    [[CONV2125:%.*]] = trunc i32 [[CONV2124]] to i16
42532 // SIMD-ONLY0-NEXT:    store i16 [[CONV2125]], ptr [[SR]], align 2
42533 // SIMD-ONLY0-NEXT:    [[TMP1316:%.*]] = load i16, ptr [[SR]], align 2
42534 // SIMD-ONLY0-NEXT:    [[TOBOOL2126:%.*]] = icmp ne i16 [[TMP1316]], 0
42535 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2126]], label [[IF_THEN2127:%.*]], label [[IF_END2128:%.*]]
42536 // SIMD-ONLY0:       if.then2127:
42537 // SIMD-ONLY0-NEXT:    [[TMP1317:%.*]] = load i16, ptr [[SD]], align 2
42538 // SIMD-ONLY0-NEXT:    store i16 [[TMP1317]], ptr [[SX]], align 2
42539 // SIMD-ONLY0-NEXT:    br label [[IF_END2128]]
42540 // SIMD-ONLY0:       if.end2128:
42541 // SIMD-ONLY0-NEXT:    [[TMP1318:%.*]] = load i16, ptr [[SE]], align 2
42542 // SIMD-ONLY0-NEXT:    [[CONV2129:%.*]] = sext i16 [[TMP1318]] to i32
42543 // SIMD-ONLY0-NEXT:    [[TMP1319:%.*]] = load i16, ptr [[SX]], align 2
42544 // SIMD-ONLY0-NEXT:    [[CONV2130:%.*]] = sext i16 [[TMP1319]] to i32
42545 // SIMD-ONLY0-NEXT:    [[CMP2131:%.*]] = icmp eq i32 [[CONV2129]], [[CONV2130]]
42546 // SIMD-ONLY0-NEXT:    [[CONV2132:%.*]] = zext i1 [[CMP2131]] to i32
42547 // SIMD-ONLY0-NEXT:    [[CONV2133:%.*]] = trunc i32 [[CONV2132]] to i16
42548 // SIMD-ONLY0-NEXT:    store i16 [[CONV2133]], ptr [[SR]], align 2
42549 // SIMD-ONLY0-NEXT:    [[TMP1320:%.*]] = load i16, ptr [[SR]], align 2
42550 // SIMD-ONLY0-NEXT:    [[TOBOOL2134:%.*]] = icmp ne i16 [[TMP1320]], 0
42551 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2134]], label [[IF_THEN2135:%.*]], label [[IF_END2136:%.*]]
42552 // SIMD-ONLY0:       if.then2135:
42553 // SIMD-ONLY0-NEXT:    [[TMP1321:%.*]] = load i16, ptr [[SD]], align 2
42554 // SIMD-ONLY0-NEXT:    store i16 [[TMP1321]], ptr [[SX]], align 2
42555 // SIMD-ONLY0-NEXT:    br label [[IF_END2136]]
42556 // SIMD-ONLY0:       if.end2136:
42557 // SIMD-ONLY0-NEXT:    [[TMP1322:%.*]] = load i16, ptr [[SX]], align 2
42558 // SIMD-ONLY0-NEXT:    [[CONV2137:%.*]] = sext i16 [[TMP1322]] to i32
42559 // SIMD-ONLY0-NEXT:    [[TMP1323:%.*]] = load i16, ptr [[SE]], align 2
42560 // SIMD-ONLY0-NEXT:    [[CONV2138:%.*]] = sext i16 [[TMP1323]] to i32
42561 // SIMD-ONLY0-NEXT:    [[CMP2139:%.*]] = icmp eq i32 [[CONV2137]], [[CONV2138]]
42562 // SIMD-ONLY0-NEXT:    [[CONV2140:%.*]] = zext i1 [[CMP2139]] to i32
42563 // SIMD-ONLY0-NEXT:    [[CONV2141:%.*]] = trunc i32 [[CONV2140]] to i16
42564 // SIMD-ONLY0-NEXT:    store i16 [[CONV2141]], ptr [[SR]], align 2
42565 // SIMD-ONLY0-NEXT:    [[TMP1324:%.*]] = load i16, ptr [[SR]], align 2
42566 // SIMD-ONLY0-NEXT:    [[TOBOOL2142:%.*]] = icmp ne i16 [[TMP1324]], 0
42567 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2142]], label [[IF_THEN2143:%.*]], label [[IF_ELSE2144:%.*]]
42568 // SIMD-ONLY0:       if.then2143:
42569 // SIMD-ONLY0-NEXT:    [[TMP1325:%.*]] = load i16, ptr [[SD]], align 2
42570 // SIMD-ONLY0-NEXT:    store i16 [[TMP1325]], ptr [[SX]], align 2
42571 // SIMD-ONLY0-NEXT:    br label [[IF_END2145:%.*]]
42572 // SIMD-ONLY0:       if.else2144:
42573 // SIMD-ONLY0-NEXT:    [[TMP1326:%.*]] = load i16, ptr [[SX]], align 2
42574 // SIMD-ONLY0-NEXT:    store i16 [[TMP1326]], ptr [[SV]], align 2
42575 // SIMD-ONLY0-NEXT:    br label [[IF_END2145]]
42576 // SIMD-ONLY0:       if.end2145:
42577 // SIMD-ONLY0-NEXT:    [[TMP1327:%.*]] = load i16, ptr [[SE]], align 2
42578 // SIMD-ONLY0-NEXT:    [[CONV2146:%.*]] = sext i16 [[TMP1327]] to i32
42579 // SIMD-ONLY0-NEXT:    [[TMP1328:%.*]] = load i16, ptr [[SX]], align 2
42580 // SIMD-ONLY0-NEXT:    [[CONV2147:%.*]] = sext i16 [[TMP1328]] to i32
42581 // SIMD-ONLY0-NEXT:    [[CMP2148:%.*]] = icmp eq i32 [[CONV2146]], [[CONV2147]]
42582 // SIMD-ONLY0-NEXT:    [[CONV2149:%.*]] = zext i1 [[CMP2148]] to i32
42583 // SIMD-ONLY0-NEXT:    [[CONV2150:%.*]] = trunc i32 [[CONV2149]] to i16
42584 // SIMD-ONLY0-NEXT:    store i16 [[CONV2150]], ptr [[SR]], align 2
42585 // SIMD-ONLY0-NEXT:    [[TMP1329:%.*]] = load i16, ptr [[SR]], align 2
42586 // SIMD-ONLY0-NEXT:    [[TOBOOL2151:%.*]] = icmp ne i16 [[TMP1329]], 0
42587 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2151]], label [[IF_THEN2152:%.*]], label [[IF_ELSE2153:%.*]]
42588 // SIMD-ONLY0:       if.then2152:
42589 // SIMD-ONLY0-NEXT:    [[TMP1330:%.*]] = load i16, ptr [[SD]], align 2
42590 // SIMD-ONLY0-NEXT:    store i16 [[TMP1330]], ptr [[SX]], align 2
42591 // SIMD-ONLY0-NEXT:    br label [[IF_END2154:%.*]]
42592 // SIMD-ONLY0:       if.else2153:
42593 // SIMD-ONLY0-NEXT:    [[TMP1331:%.*]] = load i16, ptr [[SX]], align 2
42594 // SIMD-ONLY0-NEXT:    store i16 [[TMP1331]], ptr [[SV]], align 2
42595 // SIMD-ONLY0-NEXT:    br label [[IF_END2154]]
42596 // SIMD-ONLY0:       if.end2154:
42597 // SIMD-ONLY0-NEXT:    [[TMP1332:%.*]] = load i16, ptr [[USX]], align 2
42598 // SIMD-ONLY0-NEXT:    store i16 [[TMP1332]], ptr [[USV]], align 2
42599 // SIMD-ONLY0-NEXT:    [[TMP1333:%.*]] = load i16, ptr [[USE]], align 2
42600 // SIMD-ONLY0-NEXT:    [[CONV2155:%.*]] = zext i16 [[TMP1333]] to i32
42601 // SIMD-ONLY0-NEXT:    [[TMP1334:%.*]] = load i16, ptr [[USX]], align 2
42602 // SIMD-ONLY0-NEXT:    [[CONV2156:%.*]] = zext i16 [[TMP1334]] to i32
42603 // SIMD-ONLY0-NEXT:    [[CMP2157:%.*]] = icmp sgt i32 [[CONV2155]], [[CONV2156]]
42604 // SIMD-ONLY0-NEXT:    br i1 [[CMP2157]], label [[IF_THEN2159:%.*]], label [[IF_END2160:%.*]]
42605 // SIMD-ONLY0:       if.then2159:
42606 // SIMD-ONLY0-NEXT:    [[TMP1335:%.*]] = load i16, ptr [[USE]], align 2
42607 // SIMD-ONLY0-NEXT:    store i16 [[TMP1335]], ptr [[USX]], align 2
42608 // SIMD-ONLY0-NEXT:    br label [[IF_END2160]]
42609 // SIMD-ONLY0:       if.end2160:
42610 // SIMD-ONLY0-NEXT:    [[TMP1336:%.*]] = load i16, ptr [[USX]], align 2
42611 // SIMD-ONLY0-NEXT:    store i16 [[TMP1336]], ptr [[USV]], align 2
42612 // SIMD-ONLY0-NEXT:    [[TMP1337:%.*]] = load i16, ptr [[USX]], align 2
42613 // SIMD-ONLY0-NEXT:    [[CONV2161:%.*]] = zext i16 [[TMP1337]] to i32
42614 // SIMD-ONLY0-NEXT:    [[TMP1338:%.*]] = load i16, ptr [[USE]], align 2
42615 // SIMD-ONLY0-NEXT:    [[CONV2162:%.*]] = zext i16 [[TMP1338]] to i32
42616 // SIMD-ONLY0-NEXT:    [[CMP2163:%.*]] = icmp sgt i32 [[CONV2161]], [[CONV2162]]
42617 // SIMD-ONLY0-NEXT:    br i1 [[CMP2163]], label [[IF_THEN2165:%.*]], label [[IF_END2166:%.*]]
42618 // SIMD-ONLY0:       if.then2165:
42619 // SIMD-ONLY0-NEXT:    [[TMP1339:%.*]] = load i16, ptr [[USE]], align 2
42620 // SIMD-ONLY0-NEXT:    store i16 [[TMP1339]], ptr [[USX]], align 2
42621 // SIMD-ONLY0-NEXT:    br label [[IF_END2166]]
42622 // SIMD-ONLY0:       if.end2166:
42623 // SIMD-ONLY0-NEXT:    [[TMP1340:%.*]] = load i16, ptr [[USX]], align 2
42624 // SIMD-ONLY0-NEXT:    store i16 [[TMP1340]], ptr [[USV]], align 2
42625 // SIMD-ONLY0-NEXT:    [[TMP1341:%.*]] = load i16, ptr [[USE]], align 2
42626 // SIMD-ONLY0-NEXT:    [[CONV2167:%.*]] = zext i16 [[TMP1341]] to i32
42627 // SIMD-ONLY0-NEXT:    [[TMP1342:%.*]] = load i16, ptr [[USX]], align 2
42628 // SIMD-ONLY0-NEXT:    [[CONV2168:%.*]] = zext i16 [[TMP1342]] to i32
42629 // SIMD-ONLY0-NEXT:    [[CMP2169:%.*]] = icmp slt i32 [[CONV2167]], [[CONV2168]]
42630 // SIMD-ONLY0-NEXT:    br i1 [[CMP2169]], label [[IF_THEN2171:%.*]], label [[IF_END2172:%.*]]
42631 // SIMD-ONLY0:       if.then2171:
42632 // SIMD-ONLY0-NEXT:    [[TMP1343:%.*]] = load i16, ptr [[USE]], align 2
42633 // SIMD-ONLY0-NEXT:    store i16 [[TMP1343]], ptr [[USX]], align 2
42634 // SIMD-ONLY0-NEXT:    br label [[IF_END2172]]
42635 // SIMD-ONLY0:       if.end2172:
42636 // SIMD-ONLY0-NEXT:    [[TMP1344:%.*]] = load i16, ptr [[USX]], align 2
42637 // SIMD-ONLY0-NEXT:    store i16 [[TMP1344]], ptr [[USV]], align 2
42638 // SIMD-ONLY0-NEXT:    [[TMP1345:%.*]] = load i16, ptr [[USX]], align 2
42639 // SIMD-ONLY0-NEXT:    [[CONV2173:%.*]] = zext i16 [[TMP1345]] to i32
42640 // SIMD-ONLY0-NEXT:    [[TMP1346:%.*]] = load i16, ptr [[USE]], align 2
42641 // SIMD-ONLY0-NEXT:    [[CONV2174:%.*]] = zext i16 [[TMP1346]] to i32
42642 // SIMD-ONLY0-NEXT:    [[CMP2175:%.*]] = icmp slt i32 [[CONV2173]], [[CONV2174]]
42643 // SIMD-ONLY0-NEXT:    br i1 [[CMP2175]], label [[IF_THEN2177:%.*]], label [[IF_END2178:%.*]]
42644 // SIMD-ONLY0:       if.then2177:
42645 // SIMD-ONLY0-NEXT:    [[TMP1347:%.*]] = load i16, ptr [[USE]], align 2
42646 // SIMD-ONLY0-NEXT:    store i16 [[TMP1347]], ptr [[USX]], align 2
42647 // SIMD-ONLY0-NEXT:    br label [[IF_END2178]]
42648 // SIMD-ONLY0:       if.end2178:
42649 // SIMD-ONLY0-NEXT:    [[TMP1348:%.*]] = load i16, ptr [[USX]], align 2
42650 // SIMD-ONLY0-NEXT:    store i16 [[TMP1348]], ptr [[USV]], align 2
42651 // SIMD-ONLY0-NEXT:    [[TMP1349:%.*]] = load i16, ptr [[USX]], align 2
42652 // SIMD-ONLY0-NEXT:    [[CONV2179:%.*]] = zext i16 [[TMP1349]] to i32
42653 // SIMD-ONLY0-NEXT:    [[TMP1350:%.*]] = load i16, ptr [[USE]], align 2
42654 // SIMD-ONLY0-NEXT:    [[CONV2180:%.*]] = zext i16 [[TMP1350]] to i32
42655 // SIMD-ONLY0-NEXT:    [[CMP2181:%.*]] = icmp eq i32 [[CONV2179]], [[CONV2180]]
42656 // SIMD-ONLY0-NEXT:    br i1 [[CMP2181]], label [[IF_THEN2183:%.*]], label [[IF_END2184:%.*]]
42657 // SIMD-ONLY0:       if.then2183:
42658 // SIMD-ONLY0-NEXT:    [[TMP1351:%.*]] = load i16, ptr [[USD]], align 2
42659 // SIMD-ONLY0-NEXT:    store i16 [[TMP1351]], ptr [[USX]], align 2
42660 // SIMD-ONLY0-NEXT:    br label [[IF_END2184]]
42661 // SIMD-ONLY0:       if.end2184:
42662 // SIMD-ONLY0-NEXT:    [[TMP1352:%.*]] = load i16, ptr [[USX]], align 2
42663 // SIMD-ONLY0-NEXT:    store i16 [[TMP1352]], ptr [[USV]], align 2
42664 // SIMD-ONLY0-NEXT:    [[TMP1353:%.*]] = load i16, ptr [[USE]], align 2
42665 // SIMD-ONLY0-NEXT:    [[CONV2185:%.*]] = zext i16 [[TMP1353]] to i32
42666 // SIMD-ONLY0-NEXT:    [[TMP1354:%.*]] = load i16, ptr [[USX]], align 2
42667 // SIMD-ONLY0-NEXT:    [[CONV2186:%.*]] = zext i16 [[TMP1354]] to i32
42668 // SIMD-ONLY0-NEXT:    [[CMP2187:%.*]] = icmp eq i32 [[CONV2185]], [[CONV2186]]
42669 // SIMD-ONLY0-NEXT:    br i1 [[CMP2187]], label [[IF_THEN2189:%.*]], label [[IF_END2190:%.*]]
42670 // SIMD-ONLY0:       if.then2189:
42671 // SIMD-ONLY0-NEXT:    [[TMP1355:%.*]] = load i16, ptr [[USD]], align 2
42672 // SIMD-ONLY0-NEXT:    store i16 [[TMP1355]], ptr [[USX]], align 2
42673 // SIMD-ONLY0-NEXT:    br label [[IF_END2190]]
42674 // SIMD-ONLY0:       if.end2190:
42675 // SIMD-ONLY0-NEXT:    [[TMP1356:%.*]] = load i16, ptr [[USE]], align 2
42676 // SIMD-ONLY0-NEXT:    [[CONV2191:%.*]] = zext i16 [[TMP1356]] to i32
42677 // SIMD-ONLY0-NEXT:    [[TMP1357:%.*]] = load i16, ptr [[USX]], align 2
42678 // SIMD-ONLY0-NEXT:    [[CONV2192:%.*]] = zext i16 [[TMP1357]] to i32
42679 // SIMD-ONLY0-NEXT:    [[CMP2193:%.*]] = icmp sgt i32 [[CONV2191]], [[CONV2192]]
42680 // SIMD-ONLY0-NEXT:    br i1 [[CMP2193]], label [[IF_THEN2195:%.*]], label [[IF_END2196:%.*]]
42681 // SIMD-ONLY0:       if.then2195:
42682 // SIMD-ONLY0-NEXT:    [[TMP1358:%.*]] = load i16, ptr [[USE]], align 2
42683 // SIMD-ONLY0-NEXT:    store i16 [[TMP1358]], ptr [[USX]], align 2
42684 // SIMD-ONLY0-NEXT:    br label [[IF_END2196]]
42685 // SIMD-ONLY0:       if.end2196:
42686 // SIMD-ONLY0-NEXT:    [[TMP1359:%.*]] = load i16, ptr [[USX]], align 2
42687 // SIMD-ONLY0-NEXT:    store i16 [[TMP1359]], ptr [[USV]], align 2
42688 // SIMD-ONLY0-NEXT:    [[TMP1360:%.*]] = load i16, ptr [[USX]], align 2
42689 // SIMD-ONLY0-NEXT:    [[CONV2197:%.*]] = zext i16 [[TMP1360]] to i32
42690 // SIMD-ONLY0-NEXT:    [[TMP1361:%.*]] = load i16, ptr [[USE]], align 2
42691 // SIMD-ONLY0-NEXT:    [[CONV2198:%.*]] = zext i16 [[TMP1361]] to i32
42692 // SIMD-ONLY0-NEXT:    [[CMP2199:%.*]] = icmp sgt i32 [[CONV2197]], [[CONV2198]]
42693 // SIMD-ONLY0-NEXT:    br i1 [[CMP2199]], label [[IF_THEN2201:%.*]], label [[IF_END2202:%.*]]
42694 // SIMD-ONLY0:       if.then2201:
42695 // SIMD-ONLY0-NEXT:    [[TMP1362:%.*]] = load i16, ptr [[USE]], align 2
42696 // SIMD-ONLY0-NEXT:    store i16 [[TMP1362]], ptr [[USX]], align 2
42697 // SIMD-ONLY0-NEXT:    br label [[IF_END2202]]
42698 // SIMD-ONLY0:       if.end2202:
42699 // SIMD-ONLY0-NEXT:    [[TMP1363:%.*]] = load i16, ptr [[USX]], align 2
42700 // SIMD-ONLY0-NEXT:    store i16 [[TMP1363]], ptr [[USV]], align 2
42701 // SIMD-ONLY0-NEXT:    [[TMP1364:%.*]] = load i16, ptr [[USE]], align 2
42702 // SIMD-ONLY0-NEXT:    [[CONV2203:%.*]] = zext i16 [[TMP1364]] to i32
42703 // SIMD-ONLY0-NEXT:    [[TMP1365:%.*]] = load i16, ptr [[USX]], align 2
42704 // SIMD-ONLY0-NEXT:    [[CONV2204:%.*]] = zext i16 [[TMP1365]] to i32
42705 // SIMD-ONLY0-NEXT:    [[CMP2205:%.*]] = icmp slt i32 [[CONV2203]], [[CONV2204]]
42706 // SIMD-ONLY0-NEXT:    br i1 [[CMP2205]], label [[IF_THEN2207:%.*]], label [[IF_END2208:%.*]]
42707 // SIMD-ONLY0:       if.then2207:
42708 // SIMD-ONLY0-NEXT:    [[TMP1366:%.*]] = load i16, ptr [[USE]], align 2
42709 // SIMD-ONLY0-NEXT:    store i16 [[TMP1366]], ptr [[USX]], align 2
42710 // SIMD-ONLY0-NEXT:    br label [[IF_END2208]]
42711 // SIMD-ONLY0:       if.end2208:
42712 // SIMD-ONLY0-NEXT:    [[TMP1367:%.*]] = load i16, ptr [[USX]], align 2
42713 // SIMD-ONLY0-NEXT:    store i16 [[TMP1367]], ptr [[USV]], align 2
42714 // SIMD-ONLY0-NEXT:    [[TMP1368:%.*]] = load i16, ptr [[USX]], align 2
42715 // SIMD-ONLY0-NEXT:    [[CONV2209:%.*]] = zext i16 [[TMP1368]] to i32
42716 // SIMD-ONLY0-NEXT:    [[TMP1369:%.*]] = load i16, ptr [[USE]], align 2
42717 // SIMD-ONLY0-NEXT:    [[CONV2210:%.*]] = zext i16 [[TMP1369]] to i32
42718 // SIMD-ONLY0-NEXT:    [[CMP2211:%.*]] = icmp slt i32 [[CONV2209]], [[CONV2210]]
42719 // SIMD-ONLY0-NEXT:    br i1 [[CMP2211]], label [[IF_THEN2213:%.*]], label [[IF_END2214:%.*]]
42720 // SIMD-ONLY0:       if.then2213:
42721 // SIMD-ONLY0-NEXT:    [[TMP1370:%.*]] = load i16, ptr [[USE]], align 2
42722 // SIMD-ONLY0-NEXT:    store i16 [[TMP1370]], ptr [[USX]], align 2
42723 // SIMD-ONLY0-NEXT:    br label [[IF_END2214]]
42724 // SIMD-ONLY0:       if.end2214:
42725 // SIMD-ONLY0-NEXT:    [[TMP1371:%.*]] = load i16, ptr [[USX]], align 2
42726 // SIMD-ONLY0-NEXT:    store i16 [[TMP1371]], ptr [[USV]], align 2
42727 // SIMD-ONLY0-NEXT:    [[TMP1372:%.*]] = load i16, ptr [[USX]], align 2
42728 // SIMD-ONLY0-NEXT:    [[CONV2215:%.*]] = zext i16 [[TMP1372]] to i32
42729 // SIMD-ONLY0-NEXT:    [[TMP1373:%.*]] = load i16, ptr [[USE]], align 2
42730 // SIMD-ONLY0-NEXT:    [[CONV2216:%.*]] = zext i16 [[TMP1373]] to i32
42731 // SIMD-ONLY0-NEXT:    [[CMP2217:%.*]] = icmp eq i32 [[CONV2215]], [[CONV2216]]
42732 // SIMD-ONLY0-NEXT:    br i1 [[CMP2217]], label [[IF_THEN2219:%.*]], label [[IF_END2220:%.*]]
42733 // SIMD-ONLY0:       if.then2219:
42734 // SIMD-ONLY0-NEXT:    [[TMP1374:%.*]] = load i16, ptr [[USD]], align 2
42735 // SIMD-ONLY0-NEXT:    store i16 [[TMP1374]], ptr [[USX]], align 2
42736 // SIMD-ONLY0-NEXT:    br label [[IF_END2220]]
42737 // SIMD-ONLY0:       if.end2220:
42738 // SIMD-ONLY0-NEXT:    [[TMP1375:%.*]] = load i16, ptr [[USX]], align 2
42739 // SIMD-ONLY0-NEXT:    store i16 [[TMP1375]], ptr [[USV]], align 2
42740 // SIMD-ONLY0-NEXT:    [[TMP1376:%.*]] = load i16, ptr [[USE]], align 2
42741 // SIMD-ONLY0-NEXT:    [[CONV2221:%.*]] = zext i16 [[TMP1376]] to i32
42742 // SIMD-ONLY0-NEXT:    [[TMP1377:%.*]] = load i16, ptr [[USX]], align 2
42743 // SIMD-ONLY0-NEXT:    [[CONV2222:%.*]] = zext i16 [[TMP1377]] to i32
42744 // SIMD-ONLY0-NEXT:    [[CMP2223:%.*]] = icmp eq i32 [[CONV2221]], [[CONV2222]]
42745 // SIMD-ONLY0-NEXT:    br i1 [[CMP2223]], label [[IF_THEN2225:%.*]], label [[IF_END2226:%.*]]
42746 // SIMD-ONLY0:       if.then2225:
42747 // SIMD-ONLY0-NEXT:    [[TMP1378:%.*]] = load i16, ptr [[USD]], align 2
42748 // SIMD-ONLY0-NEXT:    store i16 [[TMP1378]], ptr [[USX]], align 2
42749 // SIMD-ONLY0-NEXT:    br label [[IF_END2226]]
42750 // SIMD-ONLY0:       if.end2226:
42751 // SIMD-ONLY0-NEXT:    [[TMP1379:%.*]] = load i16, ptr [[USX]], align 2
42752 // SIMD-ONLY0-NEXT:    store i16 [[TMP1379]], ptr [[USV]], align 2
42753 // SIMD-ONLY0-NEXT:    [[TMP1380:%.*]] = load i16, ptr [[USX]], align 2
42754 // SIMD-ONLY0-NEXT:    [[CONV2227:%.*]] = zext i16 [[TMP1380]] to i32
42755 // SIMD-ONLY0-NEXT:    [[TMP1381:%.*]] = load i16, ptr [[USE]], align 2
42756 // SIMD-ONLY0-NEXT:    [[CONV2228:%.*]] = zext i16 [[TMP1381]] to i32
42757 // SIMD-ONLY0-NEXT:    [[CMP2229:%.*]] = icmp eq i32 [[CONV2227]], [[CONV2228]]
42758 // SIMD-ONLY0-NEXT:    br i1 [[CMP2229]], label [[IF_THEN2231:%.*]], label [[IF_ELSE2232:%.*]]
42759 // SIMD-ONLY0:       if.then2231:
42760 // SIMD-ONLY0-NEXT:    [[TMP1382:%.*]] = load i16, ptr [[USD]], align 2
42761 // SIMD-ONLY0-NEXT:    store i16 [[TMP1382]], ptr [[USX]], align 2
42762 // SIMD-ONLY0-NEXT:    br label [[IF_END2233:%.*]]
42763 // SIMD-ONLY0:       if.else2232:
42764 // SIMD-ONLY0-NEXT:    [[TMP1383:%.*]] = load i16, ptr [[USX]], align 2
42765 // SIMD-ONLY0-NEXT:    store i16 [[TMP1383]], ptr [[USV]], align 2
42766 // SIMD-ONLY0-NEXT:    br label [[IF_END2233]]
42767 // SIMD-ONLY0:       if.end2233:
42768 // SIMD-ONLY0-NEXT:    [[TMP1384:%.*]] = load i16, ptr [[USE]], align 2
42769 // SIMD-ONLY0-NEXT:    [[CONV2234:%.*]] = zext i16 [[TMP1384]] to i32
42770 // SIMD-ONLY0-NEXT:    [[TMP1385:%.*]] = load i16, ptr [[USX]], align 2
42771 // SIMD-ONLY0-NEXT:    [[CONV2235:%.*]] = zext i16 [[TMP1385]] to i32
42772 // SIMD-ONLY0-NEXT:    [[CMP2236:%.*]] = icmp eq i32 [[CONV2234]], [[CONV2235]]
42773 // SIMD-ONLY0-NEXT:    br i1 [[CMP2236]], label [[IF_THEN2238:%.*]], label [[IF_ELSE2239:%.*]]
42774 // SIMD-ONLY0:       if.then2238:
42775 // SIMD-ONLY0-NEXT:    [[TMP1386:%.*]] = load i16, ptr [[USD]], align 2
42776 // SIMD-ONLY0-NEXT:    store i16 [[TMP1386]], ptr [[USX]], align 2
42777 // SIMD-ONLY0-NEXT:    br label [[IF_END2240:%.*]]
42778 // SIMD-ONLY0:       if.else2239:
42779 // SIMD-ONLY0-NEXT:    [[TMP1387:%.*]] = load i16, ptr [[USX]], align 2
42780 // SIMD-ONLY0-NEXT:    store i16 [[TMP1387]], ptr [[USV]], align 2
42781 // SIMD-ONLY0-NEXT:    br label [[IF_END2240]]
42782 // SIMD-ONLY0:       if.end2240:
42783 // SIMD-ONLY0-NEXT:    [[TMP1388:%.*]] = load i16, ptr [[USX]], align 2
42784 // SIMD-ONLY0-NEXT:    [[CONV2241:%.*]] = zext i16 [[TMP1388]] to i32
42785 // SIMD-ONLY0-NEXT:    [[TMP1389:%.*]] = load i16, ptr [[USE]], align 2
42786 // SIMD-ONLY0-NEXT:    [[CONV2242:%.*]] = zext i16 [[TMP1389]] to i32
42787 // SIMD-ONLY0-NEXT:    [[CMP2243:%.*]] = icmp eq i32 [[CONV2241]], [[CONV2242]]
42788 // SIMD-ONLY0-NEXT:    [[CONV2244:%.*]] = zext i1 [[CMP2243]] to i32
42789 // SIMD-ONLY0-NEXT:    [[CONV2245:%.*]] = trunc i32 [[CONV2244]] to i16
42790 // SIMD-ONLY0-NEXT:    store i16 [[CONV2245]], ptr [[USR]], align 2
42791 // SIMD-ONLY0-NEXT:    [[TMP1390:%.*]] = load i16, ptr [[USR]], align 2
42792 // SIMD-ONLY0-NEXT:    [[TOBOOL2246:%.*]] = icmp ne i16 [[TMP1390]], 0
42793 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2246]], label [[IF_THEN2247:%.*]], label [[IF_END2248:%.*]]
42794 // SIMD-ONLY0:       if.then2247:
42795 // SIMD-ONLY0-NEXT:    [[TMP1391:%.*]] = load i16, ptr [[USD]], align 2
42796 // SIMD-ONLY0-NEXT:    store i16 [[TMP1391]], ptr [[USX]], align 2
42797 // SIMD-ONLY0-NEXT:    br label [[IF_END2248]]
42798 // SIMD-ONLY0:       if.end2248:
42799 // SIMD-ONLY0-NEXT:    [[TMP1392:%.*]] = load i16, ptr [[USE]], align 2
42800 // SIMD-ONLY0-NEXT:    [[CONV2249:%.*]] = zext i16 [[TMP1392]] to i32
42801 // SIMD-ONLY0-NEXT:    [[TMP1393:%.*]] = load i16, ptr [[USX]], align 2
42802 // SIMD-ONLY0-NEXT:    [[CONV2250:%.*]] = zext i16 [[TMP1393]] to i32
42803 // SIMD-ONLY0-NEXT:    [[CMP2251:%.*]] = icmp eq i32 [[CONV2249]], [[CONV2250]]
42804 // SIMD-ONLY0-NEXT:    [[CONV2252:%.*]] = zext i1 [[CMP2251]] to i32
42805 // SIMD-ONLY0-NEXT:    [[CONV2253:%.*]] = trunc i32 [[CONV2252]] to i16
42806 // SIMD-ONLY0-NEXT:    store i16 [[CONV2253]], ptr [[USR]], align 2
42807 // SIMD-ONLY0-NEXT:    [[TMP1394:%.*]] = load i16, ptr [[USR]], align 2
42808 // SIMD-ONLY0-NEXT:    [[TOBOOL2254:%.*]] = icmp ne i16 [[TMP1394]], 0
42809 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2254]], label [[IF_THEN2255:%.*]], label [[IF_END2256:%.*]]
42810 // SIMD-ONLY0:       if.then2255:
42811 // SIMD-ONLY0-NEXT:    [[TMP1395:%.*]] = load i16, ptr [[USD]], align 2
42812 // SIMD-ONLY0-NEXT:    store i16 [[TMP1395]], ptr [[USX]], align 2
42813 // SIMD-ONLY0-NEXT:    br label [[IF_END2256]]
42814 // SIMD-ONLY0:       if.end2256:
42815 // SIMD-ONLY0-NEXT:    [[TMP1396:%.*]] = load i16, ptr [[USX]], align 2
42816 // SIMD-ONLY0-NEXT:    [[CONV2257:%.*]] = zext i16 [[TMP1396]] to i32
42817 // SIMD-ONLY0-NEXT:    [[TMP1397:%.*]] = load i16, ptr [[USE]], align 2
42818 // SIMD-ONLY0-NEXT:    [[CONV2258:%.*]] = zext i16 [[TMP1397]] to i32
42819 // SIMD-ONLY0-NEXT:    [[CMP2259:%.*]] = icmp eq i32 [[CONV2257]], [[CONV2258]]
42820 // SIMD-ONLY0-NEXT:    [[CONV2260:%.*]] = zext i1 [[CMP2259]] to i32
42821 // SIMD-ONLY0-NEXT:    [[CONV2261:%.*]] = trunc i32 [[CONV2260]] to i16
42822 // SIMD-ONLY0-NEXT:    store i16 [[CONV2261]], ptr [[USR]], align 2
42823 // SIMD-ONLY0-NEXT:    [[TMP1398:%.*]] = load i16, ptr [[USR]], align 2
42824 // SIMD-ONLY0-NEXT:    [[TOBOOL2262:%.*]] = icmp ne i16 [[TMP1398]], 0
42825 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2262]], label [[IF_THEN2263:%.*]], label [[IF_ELSE2264:%.*]]
42826 // SIMD-ONLY0:       if.then2263:
42827 // SIMD-ONLY0-NEXT:    [[TMP1399:%.*]] = load i16, ptr [[USD]], align 2
42828 // SIMD-ONLY0-NEXT:    store i16 [[TMP1399]], ptr [[USX]], align 2
42829 // SIMD-ONLY0-NEXT:    br label [[IF_END2265:%.*]]
42830 // SIMD-ONLY0:       if.else2264:
42831 // SIMD-ONLY0-NEXT:    [[TMP1400:%.*]] = load i16, ptr [[USX]], align 2
42832 // SIMD-ONLY0-NEXT:    store i16 [[TMP1400]], ptr [[USV]], align 2
42833 // SIMD-ONLY0-NEXT:    br label [[IF_END2265]]
42834 // SIMD-ONLY0:       if.end2265:
42835 // SIMD-ONLY0-NEXT:    [[TMP1401:%.*]] = load i16, ptr [[USE]], align 2
42836 // SIMD-ONLY0-NEXT:    [[CONV2266:%.*]] = zext i16 [[TMP1401]] to i32
42837 // SIMD-ONLY0-NEXT:    [[TMP1402:%.*]] = load i16, ptr [[USX]], align 2
42838 // SIMD-ONLY0-NEXT:    [[CONV2267:%.*]] = zext i16 [[TMP1402]] to i32
42839 // SIMD-ONLY0-NEXT:    [[CMP2268:%.*]] = icmp eq i32 [[CONV2266]], [[CONV2267]]
42840 // SIMD-ONLY0-NEXT:    [[CONV2269:%.*]] = zext i1 [[CMP2268]] to i32
42841 // SIMD-ONLY0-NEXT:    [[CONV2270:%.*]] = trunc i32 [[CONV2269]] to i16
42842 // SIMD-ONLY0-NEXT:    store i16 [[CONV2270]], ptr [[USR]], align 2
42843 // SIMD-ONLY0-NEXT:    [[TMP1403:%.*]] = load i16, ptr [[USR]], align 2
42844 // SIMD-ONLY0-NEXT:    [[TOBOOL2271:%.*]] = icmp ne i16 [[TMP1403]], 0
42845 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2271]], label [[IF_THEN2272:%.*]], label [[IF_ELSE2273:%.*]]
42846 // SIMD-ONLY0:       if.then2272:
42847 // SIMD-ONLY0-NEXT:    [[TMP1404:%.*]] = load i16, ptr [[USD]], align 2
42848 // SIMD-ONLY0-NEXT:    store i16 [[TMP1404]], ptr [[USX]], align 2
42849 // SIMD-ONLY0-NEXT:    br label [[IF_END2274:%.*]]
42850 // SIMD-ONLY0:       if.else2273:
42851 // SIMD-ONLY0-NEXT:    [[TMP1405:%.*]] = load i16, ptr [[USX]], align 2
42852 // SIMD-ONLY0-NEXT:    store i16 [[TMP1405]], ptr [[USV]], align 2
42853 // SIMD-ONLY0-NEXT:    br label [[IF_END2274]]
42854 // SIMD-ONLY0:       if.end2274:
42855 // SIMD-ONLY0-NEXT:    [[TMP1406:%.*]] = load i16, ptr [[USX]], align 2
42856 // SIMD-ONLY0-NEXT:    store i16 [[TMP1406]], ptr [[USV]], align 2
42857 // SIMD-ONLY0-NEXT:    [[TMP1407:%.*]] = load i16, ptr [[USE]], align 2
42858 // SIMD-ONLY0-NEXT:    [[CONV2275:%.*]] = zext i16 [[TMP1407]] to i32
42859 // SIMD-ONLY0-NEXT:    [[TMP1408:%.*]] = load i16, ptr [[USX]], align 2
42860 // SIMD-ONLY0-NEXT:    [[CONV2276:%.*]] = zext i16 [[TMP1408]] to i32
42861 // SIMD-ONLY0-NEXT:    [[CMP2277:%.*]] = icmp sgt i32 [[CONV2275]], [[CONV2276]]
42862 // SIMD-ONLY0-NEXT:    br i1 [[CMP2277]], label [[IF_THEN2279:%.*]], label [[IF_END2280:%.*]]
42863 // SIMD-ONLY0:       if.then2279:
42864 // SIMD-ONLY0-NEXT:    [[TMP1409:%.*]] = load i16, ptr [[USE]], align 2
42865 // SIMD-ONLY0-NEXT:    store i16 [[TMP1409]], ptr [[USX]], align 2
42866 // SIMD-ONLY0-NEXT:    br label [[IF_END2280]]
42867 // SIMD-ONLY0:       if.end2280:
42868 // SIMD-ONLY0-NEXT:    [[TMP1410:%.*]] = load i16, ptr [[USX]], align 2
42869 // SIMD-ONLY0-NEXT:    store i16 [[TMP1410]], ptr [[USV]], align 2
42870 // SIMD-ONLY0-NEXT:    [[TMP1411:%.*]] = load i16, ptr [[USX]], align 2
42871 // SIMD-ONLY0-NEXT:    [[CONV2281:%.*]] = zext i16 [[TMP1411]] to i32
42872 // SIMD-ONLY0-NEXT:    [[TMP1412:%.*]] = load i16, ptr [[USE]], align 2
42873 // SIMD-ONLY0-NEXT:    [[CONV2282:%.*]] = zext i16 [[TMP1412]] to i32
42874 // SIMD-ONLY0-NEXT:    [[CMP2283:%.*]] = icmp sgt i32 [[CONV2281]], [[CONV2282]]
42875 // SIMD-ONLY0-NEXT:    br i1 [[CMP2283]], label [[IF_THEN2285:%.*]], label [[IF_END2286:%.*]]
42876 // SIMD-ONLY0:       if.then2285:
42877 // SIMD-ONLY0-NEXT:    [[TMP1413:%.*]] = load i16, ptr [[USE]], align 2
42878 // SIMD-ONLY0-NEXT:    store i16 [[TMP1413]], ptr [[USX]], align 2
42879 // SIMD-ONLY0-NEXT:    br label [[IF_END2286]]
42880 // SIMD-ONLY0:       if.end2286:
42881 // SIMD-ONLY0-NEXT:    [[TMP1414:%.*]] = load i16, ptr [[USX]], align 2
42882 // SIMD-ONLY0-NEXT:    store i16 [[TMP1414]], ptr [[USV]], align 2
42883 // SIMD-ONLY0-NEXT:    [[TMP1415:%.*]] = load i16, ptr [[USE]], align 2
42884 // SIMD-ONLY0-NEXT:    [[CONV2287:%.*]] = zext i16 [[TMP1415]] to i32
42885 // SIMD-ONLY0-NEXT:    [[TMP1416:%.*]] = load i16, ptr [[USX]], align 2
42886 // SIMD-ONLY0-NEXT:    [[CONV2288:%.*]] = zext i16 [[TMP1416]] to i32
42887 // SIMD-ONLY0-NEXT:    [[CMP2289:%.*]] = icmp slt i32 [[CONV2287]], [[CONV2288]]
42888 // SIMD-ONLY0-NEXT:    br i1 [[CMP2289]], label [[IF_THEN2291:%.*]], label [[IF_END2292:%.*]]
42889 // SIMD-ONLY0:       if.then2291:
42890 // SIMD-ONLY0-NEXT:    [[TMP1417:%.*]] = load i16, ptr [[USE]], align 2
42891 // SIMD-ONLY0-NEXT:    store i16 [[TMP1417]], ptr [[USX]], align 2
42892 // SIMD-ONLY0-NEXT:    br label [[IF_END2292]]
42893 // SIMD-ONLY0:       if.end2292:
42894 // SIMD-ONLY0-NEXT:    [[TMP1418:%.*]] = load i16, ptr [[USX]], align 2
42895 // SIMD-ONLY0-NEXT:    store i16 [[TMP1418]], ptr [[USV]], align 2
42896 // SIMD-ONLY0-NEXT:    [[TMP1419:%.*]] = load i16, ptr [[USX]], align 2
42897 // SIMD-ONLY0-NEXT:    [[CONV2293:%.*]] = zext i16 [[TMP1419]] to i32
42898 // SIMD-ONLY0-NEXT:    [[TMP1420:%.*]] = load i16, ptr [[USE]], align 2
42899 // SIMD-ONLY0-NEXT:    [[CONV2294:%.*]] = zext i16 [[TMP1420]] to i32
42900 // SIMD-ONLY0-NEXT:    [[CMP2295:%.*]] = icmp slt i32 [[CONV2293]], [[CONV2294]]
42901 // SIMD-ONLY0-NEXT:    br i1 [[CMP2295]], label [[IF_THEN2297:%.*]], label [[IF_END2298:%.*]]
42902 // SIMD-ONLY0:       if.then2297:
42903 // SIMD-ONLY0-NEXT:    [[TMP1421:%.*]] = load i16, ptr [[USE]], align 2
42904 // SIMD-ONLY0-NEXT:    store i16 [[TMP1421]], ptr [[USX]], align 2
42905 // SIMD-ONLY0-NEXT:    br label [[IF_END2298]]
42906 // SIMD-ONLY0:       if.end2298:
42907 // SIMD-ONLY0-NEXT:    [[TMP1422:%.*]] = load i16, ptr [[USX]], align 2
42908 // SIMD-ONLY0-NEXT:    store i16 [[TMP1422]], ptr [[USV]], align 2
42909 // SIMD-ONLY0-NEXT:    [[TMP1423:%.*]] = load i16, ptr [[USX]], align 2
42910 // SIMD-ONLY0-NEXT:    [[CONV2299:%.*]] = zext i16 [[TMP1423]] to i32
42911 // SIMD-ONLY0-NEXT:    [[TMP1424:%.*]] = load i16, ptr [[USE]], align 2
42912 // SIMD-ONLY0-NEXT:    [[CONV2300:%.*]] = zext i16 [[TMP1424]] to i32
42913 // SIMD-ONLY0-NEXT:    [[CMP2301:%.*]] = icmp eq i32 [[CONV2299]], [[CONV2300]]
42914 // SIMD-ONLY0-NEXT:    br i1 [[CMP2301]], label [[IF_THEN2303:%.*]], label [[IF_END2304:%.*]]
42915 // SIMD-ONLY0:       if.then2303:
42916 // SIMD-ONLY0-NEXT:    [[TMP1425:%.*]] = load i16, ptr [[USD]], align 2
42917 // SIMD-ONLY0-NEXT:    store i16 [[TMP1425]], ptr [[USX]], align 2
42918 // SIMD-ONLY0-NEXT:    br label [[IF_END2304]]
42919 // SIMD-ONLY0:       if.end2304:
42920 // SIMD-ONLY0-NEXT:    [[TMP1426:%.*]] = load i16, ptr [[USX]], align 2
42921 // SIMD-ONLY0-NEXT:    store i16 [[TMP1426]], ptr [[USV]], align 2
42922 // SIMD-ONLY0-NEXT:    [[TMP1427:%.*]] = load i16, ptr [[USE]], align 2
42923 // SIMD-ONLY0-NEXT:    [[CONV2305:%.*]] = zext i16 [[TMP1427]] to i32
42924 // SIMD-ONLY0-NEXT:    [[TMP1428:%.*]] = load i16, ptr [[USX]], align 2
42925 // SIMD-ONLY0-NEXT:    [[CONV2306:%.*]] = zext i16 [[TMP1428]] to i32
42926 // SIMD-ONLY0-NEXT:    [[CMP2307:%.*]] = icmp eq i32 [[CONV2305]], [[CONV2306]]
42927 // SIMD-ONLY0-NEXT:    br i1 [[CMP2307]], label [[IF_THEN2309:%.*]], label [[IF_END2310:%.*]]
42928 // SIMD-ONLY0:       if.then2309:
42929 // SIMD-ONLY0-NEXT:    [[TMP1429:%.*]] = load i16, ptr [[USD]], align 2
42930 // SIMD-ONLY0-NEXT:    store i16 [[TMP1429]], ptr [[USX]], align 2
42931 // SIMD-ONLY0-NEXT:    br label [[IF_END2310]]
42932 // SIMD-ONLY0:       if.end2310:
42933 // SIMD-ONLY0-NEXT:    [[TMP1430:%.*]] = load i16, ptr [[USE]], align 2
42934 // SIMD-ONLY0-NEXT:    [[CONV2311:%.*]] = zext i16 [[TMP1430]] to i32
42935 // SIMD-ONLY0-NEXT:    [[TMP1431:%.*]] = load i16, ptr [[USX]], align 2
42936 // SIMD-ONLY0-NEXT:    [[CONV2312:%.*]] = zext i16 [[TMP1431]] to i32
42937 // SIMD-ONLY0-NEXT:    [[CMP2313:%.*]] = icmp sgt i32 [[CONV2311]], [[CONV2312]]
42938 // SIMD-ONLY0-NEXT:    br i1 [[CMP2313]], label [[IF_THEN2315:%.*]], label [[IF_END2316:%.*]]
42939 // SIMD-ONLY0:       if.then2315:
42940 // SIMD-ONLY0-NEXT:    [[TMP1432:%.*]] = load i16, ptr [[USE]], align 2
42941 // SIMD-ONLY0-NEXT:    store i16 [[TMP1432]], ptr [[USX]], align 2
42942 // SIMD-ONLY0-NEXT:    br label [[IF_END2316]]
42943 // SIMD-ONLY0:       if.end2316:
42944 // SIMD-ONLY0-NEXT:    [[TMP1433:%.*]] = load i16, ptr [[USX]], align 2
42945 // SIMD-ONLY0-NEXT:    store i16 [[TMP1433]], ptr [[USV]], align 2
42946 // SIMD-ONLY0-NEXT:    [[TMP1434:%.*]] = load i16, ptr [[USX]], align 2
42947 // SIMD-ONLY0-NEXT:    [[CONV2317:%.*]] = zext i16 [[TMP1434]] to i32
42948 // SIMD-ONLY0-NEXT:    [[TMP1435:%.*]] = load i16, ptr [[USE]], align 2
42949 // SIMD-ONLY0-NEXT:    [[CONV2318:%.*]] = zext i16 [[TMP1435]] to i32
42950 // SIMD-ONLY0-NEXT:    [[CMP2319:%.*]] = icmp sgt i32 [[CONV2317]], [[CONV2318]]
42951 // SIMD-ONLY0-NEXT:    br i1 [[CMP2319]], label [[IF_THEN2321:%.*]], label [[IF_END2322:%.*]]
42952 // SIMD-ONLY0:       if.then2321:
42953 // SIMD-ONLY0-NEXT:    [[TMP1436:%.*]] = load i16, ptr [[USE]], align 2
42954 // SIMD-ONLY0-NEXT:    store i16 [[TMP1436]], ptr [[USX]], align 2
42955 // SIMD-ONLY0-NEXT:    br label [[IF_END2322]]
42956 // SIMD-ONLY0:       if.end2322:
42957 // SIMD-ONLY0-NEXT:    [[TMP1437:%.*]] = load i16, ptr [[USX]], align 2
42958 // SIMD-ONLY0-NEXT:    store i16 [[TMP1437]], ptr [[USV]], align 2
42959 // SIMD-ONLY0-NEXT:    [[TMP1438:%.*]] = load i16, ptr [[USE]], align 2
42960 // SIMD-ONLY0-NEXT:    [[CONV2323:%.*]] = zext i16 [[TMP1438]] to i32
42961 // SIMD-ONLY0-NEXT:    [[TMP1439:%.*]] = load i16, ptr [[USX]], align 2
42962 // SIMD-ONLY0-NEXT:    [[CONV2324:%.*]] = zext i16 [[TMP1439]] to i32
42963 // SIMD-ONLY0-NEXT:    [[CMP2325:%.*]] = icmp slt i32 [[CONV2323]], [[CONV2324]]
42964 // SIMD-ONLY0-NEXT:    br i1 [[CMP2325]], label [[IF_THEN2327:%.*]], label [[IF_END2328:%.*]]
42965 // SIMD-ONLY0:       if.then2327:
42966 // SIMD-ONLY0-NEXT:    [[TMP1440:%.*]] = load i16, ptr [[USE]], align 2
42967 // SIMD-ONLY0-NEXT:    store i16 [[TMP1440]], ptr [[USX]], align 2
42968 // SIMD-ONLY0-NEXT:    br label [[IF_END2328]]
42969 // SIMD-ONLY0:       if.end2328:
42970 // SIMD-ONLY0-NEXT:    [[TMP1441:%.*]] = load i16, ptr [[USX]], align 2
42971 // SIMD-ONLY0-NEXT:    store i16 [[TMP1441]], ptr [[USV]], align 2
42972 // SIMD-ONLY0-NEXT:    [[TMP1442:%.*]] = load i16, ptr [[USX]], align 2
42973 // SIMD-ONLY0-NEXT:    [[CONV2329:%.*]] = zext i16 [[TMP1442]] to i32
42974 // SIMD-ONLY0-NEXT:    [[TMP1443:%.*]] = load i16, ptr [[USE]], align 2
42975 // SIMD-ONLY0-NEXT:    [[CONV2330:%.*]] = zext i16 [[TMP1443]] to i32
42976 // SIMD-ONLY0-NEXT:    [[CMP2331:%.*]] = icmp slt i32 [[CONV2329]], [[CONV2330]]
42977 // SIMD-ONLY0-NEXT:    br i1 [[CMP2331]], label [[IF_THEN2333:%.*]], label [[IF_END2334:%.*]]
42978 // SIMD-ONLY0:       if.then2333:
42979 // SIMD-ONLY0-NEXT:    [[TMP1444:%.*]] = load i16, ptr [[USE]], align 2
42980 // SIMD-ONLY0-NEXT:    store i16 [[TMP1444]], ptr [[USX]], align 2
42981 // SIMD-ONLY0-NEXT:    br label [[IF_END2334]]
42982 // SIMD-ONLY0:       if.end2334:
42983 // SIMD-ONLY0-NEXT:    [[TMP1445:%.*]] = load i16, ptr [[USX]], align 2
42984 // SIMD-ONLY0-NEXT:    store i16 [[TMP1445]], ptr [[USV]], align 2
42985 // SIMD-ONLY0-NEXT:    [[TMP1446:%.*]] = load i16, ptr [[USX]], align 2
42986 // SIMD-ONLY0-NEXT:    [[CONV2335:%.*]] = zext i16 [[TMP1446]] to i32
42987 // SIMD-ONLY0-NEXT:    [[TMP1447:%.*]] = load i16, ptr [[USE]], align 2
42988 // SIMD-ONLY0-NEXT:    [[CONV2336:%.*]] = zext i16 [[TMP1447]] to i32
42989 // SIMD-ONLY0-NEXT:    [[CMP2337:%.*]] = icmp eq i32 [[CONV2335]], [[CONV2336]]
42990 // SIMD-ONLY0-NEXT:    br i1 [[CMP2337]], label [[IF_THEN2339:%.*]], label [[IF_END2340:%.*]]
42991 // SIMD-ONLY0:       if.then2339:
42992 // SIMD-ONLY0-NEXT:    [[TMP1448:%.*]] = load i16, ptr [[USD]], align 2
42993 // SIMD-ONLY0-NEXT:    store i16 [[TMP1448]], ptr [[USX]], align 2
42994 // SIMD-ONLY0-NEXT:    br label [[IF_END2340]]
42995 // SIMD-ONLY0:       if.end2340:
42996 // SIMD-ONLY0-NEXT:    [[TMP1449:%.*]] = load i16, ptr [[USX]], align 2
42997 // SIMD-ONLY0-NEXT:    store i16 [[TMP1449]], ptr [[USV]], align 2
42998 // SIMD-ONLY0-NEXT:    [[TMP1450:%.*]] = load i16, ptr [[USE]], align 2
42999 // SIMD-ONLY0-NEXT:    [[CONV2341:%.*]] = zext i16 [[TMP1450]] to i32
43000 // SIMD-ONLY0-NEXT:    [[TMP1451:%.*]] = load i16, ptr [[USX]], align 2
43001 // SIMD-ONLY0-NEXT:    [[CONV2342:%.*]] = zext i16 [[TMP1451]] to i32
43002 // SIMD-ONLY0-NEXT:    [[CMP2343:%.*]] = icmp eq i32 [[CONV2341]], [[CONV2342]]
43003 // SIMD-ONLY0-NEXT:    br i1 [[CMP2343]], label [[IF_THEN2345:%.*]], label [[IF_END2346:%.*]]
43004 // SIMD-ONLY0:       if.then2345:
43005 // SIMD-ONLY0-NEXT:    [[TMP1452:%.*]] = load i16, ptr [[USD]], align 2
43006 // SIMD-ONLY0-NEXT:    store i16 [[TMP1452]], ptr [[USX]], align 2
43007 // SIMD-ONLY0-NEXT:    br label [[IF_END2346]]
43008 // SIMD-ONLY0:       if.end2346:
43009 // SIMD-ONLY0-NEXT:    [[TMP1453:%.*]] = load i16, ptr [[USX]], align 2
43010 // SIMD-ONLY0-NEXT:    store i16 [[TMP1453]], ptr [[USV]], align 2
43011 // SIMD-ONLY0-NEXT:    [[TMP1454:%.*]] = load i16, ptr [[USX]], align 2
43012 // SIMD-ONLY0-NEXT:    [[CONV2347:%.*]] = zext i16 [[TMP1454]] to i32
43013 // SIMD-ONLY0-NEXT:    [[TMP1455:%.*]] = load i16, ptr [[USE]], align 2
43014 // SIMD-ONLY0-NEXT:    [[CONV2348:%.*]] = zext i16 [[TMP1455]] to i32
43015 // SIMD-ONLY0-NEXT:    [[CMP2349:%.*]] = icmp eq i32 [[CONV2347]], [[CONV2348]]
43016 // SIMD-ONLY0-NEXT:    br i1 [[CMP2349]], label [[IF_THEN2351:%.*]], label [[IF_ELSE2352:%.*]]
43017 // SIMD-ONLY0:       if.then2351:
43018 // SIMD-ONLY0-NEXT:    [[TMP1456:%.*]] = load i16, ptr [[USD]], align 2
43019 // SIMD-ONLY0-NEXT:    store i16 [[TMP1456]], ptr [[USX]], align 2
43020 // SIMD-ONLY0-NEXT:    br label [[IF_END2353:%.*]]
43021 // SIMD-ONLY0:       if.else2352:
43022 // SIMD-ONLY0-NEXT:    [[TMP1457:%.*]] = load i16, ptr [[USX]], align 2
43023 // SIMD-ONLY0-NEXT:    store i16 [[TMP1457]], ptr [[USV]], align 2
43024 // SIMD-ONLY0-NEXT:    br label [[IF_END2353]]
43025 // SIMD-ONLY0:       if.end2353:
43026 // SIMD-ONLY0-NEXT:    [[TMP1458:%.*]] = load i16, ptr [[USE]], align 2
43027 // SIMD-ONLY0-NEXT:    [[CONV2354:%.*]] = zext i16 [[TMP1458]] to i32
43028 // SIMD-ONLY0-NEXT:    [[TMP1459:%.*]] = load i16, ptr [[USX]], align 2
43029 // SIMD-ONLY0-NEXT:    [[CONV2355:%.*]] = zext i16 [[TMP1459]] to i32
43030 // SIMD-ONLY0-NEXT:    [[CMP2356:%.*]] = icmp eq i32 [[CONV2354]], [[CONV2355]]
43031 // SIMD-ONLY0-NEXT:    br i1 [[CMP2356]], label [[IF_THEN2358:%.*]], label [[IF_ELSE2359:%.*]]
43032 // SIMD-ONLY0:       if.then2358:
43033 // SIMD-ONLY0-NEXT:    [[TMP1460:%.*]] = load i16, ptr [[USD]], align 2
43034 // SIMD-ONLY0-NEXT:    store i16 [[TMP1460]], ptr [[USX]], align 2
43035 // SIMD-ONLY0-NEXT:    br label [[IF_END2360:%.*]]
43036 // SIMD-ONLY0:       if.else2359:
43037 // SIMD-ONLY0-NEXT:    [[TMP1461:%.*]] = load i16, ptr [[USX]], align 2
43038 // SIMD-ONLY0-NEXT:    store i16 [[TMP1461]], ptr [[USV]], align 2
43039 // SIMD-ONLY0-NEXT:    br label [[IF_END2360]]
43040 // SIMD-ONLY0:       if.end2360:
43041 // SIMD-ONLY0-NEXT:    [[TMP1462:%.*]] = load i16, ptr [[USX]], align 2
43042 // SIMD-ONLY0-NEXT:    [[CONV2361:%.*]] = zext i16 [[TMP1462]] to i32
43043 // SIMD-ONLY0-NEXT:    [[TMP1463:%.*]] = load i16, ptr [[USE]], align 2
43044 // SIMD-ONLY0-NEXT:    [[CONV2362:%.*]] = zext i16 [[TMP1463]] to i32
43045 // SIMD-ONLY0-NEXT:    [[CMP2363:%.*]] = icmp eq i32 [[CONV2361]], [[CONV2362]]
43046 // SIMD-ONLY0-NEXT:    [[CONV2364:%.*]] = zext i1 [[CMP2363]] to i32
43047 // SIMD-ONLY0-NEXT:    [[CONV2365:%.*]] = trunc i32 [[CONV2364]] to i16
43048 // SIMD-ONLY0-NEXT:    store i16 [[CONV2365]], ptr [[USR]], align 2
43049 // SIMD-ONLY0-NEXT:    [[TMP1464:%.*]] = load i16, ptr [[USR]], align 2
43050 // SIMD-ONLY0-NEXT:    [[TOBOOL2366:%.*]] = icmp ne i16 [[TMP1464]], 0
43051 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2366]], label [[IF_THEN2367:%.*]], label [[IF_END2368:%.*]]
43052 // SIMD-ONLY0:       if.then2367:
43053 // SIMD-ONLY0-NEXT:    [[TMP1465:%.*]] = load i16, ptr [[USD]], align 2
43054 // SIMD-ONLY0-NEXT:    store i16 [[TMP1465]], ptr [[USX]], align 2
43055 // SIMD-ONLY0-NEXT:    br label [[IF_END2368]]
43056 // SIMD-ONLY0:       if.end2368:
43057 // SIMD-ONLY0-NEXT:    [[TMP1466:%.*]] = load i16, ptr [[USE]], align 2
43058 // SIMD-ONLY0-NEXT:    [[CONV2369:%.*]] = zext i16 [[TMP1466]] to i32
43059 // SIMD-ONLY0-NEXT:    [[TMP1467:%.*]] = load i16, ptr [[USX]], align 2
43060 // SIMD-ONLY0-NEXT:    [[CONV2370:%.*]] = zext i16 [[TMP1467]] to i32
43061 // SIMD-ONLY0-NEXT:    [[CMP2371:%.*]] = icmp eq i32 [[CONV2369]], [[CONV2370]]
43062 // SIMD-ONLY0-NEXT:    [[CONV2372:%.*]] = zext i1 [[CMP2371]] to i32
43063 // SIMD-ONLY0-NEXT:    [[CONV2373:%.*]] = trunc i32 [[CONV2372]] to i16
43064 // SIMD-ONLY0-NEXT:    store i16 [[CONV2373]], ptr [[USR]], align 2
43065 // SIMD-ONLY0-NEXT:    [[TMP1468:%.*]] = load i16, ptr [[USR]], align 2
43066 // SIMD-ONLY0-NEXT:    [[TOBOOL2374:%.*]] = icmp ne i16 [[TMP1468]], 0
43067 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2374]], label [[IF_THEN2375:%.*]], label [[IF_END2376:%.*]]
43068 // SIMD-ONLY0:       if.then2375:
43069 // SIMD-ONLY0-NEXT:    [[TMP1469:%.*]] = load i16, ptr [[USD]], align 2
43070 // SIMD-ONLY0-NEXT:    store i16 [[TMP1469]], ptr [[USX]], align 2
43071 // SIMD-ONLY0-NEXT:    br label [[IF_END2376]]
43072 // SIMD-ONLY0:       if.end2376:
43073 // SIMD-ONLY0-NEXT:    [[TMP1470:%.*]] = load i16, ptr [[USX]], align 2
43074 // SIMD-ONLY0-NEXT:    [[CONV2377:%.*]] = zext i16 [[TMP1470]] to i32
43075 // SIMD-ONLY0-NEXT:    [[TMP1471:%.*]] = load i16, ptr [[USE]], align 2
43076 // SIMD-ONLY0-NEXT:    [[CONV2378:%.*]] = zext i16 [[TMP1471]] to i32
43077 // SIMD-ONLY0-NEXT:    [[CMP2379:%.*]] = icmp eq i32 [[CONV2377]], [[CONV2378]]
43078 // SIMD-ONLY0-NEXT:    [[CONV2380:%.*]] = zext i1 [[CMP2379]] to i32
43079 // SIMD-ONLY0-NEXT:    [[CONV2381:%.*]] = trunc i32 [[CONV2380]] to i16
43080 // SIMD-ONLY0-NEXT:    store i16 [[CONV2381]], ptr [[USR]], align 2
43081 // SIMD-ONLY0-NEXT:    [[TMP1472:%.*]] = load i16, ptr [[USR]], align 2
43082 // SIMD-ONLY0-NEXT:    [[TOBOOL2382:%.*]] = icmp ne i16 [[TMP1472]], 0
43083 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2382]], label [[IF_THEN2383:%.*]], label [[IF_ELSE2384:%.*]]
43084 // SIMD-ONLY0:       if.then2383:
43085 // SIMD-ONLY0-NEXT:    [[TMP1473:%.*]] = load i16, ptr [[USD]], align 2
43086 // SIMD-ONLY0-NEXT:    store i16 [[TMP1473]], ptr [[USX]], align 2
43087 // SIMD-ONLY0-NEXT:    br label [[IF_END2385:%.*]]
43088 // SIMD-ONLY0:       if.else2384:
43089 // SIMD-ONLY0-NEXT:    [[TMP1474:%.*]] = load i16, ptr [[USX]], align 2
43090 // SIMD-ONLY0-NEXT:    store i16 [[TMP1474]], ptr [[USV]], align 2
43091 // SIMD-ONLY0-NEXT:    br label [[IF_END2385]]
43092 // SIMD-ONLY0:       if.end2385:
43093 // SIMD-ONLY0-NEXT:    [[TMP1475:%.*]] = load i16, ptr [[USE]], align 2
43094 // SIMD-ONLY0-NEXT:    [[CONV2386:%.*]] = zext i16 [[TMP1475]] to i32
43095 // SIMD-ONLY0-NEXT:    [[TMP1476:%.*]] = load i16, ptr [[USX]], align 2
43096 // SIMD-ONLY0-NEXT:    [[CONV2387:%.*]] = zext i16 [[TMP1476]] to i32
43097 // SIMD-ONLY0-NEXT:    [[CMP2388:%.*]] = icmp eq i32 [[CONV2386]], [[CONV2387]]
43098 // SIMD-ONLY0-NEXT:    [[CONV2389:%.*]] = zext i1 [[CMP2388]] to i32
43099 // SIMD-ONLY0-NEXT:    [[CONV2390:%.*]] = trunc i32 [[CONV2389]] to i16
43100 // SIMD-ONLY0-NEXT:    store i16 [[CONV2390]], ptr [[USR]], align 2
43101 // SIMD-ONLY0-NEXT:    [[TMP1477:%.*]] = load i16, ptr [[USR]], align 2
43102 // SIMD-ONLY0-NEXT:    [[TOBOOL2391:%.*]] = icmp ne i16 [[TMP1477]], 0
43103 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2391]], label [[IF_THEN2392:%.*]], label [[IF_ELSE2393:%.*]]
43104 // SIMD-ONLY0:       if.then2392:
43105 // SIMD-ONLY0-NEXT:    [[TMP1478:%.*]] = load i16, ptr [[USD]], align 2
43106 // SIMD-ONLY0-NEXT:    store i16 [[TMP1478]], ptr [[USX]], align 2
43107 // SIMD-ONLY0-NEXT:    br label [[IF_END2394:%.*]]
43108 // SIMD-ONLY0:       if.else2393:
43109 // SIMD-ONLY0-NEXT:    [[TMP1479:%.*]] = load i16, ptr [[USX]], align 2
43110 // SIMD-ONLY0-NEXT:    store i16 [[TMP1479]], ptr [[USV]], align 2
43111 // SIMD-ONLY0-NEXT:    br label [[IF_END2394]]
43112 // SIMD-ONLY0:       if.end2394:
43113 // SIMD-ONLY0-NEXT:    [[TMP1480:%.*]] = load i16, ptr [[USX]], align 2
43114 // SIMD-ONLY0-NEXT:    store i16 [[TMP1480]], ptr [[USV]], align 2
43115 // SIMD-ONLY0-NEXT:    [[TMP1481:%.*]] = load i16, ptr [[USE]], align 2
43116 // SIMD-ONLY0-NEXT:    [[CONV2395:%.*]] = zext i16 [[TMP1481]] to i32
43117 // SIMD-ONLY0-NEXT:    [[TMP1482:%.*]] = load i16, ptr [[USX]], align 2
43118 // SIMD-ONLY0-NEXT:    [[CONV2396:%.*]] = zext i16 [[TMP1482]] to i32
43119 // SIMD-ONLY0-NEXT:    [[CMP2397:%.*]] = icmp sgt i32 [[CONV2395]], [[CONV2396]]
43120 // SIMD-ONLY0-NEXT:    br i1 [[CMP2397]], label [[IF_THEN2399:%.*]], label [[IF_END2400:%.*]]
43121 // SIMD-ONLY0:       if.then2399:
43122 // SIMD-ONLY0-NEXT:    [[TMP1483:%.*]] = load i16, ptr [[USE]], align 2
43123 // SIMD-ONLY0-NEXT:    store i16 [[TMP1483]], ptr [[USX]], align 2
43124 // SIMD-ONLY0-NEXT:    br label [[IF_END2400]]
43125 // SIMD-ONLY0:       if.end2400:
43126 // SIMD-ONLY0-NEXT:    [[TMP1484:%.*]] = load i16, ptr [[USX]], align 2
43127 // SIMD-ONLY0-NEXT:    store i16 [[TMP1484]], ptr [[USV]], align 2
43128 // SIMD-ONLY0-NEXT:    [[TMP1485:%.*]] = load i16, ptr [[USX]], align 2
43129 // SIMD-ONLY0-NEXT:    [[CONV2401:%.*]] = zext i16 [[TMP1485]] to i32
43130 // SIMD-ONLY0-NEXT:    [[TMP1486:%.*]] = load i16, ptr [[USE]], align 2
43131 // SIMD-ONLY0-NEXT:    [[CONV2402:%.*]] = zext i16 [[TMP1486]] to i32
43132 // SIMD-ONLY0-NEXT:    [[CMP2403:%.*]] = icmp sgt i32 [[CONV2401]], [[CONV2402]]
43133 // SIMD-ONLY0-NEXT:    br i1 [[CMP2403]], label [[IF_THEN2405:%.*]], label [[IF_END2406:%.*]]
43134 // SIMD-ONLY0:       if.then2405:
43135 // SIMD-ONLY0-NEXT:    [[TMP1487:%.*]] = load i16, ptr [[USE]], align 2
43136 // SIMD-ONLY0-NEXT:    store i16 [[TMP1487]], ptr [[USX]], align 2
43137 // SIMD-ONLY0-NEXT:    br label [[IF_END2406]]
43138 // SIMD-ONLY0:       if.end2406:
43139 // SIMD-ONLY0-NEXT:    [[TMP1488:%.*]] = load i16, ptr [[USX]], align 2
43140 // SIMD-ONLY0-NEXT:    store i16 [[TMP1488]], ptr [[USV]], align 2
43141 // SIMD-ONLY0-NEXT:    [[TMP1489:%.*]] = load i16, ptr [[USE]], align 2
43142 // SIMD-ONLY0-NEXT:    [[CONV2407:%.*]] = zext i16 [[TMP1489]] to i32
43143 // SIMD-ONLY0-NEXT:    [[TMP1490:%.*]] = load i16, ptr [[USX]], align 2
43144 // SIMD-ONLY0-NEXT:    [[CONV2408:%.*]] = zext i16 [[TMP1490]] to i32
43145 // SIMD-ONLY0-NEXT:    [[CMP2409:%.*]] = icmp slt i32 [[CONV2407]], [[CONV2408]]
43146 // SIMD-ONLY0-NEXT:    br i1 [[CMP2409]], label [[IF_THEN2411:%.*]], label [[IF_END2412:%.*]]
43147 // SIMD-ONLY0:       if.then2411:
43148 // SIMD-ONLY0-NEXT:    [[TMP1491:%.*]] = load i16, ptr [[USE]], align 2
43149 // SIMD-ONLY0-NEXT:    store i16 [[TMP1491]], ptr [[USX]], align 2
43150 // SIMD-ONLY0-NEXT:    br label [[IF_END2412]]
43151 // SIMD-ONLY0:       if.end2412:
43152 // SIMD-ONLY0-NEXT:    [[TMP1492:%.*]] = load i16, ptr [[USX]], align 2
43153 // SIMD-ONLY0-NEXT:    store i16 [[TMP1492]], ptr [[USV]], align 2
43154 // SIMD-ONLY0-NEXT:    [[TMP1493:%.*]] = load i16, ptr [[USX]], align 2
43155 // SIMD-ONLY0-NEXT:    [[CONV2413:%.*]] = zext i16 [[TMP1493]] to i32
43156 // SIMD-ONLY0-NEXT:    [[TMP1494:%.*]] = load i16, ptr [[USE]], align 2
43157 // SIMD-ONLY0-NEXT:    [[CONV2414:%.*]] = zext i16 [[TMP1494]] to i32
43158 // SIMD-ONLY0-NEXT:    [[CMP2415:%.*]] = icmp slt i32 [[CONV2413]], [[CONV2414]]
43159 // SIMD-ONLY0-NEXT:    br i1 [[CMP2415]], label [[IF_THEN2417:%.*]], label [[IF_END2418:%.*]]
43160 // SIMD-ONLY0:       if.then2417:
43161 // SIMD-ONLY0-NEXT:    [[TMP1495:%.*]] = load i16, ptr [[USE]], align 2
43162 // SIMD-ONLY0-NEXT:    store i16 [[TMP1495]], ptr [[USX]], align 2
43163 // SIMD-ONLY0-NEXT:    br label [[IF_END2418]]
43164 // SIMD-ONLY0:       if.end2418:
43165 // SIMD-ONLY0-NEXT:    [[TMP1496:%.*]] = load i16, ptr [[USX]], align 2
43166 // SIMD-ONLY0-NEXT:    store i16 [[TMP1496]], ptr [[USV]], align 2
43167 // SIMD-ONLY0-NEXT:    [[TMP1497:%.*]] = load i16, ptr [[USX]], align 2
43168 // SIMD-ONLY0-NEXT:    [[CONV2419:%.*]] = zext i16 [[TMP1497]] to i32
43169 // SIMD-ONLY0-NEXT:    [[TMP1498:%.*]] = load i16, ptr [[USE]], align 2
43170 // SIMD-ONLY0-NEXT:    [[CONV2420:%.*]] = zext i16 [[TMP1498]] to i32
43171 // SIMD-ONLY0-NEXT:    [[CMP2421:%.*]] = icmp eq i32 [[CONV2419]], [[CONV2420]]
43172 // SIMD-ONLY0-NEXT:    br i1 [[CMP2421]], label [[IF_THEN2423:%.*]], label [[IF_END2424:%.*]]
43173 // SIMD-ONLY0:       if.then2423:
43174 // SIMD-ONLY0-NEXT:    [[TMP1499:%.*]] = load i16, ptr [[USD]], align 2
43175 // SIMD-ONLY0-NEXT:    store i16 [[TMP1499]], ptr [[USX]], align 2
43176 // SIMD-ONLY0-NEXT:    br label [[IF_END2424]]
43177 // SIMD-ONLY0:       if.end2424:
43178 // SIMD-ONLY0-NEXT:    [[TMP1500:%.*]] = load i16, ptr [[USX]], align 2
43179 // SIMD-ONLY0-NEXT:    store i16 [[TMP1500]], ptr [[USV]], align 2
43180 // SIMD-ONLY0-NEXT:    [[TMP1501:%.*]] = load i16, ptr [[USE]], align 2
43181 // SIMD-ONLY0-NEXT:    [[CONV2425:%.*]] = zext i16 [[TMP1501]] to i32
43182 // SIMD-ONLY0-NEXT:    [[TMP1502:%.*]] = load i16, ptr [[USX]], align 2
43183 // SIMD-ONLY0-NEXT:    [[CONV2426:%.*]] = zext i16 [[TMP1502]] to i32
43184 // SIMD-ONLY0-NEXT:    [[CMP2427:%.*]] = icmp eq i32 [[CONV2425]], [[CONV2426]]
43185 // SIMD-ONLY0-NEXT:    br i1 [[CMP2427]], label [[IF_THEN2429:%.*]], label [[IF_END2430:%.*]]
43186 // SIMD-ONLY0:       if.then2429:
43187 // SIMD-ONLY0-NEXT:    [[TMP1503:%.*]] = load i16, ptr [[USD]], align 2
43188 // SIMD-ONLY0-NEXT:    store i16 [[TMP1503]], ptr [[USX]], align 2
43189 // SIMD-ONLY0-NEXT:    br label [[IF_END2430]]
43190 // SIMD-ONLY0:       if.end2430:
43191 // SIMD-ONLY0-NEXT:    [[TMP1504:%.*]] = load i16, ptr [[USE]], align 2
43192 // SIMD-ONLY0-NEXT:    [[CONV2431:%.*]] = zext i16 [[TMP1504]] to i32
43193 // SIMD-ONLY0-NEXT:    [[TMP1505:%.*]] = load i16, ptr [[USX]], align 2
43194 // SIMD-ONLY0-NEXT:    [[CONV2432:%.*]] = zext i16 [[TMP1505]] to i32
43195 // SIMD-ONLY0-NEXT:    [[CMP2433:%.*]] = icmp sgt i32 [[CONV2431]], [[CONV2432]]
43196 // SIMD-ONLY0-NEXT:    br i1 [[CMP2433]], label [[IF_THEN2435:%.*]], label [[IF_END2436:%.*]]
43197 // SIMD-ONLY0:       if.then2435:
43198 // SIMD-ONLY0-NEXT:    [[TMP1506:%.*]] = load i16, ptr [[USE]], align 2
43199 // SIMD-ONLY0-NEXT:    store i16 [[TMP1506]], ptr [[USX]], align 2
43200 // SIMD-ONLY0-NEXT:    br label [[IF_END2436]]
43201 // SIMD-ONLY0:       if.end2436:
43202 // SIMD-ONLY0-NEXT:    [[TMP1507:%.*]] = load i16, ptr [[USX]], align 2
43203 // SIMD-ONLY0-NEXT:    store i16 [[TMP1507]], ptr [[USV]], align 2
43204 // SIMD-ONLY0-NEXT:    [[TMP1508:%.*]] = load i16, ptr [[USX]], align 2
43205 // SIMD-ONLY0-NEXT:    [[CONV2437:%.*]] = zext i16 [[TMP1508]] to i32
43206 // SIMD-ONLY0-NEXT:    [[TMP1509:%.*]] = load i16, ptr [[USE]], align 2
43207 // SIMD-ONLY0-NEXT:    [[CONV2438:%.*]] = zext i16 [[TMP1509]] to i32
43208 // SIMD-ONLY0-NEXT:    [[CMP2439:%.*]] = icmp sgt i32 [[CONV2437]], [[CONV2438]]
43209 // SIMD-ONLY0-NEXT:    br i1 [[CMP2439]], label [[IF_THEN2441:%.*]], label [[IF_END2442:%.*]]
43210 // SIMD-ONLY0:       if.then2441:
43211 // SIMD-ONLY0-NEXT:    [[TMP1510:%.*]] = load i16, ptr [[USE]], align 2
43212 // SIMD-ONLY0-NEXT:    store i16 [[TMP1510]], ptr [[USX]], align 2
43213 // SIMD-ONLY0-NEXT:    br label [[IF_END2442]]
43214 // SIMD-ONLY0:       if.end2442:
43215 // SIMD-ONLY0-NEXT:    [[TMP1511:%.*]] = load i16, ptr [[USX]], align 2
43216 // SIMD-ONLY0-NEXT:    store i16 [[TMP1511]], ptr [[USV]], align 2
43217 // SIMD-ONLY0-NEXT:    [[TMP1512:%.*]] = load i16, ptr [[USE]], align 2
43218 // SIMD-ONLY0-NEXT:    [[CONV2443:%.*]] = zext i16 [[TMP1512]] to i32
43219 // SIMD-ONLY0-NEXT:    [[TMP1513:%.*]] = load i16, ptr [[USX]], align 2
43220 // SIMD-ONLY0-NEXT:    [[CONV2444:%.*]] = zext i16 [[TMP1513]] to i32
43221 // SIMD-ONLY0-NEXT:    [[CMP2445:%.*]] = icmp slt i32 [[CONV2443]], [[CONV2444]]
43222 // SIMD-ONLY0-NEXT:    br i1 [[CMP2445]], label [[IF_THEN2447:%.*]], label [[IF_END2448:%.*]]
43223 // SIMD-ONLY0:       if.then2447:
43224 // SIMD-ONLY0-NEXT:    [[TMP1514:%.*]] = load i16, ptr [[USE]], align 2
43225 // SIMD-ONLY0-NEXT:    store i16 [[TMP1514]], ptr [[USX]], align 2
43226 // SIMD-ONLY0-NEXT:    br label [[IF_END2448]]
43227 // SIMD-ONLY0:       if.end2448:
43228 // SIMD-ONLY0-NEXT:    [[TMP1515:%.*]] = load i16, ptr [[USX]], align 2
43229 // SIMD-ONLY0-NEXT:    store i16 [[TMP1515]], ptr [[USV]], align 2
43230 // SIMD-ONLY0-NEXT:    [[TMP1516:%.*]] = load i16, ptr [[USX]], align 2
43231 // SIMD-ONLY0-NEXT:    [[CONV2449:%.*]] = zext i16 [[TMP1516]] to i32
43232 // SIMD-ONLY0-NEXT:    [[TMP1517:%.*]] = load i16, ptr [[USE]], align 2
43233 // SIMD-ONLY0-NEXT:    [[CONV2450:%.*]] = zext i16 [[TMP1517]] to i32
43234 // SIMD-ONLY0-NEXT:    [[CMP2451:%.*]] = icmp slt i32 [[CONV2449]], [[CONV2450]]
43235 // SIMD-ONLY0-NEXT:    br i1 [[CMP2451]], label [[IF_THEN2453:%.*]], label [[IF_END2454:%.*]]
43236 // SIMD-ONLY0:       if.then2453:
43237 // SIMD-ONLY0-NEXT:    [[TMP1518:%.*]] = load i16, ptr [[USE]], align 2
43238 // SIMD-ONLY0-NEXT:    store i16 [[TMP1518]], ptr [[USX]], align 2
43239 // SIMD-ONLY0-NEXT:    br label [[IF_END2454]]
43240 // SIMD-ONLY0:       if.end2454:
43241 // SIMD-ONLY0-NEXT:    [[TMP1519:%.*]] = load i16, ptr [[USX]], align 2
43242 // SIMD-ONLY0-NEXT:    store i16 [[TMP1519]], ptr [[USV]], align 2
43243 // SIMD-ONLY0-NEXT:    [[TMP1520:%.*]] = load i16, ptr [[USX]], align 2
43244 // SIMD-ONLY0-NEXT:    [[CONV2455:%.*]] = zext i16 [[TMP1520]] to i32
43245 // SIMD-ONLY0-NEXT:    [[TMP1521:%.*]] = load i16, ptr [[USE]], align 2
43246 // SIMD-ONLY0-NEXT:    [[CONV2456:%.*]] = zext i16 [[TMP1521]] to i32
43247 // SIMD-ONLY0-NEXT:    [[CMP2457:%.*]] = icmp eq i32 [[CONV2455]], [[CONV2456]]
43248 // SIMD-ONLY0-NEXT:    br i1 [[CMP2457]], label [[IF_THEN2459:%.*]], label [[IF_END2460:%.*]]
43249 // SIMD-ONLY0:       if.then2459:
43250 // SIMD-ONLY0-NEXT:    [[TMP1522:%.*]] = load i16, ptr [[USD]], align 2
43251 // SIMD-ONLY0-NEXT:    store i16 [[TMP1522]], ptr [[USX]], align 2
43252 // SIMD-ONLY0-NEXT:    br label [[IF_END2460]]
43253 // SIMD-ONLY0:       if.end2460:
43254 // SIMD-ONLY0-NEXT:    [[TMP1523:%.*]] = load i16, ptr [[USX]], align 2
43255 // SIMD-ONLY0-NEXT:    store i16 [[TMP1523]], ptr [[USV]], align 2
43256 // SIMD-ONLY0-NEXT:    [[TMP1524:%.*]] = load i16, ptr [[USE]], align 2
43257 // SIMD-ONLY0-NEXT:    [[CONV2461:%.*]] = zext i16 [[TMP1524]] to i32
43258 // SIMD-ONLY0-NEXT:    [[TMP1525:%.*]] = load i16, ptr [[USX]], align 2
43259 // SIMD-ONLY0-NEXT:    [[CONV2462:%.*]] = zext i16 [[TMP1525]] to i32
43260 // SIMD-ONLY0-NEXT:    [[CMP2463:%.*]] = icmp eq i32 [[CONV2461]], [[CONV2462]]
43261 // SIMD-ONLY0-NEXT:    br i1 [[CMP2463]], label [[IF_THEN2465:%.*]], label [[IF_END2466:%.*]]
43262 // SIMD-ONLY0:       if.then2465:
43263 // SIMD-ONLY0-NEXT:    [[TMP1526:%.*]] = load i16, ptr [[USD]], align 2
43264 // SIMD-ONLY0-NEXT:    store i16 [[TMP1526]], ptr [[USX]], align 2
43265 // SIMD-ONLY0-NEXT:    br label [[IF_END2466]]
43266 // SIMD-ONLY0:       if.end2466:
43267 // SIMD-ONLY0-NEXT:    [[TMP1527:%.*]] = load i16, ptr [[USX]], align 2
43268 // SIMD-ONLY0-NEXT:    store i16 [[TMP1527]], ptr [[USV]], align 2
43269 // SIMD-ONLY0-NEXT:    [[TMP1528:%.*]] = load i16, ptr [[USX]], align 2
43270 // SIMD-ONLY0-NEXT:    [[CONV2467:%.*]] = zext i16 [[TMP1528]] to i32
43271 // SIMD-ONLY0-NEXT:    [[TMP1529:%.*]] = load i16, ptr [[USE]], align 2
43272 // SIMD-ONLY0-NEXT:    [[CONV2468:%.*]] = zext i16 [[TMP1529]] to i32
43273 // SIMD-ONLY0-NEXT:    [[CMP2469:%.*]] = icmp eq i32 [[CONV2467]], [[CONV2468]]
43274 // SIMD-ONLY0-NEXT:    br i1 [[CMP2469]], label [[IF_THEN2471:%.*]], label [[IF_ELSE2472:%.*]]
43275 // SIMD-ONLY0:       if.then2471:
43276 // SIMD-ONLY0-NEXT:    [[TMP1530:%.*]] = load i16, ptr [[USD]], align 2
43277 // SIMD-ONLY0-NEXT:    store i16 [[TMP1530]], ptr [[USX]], align 2
43278 // SIMD-ONLY0-NEXT:    br label [[IF_END2473:%.*]]
43279 // SIMD-ONLY0:       if.else2472:
43280 // SIMD-ONLY0-NEXT:    [[TMP1531:%.*]] = load i16, ptr [[USX]], align 2
43281 // SIMD-ONLY0-NEXT:    store i16 [[TMP1531]], ptr [[USV]], align 2
43282 // SIMD-ONLY0-NEXT:    br label [[IF_END2473]]
43283 // SIMD-ONLY0:       if.end2473:
43284 // SIMD-ONLY0-NEXT:    [[TMP1532:%.*]] = load i16, ptr [[USE]], align 2
43285 // SIMD-ONLY0-NEXT:    [[CONV2474:%.*]] = zext i16 [[TMP1532]] to i32
43286 // SIMD-ONLY0-NEXT:    [[TMP1533:%.*]] = load i16, ptr [[USX]], align 2
43287 // SIMD-ONLY0-NEXT:    [[CONV2475:%.*]] = zext i16 [[TMP1533]] to i32
43288 // SIMD-ONLY0-NEXT:    [[CMP2476:%.*]] = icmp eq i32 [[CONV2474]], [[CONV2475]]
43289 // SIMD-ONLY0-NEXT:    br i1 [[CMP2476]], label [[IF_THEN2478:%.*]], label [[IF_ELSE2479:%.*]]
43290 // SIMD-ONLY0:       if.then2478:
43291 // SIMD-ONLY0-NEXT:    [[TMP1534:%.*]] = load i16, ptr [[USD]], align 2
43292 // SIMD-ONLY0-NEXT:    store i16 [[TMP1534]], ptr [[USX]], align 2
43293 // SIMD-ONLY0-NEXT:    br label [[IF_END2480:%.*]]
43294 // SIMD-ONLY0:       if.else2479:
43295 // SIMD-ONLY0-NEXT:    [[TMP1535:%.*]] = load i16, ptr [[USX]], align 2
43296 // SIMD-ONLY0-NEXT:    store i16 [[TMP1535]], ptr [[USV]], align 2
43297 // SIMD-ONLY0-NEXT:    br label [[IF_END2480]]
43298 // SIMD-ONLY0:       if.end2480:
43299 // SIMD-ONLY0-NEXT:    [[TMP1536:%.*]] = load i16, ptr [[USX]], align 2
43300 // SIMD-ONLY0-NEXT:    [[CONV2481:%.*]] = zext i16 [[TMP1536]] to i32
43301 // SIMD-ONLY0-NEXT:    [[TMP1537:%.*]] = load i16, ptr [[USE]], align 2
43302 // SIMD-ONLY0-NEXT:    [[CONV2482:%.*]] = zext i16 [[TMP1537]] to i32
43303 // SIMD-ONLY0-NEXT:    [[CMP2483:%.*]] = icmp eq i32 [[CONV2481]], [[CONV2482]]
43304 // SIMD-ONLY0-NEXT:    [[CONV2484:%.*]] = zext i1 [[CMP2483]] to i32
43305 // SIMD-ONLY0-NEXT:    [[CONV2485:%.*]] = trunc i32 [[CONV2484]] to i16
43306 // SIMD-ONLY0-NEXT:    store i16 [[CONV2485]], ptr [[USR]], align 2
43307 // SIMD-ONLY0-NEXT:    [[TMP1538:%.*]] = load i16, ptr [[USR]], align 2
43308 // SIMD-ONLY0-NEXT:    [[TOBOOL2486:%.*]] = icmp ne i16 [[TMP1538]], 0
43309 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2486]], label [[IF_THEN2487:%.*]], label [[IF_END2488:%.*]]
43310 // SIMD-ONLY0:       if.then2487:
43311 // SIMD-ONLY0-NEXT:    [[TMP1539:%.*]] = load i16, ptr [[USD]], align 2
43312 // SIMD-ONLY0-NEXT:    store i16 [[TMP1539]], ptr [[USX]], align 2
43313 // SIMD-ONLY0-NEXT:    br label [[IF_END2488]]
43314 // SIMD-ONLY0:       if.end2488:
43315 // SIMD-ONLY0-NEXT:    [[TMP1540:%.*]] = load i16, ptr [[USE]], align 2
43316 // SIMD-ONLY0-NEXT:    [[CONV2489:%.*]] = zext i16 [[TMP1540]] to i32
43317 // SIMD-ONLY0-NEXT:    [[TMP1541:%.*]] = load i16, ptr [[USX]], align 2
43318 // SIMD-ONLY0-NEXT:    [[CONV2490:%.*]] = zext i16 [[TMP1541]] to i32
43319 // SIMD-ONLY0-NEXT:    [[CMP2491:%.*]] = icmp eq i32 [[CONV2489]], [[CONV2490]]
43320 // SIMD-ONLY0-NEXT:    [[CONV2492:%.*]] = zext i1 [[CMP2491]] to i32
43321 // SIMD-ONLY0-NEXT:    [[CONV2493:%.*]] = trunc i32 [[CONV2492]] to i16
43322 // SIMD-ONLY0-NEXT:    store i16 [[CONV2493]], ptr [[USR]], align 2
43323 // SIMD-ONLY0-NEXT:    [[TMP1542:%.*]] = load i16, ptr [[USR]], align 2
43324 // SIMD-ONLY0-NEXT:    [[TOBOOL2494:%.*]] = icmp ne i16 [[TMP1542]], 0
43325 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2494]], label [[IF_THEN2495:%.*]], label [[IF_END2496:%.*]]
43326 // SIMD-ONLY0:       if.then2495:
43327 // SIMD-ONLY0-NEXT:    [[TMP1543:%.*]] = load i16, ptr [[USD]], align 2
43328 // SIMD-ONLY0-NEXT:    store i16 [[TMP1543]], ptr [[USX]], align 2
43329 // SIMD-ONLY0-NEXT:    br label [[IF_END2496]]
43330 // SIMD-ONLY0:       if.end2496:
43331 // SIMD-ONLY0-NEXT:    [[TMP1544:%.*]] = load i16, ptr [[USX]], align 2
43332 // SIMD-ONLY0-NEXT:    [[CONV2497:%.*]] = zext i16 [[TMP1544]] to i32
43333 // SIMD-ONLY0-NEXT:    [[TMP1545:%.*]] = load i16, ptr [[USE]], align 2
43334 // SIMD-ONLY0-NEXT:    [[CONV2498:%.*]] = zext i16 [[TMP1545]] to i32
43335 // SIMD-ONLY0-NEXT:    [[CMP2499:%.*]] = icmp eq i32 [[CONV2497]], [[CONV2498]]
43336 // SIMD-ONLY0-NEXT:    [[CONV2500:%.*]] = zext i1 [[CMP2499]] to i32
43337 // SIMD-ONLY0-NEXT:    [[CONV2501:%.*]] = trunc i32 [[CONV2500]] to i16
43338 // SIMD-ONLY0-NEXT:    store i16 [[CONV2501]], ptr [[USR]], align 2
43339 // SIMD-ONLY0-NEXT:    [[TMP1546:%.*]] = load i16, ptr [[USR]], align 2
43340 // SIMD-ONLY0-NEXT:    [[TOBOOL2502:%.*]] = icmp ne i16 [[TMP1546]], 0
43341 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2502]], label [[IF_THEN2503:%.*]], label [[IF_ELSE2504:%.*]]
43342 // SIMD-ONLY0:       if.then2503:
43343 // SIMD-ONLY0-NEXT:    [[TMP1547:%.*]] = load i16, ptr [[USD]], align 2
43344 // SIMD-ONLY0-NEXT:    store i16 [[TMP1547]], ptr [[USX]], align 2
43345 // SIMD-ONLY0-NEXT:    br label [[IF_END2505:%.*]]
43346 // SIMD-ONLY0:       if.else2504:
43347 // SIMD-ONLY0-NEXT:    [[TMP1548:%.*]] = load i16, ptr [[USX]], align 2
43348 // SIMD-ONLY0-NEXT:    store i16 [[TMP1548]], ptr [[USV]], align 2
43349 // SIMD-ONLY0-NEXT:    br label [[IF_END2505]]
43350 // SIMD-ONLY0:       if.end2505:
43351 // SIMD-ONLY0-NEXT:    [[TMP1549:%.*]] = load i16, ptr [[USE]], align 2
43352 // SIMD-ONLY0-NEXT:    [[CONV2506:%.*]] = zext i16 [[TMP1549]] to i32
43353 // SIMD-ONLY0-NEXT:    [[TMP1550:%.*]] = load i16, ptr [[USX]], align 2
43354 // SIMD-ONLY0-NEXT:    [[CONV2507:%.*]] = zext i16 [[TMP1550]] to i32
43355 // SIMD-ONLY0-NEXT:    [[CMP2508:%.*]] = icmp eq i32 [[CONV2506]], [[CONV2507]]
43356 // SIMD-ONLY0-NEXT:    [[CONV2509:%.*]] = zext i1 [[CMP2508]] to i32
43357 // SIMD-ONLY0-NEXT:    [[CONV2510:%.*]] = trunc i32 [[CONV2509]] to i16
43358 // SIMD-ONLY0-NEXT:    store i16 [[CONV2510]], ptr [[USR]], align 2
43359 // SIMD-ONLY0-NEXT:    [[TMP1551:%.*]] = load i16, ptr [[USR]], align 2
43360 // SIMD-ONLY0-NEXT:    [[TOBOOL2511:%.*]] = icmp ne i16 [[TMP1551]], 0
43361 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2511]], label [[IF_THEN2512:%.*]], label [[IF_ELSE2513:%.*]]
43362 // SIMD-ONLY0:       if.then2512:
43363 // SIMD-ONLY0-NEXT:    [[TMP1552:%.*]] = load i16, ptr [[USD]], align 2
43364 // SIMD-ONLY0-NEXT:    store i16 [[TMP1552]], ptr [[USX]], align 2
43365 // SIMD-ONLY0-NEXT:    br label [[IF_END2514:%.*]]
43366 // SIMD-ONLY0:       if.else2513:
43367 // SIMD-ONLY0-NEXT:    [[TMP1553:%.*]] = load i16, ptr [[USX]], align 2
43368 // SIMD-ONLY0-NEXT:    store i16 [[TMP1553]], ptr [[USV]], align 2
43369 // SIMD-ONLY0-NEXT:    br label [[IF_END2514]]
43370 // SIMD-ONLY0:       if.end2514:
43371 // SIMD-ONLY0-NEXT:    [[TMP1554:%.*]] = load i16, ptr [[USX]], align 2
43372 // SIMD-ONLY0-NEXT:    store i16 [[TMP1554]], ptr [[USV]], align 2
43373 // SIMD-ONLY0-NEXT:    [[TMP1555:%.*]] = load i16, ptr [[USE]], align 2
43374 // SIMD-ONLY0-NEXT:    [[CONV2515:%.*]] = zext i16 [[TMP1555]] to i32
43375 // SIMD-ONLY0-NEXT:    [[TMP1556:%.*]] = load i16, ptr [[USX]], align 2
43376 // SIMD-ONLY0-NEXT:    [[CONV2516:%.*]] = zext i16 [[TMP1556]] to i32
43377 // SIMD-ONLY0-NEXT:    [[CMP2517:%.*]] = icmp sgt i32 [[CONV2515]], [[CONV2516]]
43378 // SIMD-ONLY0-NEXT:    br i1 [[CMP2517]], label [[IF_THEN2519:%.*]], label [[IF_END2520:%.*]]
43379 // SIMD-ONLY0:       if.then2519:
43380 // SIMD-ONLY0-NEXT:    [[TMP1557:%.*]] = load i16, ptr [[USE]], align 2
43381 // SIMD-ONLY0-NEXT:    store i16 [[TMP1557]], ptr [[USX]], align 2
43382 // SIMD-ONLY0-NEXT:    br label [[IF_END2520]]
43383 // SIMD-ONLY0:       if.end2520:
43384 // SIMD-ONLY0-NEXT:    [[TMP1558:%.*]] = load i16, ptr [[USX]], align 2
43385 // SIMD-ONLY0-NEXT:    store i16 [[TMP1558]], ptr [[USV]], align 2
43386 // SIMD-ONLY0-NEXT:    [[TMP1559:%.*]] = load i16, ptr [[USX]], align 2
43387 // SIMD-ONLY0-NEXT:    [[CONV2521:%.*]] = zext i16 [[TMP1559]] to i32
43388 // SIMD-ONLY0-NEXT:    [[TMP1560:%.*]] = load i16, ptr [[USE]], align 2
43389 // SIMD-ONLY0-NEXT:    [[CONV2522:%.*]] = zext i16 [[TMP1560]] to i32
43390 // SIMD-ONLY0-NEXT:    [[CMP2523:%.*]] = icmp sgt i32 [[CONV2521]], [[CONV2522]]
43391 // SIMD-ONLY0-NEXT:    br i1 [[CMP2523]], label [[IF_THEN2525:%.*]], label [[IF_END2526:%.*]]
43392 // SIMD-ONLY0:       if.then2525:
43393 // SIMD-ONLY0-NEXT:    [[TMP1561:%.*]] = load i16, ptr [[USE]], align 2
43394 // SIMD-ONLY0-NEXT:    store i16 [[TMP1561]], ptr [[USX]], align 2
43395 // SIMD-ONLY0-NEXT:    br label [[IF_END2526]]
43396 // SIMD-ONLY0:       if.end2526:
43397 // SIMD-ONLY0-NEXT:    [[TMP1562:%.*]] = load i16, ptr [[USX]], align 2
43398 // SIMD-ONLY0-NEXT:    store i16 [[TMP1562]], ptr [[USV]], align 2
43399 // SIMD-ONLY0-NEXT:    [[TMP1563:%.*]] = load i16, ptr [[USE]], align 2
43400 // SIMD-ONLY0-NEXT:    [[CONV2527:%.*]] = zext i16 [[TMP1563]] to i32
43401 // SIMD-ONLY0-NEXT:    [[TMP1564:%.*]] = load i16, ptr [[USX]], align 2
43402 // SIMD-ONLY0-NEXT:    [[CONV2528:%.*]] = zext i16 [[TMP1564]] to i32
43403 // SIMD-ONLY0-NEXT:    [[CMP2529:%.*]] = icmp slt i32 [[CONV2527]], [[CONV2528]]
43404 // SIMD-ONLY0-NEXT:    br i1 [[CMP2529]], label [[IF_THEN2531:%.*]], label [[IF_END2532:%.*]]
43405 // SIMD-ONLY0:       if.then2531:
43406 // SIMD-ONLY0-NEXT:    [[TMP1565:%.*]] = load i16, ptr [[USE]], align 2
43407 // SIMD-ONLY0-NEXT:    store i16 [[TMP1565]], ptr [[USX]], align 2
43408 // SIMD-ONLY0-NEXT:    br label [[IF_END2532]]
43409 // SIMD-ONLY0:       if.end2532:
43410 // SIMD-ONLY0-NEXT:    [[TMP1566:%.*]] = load i16, ptr [[USX]], align 2
43411 // SIMD-ONLY0-NEXT:    store i16 [[TMP1566]], ptr [[USV]], align 2
43412 // SIMD-ONLY0-NEXT:    [[TMP1567:%.*]] = load i16, ptr [[USX]], align 2
43413 // SIMD-ONLY0-NEXT:    [[CONV2533:%.*]] = zext i16 [[TMP1567]] to i32
43414 // SIMD-ONLY0-NEXT:    [[TMP1568:%.*]] = load i16, ptr [[USE]], align 2
43415 // SIMD-ONLY0-NEXT:    [[CONV2534:%.*]] = zext i16 [[TMP1568]] to i32
43416 // SIMD-ONLY0-NEXT:    [[CMP2535:%.*]] = icmp slt i32 [[CONV2533]], [[CONV2534]]
43417 // SIMD-ONLY0-NEXT:    br i1 [[CMP2535]], label [[IF_THEN2537:%.*]], label [[IF_END2538:%.*]]
43418 // SIMD-ONLY0:       if.then2537:
43419 // SIMD-ONLY0-NEXT:    [[TMP1569:%.*]] = load i16, ptr [[USE]], align 2
43420 // SIMD-ONLY0-NEXT:    store i16 [[TMP1569]], ptr [[USX]], align 2
43421 // SIMD-ONLY0-NEXT:    br label [[IF_END2538]]
43422 // SIMD-ONLY0:       if.end2538:
43423 // SIMD-ONLY0-NEXT:    [[TMP1570:%.*]] = load i16, ptr [[USX]], align 2
43424 // SIMD-ONLY0-NEXT:    store i16 [[TMP1570]], ptr [[USV]], align 2
43425 // SIMD-ONLY0-NEXT:    [[TMP1571:%.*]] = load i16, ptr [[USX]], align 2
43426 // SIMD-ONLY0-NEXT:    [[CONV2539:%.*]] = zext i16 [[TMP1571]] to i32
43427 // SIMD-ONLY0-NEXT:    [[TMP1572:%.*]] = load i16, ptr [[USE]], align 2
43428 // SIMD-ONLY0-NEXT:    [[CONV2540:%.*]] = zext i16 [[TMP1572]] to i32
43429 // SIMD-ONLY0-NEXT:    [[CMP2541:%.*]] = icmp eq i32 [[CONV2539]], [[CONV2540]]
43430 // SIMD-ONLY0-NEXT:    br i1 [[CMP2541]], label [[IF_THEN2543:%.*]], label [[IF_END2544:%.*]]
43431 // SIMD-ONLY0:       if.then2543:
43432 // SIMD-ONLY0-NEXT:    [[TMP1573:%.*]] = load i16, ptr [[USD]], align 2
43433 // SIMD-ONLY0-NEXT:    store i16 [[TMP1573]], ptr [[USX]], align 2
43434 // SIMD-ONLY0-NEXT:    br label [[IF_END2544]]
43435 // SIMD-ONLY0:       if.end2544:
43436 // SIMD-ONLY0-NEXT:    [[TMP1574:%.*]] = load i16, ptr [[USX]], align 2
43437 // SIMD-ONLY0-NEXT:    store i16 [[TMP1574]], ptr [[USV]], align 2
43438 // SIMD-ONLY0-NEXT:    [[TMP1575:%.*]] = load i16, ptr [[USE]], align 2
43439 // SIMD-ONLY0-NEXT:    [[CONV2545:%.*]] = zext i16 [[TMP1575]] to i32
43440 // SIMD-ONLY0-NEXT:    [[TMP1576:%.*]] = load i16, ptr [[USX]], align 2
43441 // SIMD-ONLY0-NEXT:    [[CONV2546:%.*]] = zext i16 [[TMP1576]] to i32
43442 // SIMD-ONLY0-NEXT:    [[CMP2547:%.*]] = icmp eq i32 [[CONV2545]], [[CONV2546]]
43443 // SIMD-ONLY0-NEXT:    br i1 [[CMP2547]], label [[IF_THEN2549:%.*]], label [[IF_END2550:%.*]]
43444 // SIMD-ONLY0:       if.then2549:
43445 // SIMD-ONLY0-NEXT:    [[TMP1577:%.*]] = load i16, ptr [[USD]], align 2
43446 // SIMD-ONLY0-NEXT:    store i16 [[TMP1577]], ptr [[USX]], align 2
43447 // SIMD-ONLY0-NEXT:    br label [[IF_END2550]]
43448 // SIMD-ONLY0:       if.end2550:
43449 // SIMD-ONLY0-NEXT:    [[TMP1578:%.*]] = load i16, ptr [[USE]], align 2
43450 // SIMD-ONLY0-NEXT:    [[CONV2551:%.*]] = zext i16 [[TMP1578]] to i32
43451 // SIMD-ONLY0-NEXT:    [[TMP1579:%.*]] = load i16, ptr [[USX]], align 2
43452 // SIMD-ONLY0-NEXT:    [[CONV2552:%.*]] = zext i16 [[TMP1579]] to i32
43453 // SIMD-ONLY0-NEXT:    [[CMP2553:%.*]] = icmp sgt i32 [[CONV2551]], [[CONV2552]]
43454 // SIMD-ONLY0-NEXT:    br i1 [[CMP2553]], label [[IF_THEN2555:%.*]], label [[IF_END2556:%.*]]
43455 // SIMD-ONLY0:       if.then2555:
43456 // SIMD-ONLY0-NEXT:    [[TMP1580:%.*]] = load i16, ptr [[USE]], align 2
43457 // SIMD-ONLY0-NEXT:    store i16 [[TMP1580]], ptr [[USX]], align 2
43458 // SIMD-ONLY0-NEXT:    br label [[IF_END2556]]
43459 // SIMD-ONLY0:       if.end2556:
43460 // SIMD-ONLY0-NEXT:    [[TMP1581:%.*]] = load i16, ptr [[USX]], align 2
43461 // SIMD-ONLY0-NEXT:    store i16 [[TMP1581]], ptr [[USV]], align 2
43462 // SIMD-ONLY0-NEXT:    [[TMP1582:%.*]] = load i16, ptr [[USX]], align 2
43463 // SIMD-ONLY0-NEXT:    [[CONV2557:%.*]] = zext i16 [[TMP1582]] to i32
43464 // SIMD-ONLY0-NEXT:    [[TMP1583:%.*]] = load i16, ptr [[USE]], align 2
43465 // SIMD-ONLY0-NEXT:    [[CONV2558:%.*]] = zext i16 [[TMP1583]] to i32
43466 // SIMD-ONLY0-NEXT:    [[CMP2559:%.*]] = icmp sgt i32 [[CONV2557]], [[CONV2558]]
43467 // SIMD-ONLY0-NEXT:    br i1 [[CMP2559]], label [[IF_THEN2561:%.*]], label [[IF_END2562:%.*]]
43468 // SIMD-ONLY0:       if.then2561:
43469 // SIMD-ONLY0-NEXT:    [[TMP1584:%.*]] = load i16, ptr [[USE]], align 2
43470 // SIMD-ONLY0-NEXT:    store i16 [[TMP1584]], ptr [[USX]], align 2
43471 // SIMD-ONLY0-NEXT:    br label [[IF_END2562]]
43472 // SIMD-ONLY0:       if.end2562:
43473 // SIMD-ONLY0-NEXT:    [[TMP1585:%.*]] = load i16, ptr [[USX]], align 2
43474 // SIMD-ONLY0-NEXT:    store i16 [[TMP1585]], ptr [[USV]], align 2
43475 // SIMD-ONLY0-NEXT:    [[TMP1586:%.*]] = load i16, ptr [[USE]], align 2
43476 // SIMD-ONLY0-NEXT:    [[CONV2563:%.*]] = zext i16 [[TMP1586]] to i32
43477 // SIMD-ONLY0-NEXT:    [[TMP1587:%.*]] = load i16, ptr [[USX]], align 2
43478 // SIMD-ONLY0-NEXT:    [[CONV2564:%.*]] = zext i16 [[TMP1587]] to i32
43479 // SIMD-ONLY0-NEXT:    [[CMP2565:%.*]] = icmp slt i32 [[CONV2563]], [[CONV2564]]
43480 // SIMD-ONLY0-NEXT:    br i1 [[CMP2565]], label [[IF_THEN2567:%.*]], label [[IF_END2568:%.*]]
43481 // SIMD-ONLY0:       if.then2567:
43482 // SIMD-ONLY0-NEXT:    [[TMP1588:%.*]] = load i16, ptr [[USE]], align 2
43483 // SIMD-ONLY0-NEXT:    store i16 [[TMP1588]], ptr [[USX]], align 2
43484 // SIMD-ONLY0-NEXT:    br label [[IF_END2568]]
43485 // SIMD-ONLY0:       if.end2568:
43486 // SIMD-ONLY0-NEXT:    [[TMP1589:%.*]] = load i16, ptr [[USX]], align 2
43487 // SIMD-ONLY0-NEXT:    store i16 [[TMP1589]], ptr [[USV]], align 2
43488 // SIMD-ONLY0-NEXT:    [[TMP1590:%.*]] = load i16, ptr [[USX]], align 2
43489 // SIMD-ONLY0-NEXT:    [[CONV2569:%.*]] = zext i16 [[TMP1590]] to i32
43490 // SIMD-ONLY0-NEXT:    [[TMP1591:%.*]] = load i16, ptr [[USE]], align 2
43491 // SIMD-ONLY0-NEXT:    [[CONV2570:%.*]] = zext i16 [[TMP1591]] to i32
43492 // SIMD-ONLY0-NEXT:    [[CMP2571:%.*]] = icmp slt i32 [[CONV2569]], [[CONV2570]]
43493 // SIMD-ONLY0-NEXT:    br i1 [[CMP2571]], label [[IF_THEN2573:%.*]], label [[IF_END2574:%.*]]
43494 // SIMD-ONLY0:       if.then2573:
43495 // SIMD-ONLY0-NEXT:    [[TMP1592:%.*]] = load i16, ptr [[USE]], align 2
43496 // SIMD-ONLY0-NEXT:    store i16 [[TMP1592]], ptr [[USX]], align 2
43497 // SIMD-ONLY0-NEXT:    br label [[IF_END2574]]
43498 // SIMD-ONLY0:       if.end2574:
43499 // SIMD-ONLY0-NEXT:    [[TMP1593:%.*]] = load i16, ptr [[USX]], align 2
43500 // SIMD-ONLY0-NEXT:    store i16 [[TMP1593]], ptr [[USV]], align 2
43501 // SIMD-ONLY0-NEXT:    [[TMP1594:%.*]] = load i16, ptr [[USX]], align 2
43502 // SIMD-ONLY0-NEXT:    [[CONV2575:%.*]] = zext i16 [[TMP1594]] to i32
43503 // SIMD-ONLY0-NEXT:    [[TMP1595:%.*]] = load i16, ptr [[USE]], align 2
43504 // SIMD-ONLY0-NEXT:    [[CONV2576:%.*]] = zext i16 [[TMP1595]] to i32
43505 // SIMD-ONLY0-NEXT:    [[CMP2577:%.*]] = icmp eq i32 [[CONV2575]], [[CONV2576]]
43506 // SIMD-ONLY0-NEXT:    br i1 [[CMP2577]], label [[IF_THEN2579:%.*]], label [[IF_END2580:%.*]]
43507 // SIMD-ONLY0:       if.then2579:
43508 // SIMD-ONLY0-NEXT:    [[TMP1596:%.*]] = load i16, ptr [[USD]], align 2
43509 // SIMD-ONLY0-NEXT:    store i16 [[TMP1596]], ptr [[USX]], align 2
43510 // SIMD-ONLY0-NEXT:    br label [[IF_END2580]]
43511 // SIMD-ONLY0:       if.end2580:
43512 // SIMD-ONLY0-NEXT:    [[TMP1597:%.*]] = load i16, ptr [[USX]], align 2
43513 // SIMD-ONLY0-NEXT:    store i16 [[TMP1597]], ptr [[USV]], align 2
43514 // SIMD-ONLY0-NEXT:    [[TMP1598:%.*]] = load i16, ptr [[USE]], align 2
43515 // SIMD-ONLY0-NEXT:    [[CONV2581:%.*]] = zext i16 [[TMP1598]] to i32
43516 // SIMD-ONLY0-NEXT:    [[TMP1599:%.*]] = load i16, ptr [[USX]], align 2
43517 // SIMD-ONLY0-NEXT:    [[CONV2582:%.*]] = zext i16 [[TMP1599]] to i32
43518 // SIMD-ONLY0-NEXT:    [[CMP2583:%.*]] = icmp eq i32 [[CONV2581]], [[CONV2582]]
43519 // SIMD-ONLY0-NEXT:    br i1 [[CMP2583]], label [[IF_THEN2585:%.*]], label [[IF_END2586:%.*]]
43520 // SIMD-ONLY0:       if.then2585:
43521 // SIMD-ONLY0-NEXT:    [[TMP1600:%.*]] = load i16, ptr [[USD]], align 2
43522 // SIMD-ONLY0-NEXT:    store i16 [[TMP1600]], ptr [[USX]], align 2
43523 // SIMD-ONLY0-NEXT:    br label [[IF_END2586]]
43524 // SIMD-ONLY0:       if.end2586:
43525 // SIMD-ONLY0-NEXT:    [[TMP1601:%.*]] = load i16, ptr [[USX]], align 2
43526 // SIMD-ONLY0-NEXT:    store i16 [[TMP1601]], ptr [[USV]], align 2
43527 // SIMD-ONLY0-NEXT:    [[TMP1602:%.*]] = load i16, ptr [[USX]], align 2
43528 // SIMD-ONLY0-NEXT:    [[CONV2587:%.*]] = zext i16 [[TMP1602]] to i32
43529 // SIMD-ONLY0-NEXT:    [[TMP1603:%.*]] = load i16, ptr [[USE]], align 2
43530 // SIMD-ONLY0-NEXT:    [[CONV2588:%.*]] = zext i16 [[TMP1603]] to i32
43531 // SIMD-ONLY0-NEXT:    [[CMP2589:%.*]] = icmp eq i32 [[CONV2587]], [[CONV2588]]
43532 // SIMD-ONLY0-NEXT:    br i1 [[CMP2589]], label [[IF_THEN2591:%.*]], label [[IF_ELSE2592:%.*]]
43533 // SIMD-ONLY0:       if.then2591:
43534 // SIMD-ONLY0-NEXT:    [[TMP1604:%.*]] = load i16, ptr [[USD]], align 2
43535 // SIMD-ONLY0-NEXT:    store i16 [[TMP1604]], ptr [[USX]], align 2
43536 // SIMD-ONLY0-NEXT:    br label [[IF_END2593:%.*]]
43537 // SIMD-ONLY0:       if.else2592:
43538 // SIMD-ONLY0-NEXT:    [[TMP1605:%.*]] = load i16, ptr [[USX]], align 2
43539 // SIMD-ONLY0-NEXT:    store i16 [[TMP1605]], ptr [[USV]], align 2
43540 // SIMD-ONLY0-NEXT:    br label [[IF_END2593]]
43541 // SIMD-ONLY0:       if.end2593:
43542 // SIMD-ONLY0-NEXT:    [[TMP1606:%.*]] = load i16, ptr [[USE]], align 2
43543 // SIMD-ONLY0-NEXT:    [[CONV2594:%.*]] = zext i16 [[TMP1606]] to i32
43544 // SIMD-ONLY0-NEXT:    [[TMP1607:%.*]] = load i16, ptr [[USX]], align 2
43545 // SIMD-ONLY0-NEXT:    [[CONV2595:%.*]] = zext i16 [[TMP1607]] to i32
43546 // SIMD-ONLY0-NEXT:    [[CMP2596:%.*]] = icmp eq i32 [[CONV2594]], [[CONV2595]]
43547 // SIMD-ONLY0-NEXT:    br i1 [[CMP2596]], label [[IF_THEN2598:%.*]], label [[IF_ELSE2599:%.*]]
43548 // SIMD-ONLY0:       if.then2598:
43549 // SIMD-ONLY0-NEXT:    [[TMP1608:%.*]] = load i16, ptr [[USD]], align 2
43550 // SIMD-ONLY0-NEXT:    store i16 [[TMP1608]], ptr [[USX]], align 2
43551 // SIMD-ONLY0-NEXT:    br label [[IF_END2600:%.*]]
43552 // SIMD-ONLY0:       if.else2599:
43553 // SIMD-ONLY0-NEXT:    [[TMP1609:%.*]] = load i16, ptr [[USX]], align 2
43554 // SIMD-ONLY0-NEXT:    store i16 [[TMP1609]], ptr [[USV]], align 2
43555 // SIMD-ONLY0-NEXT:    br label [[IF_END2600]]
43556 // SIMD-ONLY0:       if.end2600:
43557 // SIMD-ONLY0-NEXT:    [[TMP1610:%.*]] = load i16, ptr [[USX]], align 2
43558 // SIMD-ONLY0-NEXT:    [[CONV2601:%.*]] = zext i16 [[TMP1610]] to i32
43559 // SIMD-ONLY0-NEXT:    [[TMP1611:%.*]] = load i16, ptr [[USE]], align 2
43560 // SIMD-ONLY0-NEXT:    [[CONV2602:%.*]] = zext i16 [[TMP1611]] to i32
43561 // SIMD-ONLY0-NEXT:    [[CMP2603:%.*]] = icmp eq i32 [[CONV2601]], [[CONV2602]]
43562 // SIMD-ONLY0-NEXT:    [[CONV2604:%.*]] = zext i1 [[CMP2603]] to i32
43563 // SIMD-ONLY0-NEXT:    [[CONV2605:%.*]] = trunc i32 [[CONV2604]] to i16
43564 // SIMD-ONLY0-NEXT:    store i16 [[CONV2605]], ptr [[USR]], align 2
43565 // SIMD-ONLY0-NEXT:    [[TMP1612:%.*]] = load i16, ptr [[USR]], align 2
43566 // SIMD-ONLY0-NEXT:    [[TOBOOL2606:%.*]] = icmp ne i16 [[TMP1612]], 0
43567 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2606]], label [[IF_THEN2607:%.*]], label [[IF_END2608:%.*]]
43568 // SIMD-ONLY0:       if.then2607:
43569 // SIMD-ONLY0-NEXT:    [[TMP1613:%.*]] = load i16, ptr [[USD]], align 2
43570 // SIMD-ONLY0-NEXT:    store i16 [[TMP1613]], ptr [[USX]], align 2
43571 // SIMD-ONLY0-NEXT:    br label [[IF_END2608]]
43572 // SIMD-ONLY0:       if.end2608:
43573 // SIMD-ONLY0-NEXT:    [[TMP1614:%.*]] = load i16, ptr [[USE]], align 2
43574 // SIMD-ONLY0-NEXT:    [[CONV2609:%.*]] = zext i16 [[TMP1614]] to i32
43575 // SIMD-ONLY0-NEXT:    [[TMP1615:%.*]] = load i16, ptr [[USX]], align 2
43576 // SIMD-ONLY0-NEXT:    [[CONV2610:%.*]] = zext i16 [[TMP1615]] to i32
43577 // SIMD-ONLY0-NEXT:    [[CMP2611:%.*]] = icmp eq i32 [[CONV2609]], [[CONV2610]]
43578 // SIMD-ONLY0-NEXT:    [[CONV2612:%.*]] = zext i1 [[CMP2611]] to i32
43579 // SIMD-ONLY0-NEXT:    [[CONV2613:%.*]] = trunc i32 [[CONV2612]] to i16
43580 // SIMD-ONLY0-NEXT:    store i16 [[CONV2613]], ptr [[USR]], align 2
43581 // SIMD-ONLY0-NEXT:    [[TMP1616:%.*]] = load i16, ptr [[USR]], align 2
43582 // SIMD-ONLY0-NEXT:    [[TOBOOL2614:%.*]] = icmp ne i16 [[TMP1616]], 0
43583 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2614]], label [[IF_THEN2615:%.*]], label [[IF_END2616:%.*]]
43584 // SIMD-ONLY0:       if.then2615:
43585 // SIMD-ONLY0-NEXT:    [[TMP1617:%.*]] = load i16, ptr [[USD]], align 2
43586 // SIMD-ONLY0-NEXT:    store i16 [[TMP1617]], ptr [[USX]], align 2
43587 // SIMD-ONLY0-NEXT:    br label [[IF_END2616]]
43588 // SIMD-ONLY0:       if.end2616:
43589 // SIMD-ONLY0-NEXT:    [[TMP1618:%.*]] = load i16, ptr [[USX]], align 2
43590 // SIMD-ONLY0-NEXT:    [[CONV2617:%.*]] = zext i16 [[TMP1618]] to i32
43591 // SIMD-ONLY0-NEXT:    [[TMP1619:%.*]] = load i16, ptr [[USE]], align 2
43592 // SIMD-ONLY0-NEXT:    [[CONV2618:%.*]] = zext i16 [[TMP1619]] to i32
43593 // SIMD-ONLY0-NEXT:    [[CMP2619:%.*]] = icmp eq i32 [[CONV2617]], [[CONV2618]]
43594 // SIMD-ONLY0-NEXT:    [[CONV2620:%.*]] = zext i1 [[CMP2619]] to i32
43595 // SIMD-ONLY0-NEXT:    [[CONV2621:%.*]] = trunc i32 [[CONV2620]] to i16
43596 // SIMD-ONLY0-NEXT:    store i16 [[CONV2621]], ptr [[USR]], align 2
43597 // SIMD-ONLY0-NEXT:    [[TMP1620:%.*]] = load i16, ptr [[USR]], align 2
43598 // SIMD-ONLY0-NEXT:    [[TOBOOL2622:%.*]] = icmp ne i16 [[TMP1620]], 0
43599 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2622]], label [[IF_THEN2623:%.*]], label [[IF_ELSE2624:%.*]]
43600 // SIMD-ONLY0:       if.then2623:
43601 // SIMD-ONLY0-NEXT:    [[TMP1621:%.*]] = load i16, ptr [[USD]], align 2
43602 // SIMD-ONLY0-NEXT:    store i16 [[TMP1621]], ptr [[USX]], align 2
43603 // SIMD-ONLY0-NEXT:    br label [[IF_END2625:%.*]]
43604 // SIMD-ONLY0:       if.else2624:
43605 // SIMD-ONLY0-NEXT:    [[TMP1622:%.*]] = load i16, ptr [[USX]], align 2
43606 // SIMD-ONLY0-NEXT:    store i16 [[TMP1622]], ptr [[USV]], align 2
43607 // SIMD-ONLY0-NEXT:    br label [[IF_END2625]]
43608 // SIMD-ONLY0:       if.end2625:
43609 // SIMD-ONLY0-NEXT:    [[TMP1623:%.*]] = load i16, ptr [[USE]], align 2
43610 // SIMD-ONLY0-NEXT:    [[CONV2626:%.*]] = zext i16 [[TMP1623]] to i32
43611 // SIMD-ONLY0-NEXT:    [[TMP1624:%.*]] = load i16, ptr [[USX]], align 2
43612 // SIMD-ONLY0-NEXT:    [[CONV2627:%.*]] = zext i16 [[TMP1624]] to i32
43613 // SIMD-ONLY0-NEXT:    [[CMP2628:%.*]] = icmp eq i32 [[CONV2626]], [[CONV2627]]
43614 // SIMD-ONLY0-NEXT:    [[CONV2629:%.*]] = zext i1 [[CMP2628]] to i32
43615 // SIMD-ONLY0-NEXT:    [[CONV2630:%.*]] = trunc i32 [[CONV2629]] to i16
43616 // SIMD-ONLY0-NEXT:    store i16 [[CONV2630]], ptr [[USR]], align 2
43617 // SIMD-ONLY0-NEXT:    [[TMP1625:%.*]] = load i16, ptr [[USR]], align 2
43618 // SIMD-ONLY0-NEXT:    [[TOBOOL2631:%.*]] = icmp ne i16 [[TMP1625]], 0
43619 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2631]], label [[IF_THEN2632:%.*]], label [[IF_ELSE2633:%.*]]
43620 // SIMD-ONLY0:       if.then2632:
43621 // SIMD-ONLY0-NEXT:    [[TMP1626:%.*]] = load i16, ptr [[USD]], align 2
43622 // SIMD-ONLY0-NEXT:    store i16 [[TMP1626]], ptr [[USX]], align 2
43623 // SIMD-ONLY0-NEXT:    br label [[IF_END2634:%.*]]
43624 // SIMD-ONLY0:       if.else2633:
43625 // SIMD-ONLY0-NEXT:    [[TMP1627:%.*]] = load i16, ptr [[USX]], align 2
43626 // SIMD-ONLY0-NEXT:    store i16 [[TMP1627]], ptr [[USV]], align 2
43627 // SIMD-ONLY0-NEXT:    br label [[IF_END2634]]
43628 // SIMD-ONLY0:       if.end2634:
43629 // SIMD-ONLY0-NEXT:    [[TMP1628:%.*]] = load i16, ptr [[USX]], align 2
43630 // SIMD-ONLY0-NEXT:    store i16 [[TMP1628]], ptr [[USV]], align 2
43631 // SIMD-ONLY0-NEXT:    [[TMP1629:%.*]] = load i16, ptr [[USE]], align 2
43632 // SIMD-ONLY0-NEXT:    [[CONV2635:%.*]] = zext i16 [[TMP1629]] to i32
43633 // SIMD-ONLY0-NEXT:    [[TMP1630:%.*]] = load i16, ptr [[USX]], align 2
43634 // SIMD-ONLY0-NEXT:    [[CONV2636:%.*]] = zext i16 [[TMP1630]] to i32
43635 // SIMD-ONLY0-NEXT:    [[CMP2637:%.*]] = icmp sgt i32 [[CONV2635]], [[CONV2636]]
43636 // SIMD-ONLY0-NEXT:    br i1 [[CMP2637]], label [[IF_THEN2639:%.*]], label [[IF_END2640:%.*]]
43637 // SIMD-ONLY0:       if.then2639:
43638 // SIMD-ONLY0-NEXT:    [[TMP1631:%.*]] = load i16, ptr [[USE]], align 2
43639 // SIMD-ONLY0-NEXT:    store i16 [[TMP1631]], ptr [[USX]], align 2
43640 // SIMD-ONLY0-NEXT:    br label [[IF_END2640]]
43641 // SIMD-ONLY0:       if.end2640:
43642 // SIMD-ONLY0-NEXT:    [[TMP1632:%.*]] = load i16, ptr [[USX]], align 2
43643 // SIMD-ONLY0-NEXT:    store i16 [[TMP1632]], ptr [[USV]], align 2
43644 // SIMD-ONLY0-NEXT:    [[TMP1633:%.*]] = load i16, ptr [[USX]], align 2
43645 // SIMD-ONLY0-NEXT:    [[CONV2641:%.*]] = zext i16 [[TMP1633]] to i32
43646 // SIMD-ONLY0-NEXT:    [[TMP1634:%.*]] = load i16, ptr [[USE]], align 2
43647 // SIMD-ONLY0-NEXT:    [[CONV2642:%.*]] = zext i16 [[TMP1634]] to i32
43648 // SIMD-ONLY0-NEXT:    [[CMP2643:%.*]] = icmp sgt i32 [[CONV2641]], [[CONV2642]]
43649 // SIMD-ONLY0-NEXT:    br i1 [[CMP2643]], label [[IF_THEN2645:%.*]], label [[IF_END2646:%.*]]
43650 // SIMD-ONLY0:       if.then2645:
43651 // SIMD-ONLY0-NEXT:    [[TMP1635:%.*]] = load i16, ptr [[USE]], align 2
43652 // SIMD-ONLY0-NEXT:    store i16 [[TMP1635]], ptr [[USX]], align 2
43653 // SIMD-ONLY0-NEXT:    br label [[IF_END2646]]
43654 // SIMD-ONLY0:       if.end2646:
43655 // SIMD-ONLY0-NEXT:    [[TMP1636:%.*]] = load i16, ptr [[USX]], align 2
43656 // SIMD-ONLY0-NEXT:    store i16 [[TMP1636]], ptr [[USV]], align 2
43657 // SIMD-ONLY0-NEXT:    [[TMP1637:%.*]] = load i16, ptr [[USE]], align 2
43658 // SIMD-ONLY0-NEXT:    [[CONV2647:%.*]] = zext i16 [[TMP1637]] to i32
43659 // SIMD-ONLY0-NEXT:    [[TMP1638:%.*]] = load i16, ptr [[USX]], align 2
43660 // SIMD-ONLY0-NEXT:    [[CONV2648:%.*]] = zext i16 [[TMP1638]] to i32
43661 // SIMD-ONLY0-NEXT:    [[CMP2649:%.*]] = icmp slt i32 [[CONV2647]], [[CONV2648]]
43662 // SIMD-ONLY0-NEXT:    br i1 [[CMP2649]], label [[IF_THEN2651:%.*]], label [[IF_END2652:%.*]]
43663 // SIMD-ONLY0:       if.then2651:
43664 // SIMD-ONLY0-NEXT:    [[TMP1639:%.*]] = load i16, ptr [[USE]], align 2
43665 // SIMD-ONLY0-NEXT:    store i16 [[TMP1639]], ptr [[USX]], align 2
43666 // SIMD-ONLY0-NEXT:    br label [[IF_END2652]]
43667 // SIMD-ONLY0:       if.end2652:
43668 // SIMD-ONLY0-NEXT:    [[TMP1640:%.*]] = load i16, ptr [[USX]], align 2
43669 // SIMD-ONLY0-NEXT:    store i16 [[TMP1640]], ptr [[USV]], align 2
43670 // SIMD-ONLY0-NEXT:    [[TMP1641:%.*]] = load i16, ptr [[USX]], align 2
43671 // SIMD-ONLY0-NEXT:    [[CONV2653:%.*]] = zext i16 [[TMP1641]] to i32
43672 // SIMD-ONLY0-NEXT:    [[TMP1642:%.*]] = load i16, ptr [[USE]], align 2
43673 // SIMD-ONLY0-NEXT:    [[CONV2654:%.*]] = zext i16 [[TMP1642]] to i32
43674 // SIMD-ONLY0-NEXT:    [[CMP2655:%.*]] = icmp slt i32 [[CONV2653]], [[CONV2654]]
43675 // SIMD-ONLY0-NEXT:    br i1 [[CMP2655]], label [[IF_THEN2657:%.*]], label [[IF_END2658:%.*]]
43676 // SIMD-ONLY0:       if.then2657:
43677 // SIMD-ONLY0-NEXT:    [[TMP1643:%.*]] = load i16, ptr [[USE]], align 2
43678 // SIMD-ONLY0-NEXT:    store i16 [[TMP1643]], ptr [[USX]], align 2
43679 // SIMD-ONLY0-NEXT:    br label [[IF_END2658]]
43680 // SIMD-ONLY0:       if.end2658:
43681 // SIMD-ONLY0-NEXT:    [[TMP1644:%.*]] = load i16, ptr [[USX]], align 2
43682 // SIMD-ONLY0-NEXT:    store i16 [[TMP1644]], ptr [[USV]], align 2
43683 // SIMD-ONLY0-NEXT:    [[TMP1645:%.*]] = load i16, ptr [[USX]], align 2
43684 // SIMD-ONLY0-NEXT:    [[CONV2659:%.*]] = zext i16 [[TMP1645]] to i32
43685 // SIMD-ONLY0-NEXT:    [[TMP1646:%.*]] = load i16, ptr [[USE]], align 2
43686 // SIMD-ONLY0-NEXT:    [[CONV2660:%.*]] = zext i16 [[TMP1646]] to i32
43687 // SIMD-ONLY0-NEXT:    [[CMP2661:%.*]] = icmp eq i32 [[CONV2659]], [[CONV2660]]
43688 // SIMD-ONLY0-NEXT:    br i1 [[CMP2661]], label [[IF_THEN2663:%.*]], label [[IF_END2664:%.*]]
43689 // SIMD-ONLY0:       if.then2663:
43690 // SIMD-ONLY0-NEXT:    [[TMP1647:%.*]] = load i16, ptr [[USD]], align 2
43691 // SIMD-ONLY0-NEXT:    store i16 [[TMP1647]], ptr [[USX]], align 2
43692 // SIMD-ONLY0-NEXT:    br label [[IF_END2664]]
43693 // SIMD-ONLY0:       if.end2664:
43694 // SIMD-ONLY0-NEXT:    [[TMP1648:%.*]] = load i16, ptr [[USX]], align 2
43695 // SIMD-ONLY0-NEXT:    store i16 [[TMP1648]], ptr [[USV]], align 2
43696 // SIMD-ONLY0-NEXT:    [[TMP1649:%.*]] = load i16, ptr [[USE]], align 2
43697 // SIMD-ONLY0-NEXT:    [[CONV2665:%.*]] = zext i16 [[TMP1649]] to i32
43698 // SIMD-ONLY0-NEXT:    [[TMP1650:%.*]] = load i16, ptr [[USX]], align 2
43699 // SIMD-ONLY0-NEXT:    [[CONV2666:%.*]] = zext i16 [[TMP1650]] to i32
43700 // SIMD-ONLY0-NEXT:    [[CMP2667:%.*]] = icmp eq i32 [[CONV2665]], [[CONV2666]]
43701 // SIMD-ONLY0-NEXT:    br i1 [[CMP2667]], label [[IF_THEN2669:%.*]], label [[IF_END2670:%.*]]
43702 // SIMD-ONLY0:       if.then2669:
43703 // SIMD-ONLY0-NEXT:    [[TMP1651:%.*]] = load i16, ptr [[USD]], align 2
43704 // SIMD-ONLY0-NEXT:    store i16 [[TMP1651]], ptr [[USX]], align 2
43705 // SIMD-ONLY0-NEXT:    br label [[IF_END2670]]
43706 // SIMD-ONLY0:       if.end2670:
43707 // SIMD-ONLY0-NEXT:    [[TMP1652:%.*]] = load i16, ptr [[USE]], align 2
43708 // SIMD-ONLY0-NEXT:    [[CONV2671:%.*]] = zext i16 [[TMP1652]] to i32
43709 // SIMD-ONLY0-NEXT:    [[TMP1653:%.*]] = load i16, ptr [[USX]], align 2
43710 // SIMD-ONLY0-NEXT:    [[CONV2672:%.*]] = zext i16 [[TMP1653]] to i32
43711 // SIMD-ONLY0-NEXT:    [[CMP2673:%.*]] = icmp sgt i32 [[CONV2671]], [[CONV2672]]
43712 // SIMD-ONLY0-NEXT:    br i1 [[CMP2673]], label [[IF_THEN2675:%.*]], label [[IF_END2676:%.*]]
43713 // SIMD-ONLY0:       if.then2675:
43714 // SIMD-ONLY0-NEXT:    [[TMP1654:%.*]] = load i16, ptr [[USE]], align 2
43715 // SIMD-ONLY0-NEXT:    store i16 [[TMP1654]], ptr [[USX]], align 2
43716 // SIMD-ONLY0-NEXT:    br label [[IF_END2676]]
43717 // SIMD-ONLY0:       if.end2676:
43718 // SIMD-ONLY0-NEXT:    [[TMP1655:%.*]] = load i16, ptr [[USX]], align 2
43719 // SIMD-ONLY0-NEXT:    store i16 [[TMP1655]], ptr [[USV]], align 2
43720 // SIMD-ONLY0-NEXT:    [[TMP1656:%.*]] = load i16, ptr [[USX]], align 2
43721 // SIMD-ONLY0-NEXT:    [[CONV2677:%.*]] = zext i16 [[TMP1656]] to i32
43722 // SIMD-ONLY0-NEXT:    [[TMP1657:%.*]] = load i16, ptr [[USE]], align 2
43723 // SIMD-ONLY0-NEXT:    [[CONV2678:%.*]] = zext i16 [[TMP1657]] to i32
43724 // SIMD-ONLY0-NEXT:    [[CMP2679:%.*]] = icmp sgt i32 [[CONV2677]], [[CONV2678]]
43725 // SIMD-ONLY0-NEXT:    br i1 [[CMP2679]], label [[IF_THEN2681:%.*]], label [[IF_END2682:%.*]]
43726 // SIMD-ONLY0:       if.then2681:
43727 // SIMD-ONLY0-NEXT:    [[TMP1658:%.*]] = load i16, ptr [[USE]], align 2
43728 // SIMD-ONLY0-NEXT:    store i16 [[TMP1658]], ptr [[USX]], align 2
43729 // SIMD-ONLY0-NEXT:    br label [[IF_END2682]]
43730 // SIMD-ONLY0:       if.end2682:
43731 // SIMD-ONLY0-NEXT:    [[TMP1659:%.*]] = load i16, ptr [[USX]], align 2
43732 // SIMD-ONLY0-NEXT:    store i16 [[TMP1659]], ptr [[USV]], align 2
43733 // SIMD-ONLY0-NEXT:    [[TMP1660:%.*]] = load i16, ptr [[USE]], align 2
43734 // SIMD-ONLY0-NEXT:    [[CONV2683:%.*]] = zext i16 [[TMP1660]] to i32
43735 // SIMD-ONLY0-NEXT:    [[TMP1661:%.*]] = load i16, ptr [[USX]], align 2
43736 // SIMD-ONLY0-NEXT:    [[CONV2684:%.*]] = zext i16 [[TMP1661]] to i32
43737 // SIMD-ONLY0-NEXT:    [[CMP2685:%.*]] = icmp slt i32 [[CONV2683]], [[CONV2684]]
43738 // SIMD-ONLY0-NEXT:    br i1 [[CMP2685]], label [[IF_THEN2687:%.*]], label [[IF_END2688:%.*]]
43739 // SIMD-ONLY0:       if.then2687:
43740 // SIMD-ONLY0-NEXT:    [[TMP1662:%.*]] = load i16, ptr [[USE]], align 2
43741 // SIMD-ONLY0-NEXT:    store i16 [[TMP1662]], ptr [[USX]], align 2
43742 // SIMD-ONLY0-NEXT:    br label [[IF_END2688]]
43743 // SIMD-ONLY0:       if.end2688:
43744 // SIMD-ONLY0-NEXT:    [[TMP1663:%.*]] = load i16, ptr [[USX]], align 2
43745 // SIMD-ONLY0-NEXT:    store i16 [[TMP1663]], ptr [[USV]], align 2
43746 // SIMD-ONLY0-NEXT:    [[TMP1664:%.*]] = load i16, ptr [[USX]], align 2
43747 // SIMD-ONLY0-NEXT:    [[CONV2689:%.*]] = zext i16 [[TMP1664]] to i32
43748 // SIMD-ONLY0-NEXT:    [[TMP1665:%.*]] = load i16, ptr [[USE]], align 2
43749 // SIMD-ONLY0-NEXT:    [[CONV2690:%.*]] = zext i16 [[TMP1665]] to i32
43750 // SIMD-ONLY0-NEXT:    [[CMP2691:%.*]] = icmp slt i32 [[CONV2689]], [[CONV2690]]
43751 // SIMD-ONLY0-NEXT:    br i1 [[CMP2691]], label [[IF_THEN2693:%.*]], label [[IF_END2694:%.*]]
43752 // SIMD-ONLY0:       if.then2693:
43753 // SIMD-ONLY0-NEXT:    [[TMP1666:%.*]] = load i16, ptr [[USE]], align 2
43754 // SIMD-ONLY0-NEXT:    store i16 [[TMP1666]], ptr [[USX]], align 2
43755 // SIMD-ONLY0-NEXT:    br label [[IF_END2694]]
43756 // SIMD-ONLY0:       if.end2694:
43757 // SIMD-ONLY0-NEXT:    [[TMP1667:%.*]] = load i16, ptr [[USX]], align 2
43758 // SIMD-ONLY0-NEXT:    store i16 [[TMP1667]], ptr [[USV]], align 2
43759 // SIMD-ONLY0-NEXT:    [[TMP1668:%.*]] = load i16, ptr [[USX]], align 2
43760 // SIMD-ONLY0-NEXT:    [[CONV2695:%.*]] = zext i16 [[TMP1668]] to i32
43761 // SIMD-ONLY0-NEXT:    [[TMP1669:%.*]] = load i16, ptr [[USE]], align 2
43762 // SIMD-ONLY0-NEXT:    [[CONV2696:%.*]] = zext i16 [[TMP1669]] to i32
43763 // SIMD-ONLY0-NEXT:    [[CMP2697:%.*]] = icmp eq i32 [[CONV2695]], [[CONV2696]]
43764 // SIMD-ONLY0-NEXT:    br i1 [[CMP2697]], label [[IF_THEN2699:%.*]], label [[IF_END2700:%.*]]
43765 // SIMD-ONLY0:       if.then2699:
43766 // SIMD-ONLY0-NEXT:    [[TMP1670:%.*]] = load i16, ptr [[USD]], align 2
43767 // SIMD-ONLY0-NEXT:    store i16 [[TMP1670]], ptr [[USX]], align 2
43768 // SIMD-ONLY0-NEXT:    br label [[IF_END2700]]
43769 // SIMD-ONLY0:       if.end2700:
43770 // SIMD-ONLY0-NEXT:    [[TMP1671:%.*]] = load i16, ptr [[USX]], align 2
43771 // SIMD-ONLY0-NEXT:    store i16 [[TMP1671]], ptr [[USV]], align 2
43772 // SIMD-ONLY0-NEXT:    [[TMP1672:%.*]] = load i16, ptr [[USE]], align 2
43773 // SIMD-ONLY0-NEXT:    [[CONV2701:%.*]] = zext i16 [[TMP1672]] to i32
43774 // SIMD-ONLY0-NEXT:    [[TMP1673:%.*]] = load i16, ptr [[USX]], align 2
43775 // SIMD-ONLY0-NEXT:    [[CONV2702:%.*]] = zext i16 [[TMP1673]] to i32
43776 // SIMD-ONLY0-NEXT:    [[CMP2703:%.*]] = icmp eq i32 [[CONV2701]], [[CONV2702]]
43777 // SIMD-ONLY0-NEXT:    br i1 [[CMP2703]], label [[IF_THEN2705:%.*]], label [[IF_END2706:%.*]]
43778 // SIMD-ONLY0:       if.then2705:
43779 // SIMD-ONLY0-NEXT:    [[TMP1674:%.*]] = load i16, ptr [[USD]], align 2
43780 // SIMD-ONLY0-NEXT:    store i16 [[TMP1674]], ptr [[USX]], align 2
43781 // SIMD-ONLY0-NEXT:    br label [[IF_END2706]]
43782 // SIMD-ONLY0:       if.end2706:
43783 // SIMD-ONLY0-NEXT:    [[TMP1675:%.*]] = load i16, ptr [[USX]], align 2
43784 // SIMD-ONLY0-NEXT:    store i16 [[TMP1675]], ptr [[USV]], align 2
43785 // SIMD-ONLY0-NEXT:    [[TMP1676:%.*]] = load i16, ptr [[USX]], align 2
43786 // SIMD-ONLY0-NEXT:    [[CONV2707:%.*]] = zext i16 [[TMP1676]] to i32
43787 // SIMD-ONLY0-NEXT:    [[TMP1677:%.*]] = load i16, ptr [[USE]], align 2
43788 // SIMD-ONLY0-NEXT:    [[CONV2708:%.*]] = zext i16 [[TMP1677]] to i32
43789 // SIMD-ONLY0-NEXT:    [[CMP2709:%.*]] = icmp eq i32 [[CONV2707]], [[CONV2708]]
43790 // SIMD-ONLY0-NEXT:    br i1 [[CMP2709]], label [[IF_THEN2711:%.*]], label [[IF_ELSE2712:%.*]]
43791 // SIMD-ONLY0:       if.then2711:
43792 // SIMD-ONLY0-NEXT:    [[TMP1678:%.*]] = load i16, ptr [[USD]], align 2
43793 // SIMD-ONLY0-NEXT:    store i16 [[TMP1678]], ptr [[USX]], align 2
43794 // SIMD-ONLY0-NEXT:    br label [[IF_END2713:%.*]]
43795 // SIMD-ONLY0:       if.else2712:
43796 // SIMD-ONLY0-NEXT:    [[TMP1679:%.*]] = load i16, ptr [[USX]], align 2
43797 // SIMD-ONLY0-NEXT:    store i16 [[TMP1679]], ptr [[USV]], align 2
43798 // SIMD-ONLY0-NEXT:    br label [[IF_END2713]]
43799 // SIMD-ONLY0:       if.end2713:
43800 // SIMD-ONLY0-NEXT:    [[TMP1680:%.*]] = load i16, ptr [[USE]], align 2
43801 // SIMD-ONLY0-NEXT:    [[CONV2714:%.*]] = zext i16 [[TMP1680]] to i32
43802 // SIMD-ONLY0-NEXT:    [[TMP1681:%.*]] = load i16, ptr [[USX]], align 2
43803 // SIMD-ONLY0-NEXT:    [[CONV2715:%.*]] = zext i16 [[TMP1681]] to i32
43804 // SIMD-ONLY0-NEXT:    [[CMP2716:%.*]] = icmp eq i32 [[CONV2714]], [[CONV2715]]
43805 // SIMD-ONLY0-NEXT:    br i1 [[CMP2716]], label [[IF_THEN2718:%.*]], label [[IF_ELSE2719:%.*]]
43806 // SIMD-ONLY0:       if.then2718:
43807 // SIMD-ONLY0-NEXT:    [[TMP1682:%.*]] = load i16, ptr [[USD]], align 2
43808 // SIMD-ONLY0-NEXT:    store i16 [[TMP1682]], ptr [[USX]], align 2
43809 // SIMD-ONLY0-NEXT:    br label [[IF_END2720:%.*]]
43810 // SIMD-ONLY0:       if.else2719:
43811 // SIMD-ONLY0-NEXT:    [[TMP1683:%.*]] = load i16, ptr [[USX]], align 2
43812 // SIMD-ONLY0-NEXT:    store i16 [[TMP1683]], ptr [[USV]], align 2
43813 // SIMD-ONLY0-NEXT:    br label [[IF_END2720]]
43814 // SIMD-ONLY0:       if.end2720:
43815 // SIMD-ONLY0-NEXT:    [[TMP1684:%.*]] = load i16, ptr [[USX]], align 2
43816 // SIMD-ONLY0-NEXT:    [[CONV2721:%.*]] = zext i16 [[TMP1684]] to i32
43817 // SIMD-ONLY0-NEXT:    [[TMP1685:%.*]] = load i16, ptr [[USE]], align 2
43818 // SIMD-ONLY0-NEXT:    [[CONV2722:%.*]] = zext i16 [[TMP1685]] to i32
43819 // SIMD-ONLY0-NEXT:    [[CMP2723:%.*]] = icmp eq i32 [[CONV2721]], [[CONV2722]]
43820 // SIMD-ONLY0-NEXT:    [[CONV2724:%.*]] = zext i1 [[CMP2723]] to i32
43821 // SIMD-ONLY0-NEXT:    [[CONV2725:%.*]] = trunc i32 [[CONV2724]] to i16
43822 // SIMD-ONLY0-NEXT:    store i16 [[CONV2725]], ptr [[USR]], align 2
43823 // SIMD-ONLY0-NEXT:    [[TMP1686:%.*]] = load i16, ptr [[USR]], align 2
43824 // SIMD-ONLY0-NEXT:    [[TOBOOL2726:%.*]] = icmp ne i16 [[TMP1686]], 0
43825 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2726]], label [[IF_THEN2727:%.*]], label [[IF_END2728:%.*]]
43826 // SIMD-ONLY0:       if.then2727:
43827 // SIMD-ONLY0-NEXT:    [[TMP1687:%.*]] = load i16, ptr [[USD]], align 2
43828 // SIMD-ONLY0-NEXT:    store i16 [[TMP1687]], ptr [[USX]], align 2
43829 // SIMD-ONLY0-NEXT:    br label [[IF_END2728]]
43830 // SIMD-ONLY0:       if.end2728:
43831 // SIMD-ONLY0-NEXT:    [[TMP1688:%.*]] = load i16, ptr [[USE]], align 2
43832 // SIMD-ONLY0-NEXT:    [[CONV2729:%.*]] = zext i16 [[TMP1688]] to i32
43833 // SIMD-ONLY0-NEXT:    [[TMP1689:%.*]] = load i16, ptr [[USX]], align 2
43834 // SIMD-ONLY0-NEXT:    [[CONV2730:%.*]] = zext i16 [[TMP1689]] to i32
43835 // SIMD-ONLY0-NEXT:    [[CMP2731:%.*]] = icmp eq i32 [[CONV2729]], [[CONV2730]]
43836 // SIMD-ONLY0-NEXT:    [[CONV2732:%.*]] = zext i1 [[CMP2731]] to i32
43837 // SIMD-ONLY0-NEXT:    [[CONV2733:%.*]] = trunc i32 [[CONV2732]] to i16
43838 // SIMD-ONLY0-NEXT:    store i16 [[CONV2733]], ptr [[USR]], align 2
43839 // SIMD-ONLY0-NEXT:    [[TMP1690:%.*]] = load i16, ptr [[USR]], align 2
43840 // SIMD-ONLY0-NEXT:    [[TOBOOL2734:%.*]] = icmp ne i16 [[TMP1690]], 0
43841 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2734]], label [[IF_THEN2735:%.*]], label [[IF_END2736:%.*]]
43842 // SIMD-ONLY0:       if.then2735:
43843 // SIMD-ONLY0-NEXT:    [[TMP1691:%.*]] = load i16, ptr [[USD]], align 2
43844 // SIMD-ONLY0-NEXT:    store i16 [[TMP1691]], ptr [[USX]], align 2
43845 // SIMD-ONLY0-NEXT:    br label [[IF_END2736]]
43846 // SIMD-ONLY0:       if.end2736:
43847 // SIMD-ONLY0-NEXT:    [[TMP1692:%.*]] = load i16, ptr [[USX]], align 2
43848 // SIMD-ONLY0-NEXT:    [[CONV2737:%.*]] = zext i16 [[TMP1692]] to i32
43849 // SIMD-ONLY0-NEXT:    [[TMP1693:%.*]] = load i16, ptr [[USE]], align 2
43850 // SIMD-ONLY0-NEXT:    [[CONV2738:%.*]] = zext i16 [[TMP1693]] to i32
43851 // SIMD-ONLY0-NEXT:    [[CMP2739:%.*]] = icmp eq i32 [[CONV2737]], [[CONV2738]]
43852 // SIMD-ONLY0-NEXT:    [[CONV2740:%.*]] = zext i1 [[CMP2739]] to i32
43853 // SIMD-ONLY0-NEXT:    [[CONV2741:%.*]] = trunc i32 [[CONV2740]] to i16
43854 // SIMD-ONLY0-NEXT:    store i16 [[CONV2741]], ptr [[USR]], align 2
43855 // SIMD-ONLY0-NEXT:    [[TMP1694:%.*]] = load i16, ptr [[USR]], align 2
43856 // SIMD-ONLY0-NEXT:    [[TOBOOL2742:%.*]] = icmp ne i16 [[TMP1694]], 0
43857 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2742]], label [[IF_THEN2743:%.*]], label [[IF_ELSE2744:%.*]]
43858 // SIMD-ONLY0:       if.then2743:
43859 // SIMD-ONLY0-NEXT:    [[TMP1695:%.*]] = load i16, ptr [[USD]], align 2
43860 // SIMD-ONLY0-NEXT:    store i16 [[TMP1695]], ptr [[USX]], align 2
43861 // SIMD-ONLY0-NEXT:    br label [[IF_END2745:%.*]]
43862 // SIMD-ONLY0:       if.else2744:
43863 // SIMD-ONLY0-NEXT:    [[TMP1696:%.*]] = load i16, ptr [[USX]], align 2
43864 // SIMD-ONLY0-NEXT:    store i16 [[TMP1696]], ptr [[USV]], align 2
43865 // SIMD-ONLY0-NEXT:    br label [[IF_END2745]]
43866 // SIMD-ONLY0:       if.end2745:
43867 // SIMD-ONLY0-NEXT:    [[TMP1697:%.*]] = load i16, ptr [[USE]], align 2
43868 // SIMD-ONLY0-NEXT:    [[CONV2746:%.*]] = zext i16 [[TMP1697]] to i32
43869 // SIMD-ONLY0-NEXT:    [[TMP1698:%.*]] = load i16, ptr [[USX]], align 2
43870 // SIMD-ONLY0-NEXT:    [[CONV2747:%.*]] = zext i16 [[TMP1698]] to i32
43871 // SIMD-ONLY0-NEXT:    [[CMP2748:%.*]] = icmp eq i32 [[CONV2746]], [[CONV2747]]
43872 // SIMD-ONLY0-NEXT:    [[CONV2749:%.*]] = zext i1 [[CMP2748]] to i32
43873 // SIMD-ONLY0-NEXT:    [[CONV2750:%.*]] = trunc i32 [[CONV2749]] to i16
43874 // SIMD-ONLY0-NEXT:    store i16 [[CONV2750]], ptr [[USR]], align 2
43875 // SIMD-ONLY0-NEXT:    [[TMP1699:%.*]] = load i16, ptr [[USR]], align 2
43876 // SIMD-ONLY0-NEXT:    [[TOBOOL2751:%.*]] = icmp ne i16 [[TMP1699]], 0
43877 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2751]], label [[IF_THEN2752:%.*]], label [[IF_ELSE2753:%.*]]
43878 // SIMD-ONLY0:       if.then2752:
43879 // SIMD-ONLY0-NEXT:    [[TMP1700:%.*]] = load i16, ptr [[USD]], align 2
43880 // SIMD-ONLY0-NEXT:    store i16 [[TMP1700]], ptr [[USX]], align 2
43881 // SIMD-ONLY0-NEXT:    br label [[IF_END2754:%.*]]
43882 // SIMD-ONLY0:       if.else2753:
43883 // SIMD-ONLY0-NEXT:    [[TMP1701:%.*]] = load i16, ptr [[USX]], align 2
43884 // SIMD-ONLY0-NEXT:    store i16 [[TMP1701]], ptr [[USV]], align 2
43885 // SIMD-ONLY0-NEXT:    br label [[IF_END2754]]
43886 // SIMD-ONLY0:       if.end2754:
43887 // SIMD-ONLY0-NEXT:    [[TMP1702:%.*]] = load i16, ptr [[USX]], align 2
43888 // SIMD-ONLY0-NEXT:    store i16 [[TMP1702]], ptr [[USV]], align 2
43889 // SIMD-ONLY0-NEXT:    [[TMP1703:%.*]] = load i16, ptr [[USE]], align 2
43890 // SIMD-ONLY0-NEXT:    [[CONV2755:%.*]] = zext i16 [[TMP1703]] to i32
43891 // SIMD-ONLY0-NEXT:    [[TMP1704:%.*]] = load i16, ptr [[USX]], align 2
43892 // SIMD-ONLY0-NEXT:    [[CONV2756:%.*]] = zext i16 [[TMP1704]] to i32
43893 // SIMD-ONLY0-NEXT:    [[CMP2757:%.*]] = icmp sgt i32 [[CONV2755]], [[CONV2756]]
43894 // SIMD-ONLY0-NEXT:    br i1 [[CMP2757]], label [[IF_THEN2759:%.*]], label [[IF_END2760:%.*]]
43895 // SIMD-ONLY0:       if.then2759:
43896 // SIMD-ONLY0-NEXT:    [[TMP1705:%.*]] = load i16, ptr [[USE]], align 2
43897 // SIMD-ONLY0-NEXT:    store i16 [[TMP1705]], ptr [[USX]], align 2
43898 // SIMD-ONLY0-NEXT:    br label [[IF_END2760]]
43899 // SIMD-ONLY0:       if.end2760:
43900 // SIMD-ONLY0-NEXT:    [[TMP1706:%.*]] = load i16, ptr [[USX]], align 2
43901 // SIMD-ONLY0-NEXT:    store i16 [[TMP1706]], ptr [[USV]], align 2
43902 // SIMD-ONLY0-NEXT:    [[TMP1707:%.*]] = load i16, ptr [[USX]], align 2
43903 // SIMD-ONLY0-NEXT:    [[CONV2761:%.*]] = zext i16 [[TMP1707]] to i32
43904 // SIMD-ONLY0-NEXT:    [[TMP1708:%.*]] = load i16, ptr [[USE]], align 2
43905 // SIMD-ONLY0-NEXT:    [[CONV2762:%.*]] = zext i16 [[TMP1708]] to i32
43906 // SIMD-ONLY0-NEXT:    [[CMP2763:%.*]] = icmp sgt i32 [[CONV2761]], [[CONV2762]]
43907 // SIMD-ONLY0-NEXT:    br i1 [[CMP2763]], label [[IF_THEN2765:%.*]], label [[IF_END2766:%.*]]
43908 // SIMD-ONLY0:       if.then2765:
43909 // SIMD-ONLY0-NEXT:    [[TMP1709:%.*]] = load i16, ptr [[USE]], align 2
43910 // SIMD-ONLY0-NEXT:    store i16 [[TMP1709]], ptr [[USX]], align 2
43911 // SIMD-ONLY0-NEXT:    br label [[IF_END2766]]
43912 // SIMD-ONLY0:       if.end2766:
43913 // SIMD-ONLY0-NEXT:    [[TMP1710:%.*]] = load i16, ptr [[USX]], align 2
43914 // SIMD-ONLY0-NEXT:    store i16 [[TMP1710]], ptr [[USV]], align 2
43915 // SIMD-ONLY0-NEXT:    [[TMP1711:%.*]] = load i16, ptr [[USE]], align 2
43916 // SIMD-ONLY0-NEXT:    [[CONV2767:%.*]] = zext i16 [[TMP1711]] to i32
43917 // SIMD-ONLY0-NEXT:    [[TMP1712:%.*]] = load i16, ptr [[USX]], align 2
43918 // SIMD-ONLY0-NEXT:    [[CONV2768:%.*]] = zext i16 [[TMP1712]] to i32
43919 // SIMD-ONLY0-NEXT:    [[CMP2769:%.*]] = icmp slt i32 [[CONV2767]], [[CONV2768]]
43920 // SIMD-ONLY0-NEXT:    br i1 [[CMP2769]], label [[IF_THEN2771:%.*]], label [[IF_END2772:%.*]]
43921 // SIMD-ONLY0:       if.then2771:
43922 // SIMD-ONLY0-NEXT:    [[TMP1713:%.*]] = load i16, ptr [[USE]], align 2
43923 // SIMD-ONLY0-NEXT:    store i16 [[TMP1713]], ptr [[USX]], align 2
43924 // SIMD-ONLY0-NEXT:    br label [[IF_END2772]]
43925 // SIMD-ONLY0:       if.end2772:
43926 // SIMD-ONLY0-NEXT:    [[TMP1714:%.*]] = load i16, ptr [[USX]], align 2
43927 // SIMD-ONLY0-NEXT:    store i16 [[TMP1714]], ptr [[USV]], align 2
43928 // SIMD-ONLY0-NEXT:    [[TMP1715:%.*]] = load i16, ptr [[USX]], align 2
43929 // SIMD-ONLY0-NEXT:    [[CONV2773:%.*]] = zext i16 [[TMP1715]] to i32
43930 // SIMD-ONLY0-NEXT:    [[TMP1716:%.*]] = load i16, ptr [[USE]], align 2
43931 // SIMD-ONLY0-NEXT:    [[CONV2774:%.*]] = zext i16 [[TMP1716]] to i32
43932 // SIMD-ONLY0-NEXT:    [[CMP2775:%.*]] = icmp slt i32 [[CONV2773]], [[CONV2774]]
43933 // SIMD-ONLY0-NEXT:    br i1 [[CMP2775]], label [[IF_THEN2777:%.*]], label [[IF_END2778:%.*]]
43934 // SIMD-ONLY0:       if.then2777:
43935 // SIMD-ONLY0-NEXT:    [[TMP1717:%.*]] = load i16, ptr [[USE]], align 2
43936 // SIMD-ONLY0-NEXT:    store i16 [[TMP1717]], ptr [[USX]], align 2
43937 // SIMD-ONLY0-NEXT:    br label [[IF_END2778]]
43938 // SIMD-ONLY0:       if.end2778:
43939 // SIMD-ONLY0-NEXT:    [[TMP1718:%.*]] = load i16, ptr [[USX]], align 2
43940 // SIMD-ONLY0-NEXT:    store i16 [[TMP1718]], ptr [[USV]], align 2
43941 // SIMD-ONLY0-NEXT:    [[TMP1719:%.*]] = load i16, ptr [[USX]], align 2
43942 // SIMD-ONLY0-NEXT:    [[CONV2779:%.*]] = zext i16 [[TMP1719]] to i32
43943 // SIMD-ONLY0-NEXT:    [[TMP1720:%.*]] = load i16, ptr [[USE]], align 2
43944 // SIMD-ONLY0-NEXT:    [[CONV2780:%.*]] = zext i16 [[TMP1720]] to i32
43945 // SIMD-ONLY0-NEXT:    [[CMP2781:%.*]] = icmp eq i32 [[CONV2779]], [[CONV2780]]
43946 // SIMD-ONLY0-NEXT:    br i1 [[CMP2781]], label [[IF_THEN2783:%.*]], label [[IF_END2784:%.*]]
43947 // SIMD-ONLY0:       if.then2783:
43948 // SIMD-ONLY0-NEXT:    [[TMP1721:%.*]] = load i16, ptr [[USD]], align 2
43949 // SIMD-ONLY0-NEXT:    store i16 [[TMP1721]], ptr [[USX]], align 2
43950 // SIMD-ONLY0-NEXT:    br label [[IF_END2784]]
43951 // SIMD-ONLY0:       if.end2784:
43952 // SIMD-ONLY0-NEXT:    [[TMP1722:%.*]] = load i16, ptr [[USX]], align 2
43953 // SIMD-ONLY0-NEXT:    store i16 [[TMP1722]], ptr [[USV]], align 2
43954 // SIMD-ONLY0-NEXT:    [[TMP1723:%.*]] = load i16, ptr [[USE]], align 2
43955 // SIMD-ONLY0-NEXT:    [[CONV2785:%.*]] = zext i16 [[TMP1723]] to i32
43956 // SIMD-ONLY0-NEXT:    [[TMP1724:%.*]] = load i16, ptr [[USX]], align 2
43957 // SIMD-ONLY0-NEXT:    [[CONV2786:%.*]] = zext i16 [[TMP1724]] to i32
43958 // SIMD-ONLY0-NEXT:    [[CMP2787:%.*]] = icmp eq i32 [[CONV2785]], [[CONV2786]]
43959 // SIMD-ONLY0-NEXT:    br i1 [[CMP2787]], label [[IF_THEN2789:%.*]], label [[IF_END2790:%.*]]
43960 // SIMD-ONLY0:       if.then2789:
43961 // SIMD-ONLY0-NEXT:    [[TMP1725:%.*]] = load i16, ptr [[USD]], align 2
43962 // SIMD-ONLY0-NEXT:    store i16 [[TMP1725]], ptr [[USX]], align 2
43963 // SIMD-ONLY0-NEXT:    br label [[IF_END2790]]
43964 // SIMD-ONLY0:       if.end2790:
43965 // SIMD-ONLY0-NEXT:    [[TMP1726:%.*]] = load i16, ptr [[USE]], align 2
43966 // SIMD-ONLY0-NEXT:    [[CONV2791:%.*]] = zext i16 [[TMP1726]] to i32
43967 // SIMD-ONLY0-NEXT:    [[TMP1727:%.*]] = load i16, ptr [[USX]], align 2
43968 // SIMD-ONLY0-NEXT:    [[CONV2792:%.*]] = zext i16 [[TMP1727]] to i32
43969 // SIMD-ONLY0-NEXT:    [[CMP2793:%.*]] = icmp sgt i32 [[CONV2791]], [[CONV2792]]
43970 // SIMD-ONLY0-NEXT:    br i1 [[CMP2793]], label [[IF_THEN2795:%.*]], label [[IF_END2796:%.*]]
43971 // SIMD-ONLY0:       if.then2795:
43972 // SIMD-ONLY0-NEXT:    [[TMP1728:%.*]] = load i16, ptr [[USE]], align 2
43973 // SIMD-ONLY0-NEXT:    store i16 [[TMP1728]], ptr [[USX]], align 2
43974 // SIMD-ONLY0-NEXT:    br label [[IF_END2796]]
43975 // SIMD-ONLY0:       if.end2796:
43976 // SIMD-ONLY0-NEXT:    [[TMP1729:%.*]] = load i16, ptr [[USX]], align 2
43977 // SIMD-ONLY0-NEXT:    store i16 [[TMP1729]], ptr [[USV]], align 2
43978 // SIMD-ONLY0-NEXT:    [[TMP1730:%.*]] = load i16, ptr [[USX]], align 2
43979 // SIMD-ONLY0-NEXT:    [[CONV2797:%.*]] = zext i16 [[TMP1730]] to i32
43980 // SIMD-ONLY0-NEXT:    [[TMP1731:%.*]] = load i16, ptr [[USE]], align 2
43981 // SIMD-ONLY0-NEXT:    [[CONV2798:%.*]] = zext i16 [[TMP1731]] to i32
43982 // SIMD-ONLY0-NEXT:    [[CMP2799:%.*]] = icmp sgt i32 [[CONV2797]], [[CONV2798]]
43983 // SIMD-ONLY0-NEXT:    br i1 [[CMP2799]], label [[IF_THEN2801:%.*]], label [[IF_END2802:%.*]]
43984 // SIMD-ONLY0:       if.then2801:
43985 // SIMD-ONLY0-NEXT:    [[TMP1732:%.*]] = load i16, ptr [[USE]], align 2
43986 // SIMD-ONLY0-NEXT:    store i16 [[TMP1732]], ptr [[USX]], align 2
43987 // SIMD-ONLY0-NEXT:    br label [[IF_END2802]]
43988 // SIMD-ONLY0:       if.end2802:
43989 // SIMD-ONLY0-NEXT:    [[TMP1733:%.*]] = load i16, ptr [[USX]], align 2
43990 // SIMD-ONLY0-NEXT:    store i16 [[TMP1733]], ptr [[USV]], align 2
43991 // SIMD-ONLY0-NEXT:    [[TMP1734:%.*]] = load i16, ptr [[USE]], align 2
43992 // SIMD-ONLY0-NEXT:    [[CONV2803:%.*]] = zext i16 [[TMP1734]] to i32
43993 // SIMD-ONLY0-NEXT:    [[TMP1735:%.*]] = load i16, ptr [[USX]], align 2
43994 // SIMD-ONLY0-NEXT:    [[CONV2804:%.*]] = zext i16 [[TMP1735]] to i32
43995 // SIMD-ONLY0-NEXT:    [[CMP2805:%.*]] = icmp slt i32 [[CONV2803]], [[CONV2804]]
43996 // SIMD-ONLY0-NEXT:    br i1 [[CMP2805]], label [[IF_THEN2807:%.*]], label [[IF_END2808:%.*]]
43997 // SIMD-ONLY0:       if.then2807:
43998 // SIMD-ONLY0-NEXT:    [[TMP1736:%.*]] = load i16, ptr [[USE]], align 2
43999 // SIMD-ONLY0-NEXT:    store i16 [[TMP1736]], ptr [[USX]], align 2
44000 // SIMD-ONLY0-NEXT:    br label [[IF_END2808]]
44001 // SIMD-ONLY0:       if.end2808:
44002 // SIMD-ONLY0-NEXT:    [[TMP1737:%.*]] = load i16, ptr [[USX]], align 2
44003 // SIMD-ONLY0-NEXT:    store i16 [[TMP1737]], ptr [[USV]], align 2
44004 // SIMD-ONLY0-NEXT:    [[TMP1738:%.*]] = load i16, ptr [[USX]], align 2
44005 // SIMD-ONLY0-NEXT:    [[CONV2809:%.*]] = zext i16 [[TMP1738]] to i32
44006 // SIMD-ONLY0-NEXT:    [[TMP1739:%.*]] = load i16, ptr [[USE]], align 2
44007 // SIMD-ONLY0-NEXT:    [[CONV2810:%.*]] = zext i16 [[TMP1739]] to i32
44008 // SIMD-ONLY0-NEXT:    [[CMP2811:%.*]] = icmp slt i32 [[CONV2809]], [[CONV2810]]
44009 // SIMD-ONLY0-NEXT:    br i1 [[CMP2811]], label [[IF_THEN2813:%.*]], label [[IF_END2814:%.*]]
44010 // SIMD-ONLY0:       if.then2813:
44011 // SIMD-ONLY0-NEXT:    [[TMP1740:%.*]] = load i16, ptr [[USE]], align 2
44012 // SIMD-ONLY0-NEXT:    store i16 [[TMP1740]], ptr [[USX]], align 2
44013 // SIMD-ONLY0-NEXT:    br label [[IF_END2814]]
44014 // SIMD-ONLY0:       if.end2814:
44015 // SIMD-ONLY0-NEXT:    [[TMP1741:%.*]] = load i16, ptr [[USX]], align 2
44016 // SIMD-ONLY0-NEXT:    store i16 [[TMP1741]], ptr [[USV]], align 2
44017 // SIMD-ONLY0-NEXT:    [[TMP1742:%.*]] = load i16, ptr [[USX]], align 2
44018 // SIMD-ONLY0-NEXT:    [[CONV2815:%.*]] = zext i16 [[TMP1742]] to i32
44019 // SIMD-ONLY0-NEXT:    [[TMP1743:%.*]] = load i16, ptr [[USE]], align 2
44020 // SIMD-ONLY0-NEXT:    [[CONV2816:%.*]] = zext i16 [[TMP1743]] to i32
44021 // SIMD-ONLY0-NEXT:    [[CMP2817:%.*]] = icmp eq i32 [[CONV2815]], [[CONV2816]]
44022 // SIMD-ONLY0-NEXT:    br i1 [[CMP2817]], label [[IF_THEN2819:%.*]], label [[IF_END2820:%.*]]
44023 // SIMD-ONLY0:       if.then2819:
44024 // SIMD-ONLY0-NEXT:    [[TMP1744:%.*]] = load i16, ptr [[USD]], align 2
44025 // SIMD-ONLY0-NEXT:    store i16 [[TMP1744]], ptr [[USX]], align 2
44026 // SIMD-ONLY0-NEXT:    br label [[IF_END2820]]
44027 // SIMD-ONLY0:       if.end2820:
44028 // SIMD-ONLY0-NEXT:    [[TMP1745:%.*]] = load i16, ptr [[USX]], align 2
44029 // SIMD-ONLY0-NEXT:    store i16 [[TMP1745]], ptr [[USV]], align 2
44030 // SIMD-ONLY0-NEXT:    [[TMP1746:%.*]] = load i16, ptr [[USE]], align 2
44031 // SIMD-ONLY0-NEXT:    [[CONV2821:%.*]] = zext i16 [[TMP1746]] to i32
44032 // SIMD-ONLY0-NEXT:    [[TMP1747:%.*]] = load i16, ptr [[USX]], align 2
44033 // SIMD-ONLY0-NEXT:    [[CONV2822:%.*]] = zext i16 [[TMP1747]] to i32
44034 // SIMD-ONLY0-NEXT:    [[CMP2823:%.*]] = icmp eq i32 [[CONV2821]], [[CONV2822]]
44035 // SIMD-ONLY0-NEXT:    br i1 [[CMP2823]], label [[IF_THEN2825:%.*]], label [[IF_END2826:%.*]]
44036 // SIMD-ONLY0:       if.then2825:
44037 // SIMD-ONLY0-NEXT:    [[TMP1748:%.*]] = load i16, ptr [[USD]], align 2
44038 // SIMD-ONLY0-NEXT:    store i16 [[TMP1748]], ptr [[USX]], align 2
44039 // SIMD-ONLY0-NEXT:    br label [[IF_END2826]]
44040 // SIMD-ONLY0:       if.end2826:
44041 // SIMD-ONLY0-NEXT:    [[TMP1749:%.*]] = load i16, ptr [[USX]], align 2
44042 // SIMD-ONLY0-NEXT:    store i16 [[TMP1749]], ptr [[USV]], align 2
44043 // SIMD-ONLY0-NEXT:    [[TMP1750:%.*]] = load i16, ptr [[USX]], align 2
44044 // SIMD-ONLY0-NEXT:    [[CONV2827:%.*]] = zext i16 [[TMP1750]] to i32
44045 // SIMD-ONLY0-NEXT:    [[TMP1751:%.*]] = load i16, ptr [[USE]], align 2
44046 // SIMD-ONLY0-NEXT:    [[CONV2828:%.*]] = zext i16 [[TMP1751]] to i32
44047 // SIMD-ONLY0-NEXT:    [[CMP2829:%.*]] = icmp eq i32 [[CONV2827]], [[CONV2828]]
44048 // SIMD-ONLY0-NEXT:    br i1 [[CMP2829]], label [[IF_THEN2831:%.*]], label [[IF_ELSE2832:%.*]]
44049 // SIMD-ONLY0:       if.then2831:
44050 // SIMD-ONLY0-NEXT:    [[TMP1752:%.*]] = load i16, ptr [[USD]], align 2
44051 // SIMD-ONLY0-NEXT:    store i16 [[TMP1752]], ptr [[USX]], align 2
44052 // SIMD-ONLY0-NEXT:    br label [[IF_END2833:%.*]]
44053 // SIMD-ONLY0:       if.else2832:
44054 // SIMD-ONLY0-NEXT:    [[TMP1753:%.*]] = load i16, ptr [[USX]], align 2
44055 // SIMD-ONLY0-NEXT:    store i16 [[TMP1753]], ptr [[USV]], align 2
44056 // SIMD-ONLY0-NEXT:    br label [[IF_END2833]]
44057 // SIMD-ONLY0:       if.end2833:
44058 // SIMD-ONLY0-NEXT:    [[TMP1754:%.*]] = load i16, ptr [[USE]], align 2
44059 // SIMD-ONLY0-NEXT:    [[CONV2834:%.*]] = zext i16 [[TMP1754]] to i32
44060 // SIMD-ONLY0-NEXT:    [[TMP1755:%.*]] = load i16, ptr [[USX]], align 2
44061 // SIMD-ONLY0-NEXT:    [[CONV2835:%.*]] = zext i16 [[TMP1755]] to i32
44062 // SIMD-ONLY0-NEXT:    [[CMP2836:%.*]] = icmp eq i32 [[CONV2834]], [[CONV2835]]
44063 // SIMD-ONLY0-NEXT:    br i1 [[CMP2836]], label [[IF_THEN2838:%.*]], label [[IF_ELSE2839:%.*]]
44064 // SIMD-ONLY0:       if.then2838:
44065 // SIMD-ONLY0-NEXT:    [[TMP1756:%.*]] = load i16, ptr [[USD]], align 2
44066 // SIMD-ONLY0-NEXT:    store i16 [[TMP1756]], ptr [[USX]], align 2
44067 // SIMD-ONLY0-NEXT:    br label [[IF_END2840:%.*]]
44068 // SIMD-ONLY0:       if.else2839:
44069 // SIMD-ONLY0-NEXT:    [[TMP1757:%.*]] = load i16, ptr [[USX]], align 2
44070 // SIMD-ONLY0-NEXT:    store i16 [[TMP1757]], ptr [[USV]], align 2
44071 // SIMD-ONLY0-NEXT:    br label [[IF_END2840]]
44072 // SIMD-ONLY0:       if.end2840:
44073 // SIMD-ONLY0-NEXT:    [[TMP1758:%.*]] = load i16, ptr [[USX]], align 2
44074 // SIMD-ONLY0-NEXT:    [[CONV2841:%.*]] = zext i16 [[TMP1758]] to i32
44075 // SIMD-ONLY0-NEXT:    [[TMP1759:%.*]] = load i16, ptr [[USE]], align 2
44076 // SIMD-ONLY0-NEXT:    [[CONV2842:%.*]] = zext i16 [[TMP1759]] to i32
44077 // SIMD-ONLY0-NEXT:    [[CMP2843:%.*]] = icmp eq i32 [[CONV2841]], [[CONV2842]]
44078 // SIMD-ONLY0-NEXT:    [[CONV2844:%.*]] = zext i1 [[CMP2843]] to i32
44079 // SIMD-ONLY0-NEXT:    [[CONV2845:%.*]] = trunc i32 [[CONV2844]] to i16
44080 // SIMD-ONLY0-NEXT:    store i16 [[CONV2845]], ptr [[USR]], align 2
44081 // SIMD-ONLY0-NEXT:    [[TMP1760:%.*]] = load i16, ptr [[USR]], align 2
44082 // SIMD-ONLY0-NEXT:    [[TOBOOL2846:%.*]] = icmp ne i16 [[TMP1760]], 0
44083 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2846]], label [[IF_THEN2847:%.*]], label [[IF_END2848:%.*]]
44084 // SIMD-ONLY0:       if.then2847:
44085 // SIMD-ONLY0-NEXT:    [[TMP1761:%.*]] = load i16, ptr [[USD]], align 2
44086 // SIMD-ONLY0-NEXT:    store i16 [[TMP1761]], ptr [[USX]], align 2
44087 // SIMD-ONLY0-NEXT:    br label [[IF_END2848]]
44088 // SIMD-ONLY0:       if.end2848:
44089 // SIMD-ONLY0-NEXT:    [[TMP1762:%.*]] = load i16, ptr [[USE]], align 2
44090 // SIMD-ONLY0-NEXT:    [[CONV2849:%.*]] = zext i16 [[TMP1762]] to i32
44091 // SIMD-ONLY0-NEXT:    [[TMP1763:%.*]] = load i16, ptr [[USX]], align 2
44092 // SIMD-ONLY0-NEXT:    [[CONV2850:%.*]] = zext i16 [[TMP1763]] to i32
44093 // SIMD-ONLY0-NEXT:    [[CMP2851:%.*]] = icmp eq i32 [[CONV2849]], [[CONV2850]]
44094 // SIMD-ONLY0-NEXT:    [[CONV2852:%.*]] = zext i1 [[CMP2851]] to i32
44095 // SIMD-ONLY0-NEXT:    [[CONV2853:%.*]] = trunc i32 [[CONV2852]] to i16
44096 // SIMD-ONLY0-NEXT:    store i16 [[CONV2853]], ptr [[USR]], align 2
44097 // SIMD-ONLY0-NEXT:    [[TMP1764:%.*]] = load i16, ptr [[USR]], align 2
44098 // SIMD-ONLY0-NEXT:    [[TOBOOL2854:%.*]] = icmp ne i16 [[TMP1764]], 0
44099 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2854]], label [[IF_THEN2855:%.*]], label [[IF_END2856:%.*]]
44100 // SIMD-ONLY0:       if.then2855:
44101 // SIMD-ONLY0-NEXT:    [[TMP1765:%.*]] = load i16, ptr [[USD]], align 2
44102 // SIMD-ONLY0-NEXT:    store i16 [[TMP1765]], ptr [[USX]], align 2
44103 // SIMD-ONLY0-NEXT:    br label [[IF_END2856]]
44104 // SIMD-ONLY0:       if.end2856:
44105 // SIMD-ONLY0-NEXT:    [[TMP1766:%.*]] = load i16, ptr [[USX]], align 2
44106 // SIMD-ONLY0-NEXT:    [[CONV2857:%.*]] = zext i16 [[TMP1766]] to i32
44107 // SIMD-ONLY0-NEXT:    [[TMP1767:%.*]] = load i16, ptr [[USE]], align 2
44108 // SIMD-ONLY0-NEXT:    [[CONV2858:%.*]] = zext i16 [[TMP1767]] to i32
44109 // SIMD-ONLY0-NEXT:    [[CMP2859:%.*]] = icmp eq i32 [[CONV2857]], [[CONV2858]]
44110 // SIMD-ONLY0-NEXT:    [[CONV2860:%.*]] = zext i1 [[CMP2859]] to i32
44111 // SIMD-ONLY0-NEXT:    [[CONV2861:%.*]] = trunc i32 [[CONV2860]] to i16
44112 // SIMD-ONLY0-NEXT:    store i16 [[CONV2861]], ptr [[USR]], align 2
44113 // SIMD-ONLY0-NEXT:    [[TMP1768:%.*]] = load i16, ptr [[USR]], align 2
44114 // SIMD-ONLY0-NEXT:    [[TOBOOL2862:%.*]] = icmp ne i16 [[TMP1768]], 0
44115 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2862]], label [[IF_THEN2863:%.*]], label [[IF_ELSE2864:%.*]]
44116 // SIMD-ONLY0:       if.then2863:
44117 // SIMD-ONLY0-NEXT:    [[TMP1769:%.*]] = load i16, ptr [[USD]], align 2
44118 // SIMD-ONLY0-NEXT:    store i16 [[TMP1769]], ptr [[USX]], align 2
44119 // SIMD-ONLY0-NEXT:    br label [[IF_END2865:%.*]]
44120 // SIMD-ONLY0:       if.else2864:
44121 // SIMD-ONLY0-NEXT:    [[TMP1770:%.*]] = load i16, ptr [[USX]], align 2
44122 // SIMD-ONLY0-NEXT:    store i16 [[TMP1770]], ptr [[USV]], align 2
44123 // SIMD-ONLY0-NEXT:    br label [[IF_END2865]]
44124 // SIMD-ONLY0:       if.end2865:
44125 // SIMD-ONLY0-NEXT:    [[TMP1771:%.*]] = load i16, ptr [[USE]], align 2
44126 // SIMD-ONLY0-NEXT:    [[CONV2866:%.*]] = zext i16 [[TMP1771]] to i32
44127 // SIMD-ONLY0-NEXT:    [[TMP1772:%.*]] = load i16, ptr [[USX]], align 2
44128 // SIMD-ONLY0-NEXT:    [[CONV2867:%.*]] = zext i16 [[TMP1772]] to i32
44129 // SIMD-ONLY0-NEXT:    [[CMP2868:%.*]] = icmp eq i32 [[CONV2866]], [[CONV2867]]
44130 // SIMD-ONLY0-NEXT:    [[CONV2869:%.*]] = zext i1 [[CMP2868]] to i32
44131 // SIMD-ONLY0-NEXT:    [[CONV2870:%.*]] = trunc i32 [[CONV2869]] to i16
44132 // SIMD-ONLY0-NEXT:    store i16 [[CONV2870]], ptr [[USR]], align 2
44133 // SIMD-ONLY0-NEXT:    [[TMP1773:%.*]] = load i16, ptr [[USR]], align 2
44134 // SIMD-ONLY0-NEXT:    [[TOBOOL2871:%.*]] = icmp ne i16 [[TMP1773]], 0
44135 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2871]], label [[IF_THEN2872:%.*]], label [[IF_ELSE2873:%.*]]
44136 // SIMD-ONLY0:       if.then2872:
44137 // SIMD-ONLY0-NEXT:    [[TMP1774:%.*]] = load i16, ptr [[USD]], align 2
44138 // SIMD-ONLY0-NEXT:    store i16 [[TMP1774]], ptr [[USX]], align 2
44139 // SIMD-ONLY0-NEXT:    br label [[IF_END2874:%.*]]
44140 // SIMD-ONLY0:       if.else2873:
44141 // SIMD-ONLY0-NEXT:    [[TMP1775:%.*]] = load i16, ptr [[USX]], align 2
44142 // SIMD-ONLY0-NEXT:    store i16 [[TMP1775]], ptr [[USV]], align 2
44143 // SIMD-ONLY0-NEXT:    br label [[IF_END2874]]
44144 // SIMD-ONLY0:       if.end2874:
44145 // SIMD-ONLY0-NEXT:    [[TMP1776:%.*]] = load i32, ptr [[IX]], align 4
44146 // SIMD-ONLY0-NEXT:    store i32 [[TMP1776]], ptr [[IV]], align 4
44147 // SIMD-ONLY0-NEXT:    [[TMP1777:%.*]] = load i32, ptr [[IE]], align 4
44148 // SIMD-ONLY0-NEXT:    [[TMP1778:%.*]] = load i32, ptr [[IX]], align 4
44149 // SIMD-ONLY0-NEXT:    [[CMP2875:%.*]] = icmp sgt i32 [[TMP1777]], [[TMP1778]]
44150 // SIMD-ONLY0-NEXT:    br i1 [[CMP2875]], label [[IF_THEN2877:%.*]], label [[IF_END2878:%.*]]
44151 // SIMD-ONLY0:       if.then2877:
44152 // SIMD-ONLY0-NEXT:    [[TMP1779:%.*]] = load i32, ptr [[IE]], align 4
44153 // SIMD-ONLY0-NEXT:    store i32 [[TMP1779]], ptr [[IX]], align 4
44154 // SIMD-ONLY0-NEXT:    br label [[IF_END2878]]
44155 // SIMD-ONLY0:       if.end2878:
44156 // SIMD-ONLY0-NEXT:    [[TMP1780:%.*]] = load i32, ptr [[IX]], align 4
44157 // SIMD-ONLY0-NEXT:    store i32 [[TMP1780]], ptr [[IV]], align 4
44158 // SIMD-ONLY0-NEXT:    [[TMP1781:%.*]] = load i32, ptr [[IX]], align 4
44159 // SIMD-ONLY0-NEXT:    [[TMP1782:%.*]] = load i32, ptr [[IE]], align 4
44160 // SIMD-ONLY0-NEXT:    [[CMP2879:%.*]] = icmp sgt i32 [[TMP1781]], [[TMP1782]]
44161 // SIMD-ONLY0-NEXT:    br i1 [[CMP2879]], label [[IF_THEN2881:%.*]], label [[IF_END2882:%.*]]
44162 // SIMD-ONLY0:       if.then2881:
44163 // SIMD-ONLY0-NEXT:    [[TMP1783:%.*]] = load i32, ptr [[IE]], align 4
44164 // SIMD-ONLY0-NEXT:    store i32 [[TMP1783]], ptr [[IX]], align 4
44165 // SIMD-ONLY0-NEXT:    br label [[IF_END2882]]
44166 // SIMD-ONLY0:       if.end2882:
44167 // SIMD-ONLY0-NEXT:    [[TMP1784:%.*]] = load i32, ptr [[IX]], align 4
44168 // SIMD-ONLY0-NEXT:    store i32 [[TMP1784]], ptr [[IV]], align 4
44169 // SIMD-ONLY0-NEXT:    [[TMP1785:%.*]] = load i32, ptr [[IE]], align 4
44170 // SIMD-ONLY0-NEXT:    [[TMP1786:%.*]] = load i32, ptr [[IX]], align 4
44171 // SIMD-ONLY0-NEXT:    [[CMP2883:%.*]] = icmp slt i32 [[TMP1785]], [[TMP1786]]
44172 // SIMD-ONLY0-NEXT:    br i1 [[CMP2883]], label [[IF_THEN2885:%.*]], label [[IF_END2886:%.*]]
44173 // SIMD-ONLY0:       if.then2885:
44174 // SIMD-ONLY0-NEXT:    [[TMP1787:%.*]] = load i32, ptr [[IE]], align 4
44175 // SIMD-ONLY0-NEXT:    store i32 [[TMP1787]], ptr [[IX]], align 4
44176 // SIMD-ONLY0-NEXT:    br label [[IF_END2886]]
44177 // SIMD-ONLY0:       if.end2886:
44178 // SIMD-ONLY0-NEXT:    [[TMP1788:%.*]] = load i32, ptr [[IX]], align 4
44179 // SIMD-ONLY0-NEXT:    store i32 [[TMP1788]], ptr [[IV]], align 4
44180 // SIMD-ONLY0-NEXT:    [[TMP1789:%.*]] = load i32, ptr [[IX]], align 4
44181 // SIMD-ONLY0-NEXT:    [[TMP1790:%.*]] = load i32, ptr [[IE]], align 4
44182 // SIMD-ONLY0-NEXT:    [[CMP2887:%.*]] = icmp slt i32 [[TMP1789]], [[TMP1790]]
44183 // SIMD-ONLY0-NEXT:    br i1 [[CMP2887]], label [[IF_THEN2889:%.*]], label [[IF_END2890:%.*]]
44184 // SIMD-ONLY0:       if.then2889:
44185 // SIMD-ONLY0-NEXT:    [[TMP1791:%.*]] = load i32, ptr [[IE]], align 4
44186 // SIMD-ONLY0-NEXT:    store i32 [[TMP1791]], ptr [[IX]], align 4
44187 // SIMD-ONLY0-NEXT:    br label [[IF_END2890]]
44188 // SIMD-ONLY0:       if.end2890:
44189 // SIMD-ONLY0-NEXT:    [[TMP1792:%.*]] = load i32, ptr [[IX]], align 4
44190 // SIMD-ONLY0-NEXT:    store i32 [[TMP1792]], ptr [[IV]], align 4
44191 // SIMD-ONLY0-NEXT:    [[TMP1793:%.*]] = load i32, ptr [[IX]], align 4
44192 // SIMD-ONLY0-NEXT:    [[TMP1794:%.*]] = load i32, ptr [[IE]], align 4
44193 // SIMD-ONLY0-NEXT:    [[CMP2891:%.*]] = icmp eq i32 [[TMP1793]], [[TMP1794]]
44194 // SIMD-ONLY0-NEXT:    br i1 [[CMP2891]], label [[IF_THEN2893:%.*]], label [[IF_END2894:%.*]]
44195 // SIMD-ONLY0:       if.then2893:
44196 // SIMD-ONLY0-NEXT:    [[TMP1795:%.*]] = load i32, ptr [[ID]], align 4
44197 // SIMD-ONLY0-NEXT:    store i32 [[TMP1795]], ptr [[IX]], align 4
44198 // SIMD-ONLY0-NEXT:    br label [[IF_END2894]]
44199 // SIMD-ONLY0:       if.end2894:
44200 // SIMD-ONLY0-NEXT:    [[TMP1796:%.*]] = load i32, ptr [[IX]], align 4
44201 // SIMD-ONLY0-NEXT:    store i32 [[TMP1796]], ptr [[IV]], align 4
44202 // SIMD-ONLY0-NEXT:    [[TMP1797:%.*]] = load i32, ptr [[IE]], align 4
44203 // SIMD-ONLY0-NEXT:    [[TMP1798:%.*]] = load i32, ptr [[IX]], align 4
44204 // SIMD-ONLY0-NEXT:    [[CMP2895:%.*]] = icmp eq i32 [[TMP1797]], [[TMP1798]]
44205 // SIMD-ONLY0-NEXT:    br i1 [[CMP2895]], label [[IF_THEN2897:%.*]], label [[IF_END2898:%.*]]
44206 // SIMD-ONLY0:       if.then2897:
44207 // SIMD-ONLY0-NEXT:    [[TMP1799:%.*]] = load i32, ptr [[ID]], align 4
44208 // SIMD-ONLY0-NEXT:    store i32 [[TMP1799]], ptr [[IX]], align 4
44209 // SIMD-ONLY0-NEXT:    br label [[IF_END2898]]
44210 // SIMD-ONLY0:       if.end2898:
44211 // SIMD-ONLY0-NEXT:    [[TMP1800:%.*]] = load i32, ptr [[IE]], align 4
44212 // SIMD-ONLY0-NEXT:    [[TMP1801:%.*]] = load i32, ptr [[IX]], align 4
44213 // SIMD-ONLY0-NEXT:    [[CMP2899:%.*]] = icmp sgt i32 [[TMP1800]], [[TMP1801]]
44214 // SIMD-ONLY0-NEXT:    br i1 [[CMP2899]], label [[IF_THEN2901:%.*]], label [[IF_END2902:%.*]]
44215 // SIMD-ONLY0:       if.then2901:
44216 // SIMD-ONLY0-NEXT:    [[TMP1802:%.*]] = load i32, ptr [[IE]], align 4
44217 // SIMD-ONLY0-NEXT:    store i32 [[TMP1802]], ptr [[IX]], align 4
44218 // SIMD-ONLY0-NEXT:    br label [[IF_END2902]]
44219 // SIMD-ONLY0:       if.end2902:
44220 // SIMD-ONLY0-NEXT:    [[TMP1803:%.*]] = load i32, ptr [[IX]], align 4
44221 // SIMD-ONLY0-NEXT:    store i32 [[TMP1803]], ptr [[IV]], align 4
44222 // SIMD-ONLY0-NEXT:    [[TMP1804:%.*]] = load i32, ptr [[IX]], align 4
44223 // SIMD-ONLY0-NEXT:    [[TMP1805:%.*]] = load i32, ptr [[IE]], align 4
44224 // SIMD-ONLY0-NEXT:    [[CMP2903:%.*]] = icmp sgt i32 [[TMP1804]], [[TMP1805]]
44225 // SIMD-ONLY0-NEXT:    br i1 [[CMP2903]], label [[IF_THEN2905:%.*]], label [[IF_END2906:%.*]]
44226 // SIMD-ONLY0:       if.then2905:
44227 // SIMD-ONLY0-NEXT:    [[TMP1806:%.*]] = load i32, ptr [[IE]], align 4
44228 // SIMD-ONLY0-NEXT:    store i32 [[TMP1806]], ptr [[IX]], align 4
44229 // SIMD-ONLY0-NEXT:    br label [[IF_END2906]]
44230 // SIMD-ONLY0:       if.end2906:
44231 // SIMD-ONLY0-NEXT:    [[TMP1807:%.*]] = load i32, ptr [[IX]], align 4
44232 // SIMD-ONLY0-NEXT:    store i32 [[TMP1807]], ptr [[IV]], align 4
44233 // SIMD-ONLY0-NEXT:    [[TMP1808:%.*]] = load i32, ptr [[IE]], align 4
44234 // SIMD-ONLY0-NEXT:    [[TMP1809:%.*]] = load i32, ptr [[IX]], align 4
44235 // SIMD-ONLY0-NEXT:    [[CMP2907:%.*]] = icmp slt i32 [[TMP1808]], [[TMP1809]]
44236 // SIMD-ONLY0-NEXT:    br i1 [[CMP2907]], label [[IF_THEN2909:%.*]], label [[IF_END2910:%.*]]
44237 // SIMD-ONLY0:       if.then2909:
44238 // SIMD-ONLY0-NEXT:    [[TMP1810:%.*]] = load i32, ptr [[IE]], align 4
44239 // SIMD-ONLY0-NEXT:    store i32 [[TMP1810]], ptr [[IX]], align 4
44240 // SIMD-ONLY0-NEXT:    br label [[IF_END2910]]
44241 // SIMD-ONLY0:       if.end2910:
44242 // SIMD-ONLY0-NEXT:    [[TMP1811:%.*]] = load i32, ptr [[IX]], align 4
44243 // SIMD-ONLY0-NEXT:    store i32 [[TMP1811]], ptr [[IV]], align 4
44244 // SIMD-ONLY0-NEXT:    [[TMP1812:%.*]] = load i32, ptr [[IX]], align 4
44245 // SIMD-ONLY0-NEXT:    [[TMP1813:%.*]] = load i32, ptr [[IE]], align 4
44246 // SIMD-ONLY0-NEXT:    [[CMP2911:%.*]] = icmp slt i32 [[TMP1812]], [[TMP1813]]
44247 // SIMD-ONLY0-NEXT:    br i1 [[CMP2911]], label [[IF_THEN2913:%.*]], label [[IF_END2914:%.*]]
44248 // SIMD-ONLY0:       if.then2913:
44249 // SIMD-ONLY0-NEXT:    [[TMP1814:%.*]] = load i32, ptr [[IE]], align 4
44250 // SIMD-ONLY0-NEXT:    store i32 [[TMP1814]], ptr [[IX]], align 4
44251 // SIMD-ONLY0-NEXT:    br label [[IF_END2914]]
44252 // SIMD-ONLY0:       if.end2914:
44253 // SIMD-ONLY0-NEXT:    [[TMP1815:%.*]] = load i32, ptr [[IX]], align 4
44254 // SIMD-ONLY0-NEXT:    store i32 [[TMP1815]], ptr [[IV]], align 4
44255 // SIMD-ONLY0-NEXT:    [[TMP1816:%.*]] = load i32, ptr [[IX]], align 4
44256 // SIMD-ONLY0-NEXT:    [[TMP1817:%.*]] = load i32, ptr [[IE]], align 4
44257 // SIMD-ONLY0-NEXT:    [[CMP2915:%.*]] = icmp eq i32 [[TMP1816]], [[TMP1817]]
44258 // SIMD-ONLY0-NEXT:    br i1 [[CMP2915]], label [[IF_THEN2917:%.*]], label [[IF_END2918:%.*]]
44259 // SIMD-ONLY0:       if.then2917:
44260 // SIMD-ONLY0-NEXT:    [[TMP1818:%.*]] = load i32, ptr [[ID]], align 4
44261 // SIMD-ONLY0-NEXT:    store i32 [[TMP1818]], ptr [[IX]], align 4
44262 // SIMD-ONLY0-NEXT:    br label [[IF_END2918]]
44263 // SIMD-ONLY0:       if.end2918:
44264 // SIMD-ONLY0-NEXT:    [[TMP1819:%.*]] = load i32, ptr [[IX]], align 4
44265 // SIMD-ONLY0-NEXT:    store i32 [[TMP1819]], ptr [[IV]], align 4
44266 // SIMD-ONLY0-NEXT:    [[TMP1820:%.*]] = load i32, ptr [[IE]], align 4
44267 // SIMD-ONLY0-NEXT:    [[TMP1821:%.*]] = load i32, ptr [[IX]], align 4
44268 // SIMD-ONLY0-NEXT:    [[CMP2919:%.*]] = icmp eq i32 [[TMP1820]], [[TMP1821]]
44269 // SIMD-ONLY0-NEXT:    br i1 [[CMP2919]], label [[IF_THEN2921:%.*]], label [[IF_END2922:%.*]]
44270 // SIMD-ONLY0:       if.then2921:
44271 // SIMD-ONLY0-NEXT:    [[TMP1822:%.*]] = load i32, ptr [[ID]], align 4
44272 // SIMD-ONLY0-NEXT:    store i32 [[TMP1822]], ptr [[IX]], align 4
44273 // SIMD-ONLY0-NEXT:    br label [[IF_END2922]]
44274 // SIMD-ONLY0:       if.end2922:
44275 // SIMD-ONLY0-NEXT:    [[TMP1823:%.*]] = load i32, ptr [[IX]], align 4
44276 // SIMD-ONLY0-NEXT:    store i32 [[TMP1823]], ptr [[IV]], align 4
44277 // SIMD-ONLY0-NEXT:    [[TMP1824:%.*]] = load i32, ptr [[IX]], align 4
44278 // SIMD-ONLY0-NEXT:    [[TMP1825:%.*]] = load i32, ptr [[IE]], align 4
44279 // SIMD-ONLY0-NEXT:    [[CMP2923:%.*]] = icmp eq i32 [[TMP1824]], [[TMP1825]]
44280 // SIMD-ONLY0-NEXT:    br i1 [[CMP2923]], label [[IF_THEN2925:%.*]], label [[IF_ELSE2926:%.*]]
44281 // SIMD-ONLY0:       if.then2925:
44282 // SIMD-ONLY0-NEXT:    [[TMP1826:%.*]] = load i32, ptr [[ID]], align 4
44283 // SIMD-ONLY0-NEXT:    store i32 [[TMP1826]], ptr [[IX]], align 4
44284 // SIMD-ONLY0-NEXT:    br label [[IF_END2927:%.*]]
44285 // SIMD-ONLY0:       if.else2926:
44286 // SIMD-ONLY0-NEXT:    [[TMP1827:%.*]] = load i32, ptr [[IX]], align 4
44287 // SIMD-ONLY0-NEXT:    store i32 [[TMP1827]], ptr [[IV]], align 4
44288 // SIMD-ONLY0-NEXT:    br label [[IF_END2927]]
44289 // SIMD-ONLY0:       if.end2927:
44290 // SIMD-ONLY0-NEXT:    [[TMP1828:%.*]] = load i32, ptr [[IE]], align 4
44291 // SIMD-ONLY0-NEXT:    [[TMP1829:%.*]] = load i32, ptr [[IX]], align 4
44292 // SIMD-ONLY0-NEXT:    [[CMP2928:%.*]] = icmp eq i32 [[TMP1828]], [[TMP1829]]
44293 // SIMD-ONLY0-NEXT:    br i1 [[CMP2928]], label [[IF_THEN2930:%.*]], label [[IF_ELSE2931:%.*]]
44294 // SIMD-ONLY0:       if.then2930:
44295 // SIMD-ONLY0-NEXT:    [[TMP1830:%.*]] = load i32, ptr [[ID]], align 4
44296 // SIMD-ONLY0-NEXT:    store i32 [[TMP1830]], ptr [[IX]], align 4
44297 // SIMD-ONLY0-NEXT:    br label [[IF_END2932:%.*]]
44298 // SIMD-ONLY0:       if.else2931:
44299 // SIMD-ONLY0-NEXT:    [[TMP1831:%.*]] = load i32, ptr [[IX]], align 4
44300 // SIMD-ONLY0-NEXT:    store i32 [[TMP1831]], ptr [[IV]], align 4
44301 // SIMD-ONLY0-NEXT:    br label [[IF_END2932]]
44302 // SIMD-ONLY0:       if.end2932:
44303 // SIMD-ONLY0-NEXT:    [[TMP1832:%.*]] = load i32, ptr [[IX]], align 4
44304 // SIMD-ONLY0-NEXT:    [[TMP1833:%.*]] = load i32, ptr [[IE]], align 4
44305 // SIMD-ONLY0-NEXT:    [[CMP2933:%.*]] = icmp eq i32 [[TMP1832]], [[TMP1833]]
44306 // SIMD-ONLY0-NEXT:    [[CONV2934:%.*]] = zext i1 [[CMP2933]] to i32
44307 // SIMD-ONLY0-NEXT:    store i32 [[CONV2934]], ptr [[IR]], align 4
44308 // SIMD-ONLY0-NEXT:    [[TMP1834:%.*]] = load i32, ptr [[IR]], align 4
44309 // SIMD-ONLY0-NEXT:    [[TOBOOL2935:%.*]] = icmp ne i32 [[TMP1834]], 0
44310 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2935]], label [[IF_THEN2936:%.*]], label [[IF_END2937:%.*]]
44311 // SIMD-ONLY0:       if.then2936:
44312 // SIMD-ONLY0-NEXT:    [[TMP1835:%.*]] = load i32, ptr [[ID]], align 4
44313 // SIMD-ONLY0-NEXT:    store i32 [[TMP1835]], ptr [[IX]], align 4
44314 // SIMD-ONLY0-NEXT:    br label [[IF_END2937]]
44315 // SIMD-ONLY0:       if.end2937:
44316 // SIMD-ONLY0-NEXT:    [[TMP1836:%.*]] = load i32, ptr [[IE]], align 4
44317 // SIMD-ONLY0-NEXT:    [[TMP1837:%.*]] = load i32, ptr [[IX]], align 4
44318 // SIMD-ONLY0-NEXT:    [[CMP2938:%.*]] = icmp eq i32 [[TMP1836]], [[TMP1837]]
44319 // SIMD-ONLY0-NEXT:    [[CONV2939:%.*]] = zext i1 [[CMP2938]] to i32
44320 // SIMD-ONLY0-NEXT:    store i32 [[CONV2939]], ptr [[IR]], align 4
44321 // SIMD-ONLY0-NEXT:    [[TMP1838:%.*]] = load i32, ptr [[IR]], align 4
44322 // SIMD-ONLY0-NEXT:    [[TOBOOL2940:%.*]] = icmp ne i32 [[TMP1838]], 0
44323 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2940]], label [[IF_THEN2941:%.*]], label [[IF_END2942:%.*]]
44324 // SIMD-ONLY0:       if.then2941:
44325 // SIMD-ONLY0-NEXT:    [[TMP1839:%.*]] = load i32, ptr [[ID]], align 4
44326 // SIMD-ONLY0-NEXT:    store i32 [[TMP1839]], ptr [[IX]], align 4
44327 // SIMD-ONLY0-NEXT:    br label [[IF_END2942]]
44328 // SIMD-ONLY0:       if.end2942:
44329 // SIMD-ONLY0-NEXT:    [[TMP1840:%.*]] = load i32, ptr [[IX]], align 4
44330 // SIMD-ONLY0-NEXT:    [[TMP1841:%.*]] = load i32, ptr [[IE]], align 4
44331 // SIMD-ONLY0-NEXT:    [[CMP2943:%.*]] = icmp eq i32 [[TMP1840]], [[TMP1841]]
44332 // SIMD-ONLY0-NEXT:    [[CONV2944:%.*]] = zext i1 [[CMP2943]] to i32
44333 // SIMD-ONLY0-NEXT:    store i32 [[CONV2944]], ptr [[IR]], align 4
44334 // SIMD-ONLY0-NEXT:    [[TMP1842:%.*]] = load i32, ptr [[IR]], align 4
44335 // SIMD-ONLY0-NEXT:    [[TOBOOL2945:%.*]] = icmp ne i32 [[TMP1842]], 0
44336 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2945]], label [[IF_THEN2946:%.*]], label [[IF_ELSE2947:%.*]]
44337 // SIMD-ONLY0:       if.then2946:
44338 // SIMD-ONLY0-NEXT:    [[TMP1843:%.*]] = load i32, ptr [[ID]], align 4
44339 // SIMD-ONLY0-NEXT:    store i32 [[TMP1843]], ptr [[IX]], align 4
44340 // SIMD-ONLY0-NEXT:    br label [[IF_END2948:%.*]]
44341 // SIMD-ONLY0:       if.else2947:
44342 // SIMD-ONLY0-NEXT:    [[TMP1844:%.*]] = load i32, ptr [[IX]], align 4
44343 // SIMD-ONLY0-NEXT:    store i32 [[TMP1844]], ptr [[IV]], align 4
44344 // SIMD-ONLY0-NEXT:    br label [[IF_END2948]]
44345 // SIMD-ONLY0:       if.end2948:
44346 // SIMD-ONLY0-NEXT:    [[TMP1845:%.*]] = load i32, ptr [[IE]], align 4
44347 // SIMD-ONLY0-NEXT:    [[TMP1846:%.*]] = load i32, ptr [[IX]], align 4
44348 // SIMD-ONLY0-NEXT:    [[CMP2949:%.*]] = icmp eq i32 [[TMP1845]], [[TMP1846]]
44349 // SIMD-ONLY0-NEXT:    [[CONV2950:%.*]] = zext i1 [[CMP2949]] to i32
44350 // SIMD-ONLY0-NEXT:    store i32 [[CONV2950]], ptr [[IR]], align 4
44351 // SIMD-ONLY0-NEXT:    [[TMP1847:%.*]] = load i32, ptr [[IR]], align 4
44352 // SIMD-ONLY0-NEXT:    [[TOBOOL2951:%.*]] = icmp ne i32 [[TMP1847]], 0
44353 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL2951]], label [[IF_THEN2952:%.*]], label [[IF_ELSE2953:%.*]]
44354 // SIMD-ONLY0:       if.then2952:
44355 // SIMD-ONLY0-NEXT:    [[TMP1848:%.*]] = load i32, ptr [[ID]], align 4
44356 // SIMD-ONLY0-NEXT:    store i32 [[TMP1848]], ptr [[IX]], align 4
44357 // SIMD-ONLY0-NEXT:    br label [[IF_END2954:%.*]]
44358 // SIMD-ONLY0:       if.else2953:
44359 // SIMD-ONLY0-NEXT:    [[TMP1849:%.*]] = load i32, ptr [[IX]], align 4
44360 // SIMD-ONLY0-NEXT:    store i32 [[TMP1849]], ptr [[IV]], align 4
44361 // SIMD-ONLY0-NEXT:    br label [[IF_END2954]]
44362 // SIMD-ONLY0:       if.end2954:
44363 // SIMD-ONLY0-NEXT:    [[TMP1850:%.*]] = load i32, ptr [[IX]], align 4
44364 // SIMD-ONLY0-NEXT:    store i32 [[TMP1850]], ptr [[IV]], align 4
44365 // SIMD-ONLY0-NEXT:    [[TMP1851:%.*]] = load i32, ptr [[IE]], align 4
44366 // SIMD-ONLY0-NEXT:    [[TMP1852:%.*]] = load i32, ptr [[IX]], align 4
44367 // SIMD-ONLY0-NEXT:    [[CMP2955:%.*]] = icmp sgt i32 [[TMP1851]], [[TMP1852]]
44368 // SIMD-ONLY0-NEXT:    br i1 [[CMP2955]], label [[IF_THEN2957:%.*]], label [[IF_END2958:%.*]]
44369 // SIMD-ONLY0:       if.then2957:
44370 // SIMD-ONLY0-NEXT:    [[TMP1853:%.*]] = load i32, ptr [[IE]], align 4
44371 // SIMD-ONLY0-NEXT:    store i32 [[TMP1853]], ptr [[IX]], align 4
44372 // SIMD-ONLY0-NEXT:    br label [[IF_END2958]]
44373 // SIMD-ONLY0:       if.end2958:
44374 // SIMD-ONLY0-NEXT:    [[TMP1854:%.*]] = load i32, ptr [[IX]], align 4
44375 // SIMD-ONLY0-NEXT:    store i32 [[TMP1854]], ptr [[IV]], align 4
44376 // SIMD-ONLY0-NEXT:    [[TMP1855:%.*]] = load i32, ptr [[IX]], align 4
44377 // SIMD-ONLY0-NEXT:    [[TMP1856:%.*]] = load i32, ptr [[IE]], align 4
44378 // SIMD-ONLY0-NEXT:    [[CMP2959:%.*]] = icmp sgt i32 [[TMP1855]], [[TMP1856]]
44379 // SIMD-ONLY0-NEXT:    br i1 [[CMP2959]], label [[IF_THEN2961:%.*]], label [[IF_END2962:%.*]]
44380 // SIMD-ONLY0:       if.then2961:
44381 // SIMD-ONLY0-NEXT:    [[TMP1857:%.*]] = load i32, ptr [[IE]], align 4
44382 // SIMD-ONLY0-NEXT:    store i32 [[TMP1857]], ptr [[IX]], align 4
44383 // SIMD-ONLY0-NEXT:    br label [[IF_END2962]]
44384 // SIMD-ONLY0:       if.end2962:
44385 // SIMD-ONLY0-NEXT:    [[TMP1858:%.*]] = load i32, ptr [[IX]], align 4
44386 // SIMD-ONLY0-NEXT:    store i32 [[TMP1858]], ptr [[IV]], align 4
44387 // SIMD-ONLY0-NEXT:    [[TMP1859:%.*]] = load i32, ptr [[IE]], align 4
44388 // SIMD-ONLY0-NEXT:    [[TMP1860:%.*]] = load i32, ptr [[IX]], align 4
44389 // SIMD-ONLY0-NEXT:    [[CMP2963:%.*]] = icmp slt i32 [[TMP1859]], [[TMP1860]]
44390 // SIMD-ONLY0-NEXT:    br i1 [[CMP2963]], label [[IF_THEN2965:%.*]], label [[IF_END2966:%.*]]
44391 // SIMD-ONLY0:       if.then2965:
44392 // SIMD-ONLY0-NEXT:    [[TMP1861:%.*]] = load i32, ptr [[IE]], align 4
44393 // SIMD-ONLY0-NEXT:    store i32 [[TMP1861]], ptr [[IX]], align 4
44394 // SIMD-ONLY0-NEXT:    br label [[IF_END2966]]
44395 // SIMD-ONLY0:       if.end2966:
44396 // SIMD-ONLY0-NEXT:    [[TMP1862:%.*]] = load i32, ptr [[IX]], align 4
44397 // SIMD-ONLY0-NEXT:    store i32 [[TMP1862]], ptr [[IV]], align 4
44398 // SIMD-ONLY0-NEXT:    [[TMP1863:%.*]] = load i32, ptr [[IX]], align 4
44399 // SIMD-ONLY0-NEXT:    [[TMP1864:%.*]] = load i32, ptr [[IE]], align 4
44400 // SIMD-ONLY0-NEXT:    [[CMP2967:%.*]] = icmp slt i32 [[TMP1863]], [[TMP1864]]
44401 // SIMD-ONLY0-NEXT:    br i1 [[CMP2967]], label [[IF_THEN2969:%.*]], label [[IF_END2970:%.*]]
44402 // SIMD-ONLY0:       if.then2969:
44403 // SIMD-ONLY0-NEXT:    [[TMP1865:%.*]] = load i32, ptr [[IE]], align 4
44404 // SIMD-ONLY0-NEXT:    store i32 [[TMP1865]], ptr [[IX]], align 4
44405 // SIMD-ONLY0-NEXT:    br label [[IF_END2970]]
44406 // SIMD-ONLY0:       if.end2970:
44407 // SIMD-ONLY0-NEXT:    [[TMP1866:%.*]] = load i32, ptr [[IX]], align 4
44408 // SIMD-ONLY0-NEXT:    store i32 [[TMP1866]], ptr [[IV]], align 4
44409 // SIMD-ONLY0-NEXT:    [[TMP1867:%.*]] = load i32, ptr [[IX]], align 4
44410 // SIMD-ONLY0-NEXT:    [[TMP1868:%.*]] = load i32, ptr [[IE]], align 4
44411 // SIMD-ONLY0-NEXT:    [[CMP2971:%.*]] = icmp eq i32 [[TMP1867]], [[TMP1868]]
44412 // SIMD-ONLY0-NEXT:    br i1 [[CMP2971]], label [[IF_THEN2973:%.*]], label [[IF_END2974:%.*]]
44413 // SIMD-ONLY0:       if.then2973:
44414 // SIMD-ONLY0-NEXT:    [[TMP1869:%.*]] = load i32, ptr [[ID]], align 4
44415 // SIMD-ONLY0-NEXT:    store i32 [[TMP1869]], ptr [[IX]], align 4
44416 // SIMD-ONLY0-NEXT:    br label [[IF_END2974]]
44417 // SIMD-ONLY0:       if.end2974:
44418 // SIMD-ONLY0-NEXT:    [[TMP1870:%.*]] = load i32, ptr [[IX]], align 4
44419 // SIMD-ONLY0-NEXT:    store i32 [[TMP1870]], ptr [[IV]], align 4
44420 // SIMD-ONLY0-NEXT:    [[TMP1871:%.*]] = load i32, ptr [[IE]], align 4
44421 // SIMD-ONLY0-NEXT:    [[TMP1872:%.*]] = load i32, ptr [[IX]], align 4
44422 // SIMD-ONLY0-NEXT:    [[CMP2975:%.*]] = icmp eq i32 [[TMP1871]], [[TMP1872]]
44423 // SIMD-ONLY0-NEXT:    br i1 [[CMP2975]], label [[IF_THEN2977:%.*]], label [[IF_END2978:%.*]]
44424 // SIMD-ONLY0:       if.then2977:
44425 // SIMD-ONLY0-NEXT:    [[TMP1873:%.*]] = load i32, ptr [[ID]], align 4
44426 // SIMD-ONLY0-NEXT:    store i32 [[TMP1873]], ptr [[IX]], align 4
44427 // SIMD-ONLY0-NEXT:    br label [[IF_END2978]]
44428 // SIMD-ONLY0:       if.end2978:
44429 // SIMD-ONLY0-NEXT:    [[TMP1874:%.*]] = load i32, ptr [[IE]], align 4
44430 // SIMD-ONLY0-NEXT:    [[TMP1875:%.*]] = load i32, ptr [[IX]], align 4
44431 // SIMD-ONLY0-NEXT:    [[CMP2979:%.*]] = icmp sgt i32 [[TMP1874]], [[TMP1875]]
44432 // SIMD-ONLY0-NEXT:    br i1 [[CMP2979]], label [[IF_THEN2981:%.*]], label [[IF_END2982:%.*]]
44433 // SIMD-ONLY0:       if.then2981:
44434 // SIMD-ONLY0-NEXT:    [[TMP1876:%.*]] = load i32, ptr [[IE]], align 4
44435 // SIMD-ONLY0-NEXT:    store i32 [[TMP1876]], ptr [[IX]], align 4
44436 // SIMD-ONLY0-NEXT:    br label [[IF_END2982]]
44437 // SIMD-ONLY0:       if.end2982:
44438 // SIMD-ONLY0-NEXT:    [[TMP1877:%.*]] = load i32, ptr [[IX]], align 4
44439 // SIMD-ONLY0-NEXT:    store i32 [[TMP1877]], ptr [[IV]], align 4
44440 // SIMD-ONLY0-NEXT:    [[TMP1878:%.*]] = load i32, ptr [[IX]], align 4
44441 // SIMD-ONLY0-NEXT:    [[TMP1879:%.*]] = load i32, ptr [[IE]], align 4
44442 // SIMD-ONLY0-NEXT:    [[CMP2983:%.*]] = icmp sgt i32 [[TMP1878]], [[TMP1879]]
44443 // SIMD-ONLY0-NEXT:    br i1 [[CMP2983]], label [[IF_THEN2985:%.*]], label [[IF_END2986:%.*]]
44444 // SIMD-ONLY0:       if.then2985:
44445 // SIMD-ONLY0-NEXT:    [[TMP1880:%.*]] = load i32, ptr [[IE]], align 4
44446 // SIMD-ONLY0-NEXT:    store i32 [[TMP1880]], ptr [[IX]], align 4
44447 // SIMD-ONLY0-NEXT:    br label [[IF_END2986]]
44448 // SIMD-ONLY0:       if.end2986:
44449 // SIMD-ONLY0-NEXT:    [[TMP1881:%.*]] = load i32, ptr [[IX]], align 4
44450 // SIMD-ONLY0-NEXT:    store i32 [[TMP1881]], ptr [[IV]], align 4
44451 // SIMD-ONLY0-NEXT:    [[TMP1882:%.*]] = load i32, ptr [[IE]], align 4
44452 // SIMD-ONLY0-NEXT:    [[TMP1883:%.*]] = load i32, ptr [[IX]], align 4
44453 // SIMD-ONLY0-NEXT:    [[CMP2987:%.*]] = icmp slt i32 [[TMP1882]], [[TMP1883]]
44454 // SIMD-ONLY0-NEXT:    br i1 [[CMP2987]], label [[IF_THEN2989:%.*]], label [[IF_END2990:%.*]]
44455 // SIMD-ONLY0:       if.then2989:
44456 // SIMD-ONLY0-NEXT:    [[TMP1884:%.*]] = load i32, ptr [[IE]], align 4
44457 // SIMD-ONLY0-NEXT:    store i32 [[TMP1884]], ptr [[IX]], align 4
44458 // SIMD-ONLY0-NEXT:    br label [[IF_END2990]]
44459 // SIMD-ONLY0:       if.end2990:
44460 // SIMD-ONLY0-NEXT:    [[TMP1885:%.*]] = load i32, ptr [[IX]], align 4
44461 // SIMD-ONLY0-NEXT:    store i32 [[TMP1885]], ptr [[IV]], align 4
44462 // SIMD-ONLY0-NEXT:    [[TMP1886:%.*]] = load i32, ptr [[IX]], align 4
44463 // SIMD-ONLY0-NEXT:    [[TMP1887:%.*]] = load i32, ptr [[IE]], align 4
44464 // SIMD-ONLY0-NEXT:    [[CMP2991:%.*]] = icmp slt i32 [[TMP1886]], [[TMP1887]]
44465 // SIMD-ONLY0-NEXT:    br i1 [[CMP2991]], label [[IF_THEN2993:%.*]], label [[IF_END2994:%.*]]
44466 // SIMD-ONLY0:       if.then2993:
44467 // SIMD-ONLY0-NEXT:    [[TMP1888:%.*]] = load i32, ptr [[IE]], align 4
44468 // SIMD-ONLY0-NEXT:    store i32 [[TMP1888]], ptr [[IX]], align 4
44469 // SIMD-ONLY0-NEXT:    br label [[IF_END2994]]
44470 // SIMD-ONLY0:       if.end2994:
44471 // SIMD-ONLY0-NEXT:    [[TMP1889:%.*]] = load i32, ptr [[IX]], align 4
44472 // SIMD-ONLY0-NEXT:    store i32 [[TMP1889]], ptr [[IV]], align 4
44473 // SIMD-ONLY0-NEXT:    [[TMP1890:%.*]] = load i32, ptr [[IX]], align 4
44474 // SIMD-ONLY0-NEXT:    [[TMP1891:%.*]] = load i32, ptr [[IE]], align 4
44475 // SIMD-ONLY0-NEXT:    [[CMP2995:%.*]] = icmp eq i32 [[TMP1890]], [[TMP1891]]
44476 // SIMD-ONLY0-NEXT:    br i1 [[CMP2995]], label [[IF_THEN2997:%.*]], label [[IF_END2998:%.*]]
44477 // SIMD-ONLY0:       if.then2997:
44478 // SIMD-ONLY0-NEXT:    [[TMP1892:%.*]] = load i32, ptr [[ID]], align 4
44479 // SIMD-ONLY0-NEXT:    store i32 [[TMP1892]], ptr [[IX]], align 4
44480 // SIMD-ONLY0-NEXT:    br label [[IF_END2998]]
44481 // SIMD-ONLY0:       if.end2998:
44482 // SIMD-ONLY0-NEXT:    [[TMP1893:%.*]] = load i32, ptr [[IX]], align 4
44483 // SIMD-ONLY0-NEXT:    store i32 [[TMP1893]], ptr [[IV]], align 4
44484 // SIMD-ONLY0-NEXT:    [[TMP1894:%.*]] = load i32, ptr [[IE]], align 4
44485 // SIMD-ONLY0-NEXT:    [[TMP1895:%.*]] = load i32, ptr [[IX]], align 4
44486 // SIMD-ONLY0-NEXT:    [[CMP2999:%.*]] = icmp eq i32 [[TMP1894]], [[TMP1895]]
44487 // SIMD-ONLY0-NEXT:    br i1 [[CMP2999]], label [[IF_THEN3001:%.*]], label [[IF_END3002:%.*]]
44488 // SIMD-ONLY0:       if.then3001:
44489 // SIMD-ONLY0-NEXT:    [[TMP1896:%.*]] = load i32, ptr [[ID]], align 4
44490 // SIMD-ONLY0-NEXT:    store i32 [[TMP1896]], ptr [[IX]], align 4
44491 // SIMD-ONLY0-NEXT:    br label [[IF_END3002]]
44492 // SIMD-ONLY0:       if.end3002:
44493 // SIMD-ONLY0-NEXT:    [[TMP1897:%.*]] = load i32, ptr [[IX]], align 4
44494 // SIMD-ONLY0-NEXT:    store i32 [[TMP1897]], ptr [[IV]], align 4
44495 // SIMD-ONLY0-NEXT:    [[TMP1898:%.*]] = load i32, ptr [[IX]], align 4
44496 // SIMD-ONLY0-NEXT:    [[TMP1899:%.*]] = load i32, ptr [[IE]], align 4
44497 // SIMD-ONLY0-NEXT:    [[CMP3003:%.*]] = icmp eq i32 [[TMP1898]], [[TMP1899]]
44498 // SIMD-ONLY0-NEXT:    br i1 [[CMP3003]], label [[IF_THEN3005:%.*]], label [[IF_ELSE3006:%.*]]
44499 // SIMD-ONLY0:       if.then3005:
44500 // SIMD-ONLY0-NEXT:    [[TMP1900:%.*]] = load i32, ptr [[ID]], align 4
44501 // SIMD-ONLY0-NEXT:    store i32 [[TMP1900]], ptr [[IX]], align 4
44502 // SIMD-ONLY0-NEXT:    br label [[IF_END3007:%.*]]
44503 // SIMD-ONLY0:       if.else3006:
44504 // SIMD-ONLY0-NEXT:    [[TMP1901:%.*]] = load i32, ptr [[IX]], align 4
44505 // SIMD-ONLY0-NEXT:    store i32 [[TMP1901]], ptr [[IV]], align 4
44506 // SIMD-ONLY0-NEXT:    br label [[IF_END3007]]
44507 // SIMD-ONLY0:       if.end3007:
44508 // SIMD-ONLY0-NEXT:    [[TMP1902:%.*]] = load i32, ptr [[IE]], align 4
44509 // SIMD-ONLY0-NEXT:    [[TMP1903:%.*]] = load i32, ptr [[IX]], align 4
44510 // SIMD-ONLY0-NEXT:    [[CMP3008:%.*]] = icmp eq i32 [[TMP1902]], [[TMP1903]]
44511 // SIMD-ONLY0-NEXT:    br i1 [[CMP3008]], label [[IF_THEN3010:%.*]], label [[IF_ELSE3011:%.*]]
44512 // SIMD-ONLY0:       if.then3010:
44513 // SIMD-ONLY0-NEXT:    [[TMP1904:%.*]] = load i32, ptr [[ID]], align 4
44514 // SIMD-ONLY0-NEXT:    store i32 [[TMP1904]], ptr [[IX]], align 4
44515 // SIMD-ONLY0-NEXT:    br label [[IF_END3012:%.*]]
44516 // SIMD-ONLY0:       if.else3011:
44517 // SIMD-ONLY0-NEXT:    [[TMP1905:%.*]] = load i32, ptr [[IX]], align 4
44518 // SIMD-ONLY0-NEXT:    store i32 [[TMP1905]], ptr [[IV]], align 4
44519 // SIMD-ONLY0-NEXT:    br label [[IF_END3012]]
44520 // SIMD-ONLY0:       if.end3012:
44521 // SIMD-ONLY0-NEXT:    [[TMP1906:%.*]] = load i32, ptr [[IX]], align 4
44522 // SIMD-ONLY0-NEXT:    [[TMP1907:%.*]] = load i32, ptr [[IE]], align 4
44523 // SIMD-ONLY0-NEXT:    [[CMP3013:%.*]] = icmp eq i32 [[TMP1906]], [[TMP1907]]
44524 // SIMD-ONLY0-NEXT:    [[CONV3014:%.*]] = zext i1 [[CMP3013]] to i32
44525 // SIMD-ONLY0-NEXT:    store i32 [[CONV3014]], ptr [[IR]], align 4
44526 // SIMD-ONLY0-NEXT:    [[TMP1908:%.*]] = load i32, ptr [[IR]], align 4
44527 // SIMD-ONLY0-NEXT:    [[TOBOOL3015:%.*]] = icmp ne i32 [[TMP1908]], 0
44528 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3015]], label [[IF_THEN3016:%.*]], label [[IF_END3017:%.*]]
44529 // SIMD-ONLY0:       if.then3016:
44530 // SIMD-ONLY0-NEXT:    [[TMP1909:%.*]] = load i32, ptr [[ID]], align 4
44531 // SIMD-ONLY0-NEXT:    store i32 [[TMP1909]], ptr [[IX]], align 4
44532 // SIMD-ONLY0-NEXT:    br label [[IF_END3017]]
44533 // SIMD-ONLY0:       if.end3017:
44534 // SIMD-ONLY0-NEXT:    [[TMP1910:%.*]] = load i32, ptr [[IE]], align 4
44535 // SIMD-ONLY0-NEXT:    [[TMP1911:%.*]] = load i32, ptr [[IX]], align 4
44536 // SIMD-ONLY0-NEXT:    [[CMP3018:%.*]] = icmp eq i32 [[TMP1910]], [[TMP1911]]
44537 // SIMD-ONLY0-NEXT:    [[CONV3019:%.*]] = zext i1 [[CMP3018]] to i32
44538 // SIMD-ONLY0-NEXT:    store i32 [[CONV3019]], ptr [[IR]], align 4
44539 // SIMD-ONLY0-NEXT:    [[TMP1912:%.*]] = load i32, ptr [[IR]], align 4
44540 // SIMD-ONLY0-NEXT:    [[TOBOOL3020:%.*]] = icmp ne i32 [[TMP1912]], 0
44541 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3020]], label [[IF_THEN3021:%.*]], label [[IF_END3022:%.*]]
44542 // SIMD-ONLY0:       if.then3021:
44543 // SIMD-ONLY0-NEXT:    [[TMP1913:%.*]] = load i32, ptr [[ID]], align 4
44544 // SIMD-ONLY0-NEXT:    store i32 [[TMP1913]], ptr [[IX]], align 4
44545 // SIMD-ONLY0-NEXT:    br label [[IF_END3022]]
44546 // SIMD-ONLY0:       if.end3022:
44547 // SIMD-ONLY0-NEXT:    [[TMP1914:%.*]] = load i32, ptr [[IX]], align 4
44548 // SIMD-ONLY0-NEXT:    [[TMP1915:%.*]] = load i32, ptr [[IE]], align 4
44549 // SIMD-ONLY0-NEXT:    [[CMP3023:%.*]] = icmp eq i32 [[TMP1914]], [[TMP1915]]
44550 // SIMD-ONLY0-NEXT:    [[CONV3024:%.*]] = zext i1 [[CMP3023]] to i32
44551 // SIMD-ONLY0-NEXT:    store i32 [[CONV3024]], ptr [[IR]], align 4
44552 // SIMD-ONLY0-NEXT:    [[TMP1916:%.*]] = load i32, ptr [[IR]], align 4
44553 // SIMD-ONLY0-NEXT:    [[TOBOOL3025:%.*]] = icmp ne i32 [[TMP1916]], 0
44554 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3025]], label [[IF_THEN3026:%.*]], label [[IF_ELSE3027:%.*]]
44555 // SIMD-ONLY0:       if.then3026:
44556 // SIMD-ONLY0-NEXT:    [[TMP1917:%.*]] = load i32, ptr [[ID]], align 4
44557 // SIMD-ONLY0-NEXT:    store i32 [[TMP1917]], ptr [[IX]], align 4
44558 // SIMD-ONLY0-NEXT:    br label [[IF_END3028:%.*]]
44559 // SIMD-ONLY0:       if.else3027:
44560 // SIMD-ONLY0-NEXT:    [[TMP1918:%.*]] = load i32, ptr [[IX]], align 4
44561 // SIMD-ONLY0-NEXT:    store i32 [[TMP1918]], ptr [[IV]], align 4
44562 // SIMD-ONLY0-NEXT:    br label [[IF_END3028]]
44563 // SIMD-ONLY0:       if.end3028:
44564 // SIMD-ONLY0-NEXT:    [[TMP1919:%.*]] = load i32, ptr [[IE]], align 4
44565 // SIMD-ONLY0-NEXT:    [[TMP1920:%.*]] = load i32, ptr [[IX]], align 4
44566 // SIMD-ONLY0-NEXT:    [[CMP3029:%.*]] = icmp eq i32 [[TMP1919]], [[TMP1920]]
44567 // SIMD-ONLY0-NEXT:    [[CONV3030:%.*]] = zext i1 [[CMP3029]] to i32
44568 // SIMD-ONLY0-NEXT:    store i32 [[CONV3030]], ptr [[IR]], align 4
44569 // SIMD-ONLY0-NEXT:    [[TMP1921:%.*]] = load i32, ptr [[IR]], align 4
44570 // SIMD-ONLY0-NEXT:    [[TOBOOL3031:%.*]] = icmp ne i32 [[TMP1921]], 0
44571 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3031]], label [[IF_THEN3032:%.*]], label [[IF_ELSE3033:%.*]]
44572 // SIMD-ONLY0:       if.then3032:
44573 // SIMD-ONLY0-NEXT:    [[TMP1922:%.*]] = load i32, ptr [[ID]], align 4
44574 // SIMD-ONLY0-NEXT:    store i32 [[TMP1922]], ptr [[IX]], align 4
44575 // SIMD-ONLY0-NEXT:    br label [[IF_END3034:%.*]]
44576 // SIMD-ONLY0:       if.else3033:
44577 // SIMD-ONLY0-NEXT:    [[TMP1923:%.*]] = load i32, ptr [[IX]], align 4
44578 // SIMD-ONLY0-NEXT:    store i32 [[TMP1923]], ptr [[IV]], align 4
44579 // SIMD-ONLY0-NEXT:    br label [[IF_END3034]]
44580 // SIMD-ONLY0:       if.end3034:
44581 // SIMD-ONLY0-NEXT:    [[TMP1924:%.*]] = load i32, ptr [[IX]], align 4
44582 // SIMD-ONLY0-NEXT:    store i32 [[TMP1924]], ptr [[IV]], align 4
44583 // SIMD-ONLY0-NEXT:    [[TMP1925:%.*]] = load i32, ptr [[IE]], align 4
44584 // SIMD-ONLY0-NEXT:    [[TMP1926:%.*]] = load i32, ptr [[IX]], align 4
44585 // SIMD-ONLY0-NEXT:    [[CMP3035:%.*]] = icmp sgt i32 [[TMP1925]], [[TMP1926]]
44586 // SIMD-ONLY0-NEXT:    br i1 [[CMP3035]], label [[IF_THEN3037:%.*]], label [[IF_END3038:%.*]]
44587 // SIMD-ONLY0:       if.then3037:
44588 // SIMD-ONLY0-NEXT:    [[TMP1927:%.*]] = load i32, ptr [[IE]], align 4
44589 // SIMD-ONLY0-NEXT:    store i32 [[TMP1927]], ptr [[IX]], align 4
44590 // SIMD-ONLY0-NEXT:    br label [[IF_END3038]]
44591 // SIMD-ONLY0:       if.end3038:
44592 // SIMD-ONLY0-NEXT:    [[TMP1928:%.*]] = load i32, ptr [[IX]], align 4
44593 // SIMD-ONLY0-NEXT:    store i32 [[TMP1928]], ptr [[IV]], align 4
44594 // SIMD-ONLY0-NEXT:    [[TMP1929:%.*]] = load i32, ptr [[IX]], align 4
44595 // SIMD-ONLY0-NEXT:    [[TMP1930:%.*]] = load i32, ptr [[IE]], align 4
44596 // SIMD-ONLY0-NEXT:    [[CMP3039:%.*]] = icmp sgt i32 [[TMP1929]], [[TMP1930]]
44597 // SIMD-ONLY0-NEXT:    br i1 [[CMP3039]], label [[IF_THEN3041:%.*]], label [[IF_END3042:%.*]]
44598 // SIMD-ONLY0:       if.then3041:
44599 // SIMD-ONLY0-NEXT:    [[TMP1931:%.*]] = load i32, ptr [[IE]], align 4
44600 // SIMD-ONLY0-NEXT:    store i32 [[TMP1931]], ptr [[IX]], align 4
44601 // SIMD-ONLY0-NEXT:    br label [[IF_END3042]]
44602 // SIMD-ONLY0:       if.end3042:
44603 // SIMD-ONLY0-NEXT:    [[TMP1932:%.*]] = load i32, ptr [[IX]], align 4
44604 // SIMD-ONLY0-NEXT:    store i32 [[TMP1932]], ptr [[IV]], align 4
44605 // SIMD-ONLY0-NEXT:    [[TMP1933:%.*]] = load i32, ptr [[IE]], align 4
44606 // SIMD-ONLY0-NEXT:    [[TMP1934:%.*]] = load i32, ptr [[IX]], align 4
44607 // SIMD-ONLY0-NEXT:    [[CMP3043:%.*]] = icmp slt i32 [[TMP1933]], [[TMP1934]]
44608 // SIMD-ONLY0-NEXT:    br i1 [[CMP3043]], label [[IF_THEN3045:%.*]], label [[IF_END3046:%.*]]
44609 // SIMD-ONLY0:       if.then3045:
44610 // SIMD-ONLY0-NEXT:    [[TMP1935:%.*]] = load i32, ptr [[IE]], align 4
44611 // SIMD-ONLY0-NEXT:    store i32 [[TMP1935]], ptr [[IX]], align 4
44612 // SIMD-ONLY0-NEXT:    br label [[IF_END3046]]
44613 // SIMD-ONLY0:       if.end3046:
44614 // SIMD-ONLY0-NEXT:    [[TMP1936:%.*]] = load i32, ptr [[IX]], align 4
44615 // SIMD-ONLY0-NEXT:    store i32 [[TMP1936]], ptr [[IV]], align 4
44616 // SIMD-ONLY0-NEXT:    [[TMP1937:%.*]] = load i32, ptr [[IX]], align 4
44617 // SIMD-ONLY0-NEXT:    [[TMP1938:%.*]] = load i32, ptr [[IE]], align 4
44618 // SIMD-ONLY0-NEXT:    [[CMP3047:%.*]] = icmp slt i32 [[TMP1937]], [[TMP1938]]
44619 // SIMD-ONLY0-NEXT:    br i1 [[CMP3047]], label [[IF_THEN3049:%.*]], label [[IF_END3050:%.*]]
44620 // SIMD-ONLY0:       if.then3049:
44621 // SIMD-ONLY0-NEXT:    [[TMP1939:%.*]] = load i32, ptr [[IE]], align 4
44622 // SIMD-ONLY0-NEXT:    store i32 [[TMP1939]], ptr [[IX]], align 4
44623 // SIMD-ONLY0-NEXT:    br label [[IF_END3050]]
44624 // SIMD-ONLY0:       if.end3050:
44625 // SIMD-ONLY0-NEXT:    [[TMP1940:%.*]] = load i32, ptr [[IX]], align 4
44626 // SIMD-ONLY0-NEXT:    store i32 [[TMP1940]], ptr [[IV]], align 4
44627 // SIMD-ONLY0-NEXT:    [[TMP1941:%.*]] = load i32, ptr [[IX]], align 4
44628 // SIMD-ONLY0-NEXT:    [[TMP1942:%.*]] = load i32, ptr [[IE]], align 4
44629 // SIMD-ONLY0-NEXT:    [[CMP3051:%.*]] = icmp eq i32 [[TMP1941]], [[TMP1942]]
44630 // SIMD-ONLY0-NEXT:    br i1 [[CMP3051]], label [[IF_THEN3053:%.*]], label [[IF_END3054:%.*]]
44631 // SIMD-ONLY0:       if.then3053:
44632 // SIMD-ONLY0-NEXT:    [[TMP1943:%.*]] = load i32, ptr [[ID]], align 4
44633 // SIMD-ONLY0-NEXT:    store i32 [[TMP1943]], ptr [[IX]], align 4
44634 // SIMD-ONLY0-NEXT:    br label [[IF_END3054]]
44635 // SIMD-ONLY0:       if.end3054:
44636 // SIMD-ONLY0-NEXT:    [[TMP1944:%.*]] = load i32, ptr [[IX]], align 4
44637 // SIMD-ONLY0-NEXT:    store i32 [[TMP1944]], ptr [[IV]], align 4
44638 // SIMD-ONLY0-NEXT:    [[TMP1945:%.*]] = load i32, ptr [[IE]], align 4
44639 // SIMD-ONLY0-NEXT:    [[TMP1946:%.*]] = load i32, ptr [[IX]], align 4
44640 // SIMD-ONLY0-NEXT:    [[CMP3055:%.*]] = icmp eq i32 [[TMP1945]], [[TMP1946]]
44641 // SIMD-ONLY0-NEXT:    br i1 [[CMP3055]], label [[IF_THEN3057:%.*]], label [[IF_END3058:%.*]]
44642 // SIMD-ONLY0:       if.then3057:
44643 // SIMD-ONLY0-NEXT:    [[TMP1947:%.*]] = load i32, ptr [[ID]], align 4
44644 // SIMD-ONLY0-NEXT:    store i32 [[TMP1947]], ptr [[IX]], align 4
44645 // SIMD-ONLY0-NEXT:    br label [[IF_END3058]]
44646 // SIMD-ONLY0:       if.end3058:
44647 // SIMD-ONLY0-NEXT:    [[TMP1948:%.*]] = load i32, ptr [[IE]], align 4
44648 // SIMD-ONLY0-NEXT:    [[TMP1949:%.*]] = load i32, ptr [[IX]], align 4
44649 // SIMD-ONLY0-NEXT:    [[CMP3059:%.*]] = icmp sgt i32 [[TMP1948]], [[TMP1949]]
44650 // SIMD-ONLY0-NEXT:    br i1 [[CMP3059]], label [[IF_THEN3061:%.*]], label [[IF_END3062:%.*]]
44651 // SIMD-ONLY0:       if.then3061:
44652 // SIMD-ONLY0-NEXT:    [[TMP1950:%.*]] = load i32, ptr [[IE]], align 4
44653 // SIMD-ONLY0-NEXT:    store i32 [[TMP1950]], ptr [[IX]], align 4
44654 // SIMD-ONLY0-NEXT:    br label [[IF_END3062]]
44655 // SIMD-ONLY0:       if.end3062:
44656 // SIMD-ONLY0-NEXT:    [[TMP1951:%.*]] = load i32, ptr [[IX]], align 4
44657 // SIMD-ONLY0-NEXT:    store i32 [[TMP1951]], ptr [[IV]], align 4
44658 // SIMD-ONLY0-NEXT:    [[TMP1952:%.*]] = load i32, ptr [[IX]], align 4
44659 // SIMD-ONLY0-NEXT:    [[TMP1953:%.*]] = load i32, ptr [[IE]], align 4
44660 // SIMD-ONLY0-NEXT:    [[CMP3063:%.*]] = icmp sgt i32 [[TMP1952]], [[TMP1953]]
44661 // SIMD-ONLY0-NEXT:    br i1 [[CMP3063]], label [[IF_THEN3065:%.*]], label [[IF_END3066:%.*]]
44662 // SIMD-ONLY0:       if.then3065:
44663 // SIMD-ONLY0-NEXT:    [[TMP1954:%.*]] = load i32, ptr [[IE]], align 4
44664 // SIMD-ONLY0-NEXT:    store i32 [[TMP1954]], ptr [[IX]], align 4
44665 // SIMD-ONLY0-NEXT:    br label [[IF_END3066]]
44666 // SIMD-ONLY0:       if.end3066:
44667 // SIMD-ONLY0-NEXT:    [[TMP1955:%.*]] = load i32, ptr [[IX]], align 4
44668 // SIMD-ONLY0-NEXT:    store i32 [[TMP1955]], ptr [[IV]], align 4
44669 // SIMD-ONLY0-NEXT:    [[TMP1956:%.*]] = load i32, ptr [[IE]], align 4
44670 // SIMD-ONLY0-NEXT:    [[TMP1957:%.*]] = load i32, ptr [[IX]], align 4
44671 // SIMD-ONLY0-NEXT:    [[CMP3067:%.*]] = icmp slt i32 [[TMP1956]], [[TMP1957]]
44672 // SIMD-ONLY0-NEXT:    br i1 [[CMP3067]], label [[IF_THEN3069:%.*]], label [[IF_END3070:%.*]]
44673 // SIMD-ONLY0:       if.then3069:
44674 // SIMD-ONLY0-NEXT:    [[TMP1958:%.*]] = load i32, ptr [[IE]], align 4
44675 // SIMD-ONLY0-NEXT:    store i32 [[TMP1958]], ptr [[IX]], align 4
44676 // SIMD-ONLY0-NEXT:    br label [[IF_END3070]]
44677 // SIMD-ONLY0:       if.end3070:
44678 // SIMD-ONLY0-NEXT:    [[TMP1959:%.*]] = load i32, ptr [[IX]], align 4
44679 // SIMD-ONLY0-NEXT:    store i32 [[TMP1959]], ptr [[IV]], align 4
44680 // SIMD-ONLY0-NEXT:    [[TMP1960:%.*]] = load i32, ptr [[IX]], align 4
44681 // SIMD-ONLY0-NEXT:    [[TMP1961:%.*]] = load i32, ptr [[IE]], align 4
44682 // SIMD-ONLY0-NEXT:    [[CMP3071:%.*]] = icmp slt i32 [[TMP1960]], [[TMP1961]]
44683 // SIMD-ONLY0-NEXT:    br i1 [[CMP3071]], label [[IF_THEN3073:%.*]], label [[IF_END3074:%.*]]
44684 // SIMD-ONLY0:       if.then3073:
44685 // SIMD-ONLY0-NEXT:    [[TMP1962:%.*]] = load i32, ptr [[IE]], align 4
44686 // SIMD-ONLY0-NEXT:    store i32 [[TMP1962]], ptr [[IX]], align 4
44687 // SIMD-ONLY0-NEXT:    br label [[IF_END3074]]
44688 // SIMD-ONLY0:       if.end3074:
44689 // SIMD-ONLY0-NEXT:    [[TMP1963:%.*]] = load i32, ptr [[IX]], align 4
44690 // SIMD-ONLY0-NEXT:    store i32 [[TMP1963]], ptr [[IV]], align 4
44691 // SIMD-ONLY0-NEXT:    [[TMP1964:%.*]] = load i32, ptr [[IX]], align 4
44692 // SIMD-ONLY0-NEXT:    [[TMP1965:%.*]] = load i32, ptr [[IE]], align 4
44693 // SIMD-ONLY0-NEXT:    [[CMP3075:%.*]] = icmp eq i32 [[TMP1964]], [[TMP1965]]
44694 // SIMD-ONLY0-NEXT:    br i1 [[CMP3075]], label [[IF_THEN3077:%.*]], label [[IF_END3078:%.*]]
44695 // SIMD-ONLY0:       if.then3077:
44696 // SIMD-ONLY0-NEXT:    [[TMP1966:%.*]] = load i32, ptr [[ID]], align 4
44697 // SIMD-ONLY0-NEXT:    store i32 [[TMP1966]], ptr [[IX]], align 4
44698 // SIMD-ONLY0-NEXT:    br label [[IF_END3078]]
44699 // SIMD-ONLY0:       if.end3078:
44700 // SIMD-ONLY0-NEXT:    [[TMP1967:%.*]] = load i32, ptr [[IX]], align 4
44701 // SIMD-ONLY0-NEXT:    store i32 [[TMP1967]], ptr [[IV]], align 4
44702 // SIMD-ONLY0-NEXT:    [[TMP1968:%.*]] = load i32, ptr [[IE]], align 4
44703 // SIMD-ONLY0-NEXT:    [[TMP1969:%.*]] = load i32, ptr [[IX]], align 4
44704 // SIMD-ONLY0-NEXT:    [[CMP3079:%.*]] = icmp eq i32 [[TMP1968]], [[TMP1969]]
44705 // SIMD-ONLY0-NEXT:    br i1 [[CMP3079]], label [[IF_THEN3081:%.*]], label [[IF_END3082:%.*]]
44706 // SIMD-ONLY0:       if.then3081:
44707 // SIMD-ONLY0-NEXT:    [[TMP1970:%.*]] = load i32, ptr [[ID]], align 4
44708 // SIMD-ONLY0-NEXT:    store i32 [[TMP1970]], ptr [[IX]], align 4
44709 // SIMD-ONLY0-NEXT:    br label [[IF_END3082]]
44710 // SIMD-ONLY0:       if.end3082:
44711 // SIMD-ONLY0-NEXT:    [[TMP1971:%.*]] = load i32, ptr [[IX]], align 4
44712 // SIMD-ONLY0-NEXT:    store i32 [[TMP1971]], ptr [[IV]], align 4
44713 // SIMD-ONLY0-NEXT:    [[TMP1972:%.*]] = load i32, ptr [[IX]], align 4
44714 // SIMD-ONLY0-NEXT:    [[TMP1973:%.*]] = load i32, ptr [[IE]], align 4
44715 // SIMD-ONLY0-NEXT:    [[CMP3083:%.*]] = icmp eq i32 [[TMP1972]], [[TMP1973]]
44716 // SIMD-ONLY0-NEXT:    br i1 [[CMP3083]], label [[IF_THEN3085:%.*]], label [[IF_ELSE3086:%.*]]
44717 // SIMD-ONLY0:       if.then3085:
44718 // SIMD-ONLY0-NEXT:    [[TMP1974:%.*]] = load i32, ptr [[ID]], align 4
44719 // SIMD-ONLY0-NEXT:    store i32 [[TMP1974]], ptr [[IX]], align 4
44720 // SIMD-ONLY0-NEXT:    br label [[IF_END3087:%.*]]
44721 // SIMD-ONLY0:       if.else3086:
44722 // SIMD-ONLY0-NEXT:    [[TMP1975:%.*]] = load i32, ptr [[IX]], align 4
44723 // SIMD-ONLY0-NEXT:    store i32 [[TMP1975]], ptr [[IV]], align 4
44724 // SIMD-ONLY0-NEXT:    br label [[IF_END3087]]
44725 // SIMD-ONLY0:       if.end3087:
44726 // SIMD-ONLY0-NEXT:    [[TMP1976:%.*]] = load i32, ptr [[IE]], align 4
44727 // SIMD-ONLY0-NEXT:    [[TMP1977:%.*]] = load i32, ptr [[IX]], align 4
44728 // SIMD-ONLY0-NEXT:    [[CMP3088:%.*]] = icmp eq i32 [[TMP1976]], [[TMP1977]]
44729 // SIMD-ONLY0-NEXT:    br i1 [[CMP3088]], label [[IF_THEN3090:%.*]], label [[IF_ELSE3091:%.*]]
44730 // SIMD-ONLY0:       if.then3090:
44731 // SIMD-ONLY0-NEXT:    [[TMP1978:%.*]] = load i32, ptr [[ID]], align 4
44732 // SIMD-ONLY0-NEXT:    store i32 [[TMP1978]], ptr [[IX]], align 4
44733 // SIMD-ONLY0-NEXT:    br label [[IF_END3092:%.*]]
44734 // SIMD-ONLY0:       if.else3091:
44735 // SIMD-ONLY0-NEXT:    [[TMP1979:%.*]] = load i32, ptr [[IX]], align 4
44736 // SIMD-ONLY0-NEXT:    store i32 [[TMP1979]], ptr [[IV]], align 4
44737 // SIMD-ONLY0-NEXT:    br label [[IF_END3092]]
44738 // SIMD-ONLY0:       if.end3092:
44739 // SIMD-ONLY0-NEXT:    [[TMP1980:%.*]] = load i32, ptr [[IX]], align 4
44740 // SIMD-ONLY0-NEXT:    [[TMP1981:%.*]] = load i32, ptr [[IE]], align 4
44741 // SIMD-ONLY0-NEXT:    [[CMP3093:%.*]] = icmp eq i32 [[TMP1980]], [[TMP1981]]
44742 // SIMD-ONLY0-NEXT:    [[CONV3094:%.*]] = zext i1 [[CMP3093]] to i32
44743 // SIMD-ONLY0-NEXT:    store i32 [[CONV3094]], ptr [[IR]], align 4
44744 // SIMD-ONLY0-NEXT:    [[TMP1982:%.*]] = load i32, ptr [[IR]], align 4
44745 // SIMD-ONLY0-NEXT:    [[TOBOOL3095:%.*]] = icmp ne i32 [[TMP1982]], 0
44746 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3095]], label [[IF_THEN3096:%.*]], label [[IF_END3097:%.*]]
44747 // SIMD-ONLY0:       if.then3096:
44748 // SIMD-ONLY0-NEXT:    [[TMP1983:%.*]] = load i32, ptr [[ID]], align 4
44749 // SIMD-ONLY0-NEXT:    store i32 [[TMP1983]], ptr [[IX]], align 4
44750 // SIMD-ONLY0-NEXT:    br label [[IF_END3097]]
44751 // SIMD-ONLY0:       if.end3097:
44752 // SIMD-ONLY0-NEXT:    [[TMP1984:%.*]] = load i32, ptr [[IE]], align 4
44753 // SIMD-ONLY0-NEXT:    [[TMP1985:%.*]] = load i32, ptr [[IX]], align 4
44754 // SIMD-ONLY0-NEXT:    [[CMP3098:%.*]] = icmp eq i32 [[TMP1984]], [[TMP1985]]
44755 // SIMD-ONLY0-NEXT:    [[CONV3099:%.*]] = zext i1 [[CMP3098]] to i32
44756 // SIMD-ONLY0-NEXT:    store i32 [[CONV3099]], ptr [[IR]], align 4
44757 // SIMD-ONLY0-NEXT:    [[TMP1986:%.*]] = load i32, ptr [[IR]], align 4
44758 // SIMD-ONLY0-NEXT:    [[TOBOOL3100:%.*]] = icmp ne i32 [[TMP1986]], 0
44759 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3100]], label [[IF_THEN3101:%.*]], label [[IF_END3102:%.*]]
44760 // SIMD-ONLY0:       if.then3101:
44761 // SIMD-ONLY0-NEXT:    [[TMP1987:%.*]] = load i32, ptr [[ID]], align 4
44762 // SIMD-ONLY0-NEXT:    store i32 [[TMP1987]], ptr [[IX]], align 4
44763 // SIMD-ONLY0-NEXT:    br label [[IF_END3102]]
44764 // SIMD-ONLY0:       if.end3102:
44765 // SIMD-ONLY0-NEXT:    [[TMP1988:%.*]] = load i32, ptr [[IX]], align 4
44766 // SIMD-ONLY0-NEXT:    [[TMP1989:%.*]] = load i32, ptr [[IE]], align 4
44767 // SIMD-ONLY0-NEXT:    [[CMP3103:%.*]] = icmp eq i32 [[TMP1988]], [[TMP1989]]
44768 // SIMD-ONLY0-NEXT:    [[CONV3104:%.*]] = zext i1 [[CMP3103]] to i32
44769 // SIMD-ONLY0-NEXT:    store i32 [[CONV3104]], ptr [[IR]], align 4
44770 // SIMD-ONLY0-NEXT:    [[TMP1990:%.*]] = load i32, ptr [[IR]], align 4
44771 // SIMD-ONLY0-NEXT:    [[TOBOOL3105:%.*]] = icmp ne i32 [[TMP1990]], 0
44772 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3105]], label [[IF_THEN3106:%.*]], label [[IF_ELSE3107:%.*]]
44773 // SIMD-ONLY0:       if.then3106:
44774 // SIMD-ONLY0-NEXT:    [[TMP1991:%.*]] = load i32, ptr [[ID]], align 4
44775 // SIMD-ONLY0-NEXT:    store i32 [[TMP1991]], ptr [[IX]], align 4
44776 // SIMD-ONLY0-NEXT:    br label [[IF_END3108:%.*]]
44777 // SIMD-ONLY0:       if.else3107:
44778 // SIMD-ONLY0-NEXT:    [[TMP1992:%.*]] = load i32, ptr [[IX]], align 4
44779 // SIMD-ONLY0-NEXT:    store i32 [[TMP1992]], ptr [[IV]], align 4
44780 // SIMD-ONLY0-NEXT:    br label [[IF_END3108]]
44781 // SIMD-ONLY0:       if.end3108:
44782 // SIMD-ONLY0-NEXT:    [[TMP1993:%.*]] = load i32, ptr [[IE]], align 4
44783 // SIMD-ONLY0-NEXT:    [[TMP1994:%.*]] = load i32, ptr [[IX]], align 4
44784 // SIMD-ONLY0-NEXT:    [[CMP3109:%.*]] = icmp eq i32 [[TMP1993]], [[TMP1994]]
44785 // SIMD-ONLY0-NEXT:    [[CONV3110:%.*]] = zext i1 [[CMP3109]] to i32
44786 // SIMD-ONLY0-NEXT:    store i32 [[CONV3110]], ptr [[IR]], align 4
44787 // SIMD-ONLY0-NEXT:    [[TMP1995:%.*]] = load i32, ptr [[IR]], align 4
44788 // SIMD-ONLY0-NEXT:    [[TOBOOL3111:%.*]] = icmp ne i32 [[TMP1995]], 0
44789 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3111]], label [[IF_THEN3112:%.*]], label [[IF_ELSE3113:%.*]]
44790 // SIMD-ONLY0:       if.then3112:
44791 // SIMD-ONLY0-NEXT:    [[TMP1996:%.*]] = load i32, ptr [[ID]], align 4
44792 // SIMD-ONLY0-NEXT:    store i32 [[TMP1996]], ptr [[IX]], align 4
44793 // SIMD-ONLY0-NEXT:    br label [[IF_END3114:%.*]]
44794 // SIMD-ONLY0:       if.else3113:
44795 // SIMD-ONLY0-NEXT:    [[TMP1997:%.*]] = load i32, ptr [[IX]], align 4
44796 // SIMD-ONLY0-NEXT:    store i32 [[TMP1997]], ptr [[IV]], align 4
44797 // SIMD-ONLY0-NEXT:    br label [[IF_END3114]]
44798 // SIMD-ONLY0:       if.end3114:
44799 // SIMD-ONLY0-NEXT:    [[TMP1998:%.*]] = load i32, ptr [[IX]], align 4
44800 // SIMD-ONLY0-NEXT:    store i32 [[TMP1998]], ptr [[IV]], align 4
44801 // SIMD-ONLY0-NEXT:    [[TMP1999:%.*]] = load i32, ptr [[IE]], align 4
44802 // SIMD-ONLY0-NEXT:    [[TMP2000:%.*]] = load i32, ptr [[IX]], align 4
44803 // SIMD-ONLY0-NEXT:    [[CMP3115:%.*]] = icmp sgt i32 [[TMP1999]], [[TMP2000]]
44804 // SIMD-ONLY0-NEXT:    br i1 [[CMP3115]], label [[IF_THEN3117:%.*]], label [[IF_END3118:%.*]]
44805 // SIMD-ONLY0:       if.then3117:
44806 // SIMD-ONLY0-NEXT:    [[TMP2001:%.*]] = load i32, ptr [[IE]], align 4
44807 // SIMD-ONLY0-NEXT:    store i32 [[TMP2001]], ptr [[IX]], align 4
44808 // SIMD-ONLY0-NEXT:    br label [[IF_END3118]]
44809 // SIMD-ONLY0:       if.end3118:
44810 // SIMD-ONLY0-NEXT:    [[TMP2002:%.*]] = load i32, ptr [[IX]], align 4
44811 // SIMD-ONLY0-NEXT:    store i32 [[TMP2002]], ptr [[IV]], align 4
44812 // SIMD-ONLY0-NEXT:    [[TMP2003:%.*]] = load i32, ptr [[IX]], align 4
44813 // SIMD-ONLY0-NEXT:    [[TMP2004:%.*]] = load i32, ptr [[IE]], align 4
44814 // SIMD-ONLY0-NEXT:    [[CMP3119:%.*]] = icmp sgt i32 [[TMP2003]], [[TMP2004]]
44815 // SIMD-ONLY0-NEXT:    br i1 [[CMP3119]], label [[IF_THEN3121:%.*]], label [[IF_END3122:%.*]]
44816 // SIMD-ONLY0:       if.then3121:
44817 // SIMD-ONLY0-NEXT:    [[TMP2005:%.*]] = load i32, ptr [[IE]], align 4
44818 // SIMD-ONLY0-NEXT:    store i32 [[TMP2005]], ptr [[IX]], align 4
44819 // SIMD-ONLY0-NEXT:    br label [[IF_END3122]]
44820 // SIMD-ONLY0:       if.end3122:
44821 // SIMD-ONLY0-NEXT:    [[TMP2006:%.*]] = load i32, ptr [[IX]], align 4
44822 // SIMD-ONLY0-NEXT:    store i32 [[TMP2006]], ptr [[IV]], align 4
44823 // SIMD-ONLY0-NEXT:    [[TMP2007:%.*]] = load i32, ptr [[IE]], align 4
44824 // SIMD-ONLY0-NEXT:    [[TMP2008:%.*]] = load i32, ptr [[IX]], align 4
44825 // SIMD-ONLY0-NEXT:    [[CMP3123:%.*]] = icmp slt i32 [[TMP2007]], [[TMP2008]]
44826 // SIMD-ONLY0-NEXT:    br i1 [[CMP3123]], label [[IF_THEN3125:%.*]], label [[IF_END3126:%.*]]
44827 // SIMD-ONLY0:       if.then3125:
44828 // SIMD-ONLY0-NEXT:    [[TMP2009:%.*]] = load i32, ptr [[IE]], align 4
44829 // SIMD-ONLY0-NEXT:    store i32 [[TMP2009]], ptr [[IX]], align 4
44830 // SIMD-ONLY0-NEXT:    br label [[IF_END3126]]
44831 // SIMD-ONLY0:       if.end3126:
44832 // SIMD-ONLY0-NEXT:    [[TMP2010:%.*]] = load i32, ptr [[IX]], align 4
44833 // SIMD-ONLY0-NEXT:    store i32 [[TMP2010]], ptr [[IV]], align 4
44834 // SIMD-ONLY0-NEXT:    [[TMP2011:%.*]] = load i32, ptr [[IX]], align 4
44835 // SIMD-ONLY0-NEXT:    [[TMP2012:%.*]] = load i32, ptr [[IE]], align 4
44836 // SIMD-ONLY0-NEXT:    [[CMP3127:%.*]] = icmp slt i32 [[TMP2011]], [[TMP2012]]
44837 // SIMD-ONLY0-NEXT:    br i1 [[CMP3127]], label [[IF_THEN3129:%.*]], label [[IF_END3130:%.*]]
44838 // SIMD-ONLY0:       if.then3129:
44839 // SIMD-ONLY0-NEXT:    [[TMP2013:%.*]] = load i32, ptr [[IE]], align 4
44840 // SIMD-ONLY0-NEXT:    store i32 [[TMP2013]], ptr [[IX]], align 4
44841 // SIMD-ONLY0-NEXT:    br label [[IF_END3130]]
44842 // SIMD-ONLY0:       if.end3130:
44843 // SIMD-ONLY0-NEXT:    [[TMP2014:%.*]] = load i32, ptr [[IX]], align 4
44844 // SIMD-ONLY0-NEXT:    store i32 [[TMP2014]], ptr [[IV]], align 4
44845 // SIMD-ONLY0-NEXT:    [[TMP2015:%.*]] = load i32, ptr [[IX]], align 4
44846 // SIMD-ONLY0-NEXT:    [[TMP2016:%.*]] = load i32, ptr [[IE]], align 4
44847 // SIMD-ONLY0-NEXT:    [[CMP3131:%.*]] = icmp eq i32 [[TMP2015]], [[TMP2016]]
44848 // SIMD-ONLY0-NEXT:    br i1 [[CMP3131]], label [[IF_THEN3133:%.*]], label [[IF_END3134:%.*]]
44849 // SIMD-ONLY0:       if.then3133:
44850 // SIMD-ONLY0-NEXT:    [[TMP2017:%.*]] = load i32, ptr [[ID]], align 4
44851 // SIMD-ONLY0-NEXT:    store i32 [[TMP2017]], ptr [[IX]], align 4
44852 // SIMD-ONLY0-NEXT:    br label [[IF_END3134]]
44853 // SIMD-ONLY0:       if.end3134:
44854 // SIMD-ONLY0-NEXT:    [[TMP2018:%.*]] = load i32, ptr [[IX]], align 4
44855 // SIMD-ONLY0-NEXT:    store i32 [[TMP2018]], ptr [[IV]], align 4
44856 // SIMD-ONLY0-NEXT:    [[TMP2019:%.*]] = load i32, ptr [[IE]], align 4
44857 // SIMD-ONLY0-NEXT:    [[TMP2020:%.*]] = load i32, ptr [[IX]], align 4
44858 // SIMD-ONLY0-NEXT:    [[CMP3135:%.*]] = icmp eq i32 [[TMP2019]], [[TMP2020]]
44859 // SIMD-ONLY0-NEXT:    br i1 [[CMP3135]], label [[IF_THEN3137:%.*]], label [[IF_END3138:%.*]]
44860 // SIMD-ONLY0:       if.then3137:
44861 // SIMD-ONLY0-NEXT:    [[TMP2021:%.*]] = load i32, ptr [[ID]], align 4
44862 // SIMD-ONLY0-NEXT:    store i32 [[TMP2021]], ptr [[IX]], align 4
44863 // SIMD-ONLY0-NEXT:    br label [[IF_END3138]]
44864 // SIMD-ONLY0:       if.end3138:
44865 // SIMD-ONLY0-NEXT:    [[TMP2022:%.*]] = load i32, ptr [[IE]], align 4
44866 // SIMD-ONLY0-NEXT:    [[TMP2023:%.*]] = load i32, ptr [[IX]], align 4
44867 // SIMD-ONLY0-NEXT:    [[CMP3139:%.*]] = icmp sgt i32 [[TMP2022]], [[TMP2023]]
44868 // SIMD-ONLY0-NEXT:    br i1 [[CMP3139]], label [[IF_THEN3141:%.*]], label [[IF_END3142:%.*]]
44869 // SIMD-ONLY0:       if.then3141:
44870 // SIMD-ONLY0-NEXT:    [[TMP2024:%.*]] = load i32, ptr [[IE]], align 4
44871 // SIMD-ONLY0-NEXT:    store i32 [[TMP2024]], ptr [[IX]], align 4
44872 // SIMD-ONLY0-NEXT:    br label [[IF_END3142]]
44873 // SIMD-ONLY0:       if.end3142:
44874 // SIMD-ONLY0-NEXT:    [[TMP2025:%.*]] = load i32, ptr [[IX]], align 4
44875 // SIMD-ONLY0-NEXT:    store i32 [[TMP2025]], ptr [[IV]], align 4
44876 // SIMD-ONLY0-NEXT:    [[TMP2026:%.*]] = load i32, ptr [[IX]], align 4
44877 // SIMD-ONLY0-NEXT:    [[TMP2027:%.*]] = load i32, ptr [[IE]], align 4
44878 // SIMD-ONLY0-NEXT:    [[CMP3143:%.*]] = icmp sgt i32 [[TMP2026]], [[TMP2027]]
44879 // SIMD-ONLY0-NEXT:    br i1 [[CMP3143]], label [[IF_THEN3145:%.*]], label [[IF_END3146:%.*]]
44880 // SIMD-ONLY0:       if.then3145:
44881 // SIMD-ONLY0-NEXT:    [[TMP2028:%.*]] = load i32, ptr [[IE]], align 4
44882 // SIMD-ONLY0-NEXT:    store i32 [[TMP2028]], ptr [[IX]], align 4
44883 // SIMD-ONLY0-NEXT:    br label [[IF_END3146]]
44884 // SIMD-ONLY0:       if.end3146:
44885 // SIMD-ONLY0-NEXT:    [[TMP2029:%.*]] = load i32, ptr [[IX]], align 4
44886 // SIMD-ONLY0-NEXT:    store i32 [[TMP2029]], ptr [[IV]], align 4
44887 // SIMD-ONLY0-NEXT:    [[TMP2030:%.*]] = load i32, ptr [[IE]], align 4
44888 // SIMD-ONLY0-NEXT:    [[TMP2031:%.*]] = load i32, ptr [[IX]], align 4
44889 // SIMD-ONLY0-NEXT:    [[CMP3147:%.*]] = icmp slt i32 [[TMP2030]], [[TMP2031]]
44890 // SIMD-ONLY0-NEXT:    br i1 [[CMP3147]], label [[IF_THEN3149:%.*]], label [[IF_END3150:%.*]]
44891 // SIMD-ONLY0:       if.then3149:
44892 // SIMD-ONLY0-NEXT:    [[TMP2032:%.*]] = load i32, ptr [[IE]], align 4
44893 // SIMD-ONLY0-NEXT:    store i32 [[TMP2032]], ptr [[IX]], align 4
44894 // SIMD-ONLY0-NEXT:    br label [[IF_END3150]]
44895 // SIMD-ONLY0:       if.end3150:
44896 // SIMD-ONLY0-NEXT:    [[TMP2033:%.*]] = load i32, ptr [[IX]], align 4
44897 // SIMD-ONLY0-NEXT:    store i32 [[TMP2033]], ptr [[IV]], align 4
44898 // SIMD-ONLY0-NEXT:    [[TMP2034:%.*]] = load i32, ptr [[IX]], align 4
44899 // SIMD-ONLY0-NEXT:    [[TMP2035:%.*]] = load i32, ptr [[IE]], align 4
44900 // SIMD-ONLY0-NEXT:    [[CMP3151:%.*]] = icmp slt i32 [[TMP2034]], [[TMP2035]]
44901 // SIMD-ONLY0-NEXT:    br i1 [[CMP3151]], label [[IF_THEN3153:%.*]], label [[IF_END3154:%.*]]
44902 // SIMD-ONLY0:       if.then3153:
44903 // SIMD-ONLY0-NEXT:    [[TMP2036:%.*]] = load i32, ptr [[IE]], align 4
44904 // SIMD-ONLY0-NEXT:    store i32 [[TMP2036]], ptr [[IX]], align 4
44905 // SIMD-ONLY0-NEXT:    br label [[IF_END3154]]
44906 // SIMD-ONLY0:       if.end3154:
44907 // SIMD-ONLY0-NEXT:    [[TMP2037:%.*]] = load i32, ptr [[IX]], align 4
44908 // SIMD-ONLY0-NEXT:    store i32 [[TMP2037]], ptr [[IV]], align 4
44909 // SIMD-ONLY0-NEXT:    [[TMP2038:%.*]] = load i32, ptr [[IX]], align 4
44910 // SIMD-ONLY0-NEXT:    [[TMP2039:%.*]] = load i32, ptr [[IE]], align 4
44911 // SIMD-ONLY0-NEXT:    [[CMP3155:%.*]] = icmp eq i32 [[TMP2038]], [[TMP2039]]
44912 // SIMD-ONLY0-NEXT:    br i1 [[CMP3155]], label [[IF_THEN3157:%.*]], label [[IF_END3158:%.*]]
44913 // SIMD-ONLY0:       if.then3157:
44914 // SIMD-ONLY0-NEXT:    [[TMP2040:%.*]] = load i32, ptr [[ID]], align 4
44915 // SIMD-ONLY0-NEXT:    store i32 [[TMP2040]], ptr [[IX]], align 4
44916 // SIMD-ONLY0-NEXT:    br label [[IF_END3158]]
44917 // SIMD-ONLY0:       if.end3158:
44918 // SIMD-ONLY0-NEXT:    [[TMP2041:%.*]] = load i32, ptr [[IX]], align 4
44919 // SIMD-ONLY0-NEXT:    store i32 [[TMP2041]], ptr [[IV]], align 4
44920 // SIMD-ONLY0-NEXT:    [[TMP2042:%.*]] = load i32, ptr [[IE]], align 4
44921 // SIMD-ONLY0-NEXT:    [[TMP2043:%.*]] = load i32, ptr [[IX]], align 4
44922 // SIMD-ONLY0-NEXT:    [[CMP3159:%.*]] = icmp eq i32 [[TMP2042]], [[TMP2043]]
44923 // SIMD-ONLY0-NEXT:    br i1 [[CMP3159]], label [[IF_THEN3161:%.*]], label [[IF_END3162:%.*]]
44924 // SIMD-ONLY0:       if.then3161:
44925 // SIMD-ONLY0-NEXT:    [[TMP2044:%.*]] = load i32, ptr [[ID]], align 4
44926 // SIMD-ONLY0-NEXT:    store i32 [[TMP2044]], ptr [[IX]], align 4
44927 // SIMD-ONLY0-NEXT:    br label [[IF_END3162]]
44928 // SIMD-ONLY0:       if.end3162:
44929 // SIMD-ONLY0-NEXT:    [[TMP2045:%.*]] = load i32, ptr [[IX]], align 4
44930 // SIMD-ONLY0-NEXT:    store i32 [[TMP2045]], ptr [[IV]], align 4
44931 // SIMD-ONLY0-NEXT:    [[TMP2046:%.*]] = load i32, ptr [[IX]], align 4
44932 // SIMD-ONLY0-NEXT:    [[TMP2047:%.*]] = load i32, ptr [[IE]], align 4
44933 // SIMD-ONLY0-NEXT:    [[CMP3163:%.*]] = icmp eq i32 [[TMP2046]], [[TMP2047]]
44934 // SIMD-ONLY0-NEXT:    br i1 [[CMP3163]], label [[IF_THEN3165:%.*]], label [[IF_ELSE3166:%.*]]
44935 // SIMD-ONLY0:       if.then3165:
44936 // SIMD-ONLY0-NEXT:    [[TMP2048:%.*]] = load i32, ptr [[ID]], align 4
44937 // SIMD-ONLY0-NEXT:    store i32 [[TMP2048]], ptr [[IX]], align 4
44938 // SIMD-ONLY0-NEXT:    br label [[IF_END3167:%.*]]
44939 // SIMD-ONLY0:       if.else3166:
44940 // SIMD-ONLY0-NEXT:    [[TMP2049:%.*]] = load i32, ptr [[IX]], align 4
44941 // SIMD-ONLY0-NEXT:    store i32 [[TMP2049]], ptr [[IV]], align 4
44942 // SIMD-ONLY0-NEXT:    br label [[IF_END3167]]
44943 // SIMD-ONLY0:       if.end3167:
44944 // SIMD-ONLY0-NEXT:    [[TMP2050:%.*]] = load i32, ptr [[IE]], align 4
44945 // SIMD-ONLY0-NEXT:    [[TMP2051:%.*]] = load i32, ptr [[IX]], align 4
44946 // SIMD-ONLY0-NEXT:    [[CMP3168:%.*]] = icmp eq i32 [[TMP2050]], [[TMP2051]]
44947 // SIMD-ONLY0-NEXT:    br i1 [[CMP3168]], label [[IF_THEN3170:%.*]], label [[IF_ELSE3171:%.*]]
44948 // SIMD-ONLY0:       if.then3170:
44949 // SIMD-ONLY0-NEXT:    [[TMP2052:%.*]] = load i32, ptr [[ID]], align 4
44950 // SIMD-ONLY0-NEXT:    store i32 [[TMP2052]], ptr [[IX]], align 4
44951 // SIMD-ONLY0-NEXT:    br label [[IF_END3172:%.*]]
44952 // SIMD-ONLY0:       if.else3171:
44953 // SIMD-ONLY0-NEXT:    [[TMP2053:%.*]] = load i32, ptr [[IX]], align 4
44954 // SIMD-ONLY0-NEXT:    store i32 [[TMP2053]], ptr [[IV]], align 4
44955 // SIMD-ONLY0-NEXT:    br label [[IF_END3172]]
44956 // SIMD-ONLY0:       if.end3172:
44957 // SIMD-ONLY0-NEXT:    [[TMP2054:%.*]] = load i32, ptr [[IX]], align 4
44958 // SIMD-ONLY0-NEXT:    [[TMP2055:%.*]] = load i32, ptr [[IE]], align 4
44959 // SIMD-ONLY0-NEXT:    [[CMP3173:%.*]] = icmp eq i32 [[TMP2054]], [[TMP2055]]
44960 // SIMD-ONLY0-NEXT:    [[CONV3174:%.*]] = zext i1 [[CMP3173]] to i32
44961 // SIMD-ONLY0-NEXT:    store i32 [[CONV3174]], ptr [[IR]], align 4
44962 // SIMD-ONLY0-NEXT:    [[TMP2056:%.*]] = load i32, ptr [[IR]], align 4
44963 // SIMD-ONLY0-NEXT:    [[TOBOOL3175:%.*]] = icmp ne i32 [[TMP2056]], 0
44964 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3175]], label [[IF_THEN3176:%.*]], label [[IF_END3177:%.*]]
44965 // SIMD-ONLY0:       if.then3176:
44966 // SIMD-ONLY0-NEXT:    [[TMP2057:%.*]] = load i32, ptr [[ID]], align 4
44967 // SIMD-ONLY0-NEXT:    store i32 [[TMP2057]], ptr [[IX]], align 4
44968 // SIMD-ONLY0-NEXT:    br label [[IF_END3177]]
44969 // SIMD-ONLY0:       if.end3177:
44970 // SIMD-ONLY0-NEXT:    [[TMP2058:%.*]] = load i32, ptr [[IE]], align 4
44971 // SIMD-ONLY0-NEXT:    [[TMP2059:%.*]] = load i32, ptr [[IX]], align 4
44972 // SIMD-ONLY0-NEXT:    [[CMP3178:%.*]] = icmp eq i32 [[TMP2058]], [[TMP2059]]
44973 // SIMD-ONLY0-NEXT:    [[CONV3179:%.*]] = zext i1 [[CMP3178]] to i32
44974 // SIMD-ONLY0-NEXT:    store i32 [[CONV3179]], ptr [[IR]], align 4
44975 // SIMD-ONLY0-NEXT:    [[TMP2060:%.*]] = load i32, ptr [[IR]], align 4
44976 // SIMD-ONLY0-NEXT:    [[TOBOOL3180:%.*]] = icmp ne i32 [[TMP2060]], 0
44977 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3180]], label [[IF_THEN3181:%.*]], label [[IF_END3182:%.*]]
44978 // SIMD-ONLY0:       if.then3181:
44979 // SIMD-ONLY0-NEXT:    [[TMP2061:%.*]] = load i32, ptr [[ID]], align 4
44980 // SIMD-ONLY0-NEXT:    store i32 [[TMP2061]], ptr [[IX]], align 4
44981 // SIMD-ONLY0-NEXT:    br label [[IF_END3182]]
44982 // SIMD-ONLY0:       if.end3182:
44983 // SIMD-ONLY0-NEXT:    [[TMP2062:%.*]] = load i32, ptr [[IX]], align 4
44984 // SIMD-ONLY0-NEXT:    [[TMP2063:%.*]] = load i32, ptr [[IE]], align 4
44985 // SIMD-ONLY0-NEXT:    [[CMP3183:%.*]] = icmp eq i32 [[TMP2062]], [[TMP2063]]
44986 // SIMD-ONLY0-NEXT:    [[CONV3184:%.*]] = zext i1 [[CMP3183]] to i32
44987 // SIMD-ONLY0-NEXT:    store i32 [[CONV3184]], ptr [[IR]], align 4
44988 // SIMD-ONLY0-NEXT:    [[TMP2064:%.*]] = load i32, ptr [[IR]], align 4
44989 // SIMD-ONLY0-NEXT:    [[TOBOOL3185:%.*]] = icmp ne i32 [[TMP2064]], 0
44990 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3185]], label [[IF_THEN3186:%.*]], label [[IF_ELSE3187:%.*]]
44991 // SIMD-ONLY0:       if.then3186:
44992 // SIMD-ONLY0-NEXT:    [[TMP2065:%.*]] = load i32, ptr [[ID]], align 4
44993 // SIMD-ONLY0-NEXT:    store i32 [[TMP2065]], ptr [[IX]], align 4
44994 // SIMD-ONLY0-NEXT:    br label [[IF_END3188:%.*]]
44995 // SIMD-ONLY0:       if.else3187:
44996 // SIMD-ONLY0-NEXT:    [[TMP2066:%.*]] = load i32, ptr [[IX]], align 4
44997 // SIMD-ONLY0-NEXT:    store i32 [[TMP2066]], ptr [[IV]], align 4
44998 // SIMD-ONLY0-NEXT:    br label [[IF_END3188]]
44999 // SIMD-ONLY0:       if.end3188:
45000 // SIMD-ONLY0-NEXT:    [[TMP2067:%.*]] = load i32, ptr [[IE]], align 4
45001 // SIMD-ONLY0-NEXT:    [[TMP2068:%.*]] = load i32, ptr [[IX]], align 4
45002 // SIMD-ONLY0-NEXT:    [[CMP3189:%.*]] = icmp eq i32 [[TMP2067]], [[TMP2068]]
45003 // SIMD-ONLY0-NEXT:    [[CONV3190:%.*]] = zext i1 [[CMP3189]] to i32
45004 // SIMD-ONLY0-NEXT:    store i32 [[CONV3190]], ptr [[IR]], align 4
45005 // SIMD-ONLY0-NEXT:    [[TMP2069:%.*]] = load i32, ptr [[IR]], align 4
45006 // SIMD-ONLY0-NEXT:    [[TOBOOL3191:%.*]] = icmp ne i32 [[TMP2069]], 0
45007 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3191]], label [[IF_THEN3192:%.*]], label [[IF_ELSE3193:%.*]]
45008 // SIMD-ONLY0:       if.then3192:
45009 // SIMD-ONLY0-NEXT:    [[TMP2070:%.*]] = load i32, ptr [[ID]], align 4
45010 // SIMD-ONLY0-NEXT:    store i32 [[TMP2070]], ptr [[IX]], align 4
45011 // SIMD-ONLY0-NEXT:    br label [[IF_END3194:%.*]]
45012 // SIMD-ONLY0:       if.else3193:
45013 // SIMD-ONLY0-NEXT:    [[TMP2071:%.*]] = load i32, ptr [[IX]], align 4
45014 // SIMD-ONLY0-NEXT:    store i32 [[TMP2071]], ptr [[IV]], align 4
45015 // SIMD-ONLY0-NEXT:    br label [[IF_END3194]]
45016 // SIMD-ONLY0:       if.end3194:
45017 // SIMD-ONLY0-NEXT:    [[TMP2072:%.*]] = load i32, ptr [[IX]], align 4
45018 // SIMD-ONLY0-NEXT:    store i32 [[TMP2072]], ptr [[IV]], align 4
45019 // SIMD-ONLY0-NEXT:    [[TMP2073:%.*]] = load i32, ptr [[IE]], align 4
45020 // SIMD-ONLY0-NEXT:    [[TMP2074:%.*]] = load i32, ptr [[IX]], align 4
45021 // SIMD-ONLY0-NEXT:    [[CMP3195:%.*]] = icmp sgt i32 [[TMP2073]], [[TMP2074]]
45022 // SIMD-ONLY0-NEXT:    br i1 [[CMP3195]], label [[IF_THEN3197:%.*]], label [[IF_END3198:%.*]]
45023 // SIMD-ONLY0:       if.then3197:
45024 // SIMD-ONLY0-NEXT:    [[TMP2075:%.*]] = load i32, ptr [[IE]], align 4
45025 // SIMD-ONLY0-NEXT:    store i32 [[TMP2075]], ptr [[IX]], align 4
45026 // SIMD-ONLY0-NEXT:    br label [[IF_END3198]]
45027 // SIMD-ONLY0:       if.end3198:
45028 // SIMD-ONLY0-NEXT:    [[TMP2076:%.*]] = load i32, ptr [[IX]], align 4
45029 // SIMD-ONLY0-NEXT:    store i32 [[TMP2076]], ptr [[IV]], align 4
45030 // SIMD-ONLY0-NEXT:    [[TMP2077:%.*]] = load i32, ptr [[IX]], align 4
45031 // SIMD-ONLY0-NEXT:    [[TMP2078:%.*]] = load i32, ptr [[IE]], align 4
45032 // SIMD-ONLY0-NEXT:    [[CMP3199:%.*]] = icmp sgt i32 [[TMP2077]], [[TMP2078]]
45033 // SIMD-ONLY0-NEXT:    br i1 [[CMP3199]], label [[IF_THEN3201:%.*]], label [[IF_END3202:%.*]]
45034 // SIMD-ONLY0:       if.then3201:
45035 // SIMD-ONLY0-NEXT:    [[TMP2079:%.*]] = load i32, ptr [[IE]], align 4
45036 // SIMD-ONLY0-NEXT:    store i32 [[TMP2079]], ptr [[IX]], align 4
45037 // SIMD-ONLY0-NEXT:    br label [[IF_END3202]]
45038 // SIMD-ONLY0:       if.end3202:
45039 // SIMD-ONLY0-NEXT:    [[TMP2080:%.*]] = load i32, ptr [[IX]], align 4
45040 // SIMD-ONLY0-NEXT:    store i32 [[TMP2080]], ptr [[IV]], align 4
45041 // SIMD-ONLY0-NEXT:    [[TMP2081:%.*]] = load i32, ptr [[IE]], align 4
45042 // SIMD-ONLY0-NEXT:    [[TMP2082:%.*]] = load i32, ptr [[IX]], align 4
45043 // SIMD-ONLY0-NEXT:    [[CMP3203:%.*]] = icmp slt i32 [[TMP2081]], [[TMP2082]]
45044 // SIMD-ONLY0-NEXT:    br i1 [[CMP3203]], label [[IF_THEN3205:%.*]], label [[IF_END3206:%.*]]
45045 // SIMD-ONLY0:       if.then3205:
45046 // SIMD-ONLY0-NEXT:    [[TMP2083:%.*]] = load i32, ptr [[IE]], align 4
45047 // SIMD-ONLY0-NEXT:    store i32 [[TMP2083]], ptr [[IX]], align 4
45048 // SIMD-ONLY0-NEXT:    br label [[IF_END3206]]
45049 // SIMD-ONLY0:       if.end3206:
45050 // SIMD-ONLY0-NEXT:    [[TMP2084:%.*]] = load i32, ptr [[IX]], align 4
45051 // SIMD-ONLY0-NEXT:    store i32 [[TMP2084]], ptr [[IV]], align 4
45052 // SIMD-ONLY0-NEXT:    [[TMP2085:%.*]] = load i32, ptr [[IX]], align 4
45053 // SIMD-ONLY0-NEXT:    [[TMP2086:%.*]] = load i32, ptr [[IE]], align 4
45054 // SIMD-ONLY0-NEXT:    [[CMP3207:%.*]] = icmp slt i32 [[TMP2085]], [[TMP2086]]
45055 // SIMD-ONLY0-NEXT:    br i1 [[CMP3207]], label [[IF_THEN3209:%.*]], label [[IF_END3210:%.*]]
45056 // SIMD-ONLY0:       if.then3209:
45057 // SIMD-ONLY0-NEXT:    [[TMP2087:%.*]] = load i32, ptr [[IE]], align 4
45058 // SIMD-ONLY0-NEXT:    store i32 [[TMP2087]], ptr [[IX]], align 4
45059 // SIMD-ONLY0-NEXT:    br label [[IF_END3210]]
45060 // SIMD-ONLY0:       if.end3210:
45061 // SIMD-ONLY0-NEXT:    [[TMP2088:%.*]] = load i32, ptr [[IX]], align 4
45062 // SIMD-ONLY0-NEXT:    store i32 [[TMP2088]], ptr [[IV]], align 4
45063 // SIMD-ONLY0-NEXT:    [[TMP2089:%.*]] = load i32, ptr [[IX]], align 4
45064 // SIMD-ONLY0-NEXT:    [[TMP2090:%.*]] = load i32, ptr [[IE]], align 4
45065 // SIMD-ONLY0-NEXT:    [[CMP3211:%.*]] = icmp eq i32 [[TMP2089]], [[TMP2090]]
45066 // SIMD-ONLY0-NEXT:    br i1 [[CMP3211]], label [[IF_THEN3213:%.*]], label [[IF_END3214:%.*]]
45067 // SIMD-ONLY0:       if.then3213:
45068 // SIMD-ONLY0-NEXT:    [[TMP2091:%.*]] = load i32, ptr [[ID]], align 4
45069 // SIMD-ONLY0-NEXT:    store i32 [[TMP2091]], ptr [[IX]], align 4
45070 // SIMD-ONLY0-NEXT:    br label [[IF_END3214]]
45071 // SIMD-ONLY0:       if.end3214:
45072 // SIMD-ONLY0-NEXT:    [[TMP2092:%.*]] = load i32, ptr [[IX]], align 4
45073 // SIMD-ONLY0-NEXT:    store i32 [[TMP2092]], ptr [[IV]], align 4
45074 // SIMD-ONLY0-NEXT:    [[TMP2093:%.*]] = load i32, ptr [[IE]], align 4
45075 // SIMD-ONLY0-NEXT:    [[TMP2094:%.*]] = load i32, ptr [[IX]], align 4
45076 // SIMD-ONLY0-NEXT:    [[CMP3215:%.*]] = icmp eq i32 [[TMP2093]], [[TMP2094]]
45077 // SIMD-ONLY0-NEXT:    br i1 [[CMP3215]], label [[IF_THEN3217:%.*]], label [[IF_END3218:%.*]]
45078 // SIMD-ONLY0:       if.then3217:
45079 // SIMD-ONLY0-NEXT:    [[TMP2095:%.*]] = load i32, ptr [[ID]], align 4
45080 // SIMD-ONLY0-NEXT:    store i32 [[TMP2095]], ptr [[IX]], align 4
45081 // SIMD-ONLY0-NEXT:    br label [[IF_END3218]]
45082 // SIMD-ONLY0:       if.end3218:
45083 // SIMD-ONLY0-NEXT:    [[TMP2096:%.*]] = load i32, ptr [[IE]], align 4
45084 // SIMD-ONLY0-NEXT:    [[TMP2097:%.*]] = load i32, ptr [[IX]], align 4
45085 // SIMD-ONLY0-NEXT:    [[CMP3219:%.*]] = icmp sgt i32 [[TMP2096]], [[TMP2097]]
45086 // SIMD-ONLY0-NEXT:    br i1 [[CMP3219]], label [[IF_THEN3221:%.*]], label [[IF_END3222:%.*]]
45087 // SIMD-ONLY0:       if.then3221:
45088 // SIMD-ONLY0-NEXT:    [[TMP2098:%.*]] = load i32, ptr [[IE]], align 4
45089 // SIMD-ONLY0-NEXT:    store i32 [[TMP2098]], ptr [[IX]], align 4
45090 // SIMD-ONLY0-NEXT:    br label [[IF_END3222]]
45091 // SIMD-ONLY0:       if.end3222:
45092 // SIMD-ONLY0-NEXT:    [[TMP2099:%.*]] = load i32, ptr [[IX]], align 4
45093 // SIMD-ONLY0-NEXT:    store i32 [[TMP2099]], ptr [[IV]], align 4
45094 // SIMD-ONLY0-NEXT:    [[TMP2100:%.*]] = load i32, ptr [[IX]], align 4
45095 // SIMD-ONLY0-NEXT:    [[TMP2101:%.*]] = load i32, ptr [[IE]], align 4
45096 // SIMD-ONLY0-NEXT:    [[CMP3223:%.*]] = icmp sgt i32 [[TMP2100]], [[TMP2101]]
45097 // SIMD-ONLY0-NEXT:    br i1 [[CMP3223]], label [[IF_THEN3225:%.*]], label [[IF_END3226:%.*]]
45098 // SIMD-ONLY0:       if.then3225:
45099 // SIMD-ONLY0-NEXT:    [[TMP2102:%.*]] = load i32, ptr [[IE]], align 4
45100 // SIMD-ONLY0-NEXT:    store i32 [[TMP2102]], ptr [[IX]], align 4
45101 // SIMD-ONLY0-NEXT:    br label [[IF_END3226]]
45102 // SIMD-ONLY0:       if.end3226:
45103 // SIMD-ONLY0-NEXT:    [[TMP2103:%.*]] = load i32, ptr [[IX]], align 4
45104 // SIMD-ONLY0-NEXT:    store i32 [[TMP2103]], ptr [[IV]], align 4
45105 // SIMD-ONLY0-NEXT:    [[TMP2104:%.*]] = load i32, ptr [[IE]], align 4
45106 // SIMD-ONLY0-NEXT:    [[TMP2105:%.*]] = load i32, ptr [[IX]], align 4
45107 // SIMD-ONLY0-NEXT:    [[CMP3227:%.*]] = icmp slt i32 [[TMP2104]], [[TMP2105]]
45108 // SIMD-ONLY0-NEXT:    br i1 [[CMP3227]], label [[IF_THEN3229:%.*]], label [[IF_END3230:%.*]]
45109 // SIMD-ONLY0:       if.then3229:
45110 // SIMD-ONLY0-NEXT:    [[TMP2106:%.*]] = load i32, ptr [[IE]], align 4
45111 // SIMD-ONLY0-NEXT:    store i32 [[TMP2106]], ptr [[IX]], align 4
45112 // SIMD-ONLY0-NEXT:    br label [[IF_END3230]]
45113 // SIMD-ONLY0:       if.end3230:
45114 // SIMD-ONLY0-NEXT:    [[TMP2107:%.*]] = load i32, ptr [[IX]], align 4
45115 // SIMD-ONLY0-NEXT:    store i32 [[TMP2107]], ptr [[IV]], align 4
45116 // SIMD-ONLY0-NEXT:    [[TMP2108:%.*]] = load i32, ptr [[IX]], align 4
45117 // SIMD-ONLY0-NEXT:    [[TMP2109:%.*]] = load i32, ptr [[IE]], align 4
45118 // SIMD-ONLY0-NEXT:    [[CMP3231:%.*]] = icmp slt i32 [[TMP2108]], [[TMP2109]]
45119 // SIMD-ONLY0-NEXT:    br i1 [[CMP3231]], label [[IF_THEN3233:%.*]], label [[IF_END3234:%.*]]
45120 // SIMD-ONLY0:       if.then3233:
45121 // SIMD-ONLY0-NEXT:    [[TMP2110:%.*]] = load i32, ptr [[IE]], align 4
45122 // SIMD-ONLY0-NEXT:    store i32 [[TMP2110]], ptr [[IX]], align 4
45123 // SIMD-ONLY0-NEXT:    br label [[IF_END3234]]
45124 // SIMD-ONLY0:       if.end3234:
45125 // SIMD-ONLY0-NEXT:    [[TMP2111:%.*]] = load i32, ptr [[IX]], align 4
45126 // SIMD-ONLY0-NEXT:    store i32 [[TMP2111]], ptr [[IV]], align 4
45127 // SIMD-ONLY0-NEXT:    [[TMP2112:%.*]] = load i32, ptr [[IX]], align 4
45128 // SIMD-ONLY0-NEXT:    [[TMP2113:%.*]] = load i32, ptr [[IE]], align 4
45129 // SIMD-ONLY0-NEXT:    [[CMP3235:%.*]] = icmp eq i32 [[TMP2112]], [[TMP2113]]
45130 // SIMD-ONLY0-NEXT:    br i1 [[CMP3235]], label [[IF_THEN3237:%.*]], label [[IF_END3238:%.*]]
45131 // SIMD-ONLY0:       if.then3237:
45132 // SIMD-ONLY0-NEXT:    [[TMP2114:%.*]] = load i32, ptr [[ID]], align 4
45133 // SIMD-ONLY0-NEXT:    store i32 [[TMP2114]], ptr [[IX]], align 4
45134 // SIMD-ONLY0-NEXT:    br label [[IF_END3238]]
45135 // SIMD-ONLY0:       if.end3238:
45136 // SIMD-ONLY0-NEXT:    [[TMP2115:%.*]] = load i32, ptr [[IX]], align 4
45137 // SIMD-ONLY0-NEXT:    store i32 [[TMP2115]], ptr [[IV]], align 4
45138 // SIMD-ONLY0-NEXT:    [[TMP2116:%.*]] = load i32, ptr [[IE]], align 4
45139 // SIMD-ONLY0-NEXT:    [[TMP2117:%.*]] = load i32, ptr [[IX]], align 4
45140 // SIMD-ONLY0-NEXT:    [[CMP3239:%.*]] = icmp eq i32 [[TMP2116]], [[TMP2117]]
45141 // SIMD-ONLY0-NEXT:    br i1 [[CMP3239]], label [[IF_THEN3241:%.*]], label [[IF_END3242:%.*]]
45142 // SIMD-ONLY0:       if.then3241:
45143 // SIMD-ONLY0-NEXT:    [[TMP2118:%.*]] = load i32, ptr [[ID]], align 4
45144 // SIMD-ONLY0-NEXT:    store i32 [[TMP2118]], ptr [[IX]], align 4
45145 // SIMD-ONLY0-NEXT:    br label [[IF_END3242]]
45146 // SIMD-ONLY0:       if.end3242:
45147 // SIMD-ONLY0-NEXT:    [[TMP2119:%.*]] = load i32, ptr [[IX]], align 4
45148 // SIMD-ONLY0-NEXT:    store i32 [[TMP2119]], ptr [[IV]], align 4
45149 // SIMD-ONLY0-NEXT:    [[TMP2120:%.*]] = load i32, ptr [[IX]], align 4
45150 // SIMD-ONLY0-NEXT:    [[TMP2121:%.*]] = load i32, ptr [[IE]], align 4
45151 // SIMD-ONLY0-NEXT:    [[CMP3243:%.*]] = icmp eq i32 [[TMP2120]], [[TMP2121]]
45152 // SIMD-ONLY0-NEXT:    br i1 [[CMP3243]], label [[IF_THEN3245:%.*]], label [[IF_ELSE3246:%.*]]
45153 // SIMD-ONLY0:       if.then3245:
45154 // SIMD-ONLY0-NEXT:    [[TMP2122:%.*]] = load i32, ptr [[ID]], align 4
45155 // SIMD-ONLY0-NEXT:    store i32 [[TMP2122]], ptr [[IX]], align 4
45156 // SIMD-ONLY0-NEXT:    br label [[IF_END3247:%.*]]
45157 // SIMD-ONLY0:       if.else3246:
45158 // SIMD-ONLY0-NEXT:    [[TMP2123:%.*]] = load i32, ptr [[IX]], align 4
45159 // SIMD-ONLY0-NEXT:    store i32 [[TMP2123]], ptr [[IV]], align 4
45160 // SIMD-ONLY0-NEXT:    br label [[IF_END3247]]
45161 // SIMD-ONLY0:       if.end3247:
45162 // SIMD-ONLY0-NEXT:    [[TMP2124:%.*]] = load i32, ptr [[IE]], align 4
45163 // SIMD-ONLY0-NEXT:    [[TMP2125:%.*]] = load i32, ptr [[IX]], align 4
45164 // SIMD-ONLY0-NEXT:    [[CMP3248:%.*]] = icmp eq i32 [[TMP2124]], [[TMP2125]]
45165 // SIMD-ONLY0-NEXT:    br i1 [[CMP3248]], label [[IF_THEN3250:%.*]], label [[IF_ELSE3251:%.*]]
45166 // SIMD-ONLY0:       if.then3250:
45167 // SIMD-ONLY0-NEXT:    [[TMP2126:%.*]] = load i32, ptr [[ID]], align 4
45168 // SIMD-ONLY0-NEXT:    store i32 [[TMP2126]], ptr [[IX]], align 4
45169 // SIMD-ONLY0-NEXT:    br label [[IF_END3252:%.*]]
45170 // SIMD-ONLY0:       if.else3251:
45171 // SIMD-ONLY0-NEXT:    [[TMP2127:%.*]] = load i32, ptr [[IX]], align 4
45172 // SIMD-ONLY0-NEXT:    store i32 [[TMP2127]], ptr [[IV]], align 4
45173 // SIMD-ONLY0-NEXT:    br label [[IF_END3252]]
45174 // SIMD-ONLY0:       if.end3252:
45175 // SIMD-ONLY0-NEXT:    [[TMP2128:%.*]] = load i32, ptr [[IX]], align 4
45176 // SIMD-ONLY0-NEXT:    [[TMP2129:%.*]] = load i32, ptr [[IE]], align 4
45177 // SIMD-ONLY0-NEXT:    [[CMP3253:%.*]] = icmp eq i32 [[TMP2128]], [[TMP2129]]
45178 // SIMD-ONLY0-NEXT:    [[CONV3254:%.*]] = zext i1 [[CMP3253]] to i32
45179 // SIMD-ONLY0-NEXT:    store i32 [[CONV3254]], ptr [[IR]], align 4
45180 // SIMD-ONLY0-NEXT:    [[TMP2130:%.*]] = load i32, ptr [[IR]], align 4
45181 // SIMD-ONLY0-NEXT:    [[TOBOOL3255:%.*]] = icmp ne i32 [[TMP2130]], 0
45182 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3255]], label [[IF_THEN3256:%.*]], label [[IF_END3257:%.*]]
45183 // SIMD-ONLY0:       if.then3256:
45184 // SIMD-ONLY0-NEXT:    [[TMP2131:%.*]] = load i32, ptr [[ID]], align 4
45185 // SIMD-ONLY0-NEXT:    store i32 [[TMP2131]], ptr [[IX]], align 4
45186 // SIMD-ONLY0-NEXT:    br label [[IF_END3257]]
45187 // SIMD-ONLY0:       if.end3257:
45188 // SIMD-ONLY0-NEXT:    [[TMP2132:%.*]] = load i32, ptr [[IE]], align 4
45189 // SIMD-ONLY0-NEXT:    [[TMP2133:%.*]] = load i32, ptr [[IX]], align 4
45190 // SIMD-ONLY0-NEXT:    [[CMP3258:%.*]] = icmp eq i32 [[TMP2132]], [[TMP2133]]
45191 // SIMD-ONLY0-NEXT:    [[CONV3259:%.*]] = zext i1 [[CMP3258]] to i32
45192 // SIMD-ONLY0-NEXT:    store i32 [[CONV3259]], ptr [[IR]], align 4
45193 // SIMD-ONLY0-NEXT:    [[TMP2134:%.*]] = load i32, ptr [[IR]], align 4
45194 // SIMD-ONLY0-NEXT:    [[TOBOOL3260:%.*]] = icmp ne i32 [[TMP2134]], 0
45195 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3260]], label [[IF_THEN3261:%.*]], label [[IF_END3262:%.*]]
45196 // SIMD-ONLY0:       if.then3261:
45197 // SIMD-ONLY0-NEXT:    [[TMP2135:%.*]] = load i32, ptr [[ID]], align 4
45198 // SIMD-ONLY0-NEXT:    store i32 [[TMP2135]], ptr [[IX]], align 4
45199 // SIMD-ONLY0-NEXT:    br label [[IF_END3262]]
45200 // SIMD-ONLY0:       if.end3262:
45201 // SIMD-ONLY0-NEXT:    [[TMP2136:%.*]] = load i32, ptr [[IX]], align 4
45202 // SIMD-ONLY0-NEXT:    [[TMP2137:%.*]] = load i32, ptr [[IE]], align 4
45203 // SIMD-ONLY0-NEXT:    [[CMP3263:%.*]] = icmp eq i32 [[TMP2136]], [[TMP2137]]
45204 // SIMD-ONLY0-NEXT:    [[CONV3264:%.*]] = zext i1 [[CMP3263]] to i32
45205 // SIMD-ONLY0-NEXT:    store i32 [[CONV3264]], ptr [[IR]], align 4
45206 // SIMD-ONLY0-NEXT:    [[TMP2138:%.*]] = load i32, ptr [[IR]], align 4
45207 // SIMD-ONLY0-NEXT:    [[TOBOOL3265:%.*]] = icmp ne i32 [[TMP2138]], 0
45208 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3265]], label [[IF_THEN3266:%.*]], label [[IF_ELSE3267:%.*]]
45209 // SIMD-ONLY0:       if.then3266:
45210 // SIMD-ONLY0-NEXT:    [[TMP2139:%.*]] = load i32, ptr [[ID]], align 4
45211 // SIMD-ONLY0-NEXT:    store i32 [[TMP2139]], ptr [[IX]], align 4
45212 // SIMD-ONLY0-NEXT:    br label [[IF_END3268:%.*]]
45213 // SIMD-ONLY0:       if.else3267:
45214 // SIMD-ONLY0-NEXT:    [[TMP2140:%.*]] = load i32, ptr [[IX]], align 4
45215 // SIMD-ONLY0-NEXT:    store i32 [[TMP2140]], ptr [[IV]], align 4
45216 // SIMD-ONLY0-NEXT:    br label [[IF_END3268]]
45217 // SIMD-ONLY0:       if.end3268:
45218 // SIMD-ONLY0-NEXT:    [[TMP2141:%.*]] = load i32, ptr [[IE]], align 4
45219 // SIMD-ONLY0-NEXT:    [[TMP2142:%.*]] = load i32, ptr [[IX]], align 4
45220 // SIMD-ONLY0-NEXT:    [[CMP3269:%.*]] = icmp eq i32 [[TMP2141]], [[TMP2142]]
45221 // SIMD-ONLY0-NEXT:    [[CONV3270:%.*]] = zext i1 [[CMP3269]] to i32
45222 // SIMD-ONLY0-NEXT:    store i32 [[CONV3270]], ptr [[IR]], align 4
45223 // SIMD-ONLY0-NEXT:    [[TMP2143:%.*]] = load i32, ptr [[IR]], align 4
45224 // SIMD-ONLY0-NEXT:    [[TOBOOL3271:%.*]] = icmp ne i32 [[TMP2143]], 0
45225 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3271]], label [[IF_THEN3272:%.*]], label [[IF_ELSE3273:%.*]]
45226 // SIMD-ONLY0:       if.then3272:
45227 // SIMD-ONLY0-NEXT:    [[TMP2144:%.*]] = load i32, ptr [[ID]], align 4
45228 // SIMD-ONLY0-NEXT:    store i32 [[TMP2144]], ptr [[IX]], align 4
45229 // SIMD-ONLY0-NEXT:    br label [[IF_END3274:%.*]]
45230 // SIMD-ONLY0:       if.else3273:
45231 // SIMD-ONLY0-NEXT:    [[TMP2145:%.*]] = load i32, ptr [[IX]], align 4
45232 // SIMD-ONLY0-NEXT:    store i32 [[TMP2145]], ptr [[IV]], align 4
45233 // SIMD-ONLY0-NEXT:    br label [[IF_END3274]]
45234 // SIMD-ONLY0:       if.end3274:
45235 // SIMD-ONLY0-NEXT:    [[TMP2146:%.*]] = load i32, ptr [[IX]], align 4
45236 // SIMD-ONLY0-NEXT:    store i32 [[TMP2146]], ptr [[IV]], align 4
45237 // SIMD-ONLY0-NEXT:    [[TMP2147:%.*]] = load i32, ptr [[IE]], align 4
45238 // SIMD-ONLY0-NEXT:    [[TMP2148:%.*]] = load i32, ptr [[IX]], align 4
45239 // SIMD-ONLY0-NEXT:    [[CMP3275:%.*]] = icmp sgt i32 [[TMP2147]], [[TMP2148]]
45240 // SIMD-ONLY0-NEXT:    br i1 [[CMP3275]], label [[IF_THEN3277:%.*]], label [[IF_END3278:%.*]]
45241 // SIMD-ONLY0:       if.then3277:
45242 // SIMD-ONLY0-NEXT:    [[TMP2149:%.*]] = load i32, ptr [[IE]], align 4
45243 // SIMD-ONLY0-NEXT:    store i32 [[TMP2149]], ptr [[IX]], align 4
45244 // SIMD-ONLY0-NEXT:    br label [[IF_END3278]]
45245 // SIMD-ONLY0:       if.end3278:
45246 // SIMD-ONLY0-NEXT:    [[TMP2150:%.*]] = load i32, ptr [[IX]], align 4
45247 // SIMD-ONLY0-NEXT:    store i32 [[TMP2150]], ptr [[IV]], align 4
45248 // SIMD-ONLY0-NEXT:    [[TMP2151:%.*]] = load i32, ptr [[IX]], align 4
45249 // SIMD-ONLY0-NEXT:    [[TMP2152:%.*]] = load i32, ptr [[IE]], align 4
45250 // SIMD-ONLY0-NEXT:    [[CMP3279:%.*]] = icmp sgt i32 [[TMP2151]], [[TMP2152]]
45251 // SIMD-ONLY0-NEXT:    br i1 [[CMP3279]], label [[IF_THEN3281:%.*]], label [[IF_END3282:%.*]]
45252 // SIMD-ONLY0:       if.then3281:
45253 // SIMD-ONLY0-NEXT:    [[TMP2153:%.*]] = load i32, ptr [[IE]], align 4
45254 // SIMD-ONLY0-NEXT:    store i32 [[TMP2153]], ptr [[IX]], align 4
45255 // SIMD-ONLY0-NEXT:    br label [[IF_END3282]]
45256 // SIMD-ONLY0:       if.end3282:
45257 // SIMD-ONLY0-NEXT:    [[TMP2154:%.*]] = load i32, ptr [[IX]], align 4
45258 // SIMD-ONLY0-NEXT:    store i32 [[TMP2154]], ptr [[IV]], align 4
45259 // SIMD-ONLY0-NEXT:    [[TMP2155:%.*]] = load i32, ptr [[IE]], align 4
45260 // SIMD-ONLY0-NEXT:    [[TMP2156:%.*]] = load i32, ptr [[IX]], align 4
45261 // SIMD-ONLY0-NEXT:    [[CMP3283:%.*]] = icmp slt i32 [[TMP2155]], [[TMP2156]]
45262 // SIMD-ONLY0-NEXT:    br i1 [[CMP3283]], label [[IF_THEN3285:%.*]], label [[IF_END3286:%.*]]
45263 // SIMD-ONLY0:       if.then3285:
45264 // SIMD-ONLY0-NEXT:    [[TMP2157:%.*]] = load i32, ptr [[IE]], align 4
45265 // SIMD-ONLY0-NEXT:    store i32 [[TMP2157]], ptr [[IX]], align 4
45266 // SIMD-ONLY0-NEXT:    br label [[IF_END3286]]
45267 // SIMD-ONLY0:       if.end3286:
45268 // SIMD-ONLY0-NEXT:    [[TMP2158:%.*]] = load i32, ptr [[IX]], align 4
45269 // SIMD-ONLY0-NEXT:    store i32 [[TMP2158]], ptr [[IV]], align 4
45270 // SIMD-ONLY0-NEXT:    [[TMP2159:%.*]] = load i32, ptr [[IX]], align 4
45271 // SIMD-ONLY0-NEXT:    [[TMP2160:%.*]] = load i32, ptr [[IE]], align 4
45272 // SIMD-ONLY0-NEXT:    [[CMP3287:%.*]] = icmp slt i32 [[TMP2159]], [[TMP2160]]
45273 // SIMD-ONLY0-NEXT:    br i1 [[CMP3287]], label [[IF_THEN3289:%.*]], label [[IF_END3290:%.*]]
45274 // SIMD-ONLY0:       if.then3289:
45275 // SIMD-ONLY0-NEXT:    [[TMP2161:%.*]] = load i32, ptr [[IE]], align 4
45276 // SIMD-ONLY0-NEXT:    store i32 [[TMP2161]], ptr [[IX]], align 4
45277 // SIMD-ONLY0-NEXT:    br label [[IF_END3290]]
45278 // SIMD-ONLY0:       if.end3290:
45279 // SIMD-ONLY0-NEXT:    [[TMP2162:%.*]] = load i32, ptr [[IX]], align 4
45280 // SIMD-ONLY0-NEXT:    store i32 [[TMP2162]], ptr [[IV]], align 4
45281 // SIMD-ONLY0-NEXT:    [[TMP2163:%.*]] = load i32, ptr [[IX]], align 4
45282 // SIMD-ONLY0-NEXT:    [[TMP2164:%.*]] = load i32, ptr [[IE]], align 4
45283 // SIMD-ONLY0-NEXT:    [[CMP3291:%.*]] = icmp eq i32 [[TMP2163]], [[TMP2164]]
45284 // SIMD-ONLY0-NEXT:    br i1 [[CMP3291]], label [[IF_THEN3293:%.*]], label [[IF_END3294:%.*]]
45285 // SIMD-ONLY0:       if.then3293:
45286 // SIMD-ONLY0-NEXT:    [[TMP2165:%.*]] = load i32, ptr [[ID]], align 4
45287 // SIMD-ONLY0-NEXT:    store i32 [[TMP2165]], ptr [[IX]], align 4
45288 // SIMD-ONLY0-NEXT:    br label [[IF_END3294]]
45289 // SIMD-ONLY0:       if.end3294:
45290 // SIMD-ONLY0-NEXT:    [[TMP2166:%.*]] = load i32, ptr [[IX]], align 4
45291 // SIMD-ONLY0-NEXT:    store i32 [[TMP2166]], ptr [[IV]], align 4
45292 // SIMD-ONLY0-NEXT:    [[TMP2167:%.*]] = load i32, ptr [[IE]], align 4
45293 // SIMD-ONLY0-NEXT:    [[TMP2168:%.*]] = load i32, ptr [[IX]], align 4
45294 // SIMD-ONLY0-NEXT:    [[CMP3295:%.*]] = icmp eq i32 [[TMP2167]], [[TMP2168]]
45295 // SIMD-ONLY0-NEXT:    br i1 [[CMP3295]], label [[IF_THEN3297:%.*]], label [[IF_END3298:%.*]]
45296 // SIMD-ONLY0:       if.then3297:
45297 // SIMD-ONLY0-NEXT:    [[TMP2169:%.*]] = load i32, ptr [[ID]], align 4
45298 // SIMD-ONLY0-NEXT:    store i32 [[TMP2169]], ptr [[IX]], align 4
45299 // SIMD-ONLY0-NEXT:    br label [[IF_END3298]]
45300 // SIMD-ONLY0:       if.end3298:
45301 // SIMD-ONLY0-NEXT:    [[TMP2170:%.*]] = load i32, ptr [[IE]], align 4
45302 // SIMD-ONLY0-NEXT:    [[TMP2171:%.*]] = load i32, ptr [[IX]], align 4
45303 // SIMD-ONLY0-NEXT:    [[CMP3299:%.*]] = icmp sgt i32 [[TMP2170]], [[TMP2171]]
45304 // SIMD-ONLY0-NEXT:    br i1 [[CMP3299]], label [[IF_THEN3301:%.*]], label [[IF_END3302:%.*]]
45305 // SIMD-ONLY0:       if.then3301:
45306 // SIMD-ONLY0-NEXT:    [[TMP2172:%.*]] = load i32, ptr [[IE]], align 4
45307 // SIMD-ONLY0-NEXT:    store i32 [[TMP2172]], ptr [[IX]], align 4
45308 // SIMD-ONLY0-NEXT:    br label [[IF_END3302]]
45309 // SIMD-ONLY0:       if.end3302:
45310 // SIMD-ONLY0-NEXT:    [[TMP2173:%.*]] = load i32, ptr [[IX]], align 4
45311 // SIMD-ONLY0-NEXT:    store i32 [[TMP2173]], ptr [[IV]], align 4
45312 // SIMD-ONLY0-NEXT:    [[TMP2174:%.*]] = load i32, ptr [[IX]], align 4
45313 // SIMD-ONLY0-NEXT:    [[TMP2175:%.*]] = load i32, ptr [[IE]], align 4
45314 // SIMD-ONLY0-NEXT:    [[CMP3303:%.*]] = icmp sgt i32 [[TMP2174]], [[TMP2175]]
45315 // SIMD-ONLY0-NEXT:    br i1 [[CMP3303]], label [[IF_THEN3305:%.*]], label [[IF_END3306:%.*]]
45316 // SIMD-ONLY0:       if.then3305:
45317 // SIMD-ONLY0-NEXT:    [[TMP2176:%.*]] = load i32, ptr [[IE]], align 4
45318 // SIMD-ONLY0-NEXT:    store i32 [[TMP2176]], ptr [[IX]], align 4
45319 // SIMD-ONLY0-NEXT:    br label [[IF_END3306]]
45320 // SIMD-ONLY0:       if.end3306:
45321 // SIMD-ONLY0-NEXT:    [[TMP2177:%.*]] = load i32, ptr [[IX]], align 4
45322 // SIMD-ONLY0-NEXT:    store i32 [[TMP2177]], ptr [[IV]], align 4
45323 // SIMD-ONLY0-NEXT:    [[TMP2178:%.*]] = load i32, ptr [[IE]], align 4
45324 // SIMD-ONLY0-NEXT:    [[TMP2179:%.*]] = load i32, ptr [[IX]], align 4
45325 // SIMD-ONLY0-NEXT:    [[CMP3307:%.*]] = icmp slt i32 [[TMP2178]], [[TMP2179]]
45326 // SIMD-ONLY0-NEXT:    br i1 [[CMP3307]], label [[IF_THEN3309:%.*]], label [[IF_END3310:%.*]]
45327 // SIMD-ONLY0:       if.then3309:
45328 // SIMD-ONLY0-NEXT:    [[TMP2180:%.*]] = load i32, ptr [[IE]], align 4
45329 // SIMD-ONLY0-NEXT:    store i32 [[TMP2180]], ptr [[IX]], align 4
45330 // SIMD-ONLY0-NEXT:    br label [[IF_END3310]]
45331 // SIMD-ONLY0:       if.end3310:
45332 // SIMD-ONLY0-NEXT:    [[TMP2181:%.*]] = load i32, ptr [[IX]], align 4
45333 // SIMD-ONLY0-NEXT:    store i32 [[TMP2181]], ptr [[IV]], align 4
45334 // SIMD-ONLY0-NEXT:    [[TMP2182:%.*]] = load i32, ptr [[IX]], align 4
45335 // SIMD-ONLY0-NEXT:    [[TMP2183:%.*]] = load i32, ptr [[IE]], align 4
45336 // SIMD-ONLY0-NEXT:    [[CMP3311:%.*]] = icmp slt i32 [[TMP2182]], [[TMP2183]]
45337 // SIMD-ONLY0-NEXT:    br i1 [[CMP3311]], label [[IF_THEN3313:%.*]], label [[IF_END3314:%.*]]
45338 // SIMD-ONLY0:       if.then3313:
45339 // SIMD-ONLY0-NEXT:    [[TMP2184:%.*]] = load i32, ptr [[IE]], align 4
45340 // SIMD-ONLY0-NEXT:    store i32 [[TMP2184]], ptr [[IX]], align 4
45341 // SIMD-ONLY0-NEXT:    br label [[IF_END3314]]
45342 // SIMD-ONLY0:       if.end3314:
45343 // SIMD-ONLY0-NEXT:    [[TMP2185:%.*]] = load i32, ptr [[IX]], align 4
45344 // SIMD-ONLY0-NEXT:    store i32 [[TMP2185]], ptr [[IV]], align 4
45345 // SIMD-ONLY0-NEXT:    [[TMP2186:%.*]] = load i32, ptr [[IX]], align 4
45346 // SIMD-ONLY0-NEXT:    [[TMP2187:%.*]] = load i32, ptr [[IE]], align 4
45347 // SIMD-ONLY0-NEXT:    [[CMP3315:%.*]] = icmp eq i32 [[TMP2186]], [[TMP2187]]
45348 // SIMD-ONLY0-NEXT:    br i1 [[CMP3315]], label [[IF_THEN3317:%.*]], label [[IF_END3318:%.*]]
45349 // SIMD-ONLY0:       if.then3317:
45350 // SIMD-ONLY0-NEXT:    [[TMP2188:%.*]] = load i32, ptr [[ID]], align 4
45351 // SIMD-ONLY0-NEXT:    store i32 [[TMP2188]], ptr [[IX]], align 4
45352 // SIMD-ONLY0-NEXT:    br label [[IF_END3318]]
45353 // SIMD-ONLY0:       if.end3318:
45354 // SIMD-ONLY0-NEXT:    [[TMP2189:%.*]] = load i32, ptr [[IX]], align 4
45355 // SIMD-ONLY0-NEXT:    store i32 [[TMP2189]], ptr [[IV]], align 4
45356 // SIMD-ONLY0-NEXT:    [[TMP2190:%.*]] = load i32, ptr [[IE]], align 4
45357 // SIMD-ONLY0-NEXT:    [[TMP2191:%.*]] = load i32, ptr [[IX]], align 4
45358 // SIMD-ONLY0-NEXT:    [[CMP3319:%.*]] = icmp eq i32 [[TMP2190]], [[TMP2191]]
45359 // SIMD-ONLY0-NEXT:    br i1 [[CMP3319]], label [[IF_THEN3321:%.*]], label [[IF_END3322:%.*]]
45360 // SIMD-ONLY0:       if.then3321:
45361 // SIMD-ONLY0-NEXT:    [[TMP2192:%.*]] = load i32, ptr [[ID]], align 4
45362 // SIMD-ONLY0-NEXT:    store i32 [[TMP2192]], ptr [[IX]], align 4
45363 // SIMD-ONLY0-NEXT:    br label [[IF_END3322]]
45364 // SIMD-ONLY0:       if.end3322:
45365 // SIMD-ONLY0-NEXT:    [[TMP2193:%.*]] = load i32, ptr [[IX]], align 4
45366 // SIMD-ONLY0-NEXT:    store i32 [[TMP2193]], ptr [[IV]], align 4
45367 // SIMD-ONLY0-NEXT:    [[TMP2194:%.*]] = load i32, ptr [[IX]], align 4
45368 // SIMD-ONLY0-NEXT:    [[TMP2195:%.*]] = load i32, ptr [[IE]], align 4
45369 // SIMD-ONLY0-NEXT:    [[CMP3323:%.*]] = icmp eq i32 [[TMP2194]], [[TMP2195]]
45370 // SIMD-ONLY0-NEXT:    br i1 [[CMP3323]], label [[IF_THEN3325:%.*]], label [[IF_ELSE3326:%.*]]
45371 // SIMD-ONLY0:       if.then3325:
45372 // SIMD-ONLY0-NEXT:    [[TMP2196:%.*]] = load i32, ptr [[ID]], align 4
45373 // SIMD-ONLY0-NEXT:    store i32 [[TMP2196]], ptr [[IX]], align 4
45374 // SIMD-ONLY0-NEXT:    br label [[IF_END3327:%.*]]
45375 // SIMD-ONLY0:       if.else3326:
45376 // SIMD-ONLY0-NEXT:    [[TMP2197:%.*]] = load i32, ptr [[IX]], align 4
45377 // SIMD-ONLY0-NEXT:    store i32 [[TMP2197]], ptr [[IV]], align 4
45378 // SIMD-ONLY0-NEXT:    br label [[IF_END3327]]
45379 // SIMD-ONLY0:       if.end3327:
45380 // SIMD-ONLY0-NEXT:    [[TMP2198:%.*]] = load i32, ptr [[IE]], align 4
45381 // SIMD-ONLY0-NEXT:    [[TMP2199:%.*]] = load i32, ptr [[IX]], align 4
45382 // SIMD-ONLY0-NEXT:    [[CMP3328:%.*]] = icmp eq i32 [[TMP2198]], [[TMP2199]]
45383 // SIMD-ONLY0-NEXT:    br i1 [[CMP3328]], label [[IF_THEN3330:%.*]], label [[IF_ELSE3331:%.*]]
45384 // SIMD-ONLY0:       if.then3330:
45385 // SIMD-ONLY0-NEXT:    [[TMP2200:%.*]] = load i32, ptr [[ID]], align 4
45386 // SIMD-ONLY0-NEXT:    store i32 [[TMP2200]], ptr [[IX]], align 4
45387 // SIMD-ONLY0-NEXT:    br label [[IF_END3332:%.*]]
45388 // SIMD-ONLY0:       if.else3331:
45389 // SIMD-ONLY0-NEXT:    [[TMP2201:%.*]] = load i32, ptr [[IX]], align 4
45390 // SIMD-ONLY0-NEXT:    store i32 [[TMP2201]], ptr [[IV]], align 4
45391 // SIMD-ONLY0-NEXT:    br label [[IF_END3332]]
45392 // SIMD-ONLY0:       if.end3332:
45393 // SIMD-ONLY0-NEXT:    [[TMP2202:%.*]] = load i32, ptr [[IX]], align 4
45394 // SIMD-ONLY0-NEXT:    [[TMP2203:%.*]] = load i32, ptr [[IE]], align 4
45395 // SIMD-ONLY0-NEXT:    [[CMP3333:%.*]] = icmp eq i32 [[TMP2202]], [[TMP2203]]
45396 // SIMD-ONLY0-NEXT:    [[CONV3334:%.*]] = zext i1 [[CMP3333]] to i32
45397 // SIMD-ONLY0-NEXT:    store i32 [[CONV3334]], ptr [[IR]], align 4
45398 // SIMD-ONLY0-NEXT:    [[TMP2204:%.*]] = load i32, ptr [[IR]], align 4
45399 // SIMD-ONLY0-NEXT:    [[TOBOOL3335:%.*]] = icmp ne i32 [[TMP2204]], 0
45400 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3335]], label [[IF_THEN3336:%.*]], label [[IF_END3337:%.*]]
45401 // SIMD-ONLY0:       if.then3336:
45402 // SIMD-ONLY0-NEXT:    [[TMP2205:%.*]] = load i32, ptr [[ID]], align 4
45403 // SIMD-ONLY0-NEXT:    store i32 [[TMP2205]], ptr [[IX]], align 4
45404 // SIMD-ONLY0-NEXT:    br label [[IF_END3337]]
45405 // SIMD-ONLY0:       if.end3337:
45406 // SIMD-ONLY0-NEXT:    [[TMP2206:%.*]] = load i32, ptr [[IE]], align 4
45407 // SIMD-ONLY0-NEXT:    [[TMP2207:%.*]] = load i32, ptr [[IX]], align 4
45408 // SIMD-ONLY0-NEXT:    [[CMP3338:%.*]] = icmp eq i32 [[TMP2206]], [[TMP2207]]
45409 // SIMD-ONLY0-NEXT:    [[CONV3339:%.*]] = zext i1 [[CMP3338]] to i32
45410 // SIMD-ONLY0-NEXT:    store i32 [[CONV3339]], ptr [[IR]], align 4
45411 // SIMD-ONLY0-NEXT:    [[TMP2208:%.*]] = load i32, ptr [[IR]], align 4
45412 // SIMD-ONLY0-NEXT:    [[TOBOOL3340:%.*]] = icmp ne i32 [[TMP2208]], 0
45413 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3340]], label [[IF_THEN3341:%.*]], label [[IF_END3342:%.*]]
45414 // SIMD-ONLY0:       if.then3341:
45415 // SIMD-ONLY0-NEXT:    [[TMP2209:%.*]] = load i32, ptr [[ID]], align 4
45416 // SIMD-ONLY0-NEXT:    store i32 [[TMP2209]], ptr [[IX]], align 4
45417 // SIMD-ONLY0-NEXT:    br label [[IF_END3342]]
45418 // SIMD-ONLY0:       if.end3342:
45419 // SIMD-ONLY0-NEXT:    [[TMP2210:%.*]] = load i32, ptr [[IX]], align 4
45420 // SIMD-ONLY0-NEXT:    [[TMP2211:%.*]] = load i32, ptr [[IE]], align 4
45421 // SIMD-ONLY0-NEXT:    [[CMP3343:%.*]] = icmp eq i32 [[TMP2210]], [[TMP2211]]
45422 // SIMD-ONLY0-NEXT:    [[CONV3344:%.*]] = zext i1 [[CMP3343]] to i32
45423 // SIMD-ONLY0-NEXT:    store i32 [[CONV3344]], ptr [[IR]], align 4
45424 // SIMD-ONLY0-NEXT:    [[TMP2212:%.*]] = load i32, ptr [[IR]], align 4
45425 // SIMD-ONLY0-NEXT:    [[TOBOOL3345:%.*]] = icmp ne i32 [[TMP2212]], 0
45426 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3345]], label [[IF_THEN3346:%.*]], label [[IF_ELSE3347:%.*]]
45427 // SIMD-ONLY0:       if.then3346:
45428 // SIMD-ONLY0-NEXT:    [[TMP2213:%.*]] = load i32, ptr [[ID]], align 4
45429 // SIMD-ONLY0-NEXT:    store i32 [[TMP2213]], ptr [[IX]], align 4
45430 // SIMD-ONLY0-NEXT:    br label [[IF_END3348:%.*]]
45431 // SIMD-ONLY0:       if.else3347:
45432 // SIMD-ONLY0-NEXT:    [[TMP2214:%.*]] = load i32, ptr [[IX]], align 4
45433 // SIMD-ONLY0-NEXT:    store i32 [[TMP2214]], ptr [[IV]], align 4
45434 // SIMD-ONLY0-NEXT:    br label [[IF_END3348]]
45435 // SIMD-ONLY0:       if.end3348:
45436 // SIMD-ONLY0-NEXT:    [[TMP2215:%.*]] = load i32, ptr [[IE]], align 4
45437 // SIMD-ONLY0-NEXT:    [[TMP2216:%.*]] = load i32, ptr [[IX]], align 4
45438 // SIMD-ONLY0-NEXT:    [[CMP3349:%.*]] = icmp eq i32 [[TMP2215]], [[TMP2216]]
45439 // SIMD-ONLY0-NEXT:    [[CONV3350:%.*]] = zext i1 [[CMP3349]] to i32
45440 // SIMD-ONLY0-NEXT:    store i32 [[CONV3350]], ptr [[IR]], align 4
45441 // SIMD-ONLY0-NEXT:    [[TMP2217:%.*]] = load i32, ptr [[IR]], align 4
45442 // SIMD-ONLY0-NEXT:    [[TOBOOL3351:%.*]] = icmp ne i32 [[TMP2217]], 0
45443 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3351]], label [[IF_THEN3352:%.*]], label [[IF_ELSE3353:%.*]]
45444 // SIMD-ONLY0:       if.then3352:
45445 // SIMD-ONLY0-NEXT:    [[TMP2218:%.*]] = load i32, ptr [[ID]], align 4
45446 // SIMD-ONLY0-NEXT:    store i32 [[TMP2218]], ptr [[IX]], align 4
45447 // SIMD-ONLY0-NEXT:    br label [[IF_END3354:%.*]]
45448 // SIMD-ONLY0:       if.else3353:
45449 // SIMD-ONLY0-NEXT:    [[TMP2219:%.*]] = load i32, ptr [[IX]], align 4
45450 // SIMD-ONLY0-NEXT:    store i32 [[TMP2219]], ptr [[IV]], align 4
45451 // SIMD-ONLY0-NEXT:    br label [[IF_END3354]]
45452 // SIMD-ONLY0:       if.end3354:
45453 // SIMD-ONLY0-NEXT:    [[TMP2220:%.*]] = load i32, ptr [[UIX]], align 4
45454 // SIMD-ONLY0-NEXT:    store i32 [[TMP2220]], ptr [[UIV]], align 4
45455 // SIMD-ONLY0-NEXT:    [[TMP2221:%.*]] = load i32, ptr [[UIE]], align 4
45456 // SIMD-ONLY0-NEXT:    [[TMP2222:%.*]] = load i32, ptr [[UIX]], align 4
45457 // SIMD-ONLY0-NEXT:    [[CMP3355:%.*]] = icmp ugt i32 [[TMP2221]], [[TMP2222]]
45458 // SIMD-ONLY0-NEXT:    br i1 [[CMP3355]], label [[IF_THEN3357:%.*]], label [[IF_END3358:%.*]]
45459 // SIMD-ONLY0:       if.then3357:
45460 // SIMD-ONLY0-NEXT:    [[TMP2223:%.*]] = load i32, ptr [[UIE]], align 4
45461 // SIMD-ONLY0-NEXT:    store i32 [[TMP2223]], ptr [[UIX]], align 4
45462 // SIMD-ONLY0-NEXT:    br label [[IF_END3358]]
45463 // SIMD-ONLY0:       if.end3358:
45464 // SIMD-ONLY0-NEXT:    [[TMP2224:%.*]] = load i32, ptr [[UIX]], align 4
45465 // SIMD-ONLY0-NEXT:    store i32 [[TMP2224]], ptr [[UIV]], align 4
45466 // SIMD-ONLY0-NEXT:    [[TMP2225:%.*]] = load i32, ptr [[UIX]], align 4
45467 // SIMD-ONLY0-NEXT:    [[TMP2226:%.*]] = load i32, ptr [[UIE]], align 4
45468 // SIMD-ONLY0-NEXT:    [[CMP3359:%.*]] = icmp ugt i32 [[TMP2225]], [[TMP2226]]
45469 // SIMD-ONLY0-NEXT:    br i1 [[CMP3359]], label [[IF_THEN3361:%.*]], label [[IF_END3362:%.*]]
45470 // SIMD-ONLY0:       if.then3361:
45471 // SIMD-ONLY0-NEXT:    [[TMP2227:%.*]] = load i32, ptr [[UIE]], align 4
45472 // SIMD-ONLY0-NEXT:    store i32 [[TMP2227]], ptr [[UIX]], align 4
45473 // SIMD-ONLY0-NEXT:    br label [[IF_END3362]]
45474 // SIMD-ONLY0:       if.end3362:
45475 // SIMD-ONLY0-NEXT:    [[TMP2228:%.*]] = load i32, ptr [[UIX]], align 4
45476 // SIMD-ONLY0-NEXT:    store i32 [[TMP2228]], ptr [[UIV]], align 4
45477 // SIMD-ONLY0-NEXT:    [[TMP2229:%.*]] = load i32, ptr [[UIE]], align 4
45478 // SIMD-ONLY0-NEXT:    [[TMP2230:%.*]] = load i32, ptr [[UIX]], align 4
45479 // SIMD-ONLY0-NEXT:    [[CMP3363:%.*]] = icmp ult i32 [[TMP2229]], [[TMP2230]]
45480 // SIMD-ONLY0-NEXT:    br i1 [[CMP3363]], label [[IF_THEN3365:%.*]], label [[IF_END3366:%.*]]
45481 // SIMD-ONLY0:       if.then3365:
45482 // SIMD-ONLY0-NEXT:    [[TMP2231:%.*]] = load i32, ptr [[UIE]], align 4
45483 // SIMD-ONLY0-NEXT:    store i32 [[TMP2231]], ptr [[UIX]], align 4
45484 // SIMD-ONLY0-NEXT:    br label [[IF_END3366]]
45485 // SIMD-ONLY0:       if.end3366:
45486 // SIMD-ONLY0-NEXT:    [[TMP2232:%.*]] = load i32, ptr [[UIX]], align 4
45487 // SIMD-ONLY0-NEXT:    store i32 [[TMP2232]], ptr [[UIV]], align 4
45488 // SIMD-ONLY0-NEXT:    [[TMP2233:%.*]] = load i32, ptr [[UIX]], align 4
45489 // SIMD-ONLY0-NEXT:    [[TMP2234:%.*]] = load i32, ptr [[UIE]], align 4
45490 // SIMD-ONLY0-NEXT:    [[CMP3367:%.*]] = icmp ult i32 [[TMP2233]], [[TMP2234]]
45491 // SIMD-ONLY0-NEXT:    br i1 [[CMP3367]], label [[IF_THEN3369:%.*]], label [[IF_END3370:%.*]]
45492 // SIMD-ONLY0:       if.then3369:
45493 // SIMD-ONLY0-NEXT:    [[TMP2235:%.*]] = load i32, ptr [[UIE]], align 4
45494 // SIMD-ONLY0-NEXT:    store i32 [[TMP2235]], ptr [[UIX]], align 4
45495 // SIMD-ONLY0-NEXT:    br label [[IF_END3370]]
45496 // SIMD-ONLY0:       if.end3370:
45497 // SIMD-ONLY0-NEXT:    [[TMP2236:%.*]] = load i32, ptr [[UIX]], align 4
45498 // SIMD-ONLY0-NEXT:    store i32 [[TMP2236]], ptr [[UIV]], align 4
45499 // SIMD-ONLY0-NEXT:    [[TMP2237:%.*]] = load i32, ptr [[UIX]], align 4
45500 // SIMD-ONLY0-NEXT:    [[TMP2238:%.*]] = load i32, ptr [[UIE]], align 4
45501 // SIMD-ONLY0-NEXT:    [[CMP3371:%.*]] = icmp eq i32 [[TMP2237]], [[TMP2238]]
45502 // SIMD-ONLY0-NEXT:    br i1 [[CMP3371]], label [[IF_THEN3373:%.*]], label [[IF_END3374:%.*]]
45503 // SIMD-ONLY0:       if.then3373:
45504 // SIMD-ONLY0-NEXT:    [[TMP2239:%.*]] = load i32, ptr [[UID]], align 4
45505 // SIMD-ONLY0-NEXT:    store i32 [[TMP2239]], ptr [[UIX]], align 4
45506 // SIMD-ONLY0-NEXT:    br label [[IF_END3374]]
45507 // SIMD-ONLY0:       if.end3374:
45508 // SIMD-ONLY0-NEXT:    [[TMP2240:%.*]] = load i32, ptr [[UIX]], align 4
45509 // SIMD-ONLY0-NEXT:    store i32 [[TMP2240]], ptr [[UIV]], align 4
45510 // SIMD-ONLY0-NEXT:    [[TMP2241:%.*]] = load i32, ptr [[UIE]], align 4
45511 // SIMD-ONLY0-NEXT:    [[TMP2242:%.*]] = load i32, ptr [[UIX]], align 4
45512 // SIMD-ONLY0-NEXT:    [[CMP3375:%.*]] = icmp eq i32 [[TMP2241]], [[TMP2242]]
45513 // SIMD-ONLY0-NEXT:    br i1 [[CMP3375]], label [[IF_THEN3377:%.*]], label [[IF_END3378:%.*]]
45514 // SIMD-ONLY0:       if.then3377:
45515 // SIMD-ONLY0-NEXT:    [[TMP2243:%.*]] = load i32, ptr [[UID]], align 4
45516 // SIMD-ONLY0-NEXT:    store i32 [[TMP2243]], ptr [[UIX]], align 4
45517 // SIMD-ONLY0-NEXT:    br label [[IF_END3378]]
45518 // SIMD-ONLY0:       if.end3378:
45519 // SIMD-ONLY0-NEXT:    [[TMP2244:%.*]] = load i32, ptr [[UIE]], align 4
45520 // SIMD-ONLY0-NEXT:    [[TMP2245:%.*]] = load i32, ptr [[UIX]], align 4
45521 // SIMD-ONLY0-NEXT:    [[CMP3379:%.*]] = icmp ugt i32 [[TMP2244]], [[TMP2245]]
45522 // SIMD-ONLY0-NEXT:    br i1 [[CMP3379]], label [[IF_THEN3381:%.*]], label [[IF_END3382:%.*]]
45523 // SIMD-ONLY0:       if.then3381:
45524 // SIMD-ONLY0-NEXT:    [[TMP2246:%.*]] = load i32, ptr [[UIE]], align 4
45525 // SIMD-ONLY0-NEXT:    store i32 [[TMP2246]], ptr [[UIX]], align 4
45526 // SIMD-ONLY0-NEXT:    br label [[IF_END3382]]
45527 // SIMD-ONLY0:       if.end3382:
45528 // SIMD-ONLY0-NEXT:    [[TMP2247:%.*]] = load i32, ptr [[UIX]], align 4
45529 // SIMD-ONLY0-NEXT:    store i32 [[TMP2247]], ptr [[UIV]], align 4
45530 // SIMD-ONLY0-NEXT:    [[TMP2248:%.*]] = load i32, ptr [[UIX]], align 4
45531 // SIMD-ONLY0-NEXT:    [[TMP2249:%.*]] = load i32, ptr [[UIE]], align 4
45532 // SIMD-ONLY0-NEXT:    [[CMP3383:%.*]] = icmp ugt i32 [[TMP2248]], [[TMP2249]]
45533 // SIMD-ONLY0-NEXT:    br i1 [[CMP3383]], label [[IF_THEN3385:%.*]], label [[IF_END3386:%.*]]
45534 // SIMD-ONLY0:       if.then3385:
45535 // SIMD-ONLY0-NEXT:    [[TMP2250:%.*]] = load i32, ptr [[UIE]], align 4
45536 // SIMD-ONLY0-NEXT:    store i32 [[TMP2250]], ptr [[UIX]], align 4
45537 // SIMD-ONLY0-NEXT:    br label [[IF_END3386]]
45538 // SIMD-ONLY0:       if.end3386:
45539 // SIMD-ONLY0-NEXT:    [[TMP2251:%.*]] = load i32, ptr [[UIX]], align 4
45540 // SIMD-ONLY0-NEXT:    store i32 [[TMP2251]], ptr [[UIV]], align 4
45541 // SIMD-ONLY0-NEXT:    [[TMP2252:%.*]] = load i32, ptr [[UIE]], align 4
45542 // SIMD-ONLY0-NEXT:    [[TMP2253:%.*]] = load i32, ptr [[UIX]], align 4
45543 // SIMD-ONLY0-NEXT:    [[CMP3387:%.*]] = icmp ult i32 [[TMP2252]], [[TMP2253]]
45544 // SIMD-ONLY0-NEXT:    br i1 [[CMP3387]], label [[IF_THEN3389:%.*]], label [[IF_END3390:%.*]]
45545 // SIMD-ONLY0:       if.then3389:
45546 // SIMD-ONLY0-NEXT:    [[TMP2254:%.*]] = load i32, ptr [[UIE]], align 4
45547 // SIMD-ONLY0-NEXT:    store i32 [[TMP2254]], ptr [[UIX]], align 4
45548 // SIMD-ONLY0-NEXT:    br label [[IF_END3390]]
45549 // SIMD-ONLY0:       if.end3390:
45550 // SIMD-ONLY0-NEXT:    [[TMP2255:%.*]] = load i32, ptr [[UIX]], align 4
45551 // SIMD-ONLY0-NEXT:    store i32 [[TMP2255]], ptr [[UIV]], align 4
45552 // SIMD-ONLY0-NEXT:    [[TMP2256:%.*]] = load i32, ptr [[UIX]], align 4
45553 // SIMD-ONLY0-NEXT:    [[TMP2257:%.*]] = load i32, ptr [[UIE]], align 4
45554 // SIMD-ONLY0-NEXT:    [[CMP3391:%.*]] = icmp ult i32 [[TMP2256]], [[TMP2257]]
45555 // SIMD-ONLY0-NEXT:    br i1 [[CMP3391]], label [[IF_THEN3393:%.*]], label [[IF_END3394:%.*]]
45556 // SIMD-ONLY0:       if.then3393:
45557 // SIMD-ONLY0-NEXT:    [[TMP2258:%.*]] = load i32, ptr [[UIE]], align 4
45558 // SIMD-ONLY0-NEXT:    store i32 [[TMP2258]], ptr [[UIX]], align 4
45559 // SIMD-ONLY0-NEXT:    br label [[IF_END3394]]
45560 // SIMD-ONLY0:       if.end3394:
45561 // SIMD-ONLY0-NEXT:    [[TMP2259:%.*]] = load i32, ptr [[UIX]], align 4
45562 // SIMD-ONLY0-NEXT:    store i32 [[TMP2259]], ptr [[UIV]], align 4
45563 // SIMD-ONLY0-NEXT:    [[TMP2260:%.*]] = load i32, ptr [[UIX]], align 4
45564 // SIMD-ONLY0-NEXT:    [[TMP2261:%.*]] = load i32, ptr [[UIE]], align 4
45565 // SIMD-ONLY0-NEXT:    [[CMP3395:%.*]] = icmp eq i32 [[TMP2260]], [[TMP2261]]
45566 // SIMD-ONLY0-NEXT:    br i1 [[CMP3395]], label [[IF_THEN3397:%.*]], label [[IF_END3398:%.*]]
45567 // SIMD-ONLY0:       if.then3397:
45568 // SIMD-ONLY0-NEXT:    [[TMP2262:%.*]] = load i32, ptr [[UID]], align 4
45569 // SIMD-ONLY0-NEXT:    store i32 [[TMP2262]], ptr [[UIX]], align 4
45570 // SIMD-ONLY0-NEXT:    br label [[IF_END3398]]
45571 // SIMD-ONLY0:       if.end3398:
45572 // SIMD-ONLY0-NEXT:    [[TMP2263:%.*]] = load i32, ptr [[UIX]], align 4
45573 // SIMD-ONLY0-NEXT:    store i32 [[TMP2263]], ptr [[UIV]], align 4
45574 // SIMD-ONLY0-NEXT:    [[TMP2264:%.*]] = load i32, ptr [[UIE]], align 4
45575 // SIMD-ONLY0-NEXT:    [[TMP2265:%.*]] = load i32, ptr [[UIX]], align 4
45576 // SIMD-ONLY0-NEXT:    [[CMP3399:%.*]] = icmp eq i32 [[TMP2264]], [[TMP2265]]
45577 // SIMD-ONLY0-NEXT:    br i1 [[CMP3399]], label [[IF_THEN3401:%.*]], label [[IF_END3402:%.*]]
45578 // SIMD-ONLY0:       if.then3401:
45579 // SIMD-ONLY0-NEXT:    [[TMP2266:%.*]] = load i32, ptr [[UID]], align 4
45580 // SIMD-ONLY0-NEXT:    store i32 [[TMP2266]], ptr [[UIX]], align 4
45581 // SIMD-ONLY0-NEXT:    br label [[IF_END3402]]
45582 // SIMD-ONLY0:       if.end3402:
45583 // SIMD-ONLY0-NEXT:    [[TMP2267:%.*]] = load i32, ptr [[UIX]], align 4
45584 // SIMD-ONLY0-NEXT:    store i32 [[TMP2267]], ptr [[UIV]], align 4
45585 // SIMD-ONLY0-NEXT:    [[TMP2268:%.*]] = load i32, ptr [[UIX]], align 4
45586 // SIMD-ONLY0-NEXT:    [[TMP2269:%.*]] = load i32, ptr [[UIE]], align 4
45587 // SIMD-ONLY0-NEXT:    [[CMP3403:%.*]] = icmp eq i32 [[TMP2268]], [[TMP2269]]
45588 // SIMD-ONLY0-NEXT:    br i1 [[CMP3403]], label [[IF_THEN3405:%.*]], label [[IF_ELSE3406:%.*]]
45589 // SIMD-ONLY0:       if.then3405:
45590 // SIMD-ONLY0-NEXT:    [[TMP2270:%.*]] = load i32, ptr [[UID]], align 4
45591 // SIMD-ONLY0-NEXT:    store i32 [[TMP2270]], ptr [[UIX]], align 4
45592 // SIMD-ONLY0-NEXT:    br label [[IF_END3407:%.*]]
45593 // SIMD-ONLY0:       if.else3406:
45594 // SIMD-ONLY0-NEXT:    [[TMP2271:%.*]] = load i32, ptr [[UIX]], align 4
45595 // SIMD-ONLY0-NEXT:    store i32 [[TMP2271]], ptr [[UIV]], align 4
45596 // SIMD-ONLY0-NEXT:    br label [[IF_END3407]]
45597 // SIMD-ONLY0:       if.end3407:
45598 // SIMD-ONLY0-NEXT:    [[TMP2272:%.*]] = load i32, ptr [[UIE]], align 4
45599 // SIMD-ONLY0-NEXT:    [[TMP2273:%.*]] = load i32, ptr [[UIX]], align 4
45600 // SIMD-ONLY0-NEXT:    [[CMP3408:%.*]] = icmp eq i32 [[TMP2272]], [[TMP2273]]
45601 // SIMD-ONLY0-NEXT:    br i1 [[CMP3408]], label [[IF_THEN3410:%.*]], label [[IF_ELSE3411:%.*]]
45602 // SIMD-ONLY0:       if.then3410:
45603 // SIMD-ONLY0-NEXT:    [[TMP2274:%.*]] = load i32, ptr [[UID]], align 4
45604 // SIMD-ONLY0-NEXT:    store i32 [[TMP2274]], ptr [[UIX]], align 4
45605 // SIMD-ONLY0-NEXT:    br label [[IF_END3412:%.*]]
45606 // SIMD-ONLY0:       if.else3411:
45607 // SIMD-ONLY0-NEXT:    [[TMP2275:%.*]] = load i32, ptr [[UIX]], align 4
45608 // SIMD-ONLY0-NEXT:    store i32 [[TMP2275]], ptr [[UIV]], align 4
45609 // SIMD-ONLY0-NEXT:    br label [[IF_END3412]]
45610 // SIMD-ONLY0:       if.end3412:
45611 // SIMD-ONLY0-NEXT:    [[TMP2276:%.*]] = load i32, ptr [[UIX]], align 4
45612 // SIMD-ONLY0-NEXT:    [[TMP2277:%.*]] = load i32, ptr [[UIE]], align 4
45613 // SIMD-ONLY0-NEXT:    [[CMP3413:%.*]] = icmp eq i32 [[TMP2276]], [[TMP2277]]
45614 // SIMD-ONLY0-NEXT:    [[CONV3414:%.*]] = zext i1 [[CMP3413]] to i32
45615 // SIMD-ONLY0-NEXT:    store i32 [[CONV3414]], ptr [[UIR]], align 4
45616 // SIMD-ONLY0-NEXT:    [[TMP2278:%.*]] = load i32, ptr [[UIR]], align 4
45617 // SIMD-ONLY0-NEXT:    [[TOBOOL3415:%.*]] = icmp ne i32 [[TMP2278]], 0
45618 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3415]], label [[IF_THEN3416:%.*]], label [[IF_END3417:%.*]]
45619 // SIMD-ONLY0:       if.then3416:
45620 // SIMD-ONLY0-NEXT:    [[TMP2279:%.*]] = load i32, ptr [[UID]], align 4
45621 // SIMD-ONLY0-NEXT:    store i32 [[TMP2279]], ptr [[UIX]], align 4
45622 // SIMD-ONLY0-NEXT:    br label [[IF_END3417]]
45623 // SIMD-ONLY0:       if.end3417:
45624 // SIMD-ONLY0-NEXT:    [[TMP2280:%.*]] = load i32, ptr [[UIE]], align 4
45625 // SIMD-ONLY0-NEXT:    [[TMP2281:%.*]] = load i32, ptr [[UIX]], align 4
45626 // SIMD-ONLY0-NEXT:    [[CMP3418:%.*]] = icmp eq i32 [[TMP2280]], [[TMP2281]]
45627 // SIMD-ONLY0-NEXT:    [[CONV3419:%.*]] = zext i1 [[CMP3418]] to i32
45628 // SIMD-ONLY0-NEXT:    store i32 [[CONV3419]], ptr [[UIR]], align 4
45629 // SIMD-ONLY0-NEXT:    [[TMP2282:%.*]] = load i32, ptr [[UIR]], align 4
45630 // SIMD-ONLY0-NEXT:    [[TOBOOL3420:%.*]] = icmp ne i32 [[TMP2282]], 0
45631 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3420]], label [[IF_THEN3421:%.*]], label [[IF_END3422:%.*]]
45632 // SIMD-ONLY0:       if.then3421:
45633 // SIMD-ONLY0-NEXT:    [[TMP2283:%.*]] = load i32, ptr [[UID]], align 4
45634 // SIMD-ONLY0-NEXT:    store i32 [[TMP2283]], ptr [[UIX]], align 4
45635 // SIMD-ONLY0-NEXT:    br label [[IF_END3422]]
45636 // SIMD-ONLY0:       if.end3422:
45637 // SIMD-ONLY0-NEXT:    [[TMP2284:%.*]] = load i32, ptr [[UIX]], align 4
45638 // SIMD-ONLY0-NEXT:    [[TMP2285:%.*]] = load i32, ptr [[UIE]], align 4
45639 // SIMD-ONLY0-NEXT:    [[CMP3423:%.*]] = icmp eq i32 [[TMP2284]], [[TMP2285]]
45640 // SIMD-ONLY0-NEXT:    [[CONV3424:%.*]] = zext i1 [[CMP3423]] to i32
45641 // SIMD-ONLY0-NEXT:    store i32 [[CONV3424]], ptr [[UIR]], align 4
45642 // SIMD-ONLY0-NEXT:    [[TMP2286:%.*]] = load i32, ptr [[UIR]], align 4
45643 // SIMD-ONLY0-NEXT:    [[TOBOOL3425:%.*]] = icmp ne i32 [[TMP2286]], 0
45644 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3425]], label [[IF_THEN3426:%.*]], label [[IF_ELSE3427:%.*]]
45645 // SIMD-ONLY0:       if.then3426:
45646 // SIMD-ONLY0-NEXT:    [[TMP2287:%.*]] = load i32, ptr [[UID]], align 4
45647 // SIMD-ONLY0-NEXT:    store i32 [[TMP2287]], ptr [[UIX]], align 4
45648 // SIMD-ONLY0-NEXT:    br label [[IF_END3428:%.*]]
45649 // SIMD-ONLY0:       if.else3427:
45650 // SIMD-ONLY0-NEXT:    [[TMP2288:%.*]] = load i32, ptr [[UIX]], align 4
45651 // SIMD-ONLY0-NEXT:    store i32 [[TMP2288]], ptr [[UIV]], align 4
45652 // SIMD-ONLY0-NEXT:    br label [[IF_END3428]]
45653 // SIMD-ONLY0:       if.end3428:
45654 // SIMD-ONLY0-NEXT:    [[TMP2289:%.*]] = load i32, ptr [[UIE]], align 4
45655 // SIMD-ONLY0-NEXT:    [[TMP2290:%.*]] = load i32, ptr [[UIX]], align 4
45656 // SIMD-ONLY0-NEXT:    [[CMP3429:%.*]] = icmp eq i32 [[TMP2289]], [[TMP2290]]
45657 // SIMD-ONLY0-NEXT:    [[CONV3430:%.*]] = zext i1 [[CMP3429]] to i32
45658 // SIMD-ONLY0-NEXT:    store i32 [[CONV3430]], ptr [[UIR]], align 4
45659 // SIMD-ONLY0-NEXT:    [[TMP2291:%.*]] = load i32, ptr [[UIR]], align 4
45660 // SIMD-ONLY0-NEXT:    [[TOBOOL3431:%.*]] = icmp ne i32 [[TMP2291]], 0
45661 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3431]], label [[IF_THEN3432:%.*]], label [[IF_ELSE3433:%.*]]
45662 // SIMD-ONLY0:       if.then3432:
45663 // SIMD-ONLY0-NEXT:    [[TMP2292:%.*]] = load i32, ptr [[UID]], align 4
45664 // SIMD-ONLY0-NEXT:    store i32 [[TMP2292]], ptr [[UIX]], align 4
45665 // SIMD-ONLY0-NEXT:    br label [[IF_END3434:%.*]]
45666 // SIMD-ONLY0:       if.else3433:
45667 // SIMD-ONLY0-NEXT:    [[TMP2293:%.*]] = load i32, ptr [[UIX]], align 4
45668 // SIMD-ONLY0-NEXT:    store i32 [[TMP2293]], ptr [[UIV]], align 4
45669 // SIMD-ONLY0-NEXT:    br label [[IF_END3434]]
45670 // SIMD-ONLY0:       if.end3434:
45671 // SIMD-ONLY0-NEXT:    [[TMP2294:%.*]] = load i32, ptr [[UIX]], align 4
45672 // SIMD-ONLY0-NEXT:    store i32 [[TMP2294]], ptr [[UIV]], align 4
45673 // SIMD-ONLY0-NEXT:    [[TMP2295:%.*]] = load i32, ptr [[UIE]], align 4
45674 // SIMD-ONLY0-NEXT:    [[TMP2296:%.*]] = load i32, ptr [[UIX]], align 4
45675 // SIMD-ONLY0-NEXT:    [[CMP3435:%.*]] = icmp ugt i32 [[TMP2295]], [[TMP2296]]
45676 // SIMD-ONLY0-NEXT:    br i1 [[CMP3435]], label [[IF_THEN3437:%.*]], label [[IF_END3438:%.*]]
45677 // SIMD-ONLY0:       if.then3437:
45678 // SIMD-ONLY0-NEXT:    [[TMP2297:%.*]] = load i32, ptr [[UIE]], align 4
45679 // SIMD-ONLY0-NEXT:    store i32 [[TMP2297]], ptr [[UIX]], align 4
45680 // SIMD-ONLY0-NEXT:    br label [[IF_END3438]]
45681 // SIMD-ONLY0:       if.end3438:
45682 // SIMD-ONLY0-NEXT:    [[TMP2298:%.*]] = load i32, ptr [[UIX]], align 4
45683 // SIMD-ONLY0-NEXT:    store i32 [[TMP2298]], ptr [[UIV]], align 4
45684 // SIMD-ONLY0-NEXT:    [[TMP2299:%.*]] = load i32, ptr [[UIX]], align 4
45685 // SIMD-ONLY0-NEXT:    [[TMP2300:%.*]] = load i32, ptr [[UIE]], align 4
45686 // SIMD-ONLY0-NEXT:    [[CMP3439:%.*]] = icmp ugt i32 [[TMP2299]], [[TMP2300]]
45687 // SIMD-ONLY0-NEXT:    br i1 [[CMP3439]], label [[IF_THEN3441:%.*]], label [[IF_END3442:%.*]]
45688 // SIMD-ONLY0:       if.then3441:
45689 // SIMD-ONLY0-NEXT:    [[TMP2301:%.*]] = load i32, ptr [[UIE]], align 4
45690 // SIMD-ONLY0-NEXT:    store i32 [[TMP2301]], ptr [[UIX]], align 4
45691 // SIMD-ONLY0-NEXT:    br label [[IF_END3442]]
45692 // SIMD-ONLY0:       if.end3442:
45693 // SIMD-ONLY0-NEXT:    [[TMP2302:%.*]] = load i32, ptr [[UIX]], align 4
45694 // SIMD-ONLY0-NEXT:    store i32 [[TMP2302]], ptr [[UIV]], align 4
45695 // SIMD-ONLY0-NEXT:    [[TMP2303:%.*]] = load i32, ptr [[UIE]], align 4
45696 // SIMD-ONLY0-NEXT:    [[TMP2304:%.*]] = load i32, ptr [[UIX]], align 4
45697 // SIMD-ONLY0-NEXT:    [[CMP3443:%.*]] = icmp ult i32 [[TMP2303]], [[TMP2304]]
45698 // SIMD-ONLY0-NEXT:    br i1 [[CMP3443]], label [[IF_THEN3445:%.*]], label [[IF_END3446:%.*]]
45699 // SIMD-ONLY0:       if.then3445:
45700 // SIMD-ONLY0-NEXT:    [[TMP2305:%.*]] = load i32, ptr [[UIE]], align 4
45701 // SIMD-ONLY0-NEXT:    store i32 [[TMP2305]], ptr [[UIX]], align 4
45702 // SIMD-ONLY0-NEXT:    br label [[IF_END3446]]
45703 // SIMD-ONLY0:       if.end3446:
45704 // SIMD-ONLY0-NEXT:    [[TMP2306:%.*]] = load i32, ptr [[UIX]], align 4
45705 // SIMD-ONLY0-NEXT:    store i32 [[TMP2306]], ptr [[UIV]], align 4
45706 // SIMD-ONLY0-NEXT:    [[TMP2307:%.*]] = load i32, ptr [[UIX]], align 4
45707 // SIMD-ONLY0-NEXT:    [[TMP2308:%.*]] = load i32, ptr [[UIE]], align 4
45708 // SIMD-ONLY0-NEXT:    [[CMP3447:%.*]] = icmp ult i32 [[TMP2307]], [[TMP2308]]
45709 // SIMD-ONLY0-NEXT:    br i1 [[CMP3447]], label [[IF_THEN3449:%.*]], label [[IF_END3450:%.*]]
45710 // SIMD-ONLY0:       if.then3449:
45711 // SIMD-ONLY0-NEXT:    [[TMP2309:%.*]] = load i32, ptr [[UIE]], align 4
45712 // SIMD-ONLY0-NEXT:    store i32 [[TMP2309]], ptr [[UIX]], align 4
45713 // SIMD-ONLY0-NEXT:    br label [[IF_END3450]]
45714 // SIMD-ONLY0:       if.end3450:
45715 // SIMD-ONLY0-NEXT:    [[TMP2310:%.*]] = load i32, ptr [[UIX]], align 4
45716 // SIMD-ONLY0-NEXT:    store i32 [[TMP2310]], ptr [[UIV]], align 4
45717 // SIMD-ONLY0-NEXT:    [[TMP2311:%.*]] = load i32, ptr [[UIX]], align 4
45718 // SIMD-ONLY0-NEXT:    [[TMP2312:%.*]] = load i32, ptr [[UIE]], align 4
45719 // SIMD-ONLY0-NEXT:    [[CMP3451:%.*]] = icmp eq i32 [[TMP2311]], [[TMP2312]]
45720 // SIMD-ONLY0-NEXT:    br i1 [[CMP3451]], label [[IF_THEN3453:%.*]], label [[IF_END3454:%.*]]
45721 // SIMD-ONLY0:       if.then3453:
45722 // SIMD-ONLY0-NEXT:    [[TMP2313:%.*]] = load i32, ptr [[UID]], align 4
45723 // SIMD-ONLY0-NEXT:    store i32 [[TMP2313]], ptr [[UIX]], align 4
45724 // SIMD-ONLY0-NEXT:    br label [[IF_END3454]]
45725 // SIMD-ONLY0:       if.end3454:
45726 // SIMD-ONLY0-NEXT:    [[TMP2314:%.*]] = load i32, ptr [[UIX]], align 4
45727 // SIMD-ONLY0-NEXT:    store i32 [[TMP2314]], ptr [[UIV]], align 4
45728 // SIMD-ONLY0-NEXT:    [[TMP2315:%.*]] = load i32, ptr [[UIE]], align 4
45729 // SIMD-ONLY0-NEXT:    [[TMP2316:%.*]] = load i32, ptr [[UIX]], align 4
45730 // SIMD-ONLY0-NEXT:    [[CMP3455:%.*]] = icmp eq i32 [[TMP2315]], [[TMP2316]]
45731 // SIMD-ONLY0-NEXT:    br i1 [[CMP3455]], label [[IF_THEN3457:%.*]], label [[IF_END3458:%.*]]
45732 // SIMD-ONLY0:       if.then3457:
45733 // SIMD-ONLY0-NEXT:    [[TMP2317:%.*]] = load i32, ptr [[UID]], align 4
45734 // SIMD-ONLY0-NEXT:    store i32 [[TMP2317]], ptr [[UIX]], align 4
45735 // SIMD-ONLY0-NEXT:    br label [[IF_END3458]]
45736 // SIMD-ONLY0:       if.end3458:
45737 // SIMD-ONLY0-NEXT:    [[TMP2318:%.*]] = load i32, ptr [[UIE]], align 4
45738 // SIMD-ONLY0-NEXT:    [[TMP2319:%.*]] = load i32, ptr [[UIX]], align 4
45739 // SIMD-ONLY0-NEXT:    [[CMP3459:%.*]] = icmp ugt i32 [[TMP2318]], [[TMP2319]]
45740 // SIMD-ONLY0-NEXT:    br i1 [[CMP3459]], label [[IF_THEN3461:%.*]], label [[IF_END3462:%.*]]
45741 // SIMD-ONLY0:       if.then3461:
45742 // SIMD-ONLY0-NEXT:    [[TMP2320:%.*]] = load i32, ptr [[UIE]], align 4
45743 // SIMD-ONLY0-NEXT:    store i32 [[TMP2320]], ptr [[UIX]], align 4
45744 // SIMD-ONLY0-NEXT:    br label [[IF_END3462]]
45745 // SIMD-ONLY0:       if.end3462:
45746 // SIMD-ONLY0-NEXT:    [[TMP2321:%.*]] = load i32, ptr [[UIX]], align 4
45747 // SIMD-ONLY0-NEXT:    store i32 [[TMP2321]], ptr [[UIV]], align 4
45748 // SIMD-ONLY0-NEXT:    [[TMP2322:%.*]] = load i32, ptr [[UIX]], align 4
45749 // SIMD-ONLY0-NEXT:    [[TMP2323:%.*]] = load i32, ptr [[UIE]], align 4
45750 // SIMD-ONLY0-NEXT:    [[CMP3463:%.*]] = icmp ugt i32 [[TMP2322]], [[TMP2323]]
45751 // SIMD-ONLY0-NEXT:    br i1 [[CMP3463]], label [[IF_THEN3465:%.*]], label [[IF_END3466:%.*]]
45752 // SIMD-ONLY0:       if.then3465:
45753 // SIMD-ONLY0-NEXT:    [[TMP2324:%.*]] = load i32, ptr [[UIE]], align 4
45754 // SIMD-ONLY0-NEXT:    store i32 [[TMP2324]], ptr [[UIX]], align 4
45755 // SIMD-ONLY0-NEXT:    br label [[IF_END3466]]
45756 // SIMD-ONLY0:       if.end3466:
45757 // SIMD-ONLY0-NEXT:    [[TMP2325:%.*]] = load i32, ptr [[UIX]], align 4
45758 // SIMD-ONLY0-NEXT:    store i32 [[TMP2325]], ptr [[UIV]], align 4
45759 // SIMD-ONLY0-NEXT:    [[TMP2326:%.*]] = load i32, ptr [[UIE]], align 4
45760 // SIMD-ONLY0-NEXT:    [[TMP2327:%.*]] = load i32, ptr [[UIX]], align 4
45761 // SIMD-ONLY0-NEXT:    [[CMP3467:%.*]] = icmp ult i32 [[TMP2326]], [[TMP2327]]
45762 // SIMD-ONLY0-NEXT:    br i1 [[CMP3467]], label [[IF_THEN3469:%.*]], label [[IF_END3470:%.*]]
45763 // SIMD-ONLY0:       if.then3469:
45764 // SIMD-ONLY0-NEXT:    [[TMP2328:%.*]] = load i32, ptr [[UIE]], align 4
45765 // SIMD-ONLY0-NEXT:    store i32 [[TMP2328]], ptr [[UIX]], align 4
45766 // SIMD-ONLY0-NEXT:    br label [[IF_END3470]]
45767 // SIMD-ONLY0:       if.end3470:
45768 // SIMD-ONLY0-NEXT:    [[TMP2329:%.*]] = load i32, ptr [[UIX]], align 4
45769 // SIMD-ONLY0-NEXT:    store i32 [[TMP2329]], ptr [[UIV]], align 4
45770 // SIMD-ONLY0-NEXT:    [[TMP2330:%.*]] = load i32, ptr [[UIX]], align 4
45771 // SIMD-ONLY0-NEXT:    [[TMP2331:%.*]] = load i32, ptr [[UIE]], align 4
45772 // SIMD-ONLY0-NEXT:    [[CMP3471:%.*]] = icmp ult i32 [[TMP2330]], [[TMP2331]]
45773 // SIMD-ONLY0-NEXT:    br i1 [[CMP3471]], label [[IF_THEN3473:%.*]], label [[IF_END3474:%.*]]
45774 // SIMD-ONLY0:       if.then3473:
45775 // SIMD-ONLY0-NEXT:    [[TMP2332:%.*]] = load i32, ptr [[UIE]], align 4
45776 // SIMD-ONLY0-NEXT:    store i32 [[TMP2332]], ptr [[UIX]], align 4
45777 // SIMD-ONLY0-NEXT:    br label [[IF_END3474]]
45778 // SIMD-ONLY0:       if.end3474:
45779 // SIMD-ONLY0-NEXT:    [[TMP2333:%.*]] = load i32, ptr [[UIX]], align 4
45780 // SIMD-ONLY0-NEXT:    store i32 [[TMP2333]], ptr [[UIV]], align 4
45781 // SIMD-ONLY0-NEXT:    [[TMP2334:%.*]] = load i32, ptr [[UIX]], align 4
45782 // SIMD-ONLY0-NEXT:    [[TMP2335:%.*]] = load i32, ptr [[UIE]], align 4
45783 // SIMD-ONLY0-NEXT:    [[CMP3475:%.*]] = icmp eq i32 [[TMP2334]], [[TMP2335]]
45784 // SIMD-ONLY0-NEXT:    br i1 [[CMP3475]], label [[IF_THEN3477:%.*]], label [[IF_END3478:%.*]]
45785 // SIMD-ONLY0:       if.then3477:
45786 // SIMD-ONLY0-NEXT:    [[TMP2336:%.*]] = load i32, ptr [[UID]], align 4
45787 // SIMD-ONLY0-NEXT:    store i32 [[TMP2336]], ptr [[UIX]], align 4
45788 // SIMD-ONLY0-NEXT:    br label [[IF_END3478]]
45789 // SIMD-ONLY0:       if.end3478:
45790 // SIMD-ONLY0-NEXT:    [[TMP2337:%.*]] = load i32, ptr [[UIX]], align 4
45791 // SIMD-ONLY0-NEXT:    store i32 [[TMP2337]], ptr [[UIV]], align 4
45792 // SIMD-ONLY0-NEXT:    [[TMP2338:%.*]] = load i32, ptr [[UIE]], align 4
45793 // SIMD-ONLY0-NEXT:    [[TMP2339:%.*]] = load i32, ptr [[UIX]], align 4
45794 // SIMD-ONLY0-NEXT:    [[CMP3479:%.*]] = icmp eq i32 [[TMP2338]], [[TMP2339]]
45795 // SIMD-ONLY0-NEXT:    br i1 [[CMP3479]], label [[IF_THEN3481:%.*]], label [[IF_END3482:%.*]]
45796 // SIMD-ONLY0:       if.then3481:
45797 // SIMD-ONLY0-NEXT:    [[TMP2340:%.*]] = load i32, ptr [[UID]], align 4
45798 // SIMD-ONLY0-NEXT:    store i32 [[TMP2340]], ptr [[UIX]], align 4
45799 // SIMD-ONLY0-NEXT:    br label [[IF_END3482]]
45800 // SIMD-ONLY0:       if.end3482:
45801 // SIMD-ONLY0-NEXT:    [[TMP2341:%.*]] = load i32, ptr [[UIX]], align 4
45802 // SIMD-ONLY0-NEXT:    store i32 [[TMP2341]], ptr [[UIV]], align 4
45803 // SIMD-ONLY0-NEXT:    [[TMP2342:%.*]] = load i32, ptr [[UIX]], align 4
45804 // SIMD-ONLY0-NEXT:    [[TMP2343:%.*]] = load i32, ptr [[UIE]], align 4
45805 // SIMD-ONLY0-NEXT:    [[CMP3483:%.*]] = icmp eq i32 [[TMP2342]], [[TMP2343]]
45806 // SIMD-ONLY0-NEXT:    br i1 [[CMP3483]], label [[IF_THEN3485:%.*]], label [[IF_ELSE3486:%.*]]
45807 // SIMD-ONLY0:       if.then3485:
45808 // SIMD-ONLY0-NEXT:    [[TMP2344:%.*]] = load i32, ptr [[UID]], align 4
45809 // SIMD-ONLY0-NEXT:    store i32 [[TMP2344]], ptr [[UIX]], align 4
45810 // SIMD-ONLY0-NEXT:    br label [[IF_END3487:%.*]]
45811 // SIMD-ONLY0:       if.else3486:
45812 // SIMD-ONLY0-NEXT:    [[TMP2345:%.*]] = load i32, ptr [[UIX]], align 4
45813 // SIMD-ONLY0-NEXT:    store i32 [[TMP2345]], ptr [[UIV]], align 4
45814 // SIMD-ONLY0-NEXT:    br label [[IF_END3487]]
45815 // SIMD-ONLY0:       if.end3487:
45816 // SIMD-ONLY0-NEXT:    [[TMP2346:%.*]] = load i32, ptr [[UIE]], align 4
45817 // SIMD-ONLY0-NEXT:    [[TMP2347:%.*]] = load i32, ptr [[UIX]], align 4
45818 // SIMD-ONLY0-NEXT:    [[CMP3488:%.*]] = icmp eq i32 [[TMP2346]], [[TMP2347]]
45819 // SIMD-ONLY0-NEXT:    br i1 [[CMP3488]], label [[IF_THEN3490:%.*]], label [[IF_ELSE3491:%.*]]
45820 // SIMD-ONLY0:       if.then3490:
45821 // SIMD-ONLY0-NEXT:    [[TMP2348:%.*]] = load i32, ptr [[UID]], align 4
45822 // SIMD-ONLY0-NEXT:    store i32 [[TMP2348]], ptr [[UIX]], align 4
45823 // SIMD-ONLY0-NEXT:    br label [[IF_END3492:%.*]]
45824 // SIMD-ONLY0:       if.else3491:
45825 // SIMD-ONLY0-NEXT:    [[TMP2349:%.*]] = load i32, ptr [[UIX]], align 4
45826 // SIMD-ONLY0-NEXT:    store i32 [[TMP2349]], ptr [[UIV]], align 4
45827 // SIMD-ONLY0-NEXT:    br label [[IF_END3492]]
45828 // SIMD-ONLY0:       if.end3492:
45829 // SIMD-ONLY0-NEXT:    [[TMP2350:%.*]] = load i32, ptr [[UIX]], align 4
45830 // SIMD-ONLY0-NEXT:    [[TMP2351:%.*]] = load i32, ptr [[UIE]], align 4
45831 // SIMD-ONLY0-NEXT:    [[CMP3493:%.*]] = icmp eq i32 [[TMP2350]], [[TMP2351]]
45832 // SIMD-ONLY0-NEXT:    [[CONV3494:%.*]] = zext i1 [[CMP3493]] to i32
45833 // SIMD-ONLY0-NEXT:    store i32 [[CONV3494]], ptr [[UIR]], align 4
45834 // SIMD-ONLY0-NEXT:    [[TMP2352:%.*]] = load i32, ptr [[UIR]], align 4
45835 // SIMD-ONLY0-NEXT:    [[TOBOOL3495:%.*]] = icmp ne i32 [[TMP2352]], 0
45836 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3495]], label [[IF_THEN3496:%.*]], label [[IF_END3497:%.*]]
45837 // SIMD-ONLY0:       if.then3496:
45838 // SIMD-ONLY0-NEXT:    [[TMP2353:%.*]] = load i32, ptr [[UID]], align 4
45839 // SIMD-ONLY0-NEXT:    store i32 [[TMP2353]], ptr [[UIX]], align 4
45840 // SIMD-ONLY0-NEXT:    br label [[IF_END3497]]
45841 // SIMD-ONLY0:       if.end3497:
45842 // SIMD-ONLY0-NEXT:    [[TMP2354:%.*]] = load i32, ptr [[UIE]], align 4
45843 // SIMD-ONLY0-NEXT:    [[TMP2355:%.*]] = load i32, ptr [[UIX]], align 4
45844 // SIMD-ONLY0-NEXT:    [[CMP3498:%.*]] = icmp eq i32 [[TMP2354]], [[TMP2355]]
45845 // SIMD-ONLY0-NEXT:    [[CONV3499:%.*]] = zext i1 [[CMP3498]] to i32
45846 // SIMD-ONLY0-NEXT:    store i32 [[CONV3499]], ptr [[UIR]], align 4
45847 // SIMD-ONLY0-NEXT:    [[TMP2356:%.*]] = load i32, ptr [[UIR]], align 4
45848 // SIMD-ONLY0-NEXT:    [[TOBOOL3500:%.*]] = icmp ne i32 [[TMP2356]], 0
45849 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3500]], label [[IF_THEN3501:%.*]], label [[IF_END3502:%.*]]
45850 // SIMD-ONLY0:       if.then3501:
45851 // SIMD-ONLY0-NEXT:    [[TMP2357:%.*]] = load i32, ptr [[UID]], align 4
45852 // SIMD-ONLY0-NEXT:    store i32 [[TMP2357]], ptr [[UIX]], align 4
45853 // SIMD-ONLY0-NEXT:    br label [[IF_END3502]]
45854 // SIMD-ONLY0:       if.end3502:
45855 // SIMD-ONLY0-NEXT:    [[TMP2358:%.*]] = load i32, ptr [[UIX]], align 4
45856 // SIMD-ONLY0-NEXT:    [[TMP2359:%.*]] = load i32, ptr [[UIE]], align 4
45857 // SIMD-ONLY0-NEXT:    [[CMP3503:%.*]] = icmp eq i32 [[TMP2358]], [[TMP2359]]
45858 // SIMD-ONLY0-NEXT:    [[CONV3504:%.*]] = zext i1 [[CMP3503]] to i32
45859 // SIMD-ONLY0-NEXT:    store i32 [[CONV3504]], ptr [[UIR]], align 4
45860 // SIMD-ONLY0-NEXT:    [[TMP2360:%.*]] = load i32, ptr [[UIR]], align 4
45861 // SIMD-ONLY0-NEXT:    [[TOBOOL3505:%.*]] = icmp ne i32 [[TMP2360]], 0
45862 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3505]], label [[IF_THEN3506:%.*]], label [[IF_ELSE3507:%.*]]
45863 // SIMD-ONLY0:       if.then3506:
45864 // SIMD-ONLY0-NEXT:    [[TMP2361:%.*]] = load i32, ptr [[UID]], align 4
45865 // SIMD-ONLY0-NEXT:    store i32 [[TMP2361]], ptr [[UIX]], align 4
45866 // SIMD-ONLY0-NEXT:    br label [[IF_END3508:%.*]]
45867 // SIMD-ONLY0:       if.else3507:
45868 // SIMD-ONLY0-NEXT:    [[TMP2362:%.*]] = load i32, ptr [[UIX]], align 4
45869 // SIMD-ONLY0-NEXT:    store i32 [[TMP2362]], ptr [[UIV]], align 4
45870 // SIMD-ONLY0-NEXT:    br label [[IF_END3508]]
45871 // SIMD-ONLY0:       if.end3508:
45872 // SIMD-ONLY0-NEXT:    [[TMP2363:%.*]] = load i32, ptr [[UIE]], align 4
45873 // SIMD-ONLY0-NEXT:    [[TMP2364:%.*]] = load i32, ptr [[UIX]], align 4
45874 // SIMD-ONLY0-NEXT:    [[CMP3509:%.*]] = icmp eq i32 [[TMP2363]], [[TMP2364]]
45875 // SIMD-ONLY0-NEXT:    [[CONV3510:%.*]] = zext i1 [[CMP3509]] to i32
45876 // SIMD-ONLY0-NEXT:    store i32 [[CONV3510]], ptr [[UIR]], align 4
45877 // SIMD-ONLY0-NEXT:    [[TMP2365:%.*]] = load i32, ptr [[UIR]], align 4
45878 // SIMD-ONLY0-NEXT:    [[TOBOOL3511:%.*]] = icmp ne i32 [[TMP2365]], 0
45879 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3511]], label [[IF_THEN3512:%.*]], label [[IF_ELSE3513:%.*]]
45880 // SIMD-ONLY0:       if.then3512:
45881 // SIMD-ONLY0-NEXT:    [[TMP2366:%.*]] = load i32, ptr [[UID]], align 4
45882 // SIMD-ONLY0-NEXT:    store i32 [[TMP2366]], ptr [[UIX]], align 4
45883 // SIMD-ONLY0-NEXT:    br label [[IF_END3514:%.*]]
45884 // SIMD-ONLY0:       if.else3513:
45885 // SIMD-ONLY0-NEXT:    [[TMP2367:%.*]] = load i32, ptr [[UIX]], align 4
45886 // SIMD-ONLY0-NEXT:    store i32 [[TMP2367]], ptr [[UIV]], align 4
45887 // SIMD-ONLY0-NEXT:    br label [[IF_END3514]]
45888 // SIMD-ONLY0:       if.end3514:
45889 // SIMD-ONLY0-NEXT:    [[TMP2368:%.*]] = load i32, ptr [[UIX]], align 4
45890 // SIMD-ONLY0-NEXT:    store i32 [[TMP2368]], ptr [[UIV]], align 4
45891 // SIMD-ONLY0-NEXT:    [[TMP2369:%.*]] = load i32, ptr [[UIE]], align 4
45892 // SIMD-ONLY0-NEXT:    [[TMP2370:%.*]] = load i32, ptr [[UIX]], align 4
45893 // SIMD-ONLY0-NEXT:    [[CMP3515:%.*]] = icmp ugt i32 [[TMP2369]], [[TMP2370]]
45894 // SIMD-ONLY0-NEXT:    br i1 [[CMP3515]], label [[IF_THEN3517:%.*]], label [[IF_END3518:%.*]]
45895 // SIMD-ONLY0:       if.then3517:
45896 // SIMD-ONLY0-NEXT:    [[TMP2371:%.*]] = load i32, ptr [[UIE]], align 4
45897 // SIMD-ONLY0-NEXT:    store i32 [[TMP2371]], ptr [[UIX]], align 4
45898 // SIMD-ONLY0-NEXT:    br label [[IF_END3518]]
45899 // SIMD-ONLY0:       if.end3518:
45900 // SIMD-ONLY0-NEXT:    [[TMP2372:%.*]] = load i32, ptr [[UIX]], align 4
45901 // SIMD-ONLY0-NEXT:    store i32 [[TMP2372]], ptr [[UIV]], align 4
45902 // SIMD-ONLY0-NEXT:    [[TMP2373:%.*]] = load i32, ptr [[UIX]], align 4
45903 // SIMD-ONLY0-NEXT:    [[TMP2374:%.*]] = load i32, ptr [[UIE]], align 4
45904 // SIMD-ONLY0-NEXT:    [[CMP3519:%.*]] = icmp ugt i32 [[TMP2373]], [[TMP2374]]
45905 // SIMD-ONLY0-NEXT:    br i1 [[CMP3519]], label [[IF_THEN3521:%.*]], label [[IF_END3522:%.*]]
45906 // SIMD-ONLY0:       if.then3521:
45907 // SIMD-ONLY0-NEXT:    [[TMP2375:%.*]] = load i32, ptr [[UIE]], align 4
45908 // SIMD-ONLY0-NEXT:    store i32 [[TMP2375]], ptr [[UIX]], align 4
45909 // SIMD-ONLY0-NEXT:    br label [[IF_END3522]]
45910 // SIMD-ONLY0:       if.end3522:
45911 // SIMD-ONLY0-NEXT:    [[TMP2376:%.*]] = load i32, ptr [[UIX]], align 4
45912 // SIMD-ONLY0-NEXT:    store i32 [[TMP2376]], ptr [[UIV]], align 4
45913 // SIMD-ONLY0-NEXT:    [[TMP2377:%.*]] = load i32, ptr [[UIE]], align 4
45914 // SIMD-ONLY0-NEXT:    [[TMP2378:%.*]] = load i32, ptr [[UIX]], align 4
45915 // SIMD-ONLY0-NEXT:    [[CMP3523:%.*]] = icmp ult i32 [[TMP2377]], [[TMP2378]]
45916 // SIMD-ONLY0-NEXT:    br i1 [[CMP3523]], label [[IF_THEN3525:%.*]], label [[IF_END3526:%.*]]
45917 // SIMD-ONLY0:       if.then3525:
45918 // SIMD-ONLY0-NEXT:    [[TMP2379:%.*]] = load i32, ptr [[UIE]], align 4
45919 // SIMD-ONLY0-NEXT:    store i32 [[TMP2379]], ptr [[UIX]], align 4
45920 // SIMD-ONLY0-NEXT:    br label [[IF_END3526]]
45921 // SIMD-ONLY0:       if.end3526:
45922 // SIMD-ONLY0-NEXT:    [[TMP2380:%.*]] = load i32, ptr [[UIX]], align 4
45923 // SIMD-ONLY0-NEXT:    store i32 [[TMP2380]], ptr [[UIV]], align 4
45924 // SIMD-ONLY0-NEXT:    [[TMP2381:%.*]] = load i32, ptr [[UIX]], align 4
45925 // SIMD-ONLY0-NEXT:    [[TMP2382:%.*]] = load i32, ptr [[UIE]], align 4
45926 // SIMD-ONLY0-NEXT:    [[CMP3527:%.*]] = icmp ult i32 [[TMP2381]], [[TMP2382]]
45927 // SIMD-ONLY0-NEXT:    br i1 [[CMP3527]], label [[IF_THEN3529:%.*]], label [[IF_END3530:%.*]]
45928 // SIMD-ONLY0:       if.then3529:
45929 // SIMD-ONLY0-NEXT:    [[TMP2383:%.*]] = load i32, ptr [[UIE]], align 4
45930 // SIMD-ONLY0-NEXT:    store i32 [[TMP2383]], ptr [[UIX]], align 4
45931 // SIMD-ONLY0-NEXT:    br label [[IF_END3530]]
45932 // SIMD-ONLY0:       if.end3530:
45933 // SIMD-ONLY0-NEXT:    [[TMP2384:%.*]] = load i32, ptr [[UIX]], align 4
45934 // SIMD-ONLY0-NEXT:    store i32 [[TMP2384]], ptr [[UIV]], align 4
45935 // SIMD-ONLY0-NEXT:    [[TMP2385:%.*]] = load i32, ptr [[UIX]], align 4
45936 // SIMD-ONLY0-NEXT:    [[TMP2386:%.*]] = load i32, ptr [[UIE]], align 4
45937 // SIMD-ONLY0-NEXT:    [[CMP3531:%.*]] = icmp eq i32 [[TMP2385]], [[TMP2386]]
45938 // SIMD-ONLY0-NEXT:    br i1 [[CMP3531]], label [[IF_THEN3533:%.*]], label [[IF_END3534:%.*]]
45939 // SIMD-ONLY0:       if.then3533:
45940 // SIMD-ONLY0-NEXT:    [[TMP2387:%.*]] = load i32, ptr [[UID]], align 4
45941 // SIMD-ONLY0-NEXT:    store i32 [[TMP2387]], ptr [[UIX]], align 4
45942 // SIMD-ONLY0-NEXT:    br label [[IF_END3534]]
45943 // SIMD-ONLY0:       if.end3534:
45944 // SIMD-ONLY0-NEXT:    [[TMP2388:%.*]] = load i32, ptr [[UIX]], align 4
45945 // SIMD-ONLY0-NEXT:    store i32 [[TMP2388]], ptr [[UIV]], align 4
45946 // SIMD-ONLY0-NEXT:    [[TMP2389:%.*]] = load i32, ptr [[UIE]], align 4
45947 // SIMD-ONLY0-NEXT:    [[TMP2390:%.*]] = load i32, ptr [[UIX]], align 4
45948 // SIMD-ONLY0-NEXT:    [[CMP3535:%.*]] = icmp eq i32 [[TMP2389]], [[TMP2390]]
45949 // SIMD-ONLY0-NEXT:    br i1 [[CMP3535]], label [[IF_THEN3537:%.*]], label [[IF_END3538:%.*]]
45950 // SIMD-ONLY0:       if.then3537:
45951 // SIMD-ONLY0-NEXT:    [[TMP2391:%.*]] = load i32, ptr [[UID]], align 4
45952 // SIMD-ONLY0-NEXT:    store i32 [[TMP2391]], ptr [[UIX]], align 4
45953 // SIMD-ONLY0-NEXT:    br label [[IF_END3538]]
45954 // SIMD-ONLY0:       if.end3538:
45955 // SIMD-ONLY0-NEXT:    [[TMP2392:%.*]] = load i32, ptr [[UIE]], align 4
45956 // SIMD-ONLY0-NEXT:    [[TMP2393:%.*]] = load i32, ptr [[UIX]], align 4
45957 // SIMD-ONLY0-NEXT:    [[CMP3539:%.*]] = icmp ugt i32 [[TMP2392]], [[TMP2393]]
45958 // SIMD-ONLY0-NEXT:    br i1 [[CMP3539]], label [[IF_THEN3541:%.*]], label [[IF_END3542:%.*]]
45959 // SIMD-ONLY0:       if.then3541:
45960 // SIMD-ONLY0-NEXT:    [[TMP2394:%.*]] = load i32, ptr [[UIE]], align 4
45961 // SIMD-ONLY0-NEXT:    store i32 [[TMP2394]], ptr [[UIX]], align 4
45962 // SIMD-ONLY0-NEXT:    br label [[IF_END3542]]
45963 // SIMD-ONLY0:       if.end3542:
45964 // SIMD-ONLY0-NEXT:    [[TMP2395:%.*]] = load i32, ptr [[UIX]], align 4
45965 // SIMD-ONLY0-NEXT:    store i32 [[TMP2395]], ptr [[UIV]], align 4
45966 // SIMD-ONLY0-NEXT:    [[TMP2396:%.*]] = load i32, ptr [[UIX]], align 4
45967 // SIMD-ONLY0-NEXT:    [[TMP2397:%.*]] = load i32, ptr [[UIE]], align 4
45968 // SIMD-ONLY0-NEXT:    [[CMP3543:%.*]] = icmp ugt i32 [[TMP2396]], [[TMP2397]]
45969 // SIMD-ONLY0-NEXT:    br i1 [[CMP3543]], label [[IF_THEN3545:%.*]], label [[IF_END3546:%.*]]
45970 // SIMD-ONLY0:       if.then3545:
45971 // SIMD-ONLY0-NEXT:    [[TMP2398:%.*]] = load i32, ptr [[UIE]], align 4
45972 // SIMD-ONLY0-NEXT:    store i32 [[TMP2398]], ptr [[UIX]], align 4
45973 // SIMD-ONLY0-NEXT:    br label [[IF_END3546]]
45974 // SIMD-ONLY0:       if.end3546:
45975 // SIMD-ONLY0-NEXT:    [[TMP2399:%.*]] = load i32, ptr [[UIX]], align 4
45976 // SIMD-ONLY0-NEXT:    store i32 [[TMP2399]], ptr [[UIV]], align 4
45977 // SIMD-ONLY0-NEXT:    [[TMP2400:%.*]] = load i32, ptr [[UIE]], align 4
45978 // SIMD-ONLY0-NEXT:    [[TMP2401:%.*]] = load i32, ptr [[UIX]], align 4
45979 // SIMD-ONLY0-NEXT:    [[CMP3547:%.*]] = icmp ult i32 [[TMP2400]], [[TMP2401]]
45980 // SIMD-ONLY0-NEXT:    br i1 [[CMP3547]], label [[IF_THEN3549:%.*]], label [[IF_END3550:%.*]]
45981 // SIMD-ONLY0:       if.then3549:
45982 // SIMD-ONLY0-NEXT:    [[TMP2402:%.*]] = load i32, ptr [[UIE]], align 4
45983 // SIMD-ONLY0-NEXT:    store i32 [[TMP2402]], ptr [[UIX]], align 4
45984 // SIMD-ONLY0-NEXT:    br label [[IF_END3550]]
45985 // SIMD-ONLY0:       if.end3550:
45986 // SIMD-ONLY0-NEXT:    [[TMP2403:%.*]] = load i32, ptr [[UIX]], align 4
45987 // SIMD-ONLY0-NEXT:    store i32 [[TMP2403]], ptr [[UIV]], align 4
45988 // SIMD-ONLY0-NEXT:    [[TMP2404:%.*]] = load i32, ptr [[UIX]], align 4
45989 // SIMD-ONLY0-NEXT:    [[TMP2405:%.*]] = load i32, ptr [[UIE]], align 4
45990 // SIMD-ONLY0-NEXT:    [[CMP3551:%.*]] = icmp ult i32 [[TMP2404]], [[TMP2405]]
45991 // SIMD-ONLY0-NEXT:    br i1 [[CMP3551]], label [[IF_THEN3553:%.*]], label [[IF_END3554:%.*]]
45992 // SIMD-ONLY0:       if.then3553:
45993 // SIMD-ONLY0-NEXT:    [[TMP2406:%.*]] = load i32, ptr [[UIE]], align 4
45994 // SIMD-ONLY0-NEXT:    store i32 [[TMP2406]], ptr [[UIX]], align 4
45995 // SIMD-ONLY0-NEXT:    br label [[IF_END3554]]
45996 // SIMD-ONLY0:       if.end3554:
45997 // SIMD-ONLY0-NEXT:    [[TMP2407:%.*]] = load i32, ptr [[UIX]], align 4
45998 // SIMD-ONLY0-NEXT:    store i32 [[TMP2407]], ptr [[UIV]], align 4
45999 // SIMD-ONLY0-NEXT:    [[TMP2408:%.*]] = load i32, ptr [[UIX]], align 4
46000 // SIMD-ONLY0-NEXT:    [[TMP2409:%.*]] = load i32, ptr [[UIE]], align 4
46001 // SIMD-ONLY0-NEXT:    [[CMP3555:%.*]] = icmp eq i32 [[TMP2408]], [[TMP2409]]
46002 // SIMD-ONLY0-NEXT:    br i1 [[CMP3555]], label [[IF_THEN3557:%.*]], label [[IF_END3558:%.*]]
46003 // SIMD-ONLY0:       if.then3557:
46004 // SIMD-ONLY0-NEXT:    [[TMP2410:%.*]] = load i32, ptr [[UID]], align 4
46005 // SIMD-ONLY0-NEXT:    store i32 [[TMP2410]], ptr [[UIX]], align 4
46006 // SIMD-ONLY0-NEXT:    br label [[IF_END3558]]
46007 // SIMD-ONLY0:       if.end3558:
46008 // SIMD-ONLY0-NEXT:    [[TMP2411:%.*]] = load i32, ptr [[UIX]], align 4
46009 // SIMD-ONLY0-NEXT:    store i32 [[TMP2411]], ptr [[UIV]], align 4
46010 // SIMD-ONLY0-NEXT:    [[TMP2412:%.*]] = load i32, ptr [[UIE]], align 4
46011 // SIMD-ONLY0-NEXT:    [[TMP2413:%.*]] = load i32, ptr [[UIX]], align 4
46012 // SIMD-ONLY0-NEXT:    [[CMP3559:%.*]] = icmp eq i32 [[TMP2412]], [[TMP2413]]
46013 // SIMD-ONLY0-NEXT:    br i1 [[CMP3559]], label [[IF_THEN3561:%.*]], label [[IF_END3562:%.*]]
46014 // SIMD-ONLY0:       if.then3561:
46015 // SIMD-ONLY0-NEXT:    [[TMP2414:%.*]] = load i32, ptr [[UID]], align 4
46016 // SIMD-ONLY0-NEXT:    store i32 [[TMP2414]], ptr [[UIX]], align 4
46017 // SIMD-ONLY0-NEXT:    br label [[IF_END3562]]
46018 // SIMD-ONLY0:       if.end3562:
46019 // SIMD-ONLY0-NEXT:    [[TMP2415:%.*]] = load i32, ptr [[UIX]], align 4
46020 // SIMD-ONLY0-NEXT:    store i32 [[TMP2415]], ptr [[UIV]], align 4
46021 // SIMD-ONLY0-NEXT:    [[TMP2416:%.*]] = load i32, ptr [[UIX]], align 4
46022 // SIMD-ONLY0-NEXT:    [[TMP2417:%.*]] = load i32, ptr [[UIE]], align 4
46023 // SIMD-ONLY0-NEXT:    [[CMP3563:%.*]] = icmp eq i32 [[TMP2416]], [[TMP2417]]
46024 // SIMD-ONLY0-NEXT:    br i1 [[CMP3563]], label [[IF_THEN3565:%.*]], label [[IF_ELSE3566:%.*]]
46025 // SIMD-ONLY0:       if.then3565:
46026 // SIMD-ONLY0-NEXT:    [[TMP2418:%.*]] = load i32, ptr [[UID]], align 4
46027 // SIMD-ONLY0-NEXT:    store i32 [[TMP2418]], ptr [[UIX]], align 4
46028 // SIMD-ONLY0-NEXT:    br label [[IF_END3567:%.*]]
46029 // SIMD-ONLY0:       if.else3566:
46030 // SIMD-ONLY0-NEXT:    [[TMP2419:%.*]] = load i32, ptr [[UIX]], align 4
46031 // SIMD-ONLY0-NEXT:    store i32 [[TMP2419]], ptr [[UIV]], align 4
46032 // SIMD-ONLY0-NEXT:    br label [[IF_END3567]]
46033 // SIMD-ONLY0:       if.end3567:
46034 // SIMD-ONLY0-NEXT:    [[TMP2420:%.*]] = load i32, ptr [[UIE]], align 4
46035 // SIMD-ONLY0-NEXT:    [[TMP2421:%.*]] = load i32, ptr [[UIX]], align 4
46036 // SIMD-ONLY0-NEXT:    [[CMP3568:%.*]] = icmp eq i32 [[TMP2420]], [[TMP2421]]
46037 // SIMD-ONLY0-NEXT:    br i1 [[CMP3568]], label [[IF_THEN3570:%.*]], label [[IF_ELSE3571:%.*]]
46038 // SIMD-ONLY0:       if.then3570:
46039 // SIMD-ONLY0-NEXT:    [[TMP2422:%.*]] = load i32, ptr [[UID]], align 4
46040 // SIMD-ONLY0-NEXT:    store i32 [[TMP2422]], ptr [[UIX]], align 4
46041 // SIMD-ONLY0-NEXT:    br label [[IF_END3572:%.*]]
46042 // SIMD-ONLY0:       if.else3571:
46043 // SIMD-ONLY0-NEXT:    [[TMP2423:%.*]] = load i32, ptr [[UIX]], align 4
46044 // SIMD-ONLY0-NEXT:    store i32 [[TMP2423]], ptr [[UIV]], align 4
46045 // SIMD-ONLY0-NEXT:    br label [[IF_END3572]]
46046 // SIMD-ONLY0:       if.end3572:
46047 // SIMD-ONLY0-NEXT:    [[TMP2424:%.*]] = load i32, ptr [[UIX]], align 4
46048 // SIMD-ONLY0-NEXT:    [[TMP2425:%.*]] = load i32, ptr [[UIE]], align 4
46049 // SIMD-ONLY0-NEXT:    [[CMP3573:%.*]] = icmp eq i32 [[TMP2424]], [[TMP2425]]
46050 // SIMD-ONLY0-NEXT:    [[CONV3574:%.*]] = zext i1 [[CMP3573]] to i32
46051 // SIMD-ONLY0-NEXT:    store i32 [[CONV3574]], ptr [[UIR]], align 4
46052 // SIMD-ONLY0-NEXT:    [[TMP2426:%.*]] = load i32, ptr [[UIR]], align 4
46053 // SIMD-ONLY0-NEXT:    [[TOBOOL3575:%.*]] = icmp ne i32 [[TMP2426]], 0
46054 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3575]], label [[IF_THEN3576:%.*]], label [[IF_END3577:%.*]]
46055 // SIMD-ONLY0:       if.then3576:
46056 // SIMD-ONLY0-NEXT:    [[TMP2427:%.*]] = load i32, ptr [[UID]], align 4
46057 // SIMD-ONLY0-NEXT:    store i32 [[TMP2427]], ptr [[UIX]], align 4
46058 // SIMD-ONLY0-NEXT:    br label [[IF_END3577]]
46059 // SIMD-ONLY0:       if.end3577:
46060 // SIMD-ONLY0-NEXT:    [[TMP2428:%.*]] = load i32, ptr [[UIE]], align 4
46061 // SIMD-ONLY0-NEXT:    [[TMP2429:%.*]] = load i32, ptr [[UIX]], align 4
46062 // SIMD-ONLY0-NEXT:    [[CMP3578:%.*]] = icmp eq i32 [[TMP2428]], [[TMP2429]]
46063 // SIMD-ONLY0-NEXT:    [[CONV3579:%.*]] = zext i1 [[CMP3578]] to i32
46064 // SIMD-ONLY0-NEXT:    store i32 [[CONV3579]], ptr [[UIR]], align 4
46065 // SIMD-ONLY0-NEXT:    [[TMP2430:%.*]] = load i32, ptr [[UIR]], align 4
46066 // SIMD-ONLY0-NEXT:    [[TOBOOL3580:%.*]] = icmp ne i32 [[TMP2430]], 0
46067 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3580]], label [[IF_THEN3581:%.*]], label [[IF_END3582:%.*]]
46068 // SIMD-ONLY0:       if.then3581:
46069 // SIMD-ONLY0-NEXT:    [[TMP2431:%.*]] = load i32, ptr [[UID]], align 4
46070 // SIMD-ONLY0-NEXT:    store i32 [[TMP2431]], ptr [[UIX]], align 4
46071 // SIMD-ONLY0-NEXT:    br label [[IF_END3582]]
46072 // SIMD-ONLY0:       if.end3582:
46073 // SIMD-ONLY0-NEXT:    [[TMP2432:%.*]] = load i32, ptr [[UIX]], align 4
46074 // SIMD-ONLY0-NEXT:    [[TMP2433:%.*]] = load i32, ptr [[UIE]], align 4
46075 // SIMD-ONLY0-NEXT:    [[CMP3583:%.*]] = icmp eq i32 [[TMP2432]], [[TMP2433]]
46076 // SIMD-ONLY0-NEXT:    [[CONV3584:%.*]] = zext i1 [[CMP3583]] to i32
46077 // SIMD-ONLY0-NEXT:    store i32 [[CONV3584]], ptr [[UIR]], align 4
46078 // SIMD-ONLY0-NEXT:    [[TMP2434:%.*]] = load i32, ptr [[UIR]], align 4
46079 // SIMD-ONLY0-NEXT:    [[TOBOOL3585:%.*]] = icmp ne i32 [[TMP2434]], 0
46080 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3585]], label [[IF_THEN3586:%.*]], label [[IF_ELSE3587:%.*]]
46081 // SIMD-ONLY0:       if.then3586:
46082 // SIMD-ONLY0-NEXT:    [[TMP2435:%.*]] = load i32, ptr [[UID]], align 4
46083 // SIMD-ONLY0-NEXT:    store i32 [[TMP2435]], ptr [[UIX]], align 4
46084 // SIMD-ONLY0-NEXT:    br label [[IF_END3588:%.*]]
46085 // SIMD-ONLY0:       if.else3587:
46086 // SIMD-ONLY0-NEXT:    [[TMP2436:%.*]] = load i32, ptr [[UIX]], align 4
46087 // SIMD-ONLY0-NEXT:    store i32 [[TMP2436]], ptr [[UIV]], align 4
46088 // SIMD-ONLY0-NEXT:    br label [[IF_END3588]]
46089 // SIMD-ONLY0:       if.end3588:
46090 // SIMD-ONLY0-NEXT:    [[TMP2437:%.*]] = load i32, ptr [[UIE]], align 4
46091 // SIMD-ONLY0-NEXT:    [[TMP2438:%.*]] = load i32, ptr [[UIX]], align 4
46092 // SIMD-ONLY0-NEXT:    [[CMP3589:%.*]] = icmp eq i32 [[TMP2437]], [[TMP2438]]
46093 // SIMD-ONLY0-NEXT:    [[CONV3590:%.*]] = zext i1 [[CMP3589]] to i32
46094 // SIMD-ONLY0-NEXT:    store i32 [[CONV3590]], ptr [[UIR]], align 4
46095 // SIMD-ONLY0-NEXT:    [[TMP2439:%.*]] = load i32, ptr [[UIR]], align 4
46096 // SIMD-ONLY0-NEXT:    [[TOBOOL3591:%.*]] = icmp ne i32 [[TMP2439]], 0
46097 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3591]], label [[IF_THEN3592:%.*]], label [[IF_ELSE3593:%.*]]
46098 // SIMD-ONLY0:       if.then3592:
46099 // SIMD-ONLY0-NEXT:    [[TMP2440:%.*]] = load i32, ptr [[UID]], align 4
46100 // SIMD-ONLY0-NEXT:    store i32 [[TMP2440]], ptr [[UIX]], align 4
46101 // SIMD-ONLY0-NEXT:    br label [[IF_END3594:%.*]]
46102 // SIMD-ONLY0:       if.else3593:
46103 // SIMD-ONLY0-NEXT:    [[TMP2441:%.*]] = load i32, ptr [[UIX]], align 4
46104 // SIMD-ONLY0-NEXT:    store i32 [[TMP2441]], ptr [[UIV]], align 4
46105 // SIMD-ONLY0-NEXT:    br label [[IF_END3594]]
46106 // SIMD-ONLY0:       if.end3594:
46107 // SIMD-ONLY0-NEXT:    [[TMP2442:%.*]] = load i32, ptr [[UIX]], align 4
46108 // SIMD-ONLY0-NEXT:    store i32 [[TMP2442]], ptr [[UIV]], align 4
46109 // SIMD-ONLY0-NEXT:    [[TMP2443:%.*]] = load i32, ptr [[UIE]], align 4
46110 // SIMD-ONLY0-NEXT:    [[TMP2444:%.*]] = load i32, ptr [[UIX]], align 4
46111 // SIMD-ONLY0-NEXT:    [[CMP3595:%.*]] = icmp ugt i32 [[TMP2443]], [[TMP2444]]
46112 // SIMD-ONLY0-NEXT:    br i1 [[CMP3595]], label [[IF_THEN3597:%.*]], label [[IF_END3598:%.*]]
46113 // SIMD-ONLY0:       if.then3597:
46114 // SIMD-ONLY0-NEXT:    [[TMP2445:%.*]] = load i32, ptr [[UIE]], align 4
46115 // SIMD-ONLY0-NEXT:    store i32 [[TMP2445]], ptr [[UIX]], align 4
46116 // SIMD-ONLY0-NEXT:    br label [[IF_END3598]]
46117 // SIMD-ONLY0:       if.end3598:
46118 // SIMD-ONLY0-NEXT:    [[TMP2446:%.*]] = load i32, ptr [[UIX]], align 4
46119 // SIMD-ONLY0-NEXT:    store i32 [[TMP2446]], ptr [[UIV]], align 4
46120 // SIMD-ONLY0-NEXT:    [[TMP2447:%.*]] = load i32, ptr [[UIX]], align 4
46121 // SIMD-ONLY0-NEXT:    [[TMP2448:%.*]] = load i32, ptr [[UIE]], align 4
46122 // SIMD-ONLY0-NEXT:    [[CMP3599:%.*]] = icmp ugt i32 [[TMP2447]], [[TMP2448]]
46123 // SIMD-ONLY0-NEXT:    br i1 [[CMP3599]], label [[IF_THEN3601:%.*]], label [[IF_END3602:%.*]]
46124 // SIMD-ONLY0:       if.then3601:
46125 // SIMD-ONLY0-NEXT:    [[TMP2449:%.*]] = load i32, ptr [[UIE]], align 4
46126 // SIMD-ONLY0-NEXT:    store i32 [[TMP2449]], ptr [[UIX]], align 4
46127 // SIMD-ONLY0-NEXT:    br label [[IF_END3602]]
46128 // SIMD-ONLY0:       if.end3602:
46129 // SIMD-ONLY0-NEXT:    [[TMP2450:%.*]] = load i32, ptr [[UIX]], align 4
46130 // SIMD-ONLY0-NEXT:    store i32 [[TMP2450]], ptr [[UIV]], align 4
46131 // SIMD-ONLY0-NEXT:    [[TMP2451:%.*]] = load i32, ptr [[UIE]], align 4
46132 // SIMD-ONLY0-NEXT:    [[TMP2452:%.*]] = load i32, ptr [[UIX]], align 4
46133 // SIMD-ONLY0-NEXT:    [[CMP3603:%.*]] = icmp ult i32 [[TMP2451]], [[TMP2452]]
46134 // SIMD-ONLY0-NEXT:    br i1 [[CMP3603]], label [[IF_THEN3605:%.*]], label [[IF_END3606:%.*]]
46135 // SIMD-ONLY0:       if.then3605:
46136 // SIMD-ONLY0-NEXT:    [[TMP2453:%.*]] = load i32, ptr [[UIE]], align 4
46137 // SIMD-ONLY0-NEXT:    store i32 [[TMP2453]], ptr [[UIX]], align 4
46138 // SIMD-ONLY0-NEXT:    br label [[IF_END3606]]
46139 // SIMD-ONLY0:       if.end3606:
46140 // SIMD-ONLY0-NEXT:    [[TMP2454:%.*]] = load i32, ptr [[UIX]], align 4
46141 // SIMD-ONLY0-NEXT:    store i32 [[TMP2454]], ptr [[UIV]], align 4
46142 // SIMD-ONLY0-NEXT:    [[TMP2455:%.*]] = load i32, ptr [[UIX]], align 4
46143 // SIMD-ONLY0-NEXT:    [[TMP2456:%.*]] = load i32, ptr [[UIE]], align 4
46144 // SIMD-ONLY0-NEXT:    [[CMP3607:%.*]] = icmp ult i32 [[TMP2455]], [[TMP2456]]
46145 // SIMD-ONLY0-NEXT:    br i1 [[CMP3607]], label [[IF_THEN3609:%.*]], label [[IF_END3610:%.*]]
46146 // SIMD-ONLY0:       if.then3609:
46147 // SIMD-ONLY0-NEXT:    [[TMP2457:%.*]] = load i32, ptr [[UIE]], align 4
46148 // SIMD-ONLY0-NEXT:    store i32 [[TMP2457]], ptr [[UIX]], align 4
46149 // SIMD-ONLY0-NEXT:    br label [[IF_END3610]]
46150 // SIMD-ONLY0:       if.end3610:
46151 // SIMD-ONLY0-NEXT:    [[TMP2458:%.*]] = load i32, ptr [[UIX]], align 4
46152 // SIMD-ONLY0-NEXT:    store i32 [[TMP2458]], ptr [[UIV]], align 4
46153 // SIMD-ONLY0-NEXT:    [[TMP2459:%.*]] = load i32, ptr [[UIX]], align 4
46154 // SIMD-ONLY0-NEXT:    [[TMP2460:%.*]] = load i32, ptr [[UIE]], align 4
46155 // SIMD-ONLY0-NEXT:    [[CMP3611:%.*]] = icmp eq i32 [[TMP2459]], [[TMP2460]]
46156 // SIMD-ONLY0-NEXT:    br i1 [[CMP3611]], label [[IF_THEN3613:%.*]], label [[IF_END3614:%.*]]
46157 // SIMD-ONLY0:       if.then3613:
46158 // SIMD-ONLY0-NEXT:    [[TMP2461:%.*]] = load i32, ptr [[UID]], align 4
46159 // SIMD-ONLY0-NEXT:    store i32 [[TMP2461]], ptr [[UIX]], align 4
46160 // SIMD-ONLY0-NEXT:    br label [[IF_END3614]]
46161 // SIMD-ONLY0:       if.end3614:
46162 // SIMD-ONLY0-NEXT:    [[TMP2462:%.*]] = load i32, ptr [[UIX]], align 4
46163 // SIMD-ONLY0-NEXT:    store i32 [[TMP2462]], ptr [[UIV]], align 4
46164 // SIMD-ONLY0-NEXT:    [[TMP2463:%.*]] = load i32, ptr [[UIE]], align 4
46165 // SIMD-ONLY0-NEXT:    [[TMP2464:%.*]] = load i32, ptr [[UIX]], align 4
46166 // SIMD-ONLY0-NEXT:    [[CMP3615:%.*]] = icmp eq i32 [[TMP2463]], [[TMP2464]]
46167 // SIMD-ONLY0-NEXT:    br i1 [[CMP3615]], label [[IF_THEN3617:%.*]], label [[IF_END3618:%.*]]
46168 // SIMD-ONLY0:       if.then3617:
46169 // SIMD-ONLY0-NEXT:    [[TMP2465:%.*]] = load i32, ptr [[UID]], align 4
46170 // SIMD-ONLY0-NEXT:    store i32 [[TMP2465]], ptr [[UIX]], align 4
46171 // SIMD-ONLY0-NEXT:    br label [[IF_END3618]]
46172 // SIMD-ONLY0:       if.end3618:
46173 // SIMD-ONLY0-NEXT:    [[TMP2466:%.*]] = load i32, ptr [[UIE]], align 4
46174 // SIMD-ONLY0-NEXT:    [[TMP2467:%.*]] = load i32, ptr [[UIX]], align 4
46175 // SIMD-ONLY0-NEXT:    [[CMP3619:%.*]] = icmp ugt i32 [[TMP2466]], [[TMP2467]]
46176 // SIMD-ONLY0-NEXT:    br i1 [[CMP3619]], label [[IF_THEN3621:%.*]], label [[IF_END3622:%.*]]
46177 // SIMD-ONLY0:       if.then3621:
46178 // SIMD-ONLY0-NEXT:    [[TMP2468:%.*]] = load i32, ptr [[UIE]], align 4
46179 // SIMD-ONLY0-NEXT:    store i32 [[TMP2468]], ptr [[UIX]], align 4
46180 // SIMD-ONLY0-NEXT:    br label [[IF_END3622]]
46181 // SIMD-ONLY0:       if.end3622:
46182 // SIMD-ONLY0-NEXT:    [[TMP2469:%.*]] = load i32, ptr [[UIX]], align 4
46183 // SIMD-ONLY0-NEXT:    store i32 [[TMP2469]], ptr [[UIV]], align 4
46184 // SIMD-ONLY0-NEXT:    [[TMP2470:%.*]] = load i32, ptr [[UIX]], align 4
46185 // SIMD-ONLY0-NEXT:    [[TMP2471:%.*]] = load i32, ptr [[UIE]], align 4
46186 // SIMD-ONLY0-NEXT:    [[CMP3623:%.*]] = icmp ugt i32 [[TMP2470]], [[TMP2471]]
46187 // SIMD-ONLY0-NEXT:    br i1 [[CMP3623]], label [[IF_THEN3625:%.*]], label [[IF_END3626:%.*]]
46188 // SIMD-ONLY0:       if.then3625:
46189 // SIMD-ONLY0-NEXT:    [[TMP2472:%.*]] = load i32, ptr [[UIE]], align 4
46190 // SIMD-ONLY0-NEXT:    store i32 [[TMP2472]], ptr [[UIX]], align 4
46191 // SIMD-ONLY0-NEXT:    br label [[IF_END3626]]
46192 // SIMD-ONLY0:       if.end3626:
46193 // SIMD-ONLY0-NEXT:    [[TMP2473:%.*]] = load i32, ptr [[UIX]], align 4
46194 // SIMD-ONLY0-NEXT:    store i32 [[TMP2473]], ptr [[UIV]], align 4
46195 // SIMD-ONLY0-NEXT:    [[TMP2474:%.*]] = load i32, ptr [[UIE]], align 4
46196 // SIMD-ONLY0-NEXT:    [[TMP2475:%.*]] = load i32, ptr [[UIX]], align 4
46197 // SIMD-ONLY0-NEXT:    [[CMP3627:%.*]] = icmp ult i32 [[TMP2474]], [[TMP2475]]
46198 // SIMD-ONLY0-NEXT:    br i1 [[CMP3627]], label [[IF_THEN3629:%.*]], label [[IF_END3630:%.*]]
46199 // SIMD-ONLY0:       if.then3629:
46200 // SIMD-ONLY0-NEXT:    [[TMP2476:%.*]] = load i32, ptr [[UIE]], align 4
46201 // SIMD-ONLY0-NEXT:    store i32 [[TMP2476]], ptr [[UIX]], align 4
46202 // SIMD-ONLY0-NEXT:    br label [[IF_END3630]]
46203 // SIMD-ONLY0:       if.end3630:
46204 // SIMD-ONLY0-NEXT:    [[TMP2477:%.*]] = load i32, ptr [[UIX]], align 4
46205 // SIMD-ONLY0-NEXT:    store i32 [[TMP2477]], ptr [[UIV]], align 4
46206 // SIMD-ONLY0-NEXT:    [[TMP2478:%.*]] = load i32, ptr [[UIX]], align 4
46207 // SIMD-ONLY0-NEXT:    [[TMP2479:%.*]] = load i32, ptr [[UIE]], align 4
46208 // SIMD-ONLY0-NEXT:    [[CMP3631:%.*]] = icmp ult i32 [[TMP2478]], [[TMP2479]]
46209 // SIMD-ONLY0-NEXT:    br i1 [[CMP3631]], label [[IF_THEN3633:%.*]], label [[IF_END3634:%.*]]
46210 // SIMD-ONLY0:       if.then3633:
46211 // SIMD-ONLY0-NEXT:    [[TMP2480:%.*]] = load i32, ptr [[UIE]], align 4
46212 // SIMD-ONLY0-NEXT:    store i32 [[TMP2480]], ptr [[UIX]], align 4
46213 // SIMD-ONLY0-NEXT:    br label [[IF_END3634]]
46214 // SIMD-ONLY0:       if.end3634:
46215 // SIMD-ONLY0-NEXT:    [[TMP2481:%.*]] = load i32, ptr [[UIX]], align 4
46216 // SIMD-ONLY0-NEXT:    store i32 [[TMP2481]], ptr [[UIV]], align 4
46217 // SIMD-ONLY0-NEXT:    [[TMP2482:%.*]] = load i32, ptr [[UIX]], align 4
46218 // SIMD-ONLY0-NEXT:    [[TMP2483:%.*]] = load i32, ptr [[UIE]], align 4
46219 // SIMD-ONLY0-NEXT:    [[CMP3635:%.*]] = icmp eq i32 [[TMP2482]], [[TMP2483]]
46220 // SIMD-ONLY0-NEXT:    br i1 [[CMP3635]], label [[IF_THEN3637:%.*]], label [[IF_END3638:%.*]]
46221 // SIMD-ONLY0:       if.then3637:
46222 // SIMD-ONLY0-NEXT:    [[TMP2484:%.*]] = load i32, ptr [[UID]], align 4
46223 // SIMD-ONLY0-NEXT:    store i32 [[TMP2484]], ptr [[UIX]], align 4
46224 // SIMD-ONLY0-NEXT:    br label [[IF_END3638]]
46225 // SIMD-ONLY0:       if.end3638:
46226 // SIMD-ONLY0-NEXT:    [[TMP2485:%.*]] = load i32, ptr [[UIX]], align 4
46227 // SIMD-ONLY0-NEXT:    store i32 [[TMP2485]], ptr [[UIV]], align 4
46228 // SIMD-ONLY0-NEXT:    [[TMP2486:%.*]] = load i32, ptr [[UIE]], align 4
46229 // SIMD-ONLY0-NEXT:    [[TMP2487:%.*]] = load i32, ptr [[UIX]], align 4
46230 // SIMD-ONLY0-NEXT:    [[CMP3639:%.*]] = icmp eq i32 [[TMP2486]], [[TMP2487]]
46231 // SIMD-ONLY0-NEXT:    br i1 [[CMP3639]], label [[IF_THEN3641:%.*]], label [[IF_END3642:%.*]]
46232 // SIMD-ONLY0:       if.then3641:
46233 // SIMD-ONLY0-NEXT:    [[TMP2488:%.*]] = load i32, ptr [[UID]], align 4
46234 // SIMD-ONLY0-NEXT:    store i32 [[TMP2488]], ptr [[UIX]], align 4
46235 // SIMD-ONLY0-NEXT:    br label [[IF_END3642]]
46236 // SIMD-ONLY0:       if.end3642:
46237 // SIMD-ONLY0-NEXT:    [[TMP2489:%.*]] = load i32, ptr [[UIX]], align 4
46238 // SIMD-ONLY0-NEXT:    store i32 [[TMP2489]], ptr [[UIV]], align 4
46239 // SIMD-ONLY0-NEXT:    [[TMP2490:%.*]] = load i32, ptr [[UIX]], align 4
46240 // SIMD-ONLY0-NEXT:    [[TMP2491:%.*]] = load i32, ptr [[UIE]], align 4
46241 // SIMD-ONLY0-NEXT:    [[CMP3643:%.*]] = icmp eq i32 [[TMP2490]], [[TMP2491]]
46242 // SIMD-ONLY0-NEXT:    br i1 [[CMP3643]], label [[IF_THEN3645:%.*]], label [[IF_ELSE3646:%.*]]
46243 // SIMD-ONLY0:       if.then3645:
46244 // SIMD-ONLY0-NEXT:    [[TMP2492:%.*]] = load i32, ptr [[UID]], align 4
46245 // SIMD-ONLY0-NEXT:    store i32 [[TMP2492]], ptr [[UIX]], align 4
46246 // SIMD-ONLY0-NEXT:    br label [[IF_END3647:%.*]]
46247 // SIMD-ONLY0:       if.else3646:
46248 // SIMD-ONLY0-NEXT:    [[TMP2493:%.*]] = load i32, ptr [[UIX]], align 4
46249 // SIMD-ONLY0-NEXT:    store i32 [[TMP2493]], ptr [[UIV]], align 4
46250 // SIMD-ONLY0-NEXT:    br label [[IF_END3647]]
46251 // SIMD-ONLY0:       if.end3647:
46252 // SIMD-ONLY0-NEXT:    [[TMP2494:%.*]] = load i32, ptr [[UIE]], align 4
46253 // SIMD-ONLY0-NEXT:    [[TMP2495:%.*]] = load i32, ptr [[UIX]], align 4
46254 // SIMD-ONLY0-NEXT:    [[CMP3648:%.*]] = icmp eq i32 [[TMP2494]], [[TMP2495]]
46255 // SIMD-ONLY0-NEXT:    br i1 [[CMP3648]], label [[IF_THEN3650:%.*]], label [[IF_ELSE3651:%.*]]
46256 // SIMD-ONLY0:       if.then3650:
46257 // SIMD-ONLY0-NEXT:    [[TMP2496:%.*]] = load i32, ptr [[UID]], align 4
46258 // SIMD-ONLY0-NEXT:    store i32 [[TMP2496]], ptr [[UIX]], align 4
46259 // SIMD-ONLY0-NEXT:    br label [[IF_END3652:%.*]]
46260 // SIMD-ONLY0:       if.else3651:
46261 // SIMD-ONLY0-NEXT:    [[TMP2497:%.*]] = load i32, ptr [[UIX]], align 4
46262 // SIMD-ONLY0-NEXT:    store i32 [[TMP2497]], ptr [[UIV]], align 4
46263 // SIMD-ONLY0-NEXT:    br label [[IF_END3652]]
46264 // SIMD-ONLY0:       if.end3652:
46265 // SIMD-ONLY0-NEXT:    [[TMP2498:%.*]] = load i32, ptr [[UIX]], align 4
46266 // SIMD-ONLY0-NEXT:    [[TMP2499:%.*]] = load i32, ptr [[UIE]], align 4
46267 // SIMD-ONLY0-NEXT:    [[CMP3653:%.*]] = icmp eq i32 [[TMP2498]], [[TMP2499]]
46268 // SIMD-ONLY0-NEXT:    [[CONV3654:%.*]] = zext i1 [[CMP3653]] to i32
46269 // SIMD-ONLY0-NEXT:    store i32 [[CONV3654]], ptr [[UIR]], align 4
46270 // SIMD-ONLY0-NEXT:    [[TMP2500:%.*]] = load i32, ptr [[UIR]], align 4
46271 // SIMD-ONLY0-NEXT:    [[TOBOOL3655:%.*]] = icmp ne i32 [[TMP2500]], 0
46272 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3655]], label [[IF_THEN3656:%.*]], label [[IF_END3657:%.*]]
46273 // SIMD-ONLY0:       if.then3656:
46274 // SIMD-ONLY0-NEXT:    [[TMP2501:%.*]] = load i32, ptr [[UID]], align 4
46275 // SIMD-ONLY0-NEXT:    store i32 [[TMP2501]], ptr [[UIX]], align 4
46276 // SIMD-ONLY0-NEXT:    br label [[IF_END3657]]
46277 // SIMD-ONLY0:       if.end3657:
46278 // SIMD-ONLY0-NEXT:    [[TMP2502:%.*]] = load i32, ptr [[UIE]], align 4
46279 // SIMD-ONLY0-NEXT:    [[TMP2503:%.*]] = load i32, ptr [[UIX]], align 4
46280 // SIMD-ONLY0-NEXT:    [[CMP3658:%.*]] = icmp eq i32 [[TMP2502]], [[TMP2503]]
46281 // SIMD-ONLY0-NEXT:    [[CONV3659:%.*]] = zext i1 [[CMP3658]] to i32
46282 // SIMD-ONLY0-NEXT:    store i32 [[CONV3659]], ptr [[UIR]], align 4
46283 // SIMD-ONLY0-NEXT:    [[TMP2504:%.*]] = load i32, ptr [[UIR]], align 4
46284 // SIMD-ONLY0-NEXT:    [[TOBOOL3660:%.*]] = icmp ne i32 [[TMP2504]], 0
46285 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3660]], label [[IF_THEN3661:%.*]], label [[IF_END3662:%.*]]
46286 // SIMD-ONLY0:       if.then3661:
46287 // SIMD-ONLY0-NEXT:    [[TMP2505:%.*]] = load i32, ptr [[UID]], align 4
46288 // SIMD-ONLY0-NEXT:    store i32 [[TMP2505]], ptr [[UIX]], align 4
46289 // SIMD-ONLY0-NEXT:    br label [[IF_END3662]]
46290 // SIMD-ONLY0:       if.end3662:
46291 // SIMD-ONLY0-NEXT:    [[TMP2506:%.*]] = load i32, ptr [[UIX]], align 4
46292 // SIMD-ONLY0-NEXT:    [[TMP2507:%.*]] = load i32, ptr [[UIE]], align 4
46293 // SIMD-ONLY0-NEXT:    [[CMP3663:%.*]] = icmp eq i32 [[TMP2506]], [[TMP2507]]
46294 // SIMD-ONLY0-NEXT:    [[CONV3664:%.*]] = zext i1 [[CMP3663]] to i32
46295 // SIMD-ONLY0-NEXT:    store i32 [[CONV3664]], ptr [[UIR]], align 4
46296 // SIMD-ONLY0-NEXT:    [[TMP2508:%.*]] = load i32, ptr [[UIR]], align 4
46297 // SIMD-ONLY0-NEXT:    [[TOBOOL3665:%.*]] = icmp ne i32 [[TMP2508]], 0
46298 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3665]], label [[IF_THEN3666:%.*]], label [[IF_ELSE3667:%.*]]
46299 // SIMD-ONLY0:       if.then3666:
46300 // SIMD-ONLY0-NEXT:    [[TMP2509:%.*]] = load i32, ptr [[UID]], align 4
46301 // SIMD-ONLY0-NEXT:    store i32 [[TMP2509]], ptr [[UIX]], align 4
46302 // SIMD-ONLY0-NEXT:    br label [[IF_END3668:%.*]]
46303 // SIMD-ONLY0:       if.else3667:
46304 // SIMD-ONLY0-NEXT:    [[TMP2510:%.*]] = load i32, ptr [[UIX]], align 4
46305 // SIMD-ONLY0-NEXT:    store i32 [[TMP2510]], ptr [[UIV]], align 4
46306 // SIMD-ONLY0-NEXT:    br label [[IF_END3668]]
46307 // SIMD-ONLY0:       if.end3668:
46308 // SIMD-ONLY0-NEXT:    [[TMP2511:%.*]] = load i32, ptr [[UIE]], align 4
46309 // SIMD-ONLY0-NEXT:    [[TMP2512:%.*]] = load i32, ptr [[UIX]], align 4
46310 // SIMD-ONLY0-NEXT:    [[CMP3669:%.*]] = icmp eq i32 [[TMP2511]], [[TMP2512]]
46311 // SIMD-ONLY0-NEXT:    [[CONV3670:%.*]] = zext i1 [[CMP3669]] to i32
46312 // SIMD-ONLY0-NEXT:    store i32 [[CONV3670]], ptr [[UIR]], align 4
46313 // SIMD-ONLY0-NEXT:    [[TMP2513:%.*]] = load i32, ptr [[UIR]], align 4
46314 // SIMD-ONLY0-NEXT:    [[TOBOOL3671:%.*]] = icmp ne i32 [[TMP2513]], 0
46315 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3671]], label [[IF_THEN3672:%.*]], label [[IF_ELSE3673:%.*]]
46316 // SIMD-ONLY0:       if.then3672:
46317 // SIMD-ONLY0-NEXT:    [[TMP2514:%.*]] = load i32, ptr [[UID]], align 4
46318 // SIMD-ONLY0-NEXT:    store i32 [[TMP2514]], ptr [[UIX]], align 4
46319 // SIMD-ONLY0-NEXT:    br label [[IF_END3674:%.*]]
46320 // SIMD-ONLY0:       if.else3673:
46321 // SIMD-ONLY0-NEXT:    [[TMP2515:%.*]] = load i32, ptr [[UIX]], align 4
46322 // SIMD-ONLY0-NEXT:    store i32 [[TMP2515]], ptr [[UIV]], align 4
46323 // SIMD-ONLY0-NEXT:    br label [[IF_END3674]]
46324 // SIMD-ONLY0:       if.end3674:
46325 // SIMD-ONLY0-NEXT:    [[TMP2516:%.*]] = load i32, ptr [[UIX]], align 4
46326 // SIMD-ONLY0-NEXT:    store i32 [[TMP2516]], ptr [[UIV]], align 4
46327 // SIMD-ONLY0-NEXT:    [[TMP2517:%.*]] = load i32, ptr [[UIE]], align 4
46328 // SIMD-ONLY0-NEXT:    [[TMP2518:%.*]] = load i32, ptr [[UIX]], align 4
46329 // SIMD-ONLY0-NEXT:    [[CMP3675:%.*]] = icmp ugt i32 [[TMP2517]], [[TMP2518]]
46330 // SIMD-ONLY0-NEXT:    br i1 [[CMP3675]], label [[IF_THEN3677:%.*]], label [[IF_END3678:%.*]]
46331 // SIMD-ONLY0:       if.then3677:
46332 // SIMD-ONLY0-NEXT:    [[TMP2519:%.*]] = load i32, ptr [[UIE]], align 4
46333 // SIMD-ONLY0-NEXT:    store i32 [[TMP2519]], ptr [[UIX]], align 4
46334 // SIMD-ONLY0-NEXT:    br label [[IF_END3678]]
46335 // SIMD-ONLY0:       if.end3678:
46336 // SIMD-ONLY0-NEXT:    [[TMP2520:%.*]] = load i32, ptr [[UIX]], align 4
46337 // SIMD-ONLY0-NEXT:    store i32 [[TMP2520]], ptr [[UIV]], align 4
46338 // SIMD-ONLY0-NEXT:    [[TMP2521:%.*]] = load i32, ptr [[UIX]], align 4
46339 // SIMD-ONLY0-NEXT:    [[TMP2522:%.*]] = load i32, ptr [[UIE]], align 4
46340 // SIMD-ONLY0-NEXT:    [[CMP3679:%.*]] = icmp ugt i32 [[TMP2521]], [[TMP2522]]
46341 // SIMD-ONLY0-NEXT:    br i1 [[CMP3679]], label [[IF_THEN3681:%.*]], label [[IF_END3682:%.*]]
46342 // SIMD-ONLY0:       if.then3681:
46343 // SIMD-ONLY0-NEXT:    [[TMP2523:%.*]] = load i32, ptr [[UIE]], align 4
46344 // SIMD-ONLY0-NEXT:    store i32 [[TMP2523]], ptr [[UIX]], align 4
46345 // SIMD-ONLY0-NEXT:    br label [[IF_END3682]]
46346 // SIMD-ONLY0:       if.end3682:
46347 // SIMD-ONLY0-NEXT:    [[TMP2524:%.*]] = load i32, ptr [[UIX]], align 4
46348 // SIMD-ONLY0-NEXT:    store i32 [[TMP2524]], ptr [[UIV]], align 4
46349 // SIMD-ONLY0-NEXT:    [[TMP2525:%.*]] = load i32, ptr [[UIE]], align 4
46350 // SIMD-ONLY0-NEXT:    [[TMP2526:%.*]] = load i32, ptr [[UIX]], align 4
46351 // SIMD-ONLY0-NEXT:    [[CMP3683:%.*]] = icmp ult i32 [[TMP2525]], [[TMP2526]]
46352 // SIMD-ONLY0-NEXT:    br i1 [[CMP3683]], label [[IF_THEN3685:%.*]], label [[IF_END3686:%.*]]
46353 // SIMD-ONLY0:       if.then3685:
46354 // SIMD-ONLY0-NEXT:    [[TMP2527:%.*]] = load i32, ptr [[UIE]], align 4
46355 // SIMD-ONLY0-NEXT:    store i32 [[TMP2527]], ptr [[UIX]], align 4
46356 // SIMD-ONLY0-NEXT:    br label [[IF_END3686]]
46357 // SIMD-ONLY0:       if.end3686:
46358 // SIMD-ONLY0-NEXT:    [[TMP2528:%.*]] = load i32, ptr [[UIX]], align 4
46359 // SIMD-ONLY0-NEXT:    store i32 [[TMP2528]], ptr [[UIV]], align 4
46360 // SIMD-ONLY0-NEXT:    [[TMP2529:%.*]] = load i32, ptr [[UIX]], align 4
46361 // SIMD-ONLY0-NEXT:    [[TMP2530:%.*]] = load i32, ptr [[UIE]], align 4
46362 // SIMD-ONLY0-NEXT:    [[CMP3687:%.*]] = icmp ult i32 [[TMP2529]], [[TMP2530]]
46363 // SIMD-ONLY0-NEXT:    br i1 [[CMP3687]], label [[IF_THEN3689:%.*]], label [[IF_END3690:%.*]]
46364 // SIMD-ONLY0:       if.then3689:
46365 // SIMD-ONLY0-NEXT:    [[TMP2531:%.*]] = load i32, ptr [[UIE]], align 4
46366 // SIMD-ONLY0-NEXT:    store i32 [[TMP2531]], ptr [[UIX]], align 4
46367 // SIMD-ONLY0-NEXT:    br label [[IF_END3690]]
46368 // SIMD-ONLY0:       if.end3690:
46369 // SIMD-ONLY0-NEXT:    [[TMP2532:%.*]] = load i32, ptr [[UIX]], align 4
46370 // SIMD-ONLY0-NEXT:    store i32 [[TMP2532]], ptr [[UIV]], align 4
46371 // SIMD-ONLY0-NEXT:    [[TMP2533:%.*]] = load i32, ptr [[UIX]], align 4
46372 // SIMD-ONLY0-NEXT:    [[TMP2534:%.*]] = load i32, ptr [[UIE]], align 4
46373 // SIMD-ONLY0-NEXT:    [[CMP3691:%.*]] = icmp eq i32 [[TMP2533]], [[TMP2534]]
46374 // SIMD-ONLY0-NEXT:    br i1 [[CMP3691]], label [[IF_THEN3693:%.*]], label [[IF_END3694:%.*]]
46375 // SIMD-ONLY0:       if.then3693:
46376 // SIMD-ONLY0-NEXT:    [[TMP2535:%.*]] = load i32, ptr [[UID]], align 4
46377 // SIMD-ONLY0-NEXT:    store i32 [[TMP2535]], ptr [[UIX]], align 4
46378 // SIMD-ONLY0-NEXT:    br label [[IF_END3694]]
46379 // SIMD-ONLY0:       if.end3694:
46380 // SIMD-ONLY0-NEXT:    [[TMP2536:%.*]] = load i32, ptr [[UIX]], align 4
46381 // SIMD-ONLY0-NEXT:    store i32 [[TMP2536]], ptr [[UIV]], align 4
46382 // SIMD-ONLY0-NEXT:    [[TMP2537:%.*]] = load i32, ptr [[UIE]], align 4
46383 // SIMD-ONLY0-NEXT:    [[TMP2538:%.*]] = load i32, ptr [[UIX]], align 4
46384 // SIMD-ONLY0-NEXT:    [[CMP3695:%.*]] = icmp eq i32 [[TMP2537]], [[TMP2538]]
46385 // SIMD-ONLY0-NEXT:    br i1 [[CMP3695]], label [[IF_THEN3697:%.*]], label [[IF_END3698:%.*]]
46386 // SIMD-ONLY0:       if.then3697:
46387 // SIMD-ONLY0-NEXT:    [[TMP2539:%.*]] = load i32, ptr [[UID]], align 4
46388 // SIMD-ONLY0-NEXT:    store i32 [[TMP2539]], ptr [[UIX]], align 4
46389 // SIMD-ONLY0-NEXT:    br label [[IF_END3698]]
46390 // SIMD-ONLY0:       if.end3698:
46391 // SIMD-ONLY0-NEXT:    [[TMP2540:%.*]] = load i32, ptr [[UIE]], align 4
46392 // SIMD-ONLY0-NEXT:    [[TMP2541:%.*]] = load i32, ptr [[UIX]], align 4
46393 // SIMD-ONLY0-NEXT:    [[CMP3699:%.*]] = icmp ugt i32 [[TMP2540]], [[TMP2541]]
46394 // SIMD-ONLY0-NEXT:    br i1 [[CMP3699]], label [[IF_THEN3701:%.*]], label [[IF_END3702:%.*]]
46395 // SIMD-ONLY0:       if.then3701:
46396 // SIMD-ONLY0-NEXT:    [[TMP2542:%.*]] = load i32, ptr [[UIE]], align 4
46397 // SIMD-ONLY0-NEXT:    store i32 [[TMP2542]], ptr [[UIX]], align 4
46398 // SIMD-ONLY0-NEXT:    br label [[IF_END3702]]
46399 // SIMD-ONLY0:       if.end3702:
46400 // SIMD-ONLY0-NEXT:    [[TMP2543:%.*]] = load i32, ptr [[UIX]], align 4
46401 // SIMD-ONLY0-NEXT:    store i32 [[TMP2543]], ptr [[UIV]], align 4
46402 // SIMD-ONLY0-NEXT:    [[TMP2544:%.*]] = load i32, ptr [[UIX]], align 4
46403 // SIMD-ONLY0-NEXT:    [[TMP2545:%.*]] = load i32, ptr [[UIE]], align 4
46404 // SIMD-ONLY0-NEXT:    [[CMP3703:%.*]] = icmp ugt i32 [[TMP2544]], [[TMP2545]]
46405 // SIMD-ONLY0-NEXT:    br i1 [[CMP3703]], label [[IF_THEN3705:%.*]], label [[IF_END3706:%.*]]
46406 // SIMD-ONLY0:       if.then3705:
46407 // SIMD-ONLY0-NEXT:    [[TMP2546:%.*]] = load i32, ptr [[UIE]], align 4
46408 // SIMD-ONLY0-NEXT:    store i32 [[TMP2546]], ptr [[UIX]], align 4
46409 // SIMD-ONLY0-NEXT:    br label [[IF_END3706]]
46410 // SIMD-ONLY0:       if.end3706:
46411 // SIMD-ONLY0-NEXT:    [[TMP2547:%.*]] = load i32, ptr [[UIX]], align 4
46412 // SIMD-ONLY0-NEXT:    store i32 [[TMP2547]], ptr [[UIV]], align 4
46413 // SIMD-ONLY0-NEXT:    [[TMP2548:%.*]] = load i32, ptr [[UIE]], align 4
46414 // SIMD-ONLY0-NEXT:    [[TMP2549:%.*]] = load i32, ptr [[UIX]], align 4
46415 // SIMD-ONLY0-NEXT:    [[CMP3707:%.*]] = icmp ult i32 [[TMP2548]], [[TMP2549]]
46416 // SIMD-ONLY0-NEXT:    br i1 [[CMP3707]], label [[IF_THEN3709:%.*]], label [[IF_END3710:%.*]]
46417 // SIMD-ONLY0:       if.then3709:
46418 // SIMD-ONLY0-NEXT:    [[TMP2550:%.*]] = load i32, ptr [[UIE]], align 4
46419 // SIMD-ONLY0-NEXT:    store i32 [[TMP2550]], ptr [[UIX]], align 4
46420 // SIMD-ONLY0-NEXT:    br label [[IF_END3710]]
46421 // SIMD-ONLY0:       if.end3710:
46422 // SIMD-ONLY0-NEXT:    [[TMP2551:%.*]] = load i32, ptr [[UIX]], align 4
46423 // SIMD-ONLY0-NEXT:    store i32 [[TMP2551]], ptr [[UIV]], align 4
46424 // SIMD-ONLY0-NEXT:    [[TMP2552:%.*]] = load i32, ptr [[UIX]], align 4
46425 // SIMD-ONLY0-NEXT:    [[TMP2553:%.*]] = load i32, ptr [[UIE]], align 4
46426 // SIMD-ONLY0-NEXT:    [[CMP3711:%.*]] = icmp ult i32 [[TMP2552]], [[TMP2553]]
46427 // SIMD-ONLY0-NEXT:    br i1 [[CMP3711]], label [[IF_THEN3713:%.*]], label [[IF_END3714:%.*]]
46428 // SIMD-ONLY0:       if.then3713:
46429 // SIMD-ONLY0-NEXT:    [[TMP2554:%.*]] = load i32, ptr [[UIE]], align 4
46430 // SIMD-ONLY0-NEXT:    store i32 [[TMP2554]], ptr [[UIX]], align 4
46431 // SIMD-ONLY0-NEXT:    br label [[IF_END3714]]
46432 // SIMD-ONLY0:       if.end3714:
46433 // SIMD-ONLY0-NEXT:    [[TMP2555:%.*]] = load i32, ptr [[UIX]], align 4
46434 // SIMD-ONLY0-NEXT:    store i32 [[TMP2555]], ptr [[UIV]], align 4
46435 // SIMD-ONLY0-NEXT:    [[TMP2556:%.*]] = load i32, ptr [[UIX]], align 4
46436 // SIMD-ONLY0-NEXT:    [[TMP2557:%.*]] = load i32, ptr [[UIE]], align 4
46437 // SIMD-ONLY0-NEXT:    [[CMP3715:%.*]] = icmp eq i32 [[TMP2556]], [[TMP2557]]
46438 // SIMD-ONLY0-NEXT:    br i1 [[CMP3715]], label [[IF_THEN3717:%.*]], label [[IF_END3718:%.*]]
46439 // SIMD-ONLY0:       if.then3717:
46440 // SIMD-ONLY0-NEXT:    [[TMP2558:%.*]] = load i32, ptr [[UID]], align 4
46441 // SIMD-ONLY0-NEXT:    store i32 [[TMP2558]], ptr [[UIX]], align 4
46442 // SIMD-ONLY0-NEXT:    br label [[IF_END3718]]
46443 // SIMD-ONLY0:       if.end3718:
46444 // SIMD-ONLY0-NEXT:    [[TMP2559:%.*]] = load i32, ptr [[UIX]], align 4
46445 // SIMD-ONLY0-NEXT:    store i32 [[TMP2559]], ptr [[UIV]], align 4
46446 // SIMD-ONLY0-NEXT:    [[TMP2560:%.*]] = load i32, ptr [[UIE]], align 4
46447 // SIMD-ONLY0-NEXT:    [[TMP2561:%.*]] = load i32, ptr [[UIX]], align 4
46448 // SIMD-ONLY0-NEXT:    [[CMP3719:%.*]] = icmp eq i32 [[TMP2560]], [[TMP2561]]
46449 // SIMD-ONLY0-NEXT:    br i1 [[CMP3719]], label [[IF_THEN3721:%.*]], label [[IF_END3722:%.*]]
46450 // SIMD-ONLY0:       if.then3721:
46451 // SIMD-ONLY0-NEXT:    [[TMP2562:%.*]] = load i32, ptr [[UID]], align 4
46452 // SIMD-ONLY0-NEXT:    store i32 [[TMP2562]], ptr [[UIX]], align 4
46453 // SIMD-ONLY0-NEXT:    br label [[IF_END3722]]
46454 // SIMD-ONLY0:       if.end3722:
46455 // SIMD-ONLY0-NEXT:    [[TMP2563:%.*]] = load i32, ptr [[UIX]], align 4
46456 // SIMD-ONLY0-NEXT:    store i32 [[TMP2563]], ptr [[UIV]], align 4
46457 // SIMD-ONLY0-NEXT:    [[TMP2564:%.*]] = load i32, ptr [[UIX]], align 4
46458 // SIMD-ONLY0-NEXT:    [[TMP2565:%.*]] = load i32, ptr [[UIE]], align 4
46459 // SIMD-ONLY0-NEXT:    [[CMP3723:%.*]] = icmp eq i32 [[TMP2564]], [[TMP2565]]
46460 // SIMD-ONLY0-NEXT:    br i1 [[CMP3723]], label [[IF_THEN3725:%.*]], label [[IF_ELSE3726:%.*]]
46461 // SIMD-ONLY0:       if.then3725:
46462 // SIMD-ONLY0-NEXT:    [[TMP2566:%.*]] = load i32, ptr [[UID]], align 4
46463 // SIMD-ONLY0-NEXT:    store i32 [[TMP2566]], ptr [[UIX]], align 4
46464 // SIMD-ONLY0-NEXT:    br label [[IF_END3727:%.*]]
46465 // SIMD-ONLY0:       if.else3726:
46466 // SIMD-ONLY0-NEXT:    [[TMP2567:%.*]] = load i32, ptr [[UIX]], align 4
46467 // SIMD-ONLY0-NEXT:    store i32 [[TMP2567]], ptr [[UIV]], align 4
46468 // SIMD-ONLY0-NEXT:    br label [[IF_END3727]]
46469 // SIMD-ONLY0:       if.end3727:
46470 // SIMD-ONLY0-NEXT:    [[TMP2568:%.*]] = load i32, ptr [[UIE]], align 4
46471 // SIMD-ONLY0-NEXT:    [[TMP2569:%.*]] = load i32, ptr [[UIX]], align 4
46472 // SIMD-ONLY0-NEXT:    [[CMP3728:%.*]] = icmp eq i32 [[TMP2568]], [[TMP2569]]
46473 // SIMD-ONLY0-NEXT:    br i1 [[CMP3728]], label [[IF_THEN3730:%.*]], label [[IF_ELSE3731:%.*]]
46474 // SIMD-ONLY0:       if.then3730:
46475 // SIMD-ONLY0-NEXT:    [[TMP2570:%.*]] = load i32, ptr [[UID]], align 4
46476 // SIMD-ONLY0-NEXT:    store i32 [[TMP2570]], ptr [[UIX]], align 4
46477 // SIMD-ONLY0-NEXT:    br label [[IF_END3732:%.*]]
46478 // SIMD-ONLY0:       if.else3731:
46479 // SIMD-ONLY0-NEXT:    [[TMP2571:%.*]] = load i32, ptr [[UIX]], align 4
46480 // SIMD-ONLY0-NEXT:    store i32 [[TMP2571]], ptr [[UIV]], align 4
46481 // SIMD-ONLY0-NEXT:    br label [[IF_END3732]]
46482 // SIMD-ONLY0:       if.end3732:
46483 // SIMD-ONLY0-NEXT:    [[TMP2572:%.*]] = load i32, ptr [[UIX]], align 4
46484 // SIMD-ONLY0-NEXT:    [[TMP2573:%.*]] = load i32, ptr [[UIE]], align 4
46485 // SIMD-ONLY0-NEXT:    [[CMP3733:%.*]] = icmp eq i32 [[TMP2572]], [[TMP2573]]
46486 // SIMD-ONLY0-NEXT:    [[CONV3734:%.*]] = zext i1 [[CMP3733]] to i32
46487 // SIMD-ONLY0-NEXT:    store i32 [[CONV3734]], ptr [[UIR]], align 4
46488 // SIMD-ONLY0-NEXT:    [[TMP2574:%.*]] = load i32, ptr [[UIR]], align 4
46489 // SIMD-ONLY0-NEXT:    [[TOBOOL3735:%.*]] = icmp ne i32 [[TMP2574]], 0
46490 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3735]], label [[IF_THEN3736:%.*]], label [[IF_END3737:%.*]]
46491 // SIMD-ONLY0:       if.then3736:
46492 // SIMD-ONLY0-NEXT:    [[TMP2575:%.*]] = load i32, ptr [[UID]], align 4
46493 // SIMD-ONLY0-NEXT:    store i32 [[TMP2575]], ptr [[UIX]], align 4
46494 // SIMD-ONLY0-NEXT:    br label [[IF_END3737]]
46495 // SIMD-ONLY0:       if.end3737:
46496 // SIMD-ONLY0-NEXT:    [[TMP2576:%.*]] = load i32, ptr [[UIE]], align 4
46497 // SIMD-ONLY0-NEXT:    [[TMP2577:%.*]] = load i32, ptr [[UIX]], align 4
46498 // SIMD-ONLY0-NEXT:    [[CMP3738:%.*]] = icmp eq i32 [[TMP2576]], [[TMP2577]]
46499 // SIMD-ONLY0-NEXT:    [[CONV3739:%.*]] = zext i1 [[CMP3738]] to i32
46500 // SIMD-ONLY0-NEXT:    store i32 [[CONV3739]], ptr [[UIR]], align 4
46501 // SIMD-ONLY0-NEXT:    [[TMP2578:%.*]] = load i32, ptr [[UIR]], align 4
46502 // SIMD-ONLY0-NEXT:    [[TOBOOL3740:%.*]] = icmp ne i32 [[TMP2578]], 0
46503 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3740]], label [[IF_THEN3741:%.*]], label [[IF_END3742:%.*]]
46504 // SIMD-ONLY0:       if.then3741:
46505 // SIMD-ONLY0-NEXT:    [[TMP2579:%.*]] = load i32, ptr [[UID]], align 4
46506 // SIMD-ONLY0-NEXT:    store i32 [[TMP2579]], ptr [[UIX]], align 4
46507 // SIMD-ONLY0-NEXT:    br label [[IF_END3742]]
46508 // SIMD-ONLY0:       if.end3742:
46509 // SIMD-ONLY0-NEXT:    [[TMP2580:%.*]] = load i32, ptr [[UIX]], align 4
46510 // SIMD-ONLY0-NEXT:    [[TMP2581:%.*]] = load i32, ptr [[UIE]], align 4
46511 // SIMD-ONLY0-NEXT:    [[CMP3743:%.*]] = icmp eq i32 [[TMP2580]], [[TMP2581]]
46512 // SIMD-ONLY0-NEXT:    [[CONV3744:%.*]] = zext i1 [[CMP3743]] to i32
46513 // SIMD-ONLY0-NEXT:    store i32 [[CONV3744]], ptr [[UIR]], align 4
46514 // SIMD-ONLY0-NEXT:    [[TMP2582:%.*]] = load i32, ptr [[UIR]], align 4
46515 // SIMD-ONLY0-NEXT:    [[TOBOOL3745:%.*]] = icmp ne i32 [[TMP2582]], 0
46516 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3745]], label [[IF_THEN3746:%.*]], label [[IF_ELSE3747:%.*]]
46517 // SIMD-ONLY0:       if.then3746:
46518 // SIMD-ONLY0-NEXT:    [[TMP2583:%.*]] = load i32, ptr [[UID]], align 4
46519 // SIMD-ONLY0-NEXT:    store i32 [[TMP2583]], ptr [[UIX]], align 4
46520 // SIMD-ONLY0-NEXT:    br label [[IF_END3748:%.*]]
46521 // SIMD-ONLY0:       if.else3747:
46522 // SIMD-ONLY0-NEXT:    [[TMP2584:%.*]] = load i32, ptr [[UIX]], align 4
46523 // SIMD-ONLY0-NEXT:    store i32 [[TMP2584]], ptr [[UIV]], align 4
46524 // SIMD-ONLY0-NEXT:    br label [[IF_END3748]]
46525 // SIMD-ONLY0:       if.end3748:
46526 // SIMD-ONLY0-NEXT:    [[TMP2585:%.*]] = load i32, ptr [[UIE]], align 4
46527 // SIMD-ONLY0-NEXT:    [[TMP2586:%.*]] = load i32, ptr [[UIX]], align 4
46528 // SIMD-ONLY0-NEXT:    [[CMP3749:%.*]] = icmp eq i32 [[TMP2585]], [[TMP2586]]
46529 // SIMD-ONLY0-NEXT:    [[CONV3750:%.*]] = zext i1 [[CMP3749]] to i32
46530 // SIMD-ONLY0-NEXT:    store i32 [[CONV3750]], ptr [[UIR]], align 4
46531 // SIMD-ONLY0-NEXT:    [[TMP2587:%.*]] = load i32, ptr [[UIR]], align 4
46532 // SIMD-ONLY0-NEXT:    [[TOBOOL3751:%.*]] = icmp ne i32 [[TMP2587]], 0
46533 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3751]], label [[IF_THEN3752:%.*]], label [[IF_ELSE3753:%.*]]
46534 // SIMD-ONLY0:       if.then3752:
46535 // SIMD-ONLY0-NEXT:    [[TMP2588:%.*]] = load i32, ptr [[UID]], align 4
46536 // SIMD-ONLY0-NEXT:    store i32 [[TMP2588]], ptr [[UIX]], align 4
46537 // SIMD-ONLY0-NEXT:    br label [[IF_END3754:%.*]]
46538 // SIMD-ONLY0:       if.else3753:
46539 // SIMD-ONLY0-NEXT:    [[TMP2589:%.*]] = load i32, ptr [[UIX]], align 4
46540 // SIMD-ONLY0-NEXT:    store i32 [[TMP2589]], ptr [[UIV]], align 4
46541 // SIMD-ONLY0-NEXT:    br label [[IF_END3754]]
46542 // SIMD-ONLY0:       if.end3754:
46543 // SIMD-ONLY0-NEXT:    [[TMP2590:%.*]] = load i32, ptr [[UIX]], align 4
46544 // SIMD-ONLY0-NEXT:    store i32 [[TMP2590]], ptr [[UIV]], align 4
46545 // SIMD-ONLY0-NEXT:    [[TMP2591:%.*]] = load i32, ptr [[UIE]], align 4
46546 // SIMD-ONLY0-NEXT:    [[TMP2592:%.*]] = load i32, ptr [[UIX]], align 4
46547 // SIMD-ONLY0-NEXT:    [[CMP3755:%.*]] = icmp ugt i32 [[TMP2591]], [[TMP2592]]
46548 // SIMD-ONLY0-NEXT:    br i1 [[CMP3755]], label [[IF_THEN3757:%.*]], label [[IF_END3758:%.*]]
46549 // SIMD-ONLY0:       if.then3757:
46550 // SIMD-ONLY0-NEXT:    [[TMP2593:%.*]] = load i32, ptr [[UIE]], align 4
46551 // SIMD-ONLY0-NEXT:    store i32 [[TMP2593]], ptr [[UIX]], align 4
46552 // SIMD-ONLY0-NEXT:    br label [[IF_END3758]]
46553 // SIMD-ONLY0:       if.end3758:
46554 // SIMD-ONLY0-NEXT:    [[TMP2594:%.*]] = load i32, ptr [[UIX]], align 4
46555 // SIMD-ONLY0-NEXT:    store i32 [[TMP2594]], ptr [[UIV]], align 4
46556 // SIMD-ONLY0-NEXT:    [[TMP2595:%.*]] = load i32, ptr [[UIX]], align 4
46557 // SIMD-ONLY0-NEXT:    [[TMP2596:%.*]] = load i32, ptr [[UIE]], align 4
46558 // SIMD-ONLY0-NEXT:    [[CMP3759:%.*]] = icmp ugt i32 [[TMP2595]], [[TMP2596]]
46559 // SIMD-ONLY0-NEXT:    br i1 [[CMP3759]], label [[IF_THEN3761:%.*]], label [[IF_END3762:%.*]]
46560 // SIMD-ONLY0:       if.then3761:
46561 // SIMD-ONLY0-NEXT:    [[TMP2597:%.*]] = load i32, ptr [[UIE]], align 4
46562 // SIMD-ONLY0-NEXT:    store i32 [[TMP2597]], ptr [[UIX]], align 4
46563 // SIMD-ONLY0-NEXT:    br label [[IF_END3762]]
46564 // SIMD-ONLY0:       if.end3762:
46565 // SIMD-ONLY0-NEXT:    [[TMP2598:%.*]] = load i32, ptr [[UIX]], align 4
46566 // SIMD-ONLY0-NEXT:    store i32 [[TMP2598]], ptr [[UIV]], align 4
46567 // SIMD-ONLY0-NEXT:    [[TMP2599:%.*]] = load i32, ptr [[UIE]], align 4
46568 // SIMD-ONLY0-NEXT:    [[TMP2600:%.*]] = load i32, ptr [[UIX]], align 4
46569 // SIMD-ONLY0-NEXT:    [[CMP3763:%.*]] = icmp ult i32 [[TMP2599]], [[TMP2600]]
46570 // SIMD-ONLY0-NEXT:    br i1 [[CMP3763]], label [[IF_THEN3765:%.*]], label [[IF_END3766:%.*]]
46571 // SIMD-ONLY0:       if.then3765:
46572 // SIMD-ONLY0-NEXT:    [[TMP2601:%.*]] = load i32, ptr [[UIE]], align 4
46573 // SIMD-ONLY0-NEXT:    store i32 [[TMP2601]], ptr [[UIX]], align 4
46574 // SIMD-ONLY0-NEXT:    br label [[IF_END3766]]
46575 // SIMD-ONLY0:       if.end3766:
46576 // SIMD-ONLY0-NEXT:    [[TMP2602:%.*]] = load i32, ptr [[UIX]], align 4
46577 // SIMD-ONLY0-NEXT:    store i32 [[TMP2602]], ptr [[UIV]], align 4
46578 // SIMD-ONLY0-NEXT:    [[TMP2603:%.*]] = load i32, ptr [[UIX]], align 4
46579 // SIMD-ONLY0-NEXT:    [[TMP2604:%.*]] = load i32, ptr [[UIE]], align 4
46580 // SIMD-ONLY0-NEXT:    [[CMP3767:%.*]] = icmp ult i32 [[TMP2603]], [[TMP2604]]
46581 // SIMD-ONLY0-NEXT:    br i1 [[CMP3767]], label [[IF_THEN3769:%.*]], label [[IF_END3770:%.*]]
46582 // SIMD-ONLY0:       if.then3769:
46583 // SIMD-ONLY0-NEXT:    [[TMP2605:%.*]] = load i32, ptr [[UIE]], align 4
46584 // SIMD-ONLY0-NEXT:    store i32 [[TMP2605]], ptr [[UIX]], align 4
46585 // SIMD-ONLY0-NEXT:    br label [[IF_END3770]]
46586 // SIMD-ONLY0:       if.end3770:
46587 // SIMD-ONLY0-NEXT:    [[TMP2606:%.*]] = load i32, ptr [[UIX]], align 4
46588 // SIMD-ONLY0-NEXT:    store i32 [[TMP2606]], ptr [[UIV]], align 4
46589 // SIMD-ONLY0-NEXT:    [[TMP2607:%.*]] = load i32, ptr [[UIX]], align 4
46590 // SIMD-ONLY0-NEXT:    [[TMP2608:%.*]] = load i32, ptr [[UIE]], align 4
46591 // SIMD-ONLY0-NEXT:    [[CMP3771:%.*]] = icmp eq i32 [[TMP2607]], [[TMP2608]]
46592 // SIMD-ONLY0-NEXT:    br i1 [[CMP3771]], label [[IF_THEN3773:%.*]], label [[IF_END3774:%.*]]
46593 // SIMD-ONLY0:       if.then3773:
46594 // SIMD-ONLY0-NEXT:    [[TMP2609:%.*]] = load i32, ptr [[UID]], align 4
46595 // SIMD-ONLY0-NEXT:    store i32 [[TMP2609]], ptr [[UIX]], align 4
46596 // SIMD-ONLY0-NEXT:    br label [[IF_END3774]]
46597 // SIMD-ONLY0:       if.end3774:
46598 // SIMD-ONLY0-NEXT:    [[TMP2610:%.*]] = load i32, ptr [[UIX]], align 4
46599 // SIMD-ONLY0-NEXT:    store i32 [[TMP2610]], ptr [[UIV]], align 4
46600 // SIMD-ONLY0-NEXT:    [[TMP2611:%.*]] = load i32, ptr [[UIE]], align 4
46601 // SIMD-ONLY0-NEXT:    [[TMP2612:%.*]] = load i32, ptr [[UIX]], align 4
46602 // SIMD-ONLY0-NEXT:    [[CMP3775:%.*]] = icmp eq i32 [[TMP2611]], [[TMP2612]]
46603 // SIMD-ONLY0-NEXT:    br i1 [[CMP3775]], label [[IF_THEN3777:%.*]], label [[IF_END3778:%.*]]
46604 // SIMD-ONLY0:       if.then3777:
46605 // SIMD-ONLY0-NEXT:    [[TMP2613:%.*]] = load i32, ptr [[UID]], align 4
46606 // SIMD-ONLY0-NEXT:    store i32 [[TMP2613]], ptr [[UIX]], align 4
46607 // SIMD-ONLY0-NEXT:    br label [[IF_END3778]]
46608 // SIMD-ONLY0:       if.end3778:
46609 // SIMD-ONLY0-NEXT:    [[TMP2614:%.*]] = load i32, ptr [[UIE]], align 4
46610 // SIMD-ONLY0-NEXT:    [[TMP2615:%.*]] = load i32, ptr [[UIX]], align 4
46611 // SIMD-ONLY0-NEXT:    [[CMP3779:%.*]] = icmp ugt i32 [[TMP2614]], [[TMP2615]]
46612 // SIMD-ONLY0-NEXT:    br i1 [[CMP3779]], label [[IF_THEN3781:%.*]], label [[IF_END3782:%.*]]
46613 // SIMD-ONLY0:       if.then3781:
46614 // SIMD-ONLY0-NEXT:    [[TMP2616:%.*]] = load i32, ptr [[UIE]], align 4
46615 // SIMD-ONLY0-NEXT:    store i32 [[TMP2616]], ptr [[UIX]], align 4
46616 // SIMD-ONLY0-NEXT:    br label [[IF_END3782]]
46617 // SIMD-ONLY0:       if.end3782:
46618 // SIMD-ONLY0-NEXT:    [[TMP2617:%.*]] = load i32, ptr [[UIX]], align 4
46619 // SIMD-ONLY0-NEXT:    store i32 [[TMP2617]], ptr [[UIV]], align 4
46620 // SIMD-ONLY0-NEXT:    [[TMP2618:%.*]] = load i32, ptr [[UIX]], align 4
46621 // SIMD-ONLY0-NEXT:    [[TMP2619:%.*]] = load i32, ptr [[UIE]], align 4
46622 // SIMD-ONLY0-NEXT:    [[CMP3783:%.*]] = icmp ugt i32 [[TMP2618]], [[TMP2619]]
46623 // SIMD-ONLY0-NEXT:    br i1 [[CMP3783]], label [[IF_THEN3785:%.*]], label [[IF_END3786:%.*]]
46624 // SIMD-ONLY0:       if.then3785:
46625 // SIMD-ONLY0-NEXT:    [[TMP2620:%.*]] = load i32, ptr [[UIE]], align 4
46626 // SIMD-ONLY0-NEXT:    store i32 [[TMP2620]], ptr [[UIX]], align 4
46627 // SIMD-ONLY0-NEXT:    br label [[IF_END3786]]
46628 // SIMD-ONLY0:       if.end3786:
46629 // SIMD-ONLY0-NEXT:    [[TMP2621:%.*]] = load i32, ptr [[UIX]], align 4
46630 // SIMD-ONLY0-NEXT:    store i32 [[TMP2621]], ptr [[UIV]], align 4
46631 // SIMD-ONLY0-NEXT:    [[TMP2622:%.*]] = load i32, ptr [[UIE]], align 4
46632 // SIMD-ONLY0-NEXT:    [[TMP2623:%.*]] = load i32, ptr [[UIX]], align 4
46633 // SIMD-ONLY0-NEXT:    [[CMP3787:%.*]] = icmp ult i32 [[TMP2622]], [[TMP2623]]
46634 // SIMD-ONLY0-NEXT:    br i1 [[CMP3787]], label [[IF_THEN3789:%.*]], label [[IF_END3790:%.*]]
46635 // SIMD-ONLY0:       if.then3789:
46636 // SIMD-ONLY0-NEXT:    [[TMP2624:%.*]] = load i32, ptr [[UIE]], align 4
46637 // SIMD-ONLY0-NEXT:    store i32 [[TMP2624]], ptr [[UIX]], align 4
46638 // SIMD-ONLY0-NEXT:    br label [[IF_END3790]]
46639 // SIMD-ONLY0:       if.end3790:
46640 // SIMD-ONLY0-NEXT:    [[TMP2625:%.*]] = load i32, ptr [[UIX]], align 4
46641 // SIMD-ONLY0-NEXT:    store i32 [[TMP2625]], ptr [[UIV]], align 4
46642 // SIMD-ONLY0-NEXT:    [[TMP2626:%.*]] = load i32, ptr [[UIX]], align 4
46643 // SIMD-ONLY0-NEXT:    [[TMP2627:%.*]] = load i32, ptr [[UIE]], align 4
46644 // SIMD-ONLY0-NEXT:    [[CMP3791:%.*]] = icmp ult i32 [[TMP2626]], [[TMP2627]]
46645 // SIMD-ONLY0-NEXT:    br i1 [[CMP3791]], label [[IF_THEN3793:%.*]], label [[IF_END3794:%.*]]
46646 // SIMD-ONLY0:       if.then3793:
46647 // SIMD-ONLY0-NEXT:    [[TMP2628:%.*]] = load i32, ptr [[UIE]], align 4
46648 // SIMD-ONLY0-NEXT:    store i32 [[TMP2628]], ptr [[UIX]], align 4
46649 // SIMD-ONLY0-NEXT:    br label [[IF_END3794]]
46650 // SIMD-ONLY0:       if.end3794:
46651 // SIMD-ONLY0-NEXT:    [[TMP2629:%.*]] = load i32, ptr [[UIX]], align 4
46652 // SIMD-ONLY0-NEXT:    store i32 [[TMP2629]], ptr [[UIV]], align 4
46653 // SIMD-ONLY0-NEXT:    [[TMP2630:%.*]] = load i32, ptr [[UIX]], align 4
46654 // SIMD-ONLY0-NEXT:    [[TMP2631:%.*]] = load i32, ptr [[UIE]], align 4
46655 // SIMD-ONLY0-NEXT:    [[CMP3795:%.*]] = icmp eq i32 [[TMP2630]], [[TMP2631]]
46656 // SIMD-ONLY0-NEXT:    br i1 [[CMP3795]], label [[IF_THEN3797:%.*]], label [[IF_END3798:%.*]]
46657 // SIMD-ONLY0:       if.then3797:
46658 // SIMD-ONLY0-NEXT:    [[TMP2632:%.*]] = load i32, ptr [[UID]], align 4
46659 // SIMD-ONLY0-NEXT:    store i32 [[TMP2632]], ptr [[UIX]], align 4
46660 // SIMD-ONLY0-NEXT:    br label [[IF_END3798]]
46661 // SIMD-ONLY0:       if.end3798:
46662 // SIMD-ONLY0-NEXT:    [[TMP2633:%.*]] = load i32, ptr [[UIX]], align 4
46663 // SIMD-ONLY0-NEXT:    store i32 [[TMP2633]], ptr [[UIV]], align 4
46664 // SIMD-ONLY0-NEXT:    [[TMP2634:%.*]] = load i32, ptr [[UIE]], align 4
46665 // SIMD-ONLY0-NEXT:    [[TMP2635:%.*]] = load i32, ptr [[UIX]], align 4
46666 // SIMD-ONLY0-NEXT:    [[CMP3799:%.*]] = icmp eq i32 [[TMP2634]], [[TMP2635]]
46667 // SIMD-ONLY0-NEXT:    br i1 [[CMP3799]], label [[IF_THEN3801:%.*]], label [[IF_END3802:%.*]]
46668 // SIMD-ONLY0:       if.then3801:
46669 // SIMD-ONLY0-NEXT:    [[TMP2636:%.*]] = load i32, ptr [[UID]], align 4
46670 // SIMD-ONLY0-NEXT:    store i32 [[TMP2636]], ptr [[UIX]], align 4
46671 // SIMD-ONLY0-NEXT:    br label [[IF_END3802]]
46672 // SIMD-ONLY0:       if.end3802:
46673 // SIMD-ONLY0-NEXT:    [[TMP2637:%.*]] = load i32, ptr [[UIX]], align 4
46674 // SIMD-ONLY0-NEXT:    store i32 [[TMP2637]], ptr [[UIV]], align 4
46675 // SIMD-ONLY0-NEXT:    [[TMP2638:%.*]] = load i32, ptr [[UIX]], align 4
46676 // SIMD-ONLY0-NEXT:    [[TMP2639:%.*]] = load i32, ptr [[UIE]], align 4
46677 // SIMD-ONLY0-NEXT:    [[CMP3803:%.*]] = icmp eq i32 [[TMP2638]], [[TMP2639]]
46678 // SIMD-ONLY0-NEXT:    br i1 [[CMP3803]], label [[IF_THEN3805:%.*]], label [[IF_ELSE3806:%.*]]
46679 // SIMD-ONLY0:       if.then3805:
46680 // SIMD-ONLY0-NEXT:    [[TMP2640:%.*]] = load i32, ptr [[UID]], align 4
46681 // SIMD-ONLY0-NEXT:    store i32 [[TMP2640]], ptr [[UIX]], align 4
46682 // SIMD-ONLY0-NEXT:    br label [[IF_END3807:%.*]]
46683 // SIMD-ONLY0:       if.else3806:
46684 // SIMD-ONLY0-NEXT:    [[TMP2641:%.*]] = load i32, ptr [[UIX]], align 4
46685 // SIMD-ONLY0-NEXT:    store i32 [[TMP2641]], ptr [[UIV]], align 4
46686 // SIMD-ONLY0-NEXT:    br label [[IF_END3807]]
46687 // SIMD-ONLY0:       if.end3807:
46688 // SIMD-ONLY0-NEXT:    [[TMP2642:%.*]] = load i32, ptr [[UIE]], align 4
46689 // SIMD-ONLY0-NEXT:    [[TMP2643:%.*]] = load i32, ptr [[UIX]], align 4
46690 // SIMD-ONLY0-NEXT:    [[CMP3808:%.*]] = icmp eq i32 [[TMP2642]], [[TMP2643]]
46691 // SIMD-ONLY0-NEXT:    br i1 [[CMP3808]], label [[IF_THEN3810:%.*]], label [[IF_ELSE3811:%.*]]
46692 // SIMD-ONLY0:       if.then3810:
46693 // SIMD-ONLY0-NEXT:    [[TMP2644:%.*]] = load i32, ptr [[UID]], align 4
46694 // SIMD-ONLY0-NEXT:    store i32 [[TMP2644]], ptr [[UIX]], align 4
46695 // SIMD-ONLY0-NEXT:    br label [[IF_END3812:%.*]]
46696 // SIMD-ONLY0:       if.else3811:
46697 // SIMD-ONLY0-NEXT:    [[TMP2645:%.*]] = load i32, ptr [[UIX]], align 4
46698 // SIMD-ONLY0-NEXT:    store i32 [[TMP2645]], ptr [[UIV]], align 4
46699 // SIMD-ONLY0-NEXT:    br label [[IF_END3812]]
46700 // SIMD-ONLY0:       if.end3812:
46701 // SIMD-ONLY0-NEXT:    [[TMP2646:%.*]] = load i32, ptr [[UIX]], align 4
46702 // SIMD-ONLY0-NEXT:    [[TMP2647:%.*]] = load i32, ptr [[UIE]], align 4
46703 // SIMD-ONLY0-NEXT:    [[CMP3813:%.*]] = icmp eq i32 [[TMP2646]], [[TMP2647]]
46704 // SIMD-ONLY0-NEXT:    [[CONV3814:%.*]] = zext i1 [[CMP3813]] to i32
46705 // SIMD-ONLY0-NEXT:    store i32 [[CONV3814]], ptr [[UIR]], align 4
46706 // SIMD-ONLY0-NEXT:    [[TMP2648:%.*]] = load i32, ptr [[UIR]], align 4
46707 // SIMD-ONLY0-NEXT:    [[TOBOOL3815:%.*]] = icmp ne i32 [[TMP2648]], 0
46708 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3815]], label [[IF_THEN3816:%.*]], label [[IF_END3817:%.*]]
46709 // SIMD-ONLY0:       if.then3816:
46710 // SIMD-ONLY0-NEXT:    [[TMP2649:%.*]] = load i32, ptr [[UID]], align 4
46711 // SIMD-ONLY0-NEXT:    store i32 [[TMP2649]], ptr [[UIX]], align 4
46712 // SIMD-ONLY0-NEXT:    br label [[IF_END3817]]
46713 // SIMD-ONLY0:       if.end3817:
46714 // SIMD-ONLY0-NEXT:    [[TMP2650:%.*]] = load i32, ptr [[UIE]], align 4
46715 // SIMD-ONLY0-NEXT:    [[TMP2651:%.*]] = load i32, ptr [[UIX]], align 4
46716 // SIMD-ONLY0-NEXT:    [[CMP3818:%.*]] = icmp eq i32 [[TMP2650]], [[TMP2651]]
46717 // SIMD-ONLY0-NEXT:    [[CONV3819:%.*]] = zext i1 [[CMP3818]] to i32
46718 // SIMD-ONLY0-NEXT:    store i32 [[CONV3819]], ptr [[UIR]], align 4
46719 // SIMD-ONLY0-NEXT:    [[TMP2652:%.*]] = load i32, ptr [[UIR]], align 4
46720 // SIMD-ONLY0-NEXT:    [[TOBOOL3820:%.*]] = icmp ne i32 [[TMP2652]], 0
46721 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3820]], label [[IF_THEN3821:%.*]], label [[IF_END3822:%.*]]
46722 // SIMD-ONLY0:       if.then3821:
46723 // SIMD-ONLY0-NEXT:    [[TMP2653:%.*]] = load i32, ptr [[UID]], align 4
46724 // SIMD-ONLY0-NEXT:    store i32 [[TMP2653]], ptr [[UIX]], align 4
46725 // SIMD-ONLY0-NEXT:    br label [[IF_END3822]]
46726 // SIMD-ONLY0:       if.end3822:
46727 // SIMD-ONLY0-NEXT:    [[TMP2654:%.*]] = load i32, ptr [[UIX]], align 4
46728 // SIMD-ONLY0-NEXT:    [[TMP2655:%.*]] = load i32, ptr [[UIE]], align 4
46729 // SIMD-ONLY0-NEXT:    [[CMP3823:%.*]] = icmp eq i32 [[TMP2654]], [[TMP2655]]
46730 // SIMD-ONLY0-NEXT:    [[CONV3824:%.*]] = zext i1 [[CMP3823]] to i32
46731 // SIMD-ONLY0-NEXT:    store i32 [[CONV3824]], ptr [[UIR]], align 4
46732 // SIMD-ONLY0-NEXT:    [[TMP2656:%.*]] = load i32, ptr [[UIR]], align 4
46733 // SIMD-ONLY0-NEXT:    [[TOBOOL3825:%.*]] = icmp ne i32 [[TMP2656]], 0
46734 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3825]], label [[IF_THEN3826:%.*]], label [[IF_ELSE3827:%.*]]
46735 // SIMD-ONLY0:       if.then3826:
46736 // SIMD-ONLY0-NEXT:    [[TMP2657:%.*]] = load i32, ptr [[UID]], align 4
46737 // SIMD-ONLY0-NEXT:    store i32 [[TMP2657]], ptr [[UIX]], align 4
46738 // SIMD-ONLY0-NEXT:    br label [[IF_END3828:%.*]]
46739 // SIMD-ONLY0:       if.else3827:
46740 // SIMD-ONLY0-NEXT:    [[TMP2658:%.*]] = load i32, ptr [[UIX]], align 4
46741 // SIMD-ONLY0-NEXT:    store i32 [[TMP2658]], ptr [[UIV]], align 4
46742 // SIMD-ONLY0-NEXT:    br label [[IF_END3828]]
46743 // SIMD-ONLY0:       if.end3828:
46744 // SIMD-ONLY0-NEXT:    [[TMP2659:%.*]] = load i32, ptr [[UIE]], align 4
46745 // SIMD-ONLY0-NEXT:    [[TMP2660:%.*]] = load i32, ptr [[UIX]], align 4
46746 // SIMD-ONLY0-NEXT:    [[CMP3829:%.*]] = icmp eq i32 [[TMP2659]], [[TMP2660]]
46747 // SIMD-ONLY0-NEXT:    [[CONV3830:%.*]] = zext i1 [[CMP3829]] to i32
46748 // SIMD-ONLY0-NEXT:    store i32 [[CONV3830]], ptr [[UIR]], align 4
46749 // SIMD-ONLY0-NEXT:    [[TMP2661:%.*]] = load i32, ptr [[UIR]], align 4
46750 // SIMD-ONLY0-NEXT:    [[TOBOOL3831:%.*]] = icmp ne i32 [[TMP2661]], 0
46751 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3831]], label [[IF_THEN3832:%.*]], label [[IF_ELSE3833:%.*]]
46752 // SIMD-ONLY0:       if.then3832:
46753 // SIMD-ONLY0-NEXT:    [[TMP2662:%.*]] = load i32, ptr [[UID]], align 4
46754 // SIMD-ONLY0-NEXT:    store i32 [[TMP2662]], ptr [[UIX]], align 4
46755 // SIMD-ONLY0-NEXT:    br label [[IF_END3834:%.*]]
46756 // SIMD-ONLY0:       if.else3833:
46757 // SIMD-ONLY0-NEXT:    [[TMP2663:%.*]] = load i32, ptr [[UIX]], align 4
46758 // SIMD-ONLY0-NEXT:    store i32 [[TMP2663]], ptr [[UIV]], align 4
46759 // SIMD-ONLY0-NEXT:    br label [[IF_END3834]]
46760 // SIMD-ONLY0:       if.end3834:
46761 // SIMD-ONLY0-NEXT:    [[TMP2664:%.*]] = load i64, ptr [[LX]], align 8
46762 // SIMD-ONLY0-NEXT:    store i64 [[TMP2664]], ptr [[LV]], align 8
46763 // SIMD-ONLY0-NEXT:    [[TMP2665:%.*]] = load i64, ptr [[LE]], align 8
46764 // SIMD-ONLY0-NEXT:    [[TMP2666:%.*]] = load i64, ptr [[LX]], align 8
46765 // SIMD-ONLY0-NEXT:    [[CMP3835:%.*]] = icmp sgt i64 [[TMP2665]], [[TMP2666]]
46766 // SIMD-ONLY0-NEXT:    br i1 [[CMP3835]], label [[IF_THEN3837:%.*]], label [[IF_END3838:%.*]]
46767 // SIMD-ONLY0:       if.then3837:
46768 // SIMD-ONLY0-NEXT:    [[TMP2667:%.*]] = load i64, ptr [[LE]], align 8
46769 // SIMD-ONLY0-NEXT:    store i64 [[TMP2667]], ptr [[LX]], align 8
46770 // SIMD-ONLY0-NEXT:    br label [[IF_END3838]]
46771 // SIMD-ONLY0:       if.end3838:
46772 // SIMD-ONLY0-NEXT:    [[TMP2668:%.*]] = load i64, ptr [[LX]], align 8
46773 // SIMD-ONLY0-NEXT:    store i64 [[TMP2668]], ptr [[LV]], align 8
46774 // SIMD-ONLY0-NEXT:    [[TMP2669:%.*]] = load i64, ptr [[LX]], align 8
46775 // SIMD-ONLY0-NEXT:    [[TMP2670:%.*]] = load i64, ptr [[LE]], align 8
46776 // SIMD-ONLY0-NEXT:    [[CMP3839:%.*]] = icmp sgt i64 [[TMP2669]], [[TMP2670]]
46777 // SIMD-ONLY0-NEXT:    br i1 [[CMP3839]], label [[IF_THEN3841:%.*]], label [[IF_END3842:%.*]]
46778 // SIMD-ONLY0:       if.then3841:
46779 // SIMD-ONLY0-NEXT:    [[TMP2671:%.*]] = load i64, ptr [[LE]], align 8
46780 // SIMD-ONLY0-NEXT:    store i64 [[TMP2671]], ptr [[LX]], align 8
46781 // SIMD-ONLY0-NEXT:    br label [[IF_END3842]]
46782 // SIMD-ONLY0:       if.end3842:
46783 // SIMD-ONLY0-NEXT:    [[TMP2672:%.*]] = load i64, ptr [[LX]], align 8
46784 // SIMD-ONLY0-NEXT:    store i64 [[TMP2672]], ptr [[LV]], align 8
46785 // SIMD-ONLY0-NEXT:    [[TMP2673:%.*]] = load i64, ptr [[LE]], align 8
46786 // SIMD-ONLY0-NEXT:    [[TMP2674:%.*]] = load i64, ptr [[LX]], align 8
46787 // SIMD-ONLY0-NEXT:    [[CMP3843:%.*]] = icmp slt i64 [[TMP2673]], [[TMP2674]]
46788 // SIMD-ONLY0-NEXT:    br i1 [[CMP3843]], label [[IF_THEN3845:%.*]], label [[IF_END3846:%.*]]
46789 // SIMD-ONLY0:       if.then3845:
46790 // SIMD-ONLY0-NEXT:    [[TMP2675:%.*]] = load i64, ptr [[LE]], align 8
46791 // SIMD-ONLY0-NEXT:    store i64 [[TMP2675]], ptr [[LX]], align 8
46792 // SIMD-ONLY0-NEXT:    br label [[IF_END3846]]
46793 // SIMD-ONLY0:       if.end3846:
46794 // SIMD-ONLY0-NEXT:    [[TMP2676:%.*]] = load i64, ptr [[LX]], align 8
46795 // SIMD-ONLY0-NEXT:    store i64 [[TMP2676]], ptr [[LV]], align 8
46796 // SIMD-ONLY0-NEXT:    [[TMP2677:%.*]] = load i64, ptr [[LX]], align 8
46797 // SIMD-ONLY0-NEXT:    [[TMP2678:%.*]] = load i64, ptr [[LE]], align 8
46798 // SIMD-ONLY0-NEXT:    [[CMP3847:%.*]] = icmp slt i64 [[TMP2677]], [[TMP2678]]
46799 // SIMD-ONLY0-NEXT:    br i1 [[CMP3847]], label [[IF_THEN3849:%.*]], label [[IF_END3850:%.*]]
46800 // SIMD-ONLY0:       if.then3849:
46801 // SIMD-ONLY0-NEXT:    [[TMP2679:%.*]] = load i64, ptr [[LE]], align 8
46802 // SIMD-ONLY0-NEXT:    store i64 [[TMP2679]], ptr [[LX]], align 8
46803 // SIMD-ONLY0-NEXT:    br label [[IF_END3850]]
46804 // SIMD-ONLY0:       if.end3850:
46805 // SIMD-ONLY0-NEXT:    [[TMP2680:%.*]] = load i64, ptr [[LX]], align 8
46806 // SIMD-ONLY0-NEXT:    store i64 [[TMP2680]], ptr [[LV]], align 8
46807 // SIMD-ONLY0-NEXT:    [[TMP2681:%.*]] = load i64, ptr [[LX]], align 8
46808 // SIMD-ONLY0-NEXT:    [[TMP2682:%.*]] = load i64, ptr [[LE]], align 8
46809 // SIMD-ONLY0-NEXT:    [[CMP3851:%.*]] = icmp eq i64 [[TMP2681]], [[TMP2682]]
46810 // SIMD-ONLY0-NEXT:    br i1 [[CMP3851]], label [[IF_THEN3853:%.*]], label [[IF_END3854:%.*]]
46811 // SIMD-ONLY0:       if.then3853:
46812 // SIMD-ONLY0-NEXT:    [[TMP2683:%.*]] = load i64, ptr [[LD]], align 8
46813 // SIMD-ONLY0-NEXT:    store i64 [[TMP2683]], ptr [[LX]], align 8
46814 // SIMD-ONLY0-NEXT:    br label [[IF_END3854]]
46815 // SIMD-ONLY0:       if.end3854:
46816 // SIMD-ONLY0-NEXT:    [[TMP2684:%.*]] = load i64, ptr [[LX]], align 8
46817 // SIMD-ONLY0-NEXT:    store i64 [[TMP2684]], ptr [[LV]], align 8
46818 // SIMD-ONLY0-NEXT:    [[TMP2685:%.*]] = load i64, ptr [[LE]], align 8
46819 // SIMD-ONLY0-NEXT:    [[TMP2686:%.*]] = load i64, ptr [[LX]], align 8
46820 // SIMD-ONLY0-NEXT:    [[CMP3855:%.*]] = icmp eq i64 [[TMP2685]], [[TMP2686]]
46821 // SIMD-ONLY0-NEXT:    br i1 [[CMP3855]], label [[IF_THEN3857:%.*]], label [[IF_END3858:%.*]]
46822 // SIMD-ONLY0:       if.then3857:
46823 // SIMD-ONLY0-NEXT:    [[TMP2687:%.*]] = load i64, ptr [[LD]], align 8
46824 // SIMD-ONLY0-NEXT:    store i64 [[TMP2687]], ptr [[LX]], align 8
46825 // SIMD-ONLY0-NEXT:    br label [[IF_END3858]]
46826 // SIMD-ONLY0:       if.end3858:
46827 // SIMD-ONLY0-NEXT:    [[TMP2688:%.*]] = load i64, ptr [[LE]], align 8
46828 // SIMD-ONLY0-NEXT:    [[TMP2689:%.*]] = load i64, ptr [[LX]], align 8
46829 // SIMD-ONLY0-NEXT:    [[CMP3859:%.*]] = icmp sgt i64 [[TMP2688]], [[TMP2689]]
46830 // SIMD-ONLY0-NEXT:    br i1 [[CMP3859]], label [[IF_THEN3861:%.*]], label [[IF_END3862:%.*]]
46831 // SIMD-ONLY0:       if.then3861:
46832 // SIMD-ONLY0-NEXT:    [[TMP2690:%.*]] = load i64, ptr [[LE]], align 8
46833 // SIMD-ONLY0-NEXT:    store i64 [[TMP2690]], ptr [[LX]], align 8
46834 // SIMD-ONLY0-NEXT:    br label [[IF_END3862]]
46835 // SIMD-ONLY0:       if.end3862:
46836 // SIMD-ONLY0-NEXT:    [[TMP2691:%.*]] = load i64, ptr [[LX]], align 8
46837 // SIMD-ONLY0-NEXT:    store i64 [[TMP2691]], ptr [[LV]], align 8
46838 // SIMD-ONLY0-NEXT:    [[TMP2692:%.*]] = load i64, ptr [[LX]], align 8
46839 // SIMD-ONLY0-NEXT:    [[TMP2693:%.*]] = load i64, ptr [[LE]], align 8
46840 // SIMD-ONLY0-NEXT:    [[CMP3863:%.*]] = icmp sgt i64 [[TMP2692]], [[TMP2693]]
46841 // SIMD-ONLY0-NEXT:    br i1 [[CMP3863]], label [[IF_THEN3865:%.*]], label [[IF_END3866:%.*]]
46842 // SIMD-ONLY0:       if.then3865:
46843 // SIMD-ONLY0-NEXT:    [[TMP2694:%.*]] = load i64, ptr [[LE]], align 8
46844 // SIMD-ONLY0-NEXT:    store i64 [[TMP2694]], ptr [[LX]], align 8
46845 // SIMD-ONLY0-NEXT:    br label [[IF_END3866]]
46846 // SIMD-ONLY0:       if.end3866:
46847 // SIMD-ONLY0-NEXT:    [[TMP2695:%.*]] = load i64, ptr [[LX]], align 8
46848 // SIMD-ONLY0-NEXT:    store i64 [[TMP2695]], ptr [[LV]], align 8
46849 // SIMD-ONLY0-NEXT:    [[TMP2696:%.*]] = load i64, ptr [[LE]], align 8
46850 // SIMD-ONLY0-NEXT:    [[TMP2697:%.*]] = load i64, ptr [[LX]], align 8
46851 // SIMD-ONLY0-NEXT:    [[CMP3867:%.*]] = icmp slt i64 [[TMP2696]], [[TMP2697]]
46852 // SIMD-ONLY0-NEXT:    br i1 [[CMP3867]], label [[IF_THEN3869:%.*]], label [[IF_END3870:%.*]]
46853 // SIMD-ONLY0:       if.then3869:
46854 // SIMD-ONLY0-NEXT:    [[TMP2698:%.*]] = load i64, ptr [[LE]], align 8
46855 // SIMD-ONLY0-NEXT:    store i64 [[TMP2698]], ptr [[LX]], align 8
46856 // SIMD-ONLY0-NEXT:    br label [[IF_END3870]]
46857 // SIMD-ONLY0:       if.end3870:
46858 // SIMD-ONLY0-NEXT:    [[TMP2699:%.*]] = load i64, ptr [[LX]], align 8
46859 // SIMD-ONLY0-NEXT:    store i64 [[TMP2699]], ptr [[LV]], align 8
46860 // SIMD-ONLY0-NEXT:    [[TMP2700:%.*]] = load i64, ptr [[LX]], align 8
46861 // SIMD-ONLY0-NEXT:    [[TMP2701:%.*]] = load i64, ptr [[LE]], align 8
46862 // SIMD-ONLY0-NEXT:    [[CMP3871:%.*]] = icmp slt i64 [[TMP2700]], [[TMP2701]]
46863 // SIMD-ONLY0-NEXT:    br i1 [[CMP3871]], label [[IF_THEN3873:%.*]], label [[IF_END3874:%.*]]
46864 // SIMD-ONLY0:       if.then3873:
46865 // SIMD-ONLY0-NEXT:    [[TMP2702:%.*]] = load i64, ptr [[LE]], align 8
46866 // SIMD-ONLY0-NEXT:    store i64 [[TMP2702]], ptr [[LX]], align 8
46867 // SIMD-ONLY0-NEXT:    br label [[IF_END3874]]
46868 // SIMD-ONLY0:       if.end3874:
46869 // SIMD-ONLY0-NEXT:    [[TMP2703:%.*]] = load i64, ptr [[LX]], align 8
46870 // SIMD-ONLY0-NEXT:    store i64 [[TMP2703]], ptr [[LV]], align 8
46871 // SIMD-ONLY0-NEXT:    [[TMP2704:%.*]] = load i64, ptr [[LX]], align 8
46872 // SIMD-ONLY0-NEXT:    [[TMP2705:%.*]] = load i64, ptr [[LE]], align 8
46873 // SIMD-ONLY0-NEXT:    [[CMP3875:%.*]] = icmp eq i64 [[TMP2704]], [[TMP2705]]
46874 // SIMD-ONLY0-NEXT:    br i1 [[CMP3875]], label [[IF_THEN3877:%.*]], label [[IF_END3878:%.*]]
46875 // SIMD-ONLY0:       if.then3877:
46876 // SIMD-ONLY0-NEXT:    [[TMP2706:%.*]] = load i64, ptr [[LD]], align 8
46877 // SIMD-ONLY0-NEXT:    store i64 [[TMP2706]], ptr [[LX]], align 8
46878 // SIMD-ONLY0-NEXT:    br label [[IF_END3878]]
46879 // SIMD-ONLY0:       if.end3878:
46880 // SIMD-ONLY0-NEXT:    [[TMP2707:%.*]] = load i64, ptr [[LX]], align 8
46881 // SIMD-ONLY0-NEXT:    store i64 [[TMP2707]], ptr [[LV]], align 8
46882 // SIMD-ONLY0-NEXT:    [[TMP2708:%.*]] = load i64, ptr [[LE]], align 8
46883 // SIMD-ONLY0-NEXT:    [[TMP2709:%.*]] = load i64, ptr [[LX]], align 8
46884 // SIMD-ONLY0-NEXT:    [[CMP3879:%.*]] = icmp eq i64 [[TMP2708]], [[TMP2709]]
46885 // SIMD-ONLY0-NEXT:    br i1 [[CMP3879]], label [[IF_THEN3881:%.*]], label [[IF_END3882:%.*]]
46886 // SIMD-ONLY0:       if.then3881:
46887 // SIMD-ONLY0-NEXT:    [[TMP2710:%.*]] = load i64, ptr [[LD]], align 8
46888 // SIMD-ONLY0-NEXT:    store i64 [[TMP2710]], ptr [[LX]], align 8
46889 // SIMD-ONLY0-NEXT:    br label [[IF_END3882]]
46890 // SIMD-ONLY0:       if.end3882:
46891 // SIMD-ONLY0-NEXT:    [[TMP2711:%.*]] = load i64, ptr [[LX]], align 8
46892 // SIMD-ONLY0-NEXT:    store i64 [[TMP2711]], ptr [[LV]], align 8
46893 // SIMD-ONLY0-NEXT:    [[TMP2712:%.*]] = load i64, ptr [[LX]], align 8
46894 // SIMD-ONLY0-NEXT:    [[TMP2713:%.*]] = load i64, ptr [[LE]], align 8
46895 // SIMD-ONLY0-NEXT:    [[CMP3883:%.*]] = icmp eq i64 [[TMP2712]], [[TMP2713]]
46896 // SIMD-ONLY0-NEXT:    br i1 [[CMP3883]], label [[IF_THEN3885:%.*]], label [[IF_ELSE3886:%.*]]
46897 // SIMD-ONLY0:       if.then3885:
46898 // SIMD-ONLY0-NEXT:    [[TMP2714:%.*]] = load i64, ptr [[LD]], align 8
46899 // SIMD-ONLY0-NEXT:    store i64 [[TMP2714]], ptr [[LX]], align 8
46900 // SIMD-ONLY0-NEXT:    br label [[IF_END3887:%.*]]
46901 // SIMD-ONLY0:       if.else3886:
46902 // SIMD-ONLY0-NEXT:    [[TMP2715:%.*]] = load i64, ptr [[LX]], align 8
46903 // SIMD-ONLY0-NEXT:    store i64 [[TMP2715]], ptr [[LV]], align 8
46904 // SIMD-ONLY0-NEXT:    br label [[IF_END3887]]
46905 // SIMD-ONLY0:       if.end3887:
46906 // SIMD-ONLY0-NEXT:    [[TMP2716:%.*]] = load i64, ptr [[LE]], align 8
46907 // SIMD-ONLY0-NEXT:    [[TMP2717:%.*]] = load i64, ptr [[LX]], align 8
46908 // SIMD-ONLY0-NEXT:    [[CMP3888:%.*]] = icmp eq i64 [[TMP2716]], [[TMP2717]]
46909 // SIMD-ONLY0-NEXT:    br i1 [[CMP3888]], label [[IF_THEN3890:%.*]], label [[IF_ELSE3891:%.*]]
46910 // SIMD-ONLY0:       if.then3890:
46911 // SIMD-ONLY0-NEXT:    [[TMP2718:%.*]] = load i64, ptr [[LD]], align 8
46912 // SIMD-ONLY0-NEXT:    store i64 [[TMP2718]], ptr [[LX]], align 8
46913 // SIMD-ONLY0-NEXT:    br label [[IF_END3892:%.*]]
46914 // SIMD-ONLY0:       if.else3891:
46915 // SIMD-ONLY0-NEXT:    [[TMP2719:%.*]] = load i64, ptr [[LX]], align 8
46916 // SIMD-ONLY0-NEXT:    store i64 [[TMP2719]], ptr [[LV]], align 8
46917 // SIMD-ONLY0-NEXT:    br label [[IF_END3892]]
46918 // SIMD-ONLY0:       if.end3892:
46919 // SIMD-ONLY0-NEXT:    [[TMP2720:%.*]] = load i64, ptr [[LX]], align 8
46920 // SIMD-ONLY0-NEXT:    [[TMP2721:%.*]] = load i64, ptr [[LE]], align 8
46921 // SIMD-ONLY0-NEXT:    [[CMP3893:%.*]] = icmp eq i64 [[TMP2720]], [[TMP2721]]
46922 // SIMD-ONLY0-NEXT:    [[CONV3894:%.*]] = zext i1 [[CMP3893]] to i32
46923 // SIMD-ONLY0-NEXT:    [[CONV3895:%.*]] = sext i32 [[CONV3894]] to i64
46924 // SIMD-ONLY0-NEXT:    store i64 [[CONV3895]], ptr [[LR]], align 8
46925 // SIMD-ONLY0-NEXT:    [[TMP2722:%.*]] = load i64, ptr [[LR]], align 8
46926 // SIMD-ONLY0-NEXT:    [[TOBOOL3896:%.*]] = icmp ne i64 [[TMP2722]], 0
46927 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3896]], label [[IF_THEN3897:%.*]], label [[IF_END3898:%.*]]
46928 // SIMD-ONLY0:       if.then3897:
46929 // SIMD-ONLY0-NEXT:    [[TMP2723:%.*]] = load i64, ptr [[LD]], align 8
46930 // SIMD-ONLY0-NEXT:    store i64 [[TMP2723]], ptr [[LX]], align 8
46931 // SIMD-ONLY0-NEXT:    br label [[IF_END3898]]
46932 // SIMD-ONLY0:       if.end3898:
46933 // SIMD-ONLY0-NEXT:    [[TMP2724:%.*]] = load i64, ptr [[LE]], align 8
46934 // SIMD-ONLY0-NEXT:    [[TMP2725:%.*]] = load i64, ptr [[LX]], align 8
46935 // SIMD-ONLY0-NEXT:    [[CMP3899:%.*]] = icmp eq i64 [[TMP2724]], [[TMP2725]]
46936 // SIMD-ONLY0-NEXT:    [[CONV3900:%.*]] = zext i1 [[CMP3899]] to i32
46937 // SIMD-ONLY0-NEXT:    [[CONV3901:%.*]] = sext i32 [[CONV3900]] to i64
46938 // SIMD-ONLY0-NEXT:    store i64 [[CONV3901]], ptr [[LR]], align 8
46939 // SIMD-ONLY0-NEXT:    [[TMP2726:%.*]] = load i64, ptr [[LR]], align 8
46940 // SIMD-ONLY0-NEXT:    [[TOBOOL3902:%.*]] = icmp ne i64 [[TMP2726]], 0
46941 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3902]], label [[IF_THEN3903:%.*]], label [[IF_END3904:%.*]]
46942 // SIMD-ONLY0:       if.then3903:
46943 // SIMD-ONLY0-NEXT:    [[TMP2727:%.*]] = load i64, ptr [[LD]], align 8
46944 // SIMD-ONLY0-NEXT:    store i64 [[TMP2727]], ptr [[LX]], align 8
46945 // SIMD-ONLY0-NEXT:    br label [[IF_END3904]]
46946 // SIMD-ONLY0:       if.end3904:
46947 // SIMD-ONLY0-NEXT:    [[TMP2728:%.*]] = load i64, ptr [[LX]], align 8
46948 // SIMD-ONLY0-NEXT:    [[TMP2729:%.*]] = load i64, ptr [[LE]], align 8
46949 // SIMD-ONLY0-NEXT:    [[CMP3905:%.*]] = icmp eq i64 [[TMP2728]], [[TMP2729]]
46950 // SIMD-ONLY0-NEXT:    [[CONV3906:%.*]] = zext i1 [[CMP3905]] to i32
46951 // SIMD-ONLY0-NEXT:    [[CONV3907:%.*]] = sext i32 [[CONV3906]] to i64
46952 // SIMD-ONLY0-NEXT:    store i64 [[CONV3907]], ptr [[LR]], align 8
46953 // SIMD-ONLY0-NEXT:    [[TMP2730:%.*]] = load i64, ptr [[LR]], align 8
46954 // SIMD-ONLY0-NEXT:    [[TOBOOL3908:%.*]] = icmp ne i64 [[TMP2730]], 0
46955 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3908]], label [[IF_THEN3909:%.*]], label [[IF_ELSE3910:%.*]]
46956 // SIMD-ONLY0:       if.then3909:
46957 // SIMD-ONLY0-NEXT:    [[TMP2731:%.*]] = load i64, ptr [[LD]], align 8
46958 // SIMD-ONLY0-NEXT:    store i64 [[TMP2731]], ptr [[LX]], align 8
46959 // SIMD-ONLY0-NEXT:    br label [[IF_END3911:%.*]]
46960 // SIMD-ONLY0:       if.else3910:
46961 // SIMD-ONLY0-NEXT:    [[TMP2732:%.*]] = load i64, ptr [[LX]], align 8
46962 // SIMD-ONLY0-NEXT:    store i64 [[TMP2732]], ptr [[LV]], align 8
46963 // SIMD-ONLY0-NEXT:    br label [[IF_END3911]]
46964 // SIMD-ONLY0:       if.end3911:
46965 // SIMD-ONLY0-NEXT:    [[TMP2733:%.*]] = load i64, ptr [[LE]], align 8
46966 // SIMD-ONLY0-NEXT:    [[TMP2734:%.*]] = load i64, ptr [[LX]], align 8
46967 // SIMD-ONLY0-NEXT:    [[CMP3912:%.*]] = icmp eq i64 [[TMP2733]], [[TMP2734]]
46968 // SIMD-ONLY0-NEXT:    [[CONV3913:%.*]] = zext i1 [[CMP3912]] to i32
46969 // SIMD-ONLY0-NEXT:    [[CONV3914:%.*]] = sext i32 [[CONV3913]] to i64
46970 // SIMD-ONLY0-NEXT:    store i64 [[CONV3914]], ptr [[LR]], align 8
46971 // SIMD-ONLY0-NEXT:    [[TMP2735:%.*]] = load i64, ptr [[LR]], align 8
46972 // SIMD-ONLY0-NEXT:    [[TOBOOL3915:%.*]] = icmp ne i64 [[TMP2735]], 0
46973 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3915]], label [[IF_THEN3916:%.*]], label [[IF_ELSE3917:%.*]]
46974 // SIMD-ONLY0:       if.then3916:
46975 // SIMD-ONLY0-NEXT:    [[TMP2736:%.*]] = load i64, ptr [[LD]], align 8
46976 // SIMD-ONLY0-NEXT:    store i64 [[TMP2736]], ptr [[LX]], align 8
46977 // SIMD-ONLY0-NEXT:    br label [[IF_END3918:%.*]]
46978 // SIMD-ONLY0:       if.else3917:
46979 // SIMD-ONLY0-NEXT:    [[TMP2737:%.*]] = load i64, ptr [[LX]], align 8
46980 // SIMD-ONLY0-NEXT:    store i64 [[TMP2737]], ptr [[LV]], align 8
46981 // SIMD-ONLY0-NEXT:    br label [[IF_END3918]]
46982 // SIMD-ONLY0:       if.end3918:
46983 // SIMD-ONLY0-NEXT:    [[TMP2738:%.*]] = load i64, ptr [[LX]], align 8
46984 // SIMD-ONLY0-NEXT:    store i64 [[TMP2738]], ptr [[LV]], align 8
46985 // SIMD-ONLY0-NEXT:    [[TMP2739:%.*]] = load i64, ptr [[LE]], align 8
46986 // SIMD-ONLY0-NEXT:    [[TMP2740:%.*]] = load i64, ptr [[LX]], align 8
46987 // SIMD-ONLY0-NEXT:    [[CMP3919:%.*]] = icmp sgt i64 [[TMP2739]], [[TMP2740]]
46988 // SIMD-ONLY0-NEXT:    br i1 [[CMP3919]], label [[IF_THEN3921:%.*]], label [[IF_END3922:%.*]]
46989 // SIMD-ONLY0:       if.then3921:
46990 // SIMD-ONLY0-NEXT:    [[TMP2741:%.*]] = load i64, ptr [[LE]], align 8
46991 // SIMD-ONLY0-NEXT:    store i64 [[TMP2741]], ptr [[LX]], align 8
46992 // SIMD-ONLY0-NEXT:    br label [[IF_END3922]]
46993 // SIMD-ONLY0:       if.end3922:
46994 // SIMD-ONLY0-NEXT:    [[TMP2742:%.*]] = load i64, ptr [[LX]], align 8
46995 // SIMD-ONLY0-NEXT:    store i64 [[TMP2742]], ptr [[LV]], align 8
46996 // SIMD-ONLY0-NEXT:    [[TMP2743:%.*]] = load i64, ptr [[LX]], align 8
46997 // SIMD-ONLY0-NEXT:    [[TMP2744:%.*]] = load i64, ptr [[LE]], align 8
46998 // SIMD-ONLY0-NEXT:    [[CMP3923:%.*]] = icmp sgt i64 [[TMP2743]], [[TMP2744]]
46999 // SIMD-ONLY0-NEXT:    br i1 [[CMP3923]], label [[IF_THEN3925:%.*]], label [[IF_END3926:%.*]]
47000 // SIMD-ONLY0:       if.then3925:
47001 // SIMD-ONLY0-NEXT:    [[TMP2745:%.*]] = load i64, ptr [[LE]], align 8
47002 // SIMD-ONLY0-NEXT:    store i64 [[TMP2745]], ptr [[LX]], align 8
47003 // SIMD-ONLY0-NEXT:    br label [[IF_END3926]]
47004 // SIMD-ONLY0:       if.end3926:
47005 // SIMD-ONLY0-NEXT:    [[TMP2746:%.*]] = load i64, ptr [[LX]], align 8
47006 // SIMD-ONLY0-NEXT:    store i64 [[TMP2746]], ptr [[LV]], align 8
47007 // SIMD-ONLY0-NEXT:    [[TMP2747:%.*]] = load i64, ptr [[LE]], align 8
47008 // SIMD-ONLY0-NEXT:    [[TMP2748:%.*]] = load i64, ptr [[LX]], align 8
47009 // SIMD-ONLY0-NEXT:    [[CMP3927:%.*]] = icmp slt i64 [[TMP2747]], [[TMP2748]]
47010 // SIMD-ONLY0-NEXT:    br i1 [[CMP3927]], label [[IF_THEN3929:%.*]], label [[IF_END3930:%.*]]
47011 // SIMD-ONLY0:       if.then3929:
47012 // SIMD-ONLY0-NEXT:    [[TMP2749:%.*]] = load i64, ptr [[LE]], align 8
47013 // SIMD-ONLY0-NEXT:    store i64 [[TMP2749]], ptr [[LX]], align 8
47014 // SIMD-ONLY0-NEXT:    br label [[IF_END3930]]
47015 // SIMD-ONLY0:       if.end3930:
47016 // SIMD-ONLY0-NEXT:    [[TMP2750:%.*]] = load i64, ptr [[LX]], align 8
47017 // SIMD-ONLY0-NEXT:    store i64 [[TMP2750]], ptr [[LV]], align 8
47018 // SIMD-ONLY0-NEXT:    [[TMP2751:%.*]] = load i64, ptr [[LX]], align 8
47019 // SIMD-ONLY0-NEXT:    [[TMP2752:%.*]] = load i64, ptr [[LE]], align 8
47020 // SIMD-ONLY0-NEXT:    [[CMP3931:%.*]] = icmp slt i64 [[TMP2751]], [[TMP2752]]
47021 // SIMD-ONLY0-NEXT:    br i1 [[CMP3931]], label [[IF_THEN3933:%.*]], label [[IF_END3934:%.*]]
47022 // SIMD-ONLY0:       if.then3933:
47023 // SIMD-ONLY0-NEXT:    [[TMP2753:%.*]] = load i64, ptr [[LE]], align 8
47024 // SIMD-ONLY0-NEXT:    store i64 [[TMP2753]], ptr [[LX]], align 8
47025 // SIMD-ONLY0-NEXT:    br label [[IF_END3934]]
47026 // SIMD-ONLY0:       if.end3934:
47027 // SIMD-ONLY0-NEXT:    [[TMP2754:%.*]] = load i64, ptr [[LX]], align 8
47028 // SIMD-ONLY0-NEXT:    store i64 [[TMP2754]], ptr [[LV]], align 8
47029 // SIMD-ONLY0-NEXT:    [[TMP2755:%.*]] = load i64, ptr [[LX]], align 8
47030 // SIMD-ONLY0-NEXT:    [[TMP2756:%.*]] = load i64, ptr [[LE]], align 8
47031 // SIMD-ONLY0-NEXT:    [[CMP3935:%.*]] = icmp eq i64 [[TMP2755]], [[TMP2756]]
47032 // SIMD-ONLY0-NEXT:    br i1 [[CMP3935]], label [[IF_THEN3937:%.*]], label [[IF_END3938:%.*]]
47033 // SIMD-ONLY0:       if.then3937:
47034 // SIMD-ONLY0-NEXT:    [[TMP2757:%.*]] = load i64, ptr [[LD]], align 8
47035 // SIMD-ONLY0-NEXT:    store i64 [[TMP2757]], ptr [[LX]], align 8
47036 // SIMD-ONLY0-NEXT:    br label [[IF_END3938]]
47037 // SIMD-ONLY0:       if.end3938:
47038 // SIMD-ONLY0-NEXT:    [[TMP2758:%.*]] = load i64, ptr [[LX]], align 8
47039 // SIMD-ONLY0-NEXT:    store i64 [[TMP2758]], ptr [[LV]], align 8
47040 // SIMD-ONLY0-NEXT:    [[TMP2759:%.*]] = load i64, ptr [[LE]], align 8
47041 // SIMD-ONLY0-NEXT:    [[TMP2760:%.*]] = load i64, ptr [[LX]], align 8
47042 // SIMD-ONLY0-NEXT:    [[CMP3939:%.*]] = icmp eq i64 [[TMP2759]], [[TMP2760]]
47043 // SIMD-ONLY0-NEXT:    br i1 [[CMP3939]], label [[IF_THEN3941:%.*]], label [[IF_END3942:%.*]]
47044 // SIMD-ONLY0:       if.then3941:
47045 // SIMD-ONLY0-NEXT:    [[TMP2761:%.*]] = load i64, ptr [[LD]], align 8
47046 // SIMD-ONLY0-NEXT:    store i64 [[TMP2761]], ptr [[LX]], align 8
47047 // SIMD-ONLY0-NEXT:    br label [[IF_END3942]]
47048 // SIMD-ONLY0:       if.end3942:
47049 // SIMD-ONLY0-NEXT:    [[TMP2762:%.*]] = load i64, ptr [[LE]], align 8
47050 // SIMD-ONLY0-NEXT:    [[TMP2763:%.*]] = load i64, ptr [[LX]], align 8
47051 // SIMD-ONLY0-NEXT:    [[CMP3943:%.*]] = icmp sgt i64 [[TMP2762]], [[TMP2763]]
47052 // SIMD-ONLY0-NEXT:    br i1 [[CMP3943]], label [[IF_THEN3945:%.*]], label [[IF_END3946:%.*]]
47053 // SIMD-ONLY0:       if.then3945:
47054 // SIMD-ONLY0-NEXT:    [[TMP2764:%.*]] = load i64, ptr [[LE]], align 8
47055 // SIMD-ONLY0-NEXT:    store i64 [[TMP2764]], ptr [[LX]], align 8
47056 // SIMD-ONLY0-NEXT:    br label [[IF_END3946]]
47057 // SIMD-ONLY0:       if.end3946:
47058 // SIMD-ONLY0-NEXT:    [[TMP2765:%.*]] = load i64, ptr [[LX]], align 8
47059 // SIMD-ONLY0-NEXT:    store i64 [[TMP2765]], ptr [[LV]], align 8
47060 // SIMD-ONLY0-NEXT:    [[TMP2766:%.*]] = load i64, ptr [[LX]], align 8
47061 // SIMD-ONLY0-NEXT:    [[TMP2767:%.*]] = load i64, ptr [[LE]], align 8
47062 // SIMD-ONLY0-NEXT:    [[CMP3947:%.*]] = icmp sgt i64 [[TMP2766]], [[TMP2767]]
47063 // SIMD-ONLY0-NEXT:    br i1 [[CMP3947]], label [[IF_THEN3949:%.*]], label [[IF_END3950:%.*]]
47064 // SIMD-ONLY0:       if.then3949:
47065 // SIMD-ONLY0-NEXT:    [[TMP2768:%.*]] = load i64, ptr [[LE]], align 8
47066 // SIMD-ONLY0-NEXT:    store i64 [[TMP2768]], ptr [[LX]], align 8
47067 // SIMD-ONLY0-NEXT:    br label [[IF_END3950]]
47068 // SIMD-ONLY0:       if.end3950:
47069 // SIMD-ONLY0-NEXT:    [[TMP2769:%.*]] = load i64, ptr [[LX]], align 8
47070 // SIMD-ONLY0-NEXT:    store i64 [[TMP2769]], ptr [[LV]], align 8
47071 // SIMD-ONLY0-NEXT:    [[TMP2770:%.*]] = load i64, ptr [[LE]], align 8
47072 // SIMD-ONLY0-NEXT:    [[TMP2771:%.*]] = load i64, ptr [[LX]], align 8
47073 // SIMD-ONLY0-NEXT:    [[CMP3951:%.*]] = icmp slt i64 [[TMP2770]], [[TMP2771]]
47074 // SIMD-ONLY0-NEXT:    br i1 [[CMP3951]], label [[IF_THEN3953:%.*]], label [[IF_END3954:%.*]]
47075 // SIMD-ONLY0:       if.then3953:
47076 // SIMD-ONLY0-NEXT:    [[TMP2772:%.*]] = load i64, ptr [[LE]], align 8
47077 // SIMD-ONLY0-NEXT:    store i64 [[TMP2772]], ptr [[LX]], align 8
47078 // SIMD-ONLY0-NEXT:    br label [[IF_END3954]]
47079 // SIMD-ONLY0:       if.end3954:
47080 // SIMD-ONLY0-NEXT:    [[TMP2773:%.*]] = load i64, ptr [[LX]], align 8
47081 // SIMD-ONLY0-NEXT:    store i64 [[TMP2773]], ptr [[LV]], align 8
47082 // SIMD-ONLY0-NEXT:    [[TMP2774:%.*]] = load i64, ptr [[LX]], align 8
47083 // SIMD-ONLY0-NEXT:    [[TMP2775:%.*]] = load i64, ptr [[LE]], align 8
47084 // SIMD-ONLY0-NEXT:    [[CMP3955:%.*]] = icmp slt i64 [[TMP2774]], [[TMP2775]]
47085 // SIMD-ONLY0-NEXT:    br i1 [[CMP3955]], label [[IF_THEN3957:%.*]], label [[IF_END3958:%.*]]
47086 // SIMD-ONLY0:       if.then3957:
47087 // SIMD-ONLY0-NEXT:    [[TMP2776:%.*]] = load i64, ptr [[LE]], align 8
47088 // SIMD-ONLY0-NEXT:    store i64 [[TMP2776]], ptr [[LX]], align 8
47089 // SIMD-ONLY0-NEXT:    br label [[IF_END3958]]
47090 // SIMD-ONLY0:       if.end3958:
47091 // SIMD-ONLY0-NEXT:    [[TMP2777:%.*]] = load i64, ptr [[LX]], align 8
47092 // SIMD-ONLY0-NEXT:    store i64 [[TMP2777]], ptr [[LV]], align 8
47093 // SIMD-ONLY0-NEXT:    [[TMP2778:%.*]] = load i64, ptr [[LX]], align 8
47094 // SIMD-ONLY0-NEXT:    [[TMP2779:%.*]] = load i64, ptr [[LE]], align 8
47095 // SIMD-ONLY0-NEXT:    [[CMP3959:%.*]] = icmp eq i64 [[TMP2778]], [[TMP2779]]
47096 // SIMD-ONLY0-NEXT:    br i1 [[CMP3959]], label [[IF_THEN3961:%.*]], label [[IF_END3962:%.*]]
47097 // SIMD-ONLY0:       if.then3961:
47098 // SIMD-ONLY0-NEXT:    [[TMP2780:%.*]] = load i64, ptr [[LD]], align 8
47099 // SIMD-ONLY0-NEXT:    store i64 [[TMP2780]], ptr [[LX]], align 8
47100 // SIMD-ONLY0-NEXT:    br label [[IF_END3962]]
47101 // SIMD-ONLY0:       if.end3962:
47102 // SIMD-ONLY0-NEXT:    [[TMP2781:%.*]] = load i64, ptr [[LX]], align 8
47103 // SIMD-ONLY0-NEXT:    store i64 [[TMP2781]], ptr [[LV]], align 8
47104 // SIMD-ONLY0-NEXT:    [[TMP2782:%.*]] = load i64, ptr [[LE]], align 8
47105 // SIMD-ONLY0-NEXT:    [[TMP2783:%.*]] = load i64, ptr [[LX]], align 8
47106 // SIMD-ONLY0-NEXT:    [[CMP3963:%.*]] = icmp eq i64 [[TMP2782]], [[TMP2783]]
47107 // SIMD-ONLY0-NEXT:    br i1 [[CMP3963]], label [[IF_THEN3965:%.*]], label [[IF_END3966:%.*]]
47108 // SIMD-ONLY0:       if.then3965:
47109 // SIMD-ONLY0-NEXT:    [[TMP2784:%.*]] = load i64, ptr [[LD]], align 8
47110 // SIMD-ONLY0-NEXT:    store i64 [[TMP2784]], ptr [[LX]], align 8
47111 // SIMD-ONLY0-NEXT:    br label [[IF_END3966]]
47112 // SIMD-ONLY0:       if.end3966:
47113 // SIMD-ONLY0-NEXT:    [[TMP2785:%.*]] = load i64, ptr [[LX]], align 8
47114 // SIMD-ONLY0-NEXT:    store i64 [[TMP2785]], ptr [[LV]], align 8
47115 // SIMD-ONLY0-NEXT:    [[TMP2786:%.*]] = load i64, ptr [[LX]], align 8
47116 // SIMD-ONLY0-NEXT:    [[TMP2787:%.*]] = load i64, ptr [[LE]], align 8
47117 // SIMD-ONLY0-NEXT:    [[CMP3967:%.*]] = icmp eq i64 [[TMP2786]], [[TMP2787]]
47118 // SIMD-ONLY0-NEXT:    br i1 [[CMP3967]], label [[IF_THEN3969:%.*]], label [[IF_ELSE3970:%.*]]
47119 // SIMD-ONLY0:       if.then3969:
47120 // SIMD-ONLY0-NEXT:    [[TMP2788:%.*]] = load i64, ptr [[LD]], align 8
47121 // SIMD-ONLY0-NEXT:    store i64 [[TMP2788]], ptr [[LX]], align 8
47122 // SIMD-ONLY0-NEXT:    br label [[IF_END3971:%.*]]
47123 // SIMD-ONLY0:       if.else3970:
47124 // SIMD-ONLY0-NEXT:    [[TMP2789:%.*]] = load i64, ptr [[LX]], align 8
47125 // SIMD-ONLY0-NEXT:    store i64 [[TMP2789]], ptr [[LV]], align 8
47126 // SIMD-ONLY0-NEXT:    br label [[IF_END3971]]
47127 // SIMD-ONLY0:       if.end3971:
47128 // SIMD-ONLY0-NEXT:    [[TMP2790:%.*]] = load i64, ptr [[LE]], align 8
47129 // SIMD-ONLY0-NEXT:    [[TMP2791:%.*]] = load i64, ptr [[LX]], align 8
47130 // SIMD-ONLY0-NEXT:    [[CMP3972:%.*]] = icmp eq i64 [[TMP2790]], [[TMP2791]]
47131 // SIMD-ONLY0-NEXT:    br i1 [[CMP3972]], label [[IF_THEN3974:%.*]], label [[IF_ELSE3975:%.*]]
47132 // SIMD-ONLY0:       if.then3974:
47133 // SIMD-ONLY0-NEXT:    [[TMP2792:%.*]] = load i64, ptr [[LD]], align 8
47134 // SIMD-ONLY0-NEXT:    store i64 [[TMP2792]], ptr [[LX]], align 8
47135 // SIMD-ONLY0-NEXT:    br label [[IF_END3976:%.*]]
47136 // SIMD-ONLY0:       if.else3975:
47137 // SIMD-ONLY0-NEXT:    [[TMP2793:%.*]] = load i64, ptr [[LX]], align 8
47138 // SIMD-ONLY0-NEXT:    store i64 [[TMP2793]], ptr [[LV]], align 8
47139 // SIMD-ONLY0-NEXT:    br label [[IF_END3976]]
47140 // SIMD-ONLY0:       if.end3976:
47141 // SIMD-ONLY0-NEXT:    [[TMP2794:%.*]] = load i64, ptr [[LX]], align 8
47142 // SIMD-ONLY0-NEXT:    [[TMP2795:%.*]] = load i64, ptr [[LE]], align 8
47143 // SIMD-ONLY0-NEXT:    [[CMP3977:%.*]] = icmp eq i64 [[TMP2794]], [[TMP2795]]
47144 // SIMD-ONLY0-NEXT:    [[CONV3978:%.*]] = zext i1 [[CMP3977]] to i32
47145 // SIMD-ONLY0-NEXT:    [[CONV3979:%.*]] = sext i32 [[CONV3978]] to i64
47146 // SIMD-ONLY0-NEXT:    store i64 [[CONV3979]], ptr [[LR]], align 8
47147 // SIMD-ONLY0-NEXT:    [[TMP2796:%.*]] = load i64, ptr [[LR]], align 8
47148 // SIMD-ONLY0-NEXT:    [[TOBOOL3980:%.*]] = icmp ne i64 [[TMP2796]], 0
47149 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3980]], label [[IF_THEN3981:%.*]], label [[IF_END3982:%.*]]
47150 // SIMD-ONLY0:       if.then3981:
47151 // SIMD-ONLY0-NEXT:    [[TMP2797:%.*]] = load i64, ptr [[LD]], align 8
47152 // SIMD-ONLY0-NEXT:    store i64 [[TMP2797]], ptr [[LX]], align 8
47153 // SIMD-ONLY0-NEXT:    br label [[IF_END3982]]
47154 // SIMD-ONLY0:       if.end3982:
47155 // SIMD-ONLY0-NEXT:    [[TMP2798:%.*]] = load i64, ptr [[LE]], align 8
47156 // SIMD-ONLY0-NEXT:    [[TMP2799:%.*]] = load i64, ptr [[LX]], align 8
47157 // SIMD-ONLY0-NEXT:    [[CMP3983:%.*]] = icmp eq i64 [[TMP2798]], [[TMP2799]]
47158 // SIMD-ONLY0-NEXT:    [[CONV3984:%.*]] = zext i1 [[CMP3983]] to i32
47159 // SIMD-ONLY0-NEXT:    [[CONV3985:%.*]] = sext i32 [[CONV3984]] to i64
47160 // SIMD-ONLY0-NEXT:    store i64 [[CONV3985]], ptr [[LR]], align 8
47161 // SIMD-ONLY0-NEXT:    [[TMP2800:%.*]] = load i64, ptr [[LR]], align 8
47162 // SIMD-ONLY0-NEXT:    [[TOBOOL3986:%.*]] = icmp ne i64 [[TMP2800]], 0
47163 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3986]], label [[IF_THEN3987:%.*]], label [[IF_END3988:%.*]]
47164 // SIMD-ONLY0:       if.then3987:
47165 // SIMD-ONLY0-NEXT:    [[TMP2801:%.*]] = load i64, ptr [[LD]], align 8
47166 // SIMD-ONLY0-NEXT:    store i64 [[TMP2801]], ptr [[LX]], align 8
47167 // SIMD-ONLY0-NEXT:    br label [[IF_END3988]]
47168 // SIMD-ONLY0:       if.end3988:
47169 // SIMD-ONLY0-NEXT:    [[TMP2802:%.*]] = load i64, ptr [[LX]], align 8
47170 // SIMD-ONLY0-NEXT:    [[TMP2803:%.*]] = load i64, ptr [[LE]], align 8
47171 // SIMD-ONLY0-NEXT:    [[CMP3989:%.*]] = icmp eq i64 [[TMP2802]], [[TMP2803]]
47172 // SIMD-ONLY0-NEXT:    [[CONV3990:%.*]] = zext i1 [[CMP3989]] to i32
47173 // SIMD-ONLY0-NEXT:    [[CONV3991:%.*]] = sext i32 [[CONV3990]] to i64
47174 // SIMD-ONLY0-NEXT:    store i64 [[CONV3991]], ptr [[LR]], align 8
47175 // SIMD-ONLY0-NEXT:    [[TMP2804:%.*]] = load i64, ptr [[LR]], align 8
47176 // SIMD-ONLY0-NEXT:    [[TOBOOL3992:%.*]] = icmp ne i64 [[TMP2804]], 0
47177 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3992]], label [[IF_THEN3993:%.*]], label [[IF_ELSE3994:%.*]]
47178 // SIMD-ONLY0:       if.then3993:
47179 // SIMD-ONLY0-NEXT:    [[TMP2805:%.*]] = load i64, ptr [[LD]], align 8
47180 // SIMD-ONLY0-NEXT:    store i64 [[TMP2805]], ptr [[LX]], align 8
47181 // SIMD-ONLY0-NEXT:    br label [[IF_END3995:%.*]]
47182 // SIMD-ONLY0:       if.else3994:
47183 // SIMD-ONLY0-NEXT:    [[TMP2806:%.*]] = load i64, ptr [[LX]], align 8
47184 // SIMD-ONLY0-NEXT:    store i64 [[TMP2806]], ptr [[LV]], align 8
47185 // SIMD-ONLY0-NEXT:    br label [[IF_END3995]]
47186 // SIMD-ONLY0:       if.end3995:
47187 // SIMD-ONLY0-NEXT:    [[TMP2807:%.*]] = load i64, ptr [[LE]], align 8
47188 // SIMD-ONLY0-NEXT:    [[TMP2808:%.*]] = load i64, ptr [[LX]], align 8
47189 // SIMD-ONLY0-NEXT:    [[CMP3996:%.*]] = icmp eq i64 [[TMP2807]], [[TMP2808]]
47190 // SIMD-ONLY0-NEXT:    [[CONV3997:%.*]] = zext i1 [[CMP3996]] to i32
47191 // SIMD-ONLY0-NEXT:    [[CONV3998:%.*]] = sext i32 [[CONV3997]] to i64
47192 // SIMD-ONLY0-NEXT:    store i64 [[CONV3998]], ptr [[LR]], align 8
47193 // SIMD-ONLY0-NEXT:    [[TMP2809:%.*]] = load i64, ptr [[LR]], align 8
47194 // SIMD-ONLY0-NEXT:    [[TOBOOL3999:%.*]] = icmp ne i64 [[TMP2809]], 0
47195 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL3999]], label [[IF_THEN4000:%.*]], label [[IF_ELSE4001:%.*]]
47196 // SIMD-ONLY0:       if.then4000:
47197 // SIMD-ONLY0-NEXT:    [[TMP2810:%.*]] = load i64, ptr [[LD]], align 8
47198 // SIMD-ONLY0-NEXT:    store i64 [[TMP2810]], ptr [[LX]], align 8
47199 // SIMD-ONLY0-NEXT:    br label [[IF_END4002:%.*]]
47200 // SIMD-ONLY0:       if.else4001:
47201 // SIMD-ONLY0-NEXT:    [[TMP2811:%.*]] = load i64, ptr [[LX]], align 8
47202 // SIMD-ONLY0-NEXT:    store i64 [[TMP2811]], ptr [[LV]], align 8
47203 // SIMD-ONLY0-NEXT:    br label [[IF_END4002]]
47204 // SIMD-ONLY0:       if.end4002:
47205 // SIMD-ONLY0-NEXT:    [[TMP2812:%.*]] = load i64, ptr [[LX]], align 8
47206 // SIMD-ONLY0-NEXT:    store i64 [[TMP2812]], ptr [[LV]], align 8
47207 // SIMD-ONLY0-NEXT:    [[TMP2813:%.*]] = load i64, ptr [[LE]], align 8
47208 // SIMD-ONLY0-NEXT:    [[TMP2814:%.*]] = load i64, ptr [[LX]], align 8
47209 // SIMD-ONLY0-NEXT:    [[CMP4003:%.*]] = icmp sgt i64 [[TMP2813]], [[TMP2814]]
47210 // SIMD-ONLY0-NEXT:    br i1 [[CMP4003]], label [[IF_THEN4005:%.*]], label [[IF_END4006:%.*]]
47211 // SIMD-ONLY0:       if.then4005:
47212 // SIMD-ONLY0-NEXT:    [[TMP2815:%.*]] = load i64, ptr [[LE]], align 8
47213 // SIMD-ONLY0-NEXT:    store i64 [[TMP2815]], ptr [[LX]], align 8
47214 // SIMD-ONLY0-NEXT:    br label [[IF_END4006]]
47215 // SIMD-ONLY0:       if.end4006:
47216 // SIMD-ONLY0-NEXT:    [[TMP2816:%.*]] = load i64, ptr [[LX]], align 8
47217 // SIMD-ONLY0-NEXT:    store i64 [[TMP2816]], ptr [[LV]], align 8
47218 // SIMD-ONLY0-NEXT:    [[TMP2817:%.*]] = load i64, ptr [[LX]], align 8
47219 // SIMD-ONLY0-NEXT:    [[TMP2818:%.*]] = load i64, ptr [[LE]], align 8
47220 // SIMD-ONLY0-NEXT:    [[CMP4007:%.*]] = icmp sgt i64 [[TMP2817]], [[TMP2818]]
47221 // SIMD-ONLY0-NEXT:    br i1 [[CMP4007]], label [[IF_THEN4009:%.*]], label [[IF_END4010:%.*]]
47222 // SIMD-ONLY0:       if.then4009:
47223 // SIMD-ONLY0-NEXT:    [[TMP2819:%.*]] = load i64, ptr [[LE]], align 8
47224 // SIMD-ONLY0-NEXT:    store i64 [[TMP2819]], ptr [[LX]], align 8
47225 // SIMD-ONLY0-NEXT:    br label [[IF_END4010]]
47226 // SIMD-ONLY0:       if.end4010:
47227 // SIMD-ONLY0-NEXT:    [[TMP2820:%.*]] = load i64, ptr [[LX]], align 8
47228 // SIMD-ONLY0-NEXT:    store i64 [[TMP2820]], ptr [[LV]], align 8
47229 // SIMD-ONLY0-NEXT:    [[TMP2821:%.*]] = load i64, ptr [[LE]], align 8
47230 // SIMD-ONLY0-NEXT:    [[TMP2822:%.*]] = load i64, ptr [[LX]], align 8
47231 // SIMD-ONLY0-NEXT:    [[CMP4011:%.*]] = icmp slt i64 [[TMP2821]], [[TMP2822]]
47232 // SIMD-ONLY0-NEXT:    br i1 [[CMP4011]], label [[IF_THEN4013:%.*]], label [[IF_END4014:%.*]]
47233 // SIMD-ONLY0:       if.then4013:
47234 // SIMD-ONLY0-NEXT:    [[TMP2823:%.*]] = load i64, ptr [[LE]], align 8
47235 // SIMD-ONLY0-NEXT:    store i64 [[TMP2823]], ptr [[LX]], align 8
47236 // SIMD-ONLY0-NEXT:    br label [[IF_END4014]]
47237 // SIMD-ONLY0:       if.end4014:
47238 // SIMD-ONLY0-NEXT:    [[TMP2824:%.*]] = load i64, ptr [[LX]], align 8
47239 // SIMD-ONLY0-NEXT:    store i64 [[TMP2824]], ptr [[LV]], align 8
47240 // SIMD-ONLY0-NEXT:    [[TMP2825:%.*]] = load i64, ptr [[LX]], align 8
47241 // SIMD-ONLY0-NEXT:    [[TMP2826:%.*]] = load i64, ptr [[LE]], align 8
47242 // SIMD-ONLY0-NEXT:    [[CMP4015:%.*]] = icmp slt i64 [[TMP2825]], [[TMP2826]]
47243 // SIMD-ONLY0-NEXT:    br i1 [[CMP4015]], label [[IF_THEN4017:%.*]], label [[IF_END4018:%.*]]
47244 // SIMD-ONLY0:       if.then4017:
47245 // SIMD-ONLY0-NEXT:    [[TMP2827:%.*]] = load i64, ptr [[LE]], align 8
47246 // SIMD-ONLY0-NEXT:    store i64 [[TMP2827]], ptr [[LX]], align 8
47247 // SIMD-ONLY0-NEXT:    br label [[IF_END4018]]
47248 // SIMD-ONLY0:       if.end4018:
47249 // SIMD-ONLY0-NEXT:    [[TMP2828:%.*]] = load i64, ptr [[LX]], align 8
47250 // SIMD-ONLY0-NEXT:    store i64 [[TMP2828]], ptr [[LV]], align 8
47251 // SIMD-ONLY0-NEXT:    [[TMP2829:%.*]] = load i64, ptr [[LX]], align 8
47252 // SIMD-ONLY0-NEXT:    [[TMP2830:%.*]] = load i64, ptr [[LE]], align 8
47253 // SIMD-ONLY0-NEXT:    [[CMP4019:%.*]] = icmp eq i64 [[TMP2829]], [[TMP2830]]
47254 // SIMD-ONLY0-NEXT:    br i1 [[CMP4019]], label [[IF_THEN4021:%.*]], label [[IF_END4022:%.*]]
47255 // SIMD-ONLY0:       if.then4021:
47256 // SIMD-ONLY0-NEXT:    [[TMP2831:%.*]] = load i64, ptr [[LD]], align 8
47257 // SIMD-ONLY0-NEXT:    store i64 [[TMP2831]], ptr [[LX]], align 8
47258 // SIMD-ONLY0-NEXT:    br label [[IF_END4022]]
47259 // SIMD-ONLY0:       if.end4022:
47260 // SIMD-ONLY0-NEXT:    [[TMP2832:%.*]] = load i64, ptr [[LX]], align 8
47261 // SIMD-ONLY0-NEXT:    store i64 [[TMP2832]], ptr [[LV]], align 8
47262 // SIMD-ONLY0-NEXT:    [[TMP2833:%.*]] = load i64, ptr [[LE]], align 8
47263 // SIMD-ONLY0-NEXT:    [[TMP2834:%.*]] = load i64, ptr [[LX]], align 8
47264 // SIMD-ONLY0-NEXT:    [[CMP4023:%.*]] = icmp eq i64 [[TMP2833]], [[TMP2834]]
47265 // SIMD-ONLY0-NEXT:    br i1 [[CMP4023]], label [[IF_THEN4025:%.*]], label [[IF_END4026:%.*]]
47266 // SIMD-ONLY0:       if.then4025:
47267 // SIMD-ONLY0-NEXT:    [[TMP2835:%.*]] = load i64, ptr [[LD]], align 8
47268 // SIMD-ONLY0-NEXT:    store i64 [[TMP2835]], ptr [[LX]], align 8
47269 // SIMD-ONLY0-NEXT:    br label [[IF_END4026]]
47270 // SIMD-ONLY0:       if.end4026:
47271 // SIMD-ONLY0-NEXT:    [[TMP2836:%.*]] = load i64, ptr [[LE]], align 8
47272 // SIMD-ONLY0-NEXT:    [[TMP2837:%.*]] = load i64, ptr [[LX]], align 8
47273 // SIMD-ONLY0-NEXT:    [[CMP4027:%.*]] = icmp sgt i64 [[TMP2836]], [[TMP2837]]
47274 // SIMD-ONLY0-NEXT:    br i1 [[CMP4027]], label [[IF_THEN4029:%.*]], label [[IF_END4030:%.*]]
47275 // SIMD-ONLY0:       if.then4029:
47276 // SIMD-ONLY0-NEXT:    [[TMP2838:%.*]] = load i64, ptr [[LE]], align 8
47277 // SIMD-ONLY0-NEXT:    store i64 [[TMP2838]], ptr [[LX]], align 8
47278 // SIMD-ONLY0-NEXT:    br label [[IF_END4030]]
47279 // SIMD-ONLY0:       if.end4030:
47280 // SIMD-ONLY0-NEXT:    [[TMP2839:%.*]] = load i64, ptr [[LX]], align 8
47281 // SIMD-ONLY0-NEXT:    store i64 [[TMP2839]], ptr [[LV]], align 8
47282 // SIMD-ONLY0-NEXT:    [[TMP2840:%.*]] = load i64, ptr [[LX]], align 8
47283 // SIMD-ONLY0-NEXT:    [[TMP2841:%.*]] = load i64, ptr [[LE]], align 8
47284 // SIMD-ONLY0-NEXT:    [[CMP4031:%.*]] = icmp sgt i64 [[TMP2840]], [[TMP2841]]
47285 // SIMD-ONLY0-NEXT:    br i1 [[CMP4031]], label [[IF_THEN4033:%.*]], label [[IF_END4034:%.*]]
47286 // SIMD-ONLY0:       if.then4033:
47287 // SIMD-ONLY0-NEXT:    [[TMP2842:%.*]] = load i64, ptr [[LE]], align 8
47288 // SIMD-ONLY0-NEXT:    store i64 [[TMP2842]], ptr [[LX]], align 8
47289 // SIMD-ONLY0-NEXT:    br label [[IF_END4034]]
47290 // SIMD-ONLY0:       if.end4034:
47291 // SIMD-ONLY0-NEXT:    [[TMP2843:%.*]] = load i64, ptr [[LX]], align 8
47292 // SIMD-ONLY0-NEXT:    store i64 [[TMP2843]], ptr [[LV]], align 8
47293 // SIMD-ONLY0-NEXT:    [[TMP2844:%.*]] = load i64, ptr [[LE]], align 8
47294 // SIMD-ONLY0-NEXT:    [[TMP2845:%.*]] = load i64, ptr [[LX]], align 8
47295 // SIMD-ONLY0-NEXT:    [[CMP4035:%.*]] = icmp slt i64 [[TMP2844]], [[TMP2845]]
47296 // SIMD-ONLY0-NEXT:    br i1 [[CMP4035]], label [[IF_THEN4037:%.*]], label [[IF_END4038:%.*]]
47297 // SIMD-ONLY0:       if.then4037:
47298 // SIMD-ONLY0-NEXT:    [[TMP2846:%.*]] = load i64, ptr [[LE]], align 8
47299 // SIMD-ONLY0-NEXT:    store i64 [[TMP2846]], ptr [[LX]], align 8
47300 // SIMD-ONLY0-NEXT:    br label [[IF_END4038]]
47301 // SIMD-ONLY0:       if.end4038:
47302 // SIMD-ONLY0-NEXT:    [[TMP2847:%.*]] = load i64, ptr [[LX]], align 8
47303 // SIMD-ONLY0-NEXT:    store i64 [[TMP2847]], ptr [[LV]], align 8
47304 // SIMD-ONLY0-NEXT:    [[TMP2848:%.*]] = load i64, ptr [[LX]], align 8
47305 // SIMD-ONLY0-NEXT:    [[TMP2849:%.*]] = load i64, ptr [[LE]], align 8
47306 // SIMD-ONLY0-NEXT:    [[CMP4039:%.*]] = icmp slt i64 [[TMP2848]], [[TMP2849]]
47307 // SIMD-ONLY0-NEXT:    br i1 [[CMP4039]], label [[IF_THEN4041:%.*]], label [[IF_END4042:%.*]]
47308 // SIMD-ONLY0:       if.then4041:
47309 // SIMD-ONLY0-NEXT:    [[TMP2850:%.*]] = load i64, ptr [[LE]], align 8
47310 // SIMD-ONLY0-NEXT:    store i64 [[TMP2850]], ptr [[LX]], align 8
47311 // SIMD-ONLY0-NEXT:    br label [[IF_END4042]]
47312 // SIMD-ONLY0:       if.end4042:
47313 // SIMD-ONLY0-NEXT:    [[TMP2851:%.*]] = load i64, ptr [[LX]], align 8
47314 // SIMD-ONLY0-NEXT:    store i64 [[TMP2851]], ptr [[LV]], align 8
47315 // SIMD-ONLY0-NEXT:    [[TMP2852:%.*]] = load i64, ptr [[LX]], align 8
47316 // SIMD-ONLY0-NEXT:    [[TMP2853:%.*]] = load i64, ptr [[LE]], align 8
47317 // SIMD-ONLY0-NEXT:    [[CMP4043:%.*]] = icmp eq i64 [[TMP2852]], [[TMP2853]]
47318 // SIMD-ONLY0-NEXT:    br i1 [[CMP4043]], label [[IF_THEN4045:%.*]], label [[IF_END4046:%.*]]
47319 // SIMD-ONLY0:       if.then4045:
47320 // SIMD-ONLY0-NEXT:    [[TMP2854:%.*]] = load i64, ptr [[LD]], align 8
47321 // SIMD-ONLY0-NEXT:    store i64 [[TMP2854]], ptr [[LX]], align 8
47322 // SIMD-ONLY0-NEXT:    br label [[IF_END4046]]
47323 // SIMD-ONLY0:       if.end4046:
47324 // SIMD-ONLY0-NEXT:    [[TMP2855:%.*]] = load i64, ptr [[LX]], align 8
47325 // SIMD-ONLY0-NEXT:    store i64 [[TMP2855]], ptr [[LV]], align 8
47326 // SIMD-ONLY0-NEXT:    [[TMP2856:%.*]] = load i64, ptr [[LE]], align 8
47327 // SIMD-ONLY0-NEXT:    [[TMP2857:%.*]] = load i64, ptr [[LX]], align 8
47328 // SIMD-ONLY0-NEXT:    [[CMP4047:%.*]] = icmp eq i64 [[TMP2856]], [[TMP2857]]
47329 // SIMD-ONLY0-NEXT:    br i1 [[CMP4047]], label [[IF_THEN4049:%.*]], label [[IF_END4050:%.*]]
47330 // SIMD-ONLY0:       if.then4049:
47331 // SIMD-ONLY0-NEXT:    [[TMP2858:%.*]] = load i64, ptr [[LD]], align 8
47332 // SIMD-ONLY0-NEXT:    store i64 [[TMP2858]], ptr [[LX]], align 8
47333 // SIMD-ONLY0-NEXT:    br label [[IF_END4050]]
47334 // SIMD-ONLY0:       if.end4050:
47335 // SIMD-ONLY0-NEXT:    [[TMP2859:%.*]] = load i64, ptr [[LX]], align 8
47336 // SIMD-ONLY0-NEXT:    store i64 [[TMP2859]], ptr [[LV]], align 8
47337 // SIMD-ONLY0-NEXT:    [[TMP2860:%.*]] = load i64, ptr [[LX]], align 8
47338 // SIMD-ONLY0-NEXT:    [[TMP2861:%.*]] = load i64, ptr [[LE]], align 8
47339 // SIMD-ONLY0-NEXT:    [[CMP4051:%.*]] = icmp eq i64 [[TMP2860]], [[TMP2861]]
47340 // SIMD-ONLY0-NEXT:    br i1 [[CMP4051]], label [[IF_THEN4053:%.*]], label [[IF_ELSE4054:%.*]]
47341 // SIMD-ONLY0:       if.then4053:
47342 // SIMD-ONLY0-NEXT:    [[TMP2862:%.*]] = load i64, ptr [[LD]], align 8
47343 // SIMD-ONLY0-NEXT:    store i64 [[TMP2862]], ptr [[LX]], align 8
47344 // SIMD-ONLY0-NEXT:    br label [[IF_END4055:%.*]]
47345 // SIMD-ONLY0:       if.else4054:
47346 // SIMD-ONLY0-NEXT:    [[TMP2863:%.*]] = load i64, ptr [[LX]], align 8
47347 // SIMD-ONLY0-NEXT:    store i64 [[TMP2863]], ptr [[LV]], align 8
47348 // SIMD-ONLY0-NEXT:    br label [[IF_END4055]]
47349 // SIMD-ONLY0:       if.end4055:
47350 // SIMD-ONLY0-NEXT:    [[TMP2864:%.*]] = load i64, ptr [[LE]], align 8
47351 // SIMD-ONLY0-NEXT:    [[TMP2865:%.*]] = load i64, ptr [[LX]], align 8
47352 // SIMD-ONLY0-NEXT:    [[CMP4056:%.*]] = icmp eq i64 [[TMP2864]], [[TMP2865]]
47353 // SIMD-ONLY0-NEXT:    br i1 [[CMP4056]], label [[IF_THEN4058:%.*]], label [[IF_ELSE4059:%.*]]
47354 // SIMD-ONLY0:       if.then4058:
47355 // SIMD-ONLY0-NEXT:    [[TMP2866:%.*]] = load i64, ptr [[LD]], align 8
47356 // SIMD-ONLY0-NEXT:    store i64 [[TMP2866]], ptr [[LX]], align 8
47357 // SIMD-ONLY0-NEXT:    br label [[IF_END4060:%.*]]
47358 // SIMD-ONLY0:       if.else4059:
47359 // SIMD-ONLY0-NEXT:    [[TMP2867:%.*]] = load i64, ptr [[LX]], align 8
47360 // SIMD-ONLY0-NEXT:    store i64 [[TMP2867]], ptr [[LV]], align 8
47361 // SIMD-ONLY0-NEXT:    br label [[IF_END4060]]
47362 // SIMD-ONLY0:       if.end4060:
47363 // SIMD-ONLY0-NEXT:    [[TMP2868:%.*]] = load i64, ptr [[LX]], align 8
47364 // SIMD-ONLY0-NEXT:    [[TMP2869:%.*]] = load i64, ptr [[LE]], align 8
47365 // SIMD-ONLY0-NEXT:    [[CMP4061:%.*]] = icmp eq i64 [[TMP2868]], [[TMP2869]]
47366 // SIMD-ONLY0-NEXT:    [[CONV4062:%.*]] = zext i1 [[CMP4061]] to i32
47367 // SIMD-ONLY0-NEXT:    [[CONV4063:%.*]] = sext i32 [[CONV4062]] to i64
47368 // SIMD-ONLY0-NEXT:    store i64 [[CONV4063]], ptr [[LR]], align 8
47369 // SIMD-ONLY0-NEXT:    [[TMP2870:%.*]] = load i64, ptr [[LR]], align 8
47370 // SIMD-ONLY0-NEXT:    [[TOBOOL4064:%.*]] = icmp ne i64 [[TMP2870]], 0
47371 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4064]], label [[IF_THEN4065:%.*]], label [[IF_END4066:%.*]]
47372 // SIMD-ONLY0:       if.then4065:
47373 // SIMD-ONLY0-NEXT:    [[TMP2871:%.*]] = load i64, ptr [[LD]], align 8
47374 // SIMD-ONLY0-NEXT:    store i64 [[TMP2871]], ptr [[LX]], align 8
47375 // SIMD-ONLY0-NEXT:    br label [[IF_END4066]]
47376 // SIMD-ONLY0:       if.end4066:
47377 // SIMD-ONLY0-NEXT:    [[TMP2872:%.*]] = load i64, ptr [[LE]], align 8
47378 // SIMD-ONLY0-NEXT:    [[TMP2873:%.*]] = load i64, ptr [[LX]], align 8
47379 // SIMD-ONLY0-NEXT:    [[CMP4067:%.*]] = icmp eq i64 [[TMP2872]], [[TMP2873]]
47380 // SIMD-ONLY0-NEXT:    [[CONV4068:%.*]] = zext i1 [[CMP4067]] to i32
47381 // SIMD-ONLY0-NEXT:    [[CONV4069:%.*]] = sext i32 [[CONV4068]] to i64
47382 // SIMD-ONLY0-NEXT:    store i64 [[CONV4069]], ptr [[LR]], align 8
47383 // SIMD-ONLY0-NEXT:    [[TMP2874:%.*]] = load i64, ptr [[LR]], align 8
47384 // SIMD-ONLY0-NEXT:    [[TOBOOL4070:%.*]] = icmp ne i64 [[TMP2874]], 0
47385 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4070]], label [[IF_THEN4071:%.*]], label [[IF_END4072:%.*]]
47386 // SIMD-ONLY0:       if.then4071:
47387 // SIMD-ONLY0-NEXT:    [[TMP2875:%.*]] = load i64, ptr [[LD]], align 8
47388 // SIMD-ONLY0-NEXT:    store i64 [[TMP2875]], ptr [[LX]], align 8
47389 // SIMD-ONLY0-NEXT:    br label [[IF_END4072]]
47390 // SIMD-ONLY0:       if.end4072:
47391 // SIMD-ONLY0-NEXT:    [[TMP2876:%.*]] = load i64, ptr [[LX]], align 8
47392 // SIMD-ONLY0-NEXT:    [[TMP2877:%.*]] = load i64, ptr [[LE]], align 8
47393 // SIMD-ONLY0-NEXT:    [[CMP4073:%.*]] = icmp eq i64 [[TMP2876]], [[TMP2877]]
47394 // SIMD-ONLY0-NEXT:    [[CONV4074:%.*]] = zext i1 [[CMP4073]] to i32
47395 // SIMD-ONLY0-NEXT:    [[CONV4075:%.*]] = sext i32 [[CONV4074]] to i64
47396 // SIMD-ONLY0-NEXT:    store i64 [[CONV4075]], ptr [[LR]], align 8
47397 // SIMD-ONLY0-NEXT:    [[TMP2878:%.*]] = load i64, ptr [[LR]], align 8
47398 // SIMD-ONLY0-NEXT:    [[TOBOOL4076:%.*]] = icmp ne i64 [[TMP2878]], 0
47399 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4076]], label [[IF_THEN4077:%.*]], label [[IF_ELSE4078:%.*]]
47400 // SIMD-ONLY0:       if.then4077:
47401 // SIMD-ONLY0-NEXT:    [[TMP2879:%.*]] = load i64, ptr [[LD]], align 8
47402 // SIMD-ONLY0-NEXT:    store i64 [[TMP2879]], ptr [[LX]], align 8
47403 // SIMD-ONLY0-NEXT:    br label [[IF_END4079:%.*]]
47404 // SIMD-ONLY0:       if.else4078:
47405 // SIMD-ONLY0-NEXT:    [[TMP2880:%.*]] = load i64, ptr [[LX]], align 8
47406 // SIMD-ONLY0-NEXT:    store i64 [[TMP2880]], ptr [[LV]], align 8
47407 // SIMD-ONLY0-NEXT:    br label [[IF_END4079]]
47408 // SIMD-ONLY0:       if.end4079:
47409 // SIMD-ONLY0-NEXT:    [[TMP2881:%.*]] = load i64, ptr [[LE]], align 8
47410 // SIMD-ONLY0-NEXT:    [[TMP2882:%.*]] = load i64, ptr [[LX]], align 8
47411 // SIMD-ONLY0-NEXT:    [[CMP4080:%.*]] = icmp eq i64 [[TMP2881]], [[TMP2882]]
47412 // SIMD-ONLY0-NEXT:    [[CONV4081:%.*]] = zext i1 [[CMP4080]] to i32
47413 // SIMD-ONLY0-NEXT:    [[CONV4082:%.*]] = sext i32 [[CONV4081]] to i64
47414 // SIMD-ONLY0-NEXT:    store i64 [[CONV4082]], ptr [[LR]], align 8
47415 // SIMD-ONLY0-NEXT:    [[TMP2883:%.*]] = load i64, ptr [[LR]], align 8
47416 // SIMD-ONLY0-NEXT:    [[TOBOOL4083:%.*]] = icmp ne i64 [[TMP2883]], 0
47417 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4083]], label [[IF_THEN4084:%.*]], label [[IF_ELSE4085:%.*]]
47418 // SIMD-ONLY0:       if.then4084:
47419 // SIMD-ONLY0-NEXT:    [[TMP2884:%.*]] = load i64, ptr [[LD]], align 8
47420 // SIMD-ONLY0-NEXT:    store i64 [[TMP2884]], ptr [[LX]], align 8
47421 // SIMD-ONLY0-NEXT:    br label [[IF_END4086:%.*]]
47422 // SIMD-ONLY0:       if.else4085:
47423 // SIMD-ONLY0-NEXT:    [[TMP2885:%.*]] = load i64, ptr [[LX]], align 8
47424 // SIMD-ONLY0-NEXT:    store i64 [[TMP2885]], ptr [[LV]], align 8
47425 // SIMD-ONLY0-NEXT:    br label [[IF_END4086]]
47426 // SIMD-ONLY0:       if.end4086:
47427 // SIMD-ONLY0-NEXT:    [[TMP2886:%.*]] = load i64, ptr [[LX]], align 8
47428 // SIMD-ONLY0-NEXT:    store i64 [[TMP2886]], ptr [[LV]], align 8
47429 // SIMD-ONLY0-NEXT:    [[TMP2887:%.*]] = load i64, ptr [[LE]], align 8
47430 // SIMD-ONLY0-NEXT:    [[TMP2888:%.*]] = load i64, ptr [[LX]], align 8
47431 // SIMD-ONLY0-NEXT:    [[CMP4087:%.*]] = icmp sgt i64 [[TMP2887]], [[TMP2888]]
47432 // SIMD-ONLY0-NEXT:    br i1 [[CMP4087]], label [[IF_THEN4089:%.*]], label [[IF_END4090:%.*]]
47433 // SIMD-ONLY0:       if.then4089:
47434 // SIMD-ONLY0-NEXT:    [[TMP2889:%.*]] = load i64, ptr [[LE]], align 8
47435 // SIMD-ONLY0-NEXT:    store i64 [[TMP2889]], ptr [[LX]], align 8
47436 // SIMD-ONLY0-NEXT:    br label [[IF_END4090]]
47437 // SIMD-ONLY0:       if.end4090:
47438 // SIMD-ONLY0-NEXT:    [[TMP2890:%.*]] = load i64, ptr [[LX]], align 8
47439 // SIMD-ONLY0-NEXT:    store i64 [[TMP2890]], ptr [[LV]], align 8
47440 // SIMD-ONLY0-NEXT:    [[TMP2891:%.*]] = load i64, ptr [[LX]], align 8
47441 // SIMD-ONLY0-NEXT:    [[TMP2892:%.*]] = load i64, ptr [[LE]], align 8
47442 // SIMD-ONLY0-NEXT:    [[CMP4091:%.*]] = icmp sgt i64 [[TMP2891]], [[TMP2892]]
47443 // SIMD-ONLY0-NEXT:    br i1 [[CMP4091]], label [[IF_THEN4093:%.*]], label [[IF_END4094:%.*]]
47444 // SIMD-ONLY0:       if.then4093:
47445 // SIMD-ONLY0-NEXT:    [[TMP2893:%.*]] = load i64, ptr [[LE]], align 8
47446 // SIMD-ONLY0-NEXT:    store i64 [[TMP2893]], ptr [[LX]], align 8
47447 // SIMD-ONLY0-NEXT:    br label [[IF_END4094]]
47448 // SIMD-ONLY0:       if.end4094:
47449 // SIMD-ONLY0-NEXT:    [[TMP2894:%.*]] = load i64, ptr [[LX]], align 8
47450 // SIMD-ONLY0-NEXT:    store i64 [[TMP2894]], ptr [[LV]], align 8
47451 // SIMD-ONLY0-NEXT:    [[TMP2895:%.*]] = load i64, ptr [[LE]], align 8
47452 // SIMD-ONLY0-NEXT:    [[TMP2896:%.*]] = load i64, ptr [[LX]], align 8
47453 // SIMD-ONLY0-NEXT:    [[CMP4095:%.*]] = icmp slt i64 [[TMP2895]], [[TMP2896]]
47454 // SIMD-ONLY0-NEXT:    br i1 [[CMP4095]], label [[IF_THEN4097:%.*]], label [[IF_END4098:%.*]]
47455 // SIMD-ONLY0:       if.then4097:
47456 // SIMD-ONLY0-NEXT:    [[TMP2897:%.*]] = load i64, ptr [[LE]], align 8
47457 // SIMD-ONLY0-NEXT:    store i64 [[TMP2897]], ptr [[LX]], align 8
47458 // SIMD-ONLY0-NEXT:    br label [[IF_END4098]]
47459 // SIMD-ONLY0:       if.end4098:
47460 // SIMD-ONLY0-NEXT:    [[TMP2898:%.*]] = load i64, ptr [[LX]], align 8
47461 // SIMD-ONLY0-NEXT:    store i64 [[TMP2898]], ptr [[LV]], align 8
47462 // SIMD-ONLY0-NEXT:    [[TMP2899:%.*]] = load i64, ptr [[LX]], align 8
47463 // SIMD-ONLY0-NEXT:    [[TMP2900:%.*]] = load i64, ptr [[LE]], align 8
47464 // SIMD-ONLY0-NEXT:    [[CMP4099:%.*]] = icmp slt i64 [[TMP2899]], [[TMP2900]]
47465 // SIMD-ONLY0-NEXT:    br i1 [[CMP4099]], label [[IF_THEN4101:%.*]], label [[IF_END4102:%.*]]
47466 // SIMD-ONLY0:       if.then4101:
47467 // SIMD-ONLY0-NEXT:    [[TMP2901:%.*]] = load i64, ptr [[LE]], align 8
47468 // SIMD-ONLY0-NEXT:    store i64 [[TMP2901]], ptr [[LX]], align 8
47469 // SIMD-ONLY0-NEXT:    br label [[IF_END4102]]
47470 // SIMD-ONLY0:       if.end4102:
47471 // SIMD-ONLY0-NEXT:    [[TMP2902:%.*]] = load i64, ptr [[LX]], align 8
47472 // SIMD-ONLY0-NEXT:    store i64 [[TMP2902]], ptr [[LV]], align 8
47473 // SIMD-ONLY0-NEXT:    [[TMP2903:%.*]] = load i64, ptr [[LX]], align 8
47474 // SIMD-ONLY0-NEXT:    [[TMP2904:%.*]] = load i64, ptr [[LE]], align 8
47475 // SIMD-ONLY0-NEXT:    [[CMP4103:%.*]] = icmp eq i64 [[TMP2903]], [[TMP2904]]
47476 // SIMD-ONLY0-NEXT:    br i1 [[CMP4103]], label [[IF_THEN4105:%.*]], label [[IF_END4106:%.*]]
47477 // SIMD-ONLY0:       if.then4105:
47478 // SIMD-ONLY0-NEXT:    [[TMP2905:%.*]] = load i64, ptr [[LD]], align 8
47479 // SIMD-ONLY0-NEXT:    store i64 [[TMP2905]], ptr [[LX]], align 8
47480 // SIMD-ONLY0-NEXT:    br label [[IF_END4106]]
47481 // SIMD-ONLY0:       if.end4106:
47482 // SIMD-ONLY0-NEXT:    [[TMP2906:%.*]] = load i64, ptr [[LX]], align 8
47483 // SIMD-ONLY0-NEXT:    store i64 [[TMP2906]], ptr [[LV]], align 8
47484 // SIMD-ONLY0-NEXT:    [[TMP2907:%.*]] = load i64, ptr [[LE]], align 8
47485 // SIMD-ONLY0-NEXT:    [[TMP2908:%.*]] = load i64, ptr [[LX]], align 8
47486 // SIMD-ONLY0-NEXT:    [[CMP4107:%.*]] = icmp eq i64 [[TMP2907]], [[TMP2908]]
47487 // SIMD-ONLY0-NEXT:    br i1 [[CMP4107]], label [[IF_THEN4109:%.*]], label [[IF_END4110:%.*]]
47488 // SIMD-ONLY0:       if.then4109:
47489 // SIMD-ONLY0-NEXT:    [[TMP2909:%.*]] = load i64, ptr [[LD]], align 8
47490 // SIMD-ONLY0-NEXT:    store i64 [[TMP2909]], ptr [[LX]], align 8
47491 // SIMD-ONLY0-NEXT:    br label [[IF_END4110]]
47492 // SIMD-ONLY0:       if.end4110:
47493 // SIMD-ONLY0-NEXT:    [[TMP2910:%.*]] = load i64, ptr [[LE]], align 8
47494 // SIMD-ONLY0-NEXT:    [[TMP2911:%.*]] = load i64, ptr [[LX]], align 8
47495 // SIMD-ONLY0-NEXT:    [[CMP4111:%.*]] = icmp sgt i64 [[TMP2910]], [[TMP2911]]
47496 // SIMD-ONLY0-NEXT:    br i1 [[CMP4111]], label [[IF_THEN4113:%.*]], label [[IF_END4114:%.*]]
47497 // SIMD-ONLY0:       if.then4113:
47498 // SIMD-ONLY0-NEXT:    [[TMP2912:%.*]] = load i64, ptr [[LE]], align 8
47499 // SIMD-ONLY0-NEXT:    store i64 [[TMP2912]], ptr [[LX]], align 8
47500 // SIMD-ONLY0-NEXT:    br label [[IF_END4114]]
47501 // SIMD-ONLY0:       if.end4114:
47502 // SIMD-ONLY0-NEXT:    [[TMP2913:%.*]] = load i64, ptr [[LX]], align 8
47503 // SIMD-ONLY0-NEXT:    store i64 [[TMP2913]], ptr [[LV]], align 8
47504 // SIMD-ONLY0-NEXT:    [[TMP2914:%.*]] = load i64, ptr [[LX]], align 8
47505 // SIMD-ONLY0-NEXT:    [[TMP2915:%.*]] = load i64, ptr [[LE]], align 8
47506 // SIMD-ONLY0-NEXT:    [[CMP4115:%.*]] = icmp sgt i64 [[TMP2914]], [[TMP2915]]
47507 // SIMD-ONLY0-NEXT:    br i1 [[CMP4115]], label [[IF_THEN4117:%.*]], label [[IF_END4118:%.*]]
47508 // SIMD-ONLY0:       if.then4117:
47509 // SIMD-ONLY0-NEXT:    [[TMP2916:%.*]] = load i64, ptr [[LE]], align 8
47510 // SIMD-ONLY0-NEXT:    store i64 [[TMP2916]], ptr [[LX]], align 8
47511 // SIMD-ONLY0-NEXT:    br label [[IF_END4118]]
47512 // SIMD-ONLY0:       if.end4118:
47513 // SIMD-ONLY0-NEXT:    [[TMP2917:%.*]] = load i64, ptr [[LX]], align 8
47514 // SIMD-ONLY0-NEXT:    store i64 [[TMP2917]], ptr [[LV]], align 8
47515 // SIMD-ONLY0-NEXT:    [[TMP2918:%.*]] = load i64, ptr [[LE]], align 8
47516 // SIMD-ONLY0-NEXT:    [[TMP2919:%.*]] = load i64, ptr [[LX]], align 8
47517 // SIMD-ONLY0-NEXT:    [[CMP4119:%.*]] = icmp slt i64 [[TMP2918]], [[TMP2919]]
47518 // SIMD-ONLY0-NEXT:    br i1 [[CMP4119]], label [[IF_THEN4121:%.*]], label [[IF_END4122:%.*]]
47519 // SIMD-ONLY0:       if.then4121:
47520 // SIMD-ONLY0-NEXT:    [[TMP2920:%.*]] = load i64, ptr [[LE]], align 8
47521 // SIMD-ONLY0-NEXT:    store i64 [[TMP2920]], ptr [[LX]], align 8
47522 // SIMD-ONLY0-NEXT:    br label [[IF_END4122]]
47523 // SIMD-ONLY0:       if.end4122:
47524 // SIMD-ONLY0-NEXT:    [[TMP2921:%.*]] = load i64, ptr [[LX]], align 8
47525 // SIMD-ONLY0-NEXT:    store i64 [[TMP2921]], ptr [[LV]], align 8
47526 // SIMD-ONLY0-NEXT:    [[TMP2922:%.*]] = load i64, ptr [[LX]], align 8
47527 // SIMD-ONLY0-NEXT:    [[TMP2923:%.*]] = load i64, ptr [[LE]], align 8
47528 // SIMD-ONLY0-NEXT:    [[CMP4123:%.*]] = icmp slt i64 [[TMP2922]], [[TMP2923]]
47529 // SIMD-ONLY0-NEXT:    br i1 [[CMP4123]], label [[IF_THEN4125:%.*]], label [[IF_END4126:%.*]]
47530 // SIMD-ONLY0:       if.then4125:
47531 // SIMD-ONLY0-NEXT:    [[TMP2924:%.*]] = load i64, ptr [[LE]], align 8
47532 // SIMD-ONLY0-NEXT:    store i64 [[TMP2924]], ptr [[LX]], align 8
47533 // SIMD-ONLY0-NEXT:    br label [[IF_END4126]]
47534 // SIMD-ONLY0:       if.end4126:
47535 // SIMD-ONLY0-NEXT:    [[TMP2925:%.*]] = load i64, ptr [[LX]], align 8
47536 // SIMD-ONLY0-NEXT:    store i64 [[TMP2925]], ptr [[LV]], align 8
47537 // SIMD-ONLY0-NEXT:    [[TMP2926:%.*]] = load i64, ptr [[LX]], align 8
47538 // SIMD-ONLY0-NEXT:    [[TMP2927:%.*]] = load i64, ptr [[LE]], align 8
47539 // SIMD-ONLY0-NEXT:    [[CMP4127:%.*]] = icmp eq i64 [[TMP2926]], [[TMP2927]]
47540 // SIMD-ONLY0-NEXT:    br i1 [[CMP4127]], label [[IF_THEN4129:%.*]], label [[IF_END4130:%.*]]
47541 // SIMD-ONLY0:       if.then4129:
47542 // SIMD-ONLY0-NEXT:    [[TMP2928:%.*]] = load i64, ptr [[LD]], align 8
47543 // SIMD-ONLY0-NEXT:    store i64 [[TMP2928]], ptr [[LX]], align 8
47544 // SIMD-ONLY0-NEXT:    br label [[IF_END4130]]
47545 // SIMD-ONLY0:       if.end4130:
47546 // SIMD-ONLY0-NEXT:    [[TMP2929:%.*]] = load i64, ptr [[LX]], align 8
47547 // SIMD-ONLY0-NEXT:    store i64 [[TMP2929]], ptr [[LV]], align 8
47548 // SIMD-ONLY0-NEXT:    [[TMP2930:%.*]] = load i64, ptr [[LE]], align 8
47549 // SIMD-ONLY0-NEXT:    [[TMP2931:%.*]] = load i64, ptr [[LX]], align 8
47550 // SIMD-ONLY0-NEXT:    [[CMP4131:%.*]] = icmp eq i64 [[TMP2930]], [[TMP2931]]
47551 // SIMD-ONLY0-NEXT:    br i1 [[CMP4131]], label [[IF_THEN4133:%.*]], label [[IF_END4134:%.*]]
47552 // SIMD-ONLY0:       if.then4133:
47553 // SIMD-ONLY0-NEXT:    [[TMP2932:%.*]] = load i64, ptr [[LD]], align 8
47554 // SIMD-ONLY0-NEXT:    store i64 [[TMP2932]], ptr [[LX]], align 8
47555 // SIMD-ONLY0-NEXT:    br label [[IF_END4134]]
47556 // SIMD-ONLY0:       if.end4134:
47557 // SIMD-ONLY0-NEXT:    [[TMP2933:%.*]] = load i64, ptr [[LX]], align 8
47558 // SIMD-ONLY0-NEXT:    store i64 [[TMP2933]], ptr [[LV]], align 8
47559 // SIMD-ONLY0-NEXT:    [[TMP2934:%.*]] = load i64, ptr [[LX]], align 8
47560 // SIMD-ONLY0-NEXT:    [[TMP2935:%.*]] = load i64, ptr [[LE]], align 8
47561 // SIMD-ONLY0-NEXT:    [[CMP4135:%.*]] = icmp eq i64 [[TMP2934]], [[TMP2935]]
47562 // SIMD-ONLY0-NEXT:    br i1 [[CMP4135]], label [[IF_THEN4137:%.*]], label [[IF_ELSE4138:%.*]]
47563 // SIMD-ONLY0:       if.then4137:
47564 // SIMD-ONLY0-NEXT:    [[TMP2936:%.*]] = load i64, ptr [[LD]], align 8
47565 // SIMD-ONLY0-NEXT:    store i64 [[TMP2936]], ptr [[LX]], align 8
47566 // SIMD-ONLY0-NEXT:    br label [[IF_END4139:%.*]]
47567 // SIMD-ONLY0:       if.else4138:
47568 // SIMD-ONLY0-NEXT:    [[TMP2937:%.*]] = load i64, ptr [[LX]], align 8
47569 // SIMD-ONLY0-NEXT:    store i64 [[TMP2937]], ptr [[LV]], align 8
47570 // SIMD-ONLY0-NEXT:    br label [[IF_END4139]]
47571 // SIMD-ONLY0:       if.end4139:
47572 // SIMD-ONLY0-NEXT:    [[TMP2938:%.*]] = load i64, ptr [[LE]], align 8
47573 // SIMD-ONLY0-NEXT:    [[TMP2939:%.*]] = load i64, ptr [[LX]], align 8
47574 // SIMD-ONLY0-NEXT:    [[CMP4140:%.*]] = icmp eq i64 [[TMP2938]], [[TMP2939]]
47575 // SIMD-ONLY0-NEXT:    br i1 [[CMP4140]], label [[IF_THEN4142:%.*]], label [[IF_ELSE4143:%.*]]
47576 // SIMD-ONLY0:       if.then4142:
47577 // SIMD-ONLY0-NEXT:    [[TMP2940:%.*]] = load i64, ptr [[LD]], align 8
47578 // SIMD-ONLY0-NEXT:    store i64 [[TMP2940]], ptr [[LX]], align 8
47579 // SIMD-ONLY0-NEXT:    br label [[IF_END4144:%.*]]
47580 // SIMD-ONLY0:       if.else4143:
47581 // SIMD-ONLY0-NEXT:    [[TMP2941:%.*]] = load i64, ptr [[LX]], align 8
47582 // SIMD-ONLY0-NEXT:    store i64 [[TMP2941]], ptr [[LV]], align 8
47583 // SIMD-ONLY0-NEXT:    br label [[IF_END4144]]
47584 // SIMD-ONLY0:       if.end4144:
47585 // SIMD-ONLY0-NEXT:    [[TMP2942:%.*]] = load i64, ptr [[LX]], align 8
47586 // SIMD-ONLY0-NEXT:    [[TMP2943:%.*]] = load i64, ptr [[LE]], align 8
47587 // SIMD-ONLY0-NEXT:    [[CMP4145:%.*]] = icmp eq i64 [[TMP2942]], [[TMP2943]]
47588 // SIMD-ONLY0-NEXT:    [[CONV4146:%.*]] = zext i1 [[CMP4145]] to i32
47589 // SIMD-ONLY0-NEXT:    [[CONV4147:%.*]] = sext i32 [[CONV4146]] to i64
47590 // SIMD-ONLY0-NEXT:    store i64 [[CONV4147]], ptr [[LR]], align 8
47591 // SIMD-ONLY0-NEXT:    [[TMP2944:%.*]] = load i64, ptr [[LR]], align 8
47592 // SIMD-ONLY0-NEXT:    [[TOBOOL4148:%.*]] = icmp ne i64 [[TMP2944]], 0
47593 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4148]], label [[IF_THEN4149:%.*]], label [[IF_END4150:%.*]]
47594 // SIMD-ONLY0:       if.then4149:
47595 // SIMD-ONLY0-NEXT:    [[TMP2945:%.*]] = load i64, ptr [[LD]], align 8
47596 // SIMD-ONLY0-NEXT:    store i64 [[TMP2945]], ptr [[LX]], align 8
47597 // SIMD-ONLY0-NEXT:    br label [[IF_END4150]]
47598 // SIMD-ONLY0:       if.end4150:
47599 // SIMD-ONLY0-NEXT:    [[TMP2946:%.*]] = load i64, ptr [[LE]], align 8
47600 // SIMD-ONLY0-NEXT:    [[TMP2947:%.*]] = load i64, ptr [[LX]], align 8
47601 // SIMD-ONLY0-NEXT:    [[CMP4151:%.*]] = icmp eq i64 [[TMP2946]], [[TMP2947]]
47602 // SIMD-ONLY0-NEXT:    [[CONV4152:%.*]] = zext i1 [[CMP4151]] to i32
47603 // SIMD-ONLY0-NEXT:    [[CONV4153:%.*]] = sext i32 [[CONV4152]] to i64
47604 // SIMD-ONLY0-NEXT:    store i64 [[CONV4153]], ptr [[LR]], align 8
47605 // SIMD-ONLY0-NEXT:    [[TMP2948:%.*]] = load i64, ptr [[LR]], align 8
47606 // SIMD-ONLY0-NEXT:    [[TOBOOL4154:%.*]] = icmp ne i64 [[TMP2948]], 0
47607 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4154]], label [[IF_THEN4155:%.*]], label [[IF_END4156:%.*]]
47608 // SIMD-ONLY0:       if.then4155:
47609 // SIMD-ONLY0-NEXT:    [[TMP2949:%.*]] = load i64, ptr [[LD]], align 8
47610 // SIMD-ONLY0-NEXT:    store i64 [[TMP2949]], ptr [[LX]], align 8
47611 // SIMD-ONLY0-NEXT:    br label [[IF_END4156]]
47612 // SIMD-ONLY0:       if.end4156:
47613 // SIMD-ONLY0-NEXT:    [[TMP2950:%.*]] = load i64, ptr [[LX]], align 8
47614 // SIMD-ONLY0-NEXT:    [[TMP2951:%.*]] = load i64, ptr [[LE]], align 8
47615 // SIMD-ONLY0-NEXT:    [[CMP4157:%.*]] = icmp eq i64 [[TMP2950]], [[TMP2951]]
47616 // SIMD-ONLY0-NEXT:    [[CONV4158:%.*]] = zext i1 [[CMP4157]] to i32
47617 // SIMD-ONLY0-NEXT:    [[CONV4159:%.*]] = sext i32 [[CONV4158]] to i64
47618 // SIMD-ONLY0-NEXT:    store i64 [[CONV4159]], ptr [[LR]], align 8
47619 // SIMD-ONLY0-NEXT:    [[TMP2952:%.*]] = load i64, ptr [[LR]], align 8
47620 // SIMD-ONLY0-NEXT:    [[TOBOOL4160:%.*]] = icmp ne i64 [[TMP2952]], 0
47621 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4160]], label [[IF_THEN4161:%.*]], label [[IF_ELSE4162:%.*]]
47622 // SIMD-ONLY0:       if.then4161:
47623 // SIMD-ONLY0-NEXT:    [[TMP2953:%.*]] = load i64, ptr [[LD]], align 8
47624 // SIMD-ONLY0-NEXT:    store i64 [[TMP2953]], ptr [[LX]], align 8
47625 // SIMD-ONLY0-NEXT:    br label [[IF_END4163:%.*]]
47626 // SIMD-ONLY0:       if.else4162:
47627 // SIMD-ONLY0-NEXT:    [[TMP2954:%.*]] = load i64, ptr [[LX]], align 8
47628 // SIMD-ONLY0-NEXT:    store i64 [[TMP2954]], ptr [[LV]], align 8
47629 // SIMD-ONLY0-NEXT:    br label [[IF_END4163]]
47630 // SIMD-ONLY0:       if.end4163:
47631 // SIMD-ONLY0-NEXT:    [[TMP2955:%.*]] = load i64, ptr [[LE]], align 8
47632 // SIMD-ONLY0-NEXT:    [[TMP2956:%.*]] = load i64, ptr [[LX]], align 8
47633 // SIMD-ONLY0-NEXT:    [[CMP4164:%.*]] = icmp eq i64 [[TMP2955]], [[TMP2956]]
47634 // SIMD-ONLY0-NEXT:    [[CONV4165:%.*]] = zext i1 [[CMP4164]] to i32
47635 // SIMD-ONLY0-NEXT:    [[CONV4166:%.*]] = sext i32 [[CONV4165]] to i64
47636 // SIMD-ONLY0-NEXT:    store i64 [[CONV4166]], ptr [[LR]], align 8
47637 // SIMD-ONLY0-NEXT:    [[TMP2957:%.*]] = load i64, ptr [[LR]], align 8
47638 // SIMD-ONLY0-NEXT:    [[TOBOOL4167:%.*]] = icmp ne i64 [[TMP2957]], 0
47639 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4167]], label [[IF_THEN4168:%.*]], label [[IF_ELSE4169:%.*]]
47640 // SIMD-ONLY0:       if.then4168:
47641 // SIMD-ONLY0-NEXT:    [[TMP2958:%.*]] = load i64, ptr [[LD]], align 8
47642 // SIMD-ONLY0-NEXT:    store i64 [[TMP2958]], ptr [[LX]], align 8
47643 // SIMD-ONLY0-NEXT:    br label [[IF_END4170:%.*]]
47644 // SIMD-ONLY0:       if.else4169:
47645 // SIMD-ONLY0-NEXT:    [[TMP2959:%.*]] = load i64, ptr [[LX]], align 8
47646 // SIMD-ONLY0-NEXT:    store i64 [[TMP2959]], ptr [[LV]], align 8
47647 // SIMD-ONLY0-NEXT:    br label [[IF_END4170]]
47648 // SIMD-ONLY0:       if.end4170:
47649 // SIMD-ONLY0-NEXT:    [[TMP2960:%.*]] = load i64, ptr [[LX]], align 8
47650 // SIMD-ONLY0-NEXT:    store i64 [[TMP2960]], ptr [[LV]], align 8
47651 // SIMD-ONLY0-NEXT:    [[TMP2961:%.*]] = load i64, ptr [[LE]], align 8
47652 // SIMD-ONLY0-NEXT:    [[TMP2962:%.*]] = load i64, ptr [[LX]], align 8
47653 // SIMD-ONLY0-NEXT:    [[CMP4171:%.*]] = icmp sgt i64 [[TMP2961]], [[TMP2962]]
47654 // SIMD-ONLY0-NEXT:    br i1 [[CMP4171]], label [[IF_THEN4173:%.*]], label [[IF_END4174:%.*]]
47655 // SIMD-ONLY0:       if.then4173:
47656 // SIMD-ONLY0-NEXT:    [[TMP2963:%.*]] = load i64, ptr [[LE]], align 8
47657 // SIMD-ONLY0-NEXT:    store i64 [[TMP2963]], ptr [[LX]], align 8
47658 // SIMD-ONLY0-NEXT:    br label [[IF_END4174]]
47659 // SIMD-ONLY0:       if.end4174:
47660 // SIMD-ONLY0-NEXT:    [[TMP2964:%.*]] = load i64, ptr [[LX]], align 8
47661 // SIMD-ONLY0-NEXT:    store i64 [[TMP2964]], ptr [[LV]], align 8
47662 // SIMD-ONLY0-NEXT:    [[TMP2965:%.*]] = load i64, ptr [[LX]], align 8
47663 // SIMD-ONLY0-NEXT:    [[TMP2966:%.*]] = load i64, ptr [[LE]], align 8
47664 // SIMD-ONLY0-NEXT:    [[CMP4175:%.*]] = icmp sgt i64 [[TMP2965]], [[TMP2966]]
47665 // SIMD-ONLY0-NEXT:    br i1 [[CMP4175]], label [[IF_THEN4177:%.*]], label [[IF_END4178:%.*]]
47666 // SIMD-ONLY0:       if.then4177:
47667 // SIMD-ONLY0-NEXT:    [[TMP2967:%.*]] = load i64, ptr [[LE]], align 8
47668 // SIMD-ONLY0-NEXT:    store i64 [[TMP2967]], ptr [[LX]], align 8
47669 // SIMD-ONLY0-NEXT:    br label [[IF_END4178]]
47670 // SIMD-ONLY0:       if.end4178:
47671 // SIMD-ONLY0-NEXT:    [[TMP2968:%.*]] = load i64, ptr [[LX]], align 8
47672 // SIMD-ONLY0-NEXT:    store i64 [[TMP2968]], ptr [[LV]], align 8
47673 // SIMD-ONLY0-NEXT:    [[TMP2969:%.*]] = load i64, ptr [[LE]], align 8
47674 // SIMD-ONLY0-NEXT:    [[TMP2970:%.*]] = load i64, ptr [[LX]], align 8
47675 // SIMD-ONLY0-NEXT:    [[CMP4179:%.*]] = icmp slt i64 [[TMP2969]], [[TMP2970]]
47676 // SIMD-ONLY0-NEXT:    br i1 [[CMP4179]], label [[IF_THEN4181:%.*]], label [[IF_END4182:%.*]]
47677 // SIMD-ONLY0:       if.then4181:
47678 // SIMD-ONLY0-NEXT:    [[TMP2971:%.*]] = load i64, ptr [[LE]], align 8
47679 // SIMD-ONLY0-NEXT:    store i64 [[TMP2971]], ptr [[LX]], align 8
47680 // SIMD-ONLY0-NEXT:    br label [[IF_END4182]]
47681 // SIMD-ONLY0:       if.end4182:
47682 // SIMD-ONLY0-NEXT:    [[TMP2972:%.*]] = load i64, ptr [[LX]], align 8
47683 // SIMD-ONLY0-NEXT:    store i64 [[TMP2972]], ptr [[LV]], align 8
47684 // SIMD-ONLY0-NEXT:    [[TMP2973:%.*]] = load i64, ptr [[LX]], align 8
47685 // SIMD-ONLY0-NEXT:    [[TMP2974:%.*]] = load i64, ptr [[LE]], align 8
47686 // SIMD-ONLY0-NEXT:    [[CMP4183:%.*]] = icmp slt i64 [[TMP2973]], [[TMP2974]]
47687 // SIMD-ONLY0-NEXT:    br i1 [[CMP4183]], label [[IF_THEN4185:%.*]], label [[IF_END4186:%.*]]
47688 // SIMD-ONLY0:       if.then4185:
47689 // SIMD-ONLY0-NEXT:    [[TMP2975:%.*]] = load i64, ptr [[LE]], align 8
47690 // SIMD-ONLY0-NEXT:    store i64 [[TMP2975]], ptr [[LX]], align 8
47691 // SIMD-ONLY0-NEXT:    br label [[IF_END4186]]
47692 // SIMD-ONLY0:       if.end4186:
47693 // SIMD-ONLY0-NEXT:    [[TMP2976:%.*]] = load i64, ptr [[LX]], align 8
47694 // SIMD-ONLY0-NEXT:    store i64 [[TMP2976]], ptr [[LV]], align 8
47695 // SIMD-ONLY0-NEXT:    [[TMP2977:%.*]] = load i64, ptr [[LX]], align 8
47696 // SIMD-ONLY0-NEXT:    [[TMP2978:%.*]] = load i64, ptr [[LE]], align 8
47697 // SIMD-ONLY0-NEXT:    [[CMP4187:%.*]] = icmp eq i64 [[TMP2977]], [[TMP2978]]
47698 // SIMD-ONLY0-NEXT:    br i1 [[CMP4187]], label [[IF_THEN4189:%.*]], label [[IF_END4190:%.*]]
47699 // SIMD-ONLY0:       if.then4189:
47700 // SIMD-ONLY0-NEXT:    [[TMP2979:%.*]] = load i64, ptr [[LD]], align 8
47701 // SIMD-ONLY0-NEXT:    store i64 [[TMP2979]], ptr [[LX]], align 8
47702 // SIMD-ONLY0-NEXT:    br label [[IF_END4190]]
47703 // SIMD-ONLY0:       if.end4190:
47704 // SIMD-ONLY0-NEXT:    [[TMP2980:%.*]] = load i64, ptr [[LX]], align 8
47705 // SIMD-ONLY0-NEXT:    store i64 [[TMP2980]], ptr [[LV]], align 8
47706 // SIMD-ONLY0-NEXT:    [[TMP2981:%.*]] = load i64, ptr [[LE]], align 8
47707 // SIMD-ONLY0-NEXT:    [[TMP2982:%.*]] = load i64, ptr [[LX]], align 8
47708 // SIMD-ONLY0-NEXT:    [[CMP4191:%.*]] = icmp eq i64 [[TMP2981]], [[TMP2982]]
47709 // SIMD-ONLY0-NEXT:    br i1 [[CMP4191]], label [[IF_THEN4193:%.*]], label [[IF_END4194:%.*]]
47710 // SIMD-ONLY0:       if.then4193:
47711 // SIMD-ONLY0-NEXT:    [[TMP2983:%.*]] = load i64, ptr [[LD]], align 8
47712 // SIMD-ONLY0-NEXT:    store i64 [[TMP2983]], ptr [[LX]], align 8
47713 // SIMD-ONLY0-NEXT:    br label [[IF_END4194]]
47714 // SIMD-ONLY0:       if.end4194:
47715 // SIMD-ONLY0-NEXT:    [[TMP2984:%.*]] = load i64, ptr [[LE]], align 8
47716 // SIMD-ONLY0-NEXT:    [[TMP2985:%.*]] = load i64, ptr [[LX]], align 8
47717 // SIMD-ONLY0-NEXT:    [[CMP4195:%.*]] = icmp sgt i64 [[TMP2984]], [[TMP2985]]
47718 // SIMD-ONLY0-NEXT:    br i1 [[CMP4195]], label [[IF_THEN4197:%.*]], label [[IF_END4198:%.*]]
47719 // SIMD-ONLY0:       if.then4197:
47720 // SIMD-ONLY0-NEXT:    [[TMP2986:%.*]] = load i64, ptr [[LE]], align 8
47721 // SIMD-ONLY0-NEXT:    store i64 [[TMP2986]], ptr [[LX]], align 8
47722 // SIMD-ONLY0-NEXT:    br label [[IF_END4198]]
47723 // SIMD-ONLY0:       if.end4198:
47724 // SIMD-ONLY0-NEXT:    [[TMP2987:%.*]] = load i64, ptr [[LX]], align 8
47725 // SIMD-ONLY0-NEXT:    store i64 [[TMP2987]], ptr [[LV]], align 8
47726 // SIMD-ONLY0-NEXT:    [[TMP2988:%.*]] = load i64, ptr [[LX]], align 8
47727 // SIMD-ONLY0-NEXT:    [[TMP2989:%.*]] = load i64, ptr [[LE]], align 8
47728 // SIMD-ONLY0-NEXT:    [[CMP4199:%.*]] = icmp sgt i64 [[TMP2988]], [[TMP2989]]
47729 // SIMD-ONLY0-NEXT:    br i1 [[CMP4199]], label [[IF_THEN4201:%.*]], label [[IF_END4202:%.*]]
47730 // SIMD-ONLY0:       if.then4201:
47731 // SIMD-ONLY0-NEXT:    [[TMP2990:%.*]] = load i64, ptr [[LE]], align 8
47732 // SIMD-ONLY0-NEXT:    store i64 [[TMP2990]], ptr [[LX]], align 8
47733 // SIMD-ONLY0-NEXT:    br label [[IF_END4202]]
47734 // SIMD-ONLY0:       if.end4202:
47735 // SIMD-ONLY0-NEXT:    [[TMP2991:%.*]] = load i64, ptr [[LX]], align 8
47736 // SIMD-ONLY0-NEXT:    store i64 [[TMP2991]], ptr [[LV]], align 8
47737 // SIMD-ONLY0-NEXT:    [[TMP2992:%.*]] = load i64, ptr [[LE]], align 8
47738 // SIMD-ONLY0-NEXT:    [[TMP2993:%.*]] = load i64, ptr [[LX]], align 8
47739 // SIMD-ONLY0-NEXT:    [[CMP4203:%.*]] = icmp slt i64 [[TMP2992]], [[TMP2993]]
47740 // SIMD-ONLY0-NEXT:    br i1 [[CMP4203]], label [[IF_THEN4205:%.*]], label [[IF_END4206:%.*]]
47741 // SIMD-ONLY0:       if.then4205:
47742 // SIMD-ONLY0-NEXT:    [[TMP2994:%.*]] = load i64, ptr [[LE]], align 8
47743 // SIMD-ONLY0-NEXT:    store i64 [[TMP2994]], ptr [[LX]], align 8
47744 // SIMD-ONLY0-NEXT:    br label [[IF_END4206]]
47745 // SIMD-ONLY0:       if.end4206:
47746 // SIMD-ONLY0-NEXT:    [[TMP2995:%.*]] = load i64, ptr [[LX]], align 8
47747 // SIMD-ONLY0-NEXT:    store i64 [[TMP2995]], ptr [[LV]], align 8
47748 // SIMD-ONLY0-NEXT:    [[TMP2996:%.*]] = load i64, ptr [[LX]], align 8
47749 // SIMD-ONLY0-NEXT:    [[TMP2997:%.*]] = load i64, ptr [[LE]], align 8
47750 // SIMD-ONLY0-NEXT:    [[CMP4207:%.*]] = icmp slt i64 [[TMP2996]], [[TMP2997]]
47751 // SIMD-ONLY0-NEXT:    br i1 [[CMP4207]], label [[IF_THEN4209:%.*]], label [[IF_END4210:%.*]]
47752 // SIMD-ONLY0:       if.then4209:
47753 // SIMD-ONLY0-NEXT:    [[TMP2998:%.*]] = load i64, ptr [[LE]], align 8
47754 // SIMD-ONLY0-NEXT:    store i64 [[TMP2998]], ptr [[LX]], align 8
47755 // SIMD-ONLY0-NEXT:    br label [[IF_END4210]]
47756 // SIMD-ONLY0:       if.end4210:
47757 // SIMD-ONLY0-NEXT:    [[TMP2999:%.*]] = load i64, ptr [[LX]], align 8
47758 // SIMD-ONLY0-NEXT:    store i64 [[TMP2999]], ptr [[LV]], align 8
47759 // SIMD-ONLY0-NEXT:    [[TMP3000:%.*]] = load i64, ptr [[LX]], align 8
47760 // SIMD-ONLY0-NEXT:    [[TMP3001:%.*]] = load i64, ptr [[LE]], align 8
47761 // SIMD-ONLY0-NEXT:    [[CMP4211:%.*]] = icmp eq i64 [[TMP3000]], [[TMP3001]]
47762 // SIMD-ONLY0-NEXT:    br i1 [[CMP4211]], label [[IF_THEN4213:%.*]], label [[IF_END4214:%.*]]
47763 // SIMD-ONLY0:       if.then4213:
47764 // SIMD-ONLY0-NEXT:    [[TMP3002:%.*]] = load i64, ptr [[LD]], align 8
47765 // SIMD-ONLY0-NEXT:    store i64 [[TMP3002]], ptr [[LX]], align 8
47766 // SIMD-ONLY0-NEXT:    br label [[IF_END4214]]
47767 // SIMD-ONLY0:       if.end4214:
47768 // SIMD-ONLY0-NEXT:    [[TMP3003:%.*]] = load i64, ptr [[LX]], align 8
47769 // SIMD-ONLY0-NEXT:    store i64 [[TMP3003]], ptr [[LV]], align 8
47770 // SIMD-ONLY0-NEXT:    [[TMP3004:%.*]] = load i64, ptr [[LE]], align 8
47771 // SIMD-ONLY0-NEXT:    [[TMP3005:%.*]] = load i64, ptr [[LX]], align 8
47772 // SIMD-ONLY0-NEXT:    [[CMP4215:%.*]] = icmp eq i64 [[TMP3004]], [[TMP3005]]
47773 // SIMD-ONLY0-NEXT:    br i1 [[CMP4215]], label [[IF_THEN4217:%.*]], label [[IF_END4218:%.*]]
47774 // SIMD-ONLY0:       if.then4217:
47775 // SIMD-ONLY0-NEXT:    [[TMP3006:%.*]] = load i64, ptr [[LD]], align 8
47776 // SIMD-ONLY0-NEXT:    store i64 [[TMP3006]], ptr [[LX]], align 8
47777 // SIMD-ONLY0-NEXT:    br label [[IF_END4218]]
47778 // SIMD-ONLY0:       if.end4218:
47779 // SIMD-ONLY0-NEXT:    [[TMP3007:%.*]] = load i64, ptr [[LX]], align 8
47780 // SIMD-ONLY0-NEXT:    store i64 [[TMP3007]], ptr [[LV]], align 8
47781 // SIMD-ONLY0-NEXT:    [[TMP3008:%.*]] = load i64, ptr [[LX]], align 8
47782 // SIMD-ONLY0-NEXT:    [[TMP3009:%.*]] = load i64, ptr [[LE]], align 8
47783 // SIMD-ONLY0-NEXT:    [[CMP4219:%.*]] = icmp eq i64 [[TMP3008]], [[TMP3009]]
47784 // SIMD-ONLY0-NEXT:    br i1 [[CMP4219]], label [[IF_THEN4221:%.*]], label [[IF_ELSE4222:%.*]]
47785 // SIMD-ONLY0:       if.then4221:
47786 // SIMD-ONLY0-NEXT:    [[TMP3010:%.*]] = load i64, ptr [[LD]], align 8
47787 // SIMD-ONLY0-NEXT:    store i64 [[TMP3010]], ptr [[LX]], align 8
47788 // SIMD-ONLY0-NEXT:    br label [[IF_END4223:%.*]]
47789 // SIMD-ONLY0:       if.else4222:
47790 // SIMD-ONLY0-NEXT:    [[TMP3011:%.*]] = load i64, ptr [[LX]], align 8
47791 // SIMD-ONLY0-NEXT:    store i64 [[TMP3011]], ptr [[LV]], align 8
47792 // SIMD-ONLY0-NEXT:    br label [[IF_END4223]]
47793 // SIMD-ONLY0:       if.end4223:
47794 // SIMD-ONLY0-NEXT:    [[TMP3012:%.*]] = load i64, ptr [[LE]], align 8
47795 // SIMD-ONLY0-NEXT:    [[TMP3013:%.*]] = load i64, ptr [[LX]], align 8
47796 // SIMD-ONLY0-NEXT:    [[CMP4224:%.*]] = icmp eq i64 [[TMP3012]], [[TMP3013]]
47797 // SIMD-ONLY0-NEXT:    br i1 [[CMP4224]], label [[IF_THEN4226:%.*]], label [[IF_ELSE4227:%.*]]
47798 // SIMD-ONLY0:       if.then4226:
47799 // SIMD-ONLY0-NEXT:    [[TMP3014:%.*]] = load i64, ptr [[LD]], align 8
47800 // SIMD-ONLY0-NEXT:    store i64 [[TMP3014]], ptr [[LX]], align 8
47801 // SIMD-ONLY0-NEXT:    br label [[IF_END4228:%.*]]
47802 // SIMD-ONLY0:       if.else4227:
47803 // SIMD-ONLY0-NEXT:    [[TMP3015:%.*]] = load i64, ptr [[LX]], align 8
47804 // SIMD-ONLY0-NEXT:    store i64 [[TMP3015]], ptr [[LV]], align 8
47805 // SIMD-ONLY0-NEXT:    br label [[IF_END4228]]
47806 // SIMD-ONLY0:       if.end4228:
47807 // SIMD-ONLY0-NEXT:    [[TMP3016:%.*]] = load i64, ptr [[LX]], align 8
47808 // SIMD-ONLY0-NEXT:    [[TMP3017:%.*]] = load i64, ptr [[LE]], align 8
47809 // SIMD-ONLY0-NEXT:    [[CMP4229:%.*]] = icmp eq i64 [[TMP3016]], [[TMP3017]]
47810 // SIMD-ONLY0-NEXT:    [[CONV4230:%.*]] = zext i1 [[CMP4229]] to i32
47811 // SIMD-ONLY0-NEXT:    [[CONV4231:%.*]] = sext i32 [[CONV4230]] to i64
47812 // SIMD-ONLY0-NEXT:    store i64 [[CONV4231]], ptr [[LR]], align 8
47813 // SIMD-ONLY0-NEXT:    [[TMP3018:%.*]] = load i64, ptr [[LR]], align 8
47814 // SIMD-ONLY0-NEXT:    [[TOBOOL4232:%.*]] = icmp ne i64 [[TMP3018]], 0
47815 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4232]], label [[IF_THEN4233:%.*]], label [[IF_END4234:%.*]]
47816 // SIMD-ONLY0:       if.then4233:
47817 // SIMD-ONLY0-NEXT:    [[TMP3019:%.*]] = load i64, ptr [[LD]], align 8
47818 // SIMD-ONLY0-NEXT:    store i64 [[TMP3019]], ptr [[LX]], align 8
47819 // SIMD-ONLY0-NEXT:    br label [[IF_END4234]]
47820 // SIMD-ONLY0:       if.end4234:
47821 // SIMD-ONLY0-NEXT:    [[TMP3020:%.*]] = load i64, ptr [[LE]], align 8
47822 // SIMD-ONLY0-NEXT:    [[TMP3021:%.*]] = load i64, ptr [[LX]], align 8
47823 // SIMD-ONLY0-NEXT:    [[CMP4235:%.*]] = icmp eq i64 [[TMP3020]], [[TMP3021]]
47824 // SIMD-ONLY0-NEXT:    [[CONV4236:%.*]] = zext i1 [[CMP4235]] to i32
47825 // SIMD-ONLY0-NEXT:    [[CONV4237:%.*]] = sext i32 [[CONV4236]] to i64
47826 // SIMD-ONLY0-NEXT:    store i64 [[CONV4237]], ptr [[LR]], align 8
47827 // SIMD-ONLY0-NEXT:    [[TMP3022:%.*]] = load i64, ptr [[LR]], align 8
47828 // SIMD-ONLY0-NEXT:    [[TOBOOL4238:%.*]] = icmp ne i64 [[TMP3022]], 0
47829 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4238]], label [[IF_THEN4239:%.*]], label [[IF_END4240:%.*]]
47830 // SIMD-ONLY0:       if.then4239:
47831 // SIMD-ONLY0-NEXT:    [[TMP3023:%.*]] = load i64, ptr [[LD]], align 8
47832 // SIMD-ONLY0-NEXT:    store i64 [[TMP3023]], ptr [[LX]], align 8
47833 // SIMD-ONLY0-NEXT:    br label [[IF_END4240]]
47834 // SIMD-ONLY0:       if.end4240:
47835 // SIMD-ONLY0-NEXT:    [[TMP3024:%.*]] = load i64, ptr [[LX]], align 8
47836 // SIMD-ONLY0-NEXT:    [[TMP3025:%.*]] = load i64, ptr [[LE]], align 8
47837 // SIMD-ONLY0-NEXT:    [[CMP4241:%.*]] = icmp eq i64 [[TMP3024]], [[TMP3025]]
47838 // SIMD-ONLY0-NEXT:    [[CONV4242:%.*]] = zext i1 [[CMP4241]] to i32
47839 // SIMD-ONLY0-NEXT:    [[CONV4243:%.*]] = sext i32 [[CONV4242]] to i64
47840 // SIMD-ONLY0-NEXT:    store i64 [[CONV4243]], ptr [[LR]], align 8
47841 // SIMD-ONLY0-NEXT:    [[TMP3026:%.*]] = load i64, ptr [[LR]], align 8
47842 // SIMD-ONLY0-NEXT:    [[TOBOOL4244:%.*]] = icmp ne i64 [[TMP3026]], 0
47843 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4244]], label [[IF_THEN4245:%.*]], label [[IF_ELSE4246:%.*]]
47844 // SIMD-ONLY0:       if.then4245:
47845 // SIMD-ONLY0-NEXT:    [[TMP3027:%.*]] = load i64, ptr [[LD]], align 8
47846 // SIMD-ONLY0-NEXT:    store i64 [[TMP3027]], ptr [[LX]], align 8
47847 // SIMD-ONLY0-NEXT:    br label [[IF_END4247:%.*]]
47848 // SIMD-ONLY0:       if.else4246:
47849 // SIMD-ONLY0-NEXT:    [[TMP3028:%.*]] = load i64, ptr [[LX]], align 8
47850 // SIMD-ONLY0-NEXT:    store i64 [[TMP3028]], ptr [[LV]], align 8
47851 // SIMD-ONLY0-NEXT:    br label [[IF_END4247]]
47852 // SIMD-ONLY0:       if.end4247:
47853 // SIMD-ONLY0-NEXT:    [[TMP3029:%.*]] = load i64, ptr [[LE]], align 8
47854 // SIMD-ONLY0-NEXT:    [[TMP3030:%.*]] = load i64, ptr [[LX]], align 8
47855 // SIMD-ONLY0-NEXT:    [[CMP4248:%.*]] = icmp eq i64 [[TMP3029]], [[TMP3030]]
47856 // SIMD-ONLY0-NEXT:    [[CONV4249:%.*]] = zext i1 [[CMP4248]] to i32
47857 // SIMD-ONLY0-NEXT:    [[CONV4250:%.*]] = sext i32 [[CONV4249]] to i64
47858 // SIMD-ONLY0-NEXT:    store i64 [[CONV4250]], ptr [[LR]], align 8
47859 // SIMD-ONLY0-NEXT:    [[TMP3031:%.*]] = load i64, ptr [[LR]], align 8
47860 // SIMD-ONLY0-NEXT:    [[TOBOOL4251:%.*]] = icmp ne i64 [[TMP3031]], 0
47861 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4251]], label [[IF_THEN4252:%.*]], label [[IF_ELSE4253:%.*]]
47862 // SIMD-ONLY0:       if.then4252:
47863 // SIMD-ONLY0-NEXT:    [[TMP3032:%.*]] = load i64, ptr [[LD]], align 8
47864 // SIMD-ONLY0-NEXT:    store i64 [[TMP3032]], ptr [[LX]], align 8
47865 // SIMD-ONLY0-NEXT:    br label [[IF_END4254:%.*]]
47866 // SIMD-ONLY0:       if.else4253:
47867 // SIMD-ONLY0-NEXT:    [[TMP3033:%.*]] = load i64, ptr [[LX]], align 8
47868 // SIMD-ONLY0-NEXT:    store i64 [[TMP3033]], ptr [[LV]], align 8
47869 // SIMD-ONLY0-NEXT:    br label [[IF_END4254]]
47870 // SIMD-ONLY0:       if.end4254:
47871 // SIMD-ONLY0-NEXT:    [[TMP3034:%.*]] = load i64, ptr [[LX]], align 8
47872 // SIMD-ONLY0-NEXT:    store i64 [[TMP3034]], ptr [[LV]], align 8
47873 // SIMD-ONLY0-NEXT:    [[TMP3035:%.*]] = load i64, ptr [[LE]], align 8
47874 // SIMD-ONLY0-NEXT:    [[TMP3036:%.*]] = load i64, ptr [[LX]], align 8
47875 // SIMD-ONLY0-NEXT:    [[CMP4255:%.*]] = icmp sgt i64 [[TMP3035]], [[TMP3036]]
47876 // SIMD-ONLY0-NEXT:    br i1 [[CMP4255]], label [[IF_THEN4257:%.*]], label [[IF_END4258:%.*]]
47877 // SIMD-ONLY0:       if.then4257:
47878 // SIMD-ONLY0-NEXT:    [[TMP3037:%.*]] = load i64, ptr [[LE]], align 8
47879 // SIMD-ONLY0-NEXT:    store i64 [[TMP3037]], ptr [[LX]], align 8
47880 // SIMD-ONLY0-NEXT:    br label [[IF_END4258]]
47881 // SIMD-ONLY0:       if.end4258:
47882 // SIMD-ONLY0-NEXT:    [[TMP3038:%.*]] = load i64, ptr [[LX]], align 8
47883 // SIMD-ONLY0-NEXT:    store i64 [[TMP3038]], ptr [[LV]], align 8
47884 // SIMD-ONLY0-NEXT:    [[TMP3039:%.*]] = load i64, ptr [[LX]], align 8
47885 // SIMD-ONLY0-NEXT:    [[TMP3040:%.*]] = load i64, ptr [[LE]], align 8
47886 // SIMD-ONLY0-NEXT:    [[CMP4259:%.*]] = icmp sgt i64 [[TMP3039]], [[TMP3040]]
47887 // SIMD-ONLY0-NEXT:    br i1 [[CMP4259]], label [[IF_THEN4261:%.*]], label [[IF_END4262:%.*]]
47888 // SIMD-ONLY0:       if.then4261:
47889 // SIMD-ONLY0-NEXT:    [[TMP3041:%.*]] = load i64, ptr [[LE]], align 8
47890 // SIMD-ONLY0-NEXT:    store i64 [[TMP3041]], ptr [[LX]], align 8
47891 // SIMD-ONLY0-NEXT:    br label [[IF_END4262]]
47892 // SIMD-ONLY0:       if.end4262:
47893 // SIMD-ONLY0-NEXT:    [[TMP3042:%.*]] = load i64, ptr [[LX]], align 8
47894 // SIMD-ONLY0-NEXT:    store i64 [[TMP3042]], ptr [[LV]], align 8
47895 // SIMD-ONLY0-NEXT:    [[TMP3043:%.*]] = load i64, ptr [[LE]], align 8
47896 // SIMD-ONLY0-NEXT:    [[TMP3044:%.*]] = load i64, ptr [[LX]], align 8
47897 // SIMD-ONLY0-NEXT:    [[CMP4263:%.*]] = icmp slt i64 [[TMP3043]], [[TMP3044]]
47898 // SIMD-ONLY0-NEXT:    br i1 [[CMP4263]], label [[IF_THEN4265:%.*]], label [[IF_END4266:%.*]]
47899 // SIMD-ONLY0:       if.then4265:
47900 // SIMD-ONLY0-NEXT:    [[TMP3045:%.*]] = load i64, ptr [[LE]], align 8
47901 // SIMD-ONLY0-NEXT:    store i64 [[TMP3045]], ptr [[LX]], align 8
47902 // SIMD-ONLY0-NEXT:    br label [[IF_END4266]]
47903 // SIMD-ONLY0:       if.end4266:
47904 // SIMD-ONLY0-NEXT:    [[TMP3046:%.*]] = load i64, ptr [[LX]], align 8
47905 // SIMD-ONLY0-NEXT:    store i64 [[TMP3046]], ptr [[LV]], align 8
47906 // SIMD-ONLY0-NEXT:    [[TMP3047:%.*]] = load i64, ptr [[LX]], align 8
47907 // SIMD-ONLY0-NEXT:    [[TMP3048:%.*]] = load i64, ptr [[LE]], align 8
47908 // SIMD-ONLY0-NEXT:    [[CMP4267:%.*]] = icmp slt i64 [[TMP3047]], [[TMP3048]]
47909 // SIMD-ONLY0-NEXT:    br i1 [[CMP4267]], label [[IF_THEN4269:%.*]], label [[IF_END4270:%.*]]
47910 // SIMD-ONLY0:       if.then4269:
47911 // SIMD-ONLY0-NEXT:    [[TMP3049:%.*]] = load i64, ptr [[LE]], align 8
47912 // SIMD-ONLY0-NEXT:    store i64 [[TMP3049]], ptr [[LX]], align 8
47913 // SIMD-ONLY0-NEXT:    br label [[IF_END4270]]
47914 // SIMD-ONLY0:       if.end4270:
47915 // SIMD-ONLY0-NEXT:    [[TMP3050:%.*]] = load i64, ptr [[LX]], align 8
47916 // SIMD-ONLY0-NEXT:    store i64 [[TMP3050]], ptr [[LV]], align 8
47917 // SIMD-ONLY0-NEXT:    [[TMP3051:%.*]] = load i64, ptr [[LX]], align 8
47918 // SIMD-ONLY0-NEXT:    [[TMP3052:%.*]] = load i64, ptr [[LE]], align 8
47919 // SIMD-ONLY0-NEXT:    [[CMP4271:%.*]] = icmp eq i64 [[TMP3051]], [[TMP3052]]
47920 // SIMD-ONLY0-NEXT:    br i1 [[CMP4271]], label [[IF_THEN4273:%.*]], label [[IF_END4274:%.*]]
47921 // SIMD-ONLY0:       if.then4273:
47922 // SIMD-ONLY0-NEXT:    [[TMP3053:%.*]] = load i64, ptr [[LD]], align 8
47923 // SIMD-ONLY0-NEXT:    store i64 [[TMP3053]], ptr [[LX]], align 8
47924 // SIMD-ONLY0-NEXT:    br label [[IF_END4274]]
47925 // SIMD-ONLY0:       if.end4274:
47926 // SIMD-ONLY0-NEXT:    [[TMP3054:%.*]] = load i64, ptr [[LX]], align 8
47927 // SIMD-ONLY0-NEXT:    store i64 [[TMP3054]], ptr [[LV]], align 8
47928 // SIMD-ONLY0-NEXT:    [[TMP3055:%.*]] = load i64, ptr [[LE]], align 8
47929 // SIMD-ONLY0-NEXT:    [[TMP3056:%.*]] = load i64, ptr [[LX]], align 8
47930 // SIMD-ONLY0-NEXT:    [[CMP4275:%.*]] = icmp eq i64 [[TMP3055]], [[TMP3056]]
47931 // SIMD-ONLY0-NEXT:    br i1 [[CMP4275]], label [[IF_THEN4277:%.*]], label [[IF_END4278:%.*]]
47932 // SIMD-ONLY0:       if.then4277:
47933 // SIMD-ONLY0-NEXT:    [[TMP3057:%.*]] = load i64, ptr [[LD]], align 8
47934 // SIMD-ONLY0-NEXT:    store i64 [[TMP3057]], ptr [[LX]], align 8
47935 // SIMD-ONLY0-NEXT:    br label [[IF_END4278]]
47936 // SIMD-ONLY0:       if.end4278:
47937 // SIMD-ONLY0-NEXT:    [[TMP3058:%.*]] = load i64, ptr [[LE]], align 8
47938 // SIMD-ONLY0-NEXT:    [[TMP3059:%.*]] = load i64, ptr [[LX]], align 8
47939 // SIMD-ONLY0-NEXT:    [[CMP4279:%.*]] = icmp sgt i64 [[TMP3058]], [[TMP3059]]
47940 // SIMD-ONLY0-NEXT:    br i1 [[CMP4279]], label [[IF_THEN4281:%.*]], label [[IF_END4282:%.*]]
47941 // SIMD-ONLY0:       if.then4281:
47942 // SIMD-ONLY0-NEXT:    [[TMP3060:%.*]] = load i64, ptr [[LE]], align 8
47943 // SIMD-ONLY0-NEXT:    store i64 [[TMP3060]], ptr [[LX]], align 8
47944 // SIMD-ONLY0-NEXT:    br label [[IF_END4282]]
47945 // SIMD-ONLY0:       if.end4282:
47946 // SIMD-ONLY0-NEXT:    [[TMP3061:%.*]] = load i64, ptr [[LX]], align 8
47947 // SIMD-ONLY0-NEXT:    store i64 [[TMP3061]], ptr [[LV]], align 8
47948 // SIMD-ONLY0-NEXT:    [[TMP3062:%.*]] = load i64, ptr [[LX]], align 8
47949 // SIMD-ONLY0-NEXT:    [[TMP3063:%.*]] = load i64, ptr [[LE]], align 8
47950 // SIMD-ONLY0-NEXT:    [[CMP4283:%.*]] = icmp sgt i64 [[TMP3062]], [[TMP3063]]
47951 // SIMD-ONLY0-NEXT:    br i1 [[CMP4283]], label [[IF_THEN4285:%.*]], label [[IF_END4286:%.*]]
47952 // SIMD-ONLY0:       if.then4285:
47953 // SIMD-ONLY0-NEXT:    [[TMP3064:%.*]] = load i64, ptr [[LE]], align 8
47954 // SIMD-ONLY0-NEXT:    store i64 [[TMP3064]], ptr [[LX]], align 8
47955 // SIMD-ONLY0-NEXT:    br label [[IF_END4286]]
47956 // SIMD-ONLY0:       if.end4286:
47957 // SIMD-ONLY0-NEXT:    [[TMP3065:%.*]] = load i64, ptr [[LX]], align 8
47958 // SIMD-ONLY0-NEXT:    store i64 [[TMP3065]], ptr [[LV]], align 8
47959 // SIMD-ONLY0-NEXT:    [[TMP3066:%.*]] = load i64, ptr [[LE]], align 8
47960 // SIMD-ONLY0-NEXT:    [[TMP3067:%.*]] = load i64, ptr [[LX]], align 8
47961 // SIMD-ONLY0-NEXT:    [[CMP4287:%.*]] = icmp slt i64 [[TMP3066]], [[TMP3067]]
47962 // SIMD-ONLY0-NEXT:    br i1 [[CMP4287]], label [[IF_THEN4289:%.*]], label [[IF_END4290:%.*]]
47963 // SIMD-ONLY0:       if.then4289:
47964 // SIMD-ONLY0-NEXT:    [[TMP3068:%.*]] = load i64, ptr [[LE]], align 8
47965 // SIMD-ONLY0-NEXT:    store i64 [[TMP3068]], ptr [[LX]], align 8
47966 // SIMD-ONLY0-NEXT:    br label [[IF_END4290]]
47967 // SIMD-ONLY0:       if.end4290:
47968 // SIMD-ONLY0-NEXT:    [[TMP3069:%.*]] = load i64, ptr [[LX]], align 8
47969 // SIMD-ONLY0-NEXT:    store i64 [[TMP3069]], ptr [[LV]], align 8
47970 // SIMD-ONLY0-NEXT:    [[TMP3070:%.*]] = load i64, ptr [[LX]], align 8
47971 // SIMD-ONLY0-NEXT:    [[TMP3071:%.*]] = load i64, ptr [[LE]], align 8
47972 // SIMD-ONLY0-NEXT:    [[CMP4291:%.*]] = icmp slt i64 [[TMP3070]], [[TMP3071]]
47973 // SIMD-ONLY0-NEXT:    br i1 [[CMP4291]], label [[IF_THEN4293:%.*]], label [[IF_END4294:%.*]]
47974 // SIMD-ONLY0:       if.then4293:
47975 // SIMD-ONLY0-NEXT:    [[TMP3072:%.*]] = load i64, ptr [[LE]], align 8
47976 // SIMD-ONLY0-NEXT:    store i64 [[TMP3072]], ptr [[LX]], align 8
47977 // SIMD-ONLY0-NEXT:    br label [[IF_END4294]]
47978 // SIMD-ONLY0:       if.end4294:
47979 // SIMD-ONLY0-NEXT:    [[TMP3073:%.*]] = load i64, ptr [[LX]], align 8
47980 // SIMD-ONLY0-NEXT:    store i64 [[TMP3073]], ptr [[LV]], align 8
47981 // SIMD-ONLY0-NEXT:    [[TMP3074:%.*]] = load i64, ptr [[LX]], align 8
47982 // SIMD-ONLY0-NEXT:    [[TMP3075:%.*]] = load i64, ptr [[LE]], align 8
47983 // SIMD-ONLY0-NEXT:    [[CMP4295:%.*]] = icmp eq i64 [[TMP3074]], [[TMP3075]]
47984 // SIMD-ONLY0-NEXT:    br i1 [[CMP4295]], label [[IF_THEN4297:%.*]], label [[IF_END4298:%.*]]
47985 // SIMD-ONLY0:       if.then4297:
47986 // SIMD-ONLY0-NEXT:    [[TMP3076:%.*]] = load i64, ptr [[LD]], align 8
47987 // SIMD-ONLY0-NEXT:    store i64 [[TMP3076]], ptr [[LX]], align 8
47988 // SIMD-ONLY0-NEXT:    br label [[IF_END4298]]
47989 // SIMD-ONLY0:       if.end4298:
47990 // SIMD-ONLY0-NEXT:    [[TMP3077:%.*]] = load i64, ptr [[LX]], align 8
47991 // SIMD-ONLY0-NEXT:    store i64 [[TMP3077]], ptr [[LV]], align 8
47992 // SIMD-ONLY0-NEXT:    [[TMP3078:%.*]] = load i64, ptr [[LE]], align 8
47993 // SIMD-ONLY0-NEXT:    [[TMP3079:%.*]] = load i64, ptr [[LX]], align 8
47994 // SIMD-ONLY0-NEXT:    [[CMP4299:%.*]] = icmp eq i64 [[TMP3078]], [[TMP3079]]
47995 // SIMD-ONLY0-NEXT:    br i1 [[CMP4299]], label [[IF_THEN4301:%.*]], label [[IF_END4302:%.*]]
47996 // SIMD-ONLY0:       if.then4301:
47997 // SIMD-ONLY0-NEXT:    [[TMP3080:%.*]] = load i64, ptr [[LD]], align 8
47998 // SIMD-ONLY0-NEXT:    store i64 [[TMP3080]], ptr [[LX]], align 8
47999 // SIMD-ONLY0-NEXT:    br label [[IF_END4302]]
48000 // SIMD-ONLY0:       if.end4302:
48001 // SIMD-ONLY0-NEXT:    [[TMP3081:%.*]] = load i64, ptr [[LX]], align 8
48002 // SIMD-ONLY0-NEXT:    store i64 [[TMP3081]], ptr [[LV]], align 8
48003 // SIMD-ONLY0-NEXT:    [[TMP3082:%.*]] = load i64, ptr [[LX]], align 8
48004 // SIMD-ONLY0-NEXT:    [[TMP3083:%.*]] = load i64, ptr [[LE]], align 8
48005 // SIMD-ONLY0-NEXT:    [[CMP4303:%.*]] = icmp eq i64 [[TMP3082]], [[TMP3083]]
48006 // SIMD-ONLY0-NEXT:    br i1 [[CMP4303]], label [[IF_THEN4305:%.*]], label [[IF_ELSE4306:%.*]]
48007 // SIMD-ONLY0:       if.then4305:
48008 // SIMD-ONLY0-NEXT:    [[TMP3084:%.*]] = load i64, ptr [[LD]], align 8
48009 // SIMD-ONLY0-NEXT:    store i64 [[TMP3084]], ptr [[LX]], align 8
48010 // SIMD-ONLY0-NEXT:    br label [[IF_END4307:%.*]]
48011 // SIMD-ONLY0:       if.else4306:
48012 // SIMD-ONLY0-NEXT:    [[TMP3085:%.*]] = load i64, ptr [[LX]], align 8
48013 // SIMD-ONLY0-NEXT:    store i64 [[TMP3085]], ptr [[LV]], align 8
48014 // SIMD-ONLY0-NEXT:    br label [[IF_END4307]]
48015 // SIMD-ONLY0:       if.end4307:
48016 // SIMD-ONLY0-NEXT:    [[TMP3086:%.*]] = load i64, ptr [[LE]], align 8
48017 // SIMD-ONLY0-NEXT:    [[TMP3087:%.*]] = load i64, ptr [[LX]], align 8
48018 // SIMD-ONLY0-NEXT:    [[CMP4308:%.*]] = icmp eq i64 [[TMP3086]], [[TMP3087]]
48019 // SIMD-ONLY0-NEXT:    br i1 [[CMP4308]], label [[IF_THEN4310:%.*]], label [[IF_ELSE4311:%.*]]
48020 // SIMD-ONLY0:       if.then4310:
48021 // SIMD-ONLY0-NEXT:    [[TMP3088:%.*]] = load i64, ptr [[LD]], align 8
48022 // SIMD-ONLY0-NEXT:    store i64 [[TMP3088]], ptr [[LX]], align 8
48023 // SIMD-ONLY0-NEXT:    br label [[IF_END4312:%.*]]
48024 // SIMD-ONLY0:       if.else4311:
48025 // SIMD-ONLY0-NEXT:    [[TMP3089:%.*]] = load i64, ptr [[LX]], align 8
48026 // SIMD-ONLY0-NEXT:    store i64 [[TMP3089]], ptr [[LV]], align 8
48027 // SIMD-ONLY0-NEXT:    br label [[IF_END4312]]
48028 // SIMD-ONLY0:       if.end4312:
48029 // SIMD-ONLY0-NEXT:    [[TMP3090:%.*]] = load i64, ptr [[LX]], align 8
48030 // SIMD-ONLY0-NEXT:    [[TMP3091:%.*]] = load i64, ptr [[LE]], align 8
48031 // SIMD-ONLY0-NEXT:    [[CMP4313:%.*]] = icmp eq i64 [[TMP3090]], [[TMP3091]]
48032 // SIMD-ONLY0-NEXT:    [[CONV4314:%.*]] = zext i1 [[CMP4313]] to i32
48033 // SIMD-ONLY0-NEXT:    [[CONV4315:%.*]] = sext i32 [[CONV4314]] to i64
48034 // SIMD-ONLY0-NEXT:    store i64 [[CONV4315]], ptr [[LR]], align 8
48035 // SIMD-ONLY0-NEXT:    [[TMP3092:%.*]] = load i64, ptr [[LR]], align 8
48036 // SIMD-ONLY0-NEXT:    [[TOBOOL4316:%.*]] = icmp ne i64 [[TMP3092]], 0
48037 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4316]], label [[IF_THEN4317:%.*]], label [[IF_END4318:%.*]]
48038 // SIMD-ONLY0:       if.then4317:
48039 // SIMD-ONLY0-NEXT:    [[TMP3093:%.*]] = load i64, ptr [[LD]], align 8
48040 // SIMD-ONLY0-NEXT:    store i64 [[TMP3093]], ptr [[LX]], align 8
48041 // SIMD-ONLY0-NEXT:    br label [[IF_END4318]]
48042 // SIMD-ONLY0:       if.end4318:
48043 // SIMD-ONLY0-NEXT:    [[TMP3094:%.*]] = load i64, ptr [[LE]], align 8
48044 // SIMD-ONLY0-NEXT:    [[TMP3095:%.*]] = load i64, ptr [[LX]], align 8
48045 // SIMD-ONLY0-NEXT:    [[CMP4319:%.*]] = icmp eq i64 [[TMP3094]], [[TMP3095]]
48046 // SIMD-ONLY0-NEXT:    [[CONV4320:%.*]] = zext i1 [[CMP4319]] to i32
48047 // SIMD-ONLY0-NEXT:    [[CONV4321:%.*]] = sext i32 [[CONV4320]] to i64
48048 // SIMD-ONLY0-NEXT:    store i64 [[CONV4321]], ptr [[LR]], align 8
48049 // SIMD-ONLY0-NEXT:    [[TMP3096:%.*]] = load i64, ptr [[LR]], align 8
48050 // SIMD-ONLY0-NEXT:    [[TOBOOL4322:%.*]] = icmp ne i64 [[TMP3096]], 0
48051 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4322]], label [[IF_THEN4323:%.*]], label [[IF_END4324:%.*]]
48052 // SIMD-ONLY0:       if.then4323:
48053 // SIMD-ONLY0-NEXT:    [[TMP3097:%.*]] = load i64, ptr [[LD]], align 8
48054 // SIMD-ONLY0-NEXT:    store i64 [[TMP3097]], ptr [[LX]], align 8
48055 // SIMD-ONLY0-NEXT:    br label [[IF_END4324]]
48056 // SIMD-ONLY0:       if.end4324:
48057 // SIMD-ONLY0-NEXT:    [[TMP3098:%.*]] = load i64, ptr [[LX]], align 8
48058 // SIMD-ONLY0-NEXT:    [[TMP3099:%.*]] = load i64, ptr [[LE]], align 8
48059 // SIMD-ONLY0-NEXT:    [[CMP4325:%.*]] = icmp eq i64 [[TMP3098]], [[TMP3099]]
48060 // SIMD-ONLY0-NEXT:    [[CONV4326:%.*]] = zext i1 [[CMP4325]] to i32
48061 // SIMD-ONLY0-NEXT:    [[CONV4327:%.*]] = sext i32 [[CONV4326]] to i64
48062 // SIMD-ONLY0-NEXT:    store i64 [[CONV4327]], ptr [[LR]], align 8
48063 // SIMD-ONLY0-NEXT:    [[TMP3100:%.*]] = load i64, ptr [[LR]], align 8
48064 // SIMD-ONLY0-NEXT:    [[TOBOOL4328:%.*]] = icmp ne i64 [[TMP3100]], 0
48065 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4328]], label [[IF_THEN4329:%.*]], label [[IF_ELSE4330:%.*]]
48066 // SIMD-ONLY0:       if.then4329:
48067 // SIMD-ONLY0-NEXT:    [[TMP3101:%.*]] = load i64, ptr [[LD]], align 8
48068 // SIMD-ONLY0-NEXT:    store i64 [[TMP3101]], ptr [[LX]], align 8
48069 // SIMD-ONLY0-NEXT:    br label [[IF_END4331:%.*]]
48070 // SIMD-ONLY0:       if.else4330:
48071 // SIMD-ONLY0-NEXT:    [[TMP3102:%.*]] = load i64, ptr [[LX]], align 8
48072 // SIMD-ONLY0-NEXT:    store i64 [[TMP3102]], ptr [[LV]], align 8
48073 // SIMD-ONLY0-NEXT:    br label [[IF_END4331]]
48074 // SIMD-ONLY0:       if.end4331:
48075 // SIMD-ONLY0-NEXT:    [[TMP3103:%.*]] = load i64, ptr [[LE]], align 8
48076 // SIMD-ONLY0-NEXT:    [[TMP3104:%.*]] = load i64, ptr [[LX]], align 8
48077 // SIMD-ONLY0-NEXT:    [[CMP4332:%.*]] = icmp eq i64 [[TMP3103]], [[TMP3104]]
48078 // SIMD-ONLY0-NEXT:    [[CONV4333:%.*]] = zext i1 [[CMP4332]] to i32
48079 // SIMD-ONLY0-NEXT:    [[CONV4334:%.*]] = sext i32 [[CONV4333]] to i64
48080 // SIMD-ONLY0-NEXT:    store i64 [[CONV4334]], ptr [[LR]], align 8
48081 // SIMD-ONLY0-NEXT:    [[TMP3105:%.*]] = load i64, ptr [[LR]], align 8
48082 // SIMD-ONLY0-NEXT:    [[TOBOOL4335:%.*]] = icmp ne i64 [[TMP3105]], 0
48083 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4335]], label [[IF_THEN4336:%.*]], label [[IF_ELSE4337:%.*]]
48084 // SIMD-ONLY0:       if.then4336:
48085 // SIMD-ONLY0-NEXT:    [[TMP3106:%.*]] = load i64, ptr [[LD]], align 8
48086 // SIMD-ONLY0-NEXT:    store i64 [[TMP3106]], ptr [[LX]], align 8
48087 // SIMD-ONLY0-NEXT:    br label [[IF_END4338:%.*]]
48088 // SIMD-ONLY0:       if.else4337:
48089 // SIMD-ONLY0-NEXT:    [[TMP3107:%.*]] = load i64, ptr [[LX]], align 8
48090 // SIMD-ONLY0-NEXT:    store i64 [[TMP3107]], ptr [[LV]], align 8
48091 // SIMD-ONLY0-NEXT:    br label [[IF_END4338]]
48092 // SIMD-ONLY0:       if.end4338:
48093 // SIMD-ONLY0-NEXT:    [[TMP3108:%.*]] = load i64, ptr [[ULX]], align 8
48094 // SIMD-ONLY0-NEXT:    store i64 [[TMP3108]], ptr [[ULV]], align 8
48095 // SIMD-ONLY0-NEXT:    [[TMP3109:%.*]] = load i64, ptr [[ULE]], align 8
48096 // SIMD-ONLY0-NEXT:    [[TMP3110:%.*]] = load i64, ptr [[ULX]], align 8
48097 // SIMD-ONLY0-NEXT:    [[CMP4339:%.*]] = icmp ugt i64 [[TMP3109]], [[TMP3110]]
48098 // SIMD-ONLY0-NEXT:    br i1 [[CMP4339]], label [[IF_THEN4341:%.*]], label [[IF_END4342:%.*]]
48099 // SIMD-ONLY0:       if.then4341:
48100 // SIMD-ONLY0-NEXT:    [[TMP3111:%.*]] = load i64, ptr [[ULE]], align 8
48101 // SIMD-ONLY0-NEXT:    store i64 [[TMP3111]], ptr [[ULX]], align 8
48102 // SIMD-ONLY0-NEXT:    br label [[IF_END4342]]
48103 // SIMD-ONLY0:       if.end4342:
48104 // SIMD-ONLY0-NEXT:    [[TMP3112:%.*]] = load i64, ptr [[ULX]], align 8
48105 // SIMD-ONLY0-NEXT:    store i64 [[TMP3112]], ptr [[ULV]], align 8
48106 // SIMD-ONLY0-NEXT:    [[TMP3113:%.*]] = load i64, ptr [[ULX]], align 8
48107 // SIMD-ONLY0-NEXT:    [[TMP3114:%.*]] = load i64, ptr [[ULE]], align 8
48108 // SIMD-ONLY0-NEXT:    [[CMP4343:%.*]] = icmp ugt i64 [[TMP3113]], [[TMP3114]]
48109 // SIMD-ONLY0-NEXT:    br i1 [[CMP4343]], label [[IF_THEN4345:%.*]], label [[IF_END4346:%.*]]
48110 // SIMD-ONLY0:       if.then4345:
48111 // SIMD-ONLY0-NEXT:    [[TMP3115:%.*]] = load i64, ptr [[ULE]], align 8
48112 // SIMD-ONLY0-NEXT:    store i64 [[TMP3115]], ptr [[ULX]], align 8
48113 // SIMD-ONLY0-NEXT:    br label [[IF_END4346]]
48114 // SIMD-ONLY0:       if.end4346:
48115 // SIMD-ONLY0-NEXT:    [[TMP3116:%.*]] = load i64, ptr [[ULX]], align 8
48116 // SIMD-ONLY0-NEXT:    store i64 [[TMP3116]], ptr [[ULV]], align 8
48117 // SIMD-ONLY0-NEXT:    [[TMP3117:%.*]] = load i64, ptr [[ULE]], align 8
48118 // SIMD-ONLY0-NEXT:    [[TMP3118:%.*]] = load i64, ptr [[ULX]], align 8
48119 // SIMD-ONLY0-NEXT:    [[CMP4347:%.*]] = icmp ult i64 [[TMP3117]], [[TMP3118]]
48120 // SIMD-ONLY0-NEXT:    br i1 [[CMP4347]], label [[IF_THEN4349:%.*]], label [[IF_END4350:%.*]]
48121 // SIMD-ONLY0:       if.then4349:
48122 // SIMD-ONLY0-NEXT:    [[TMP3119:%.*]] = load i64, ptr [[ULE]], align 8
48123 // SIMD-ONLY0-NEXT:    store i64 [[TMP3119]], ptr [[ULX]], align 8
48124 // SIMD-ONLY0-NEXT:    br label [[IF_END4350]]
48125 // SIMD-ONLY0:       if.end4350:
48126 // SIMD-ONLY0-NEXT:    [[TMP3120:%.*]] = load i64, ptr [[ULX]], align 8
48127 // SIMD-ONLY0-NEXT:    store i64 [[TMP3120]], ptr [[ULV]], align 8
48128 // SIMD-ONLY0-NEXT:    [[TMP3121:%.*]] = load i64, ptr [[ULX]], align 8
48129 // SIMD-ONLY0-NEXT:    [[TMP3122:%.*]] = load i64, ptr [[ULE]], align 8
48130 // SIMD-ONLY0-NEXT:    [[CMP4351:%.*]] = icmp ult i64 [[TMP3121]], [[TMP3122]]
48131 // SIMD-ONLY0-NEXT:    br i1 [[CMP4351]], label [[IF_THEN4353:%.*]], label [[IF_END4354:%.*]]
48132 // SIMD-ONLY0:       if.then4353:
48133 // SIMD-ONLY0-NEXT:    [[TMP3123:%.*]] = load i64, ptr [[ULE]], align 8
48134 // SIMD-ONLY0-NEXT:    store i64 [[TMP3123]], ptr [[ULX]], align 8
48135 // SIMD-ONLY0-NEXT:    br label [[IF_END4354]]
48136 // SIMD-ONLY0:       if.end4354:
48137 // SIMD-ONLY0-NEXT:    [[TMP3124:%.*]] = load i64, ptr [[ULX]], align 8
48138 // SIMD-ONLY0-NEXT:    store i64 [[TMP3124]], ptr [[ULV]], align 8
48139 // SIMD-ONLY0-NEXT:    [[TMP3125:%.*]] = load i64, ptr [[ULX]], align 8
48140 // SIMD-ONLY0-NEXT:    [[TMP3126:%.*]] = load i64, ptr [[ULE]], align 8
48141 // SIMD-ONLY0-NEXT:    [[CMP4355:%.*]] = icmp eq i64 [[TMP3125]], [[TMP3126]]
48142 // SIMD-ONLY0-NEXT:    br i1 [[CMP4355]], label [[IF_THEN4357:%.*]], label [[IF_END4358:%.*]]
48143 // SIMD-ONLY0:       if.then4357:
48144 // SIMD-ONLY0-NEXT:    [[TMP3127:%.*]] = load i64, ptr [[ULD]], align 8
48145 // SIMD-ONLY0-NEXT:    store i64 [[TMP3127]], ptr [[ULX]], align 8
48146 // SIMD-ONLY0-NEXT:    br label [[IF_END4358]]
48147 // SIMD-ONLY0:       if.end4358:
48148 // SIMD-ONLY0-NEXT:    [[TMP3128:%.*]] = load i64, ptr [[ULX]], align 8
48149 // SIMD-ONLY0-NEXT:    store i64 [[TMP3128]], ptr [[ULV]], align 8
48150 // SIMD-ONLY0-NEXT:    [[TMP3129:%.*]] = load i64, ptr [[ULE]], align 8
48151 // SIMD-ONLY0-NEXT:    [[TMP3130:%.*]] = load i64, ptr [[ULX]], align 8
48152 // SIMD-ONLY0-NEXT:    [[CMP4359:%.*]] = icmp eq i64 [[TMP3129]], [[TMP3130]]
48153 // SIMD-ONLY0-NEXT:    br i1 [[CMP4359]], label [[IF_THEN4361:%.*]], label [[IF_END4362:%.*]]
48154 // SIMD-ONLY0:       if.then4361:
48155 // SIMD-ONLY0-NEXT:    [[TMP3131:%.*]] = load i64, ptr [[ULD]], align 8
48156 // SIMD-ONLY0-NEXT:    store i64 [[TMP3131]], ptr [[ULX]], align 8
48157 // SIMD-ONLY0-NEXT:    br label [[IF_END4362]]
48158 // SIMD-ONLY0:       if.end4362:
48159 // SIMD-ONLY0-NEXT:    [[TMP3132:%.*]] = load i64, ptr [[ULE]], align 8
48160 // SIMD-ONLY0-NEXT:    [[TMP3133:%.*]] = load i64, ptr [[ULX]], align 8
48161 // SIMD-ONLY0-NEXT:    [[CMP4363:%.*]] = icmp ugt i64 [[TMP3132]], [[TMP3133]]
48162 // SIMD-ONLY0-NEXT:    br i1 [[CMP4363]], label [[IF_THEN4365:%.*]], label [[IF_END4366:%.*]]
48163 // SIMD-ONLY0:       if.then4365:
48164 // SIMD-ONLY0-NEXT:    [[TMP3134:%.*]] = load i64, ptr [[ULE]], align 8
48165 // SIMD-ONLY0-NEXT:    store i64 [[TMP3134]], ptr [[ULX]], align 8
48166 // SIMD-ONLY0-NEXT:    br label [[IF_END4366]]
48167 // SIMD-ONLY0:       if.end4366:
48168 // SIMD-ONLY0-NEXT:    [[TMP3135:%.*]] = load i64, ptr [[ULX]], align 8
48169 // SIMD-ONLY0-NEXT:    store i64 [[TMP3135]], ptr [[ULV]], align 8
48170 // SIMD-ONLY0-NEXT:    [[TMP3136:%.*]] = load i64, ptr [[ULX]], align 8
48171 // SIMD-ONLY0-NEXT:    [[TMP3137:%.*]] = load i64, ptr [[ULE]], align 8
48172 // SIMD-ONLY0-NEXT:    [[CMP4367:%.*]] = icmp ugt i64 [[TMP3136]], [[TMP3137]]
48173 // SIMD-ONLY0-NEXT:    br i1 [[CMP4367]], label [[IF_THEN4369:%.*]], label [[IF_END4370:%.*]]
48174 // SIMD-ONLY0:       if.then4369:
48175 // SIMD-ONLY0-NEXT:    [[TMP3138:%.*]] = load i64, ptr [[ULE]], align 8
48176 // SIMD-ONLY0-NEXT:    store i64 [[TMP3138]], ptr [[ULX]], align 8
48177 // SIMD-ONLY0-NEXT:    br label [[IF_END4370]]
48178 // SIMD-ONLY0:       if.end4370:
48179 // SIMD-ONLY0-NEXT:    [[TMP3139:%.*]] = load i64, ptr [[ULX]], align 8
48180 // SIMD-ONLY0-NEXT:    store i64 [[TMP3139]], ptr [[ULV]], align 8
48181 // SIMD-ONLY0-NEXT:    [[TMP3140:%.*]] = load i64, ptr [[ULE]], align 8
48182 // SIMD-ONLY0-NEXT:    [[TMP3141:%.*]] = load i64, ptr [[ULX]], align 8
48183 // SIMD-ONLY0-NEXT:    [[CMP4371:%.*]] = icmp ult i64 [[TMP3140]], [[TMP3141]]
48184 // SIMD-ONLY0-NEXT:    br i1 [[CMP4371]], label [[IF_THEN4373:%.*]], label [[IF_END4374:%.*]]
48185 // SIMD-ONLY0:       if.then4373:
48186 // SIMD-ONLY0-NEXT:    [[TMP3142:%.*]] = load i64, ptr [[ULE]], align 8
48187 // SIMD-ONLY0-NEXT:    store i64 [[TMP3142]], ptr [[ULX]], align 8
48188 // SIMD-ONLY0-NEXT:    br label [[IF_END4374]]
48189 // SIMD-ONLY0:       if.end4374:
48190 // SIMD-ONLY0-NEXT:    [[TMP3143:%.*]] = load i64, ptr [[ULX]], align 8
48191 // SIMD-ONLY0-NEXT:    store i64 [[TMP3143]], ptr [[ULV]], align 8
48192 // SIMD-ONLY0-NEXT:    [[TMP3144:%.*]] = load i64, ptr [[ULX]], align 8
48193 // SIMD-ONLY0-NEXT:    [[TMP3145:%.*]] = load i64, ptr [[ULE]], align 8
48194 // SIMD-ONLY0-NEXT:    [[CMP4375:%.*]] = icmp ult i64 [[TMP3144]], [[TMP3145]]
48195 // SIMD-ONLY0-NEXT:    br i1 [[CMP4375]], label [[IF_THEN4377:%.*]], label [[IF_END4378:%.*]]
48196 // SIMD-ONLY0:       if.then4377:
48197 // SIMD-ONLY0-NEXT:    [[TMP3146:%.*]] = load i64, ptr [[ULE]], align 8
48198 // SIMD-ONLY0-NEXT:    store i64 [[TMP3146]], ptr [[ULX]], align 8
48199 // SIMD-ONLY0-NEXT:    br label [[IF_END4378]]
48200 // SIMD-ONLY0:       if.end4378:
48201 // SIMD-ONLY0-NEXT:    [[TMP3147:%.*]] = load i64, ptr [[ULX]], align 8
48202 // SIMD-ONLY0-NEXT:    store i64 [[TMP3147]], ptr [[ULV]], align 8
48203 // SIMD-ONLY0-NEXT:    [[TMP3148:%.*]] = load i64, ptr [[ULX]], align 8
48204 // SIMD-ONLY0-NEXT:    [[TMP3149:%.*]] = load i64, ptr [[ULE]], align 8
48205 // SIMD-ONLY0-NEXT:    [[CMP4379:%.*]] = icmp eq i64 [[TMP3148]], [[TMP3149]]
48206 // SIMD-ONLY0-NEXT:    br i1 [[CMP4379]], label [[IF_THEN4381:%.*]], label [[IF_END4382:%.*]]
48207 // SIMD-ONLY0:       if.then4381:
48208 // SIMD-ONLY0-NEXT:    [[TMP3150:%.*]] = load i64, ptr [[ULD]], align 8
48209 // SIMD-ONLY0-NEXT:    store i64 [[TMP3150]], ptr [[ULX]], align 8
48210 // SIMD-ONLY0-NEXT:    br label [[IF_END4382]]
48211 // SIMD-ONLY0:       if.end4382:
48212 // SIMD-ONLY0-NEXT:    [[TMP3151:%.*]] = load i64, ptr [[ULX]], align 8
48213 // SIMD-ONLY0-NEXT:    store i64 [[TMP3151]], ptr [[ULV]], align 8
48214 // SIMD-ONLY0-NEXT:    [[TMP3152:%.*]] = load i64, ptr [[ULE]], align 8
48215 // SIMD-ONLY0-NEXT:    [[TMP3153:%.*]] = load i64, ptr [[ULX]], align 8
48216 // SIMD-ONLY0-NEXT:    [[CMP4383:%.*]] = icmp eq i64 [[TMP3152]], [[TMP3153]]
48217 // SIMD-ONLY0-NEXT:    br i1 [[CMP4383]], label [[IF_THEN4385:%.*]], label [[IF_END4386:%.*]]
48218 // SIMD-ONLY0:       if.then4385:
48219 // SIMD-ONLY0-NEXT:    [[TMP3154:%.*]] = load i64, ptr [[ULD]], align 8
48220 // SIMD-ONLY0-NEXT:    store i64 [[TMP3154]], ptr [[ULX]], align 8
48221 // SIMD-ONLY0-NEXT:    br label [[IF_END4386]]
48222 // SIMD-ONLY0:       if.end4386:
48223 // SIMD-ONLY0-NEXT:    [[TMP3155:%.*]] = load i64, ptr [[ULX]], align 8
48224 // SIMD-ONLY0-NEXT:    store i64 [[TMP3155]], ptr [[ULV]], align 8
48225 // SIMD-ONLY0-NEXT:    [[TMP3156:%.*]] = load i64, ptr [[ULX]], align 8
48226 // SIMD-ONLY0-NEXT:    [[TMP3157:%.*]] = load i64, ptr [[ULE]], align 8
48227 // SIMD-ONLY0-NEXT:    [[CMP4387:%.*]] = icmp eq i64 [[TMP3156]], [[TMP3157]]
48228 // SIMD-ONLY0-NEXT:    br i1 [[CMP4387]], label [[IF_THEN4389:%.*]], label [[IF_ELSE4390:%.*]]
48229 // SIMD-ONLY0:       if.then4389:
48230 // SIMD-ONLY0-NEXT:    [[TMP3158:%.*]] = load i64, ptr [[ULD]], align 8
48231 // SIMD-ONLY0-NEXT:    store i64 [[TMP3158]], ptr [[ULX]], align 8
48232 // SIMD-ONLY0-NEXT:    br label [[IF_END4391:%.*]]
48233 // SIMD-ONLY0:       if.else4390:
48234 // SIMD-ONLY0-NEXT:    [[TMP3159:%.*]] = load i64, ptr [[ULX]], align 8
48235 // SIMD-ONLY0-NEXT:    store i64 [[TMP3159]], ptr [[ULV]], align 8
48236 // SIMD-ONLY0-NEXT:    br label [[IF_END4391]]
48237 // SIMD-ONLY0:       if.end4391:
48238 // SIMD-ONLY0-NEXT:    [[TMP3160:%.*]] = load i64, ptr [[ULE]], align 8
48239 // SIMD-ONLY0-NEXT:    [[TMP3161:%.*]] = load i64, ptr [[ULX]], align 8
48240 // SIMD-ONLY0-NEXT:    [[CMP4392:%.*]] = icmp eq i64 [[TMP3160]], [[TMP3161]]
48241 // SIMD-ONLY0-NEXT:    br i1 [[CMP4392]], label [[IF_THEN4394:%.*]], label [[IF_ELSE4395:%.*]]
48242 // SIMD-ONLY0:       if.then4394:
48243 // SIMD-ONLY0-NEXT:    [[TMP3162:%.*]] = load i64, ptr [[ULD]], align 8
48244 // SIMD-ONLY0-NEXT:    store i64 [[TMP3162]], ptr [[ULX]], align 8
48245 // SIMD-ONLY0-NEXT:    br label [[IF_END4396:%.*]]
48246 // SIMD-ONLY0:       if.else4395:
48247 // SIMD-ONLY0-NEXT:    [[TMP3163:%.*]] = load i64, ptr [[ULX]], align 8
48248 // SIMD-ONLY0-NEXT:    store i64 [[TMP3163]], ptr [[ULV]], align 8
48249 // SIMD-ONLY0-NEXT:    br label [[IF_END4396]]
48250 // SIMD-ONLY0:       if.end4396:
48251 // SIMD-ONLY0-NEXT:    [[TMP3164:%.*]] = load i64, ptr [[ULX]], align 8
48252 // SIMD-ONLY0-NEXT:    [[TMP3165:%.*]] = load i64, ptr [[ULE]], align 8
48253 // SIMD-ONLY0-NEXT:    [[CMP4397:%.*]] = icmp eq i64 [[TMP3164]], [[TMP3165]]
48254 // SIMD-ONLY0-NEXT:    [[CONV4398:%.*]] = zext i1 [[CMP4397]] to i32
48255 // SIMD-ONLY0-NEXT:    [[CONV4399:%.*]] = sext i32 [[CONV4398]] to i64
48256 // SIMD-ONLY0-NEXT:    store i64 [[CONV4399]], ptr [[ULR]], align 8
48257 // SIMD-ONLY0-NEXT:    [[TMP3166:%.*]] = load i64, ptr [[ULR]], align 8
48258 // SIMD-ONLY0-NEXT:    [[TOBOOL4400:%.*]] = icmp ne i64 [[TMP3166]], 0
48259 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4400]], label [[IF_THEN4401:%.*]], label [[IF_END4402:%.*]]
48260 // SIMD-ONLY0:       if.then4401:
48261 // SIMD-ONLY0-NEXT:    [[TMP3167:%.*]] = load i64, ptr [[ULD]], align 8
48262 // SIMD-ONLY0-NEXT:    store i64 [[TMP3167]], ptr [[ULX]], align 8
48263 // SIMD-ONLY0-NEXT:    br label [[IF_END4402]]
48264 // SIMD-ONLY0:       if.end4402:
48265 // SIMD-ONLY0-NEXT:    [[TMP3168:%.*]] = load i64, ptr [[ULE]], align 8
48266 // SIMD-ONLY0-NEXT:    [[TMP3169:%.*]] = load i64, ptr [[ULX]], align 8
48267 // SIMD-ONLY0-NEXT:    [[CMP4403:%.*]] = icmp eq i64 [[TMP3168]], [[TMP3169]]
48268 // SIMD-ONLY0-NEXT:    [[CONV4404:%.*]] = zext i1 [[CMP4403]] to i32
48269 // SIMD-ONLY0-NEXT:    [[CONV4405:%.*]] = sext i32 [[CONV4404]] to i64
48270 // SIMD-ONLY0-NEXT:    store i64 [[CONV4405]], ptr [[ULR]], align 8
48271 // SIMD-ONLY0-NEXT:    [[TMP3170:%.*]] = load i64, ptr [[ULR]], align 8
48272 // SIMD-ONLY0-NEXT:    [[TOBOOL4406:%.*]] = icmp ne i64 [[TMP3170]], 0
48273 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4406]], label [[IF_THEN4407:%.*]], label [[IF_END4408:%.*]]
48274 // SIMD-ONLY0:       if.then4407:
48275 // SIMD-ONLY0-NEXT:    [[TMP3171:%.*]] = load i64, ptr [[ULD]], align 8
48276 // SIMD-ONLY0-NEXT:    store i64 [[TMP3171]], ptr [[ULX]], align 8
48277 // SIMD-ONLY0-NEXT:    br label [[IF_END4408]]
48278 // SIMD-ONLY0:       if.end4408:
48279 // SIMD-ONLY0-NEXT:    [[TMP3172:%.*]] = load i64, ptr [[ULX]], align 8
48280 // SIMD-ONLY0-NEXT:    [[TMP3173:%.*]] = load i64, ptr [[ULE]], align 8
48281 // SIMD-ONLY0-NEXT:    [[CMP4409:%.*]] = icmp eq i64 [[TMP3172]], [[TMP3173]]
48282 // SIMD-ONLY0-NEXT:    [[CONV4410:%.*]] = zext i1 [[CMP4409]] to i32
48283 // SIMD-ONLY0-NEXT:    [[CONV4411:%.*]] = sext i32 [[CONV4410]] to i64
48284 // SIMD-ONLY0-NEXT:    store i64 [[CONV4411]], ptr [[ULR]], align 8
48285 // SIMD-ONLY0-NEXT:    [[TMP3174:%.*]] = load i64, ptr [[ULR]], align 8
48286 // SIMD-ONLY0-NEXT:    [[TOBOOL4412:%.*]] = icmp ne i64 [[TMP3174]], 0
48287 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4412]], label [[IF_THEN4413:%.*]], label [[IF_ELSE4414:%.*]]
48288 // SIMD-ONLY0:       if.then4413:
48289 // SIMD-ONLY0-NEXT:    [[TMP3175:%.*]] = load i64, ptr [[ULD]], align 8
48290 // SIMD-ONLY0-NEXT:    store i64 [[TMP3175]], ptr [[ULX]], align 8
48291 // SIMD-ONLY0-NEXT:    br label [[IF_END4415:%.*]]
48292 // SIMD-ONLY0:       if.else4414:
48293 // SIMD-ONLY0-NEXT:    [[TMP3176:%.*]] = load i64, ptr [[ULX]], align 8
48294 // SIMD-ONLY0-NEXT:    store i64 [[TMP3176]], ptr [[ULV]], align 8
48295 // SIMD-ONLY0-NEXT:    br label [[IF_END4415]]
48296 // SIMD-ONLY0:       if.end4415:
48297 // SIMD-ONLY0-NEXT:    [[TMP3177:%.*]] = load i64, ptr [[ULE]], align 8
48298 // SIMD-ONLY0-NEXT:    [[TMP3178:%.*]] = load i64, ptr [[ULX]], align 8
48299 // SIMD-ONLY0-NEXT:    [[CMP4416:%.*]] = icmp eq i64 [[TMP3177]], [[TMP3178]]
48300 // SIMD-ONLY0-NEXT:    [[CONV4417:%.*]] = zext i1 [[CMP4416]] to i32
48301 // SIMD-ONLY0-NEXT:    [[CONV4418:%.*]] = sext i32 [[CONV4417]] to i64
48302 // SIMD-ONLY0-NEXT:    store i64 [[CONV4418]], ptr [[ULR]], align 8
48303 // SIMD-ONLY0-NEXT:    [[TMP3179:%.*]] = load i64, ptr [[ULR]], align 8
48304 // SIMD-ONLY0-NEXT:    [[TOBOOL4419:%.*]] = icmp ne i64 [[TMP3179]], 0
48305 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4419]], label [[IF_THEN4420:%.*]], label [[IF_ELSE4421:%.*]]
48306 // SIMD-ONLY0:       if.then4420:
48307 // SIMD-ONLY0-NEXT:    [[TMP3180:%.*]] = load i64, ptr [[ULD]], align 8
48308 // SIMD-ONLY0-NEXT:    store i64 [[TMP3180]], ptr [[ULX]], align 8
48309 // SIMD-ONLY0-NEXT:    br label [[IF_END4422:%.*]]
48310 // SIMD-ONLY0:       if.else4421:
48311 // SIMD-ONLY0-NEXT:    [[TMP3181:%.*]] = load i64, ptr [[ULX]], align 8
48312 // SIMD-ONLY0-NEXT:    store i64 [[TMP3181]], ptr [[ULV]], align 8
48313 // SIMD-ONLY0-NEXT:    br label [[IF_END4422]]
48314 // SIMD-ONLY0:       if.end4422:
48315 // SIMD-ONLY0-NEXT:    [[TMP3182:%.*]] = load i64, ptr [[ULX]], align 8
48316 // SIMD-ONLY0-NEXT:    store i64 [[TMP3182]], ptr [[ULV]], align 8
48317 // SIMD-ONLY0-NEXT:    [[TMP3183:%.*]] = load i64, ptr [[ULE]], align 8
48318 // SIMD-ONLY0-NEXT:    [[TMP3184:%.*]] = load i64, ptr [[ULX]], align 8
48319 // SIMD-ONLY0-NEXT:    [[CMP4423:%.*]] = icmp ugt i64 [[TMP3183]], [[TMP3184]]
48320 // SIMD-ONLY0-NEXT:    br i1 [[CMP4423]], label [[IF_THEN4425:%.*]], label [[IF_END4426:%.*]]
48321 // SIMD-ONLY0:       if.then4425:
48322 // SIMD-ONLY0-NEXT:    [[TMP3185:%.*]] = load i64, ptr [[ULE]], align 8
48323 // SIMD-ONLY0-NEXT:    store i64 [[TMP3185]], ptr [[ULX]], align 8
48324 // SIMD-ONLY0-NEXT:    br label [[IF_END4426]]
48325 // SIMD-ONLY0:       if.end4426:
48326 // SIMD-ONLY0-NEXT:    [[TMP3186:%.*]] = load i64, ptr [[ULX]], align 8
48327 // SIMD-ONLY0-NEXT:    store i64 [[TMP3186]], ptr [[ULV]], align 8
48328 // SIMD-ONLY0-NEXT:    [[TMP3187:%.*]] = load i64, ptr [[ULX]], align 8
48329 // SIMD-ONLY0-NEXT:    [[TMP3188:%.*]] = load i64, ptr [[ULE]], align 8
48330 // SIMD-ONLY0-NEXT:    [[CMP4427:%.*]] = icmp ugt i64 [[TMP3187]], [[TMP3188]]
48331 // SIMD-ONLY0-NEXT:    br i1 [[CMP4427]], label [[IF_THEN4429:%.*]], label [[IF_END4430:%.*]]
48332 // SIMD-ONLY0:       if.then4429:
48333 // SIMD-ONLY0-NEXT:    [[TMP3189:%.*]] = load i64, ptr [[ULE]], align 8
48334 // SIMD-ONLY0-NEXT:    store i64 [[TMP3189]], ptr [[ULX]], align 8
48335 // SIMD-ONLY0-NEXT:    br label [[IF_END4430]]
48336 // SIMD-ONLY0:       if.end4430:
48337 // SIMD-ONLY0-NEXT:    [[TMP3190:%.*]] = load i64, ptr [[ULX]], align 8
48338 // SIMD-ONLY0-NEXT:    store i64 [[TMP3190]], ptr [[ULV]], align 8
48339 // SIMD-ONLY0-NEXT:    [[TMP3191:%.*]] = load i64, ptr [[ULE]], align 8
48340 // SIMD-ONLY0-NEXT:    [[TMP3192:%.*]] = load i64, ptr [[ULX]], align 8
48341 // SIMD-ONLY0-NEXT:    [[CMP4431:%.*]] = icmp ult i64 [[TMP3191]], [[TMP3192]]
48342 // SIMD-ONLY0-NEXT:    br i1 [[CMP4431]], label [[IF_THEN4433:%.*]], label [[IF_END4434:%.*]]
48343 // SIMD-ONLY0:       if.then4433:
48344 // SIMD-ONLY0-NEXT:    [[TMP3193:%.*]] = load i64, ptr [[ULE]], align 8
48345 // SIMD-ONLY0-NEXT:    store i64 [[TMP3193]], ptr [[ULX]], align 8
48346 // SIMD-ONLY0-NEXT:    br label [[IF_END4434]]
48347 // SIMD-ONLY0:       if.end4434:
48348 // SIMD-ONLY0-NEXT:    [[TMP3194:%.*]] = load i64, ptr [[ULX]], align 8
48349 // SIMD-ONLY0-NEXT:    store i64 [[TMP3194]], ptr [[ULV]], align 8
48350 // SIMD-ONLY0-NEXT:    [[TMP3195:%.*]] = load i64, ptr [[ULX]], align 8
48351 // SIMD-ONLY0-NEXT:    [[TMP3196:%.*]] = load i64, ptr [[ULE]], align 8
48352 // SIMD-ONLY0-NEXT:    [[CMP4435:%.*]] = icmp ult i64 [[TMP3195]], [[TMP3196]]
48353 // SIMD-ONLY0-NEXT:    br i1 [[CMP4435]], label [[IF_THEN4437:%.*]], label [[IF_END4438:%.*]]
48354 // SIMD-ONLY0:       if.then4437:
48355 // SIMD-ONLY0-NEXT:    [[TMP3197:%.*]] = load i64, ptr [[ULE]], align 8
48356 // SIMD-ONLY0-NEXT:    store i64 [[TMP3197]], ptr [[ULX]], align 8
48357 // SIMD-ONLY0-NEXT:    br label [[IF_END4438]]
48358 // SIMD-ONLY0:       if.end4438:
48359 // SIMD-ONLY0-NEXT:    [[TMP3198:%.*]] = load i64, ptr [[ULX]], align 8
48360 // SIMD-ONLY0-NEXT:    store i64 [[TMP3198]], ptr [[ULV]], align 8
48361 // SIMD-ONLY0-NEXT:    [[TMP3199:%.*]] = load i64, ptr [[ULX]], align 8
48362 // SIMD-ONLY0-NEXT:    [[TMP3200:%.*]] = load i64, ptr [[ULE]], align 8
48363 // SIMD-ONLY0-NEXT:    [[CMP4439:%.*]] = icmp eq i64 [[TMP3199]], [[TMP3200]]
48364 // SIMD-ONLY0-NEXT:    br i1 [[CMP4439]], label [[IF_THEN4441:%.*]], label [[IF_END4442:%.*]]
48365 // SIMD-ONLY0:       if.then4441:
48366 // SIMD-ONLY0-NEXT:    [[TMP3201:%.*]] = load i64, ptr [[ULD]], align 8
48367 // SIMD-ONLY0-NEXT:    store i64 [[TMP3201]], ptr [[ULX]], align 8
48368 // SIMD-ONLY0-NEXT:    br label [[IF_END4442]]
48369 // SIMD-ONLY0:       if.end4442:
48370 // SIMD-ONLY0-NEXT:    [[TMP3202:%.*]] = load i64, ptr [[ULX]], align 8
48371 // SIMD-ONLY0-NEXT:    store i64 [[TMP3202]], ptr [[ULV]], align 8
48372 // SIMD-ONLY0-NEXT:    [[TMP3203:%.*]] = load i64, ptr [[ULE]], align 8
48373 // SIMD-ONLY0-NEXT:    [[TMP3204:%.*]] = load i64, ptr [[ULX]], align 8
48374 // SIMD-ONLY0-NEXT:    [[CMP4443:%.*]] = icmp eq i64 [[TMP3203]], [[TMP3204]]
48375 // SIMD-ONLY0-NEXT:    br i1 [[CMP4443]], label [[IF_THEN4445:%.*]], label [[IF_END4446:%.*]]
48376 // SIMD-ONLY0:       if.then4445:
48377 // SIMD-ONLY0-NEXT:    [[TMP3205:%.*]] = load i64, ptr [[ULD]], align 8
48378 // SIMD-ONLY0-NEXT:    store i64 [[TMP3205]], ptr [[ULX]], align 8
48379 // SIMD-ONLY0-NEXT:    br label [[IF_END4446]]
48380 // SIMD-ONLY0:       if.end4446:
48381 // SIMD-ONLY0-NEXT:    [[TMP3206:%.*]] = load i64, ptr [[ULE]], align 8
48382 // SIMD-ONLY0-NEXT:    [[TMP3207:%.*]] = load i64, ptr [[ULX]], align 8
48383 // SIMD-ONLY0-NEXT:    [[CMP4447:%.*]] = icmp ugt i64 [[TMP3206]], [[TMP3207]]
48384 // SIMD-ONLY0-NEXT:    br i1 [[CMP4447]], label [[IF_THEN4449:%.*]], label [[IF_END4450:%.*]]
48385 // SIMD-ONLY0:       if.then4449:
48386 // SIMD-ONLY0-NEXT:    [[TMP3208:%.*]] = load i64, ptr [[ULE]], align 8
48387 // SIMD-ONLY0-NEXT:    store i64 [[TMP3208]], ptr [[ULX]], align 8
48388 // SIMD-ONLY0-NEXT:    br label [[IF_END4450]]
48389 // SIMD-ONLY0:       if.end4450:
48390 // SIMD-ONLY0-NEXT:    [[TMP3209:%.*]] = load i64, ptr [[ULX]], align 8
48391 // SIMD-ONLY0-NEXT:    store i64 [[TMP3209]], ptr [[ULV]], align 8
48392 // SIMD-ONLY0-NEXT:    [[TMP3210:%.*]] = load i64, ptr [[ULX]], align 8
48393 // SIMD-ONLY0-NEXT:    [[TMP3211:%.*]] = load i64, ptr [[ULE]], align 8
48394 // SIMD-ONLY0-NEXT:    [[CMP4451:%.*]] = icmp ugt i64 [[TMP3210]], [[TMP3211]]
48395 // SIMD-ONLY0-NEXT:    br i1 [[CMP4451]], label [[IF_THEN4453:%.*]], label [[IF_END4454:%.*]]
48396 // SIMD-ONLY0:       if.then4453:
48397 // SIMD-ONLY0-NEXT:    [[TMP3212:%.*]] = load i64, ptr [[ULE]], align 8
48398 // SIMD-ONLY0-NEXT:    store i64 [[TMP3212]], ptr [[ULX]], align 8
48399 // SIMD-ONLY0-NEXT:    br label [[IF_END4454]]
48400 // SIMD-ONLY0:       if.end4454:
48401 // SIMD-ONLY0-NEXT:    [[TMP3213:%.*]] = load i64, ptr [[ULX]], align 8
48402 // SIMD-ONLY0-NEXT:    store i64 [[TMP3213]], ptr [[ULV]], align 8
48403 // SIMD-ONLY0-NEXT:    [[TMP3214:%.*]] = load i64, ptr [[ULE]], align 8
48404 // SIMD-ONLY0-NEXT:    [[TMP3215:%.*]] = load i64, ptr [[ULX]], align 8
48405 // SIMD-ONLY0-NEXT:    [[CMP4455:%.*]] = icmp ult i64 [[TMP3214]], [[TMP3215]]
48406 // SIMD-ONLY0-NEXT:    br i1 [[CMP4455]], label [[IF_THEN4457:%.*]], label [[IF_END4458:%.*]]
48407 // SIMD-ONLY0:       if.then4457:
48408 // SIMD-ONLY0-NEXT:    [[TMP3216:%.*]] = load i64, ptr [[ULE]], align 8
48409 // SIMD-ONLY0-NEXT:    store i64 [[TMP3216]], ptr [[ULX]], align 8
48410 // SIMD-ONLY0-NEXT:    br label [[IF_END4458]]
48411 // SIMD-ONLY0:       if.end4458:
48412 // SIMD-ONLY0-NEXT:    [[TMP3217:%.*]] = load i64, ptr [[ULX]], align 8
48413 // SIMD-ONLY0-NEXT:    store i64 [[TMP3217]], ptr [[ULV]], align 8
48414 // SIMD-ONLY0-NEXT:    [[TMP3218:%.*]] = load i64, ptr [[ULX]], align 8
48415 // SIMD-ONLY0-NEXT:    [[TMP3219:%.*]] = load i64, ptr [[ULE]], align 8
48416 // SIMD-ONLY0-NEXT:    [[CMP4459:%.*]] = icmp ult i64 [[TMP3218]], [[TMP3219]]
48417 // SIMD-ONLY0-NEXT:    br i1 [[CMP4459]], label [[IF_THEN4461:%.*]], label [[IF_END4462:%.*]]
48418 // SIMD-ONLY0:       if.then4461:
48419 // SIMD-ONLY0-NEXT:    [[TMP3220:%.*]] = load i64, ptr [[ULE]], align 8
48420 // SIMD-ONLY0-NEXT:    store i64 [[TMP3220]], ptr [[ULX]], align 8
48421 // SIMD-ONLY0-NEXT:    br label [[IF_END4462]]
48422 // SIMD-ONLY0:       if.end4462:
48423 // SIMD-ONLY0-NEXT:    [[TMP3221:%.*]] = load i64, ptr [[ULX]], align 8
48424 // SIMD-ONLY0-NEXT:    store i64 [[TMP3221]], ptr [[ULV]], align 8
48425 // SIMD-ONLY0-NEXT:    [[TMP3222:%.*]] = load i64, ptr [[ULX]], align 8
48426 // SIMD-ONLY0-NEXT:    [[TMP3223:%.*]] = load i64, ptr [[ULE]], align 8
48427 // SIMD-ONLY0-NEXT:    [[CMP4463:%.*]] = icmp eq i64 [[TMP3222]], [[TMP3223]]
48428 // SIMD-ONLY0-NEXT:    br i1 [[CMP4463]], label [[IF_THEN4465:%.*]], label [[IF_END4466:%.*]]
48429 // SIMD-ONLY0:       if.then4465:
48430 // SIMD-ONLY0-NEXT:    [[TMP3224:%.*]] = load i64, ptr [[ULD]], align 8
48431 // SIMD-ONLY0-NEXT:    store i64 [[TMP3224]], ptr [[ULX]], align 8
48432 // SIMD-ONLY0-NEXT:    br label [[IF_END4466]]
48433 // SIMD-ONLY0:       if.end4466:
48434 // SIMD-ONLY0-NEXT:    [[TMP3225:%.*]] = load i64, ptr [[ULX]], align 8
48435 // SIMD-ONLY0-NEXT:    store i64 [[TMP3225]], ptr [[ULV]], align 8
48436 // SIMD-ONLY0-NEXT:    [[TMP3226:%.*]] = load i64, ptr [[ULE]], align 8
48437 // SIMD-ONLY0-NEXT:    [[TMP3227:%.*]] = load i64, ptr [[ULX]], align 8
48438 // SIMD-ONLY0-NEXT:    [[CMP4467:%.*]] = icmp eq i64 [[TMP3226]], [[TMP3227]]
48439 // SIMD-ONLY0-NEXT:    br i1 [[CMP4467]], label [[IF_THEN4469:%.*]], label [[IF_END4470:%.*]]
48440 // SIMD-ONLY0:       if.then4469:
48441 // SIMD-ONLY0-NEXT:    [[TMP3228:%.*]] = load i64, ptr [[ULD]], align 8
48442 // SIMD-ONLY0-NEXT:    store i64 [[TMP3228]], ptr [[ULX]], align 8
48443 // SIMD-ONLY0-NEXT:    br label [[IF_END4470]]
48444 // SIMD-ONLY0:       if.end4470:
48445 // SIMD-ONLY0-NEXT:    [[TMP3229:%.*]] = load i64, ptr [[ULX]], align 8
48446 // SIMD-ONLY0-NEXT:    store i64 [[TMP3229]], ptr [[ULV]], align 8
48447 // SIMD-ONLY0-NEXT:    [[TMP3230:%.*]] = load i64, ptr [[ULX]], align 8
48448 // SIMD-ONLY0-NEXT:    [[TMP3231:%.*]] = load i64, ptr [[ULE]], align 8
48449 // SIMD-ONLY0-NEXT:    [[CMP4471:%.*]] = icmp eq i64 [[TMP3230]], [[TMP3231]]
48450 // SIMD-ONLY0-NEXT:    br i1 [[CMP4471]], label [[IF_THEN4473:%.*]], label [[IF_ELSE4474:%.*]]
48451 // SIMD-ONLY0:       if.then4473:
48452 // SIMD-ONLY0-NEXT:    [[TMP3232:%.*]] = load i64, ptr [[ULD]], align 8
48453 // SIMD-ONLY0-NEXT:    store i64 [[TMP3232]], ptr [[ULX]], align 8
48454 // SIMD-ONLY0-NEXT:    br label [[IF_END4475:%.*]]
48455 // SIMD-ONLY0:       if.else4474:
48456 // SIMD-ONLY0-NEXT:    [[TMP3233:%.*]] = load i64, ptr [[ULX]], align 8
48457 // SIMD-ONLY0-NEXT:    store i64 [[TMP3233]], ptr [[ULV]], align 8
48458 // SIMD-ONLY0-NEXT:    br label [[IF_END4475]]
48459 // SIMD-ONLY0:       if.end4475:
48460 // SIMD-ONLY0-NEXT:    [[TMP3234:%.*]] = load i64, ptr [[ULE]], align 8
48461 // SIMD-ONLY0-NEXT:    [[TMP3235:%.*]] = load i64, ptr [[ULX]], align 8
48462 // SIMD-ONLY0-NEXT:    [[CMP4476:%.*]] = icmp eq i64 [[TMP3234]], [[TMP3235]]
48463 // SIMD-ONLY0-NEXT:    br i1 [[CMP4476]], label [[IF_THEN4478:%.*]], label [[IF_ELSE4479:%.*]]
48464 // SIMD-ONLY0:       if.then4478:
48465 // SIMD-ONLY0-NEXT:    [[TMP3236:%.*]] = load i64, ptr [[ULD]], align 8
48466 // SIMD-ONLY0-NEXT:    store i64 [[TMP3236]], ptr [[ULX]], align 8
48467 // SIMD-ONLY0-NEXT:    br label [[IF_END4480:%.*]]
48468 // SIMD-ONLY0:       if.else4479:
48469 // SIMD-ONLY0-NEXT:    [[TMP3237:%.*]] = load i64, ptr [[ULX]], align 8
48470 // SIMD-ONLY0-NEXT:    store i64 [[TMP3237]], ptr [[ULV]], align 8
48471 // SIMD-ONLY0-NEXT:    br label [[IF_END4480]]
48472 // SIMD-ONLY0:       if.end4480:
48473 // SIMD-ONLY0-NEXT:    [[TMP3238:%.*]] = load i64, ptr [[ULX]], align 8
48474 // SIMD-ONLY0-NEXT:    [[TMP3239:%.*]] = load i64, ptr [[ULE]], align 8
48475 // SIMD-ONLY0-NEXT:    [[CMP4481:%.*]] = icmp eq i64 [[TMP3238]], [[TMP3239]]
48476 // SIMD-ONLY0-NEXT:    [[CONV4482:%.*]] = zext i1 [[CMP4481]] to i32
48477 // SIMD-ONLY0-NEXT:    [[CONV4483:%.*]] = sext i32 [[CONV4482]] to i64
48478 // SIMD-ONLY0-NEXT:    store i64 [[CONV4483]], ptr [[ULR]], align 8
48479 // SIMD-ONLY0-NEXT:    [[TMP3240:%.*]] = load i64, ptr [[ULR]], align 8
48480 // SIMD-ONLY0-NEXT:    [[TOBOOL4484:%.*]] = icmp ne i64 [[TMP3240]], 0
48481 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4484]], label [[IF_THEN4485:%.*]], label [[IF_END4486:%.*]]
48482 // SIMD-ONLY0:       if.then4485:
48483 // SIMD-ONLY0-NEXT:    [[TMP3241:%.*]] = load i64, ptr [[ULD]], align 8
48484 // SIMD-ONLY0-NEXT:    store i64 [[TMP3241]], ptr [[ULX]], align 8
48485 // SIMD-ONLY0-NEXT:    br label [[IF_END4486]]
48486 // SIMD-ONLY0:       if.end4486:
48487 // SIMD-ONLY0-NEXT:    [[TMP3242:%.*]] = load i64, ptr [[ULE]], align 8
48488 // SIMD-ONLY0-NEXT:    [[TMP3243:%.*]] = load i64, ptr [[ULX]], align 8
48489 // SIMD-ONLY0-NEXT:    [[CMP4487:%.*]] = icmp eq i64 [[TMP3242]], [[TMP3243]]
48490 // SIMD-ONLY0-NEXT:    [[CONV4488:%.*]] = zext i1 [[CMP4487]] to i32
48491 // SIMD-ONLY0-NEXT:    [[CONV4489:%.*]] = sext i32 [[CONV4488]] to i64
48492 // SIMD-ONLY0-NEXT:    store i64 [[CONV4489]], ptr [[ULR]], align 8
48493 // SIMD-ONLY0-NEXT:    [[TMP3244:%.*]] = load i64, ptr [[ULR]], align 8
48494 // SIMD-ONLY0-NEXT:    [[TOBOOL4490:%.*]] = icmp ne i64 [[TMP3244]], 0
48495 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4490]], label [[IF_THEN4491:%.*]], label [[IF_END4492:%.*]]
48496 // SIMD-ONLY0:       if.then4491:
48497 // SIMD-ONLY0-NEXT:    [[TMP3245:%.*]] = load i64, ptr [[ULD]], align 8
48498 // SIMD-ONLY0-NEXT:    store i64 [[TMP3245]], ptr [[ULX]], align 8
48499 // SIMD-ONLY0-NEXT:    br label [[IF_END4492]]
48500 // SIMD-ONLY0:       if.end4492:
48501 // SIMD-ONLY0-NEXT:    [[TMP3246:%.*]] = load i64, ptr [[ULX]], align 8
48502 // SIMD-ONLY0-NEXT:    [[TMP3247:%.*]] = load i64, ptr [[ULE]], align 8
48503 // SIMD-ONLY0-NEXT:    [[CMP4493:%.*]] = icmp eq i64 [[TMP3246]], [[TMP3247]]
48504 // SIMD-ONLY0-NEXT:    [[CONV4494:%.*]] = zext i1 [[CMP4493]] to i32
48505 // SIMD-ONLY0-NEXT:    [[CONV4495:%.*]] = sext i32 [[CONV4494]] to i64
48506 // SIMD-ONLY0-NEXT:    store i64 [[CONV4495]], ptr [[ULR]], align 8
48507 // SIMD-ONLY0-NEXT:    [[TMP3248:%.*]] = load i64, ptr [[ULR]], align 8
48508 // SIMD-ONLY0-NEXT:    [[TOBOOL4496:%.*]] = icmp ne i64 [[TMP3248]], 0
48509 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4496]], label [[IF_THEN4497:%.*]], label [[IF_ELSE4498:%.*]]
48510 // SIMD-ONLY0:       if.then4497:
48511 // SIMD-ONLY0-NEXT:    [[TMP3249:%.*]] = load i64, ptr [[ULD]], align 8
48512 // SIMD-ONLY0-NEXT:    store i64 [[TMP3249]], ptr [[ULX]], align 8
48513 // SIMD-ONLY0-NEXT:    br label [[IF_END4499:%.*]]
48514 // SIMD-ONLY0:       if.else4498:
48515 // SIMD-ONLY0-NEXT:    [[TMP3250:%.*]] = load i64, ptr [[ULX]], align 8
48516 // SIMD-ONLY0-NEXT:    store i64 [[TMP3250]], ptr [[ULV]], align 8
48517 // SIMD-ONLY0-NEXT:    br label [[IF_END4499]]
48518 // SIMD-ONLY0:       if.end4499:
48519 // SIMD-ONLY0-NEXT:    [[TMP3251:%.*]] = load i64, ptr [[ULE]], align 8
48520 // SIMD-ONLY0-NEXT:    [[TMP3252:%.*]] = load i64, ptr [[ULX]], align 8
48521 // SIMD-ONLY0-NEXT:    [[CMP4500:%.*]] = icmp eq i64 [[TMP3251]], [[TMP3252]]
48522 // SIMD-ONLY0-NEXT:    [[CONV4501:%.*]] = zext i1 [[CMP4500]] to i32
48523 // SIMD-ONLY0-NEXT:    [[CONV4502:%.*]] = sext i32 [[CONV4501]] to i64
48524 // SIMD-ONLY0-NEXT:    store i64 [[CONV4502]], ptr [[ULR]], align 8
48525 // SIMD-ONLY0-NEXT:    [[TMP3253:%.*]] = load i64, ptr [[ULR]], align 8
48526 // SIMD-ONLY0-NEXT:    [[TOBOOL4503:%.*]] = icmp ne i64 [[TMP3253]], 0
48527 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4503]], label [[IF_THEN4504:%.*]], label [[IF_ELSE4505:%.*]]
48528 // SIMD-ONLY0:       if.then4504:
48529 // SIMD-ONLY0-NEXT:    [[TMP3254:%.*]] = load i64, ptr [[ULD]], align 8
48530 // SIMD-ONLY0-NEXT:    store i64 [[TMP3254]], ptr [[ULX]], align 8
48531 // SIMD-ONLY0-NEXT:    br label [[IF_END4506:%.*]]
48532 // SIMD-ONLY0:       if.else4505:
48533 // SIMD-ONLY0-NEXT:    [[TMP3255:%.*]] = load i64, ptr [[ULX]], align 8
48534 // SIMD-ONLY0-NEXT:    store i64 [[TMP3255]], ptr [[ULV]], align 8
48535 // SIMD-ONLY0-NEXT:    br label [[IF_END4506]]
48536 // SIMD-ONLY0:       if.end4506:
48537 // SIMD-ONLY0-NEXT:    [[TMP3256:%.*]] = load i64, ptr [[ULX]], align 8
48538 // SIMD-ONLY0-NEXT:    store i64 [[TMP3256]], ptr [[ULV]], align 8
48539 // SIMD-ONLY0-NEXT:    [[TMP3257:%.*]] = load i64, ptr [[ULE]], align 8
48540 // SIMD-ONLY0-NEXT:    [[TMP3258:%.*]] = load i64, ptr [[ULX]], align 8
48541 // SIMD-ONLY0-NEXT:    [[CMP4507:%.*]] = icmp ugt i64 [[TMP3257]], [[TMP3258]]
48542 // SIMD-ONLY0-NEXT:    br i1 [[CMP4507]], label [[IF_THEN4509:%.*]], label [[IF_END4510:%.*]]
48543 // SIMD-ONLY0:       if.then4509:
48544 // SIMD-ONLY0-NEXT:    [[TMP3259:%.*]] = load i64, ptr [[ULE]], align 8
48545 // SIMD-ONLY0-NEXT:    store i64 [[TMP3259]], ptr [[ULX]], align 8
48546 // SIMD-ONLY0-NEXT:    br label [[IF_END4510]]
48547 // SIMD-ONLY0:       if.end4510:
48548 // SIMD-ONLY0-NEXT:    [[TMP3260:%.*]] = load i64, ptr [[ULX]], align 8
48549 // SIMD-ONLY0-NEXT:    store i64 [[TMP3260]], ptr [[ULV]], align 8
48550 // SIMD-ONLY0-NEXT:    [[TMP3261:%.*]] = load i64, ptr [[ULX]], align 8
48551 // SIMD-ONLY0-NEXT:    [[TMP3262:%.*]] = load i64, ptr [[ULE]], align 8
48552 // SIMD-ONLY0-NEXT:    [[CMP4511:%.*]] = icmp ugt i64 [[TMP3261]], [[TMP3262]]
48553 // SIMD-ONLY0-NEXT:    br i1 [[CMP4511]], label [[IF_THEN4513:%.*]], label [[IF_END4514:%.*]]
48554 // SIMD-ONLY0:       if.then4513:
48555 // SIMD-ONLY0-NEXT:    [[TMP3263:%.*]] = load i64, ptr [[ULE]], align 8
48556 // SIMD-ONLY0-NEXT:    store i64 [[TMP3263]], ptr [[ULX]], align 8
48557 // SIMD-ONLY0-NEXT:    br label [[IF_END4514]]
48558 // SIMD-ONLY0:       if.end4514:
48559 // SIMD-ONLY0-NEXT:    [[TMP3264:%.*]] = load i64, ptr [[ULX]], align 8
48560 // SIMD-ONLY0-NEXT:    store i64 [[TMP3264]], ptr [[ULV]], align 8
48561 // SIMD-ONLY0-NEXT:    [[TMP3265:%.*]] = load i64, ptr [[ULE]], align 8
48562 // SIMD-ONLY0-NEXT:    [[TMP3266:%.*]] = load i64, ptr [[ULX]], align 8
48563 // SIMD-ONLY0-NEXT:    [[CMP4515:%.*]] = icmp ult i64 [[TMP3265]], [[TMP3266]]
48564 // SIMD-ONLY0-NEXT:    br i1 [[CMP4515]], label [[IF_THEN4517:%.*]], label [[IF_END4518:%.*]]
48565 // SIMD-ONLY0:       if.then4517:
48566 // SIMD-ONLY0-NEXT:    [[TMP3267:%.*]] = load i64, ptr [[ULE]], align 8
48567 // SIMD-ONLY0-NEXT:    store i64 [[TMP3267]], ptr [[ULX]], align 8
48568 // SIMD-ONLY0-NEXT:    br label [[IF_END4518]]
48569 // SIMD-ONLY0:       if.end4518:
48570 // SIMD-ONLY0-NEXT:    [[TMP3268:%.*]] = load i64, ptr [[ULX]], align 8
48571 // SIMD-ONLY0-NEXT:    store i64 [[TMP3268]], ptr [[ULV]], align 8
48572 // SIMD-ONLY0-NEXT:    [[TMP3269:%.*]] = load i64, ptr [[ULX]], align 8
48573 // SIMD-ONLY0-NEXT:    [[TMP3270:%.*]] = load i64, ptr [[ULE]], align 8
48574 // SIMD-ONLY0-NEXT:    [[CMP4519:%.*]] = icmp ult i64 [[TMP3269]], [[TMP3270]]
48575 // SIMD-ONLY0-NEXT:    br i1 [[CMP4519]], label [[IF_THEN4521:%.*]], label [[IF_END4522:%.*]]
48576 // SIMD-ONLY0:       if.then4521:
48577 // SIMD-ONLY0-NEXT:    [[TMP3271:%.*]] = load i64, ptr [[ULE]], align 8
48578 // SIMD-ONLY0-NEXT:    store i64 [[TMP3271]], ptr [[ULX]], align 8
48579 // SIMD-ONLY0-NEXT:    br label [[IF_END4522]]
48580 // SIMD-ONLY0:       if.end4522:
48581 // SIMD-ONLY0-NEXT:    [[TMP3272:%.*]] = load i64, ptr [[ULX]], align 8
48582 // SIMD-ONLY0-NEXT:    store i64 [[TMP3272]], ptr [[ULV]], align 8
48583 // SIMD-ONLY0-NEXT:    [[TMP3273:%.*]] = load i64, ptr [[ULX]], align 8
48584 // SIMD-ONLY0-NEXT:    [[TMP3274:%.*]] = load i64, ptr [[ULE]], align 8
48585 // SIMD-ONLY0-NEXT:    [[CMP4523:%.*]] = icmp eq i64 [[TMP3273]], [[TMP3274]]
48586 // SIMD-ONLY0-NEXT:    br i1 [[CMP4523]], label [[IF_THEN4525:%.*]], label [[IF_END4526:%.*]]
48587 // SIMD-ONLY0:       if.then4525:
48588 // SIMD-ONLY0-NEXT:    [[TMP3275:%.*]] = load i64, ptr [[ULD]], align 8
48589 // SIMD-ONLY0-NEXT:    store i64 [[TMP3275]], ptr [[ULX]], align 8
48590 // SIMD-ONLY0-NEXT:    br label [[IF_END4526]]
48591 // SIMD-ONLY0:       if.end4526:
48592 // SIMD-ONLY0-NEXT:    [[TMP3276:%.*]] = load i64, ptr [[ULX]], align 8
48593 // SIMD-ONLY0-NEXT:    store i64 [[TMP3276]], ptr [[ULV]], align 8
48594 // SIMD-ONLY0-NEXT:    [[TMP3277:%.*]] = load i64, ptr [[ULE]], align 8
48595 // SIMD-ONLY0-NEXT:    [[TMP3278:%.*]] = load i64, ptr [[ULX]], align 8
48596 // SIMD-ONLY0-NEXT:    [[CMP4527:%.*]] = icmp eq i64 [[TMP3277]], [[TMP3278]]
48597 // SIMD-ONLY0-NEXT:    br i1 [[CMP4527]], label [[IF_THEN4529:%.*]], label [[IF_END4530:%.*]]
48598 // SIMD-ONLY0:       if.then4529:
48599 // SIMD-ONLY0-NEXT:    [[TMP3279:%.*]] = load i64, ptr [[ULD]], align 8
48600 // SIMD-ONLY0-NEXT:    store i64 [[TMP3279]], ptr [[ULX]], align 8
48601 // SIMD-ONLY0-NEXT:    br label [[IF_END4530]]
48602 // SIMD-ONLY0:       if.end4530:
48603 // SIMD-ONLY0-NEXT:    [[TMP3280:%.*]] = load i64, ptr [[ULE]], align 8
48604 // SIMD-ONLY0-NEXT:    [[TMP3281:%.*]] = load i64, ptr [[ULX]], align 8
48605 // SIMD-ONLY0-NEXT:    [[CMP4531:%.*]] = icmp ugt i64 [[TMP3280]], [[TMP3281]]
48606 // SIMD-ONLY0-NEXT:    br i1 [[CMP4531]], label [[IF_THEN4533:%.*]], label [[IF_END4534:%.*]]
48607 // SIMD-ONLY0:       if.then4533:
48608 // SIMD-ONLY0-NEXT:    [[TMP3282:%.*]] = load i64, ptr [[ULE]], align 8
48609 // SIMD-ONLY0-NEXT:    store i64 [[TMP3282]], ptr [[ULX]], align 8
48610 // SIMD-ONLY0-NEXT:    br label [[IF_END4534]]
48611 // SIMD-ONLY0:       if.end4534:
48612 // SIMD-ONLY0-NEXT:    [[TMP3283:%.*]] = load i64, ptr [[ULX]], align 8
48613 // SIMD-ONLY0-NEXT:    store i64 [[TMP3283]], ptr [[ULV]], align 8
48614 // SIMD-ONLY0-NEXT:    [[TMP3284:%.*]] = load i64, ptr [[ULX]], align 8
48615 // SIMD-ONLY0-NEXT:    [[TMP3285:%.*]] = load i64, ptr [[ULE]], align 8
48616 // SIMD-ONLY0-NEXT:    [[CMP4535:%.*]] = icmp ugt i64 [[TMP3284]], [[TMP3285]]
48617 // SIMD-ONLY0-NEXT:    br i1 [[CMP4535]], label [[IF_THEN4537:%.*]], label [[IF_END4538:%.*]]
48618 // SIMD-ONLY0:       if.then4537:
48619 // SIMD-ONLY0-NEXT:    [[TMP3286:%.*]] = load i64, ptr [[ULE]], align 8
48620 // SIMD-ONLY0-NEXT:    store i64 [[TMP3286]], ptr [[ULX]], align 8
48621 // SIMD-ONLY0-NEXT:    br label [[IF_END4538]]
48622 // SIMD-ONLY0:       if.end4538:
48623 // SIMD-ONLY0-NEXT:    [[TMP3287:%.*]] = load i64, ptr [[ULX]], align 8
48624 // SIMD-ONLY0-NEXT:    store i64 [[TMP3287]], ptr [[ULV]], align 8
48625 // SIMD-ONLY0-NEXT:    [[TMP3288:%.*]] = load i64, ptr [[ULE]], align 8
48626 // SIMD-ONLY0-NEXT:    [[TMP3289:%.*]] = load i64, ptr [[ULX]], align 8
48627 // SIMD-ONLY0-NEXT:    [[CMP4539:%.*]] = icmp ult i64 [[TMP3288]], [[TMP3289]]
48628 // SIMD-ONLY0-NEXT:    br i1 [[CMP4539]], label [[IF_THEN4541:%.*]], label [[IF_END4542:%.*]]
48629 // SIMD-ONLY0:       if.then4541:
48630 // SIMD-ONLY0-NEXT:    [[TMP3290:%.*]] = load i64, ptr [[ULE]], align 8
48631 // SIMD-ONLY0-NEXT:    store i64 [[TMP3290]], ptr [[ULX]], align 8
48632 // SIMD-ONLY0-NEXT:    br label [[IF_END4542]]
48633 // SIMD-ONLY0:       if.end4542:
48634 // SIMD-ONLY0-NEXT:    [[TMP3291:%.*]] = load i64, ptr [[ULX]], align 8
48635 // SIMD-ONLY0-NEXT:    store i64 [[TMP3291]], ptr [[ULV]], align 8
48636 // SIMD-ONLY0-NEXT:    [[TMP3292:%.*]] = load i64, ptr [[ULX]], align 8
48637 // SIMD-ONLY0-NEXT:    [[TMP3293:%.*]] = load i64, ptr [[ULE]], align 8
48638 // SIMD-ONLY0-NEXT:    [[CMP4543:%.*]] = icmp ult i64 [[TMP3292]], [[TMP3293]]
48639 // SIMD-ONLY0-NEXT:    br i1 [[CMP4543]], label [[IF_THEN4545:%.*]], label [[IF_END4546:%.*]]
48640 // SIMD-ONLY0:       if.then4545:
48641 // SIMD-ONLY0-NEXT:    [[TMP3294:%.*]] = load i64, ptr [[ULE]], align 8
48642 // SIMD-ONLY0-NEXT:    store i64 [[TMP3294]], ptr [[ULX]], align 8
48643 // SIMD-ONLY0-NEXT:    br label [[IF_END4546]]
48644 // SIMD-ONLY0:       if.end4546:
48645 // SIMD-ONLY0-NEXT:    [[TMP3295:%.*]] = load i64, ptr [[ULX]], align 8
48646 // SIMD-ONLY0-NEXT:    store i64 [[TMP3295]], ptr [[ULV]], align 8
48647 // SIMD-ONLY0-NEXT:    [[TMP3296:%.*]] = load i64, ptr [[ULX]], align 8
48648 // SIMD-ONLY0-NEXT:    [[TMP3297:%.*]] = load i64, ptr [[ULE]], align 8
48649 // SIMD-ONLY0-NEXT:    [[CMP4547:%.*]] = icmp eq i64 [[TMP3296]], [[TMP3297]]
48650 // SIMD-ONLY0-NEXT:    br i1 [[CMP4547]], label [[IF_THEN4549:%.*]], label [[IF_END4550:%.*]]
48651 // SIMD-ONLY0:       if.then4549:
48652 // SIMD-ONLY0-NEXT:    [[TMP3298:%.*]] = load i64, ptr [[ULD]], align 8
48653 // SIMD-ONLY0-NEXT:    store i64 [[TMP3298]], ptr [[ULX]], align 8
48654 // SIMD-ONLY0-NEXT:    br label [[IF_END4550]]
48655 // SIMD-ONLY0:       if.end4550:
48656 // SIMD-ONLY0-NEXT:    [[TMP3299:%.*]] = load i64, ptr [[ULX]], align 8
48657 // SIMD-ONLY0-NEXT:    store i64 [[TMP3299]], ptr [[ULV]], align 8
48658 // SIMD-ONLY0-NEXT:    [[TMP3300:%.*]] = load i64, ptr [[ULE]], align 8
48659 // SIMD-ONLY0-NEXT:    [[TMP3301:%.*]] = load i64, ptr [[ULX]], align 8
48660 // SIMD-ONLY0-NEXT:    [[CMP4551:%.*]] = icmp eq i64 [[TMP3300]], [[TMP3301]]
48661 // SIMD-ONLY0-NEXT:    br i1 [[CMP4551]], label [[IF_THEN4553:%.*]], label [[IF_END4554:%.*]]
48662 // SIMD-ONLY0:       if.then4553:
48663 // SIMD-ONLY0-NEXT:    [[TMP3302:%.*]] = load i64, ptr [[ULD]], align 8
48664 // SIMD-ONLY0-NEXT:    store i64 [[TMP3302]], ptr [[ULX]], align 8
48665 // SIMD-ONLY0-NEXT:    br label [[IF_END4554]]
48666 // SIMD-ONLY0:       if.end4554:
48667 // SIMD-ONLY0-NEXT:    [[TMP3303:%.*]] = load i64, ptr [[ULX]], align 8
48668 // SIMD-ONLY0-NEXT:    store i64 [[TMP3303]], ptr [[ULV]], align 8
48669 // SIMD-ONLY0-NEXT:    [[TMP3304:%.*]] = load i64, ptr [[ULX]], align 8
48670 // SIMD-ONLY0-NEXT:    [[TMP3305:%.*]] = load i64, ptr [[ULE]], align 8
48671 // SIMD-ONLY0-NEXT:    [[CMP4555:%.*]] = icmp eq i64 [[TMP3304]], [[TMP3305]]
48672 // SIMD-ONLY0-NEXT:    br i1 [[CMP4555]], label [[IF_THEN4557:%.*]], label [[IF_ELSE4558:%.*]]
48673 // SIMD-ONLY0:       if.then4557:
48674 // SIMD-ONLY0-NEXT:    [[TMP3306:%.*]] = load i64, ptr [[ULD]], align 8
48675 // SIMD-ONLY0-NEXT:    store i64 [[TMP3306]], ptr [[ULX]], align 8
48676 // SIMD-ONLY0-NEXT:    br label [[IF_END4559:%.*]]
48677 // SIMD-ONLY0:       if.else4558:
48678 // SIMD-ONLY0-NEXT:    [[TMP3307:%.*]] = load i64, ptr [[ULX]], align 8
48679 // SIMD-ONLY0-NEXT:    store i64 [[TMP3307]], ptr [[ULV]], align 8
48680 // SIMD-ONLY0-NEXT:    br label [[IF_END4559]]
48681 // SIMD-ONLY0:       if.end4559:
48682 // SIMD-ONLY0-NEXT:    [[TMP3308:%.*]] = load i64, ptr [[ULE]], align 8
48683 // SIMD-ONLY0-NEXT:    [[TMP3309:%.*]] = load i64, ptr [[ULX]], align 8
48684 // SIMD-ONLY0-NEXT:    [[CMP4560:%.*]] = icmp eq i64 [[TMP3308]], [[TMP3309]]
48685 // SIMD-ONLY0-NEXT:    br i1 [[CMP4560]], label [[IF_THEN4562:%.*]], label [[IF_ELSE4563:%.*]]
48686 // SIMD-ONLY0:       if.then4562:
48687 // SIMD-ONLY0-NEXT:    [[TMP3310:%.*]] = load i64, ptr [[ULD]], align 8
48688 // SIMD-ONLY0-NEXT:    store i64 [[TMP3310]], ptr [[ULX]], align 8
48689 // SIMD-ONLY0-NEXT:    br label [[IF_END4564:%.*]]
48690 // SIMD-ONLY0:       if.else4563:
48691 // SIMD-ONLY0-NEXT:    [[TMP3311:%.*]] = load i64, ptr [[ULX]], align 8
48692 // SIMD-ONLY0-NEXT:    store i64 [[TMP3311]], ptr [[ULV]], align 8
48693 // SIMD-ONLY0-NEXT:    br label [[IF_END4564]]
48694 // SIMD-ONLY0:       if.end4564:
48695 // SIMD-ONLY0-NEXT:    [[TMP3312:%.*]] = load i64, ptr [[ULX]], align 8
48696 // SIMD-ONLY0-NEXT:    [[TMP3313:%.*]] = load i64, ptr [[ULE]], align 8
48697 // SIMD-ONLY0-NEXT:    [[CMP4565:%.*]] = icmp eq i64 [[TMP3312]], [[TMP3313]]
48698 // SIMD-ONLY0-NEXT:    [[CONV4566:%.*]] = zext i1 [[CMP4565]] to i32
48699 // SIMD-ONLY0-NEXT:    [[CONV4567:%.*]] = sext i32 [[CONV4566]] to i64
48700 // SIMD-ONLY0-NEXT:    store i64 [[CONV4567]], ptr [[ULR]], align 8
48701 // SIMD-ONLY0-NEXT:    [[TMP3314:%.*]] = load i64, ptr [[ULR]], align 8
48702 // SIMD-ONLY0-NEXT:    [[TOBOOL4568:%.*]] = icmp ne i64 [[TMP3314]], 0
48703 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4568]], label [[IF_THEN4569:%.*]], label [[IF_END4570:%.*]]
48704 // SIMD-ONLY0:       if.then4569:
48705 // SIMD-ONLY0-NEXT:    [[TMP3315:%.*]] = load i64, ptr [[ULD]], align 8
48706 // SIMD-ONLY0-NEXT:    store i64 [[TMP3315]], ptr [[ULX]], align 8
48707 // SIMD-ONLY0-NEXT:    br label [[IF_END4570]]
48708 // SIMD-ONLY0:       if.end4570:
48709 // SIMD-ONLY0-NEXT:    [[TMP3316:%.*]] = load i64, ptr [[ULE]], align 8
48710 // SIMD-ONLY0-NEXT:    [[TMP3317:%.*]] = load i64, ptr [[ULX]], align 8
48711 // SIMD-ONLY0-NEXT:    [[CMP4571:%.*]] = icmp eq i64 [[TMP3316]], [[TMP3317]]
48712 // SIMD-ONLY0-NEXT:    [[CONV4572:%.*]] = zext i1 [[CMP4571]] to i32
48713 // SIMD-ONLY0-NEXT:    [[CONV4573:%.*]] = sext i32 [[CONV4572]] to i64
48714 // SIMD-ONLY0-NEXT:    store i64 [[CONV4573]], ptr [[ULR]], align 8
48715 // SIMD-ONLY0-NEXT:    [[TMP3318:%.*]] = load i64, ptr [[ULR]], align 8
48716 // SIMD-ONLY0-NEXT:    [[TOBOOL4574:%.*]] = icmp ne i64 [[TMP3318]], 0
48717 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4574]], label [[IF_THEN4575:%.*]], label [[IF_END4576:%.*]]
48718 // SIMD-ONLY0:       if.then4575:
48719 // SIMD-ONLY0-NEXT:    [[TMP3319:%.*]] = load i64, ptr [[ULD]], align 8
48720 // SIMD-ONLY0-NEXT:    store i64 [[TMP3319]], ptr [[ULX]], align 8
48721 // SIMD-ONLY0-NEXT:    br label [[IF_END4576]]
48722 // SIMD-ONLY0:       if.end4576:
48723 // SIMD-ONLY0-NEXT:    [[TMP3320:%.*]] = load i64, ptr [[ULX]], align 8
48724 // SIMD-ONLY0-NEXT:    [[TMP3321:%.*]] = load i64, ptr [[ULE]], align 8
48725 // SIMD-ONLY0-NEXT:    [[CMP4577:%.*]] = icmp eq i64 [[TMP3320]], [[TMP3321]]
48726 // SIMD-ONLY0-NEXT:    [[CONV4578:%.*]] = zext i1 [[CMP4577]] to i32
48727 // SIMD-ONLY0-NEXT:    [[CONV4579:%.*]] = sext i32 [[CONV4578]] to i64
48728 // SIMD-ONLY0-NEXT:    store i64 [[CONV4579]], ptr [[ULR]], align 8
48729 // SIMD-ONLY0-NEXT:    [[TMP3322:%.*]] = load i64, ptr [[ULR]], align 8
48730 // SIMD-ONLY0-NEXT:    [[TOBOOL4580:%.*]] = icmp ne i64 [[TMP3322]], 0
48731 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4580]], label [[IF_THEN4581:%.*]], label [[IF_ELSE4582:%.*]]
48732 // SIMD-ONLY0:       if.then4581:
48733 // SIMD-ONLY0-NEXT:    [[TMP3323:%.*]] = load i64, ptr [[ULD]], align 8
48734 // SIMD-ONLY0-NEXT:    store i64 [[TMP3323]], ptr [[ULX]], align 8
48735 // SIMD-ONLY0-NEXT:    br label [[IF_END4583:%.*]]
48736 // SIMD-ONLY0:       if.else4582:
48737 // SIMD-ONLY0-NEXT:    [[TMP3324:%.*]] = load i64, ptr [[ULX]], align 8
48738 // SIMD-ONLY0-NEXT:    store i64 [[TMP3324]], ptr [[ULV]], align 8
48739 // SIMD-ONLY0-NEXT:    br label [[IF_END4583]]
48740 // SIMD-ONLY0:       if.end4583:
48741 // SIMD-ONLY0-NEXT:    [[TMP3325:%.*]] = load i64, ptr [[ULE]], align 8
48742 // SIMD-ONLY0-NEXT:    [[TMP3326:%.*]] = load i64, ptr [[ULX]], align 8
48743 // SIMD-ONLY0-NEXT:    [[CMP4584:%.*]] = icmp eq i64 [[TMP3325]], [[TMP3326]]
48744 // SIMD-ONLY0-NEXT:    [[CONV4585:%.*]] = zext i1 [[CMP4584]] to i32
48745 // SIMD-ONLY0-NEXT:    [[CONV4586:%.*]] = sext i32 [[CONV4585]] to i64
48746 // SIMD-ONLY0-NEXT:    store i64 [[CONV4586]], ptr [[ULR]], align 8
48747 // SIMD-ONLY0-NEXT:    [[TMP3327:%.*]] = load i64, ptr [[ULR]], align 8
48748 // SIMD-ONLY0-NEXT:    [[TOBOOL4587:%.*]] = icmp ne i64 [[TMP3327]], 0
48749 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4587]], label [[IF_THEN4588:%.*]], label [[IF_ELSE4589:%.*]]
48750 // SIMD-ONLY0:       if.then4588:
48751 // SIMD-ONLY0-NEXT:    [[TMP3328:%.*]] = load i64, ptr [[ULD]], align 8
48752 // SIMD-ONLY0-NEXT:    store i64 [[TMP3328]], ptr [[ULX]], align 8
48753 // SIMD-ONLY0-NEXT:    br label [[IF_END4590:%.*]]
48754 // SIMD-ONLY0:       if.else4589:
48755 // SIMD-ONLY0-NEXT:    [[TMP3329:%.*]] = load i64, ptr [[ULX]], align 8
48756 // SIMD-ONLY0-NEXT:    store i64 [[TMP3329]], ptr [[ULV]], align 8
48757 // SIMD-ONLY0-NEXT:    br label [[IF_END4590]]
48758 // SIMD-ONLY0:       if.end4590:
48759 // SIMD-ONLY0-NEXT:    [[TMP3330:%.*]] = load i64, ptr [[ULX]], align 8
48760 // SIMD-ONLY0-NEXT:    store i64 [[TMP3330]], ptr [[ULV]], align 8
48761 // SIMD-ONLY0-NEXT:    [[TMP3331:%.*]] = load i64, ptr [[ULE]], align 8
48762 // SIMD-ONLY0-NEXT:    [[TMP3332:%.*]] = load i64, ptr [[ULX]], align 8
48763 // SIMD-ONLY0-NEXT:    [[CMP4591:%.*]] = icmp ugt i64 [[TMP3331]], [[TMP3332]]
48764 // SIMD-ONLY0-NEXT:    br i1 [[CMP4591]], label [[IF_THEN4593:%.*]], label [[IF_END4594:%.*]]
48765 // SIMD-ONLY0:       if.then4593:
48766 // SIMD-ONLY0-NEXT:    [[TMP3333:%.*]] = load i64, ptr [[ULE]], align 8
48767 // SIMD-ONLY0-NEXT:    store i64 [[TMP3333]], ptr [[ULX]], align 8
48768 // SIMD-ONLY0-NEXT:    br label [[IF_END4594]]
48769 // SIMD-ONLY0:       if.end4594:
48770 // SIMD-ONLY0-NEXT:    [[TMP3334:%.*]] = load i64, ptr [[ULX]], align 8
48771 // SIMD-ONLY0-NEXT:    store i64 [[TMP3334]], ptr [[ULV]], align 8
48772 // SIMD-ONLY0-NEXT:    [[TMP3335:%.*]] = load i64, ptr [[ULX]], align 8
48773 // SIMD-ONLY0-NEXT:    [[TMP3336:%.*]] = load i64, ptr [[ULE]], align 8
48774 // SIMD-ONLY0-NEXT:    [[CMP4595:%.*]] = icmp ugt i64 [[TMP3335]], [[TMP3336]]
48775 // SIMD-ONLY0-NEXT:    br i1 [[CMP4595]], label [[IF_THEN4597:%.*]], label [[IF_END4598:%.*]]
48776 // SIMD-ONLY0:       if.then4597:
48777 // SIMD-ONLY0-NEXT:    [[TMP3337:%.*]] = load i64, ptr [[ULE]], align 8
48778 // SIMD-ONLY0-NEXT:    store i64 [[TMP3337]], ptr [[ULX]], align 8
48779 // SIMD-ONLY0-NEXT:    br label [[IF_END4598]]
48780 // SIMD-ONLY0:       if.end4598:
48781 // SIMD-ONLY0-NEXT:    [[TMP3338:%.*]] = load i64, ptr [[ULX]], align 8
48782 // SIMD-ONLY0-NEXT:    store i64 [[TMP3338]], ptr [[ULV]], align 8
48783 // SIMD-ONLY0-NEXT:    [[TMP3339:%.*]] = load i64, ptr [[ULE]], align 8
48784 // SIMD-ONLY0-NEXT:    [[TMP3340:%.*]] = load i64, ptr [[ULX]], align 8
48785 // SIMD-ONLY0-NEXT:    [[CMP4599:%.*]] = icmp ult i64 [[TMP3339]], [[TMP3340]]
48786 // SIMD-ONLY0-NEXT:    br i1 [[CMP4599]], label [[IF_THEN4601:%.*]], label [[IF_END4602:%.*]]
48787 // SIMD-ONLY0:       if.then4601:
48788 // SIMD-ONLY0-NEXT:    [[TMP3341:%.*]] = load i64, ptr [[ULE]], align 8
48789 // SIMD-ONLY0-NEXT:    store i64 [[TMP3341]], ptr [[ULX]], align 8
48790 // SIMD-ONLY0-NEXT:    br label [[IF_END4602]]
48791 // SIMD-ONLY0:       if.end4602:
48792 // SIMD-ONLY0-NEXT:    [[TMP3342:%.*]] = load i64, ptr [[ULX]], align 8
48793 // SIMD-ONLY0-NEXT:    store i64 [[TMP3342]], ptr [[ULV]], align 8
48794 // SIMD-ONLY0-NEXT:    [[TMP3343:%.*]] = load i64, ptr [[ULX]], align 8
48795 // SIMD-ONLY0-NEXT:    [[TMP3344:%.*]] = load i64, ptr [[ULE]], align 8
48796 // SIMD-ONLY0-NEXT:    [[CMP4603:%.*]] = icmp ult i64 [[TMP3343]], [[TMP3344]]
48797 // SIMD-ONLY0-NEXT:    br i1 [[CMP4603]], label [[IF_THEN4605:%.*]], label [[IF_END4606:%.*]]
48798 // SIMD-ONLY0:       if.then4605:
48799 // SIMD-ONLY0-NEXT:    [[TMP3345:%.*]] = load i64, ptr [[ULE]], align 8
48800 // SIMD-ONLY0-NEXT:    store i64 [[TMP3345]], ptr [[ULX]], align 8
48801 // SIMD-ONLY0-NEXT:    br label [[IF_END4606]]
48802 // SIMD-ONLY0:       if.end4606:
48803 // SIMD-ONLY0-NEXT:    [[TMP3346:%.*]] = load i64, ptr [[ULX]], align 8
48804 // SIMD-ONLY0-NEXT:    store i64 [[TMP3346]], ptr [[ULV]], align 8
48805 // SIMD-ONLY0-NEXT:    [[TMP3347:%.*]] = load i64, ptr [[ULX]], align 8
48806 // SIMD-ONLY0-NEXT:    [[TMP3348:%.*]] = load i64, ptr [[ULE]], align 8
48807 // SIMD-ONLY0-NEXT:    [[CMP4607:%.*]] = icmp eq i64 [[TMP3347]], [[TMP3348]]
48808 // SIMD-ONLY0-NEXT:    br i1 [[CMP4607]], label [[IF_THEN4609:%.*]], label [[IF_END4610:%.*]]
48809 // SIMD-ONLY0:       if.then4609:
48810 // SIMD-ONLY0-NEXT:    [[TMP3349:%.*]] = load i64, ptr [[ULD]], align 8
48811 // SIMD-ONLY0-NEXT:    store i64 [[TMP3349]], ptr [[ULX]], align 8
48812 // SIMD-ONLY0-NEXT:    br label [[IF_END4610]]
48813 // SIMD-ONLY0:       if.end4610:
48814 // SIMD-ONLY0-NEXT:    [[TMP3350:%.*]] = load i64, ptr [[ULX]], align 8
48815 // SIMD-ONLY0-NEXT:    store i64 [[TMP3350]], ptr [[ULV]], align 8
48816 // SIMD-ONLY0-NEXT:    [[TMP3351:%.*]] = load i64, ptr [[ULE]], align 8
48817 // SIMD-ONLY0-NEXT:    [[TMP3352:%.*]] = load i64, ptr [[ULX]], align 8
48818 // SIMD-ONLY0-NEXT:    [[CMP4611:%.*]] = icmp eq i64 [[TMP3351]], [[TMP3352]]
48819 // SIMD-ONLY0-NEXT:    br i1 [[CMP4611]], label [[IF_THEN4613:%.*]], label [[IF_END4614:%.*]]
48820 // SIMD-ONLY0:       if.then4613:
48821 // SIMD-ONLY0-NEXT:    [[TMP3353:%.*]] = load i64, ptr [[ULD]], align 8
48822 // SIMD-ONLY0-NEXT:    store i64 [[TMP3353]], ptr [[ULX]], align 8
48823 // SIMD-ONLY0-NEXT:    br label [[IF_END4614]]
48824 // SIMD-ONLY0:       if.end4614:
48825 // SIMD-ONLY0-NEXT:    [[TMP3354:%.*]] = load i64, ptr [[ULE]], align 8
48826 // SIMD-ONLY0-NEXT:    [[TMP3355:%.*]] = load i64, ptr [[ULX]], align 8
48827 // SIMD-ONLY0-NEXT:    [[CMP4615:%.*]] = icmp ugt i64 [[TMP3354]], [[TMP3355]]
48828 // SIMD-ONLY0-NEXT:    br i1 [[CMP4615]], label [[IF_THEN4617:%.*]], label [[IF_END4618:%.*]]
48829 // SIMD-ONLY0:       if.then4617:
48830 // SIMD-ONLY0-NEXT:    [[TMP3356:%.*]] = load i64, ptr [[ULE]], align 8
48831 // SIMD-ONLY0-NEXT:    store i64 [[TMP3356]], ptr [[ULX]], align 8
48832 // SIMD-ONLY0-NEXT:    br label [[IF_END4618]]
48833 // SIMD-ONLY0:       if.end4618:
48834 // SIMD-ONLY0-NEXT:    [[TMP3357:%.*]] = load i64, ptr [[ULX]], align 8
48835 // SIMD-ONLY0-NEXT:    store i64 [[TMP3357]], ptr [[ULV]], align 8
48836 // SIMD-ONLY0-NEXT:    [[TMP3358:%.*]] = load i64, ptr [[ULX]], align 8
48837 // SIMD-ONLY0-NEXT:    [[TMP3359:%.*]] = load i64, ptr [[ULE]], align 8
48838 // SIMD-ONLY0-NEXT:    [[CMP4619:%.*]] = icmp ugt i64 [[TMP3358]], [[TMP3359]]
48839 // SIMD-ONLY0-NEXT:    br i1 [[CMP4619]], label [[IF_THEN4621:%.*]], label [[IF_END4622:%.*]]
48840 // SIMD-ONLY0:       if.then4621:
48841 // SIMD-ONLY0-NEXT:    [[TMP3360:%.*]] = load i64, ptr [[ULE]], align 8
48842 // SIMD-ONLY0-NEXT:    store i64 [[TMP3360]], ptr [[ULX]], align 8
48843 // SIMD-ONLY0-NEXT:    br label [[IF_END4622]]
48844 // SIMD-ONLY0:       if.end4622:
48845 // SIMD-ONLY0-NEXT:    [[TMP3361:%.*]] = load i64, ptr [[ULX]], align 8
48846 // SIMD-ONLY0-NEXT:    store i64 [[TMP3361]], ptr [[ULV]], align 8
48847 // SIMD-ONLY0-NEXT:    [[TMP3362:%.*]] = load i64, ptr [[ULE]], align 8
48848 // SIMD-ONLY0-NEXT:    [[TMP3363:%.*]] = load i64, ptr [[ULX]], align 8
48849 // SIMD-ONLY0-NEXT:    [[CMP4623:%.*]] = icmp ult i64 [[TMP3362]], [[TMP3363]]
48850 // SIMD-ONLY0-NEXT:    br i1 [[CMP4623]], label [[IF_THEN4625:%.*]], label [[IF_END4626:%.*]]
48851 // SIMD-ONLY0:       if.then4625:
48852 // SIMD-ONLY0-NEXT:    [[TMP3364:%.*]] = load i64, ptr [[ULE]], align 8
48853 // SIMD-ONLY0-NEXT:    store i64 [[TMP3364]], ptr [[ULX]], align 8
48854 // SIMD-ONLY0-NEXT:    br label [[IF_END4626]]
48855 // SIMD-ONLY0:       if.end4626:
48856 // SIMD-ONLY0-NEXT:    [[TMP3365:%.*]] = load i64, ptr [[ULX]], align 8
48857 // SIMD-ONLY0-NEXT:    store i64 [[TMP3365]], ptr [[ULV]], align 8
48858 // SIMD-ONLY0-NEXT:    [[TMP3366:%.*]] = load i64, ptr [[ULX]], align 8
48859 // SIMD-ONLY0-NEXT:    [[TMP3367:%.*]] = load i64, ptr [[ULE]], align 8
48860 // SIMD-ONLY0-NEXT:    [[CMP4627:%.*]] = icmp ult i64 [[TMP3366]], [[TMP3367]]
48861 // SIMD-ONLY0-NEXT:    br i1 [[CMP4627]], label [[IF_THEN4629:%.*]], label [[IF_END4630:%.*]]
48862 // SIMD-ONLY0:       if.then4629:
48863 // SIMD-ONLY0-NEXT:    [[TMP3368:%.*]] = load i64, ptr [[ULE]], align 8
48864 // SIMD-ONLY0-NEXT:    store i64 [[TMP3368]], ptr [[ULX]], align 8
48865 // SIMD-ONLY0-NEXT:    br label [[IF_END4630]]
48866 // SIMD-ONLY0:       if.end4630:
48867 // SIMD-ONLY0-NEXT:    [[TMP3369:%.*]] = load i64, ptr [[ULX]], align 8
48868 // SIMD-ONLY0-NEXT:    store i64 [[TMP3369]], ptr [[ULV]], align 8
48869 // SIMD-ONLY0-NEXT:    [[TMP3370:%.*]] = load i64, ptr [[ULX]], align 8
48870 // SIMD-ONLY0-NEXT:    [[TMP3371:%.*]] = load i64, ptr [[ULE]], align 8
48871 // SIMD-ONLY0-NEXT:    [[CMP4631:%.*]] = icmp eq i64 [[TMP3370]], [[TMP3371]]
48872 // SIMD-ONLY0-NEXT:    br i1 [[CMP4631]], label [[IF_THEN4633:%.*]], label [[IF_END4634:%.*]]
48873 // SIMD-ONLY0:       if.then4633:
48874 // SIMD-ONLY0-NEXT:    [[TMP3372:%.*]] = load i64, ptr [[ULD]], align 8
48875 // SIMD-ONLY0-NEXT:    store i64 [[TMP3372]], ptr [[ULX]], align 8
48876 // SIMD-ONLY0-NEXT:    br label [[IF_END4634]]
48877 // SIMD-ONLY0:       if.end4634:
48878 // SIMD-ONLY0-NEXT:    [[TMP3373:%.*]] = load i64, ptr [[ULX]], align 8
48879 // SIMD-ONLY0-NEXT:    store i64 [[TMP3373]], ptr [[ULV]], align 8
48880 // SIMD-ONLY0-NEXT:    [[TMP3374:%.*]] = load i64, ptr [[ULE]], align 8
48881 // SIMD-ONLY0-NEXT:    [[TMP3375:%.*]] = load i64, ptr [[ULX]], align 8
48882 // SIMD-ONLY0-NEXT:    [[CMP4635:%.*]] = icmp eq i64 [[TMP3374]], [[TMP3375]]
48883 // SIMD-ONLY0-NEXT:    br i1 [[CMP4635]], label [[IF_THEN4637:%.*]], label [[IF_END4638:%.*]]
48884 // SIMD-ONLY0:       if.then4637:
48885 // SIMD-ONLY0-NEXT:    [[TMP3376:%.*]] = load i64, ptr [[ULD]], align 8
48886 // SIMD-ONLY0-NEXT:    store i64 [[TMP3376]], ptr [[ULX]], align 8
48887 // SIMD-ONLY0-NEXT:    br label [[IF_END4638]]
48888 // SIMD-ONLY0:       if.end4638:
48889 // SIMD-ONLY0-NEXT:    [[TMP3377:%.*]] = load i64, ptr [[ULX]], align 8
48890 // SIMD-ONLY0-NEXT:    store i64 [[TMP3377]], ptr [[ULV]], align 8
48891 // SIMD-ONLY0-NEXT:    [[TMP3378:%.*]] = load i64, ptr [[ULX]], align 8
48892 // SIMD-ONLY0-NEXT:    [[TMP3379:%.*]] = load i64, ptr [[ULE]], align 8
48893 // SIMD-ONLY0-NEXT:    [[CMP4639:%.*]] = icmp eq i64 [[TMP3378]], [[TMP3379]]
48894 // SIMD-ONLY0-NEXT:    br i1 [[CMP4639]], label [[IF_THEN4641:%.*]], label [[IF_ELSE4642:%.*]]
48895 // SIMD-ONLY0:       if.then4641:
48896 // SIMD-ONLY0-NEXT:    [[TMP3380:%.*]] = load i64, ptr [[ULD]], align 8
48897 // SIMD-ONLY0-NEXT:    store i64 [[TMP3380]], ptr [[ULX]], align 8
48898 // SIMD-ONLY0-NEXT:    br label [[IF_END4643:%.*]]
48899 // SIMD-ONLY0:       if.else4642:
48900 // SIMD-ONLY0-NEXT:    [[TMP3381:%.*]] = load i64, ptr [[ULX]], align 8
48901 // SIMD-ONLY0-NEXT:    store i64 [[TMP3381]], ptr [[ULV]], align 8
48902 // SIMD-ONLY0-NEXT:    br label [[IF_END4643]]
48903 // SIMD-ONLY0:       if.end4643:
48904 // SIMD-ONLY0-NEXT:    [[TMP3382:%.*]] = load i64, ptr [[ULE]], align 8
48905 // SIMD-ONLY0-NEXT:    [[TMP3383:%.*]] = load i64, ptr [[ULX]], align 8
48906 // SIMD-ONLY0-NEXT:    [[CMP4644:%.*]] = icmp eq i64 [[TMP3382]], [[TMP3383]]
48907 // SIMD-ONLY0-NEXT:    br i1 [[CMP4644]], label [[IF_THEN4646:%.*]], label [[IF_ELSE4647:%.*]]
48908 // SIMD-ONLY0:       if.then4646:
48909 // SIMD-ONLY0-NEXT:    [[TMP3384:%.*]] = load i64, ptr [[ULD]], align 8
48910 // SIMD-ONLY0-NEXT:    store i64 [[TMP3384]], ptr [[ULX]], align 8
48911 // SIMD-ONLY0-NEXT:    br label [[IF_END4648:%.*]]
48912 // SIMD-ONLY0:       if.else4647:
48913 // SIMD-ONLY0-NEXT:    [[TMP3385:%.*]] = load i64, ptr [[ULX]], align 8
48914 // SIMD-ONLY0-NEXT:    store i64 [[TMP3385]], ptr [[ULV]], align 8
48915 // SIMD-ONLY0-NEXT:    br label [[IF_END4648]]
48916 // SIMD-ONLY0:       if.end4648:
48917 // SIMD-ONLY0-NEXT:    [[TMP3386:%.*]] = load i64, ptr [[ULX]], align 8
48918 // SIMD-ONLY0-NEXT:    [[TMP3387:%.*]] = load i64, ptr [[ULE]], align 8
48919 // SIMD-ONLY0-NEXT:    [[CMP4649:%.*]] = icmp eq i64 [[TMP3386]], [[TMP3387]]
48920 // SIMD-ONLY0-NEXT:    [[CONV4650:%.*]] = zext i1 [[CMP4649]] to i32
48921 // SIMD-ONLY0-NEXT:    [[CONV4651:%.*]] = sext i32 [[CONV4650]] to i64
48922 // SIMD-ONLY0-NEXT:    store i64 [[CONV4651]], ptr [[ULR]], align 8
48923 // SIMD-ONLY0-NEXT:    [[TMP3388:%.*]] = load i64, ptr [[ULR]], align 8
48924 // SIMD-ONLY0-NEXT:    [[TOBOOL4652:%.*]] = icmp ne i64 [[TMP3388]], 0
48925 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4652]], label [[IF_THEN4653:%.*]], label [[IF_END4654:%.*]]
48926 // SIMD-ONLY0:       if.then4653:
48927 // SIMD-ONLY0-NEXT:    [[TMP3389:%.*]] = load i64, ptr [[ULD]], align 8
48928 // SIMD-ONLY0-NEXT:    store i64 [[TMP3389]], ptr [[ULX]], align 8
48929 // SIMD-ONLY0-NEXT:    br label [[IF_END4654]]
48930 // SIMD-ONLY0:       if.end4654:
48931 // SIMD-ONLY0-NEXT:    [[TMP3390:%.*]] = load i64, ptr [[ULE]], align 8
48932 // SIMD-ONLY0-NEXT:    [[TMP3391:%.*]] = load i64, ptr [[ULX]], align 8
48933 // SIMD-ONLY0-NEXT:    [[CMP4655:%.*]] = icmp eq i64 [[TMP3390]], [[TMP3391]]
48934 // SIMD-ONLY0-NEXT:    [[CONV4656:%.*]] = zext i1 [[CMP4655]] to i32
48935 // SIMD-ONLY0-NEXT:    [[CONV4657:%.*]] = sext i32 [[CONV4656]] to i64
48936 // SIMD-ONLY0-NEXT:    store i64 [[CONV4657]], ptr [[ULR]], align 8
48937 // SIMD-ONLY0-NEXT:    [[TMP3392:%.*]] = load i64, ptr [[ULR]], align 8
48938 // SIMD-ONLY0-NEXT:    [[TOBOOL4658:%.*]] = icmp ne i64 [[TMP3392]], 0
48939 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4658]], label [[IF_THEN4659:%.*]], label [[IF_END4660:%.*]]
48940 // SIMD-ONLY0:       if.then4659:
48941 // SIMD-ONLY0-NEXT:    [[TMP3393:%.*]] = load i64, ptr [[ULD]], align 8
48942 // SIMD-ONLY0-NEXT:    store i64 [[TMP3393]], ptr [[ULX]], align 8
48943 // SIMD-ONLY0-NEXT:    br label [[IF_END4660]]
48944 // SIMD-ONLY0:       if.end4660:
48945 // SIMD-ONLY0-NEXT:    [[TMP3394:%.*]] = load i64, ptr [[ULX]], align 8
48946 // SIMD-ONLY0-NEXT:    [[TMP3395:%.*]] = load i64, ptr [[ULE]], align 8
48947 // SIMD-ONLY0-NEXT:    [[CMP4661:%.*]] = icmp eq i64 [[TMP3394]], [[TMP3395]]
48948 // SIMD-ONLY0-NEXT:    [[CONV4662:%.*]] = zext i1 [[CMP4661]] to i32
48949 // SIMD-ONLY0-NEXT:    [[CONV4663:%.*]] = sext i32 [[CONV4662]] to i64
48950 // SIMD-ONLY0-NEXT:    store i64 [[CONV4663]], ptr [[ULR]], align 8
48951 // SIMD-ONLY0-NEXT:    [[TMP3396:%.*]] = load i64, ptr [[ULR]], align 8
48952 // SIMD-ONLY0-NEXT:    [[TOBOOL4664:%.*]] = icmp ne i64 [[TMP3396]], 0
48953 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4664]], label [[IF_THEN4665:%.*]], label [[IF_ELSE4666:%.*]]
48954 // SIMD-ONLY0:       if.then4665:
48955 // SIMD-ONLY0-NEXT:    [[TMP3397:%.*]] = load i64, ptr [[ULD]], align 8
48956 // SIMD-ONLY0-NEXT:    store i64 [[TMP3397]], ptr [[ULX]], align 8
48957 // SIMD-ONLY0-NEXT:    br label [[IF_END4667:%.*]]
48958 // SIMD-ONLY0:       if.else4666:
48959 // SIMD-ONLY0-NEXT:    [[TMP3398:%.*]] = load i64, ptr [[ULX]], align 8
48960 // SIMD-ONLY0-NEXT:    store i64 [[TMP3398]], ptr [[ULV]], align 8
48961 // SIMD-ONLY0-NEXT:    br label [[IF_END4667]]
48962 // SIMD-ONLY0:       if.end4667:
48963 // SIMD-ONLY0-NEXT:    [[TMP3399:%.*]] = load i64, ptr [[ULE]], align 8
48964 // SIMD-ONLY0-NEXT:    [[TMP3400:%.*]] = load i64, ptr [[ULX]], align 8
48965 // SIMD-ONLY0-NEXT:    [[CMP4668:%.*]] = icmp eq i64 [[TMP3399]], [[TMP3400]]
48966 // SIMD-ONLY0-NEXT:    [[CONV4669:%.*]] = zext i1 [[CMP4668]] to i32
48967 // SIMD-ONLY0-NEXT:    [[CONV4670:%.*]] = sext i32 [[CONV4669]] to i64
48968 // SIMD-ONLY0-NEXT:    store i64 [[CONV4670]], ptr [[ULR]], align 8
48969 // SIMD-ONLY0-NEXT:    [[TMP3401:%.*]] = load i64, ptr [[ULR]], align 8
48970 // SIMD-ONLY0-NEXT:    [[TOBOOL4671:%.*]] = icmp ne i64 [[TMP3401]], 0
48971 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4671]], label [[IF_THEN4672:%.*]], label [[IF_ELSE4673:%.*]]
48972 // SIMD-ONLY0:       if.then4672:
48973 // SIMD-ONLY0-NEXT:    [[TMP3402:%.*]] = load i64, ptr [[ULD]], align 8
48974 // SIMD-ONLY0-NEXT:    store i64 [[TMP3402]], ptr [[ULX]], align 8
48975 // SIMD-ONLY0-NEXT:    br label [[IF_END4674:%.*]]
48976 // SIMD-ONLY0:       if.else4673:
48977 // SIMD-ONLY0-NEXT:    [[TMP3403:%.*]] = load i64, ptr [[ULX]], align 8
48978 // SIMD-ONLY0-NEXT:    store i64 [[TMP3403]], ptr [[ULV]], align 8
48979 // SIMD-ONLY0-NEXT:    br label [[IF_END4674]]
48980 // SIMD-ONLY0:       if.end4674:
48981 // SIMD-ONLY0-NEXT:    [[TMP3404:%.*]] = load i64, ptr [[ULX]], align 8
48982 // SIMD-ONLY0-NEXT:    store i64 [[TMP3404]], ptr [[ULV]], align 8
48983 // SIMD-ONLY0-NEXT:    [[TMP3405:%.*]] = load i64, ptr [[ULE]], align 8
48984 // SIMD-ONLY0-NEXT:    [[TMP3406:%.*]] = load i64, ptr [[ULX]], align 8
48985 // SIMD-ONLY0-NEXT:    [[CMP4675:%.*]] = icmp ugt i64 [[TMP3405]], [[TMP3406]]
48986 // SIMD-ONLY0-NEXT:    br i1 [[CMP4675]], label [[IF_THEN4677:%.*]], label [[IF_END4678:%.*]]
48987 // SIMD-ONLY0:       if.then4677:
48988 // SIMD-ONLY0-NEXT:    [[TMP3407:%.*]] = load i64, ptr [[ULE]], align 8
48989 // SIMD-ONLY0-NEXT:    store i64 [[TMP3407]], ptr [[ULX]], align 8
48990 // SIMD-ONLY0-NEXT:    br label [[IF_END4678]]
48991 // SIMD-ONLY0:       if.end4678:
48992 // SIMD-ONLY0-NEXT:    [[TMP3408:%.*]] = load i64, ptr [[ULX]], align 8
48993 // SIMD-ONLY0-NEXT:    store i64 [[TMP3408]], ptr [[ULV]], align 8
48994 // SIMD-ONLY0-NEXT:    [[TMP3409:%.*]] = load i64, ptr [[ULX]], align 8
48995 // SIMD-ONLY0-NEXT:    [[TMP3410:%.*]] = load i64, ptr [[ULE]], align 8
48996 // SIMD-ONLY0-NEXT:    [[CMP4679:%.*]] = icmp ugt i64 [[TMP3409]], [[TMP3410]]
48997 // SIMD-ONLY0-NEXT:    br i1 [[CMP4679]], label [[IF_THEN4681:%.*]], label [[IF_END4682:%.*]]
48998 // SIMD-ONLY0:       if.then4681:
48999 // SIMD-ONLY0-NEXT:    [[TMP3411:%.*]] = load i64, ptr [[ULE]], align 8
49000 // SIMD-ONLY0-NEXT:    store i64 [[TMP3411]], ptr [[ULX]], align 8
49001 // SIMD-ONLY0-NEXT:    br label [[IF_END4682]]
49002 // SIMD-ONLY0:       if.end4682:
49003 // SIMD-ONLY0-NEXT:    [[TMP3412:%.*]] = load i64, ptr [[ULX]], align 8
49004 // SIMD-ONLY0-NEXT:    store i64 [[TMP3412]], ptr [[ULV]], align 8
49005 // SIMD-ONLY0-NEXT:    [[TMP3413:%.*]] = load i64, ptr [[ULE]], align 8
49006 // SIMD-ONLY0-NEXT:    [[TMP3414:%.*]] = load i64, ptr [[ULX]], align 8
49007 // SIMD-ONLY0-NEXT:    [[CMP4683:%.*]] = icmp ult i64 [[TMP3413]], [[TMP3414]]
49008 // SIMD-ONLY0-NEXT:    br i1 [[CMP4683]], label [[IF_THEN4685:%.*]], label [[IF_END4686:%.*]]
49009 // SIMD-ONLY0:       if.then4685:
49010 // SIMD-ONLY0-NEXT:    [[TMP3415:%.*]] = load i64, ptr [[ULE]], align 8
49011 // SIMD-ONLY0-NEXT:    store i64 [[TMP3415]], ptr [[ULX]], align 8
49012 // SIMD-ONLY0-NEXT:    br label [[IF_END4686]]
49013 // SIMD-ONLY0:       if.end4686:
49014 // SIMD-ONLY0-NEXT:    [[TMP3416:%.*]] = load i64, ptr [[ULX]], align 8
49015 // SIMD-ONLY0-NEXT:    store i64 [[TMP3416]], ptr [[ULV]], align 8
49016 // SIMD-ONLY0-NEXT:    [[TMP3417:%.*]] = load i64, ptr [[ULX]], align 8
49017 // SIMD-ONLY0-NEXT:    [[TMP3418:%.*]] = load i64, ptr [[ULE]], align 8
49018 // SIMD-ONLY0-NEXT:    [[CMP4687:%.*]] = icmp ult i64 [[TMP3417]], [[TMP3418]]
49019 // SIMD-ONLY0-NEXT:    br i1 [[CMP4687]], label [[IF_THEN4689:%.*]], label [[IF_END4690:%.*]]
49020 // SIMD-ONLY0:       if.then4689:
49021 // SIMD-ONLY0-NEXT:    [[TMP3419:%.*]] = load i64, ptr [[ULE]], align 8
49022 // SIMD-ONLY0-NEXT:    store i64 [[TMP3419]], ptr [[ULX]], align 8
49023 // SIMD-ONLY0-NEXT:    br label [[IF_END4690]]
49024 // SIMD-ONLY0:       if.end4690:
49025 // SIMD-ONLY0-NEXT:    [[TMP3420:%.*]] = load i64, ptr [[ULX]], align 8
49026 // SIMD-ONLY0-NEXT:    store i64 [[TMP3420]], ptr [[ULV]], align 8
49027 // SIMD-ONLY0-NEXT:    [[TMP3421:%.*]] = load i64, ptr [[ULX]], align 8
49028 // SIMD-ONLY0-NEXT:    [[TMP3422:%.*]] = load i64, ptr [[ULE]], align 8
49029 // SIMD-ONLY0-NEXT:    [[CMP4691:%.*]] = icmp eq i64 [[TMP3421]], [[TMP3422]]
49030 // SIMD-ONLY0-NEXT:    br i1 [[CMP4691]], label [[IF_THEN4693:%.*]], label [[IF_END4694:%.*]]
49031 // SIMD-ONLY0:       if.then4693:
49032 // SIMD-ONLY0-NEXT:    [[TMP3423:%.*]] = load i64, ptr [[ULD]], align 8
49033 // SIMD-ONLY0-NEXT:    store i64 [[TMP3423]], ptr [[ULX]], align 8
49034 // SIMD-ONLY0-NEXT:    br label [[IF_END4694]]
49035 // SIMD-ONLY0:       if.end4694:
49036 // SIMD-ONLY0-NEXT:    [[TMP3424:%.*]] = load i64, ptr [[ULX]], align 8
49037 // SIMD-ONLY0-NEXT:    store i64 [[TMP3424]], ptr [[ULV]], align 8
49038 // SIMD-ONLY0-NEXT:    [[TMP3425:%.*]] = load i64, ptr [[ULE]], align 8
49039 // SIMD-ONLY0-NEXT:    [[TMP3426:%.*]] = load i64, ptr [[ULX]], align 8
49040 // SIMD-ONLY0-NEXT:    [[CMP4695:%.*]] = icmp eq i64 [[TMP3425]], [[TMP3426]]
49041 // SIMD-ONLY0-NEXT:    br i1 [[CMP4695]], label [[IF_THEN4697:%.*]], label [[IF_END4698:%.*]]
49042 // SIMD-ONLY0:       if.then4697:
49043 // SIMD-ONLY0-NEXT:    [[TMP3427:%.*]] = load i64, ptr [[ULD]], align 8
49044 // SIMD-ONLY0-NEXT:    store i64 [[TMP3427]], ptr [[ULX]], align 8
49045 // SIMD-ONLY0-NEXT:    br label [[IF_END4698]]
49046 // SIMD-ONLY0:       if.end4698:
49047 // SIMD-ONLY0-NEXT:    [[TMP3428:%.*]] = load i64, ptr [[ULE]], align 8
49048 // SIMD-ONLY0-NEXT:    [[TMP3429:%.*]] = load i64, ptr [[ULX]], align 8
49049 // SIMD-ONLY0-NEXT:    [[CMP4699:%.*]] = icmp ugt i64 [[TMP3428]], [[TMP3429]]
49050 // SIMD-ONLY0-NEXT:    br i1 [[CMP4699]], label [[IF_THEN4701:%.*]], label [[IF_END4702:%.*]]
49051 // SIMD-ONLY0:       if.then4701:
49052 // SIMD-ONLY0-NEXT:    [[TMP3430:%.*]] = load i64, ptr [[ULE]], align 8
49053 // SIMD-ONLY0-NEXT:    store i64 [[TMP3430]], ptr [[ULX]], align 8
49054 // SIMD-ONLY0-NEXT:    br label [[IF_END4702]]
49055 // SIMD-ONLY0:       if.end4702:
49056 // SIMD-ONLY0-NEXT:    [[TMP3431:%.*]] = load i64, ptr [[ULX]], align 8
49057 // SIMD-ONLY0-NEXT:    store i64 [[TMP3431]], ptr [[ULV]], align 8
49058 // SIMD-ONLY0-NEXT:    [[TMP3432:%.*]] = load i64, ptr [[ULX]], align 8
49059 // SIMD-ONLY0-NEXT:    [[TMP3433:%.*]] = load i64, ptr [[ULE]], align 8
49060 // SIMD-ONLY0-NEXT:    [[CMP4703:%.*]] = icmp ugt i64 [[TMP3432]], [[TMP3433]]
49061 // SIMD-ONLY0-NEXT:    br i1 [[CMP4703]], label [[IF_THEN4705:%.*]], label [[IF_END4706:%.*]]
49062 // SIMD-ONLY0:       if.then4705:
49063 // SIMD-ONLY0-NEXT:    [[TMP3434:%.*]] = load i64, ptr [[ULE]], align 8
49064 // SIMD-ONLY0-NEXT:    store i64 [[TMP3434]], ptr [[ULX]], align 8
49065 // SIMD-ONLY0-NEXT:    br label [[IF_END4706]]
49066 // SIMD-ONLY0:       if.end4706:
49067 // SIMD-ONLY0-NEXT:    [[TMP3435:%.*]] = load i64, ptr [[ULX]], align 8
49068 // SIMD-ONLY0-NEXT:    store i64 [[TMP3435]], ptr [[ULV]], align 8
49069 // SIMD-ONLY0-NEXT:    [[TMP3436:%.*]] = load i64, ptr [[ULE]], align 8
49070 // SIMD-ONLY0-NEXT:    [[TMP3437:%.*]] = load i64, ptr [[ULX]], align 8
49071 // SIMD-ONLY0-NEXT:    [[CMP4707:%.*]] = icmp ult i64 [[TMP3436]], [[TMP3437]]
49072 // SIMD-ONLY0-NEXT:    br i1 [[CMP4707]], label [[IF_THEN4709:%.*]], label [[IF_END4710:%.*]]
49073 // SIMD-ONLY0:       if.then4709:
49074 // SIMD-ONLY0-NEXT:    [[TMP3438:%.*]] = load i64, ptr [[ULE]], align 8
49075 // SIMD-ONLY0-NEXT:    store i64 [[TMP3438]], ptr [[ULX]], align 8
49076 // SIMD-ONLY0-NEXT:    br label [[IF_END4710]]
49077 // SIMD-ONLY0:       if.end4710:
49078 // SIMD-ONLY0-NEXT:    [[TMP3439:%.*]] = load i64, ptr [[ULX]], align 8
49079 // SIMD-ONLY0-NEXT:    store i64 [[TMP3439]], ptr [[ULV]], align 8
49080 // SIMD-ONLY0-NEXT:    [[TMP3440:%.*]] = load i64, ptr [[ULX]], align 8
49081 // SIMD-ONLY0-NEXT:    [[TMP3441:%.*]] = load i64, ptr [[ULE]], align 8
49082 // SIMD-ONLY0-NEXT:    [[CMP4711:%.*]] = icmp ult i64 [[TMP3440]], [[TMP3441]]
49083 // SIMD-ONLY0-NEXT:    br i1 [[CMP4711]], label [[IF_THEN4713:%.*]], label [[IF_END4714:%.*]]
49084 // SIMD-ONLY0:       if.then4713:
49085 // SIMD-ONLY0-NEXT:    [[TMP3442:%.*]] = load i64, ptr [[ULE]], align 8
49086 // SIMD-ONLY0-NEXT:    store i64 [[TMP3442]], ptr [[ULX]], align 8
49087 // SIMD-ONLY0-NEXT:    br label [[IF_END4714]]
49088 // SIMD-ONLY0:       if.end4714:
49089 // SIMD-ONLY0-NEXT:    [[TMP3443:%.*]] = load i64, ptr [[ULX]], align 8
49090 // SIMD-ONLY0-NEXT:    store i64 [[TMP3443]], ptr [[ULV]], align 8
49091 // SIMD-ONLY0-NEXT:    [[TMP3444:%.*]] = load i64, ptr [[ULX]], align 8
49092 // SIMD-ONLY0-NEXT:    [[TMP3445:%.*]] = load i64, ptr [[ULE]], align 8
49093 // SIMD-ONLY0-NEXT:    [[CMP4715:%.*]] = icmp eq i64 [[TMP3444]], [[TMP3445]]
49094 // SIMD-ONLY0-NEXT:    br i1 [[CMP4715]], label [[IF_THEN4717:%.*]], label [[IF_END4718:%.*]]
49095 // SIMD-ONLY0:       if.then4717:
49096 // SIMD-ONLY0-NEXT:    [[TMP3446:%.*]] = load i64, ptr [[ULD]], align 8
49097 // SIMD-ONLY0-NEXT:    store i64 [[TMP3446]], ptr [[ULX]], align 8
49098 // SIMD-ONLY0-NEXT:    br label [[IF_END4718]]
49099 // SIMD-ONLY0:       if.end4718:
49100 // SIMD-ONLY0-NEXT:    [[TMP3447:%.*]] = load i64, ptr [[ULX]], align 8
49101 // SIMD-ONLY0-NEXT:    store i64 [[TMP3447]], ptr [[ULV]], align 8
49102 // SIMD-ONLY0-NEXT:    [[TMP3448:%.*]] = load i64, ptr [[ULE]], align 8
49103 // SIMD-ONLY0-NEXT:    [[TMP3449:%.*]] = load i64, ptr [[ULX]], align 8
49104 // SIMD-ONLY0-NEXT:    [[CMP4719:%.*]] = icmp eq i64 [[TMP3448]], [[TMP3449]]
49105 // SIMD-ONLY0-NEXT:    br i1 [[CMP4719]], label [[IF_THEN4721:%.*]], label [[IF_END4722:%.*]]
49106 // SIMD-ONLY0:       if.then4721:
49107 // SIMD-ONLY0-NEXT:    [[TMP3450:%.*]] = load i64, ptr [[ULD]], align 8
49108 // SIMD-ONLY0-NEXT:    store i64 [[TMP3450]], ptr [[ULX]], align 8
49109 // SIMD-ONLY0-NEXT:    br label [[IF_END4722]]
49110 // SIMD-ONLY0:       if.end4722:
49111 // SIMD-ONLY0-NEXT:    [[TMP3451:%.*]] = load i64, ptr [[ULX]], align 8
49112 // SIMD-ONLY0-NEXT:    store i64 [[TMP3451]], ptr [[ULV]], align 8
49113 // SIMD-ONLY0-NEXT:    [[TMP3452:%.*]] = load i64, ptr [[ULX]], align 8
49114 // SIMD-ONLY0-NEXT:    [[TMP3453:%.*]] = load i64, ptr [[ULE]], align 8
49115 // SIMD-ONLY0-NEXT:    [[CMP4723:%.*]] = icmp eq i64 [[TMP3452]], [[TMP3453]]
49116 // SIMD-ONLY0-NEXT:    br i1 [[CMP4723]], label [[IF_THEN4725:%.*]], label [[IF_ELSE4726:%.*]]
49117 // SIMD-ONLY0:       if.then4725:
49118 // SIMD-ONLY0-NEXT:    [[TMP3454:%.*]] = load i64, ptr [[ULD]], align 8
49119 // SIMD-ONLY0-NEXT:    store i64 [[TMP3454]], ptr [[ULX]], align 8
49120 // SIMD-ONLY0-NEXT:    br label [[IF_END4727:%.*]]
49121 // SIMD-ONLY0:       if.else4726:
49122 // SIMD-ONLY0-NEXT:    [[TMP3455:%.*]] = load i64, ptr [[ULX]], align 8
49123 // SIMD-ONLY0-NEXT:    store i64 [[TMP3455]], ptr [[ULV]], align 8
49124 // SIMD-ONLY0-NEXT:    br label [[IF_END4727]]
49125 // SIMD-ONLY0:       if.end4727:
49126 // SIMD-ONLY0-NEXT:    [[TMP3456:%.*]] = load i64, ptr [[ULE]], align 8
49127 // SIMD-ONLY0-NEXT:    [[TMP3457:%.*]] = load i64, ptr [[ULX]], align 8
49128 // SIMD-ONLY0-NEXT:    [[CMP4728:%.*]] = icmp eq i64 [[TMP3456]], [[TMP3457]]
49129 // SIMD-ONLY0-NEXT:    br i1 [[CMP4728]], label [[IF_THEN4730:%.*]], label [[IF_ELSE4731:%.*]]
49130 // SIMD-ONLY0:       if.then4730:
49131 // SIMD-ONLY0-NEXT:    [[TMP3458:%.*]] = load i64, ptr [[ULD]], align 8
49132 // SIMD-ONLY0-NEXT:    store i64 [[TMP3458]], ptr [[ULX]], align 8
49133 // SIMD-ONLY0-NEXT:    br label [[IF_END4732:%.*]]
49134 // SIMD-ONLY0:       if.else4731:
49135 // SIMD-ONLY0-NEXT:    [[TMP3459:%.*]] = load i64, ptr [[ULX]], align 8
49136 // SIMD-ONLY0-NEXT:    store i64 [[TMP3459]], ptr [[ULV]], align 8
49137 // SIMD-ONLY0-NEXT:    br label [[IF_END4732]]
49138 // SIMD-ONLY0:       if.end4732:
49139 // SIMD-ONLY0-NEXT:    [[TMP3460:%.*]] = load i64, ptr [[ULX]], align 8
49140 // SIMD-ONLY0-NEXT:    [[TMP3461:%.*]] = load i64, ptr [[ULE]], align 8
49141 // SIMD-ONLY0-NEXT:    [[CMP4733:%.*]] = icmp eq i64 [[TMP3460]], [[TMP3461]]
49142 // SIMD-ONLY0-NEXT:    [[CONV4734:%.*]] = zext i1 [[CMP4733]] to i32
49143 // SIMD-ONLY0-NEXT:    [[CONV4735:%.*]] = sext i32 [[CONV4734]] to i64
49144 // SIMD-ONLY0-NEXT:    store i64 [[CONV4735]], ptr [[ULR]], align 8
49145 // SIMD-ONLY0-NEXT:    [[TMP3462:%.*]] = load i64, ptr [[ULR]], align 8
49146 // SIMD-ONLY0-NEXT:    [[TOBOOL4736:%.*]] = icmp ne i64 [[TMP3462]], 0
49147 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4736]], label [[IF_THEN4737:%.*]], label [[IF_END4738:%.*]]
49148 // SIMD-ONLY0:       if.then4737:
49149 // SIMD-ONLY0-NEXT:    [[TMP3463:%.*]] = load i64, ptr [[ULD]], align 8
49150 // SIMD-ONLY0-NEXT:    store i64 [[TMP3463]], ptr [[ULX]], align 8
49151 // SIMD-ONLY0-NEXT:    br label [[IF_END4738]]
49152 // SIMD-ONLY0:       if.end4738:
49153 // SIMD-ONLY0-NEXT:    [[TMP3464:%.*]] = load i64, ptr [[ULE]], align 8
49154 // SIMD-ONLY0-NEXT:    [[TMP3465:%.*]] = load i64, ptr [[ULX]], align 8
49155 // SIMD-ONLY0-NEXT:    [[CMP4739:%.*]] = icmp eq i64 [[TMP3464]], [[TMP3465]]
49156 // SIMD-ONLY0-NEXT:    [[CONV4740:%.*]] = zext i1 [[CMP4739]] to i32
49157 // SIMD-ONLY0-NEXT:    [[CONV4741:%.*]] = sext i32 [[CONV4740]] to i64
49158 // SIMD-ONLY0-NEXT:    store i64 [[CONV4741]], ptr [[ULR]], align 8
49159 // SIMD-ONLY0-NEXT:    [[TMP3466:%.*]] = load i64, ptr [[ULR]], align 8
49160 // SIMD-ONLY0-NEXT:    [[TOBOOL4742:%.*]] = icmp ne i64 [[TMP3466]], 0
49161 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4742]], label [[IF_THEN4743:%.*]], label [[IF_END4744:%.*]]
49162 // SIMD-ONLY0:       if.then4743:
49163 // SIMD-ONLY0-NEXT:    [[TMP3467:%.*]] = load i64, ptr [[ULD]], align 8
49164 // SIMD-ONLY0-NEXT:    store i64 [[TMP3467]], ptr [[ULX]], align 8
49165 // SIMD-ONLY0-NEXT:    br label [[IF_END4744]]
49166 // SIMD-ONLY0:       if.end4744:
49167 // SIMD-ONLY0-NEXT:    [[TMP3468:%.*]] = load i64, ptr [[ULX]], align 8
49168 // SIMD-ONLY0-NEXT:    [[TMP3469:%.*]] = load i64, ptr [[ULE]], align 8
49169 // SIMD-ONLY0-NEXT:    [[CMP4745:%.*]] = icmp eq i64 [[TMP3468]], [[TMP3469]]
49170 // SIMD-ONLY0-NEXT:    [[CONV4746:%.*]] = zext i1 [[CMP4745]] to i32
49171 // SIMD-ONLY0-NEXT:    [[CONV4747:%.*]] = sext i32 [[CONV4746]] to i64
49172 // SIMD-ONLY0-NEXT:    store i64 [[CONV4747]], ptr [[ULR]], align 8
49173 // SIMD-ONLY0-NEXT:    [[TMP3470:%.*]] = load i64, ptr [[ULR]], align 8
49174 // SIMD-ONLY0-NEXT:    [[TOBOOL4748:%.*]] = icmp ne i64 [[TMP3470]], 0
49175 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4748]], label [[IF_THEN4749:%.*]], label [[IF_ELSE4750:%.*]]
49176 // SIMD-ONLY0:       if.then4749:
49177 // SIMD-ONLY0-NEXT:    [[TMP3471:%.*]] = load i64, ptr [[ULD]], align 8
49178 // SIMD-ONLY0-NEXT:    store i64 [[TMP3471]], ptr [[ULX]], align 8
49179 // SIMD-ONLY0-NEXT:    br label [[IF_END4751:%.*]]
49180 // SIMD-ONLY0:       if.else4750:
49181 // SIMD-ONLY0-NEXT:    [[TMP3472:%.*]] = load i64, ptr [[ULX]], align 8
49182 // SIMD-ONLY0-NEXT:    store i64 [[TMP3472]], ptr [[ULV]], align 8
49183 // SIMD-ONLY0-NEXT:    br label [[IF_END4751]]
49184 // SIMD-ONLY0:       if.end4751:
49185 // SIMD-ONLY0-NEXT:    [[TMP3473:%.*]] = load i64, ptr [[ULE]], align 8
49186 // SIMD-ONLY0-NEXT:    [[TMP3474:%.*]] = load i64, ptr [[ULX]], align 8
49187 // SIMD-ONLY0-NEXT:    [[CMP4752:%.*]] = icmp eq i64 [[TMP3473]], [[TMP3474]]
49188 // SIMD-ONLY0-NEXT:    [[CONV4753:%.*]] = zext i1 [[CMP4752]] to i32
49189 // SIMD-ONLY0-NEXT:    [[CONV4754:%.*]] = sext i32 [[CONV4753]] to i64
49190 // SIMD-ONLY0-NEXT:    store i64 [[CONV4754]], ptr [[ULR]], align 8
49191 // SIMD-ONLY0-NEXT:    [[TMP3475:%.*]] = load i64, ptr [[ULR]], align 8
49192 // SIMD-ONLY0-NEXT:    [[TOBOOL4755:%.*]] = icmp ne i64 [[TMP3475]], 0
49193 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4755]], label [[IF_THEN4756:%.*]], label [[IF_ELSE4757:%.*]]
49194 // SIMD-ONLY0:       if.then4756:
49195 // SIMD-ONLY0-NEXT:    [[TMP3476:%.*]] = load i64, ptr [[ULD]], align 8
49196 // SIMD-ONLY0-NEXT:    store i64 [[TMP3476]], ptr [[ULX]], align 8
49197 // SIMD-ONLY0-NEXT:    br label [[IF_END4758:%.*]]
49198 // SIMD-ONLY0:       if.else4757:
49199 // SIMD-ONLY0-NEXT:    [[TMP3477:%.*]] = load i64, ptr [[ULX]], align 8
49200 // SIMD-ONLY0-NEXT:    store i64 [[TMP3477]], ptr [[ULV]], align 8
49201 // SIMD-ONLY0-NEXT:    br label [[IF_END4758]]
49202 // SIMD-ONLY0:       if.end4758:
49203 // SIMD-ONLY0-NEXT:    [[TMP3478:%.*]] = load i64, ptr [[ULX]], align 8
49204 // SIMD-ONLY0-NEXT:    store i64 [[TMP3478]], ptr [[ULV]], align 8
49205 // SIMD-ONLY0-NEXT:    [[TMP3479:%.*]] = load i64, ptr [[ULE]], align 8
49206 // SIMD-ONLY0-NEXT:    [[TMP3480:%.*]] = load i64, ptr [[ULX]], align 8
49207 // SIMD-ONLY0-NEXT:    [[CMP4759:%.*]] = icmp ugt i64 [[TMP3479]], [[TMP3480]]
49208 // SIMD-ONLY0-NEXT:    br i1 [[CMP4759]], label [[IF_THEN4761:%.*]], label [[IF_END4762:%.*]]
49209 // SIMD-ONLY0:       if.then4761:
49210 // SIMD-ONLY0-NEXT:    [[TMP3481:%.*]] = load i64, ptr [[ULE]], align 8
49211 // SIMD-ONLY0-NEXT:    store i64 [[TMP3481]], ptr [[ULX]], align 8
49212 // SIMD-ONLY0-NEXT:    br label [[IF_END4762]]
49213 // SIMD-ONLY0:       if.end4762:
49214 // SIMD-ONLY0-NEXT:    [[TMP3482:%.*]] = load i64, ptr [[ULX]], align 8
49215 // SIMD-ONLY0-NEXT:    store i64 [[TMP3482]], ptr [[ULV]], align 8
49216 // SIMD-ONLY0-NEXT:    [[TMP3483:%.*]] = load i64, ptr [[ULX]], align 8
49217 // SIMD-ONLY0-NEXT:    [[TMP3484:%.*]] = load i64, ptr [[ULE]], align 8
49218 // SIMD-ONLY0-NEXT:    [[CMP4763:%.*]] = icmp ugt i64 [[TMP3483]], [[TMP3484]]
49219 // SIMD-ONLY0-NEXT:    br i1 [[CMP4763]], label [[IF_THEN4765:%.*]], label [[IF_END4766:%.*]]
49220 // SIMD-ONLY0:       if.then4765:
49221 // SIMD-ONLY0-NEXT:    [[TMP3485:%.*]] = load i64, ptr [[ULE]], align 8
49222 // SIMD-ONLY0-NEXT:    store i64 [[TMP3485]], ptr [[ULX]], align 8
49223 // SIMD-ONLY0-NEXT:    br label [[IF_END4766]]
49224 // SIMD-ONLY0:       if.end4766:
49225 // SIMD-ONLY0-NEXT:    [[TMP3486:%.*]] = load i64, ptr [[ULX]], align 8
49226 // SIMD-ONLY0-NEXT:    store i64 [[TMP3486]], ptr [[ULV]], align 8
49227 // SIMD-ONLY0-NEXT:    [[TMP3487:%.*]] = load i64, ptr [[ULE]], align 8
49228 // SIMD-ONLY0-NEXT:    [[TMP3488:%.*]] = load i64, ptr [[ULX]], align 8
49229 // SIMD-ONLY0-NEXT:    [[CMP4767:%.*]] = icmp ult i64 [[TMP3487]], [[TMP3488]]
49230 // SIMD-ONLY0-NEXT:    br i1 [[CMP4767]], label [[IF_THEN4769:%.*]], label [[IF_END4770:%.*]]
49231 // SIMD-ONLY0:       if.then4769:
49232 // SIMD-ONLY0-NEXT:    [[TMP3489:%.*]] = load i64, ptr [[ULE]], align 8
49233 // SIMD-ONLY0-NEXT:    store i64 [[TMP3489]], ptr [[ULX]], align 8
49234 // SIMD-ONLY0-NEXT:    br label [[IF_END4770]]
49235 // SIMD-ONLY0:       if.end4770:
49236 // SIMD-ONLY0-NEXT:    [[TMP3490:%.*]] = load i64, ptr [[ULX]], align 8
49237 // SIMD-ONLY0-NEXT:    store i64 [[TMP3490]], ptr [[ULV]], align 8
49238 // SIMD-ONLY0-NEXT:    [[TMP3491:%.*]] = load i64, ptr [[ULX]], align 8
49239 // SIMD-ONLY0-NEXT:    [[TMP3492:%.*]] = load i64, ptr [[ULE]], align 8
49240 // SIMD-ONLY0-NEXT:    [[CMP4771:%.*]] = icmp ult i64 [[TMP3491]], [[TMP3492]]
49241 // SIMD-ONLY0-NEXT:    br i1 [[CMP4771]], label [[IF_THEN4773:%.*]], label [[IF_END4774:%.*]]
49242 // SIMD-ONLY0:       if.then4773:
49243 // SIMD-ONLY0-NEXT:    [[TMP3493:%.*]] = load i64, ptr [[ULE]], align 8
49244 // SIMD-ONLY0-NEXT:    store i64 [[TMP3493]], ptr [[ULX]], align 8
49245 // SIMD-ONLY0-NEXT:    br label [[IF_END4774]]
49246 // SIMD-ONLY0:       if.end4774:
49247 // SIMD-ONLY0-NEXT:    [[TMP3494:%.*]] = load i64, ptr [[ULX]], align 8
49248 // SIMD-ONLY0-NEXT:    store i64 [[TMP3494]], ptr [[ULV]], align 8
49249 // SIMD-ONLY0-NEXT:    [[TMP3495:%.*]] = load i64, ptr [[ULX]], align 8
49250 // SIMD-ONLY0-NEXT:    [[TMP3496:%.*]] = load i64, ptr [[ULE]], align 8
49251 // SIMD-ONLY0-NEXT:    [[CMP4775:%.*]] = icmp eq i64 [[TMP3495]], [[TMP3496]]
49252 // SIMD-ONLY0-NEXT:    br i1 [[CMP4775]], label [[IF_THEN4777:%.*]], label [[IF_END4778:%.*]]
49253 // SIMD-ONLY0:       if.then4777:
49254 // SIMD-ONLY0-NEXT:    [[TMP3497:%.*]] = load i64, ptr [[ULD]], align 8
49255 // SIMD-ONLY0-NEXT:    store i64 [[TMP3497]], ptr [[ULX]], align 8
49256 // SIMD-ONLY0-NEXT:    br label [[IF_END4778]]
49257 // SIMD-ONLY0:       if.end4778:
49258 // SIMD-ONLY0-NEXT:    [[TMP3498:%.*]] = load i64, ptr [[ULX]], align 8
49259 // SIMD-ONLY0-NEXT:    store i64 [[TMP3498]], ptr [[ULV]], align 8
49260 // SIMD-ONLY0-NEXT:    [[TMP3499:%.*]] = load i64, ptr [[ULE]], align 8
49261 // SIMD-ONLY0-NEXT:    [[TMP3500:%.*]] = load i64, ptr [[ULX]], align 8
49262 // SIMD-ONLY0-NEXT:    [[CMP4779:%.*]] = icmp eq i64 [[TMP3499]], [[TMP3500]]
49263 // SIMD-ONLY0-NEXT:    br i1 [[CMP4779]], label [[IF_THEN4781:%.*]], label [[IF_END4782:%.*]]
49264 // SIMD-ONLY0:       if.then4781:
49265 // SIMD-ONLY0-NEXT:    [[TMP3501:%.*]] = load i64, ptr [[ULD]], align 8
49266 // SIMD-ONLY0-NEXT:    store i64 [[TMP3501]], ptr [[ULX]], align 8
49267 // SIMD-ONLY0-NEXT:    br label [[IF_END4782]]
49268 // SIMD-ONLY0:       if.end4782:
49269 // SIMD-ONLY0-NEXT:    [[TMP3502:%.*]] = load i64, ptr [[ULE]], align 8
49270 // SIMD-ONLY0-NEXT:    [[TMP3503:%.*]] = load i64, ptr [[ULX]], align 8
49271 // SIMD-ONLY0-NEXT:    [[CMP4783:%.*]] = icmp ugt i64 [[TMP3502]], [[TMP3503]]
49272 // SIMD-ONLY0-NEXT:    br i1 [[CMP4783]], label [[IF_THEN4785:%.*]], label [[IF_END4786:%.*]]
49273 // SIMD-ONLY0:       if.then4785:
49274 // SIMD-ONLY0-NEXT:    [[TMP3504:%.*]] = load i64, ptr [[ULE]], align 8
49275 // SIMD-ONLY0-NEXT:    store i64 [[TMP3504]], ptr [[ULX]], align 8
49276 // SIMD-ONLY0-NEXT:    br label [[IF_END4786]]
49277 // SIMD-ONLY0:       if.end4786:
49278 // SIMD-ONLY0-NEXT:    [[TMP3505:%.*]] = load i64, ptr [[ULX]], align 8
49279 // SIMD-ONLY0-NEXT:    store i64 [[TMP3505]], ptr [[ULV]], align 8
49280 // SIMD-ONLY0-NEXT:    [[TMP3506:%.*]] = load i64, ptr [[ULX]], align 8
49281 // SIMD-ONLY0-NEXT:    [[TMP3507:%.*]] = load i64, ptr [[ULE]], align 8
49282 // SIMD-ONLY0-NEXT:    [[CMP4787:%.*]] = icmp ugt i64 [[TMP3506]], [[TMP3507]]
49283 // SIMD-ONLY0-NEXT:    br i1 [[CMP4787]], label [[IF_THEN4789:%.*]], label [[IF_END4790:%.*]]
49284 // SIMD-ONLY0:       if.then4789:
49285 // SIMD-ONLY0-NEXT:    [[TMP3508:%.*]] = load i64, ptr [[ULE]], align 8
49286 // SIMD-ONLY0-NEXT:    store i64 [[TMP3508]], ptr [[ULX]], align 8
49287 // SIMD-ONLY0-NEXT:    br label [[IF_END4790]]
49288 // SIMD-ONLY0:       if.end4790:
49289 // SIMD-ONLY0-NEXT:    [[TMP3509:%.*]] = load i64, ptr [[ULX]], align 8
49290 // SIMD-ONLY0-NEXT:    store i64 [[TMP3509]], ptr [[ULV]], align 8
49291 // SIMD-ONLY0-NEXT:    [[TMP3510:%.*]] = load i64, ptr [[ULE]], align 8
49292 // SIMD-ONLY0-NEXT:    [[TMP3511:%.*]] = load i64, ptr [[ULX]], align 8
49293 // SIMD-ONLY0-NEXT:    [[CMP4791:%.*]] = icmp ult i64 [[TMP3510]], [[TMP3511]]
49294 // SIMD-ONLY0-NEXT:    br i1 [[CMP4791]], label [[IF_THEN4793:%.*]], label [[IF_END4794:%.*]]
49295 // SIMD-ONLY0:       if.then4793:
49296 // SIMD-ONLY0-NEXT:    [[TMP3512:%.*]] = load i64, ptr [[ULE]], align 8
49297 // SIMD-ONLY0-NEXT:    store i64 [[TMP3512]], ptr [[ULX]], align 8
49298 // SIMD-ONLY0-NEXT:    br label [[IF_END4794]]
49299 // SIMD-ONLY0:       if.end4794:
49300 // SIMD-ONLY0-NEXT:    [[TMP3513:%.*]] = load i64, ptr [[ULX]], align 8
49301 // SIMD-ONLY0-NEXT:    store i64 [[TMP3513]], ptr [[ULV]], align 8
49302 // SIMD-ONLY0-NEXT:    [[TMP3514:%.*]] = load i64, ptr [[ULX]], align 8
49303 // SIMD-ONLY0-NEXT:    [[TMP3515:%.*]] = load i64, ptr [[ULE]], align 8
49304 // SIMD-ONLY0-NEXT:    [[CMP4795:%.*]] = icmp ult i64 [[TMP3514]], [[TMP3515]]
49305 // SIMD-ONLY0-NEXT:    br i1 [[CMP4795]], label [[IF_THEN4797:%.*]], label [[IF_END4798:%.*]]
49306 // SIMD-ONLY0:       if.then4797:
49307 // SIMD-ONLY0-NEXT:    [[TMP3516:%.*]] = load i64, ptr [[ULE]], align 8
49308 // SIMD-ONLY0-NEXT:    store i64 [[TMP3516]], ptr [[ULX]], align 8
49309 // SIMD-ONLY0-NEXT:    br label [[IF_END4798]]
49310 // SIMD-ONLY0:       if.end4798:
49311 // SIMD-ONLY0-NEXT:    [[TMP3517:%.*]] = load i64, ptr [[ULX]], align 8
49312 // SIMD-ONLY0-NEXT:    store i64 [[TMP3517]], ptr [[ULV]], align 8
49313 // SIMD-ONLY0-NEXT:    [[TMP3518:%.*]] = load i64, ptr [[ULX]], align 8
49314 // SIMD-ONLY0-NEXT:    [[TMP3519:%.*]] = load i64, ptr [[ULE]], align 8
49315 // SIMD-ONLY0-NEXT:    [[CMP4799:%.*]] = icmp eq i64 [[TMP3518]], [[TMP3519]]
49316 // SIMD-ONLY0-NEXT:    br i1 [[CMP4799]], label [[IF_THEN4801:%.*]], label [[IF_END4802:%.*]]
49317 // SIMD-ONLY0:       if.then4801:
49318 // SIMD-ONLY0-NEXT:    [[TMP3520:%.*]] = load i64, ptr [[ULD]], align 8
49319 // SIMD-ONLY0-NEXT:    store i64 [[TMP3520]], ptr [[ULX]], align 8
49320 // SIMD-ONLY0-NEXT:    br label [[IF_END4802]]
49321 // SIMD-ONLY0:       if.end4802:
49322 // SIMD-ONLY0-NEXT:    [[TMP3521:%.*]] = load i64, ptr [[ULX]], align 8
49323 // SIMD-ONLY0-NEXT:    store i64 [[TMP3521]], ptr [[ULV]], align 8
49324 // SIMD-ONLY0-NEXT:    [[TMP3522:%.*]] = load i64, ptr [[ULE]], align 8
49325 // SIMD-ONLY0-NEXT:    [[TMP3523:%.*]] = load i64, ptr [[ULX]], align 8
49326 // SIMD-ONLY0-NEXT:    [[CMP4803:%.*]] = icmp eq i64 [[TMP3522]], [[TMP3523]]
49327 // SIMD-ONLY0-NEXT:    br i1 [[CMP4803]], label [[IF_THEN4805:%.*]], label [[IF_END4806:%.*]]
49328 // SIMD-ONLY0:       if.then4805:
49329 // SIMD-ONLY0-NEXT:    [[TMP3524:%.*]] = load i64, ptr [[ULD]], align 8
49330 // SIMD-ONLY0-NEXT:    store i64 [[TMP3524]], ptr [[ULX]], align 8
49331 // SIMD-ONLY0-NEXT:    br label [[IF_END4806]]
49332 // SIMD-ONLY0:       if.end4806:
49333 // SIMD-ONLY0-NEXT:    [[TMP3525:%.*]] = load i64, ptr [[ULX]], align 8
49334 // SIMD-ONLY0-NEXT:    store i64 [[TMP3525]], ptr [[ULV]], align 8
49335 // SIMD-ONLY0-NEXT:    [[TMP3526:%.*]] = load i64, ptr [[ULX]], align 8
49336 // SIMD-ONLY0-NEXT:    [[TMP3527:%.*]] = load i64, ptr [[ULE]], align 8
49337 // SIMD-ONLY0-NEXT:    [[CMP4807:%.*]] = icmp eq i64 [[TMP3526]], [[TMP3527]]
49338 // SIMD-ONLY0-NEXT:    br i1 [[CMP4807]], label [[IF_THEN4809:%.*]], label [[IF_ELSE4810:%.*]]
49339 // SIMD-ONLY0:       if.then4809:
49340 // SIMD-ONLY0-NEXT:    [[TMP3528:%.*]] = load i64, ptr [[ULD]], align 8
49341 // SIMD-ONLY0-NEXT:    store i64 [[TMP3528]], ptr [[ULX]], align 8
49342 // SIMD-ONLY0-NEXT:    br label [[IF_END4811:%.*]]
49343 // SIMD-ONLY0:       if.else4810:
49344 // SIMD-ONLY0-NEXT:    [[TMP3529:%.*]] = load i64, ptr [[ULX]], align 8
49345 // SIMD-ONLY0-NEXT:    store i64 [[TMP3529]], ptr [[ULV]], align 8
49346 // SIMD-ONLY0-NEXT:    br label [[IF_END4811]]
49347 // SIMD-ONLY0:       if.end4811:
49348 // SIMD-ONLY0-NEXT:    [[TMP3530:%.*]] = load i64, ptr [[ULE]], align 8
49349 // SIMD-ONLY0-NEXT:    [[TMP3531:%.*]] = load i64, ptr [[ULX]], align 8
49350 // SIMD-ONLY0-NEXT:    [[CMP4812:%.*]] = icmp eq i64 [[TMP3530]], [[TMP3531]]
49351 // SIMD-ONLY0-NEXT:    br i1 [[CMP4812]], label [[IF_THEN4814:%.*]], label [[IF_ELSE4815:%.*]]
49352 // SIMD-ONLY0:       if.then4814:
49353 // SIMD-ONLY0-NEXT:    [[TMP3532:%.*]] = load i64, ptr [[ULD]], align 8
49354 // SIMD-ONLY0-NEXT:    store i64 [[TMP3532]], ptr [[ULX]], align 8
49355 // SIMD-ONLY0-NEXT:    br label [[IF_END4816:%.*]]
49356 // SIMD-ONLY0:       if.else4815:
49357 // SIMD-ONLY0-NEXT:    [[TMP3533:%.*]] = load i64, ptr [[ULX]], align 8
49358 // SIMD-ONLY0-NEXT:    store i64 [[TMP3533]], ptr [[ULV]], align 8
49359 // SIMD-ONLY0-NEXT:    br label [[IF_END4816]]
49360 // SIMD-ONLY0:       if.end4816:
49361 // SIMD-ONLY0-NEXT:    [[TMP3534:%.*]] = load i64, ptr [[ULX]], align 8
49362 // SIMD-ONLY0-NEXT:    [[TMP3535:%.*]] = load i64, ptr [[ULE]], align 8
49363 // SIMD-ONLY0-NEXT:    [[CMP4817:%.*]] = icmp eq i64 [[TMP3534]], [[TMP3535]]
49364 // SIMD-ONLY0-NEXT:    [[CONV4818:%.*]] = zext i1 [[CMP4817]] to i32
49365 // SIMD-ONLY0-NEXT:    [[CONV4819:%.*]] = sext i32 [[CONV4818]] to i64
49366 // SIMD-ONLY0-NEXT:    store i64 [[CONV4819]], ptr [[ULR]], align 8
49367 // SIMD-ONLY0-NEXT:    [[TMP3536:%.*]] = load i64, ptr [[ULR]], align 8
49368 // SIMD-ONLY0-NEXT:    [[TOBOOL4820:%.*]] = icmp ne i64 [[TMP3536]], 0
49369 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4820]], label [[IF_THEN4821:%.*]], label [[IF_END4822:%.*]]
49370 // SIMD-ONLY0:       if.then4821:
49371 // SIMD-ONLY0-NEXT:    [[TMP3537:%.*]] = load i64, ptr [[ULD]], align 8
49372 // SIMD-ONLY0-NEXT:    store i64 [[TMP3537]], ptr [[ULX]], align 8
49373 // SIMD-ONLY0-NEXT:    br label [[IF_END4822]]
49374 // SIMD-ONLY0:       if.end4822:
49375 // SIMD-ONLY0-NEXT:    [[TMP3538:%.*]] = load i64, ptr [[ULE]], align 8
49376 // SIMD-ONLY0-NEXT:    [[TMP3539:%.*]] = load i64, ptr [[ULX]], align 8
49377 // SIMD-ONLY0-NEXT:    [[CMP4823:%.*]] = icmp eq i64 [[TMP3538]], [[TMP3539]]
49378 // SIMD-ONLY0-NEXT:    [[CONV4824:%.*]] = zext i1 [[CMP4823]] to i32
49379 // SIMD-ONLY0-NEXT:    [[CONV4825:%.*]] = sext i32 [[CONV4824]] to i64
49380 // SIMD-ONLY0-NEXT:    store i64 [[CONV4825]], ptr [[ULR]], align 8
49381 // SIMD-ONLY0-NEXT:    [[TMP3540:%.*]] = load i64, ptr [[ULR]], align 8
49382 // SIMD-ONLY0-NEXT:    [[TOBOOL4826:%.*]] = icmp ne i64 [[TMP3540]], 0
49383 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4826]], label [[IF_THEN4827:%.*]], label [[IF_END4828:%.*]]
49384 // SIMD-ONLY0:       if.then4827:
49385 // SIMD-ONLY0-NEXT:    [[TMP3541:%.*]] = load i64, ptr [[ULD]], align 8
49386 // SIMD-ONLY0-NEXT:    store i64 [[TMP3541]], ptr [[ULX]], align 8
49387 // SIMD-ONLY0-NEXT:    br label [[IF_END4828]]
49388 // SIMD-ONLY0:       if.end4828:
49389 // SIMD-ONLY0-NEXT:    [[TMP3542:%.*]] = load i64, ptr [[ULX]], align 8
49390 // SIMD-ONLY0-NEXT:    [[TMP3543:%.*]] = load i64, ptr [[ULE]], align 8
49391 // SIMD-ONLY0-NEXT:    [[CMP4829:%.*]] = icmp eq i64 [[TMP3542]], [[TMP3543]]
49392 // SIMD-ONLY0-NEXT:    [[CONV4830:%.*]] = zext i1 [[CMP4829]] to i32
49393 // SIMD-ONLY0-NEXT:    [[CONV4831:%.*]] = sext i32 [[CONV4830]] to i64
49394 // SIMD-ONLY0-NEXT:    store i64 [[CONV4831]], ptr [[ULR]], align 8
49395 // SIMD-ONLY0-NEXT:    [[TMP3544:%.*]] = load i64, ptr [[ULR]], align 8
49396 // SIMD-ONLY0-NEXT:    [[TOBOOL4832:%.*]] = icmp ne i64 [[TMP3544]], 0
49397 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4832]], label [[IF_THEN4833:%.*]], label [[IF_ELSE4834:%.*]]
49398 // SIMD-ONLY0:       if.then4833:
49399 // SIMD-ONLY0-NEXT:    [[TMP3545:%.*]] = load i64, ptr [[ULD]], align 8
49400 // SIMD-ONLY0-NEXT:    store i64 [[TMP3545]], ptr [[ULX]], align 8
49401 // SIMD-ONLY0-NEXT:    br label [[IF_END4835:%.*]]
49402 // SIMD-ONLY0:       if.else4834:
49403 // SIMD-ONLY0-NEXT:    [[TMP3546:%.*]] = load i64, ptr [[ULX]], align 8
49404 // SIMD-ONLY0-NEXT:    store i64 [[TMP3546]], ptr [[ULV]], align 8
49405 // SIMD-ONLY0-NEXT:    br label [[IF_END4835]]
49406 // SIMD-ONLY0:       if.end4835:
49407 // SIMD-ONLY0-NEXT:    [[TMP3547:%.*]] = load i64, ptr [[ULE]], align 8
49408 // SIMD-ONLY0-NEXT:    [[TMP3548:%.*]] = load i64, ptr [[ULX]], align 8
49409 // SIMD-ONLY0-NEXT:    [[CMP4836:%.*]] = icmp eq i64 [[TMP3547]], [[TMP3548]]
49410 // SIMD-ONLY0-NEXT:    [[CONV4837:%.*]] = zext i1 [[CMP4836]] to i32
49411 // SIMD-ONLY0-NEXT:    [[CONV4838:%.*]] = sext i32 [[CONV4837]] to i64
49412 // SIMD-ONLY0-NEXT:    store i64 [[CONV4838]], ptr [[ULR]], align 8
49413 // SIMD-ONLY0-NEXT:    [[TMP3549:%.*]] = load i64, ptr [[ULR]], align 8
49414 // SIMD-ONLY0-NEXT:    [[TOBOOL4839:%.*]] = icmp ne i64 [[TMP3549]], 0
49415 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4839]], label [[IF_THEN4840:%.*]], label [[IF_ELSE4841:%.*]]
49416 // SIMD-ONLY0:       if.then4840:
49417 // SIMD-ONLY0-NEXT:    [[TMP3550:%.*]] = load i64, ptr [[ULD]], align 8
49418 // SIMD-ONLY0-NEXT:    store i64 [[TMP3550]], ptr [[ULX]], align 8
49419 // SIMD-ONLY0-NEXT:    br label [[IF_END4842:%.*]]
49420 // SIMD-ONLY0:       if.else4841:
49421 // SIMD-ONLY0-NEXT:    [[TMP3551:%.*]] = load i64, ptr [[ULX]], align 8
49422 // SIMD-ONLY0-NEXT:    store i64 [[TMP3551]], ptr [[ULV]], align 8
49423 // SIMD-ONLY0-NEXT:    br label [[IF_END4842]]
49424 // SIMD-ONLY0:       if.end4842:
49425 // SIMD-ONLY0-NEXT:    [[TMP3552:%.*]] = load i64, ptr [[LLX]], align 8
49426 // SIMD-ONLY0-NEXT:    store i64 [[TMP3552]], ptr [[LLV]], align 8
49427 // SIMD-ONLY0-NEXT:    [[TMP3553:%.*]] = load i64, ptr [[LLE]], align 8
49428 // SIMD-ONLY0-NEXT:    [[TMP3554:%.*]] = load i64, ptr [[LLX]], align 8
49429 // SIMD-ONLY0-NEXT:    [[CMP4843:%.*]] = icmp sgt i64 [[TMP3553]], [[TMP3554]]
49430 // SIMD-ONLY0-NEXT:    br i1 [[CMP4843]], label [[IF_THEN4845:%.*]], label [[IF_END4846:%.*]]
49431 // SIMD-ONLY0:       if.then4845:
49432 // SIMD-ONLY0-NEXT:    [[TMP3555:%.*]] = load i64, ptr [[LLE]], align 8
49433 // SIMD-ONLY0-NEXT:    store i64 [[TMP3555]], ptr [[LLX]], align 8
49434 // SIMD-ONLY0-NEXT:    br label [[IF_END4846]]
49435 // SIMD-ONLY0:       if.end4846:
49436 // SIMD-ONLY0-NEXT:    [[TMP3556:%.*]] = load i64, ptr [[LLX]], align 8
49437 // SIMD-ONLY0-NEXT:    store i64 [[TMP3556]], ptr [[LLV]], align 8
49438 // SIMD-ONLY0-NEXT:    [[TMP3557:%.*]] = load i64, ptr [[LLX]], align 8
49439 // SIMD-ONLY0-NEXT:    [[TMP3558:%.*]] = load i64, ptr [[LLE]], align 8
49440 // SIMD-ONLY0-NEXT:    [[CMP4847:%.*]] = icmp sgt i64 [[TMP3557]], [[TMP3558]]
49441 // SIMD-ONLY0-NEXT:    br i1 [[CMP4847]], label [[IF_THEN4849:%.*]], label [[IF_END4850:%.*]]
49442 // SIMD-ONLY0:       if.then4849:
49443 // SIMD-ONLY0-NEXT:    [[TMP3559:%.*]] = load i64, ptr [[LLE]], align 8
49444 // SIMD-ONLY0-NEXT:    store i64 [[TMP3559]], ptr [[LLX]], align 8
49445 // SIMD-ONLY0-NEXT:    br label [[IF_END4850]]
49446 // SIMD-ONLY0:       if.end4850:
49447 // SIMD-ONLY0-NEXT:    [[TMP3560:%.*]] = load i64, ptr [[LLX]], align 8
49448 // SIMD-ONLY0-NEXT:    store i64 [[TMP3560]], ptr [[LLV]], align 8
49449 // SIMD-ONLY0-NEXT:    [[TMP3561:%.*]] = load i64, ptr [[LLE]], align 8
49450 // SIMD-ONLY0-NEXT:    [[TMP3562:%.*]] = load i64, ptr [[LLX]], align 8
49451 // SIMD-ONLY0-NEXT:    [[CMP4851:%.*]] = icmp slt i64 [[TMP3561]], [[TMP3562]]
49452 // SIMD-ONLY0-NEXT:    br i1 [[CMP4851]], label [[IF_THEN4853:%.*]], label [[IF_END4854:%.*]]
49453 // SIMD-ONLY0:       if.then4853:
49454 // SIMD-ONLY0-NEXT:    [[TMP3563:%.*]] = load i64, ptr [[LLE]], align 8
49455 // SIMD-ONLY0-NEXT:    store i64 [[TMP3563]], ptr [[LLX]], align 8
49456 // SIMD-ONLY0-NEXT:    br label [[IF_END4854]]
49457 // SIMD-ONLY0:       if.end4854:
49458 // SIMD-ONLY0-NEXT:    [[TMP3564:%.*]] = load i64, ptr [[LLX]], align 8
49459 // SIMD-ONLY0-NEXT:    store i64 [[TMP3564]], ptr [[LLV]], align 8
49460 // SIMD-ONLY0-NEXT:    [[TMP3565:%.*]] = load i64, ptr [[LLX]], align 8
49461 // SIMD-ONLY0-NEXT:    [[TMP3566:%.*]] = load i64, ptr [[LLE]], align 8
49462 // SIMD-ONLY0-NEXT:    [[CMP4855:%.*]] = icmp slt i64 [[TMP3565]], [[TMP3566]]
49463 // SIMD-ONLY0-NEXT:    br i1 [[CMP4855]], label [[IF_THEN4857:%.*]], label [[IF_END4858:%.*]]
49464 // SIMD-ONLY0:       if.then4857:
49465 // SIMD-ONLY0-NEXT:    [[TMP3567:%.*]] = load i64, ptr [[LLE]], align 8
49466 // SIMD-ONLY0-NEXT:    store i64 [[TMP3567]], ptr [[LLX]], align 8
49467 // SIMD-ONLY0-NEXT:    br label [[IF_END4858]]
49468 // SIMD-ONLY0:       if.end4858:
49469 // SIMD-ONLY0-NEXT:    [[TMP3568:%.*]] = load i64, ptr [[LLX]], align 8
49470 // SIMD-ONLY0-NEXT:    store i64 [[TMP3568]], ptr [[LLV]], align 8
49471 // SIMD-ONLY0-NEXT:    [[TMP3569:%.*]] = load i64, ptr [[LLX]], align 8
49472 // SIMD-ONLY0-NEXT:    [[TMP3570:%.*]] = load i64, ptr [[LLE]], align 8
49473 // SIMD-ONLY0-NEXT:    [[CMP4859:%.*]] = icmp eq i64 [[TMP3569]], [[TMP3570]]
49474 // SIMD-ONLY0-NEXT:    br i1 [[CMP4859]], label [[IF_THEN4861:%.*]], label [[IF_END4862:%.*]]
49475 // SIMD-ONLY0:       if.then4861:
49476 // SIMD-ONLY0-NEXT:    [[TMP3571:%.*]] = load i64, ptr [[LLD]], align 8
49477 // SIMD-ONLY0-NEXT:    store i64 [[TMP3571]], ptr [[LLX]], align 8
49478 // SIMD-ONLY0-NEXT:    br label [[IF_END4862]]
49479 // SIMD-ONLY0:       if.end4862:
49480 // SIMD-ONLY0-NEXT:    [[TMP3572:%.*]] = load i64, ptr [[LLX]], align 8
49481 // SIMD-ONLY0-NEXT:    store i64 [[TMP3572]], ptr [[LLV]], align 8
49482 // SIMD-ONLY0-NEXT:    [[TMP3573:%.*]] = load i64, ptr [[LLE]], align 8
49483 // SIMD-ONLY0-NEXT:    [[TMP3574:%.*]] = load i64, ptr [[LLX]], align 8
49484 // SIMD-ONLY0-NEXT:    [[CMP4863:%.*]] = icmp eq i64 [[TMP3573]], [[TMP3574]]
49485 // SIMD-ONLY0-NEXT:    br i1 [[CMP4863]], label [[IF_THEN4865:%.*]], label [[IF_END4866:%.*]]
49486 // SIMD-ONLY0:       if.then4865:
49487 // SIMD-ONLY0-NEXT:    [[TMP3575:%.*]] = load i64, ptr [[LLD]], align 8
49488 // SIMD-ONLY0-NEXT:    store i64 [[TMP3575]], ptr [[LLX]], align 8
49489 // SIMD-ONLY0-NEXT:    br label [[IF_END4866]]
49490 // SIMD-ONLY0:       if.end4866:
49491 // SIMD-ONLY0-NEXT:    [[TMP3576:%.*]] = load i64, ptr [[LLE]], align 8
49492 // SIMD-ONLY0-NEXT:    [[TMP3577:%.*]] = load i64, ptr [[LLX]], align 8
49493 // SIMD-ONLY0-NEXT:    [[CMP4867:%.*]] = icmp sgt i64 [[TMP3576]], [[TMP3577]]
49494 // SIMD-ONLY0-NEXT:    br i1 [[CMP4867]], label [[IF_THEN4869:%.*]], label [[IF_END4870:%.*]]
49495 // SIMD-ONLY0:       if.then4869:
49496 // SIMD-ONLY0-NEXT:    [[TMP3578:%.*]] = load i64, ptr [[LLE]], align 8
49497 // SIMD-ONLY0-NEXT:    store i64 [[TMP3578]], ptr [[LLX]], align 8
49498 // SIMD-ONLY0-NEXT:    br label [[IF_END4870]]
49499 // SIMD-ONLY0:       if.end4870:
49500 // SIMD-ONLY0-NEXT:    [[TMP3579:%.*]] = load i64, ptr [[LLX]], align 8
49501 // SIMD-ONLY0-NEXT:    store i64 [[TMP3579]], ptr [[LLV]], align 8
49502 // SIMD-ONLY0-NEXT:    [[TMP3580:%.*]] = load i64, ptr [[LLX]], align 8
49503 // SIMD-ONLY0-NEXT:    [[TMP3581:%.*]] = load i64, ptr [[LLE]], align 8
49504 // SIMD-ONLY0-NEXT:    [[CMP4871:%.*]] = icmp sgt i64 [[TMP3580]], [[TMP3581]]
49505 // SIMD-ONLY0-NEXT:    br i1 [[CMP4871]], label [[IF_THEN4873:%.*]], label [[IF_END4874:%.*]]
49506 // SIMD-ONLY0:       if.then4873:
49507 // SIMD-ONLY0-NEXT:    [[TMP3582:%.*]] = load i64, ptr [[LLE]], align 8
49508 // SIMD-ONLY0-NEXT:    store i64 [[TMP3582]], ptr [[LLX]], align 8
49509 // SIMD-ONLY0-NEXT:    br label [[IF_END4874]]
49510 // SIMD-ONLY0:       if.end4874:
49511 // SIMD-ONLY0-NEXT:    [[TMP3583:%.*]] = load i64, ptr [[LLX]], align 8
49512 // SIMD-ONLY0-NEXT:    store i64 [[TMP3583]], ptr [[LLV]], align 8
49513 // SIMD-ONLY0-NEXT:    [[TMP3584:%.*]] = load i64, ptr [[LLE]], align 8
49514 // SIMD-ONLY0-NEXT:    [[TMP3585:%.*]] = load i64, ptr [[LLX]], align 8
49515 // SIMD-ONLY0-NEXT:    [[CMP4875:%.*]] = icmp slt i64 [[TMP3584]], [[TMP3585]]
49516 // SIMD-ONLY0-NEXT:    br i1 [[CMP4875]], label [[IF_THEN4877:%.*]], label [[IF_END4878:%.*]]
49517 // SIMD-ONLY0:       if.then4877:
49518 // SIMD-ONLY0-NEXT:    [[TMP3586:%.*]] = load i64, ptr [[LLE]], align 8
49519 // SIMD-ONLY0-NEXT:    store i64 [[TMP3586]], ptr [[LLX]], align 8
49520 // SIMD-ONLY0-NEXT:    br label [[IF_END4878]]
49521 // SIMD-ONLY0:       if.end4878:
49522 // SIMD-ONLY0-NEXT:    [[TMP3587:%.*]] = load i64, ptr [[LLX]], align 8
49523 // SIMD-ONLY0-NEXT:    store i64 [[TMP3587]], ptr [[LLV]], align 8
49524 // SIMD-ONLY0-NEXT:    [[TMP3588:%.*]] = load i64, ptr [[LLX]], align 8
49525 // SIMD-ONLY0-NEXT:    [[TMP3589:%.*]] = load i64, ptr [[LLE]], align 8
49526 // SIMD-ONLY0-NEXT:    [[CMP4879:%.*]] = icmp slt i64 [[TMP3588]], [[TMP3589]]
49527 // SIMD-ONLY0-NEXT:    br i1 [[CMP4879]], label [[IF_THEN4881:%.*]], label [[IF_END4882:%.*]]
49528 // SIMD-ONLY0:       if.then4881:
49529 // SIMD-ONLY0-NEXT:    [[TMP3590:%.*]] = load i64, ptr [[LLE]], align 8
49530 // SIMD-ONLY0-NEXT:    store i64 [[TMP3590]], ptr [[LLX]], align 8
49531 // SIMD-ONLY0-NEXT:    br label [[IF_END4882]]
49532 // SIMD-ONLY0:       if.end4882:
49533 // SIMD-ONLY0-NEXT:    [[TMP3591:%.*]] = load i64, ptr [[LLX]], align 8
49534 // SIMD-ONLY0-NEXT:    store i64 [[TMP3591]], ptr [[LLV]], align 8
49535 // SIMD-ONLY0-NEXT:    [[TMP3592:%.*]] = load i64, ptr [[LLX]], align 8
49536 // SIMD-ONLY0-NEXT:    [[TMP3593:%.*]] = load i64, ptr [[LLE]], align 8
49537 // SIMD-ONLY0-NEXT:    [[CMP4883:%.*]] = icmp eq i64 [[TMP3592]], [[TMP3593]]
49538 // SIMD-ONLY0-NEXT:    br i1 [[CMP4883]], label [[IF_THEN4885:%.*]], label [[IF_END4886:%.*]]
49539 // SIMD-ONLY0:       if.then4885:
49540 // SIMD-ONLY0-NEXT:    [[TMP3594:%.*]] = load i64, ptr [[LLD]], align 8
49541 // SIMD-ONLY0-NEXT:    store i64 [[TMP3594]], ptr [[LLX]], align 8
49542 // SIMD-ONLY0-NEXT:    br label [[IF_END4886]]
49543 // SIMD-ONLY0:       if.end4886:
49544 // SIMD-ONLY0-NEXT:    [[TMP3595:%.*]] = load i64, ptr [[LLX]], align 8
49545 // SIMD-ONLY0-NEXT:    store i64 [[TMP3595]], ptr [[LLV]], align 8
49546 // SIMD-ONLY0-NEXT:    [[TMP3596:%.*]] = load i64, ptr [[LLE]], align 8
49547 // SIMD-ONLY0-NEXT:    [[TMP3597:%.*]] = load i64, ptr [[LLX]], align 8
49548 // SIMD-ONLY0-NEXT:    [[CMP4887:%.*]] = icmp eq i64 [[TMP3596]], [[TMP3597]]
49549 // SIMD-ONLY0-NEXT:    br i1 [[CMP4887]], label [[IF_THEN4889:%.*]], label [[IF_END4890:%.*]]
49550 // SIMD-ONLY0:       if.then4889:
49551 // SIMD-ONLY0-NEXT:    [[TMP3598:%.*]] = load i64, ptr [[LLD]], align 8
49552 // SIMD-ONLY0-NEXT:    store i64 [[TMP3598]], ptr [[LLX]], align 8
49553 // SIMD-ONLY0-NEXT:    br label [[IF_END4890]]
49554 // SIMD-ONLY0:       if.end4890:
49555 // SIMD-ONLY0-NEXT:    [[TMP3599:%.*]] = load i64, ptr [[LLX]], align 8
49556 // SIMD-ONLY0-NEXT:    store i64 [[TMP3599]], ptr [[LLV]], align 8
49557 // SIMD-ONLY0-NEXT:    [[TMP3600:%.*]] = load i64, ptr [[LLX]], align 8
49558 // SIMD-ONLY0-NEXT:    [[TMP3601:%.*]] = load i64, ptr [[LLE]], align 8
49559 // SIMD-ONLY0-NEXT:    [[CMP4891:%.*]] = icmp eq i64 [[TMP3600]], [[TMP3601]]
49560 // SIMD-ONLY0-NEXT:    br i1 [[CMP4891]], label [[IF_THEN4893:%.*]], label [[IF_ELSE4894:%.*]]
49561 // SIMD-ONLY0:       if.then4893:
49562 // SIMD-ONLY0-NEXT:    [[TMP3602:%.*]] = load i64, ptr [[LLD]], align 8
49563 // SIMD-ONLY0-NEXT:    store i64 [[TMP3602]], ptr [[LLX]], align 8
49564 // SIMD-ONLY0-NEXT:    br label [[IF_END4895:%.*]]
49565 // SIMD-ONLY0:       if.else4894:
49566 // SIMD-ONLY0-NEXT:    [[TMP3603:%.*]] = load i64, ptr [[LLX]], align 8
49567 // SIMD-ONLY0-NEXT:    store i64 [[TMP3603]], ptr [[LLV]], align 8
49568 // SIMD-ONLY0-NEXT:    br label [[IF_END4895]]
49569 // SIMD-ONLY0:       if.end4895:
49570 // SIMD-ONLY0-NEXT:    [[TMP3604:%.*]] = load i64, ptr [[LLE]], align 8
49571 // SIMD-ONLY0-NEXT:    [[TMP3605:%.*]] = load i64, ptr [[LLX]], align 8
49572 // SIMD-ONLY0-NEXT:    [[CMP4896:%.*]] = icmp eq i64 [[TMP3604]], [[TMP3605]]
49573 // SIMD-ONLY0-NEXT:    br i1 [[CMP4896]], label [[IF_THEN4898:%.*]], label [[IF_ELSE4899:%.*]]
49574 // SIMD-ONLY0:       if.then4898:
49575 // SIMD-ONLY0-NEXT:    [[TMP3606:%.*]] = load i64, ptr [[LLD]], align 8
49576 // SIMD-ONLY0-NEXT:    store i64 [[TMP3606]], ptr [[LLX]], align 8
49577 // SIMD-ONLY0-NEXT:    br label [[IF_END4900:%.*]]
49578 // SIMD-ONLY0:       if.else4899:
49579 // SIMD-ONLY0-NEXT:    [[TMP3607:%.*]] = load i64, ptr [[LLX]], align 8
49580 // SIMD-ONLY0-NEXT:    store i64 [[TMP3607]], ptr [[LLV]], align 8
49581 // SIMD-ONLY0-NEXT:    br label [[IF_END4900]]
49582 // SIMD-ONLY0:       if.end4900:
49583 // SIMD-ONLY0-NEXT:    [[TMP3608:%.*]] = load i64, ptr [[LLX]], align 8
49584 // SIMD-ONLY0-NEXT:    [[TMP3609:%.*]] = load i64, ptr [[LLE]], align 8
49585 // SIMD-ONLY0-NEXT:    [[CMP4901:%.*]] = icmp eq i64 [[TMP3608]], [[TMP3609]]
49586 // SIMD-ONLY0-NEXT:    [[CONV4902:%.*]] = zext i1 [[CMP4901]] to i32
49587 // SIMD-ONLY0-NEXT:    [[CONV4903:%.*]] = sext i32 [[CONV4902]] to i64
49588 // SIMD-ONLY0-NEXT:    store i64 [[CONV4903]], ptr [[LLR]], align 8
49589 // SIMD-ONLY0-NEXT:    [[TMP3610:%.*]] = load i64, ptr [[LLR]], align 8
49590 // SIMD-ONLY0-NEXT:    [[TOBOOL4904:%.*]] = icmp ne i64 [[TMP3610]], 0
49591 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4904]], label [[IF_THEN4905:%.*]], label [[IF_END4906:%.*]]
49592 // SIMD-ONLY0:       if.then4905:
49593 // SIMD-ONLY0-NEXT:    [[TMP3611:%.*]] = load i64, ptr [[LLD]], align 8
49594 // SIMD-ONLY0-NEXT:    store i64 [[TMP3611]], ptr [[LLX]], align 8
49595 // SIMD-ONLY0-NEXT:    br label [[IF_END4906]]
49596 // SIMD-ONLY0:       if.end4906:
49597 // SIMD-ONLY0-NEXT:    [[TMP3612:%.*]] = load i64, ptr [[LLE]], align 8
49598 // SIMD-ONLY0-NEXT:    [[TMP3613:%.*]] = load i64, ptr [[LLX]], align 8
49599 // SIMD-ONLY0-NEXT:    [[CMP4907:%.*]] = icmp eq i64 [[TMP3612]], [[TMP3613]]
49600 // SIMD-ONLY0-NEXT:    [[CONV4908:%.*]] = zext i1 [[CMP4907]] to i32
49601 // SIMD-ONLY0-NEXT:    [[CONV4909:%.*]] = sext i32 [[CONV4908]] to i64
49602 // SIMD-ONLY0-NEXT:    store i64 [[CONV4909]], ptr [[LLR]], align 8
49603 // SIMD-ONLY0-NEXT:    [[TMP3614:%.*]] = load i64, ptr [[LLR]], align 8
49604 // SIMD-ONLY0-NEXT:    [[TOBOOL4910:%.*]] = icmp ne i64 [[TMP3614]], 0
49605 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4910]], label [[IF_THEN4911:%.*]], label [[IF_END4912:%.*]]
49606 // SIMD-ONLY0:       if.then4911:
49607 // SIMD-ONLY0-NEXT:    [[TMP3615:%.*]] = load i64, ptr [[LLD]], align 8
49608 // SIMD-ONLY0-NEXT:    store i64 [[TMP3615]], ptr [[LLX]], align 8
49609 // SIMD-ONLY0-NEXT:    br label [[IF_END4912]]
49610 // SIMD-ONLY0:       if.end4912:
49611 // SIMD-ONLY0-NEXT:    [[TMP3616:%.*]] = load i64, ptr [[LLX]], align 8
49612 // SIMD-ONLY0-NEXT:    [[TMP3617:%.*]] = load i64, ptr [[LLE]], align 8
49613 // SIMD-ONLY0-NEXT:    [[CMP4913:%.*]] = icmp eq i64 [[TMP3616]], [[TMP3617]]
49614 // SIMD-ONLY0-NEXT:    [[CONV4914:%.*]] = zext i1 [[CMP4913]] to i32
49615 // SIMD-ONLY0-NEXT:    [[CONV4915:%.*]] = sext i32 [[CONV4914]] to i64
49616 // SIMD-ONLY0-NEXT:    store i64 [[CONV4915]], ptr [[LLR]], align 8
49617 // SIMD-ONLY0-NEXT:    [[TMP3618:%.*]] = load i64, ptr [[LLR]], align 8
49618 // SIMD-ONLY0-NEXT:    [[TOBOOL4916:%.*]] = icmp ne i64 [[TMP3618]], 0
49619 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4916]], label [[IF_THEN4917:%.*]], label [[IF_ELSE4918:%.*]]
49620 // SIMD-ONLY0:       if.then4917:
49621 // SIMD-ONLY0-NEXT:    [[TMP3619:%.*]] = load i64, ptr [[LLD]], align 8
49622 // SIMD-ONLY0-NEXT:    store i64 [[TMP3619]], ptr [[LLX]], align 8
49623 // SIMD-ONLY0-NEXT:    br label [[IF_END4919:%.*]]
49624 // SIMD-ONLY0:       if.else4918:
49625 // SIMD-ONLY0-NEXT:    [[TMP3620:%.*]] = load i64, ptr [[LLX]], align 8
49626 // SIMD-ONLY0-NEXT:    store i64 [[TMP3620]], ptr [[LLV]], align 8
49627 // SIMD-ONLY0-NEXT:    br label [[IF_END4919]]
49628 // SIMD-ONLY0:       if.end4919:
49629 // SIMD-ONLY0-NEXT:    [[TMP3621:%.*]] = load i64, ptr [[LLE]], align 8
49630 // SIMD-ONLY0-NEXT:    [[TMP3622:%.*]] = load i64, ptr [[LLX]], align 8
49631 // SIMD-ONLY0-NEXT:    [[CMP4920:%.*]] = icmp eq i64 [[TMP3621]], [[TMP3622]]
49632 // SIMD-ONLY0-NEXT:    [[CONV4921:%.*]] = zext i1 [[CMP4920]] to i32
49633 // SIMD-ONLY0-NEXT:    [[CONV4922:%.*]] = sext i32 [[CONV4921]] to i64
49634 // SIMD-ONLY0-NEXT:    store i64 [[CONV4922]], ptr [[LLR]], align 8
49635 // SIMD-ONLY0-NEXT:    [[TMP3623:%.*]] = load i64, ptr [[LLR]], align 8
49636 // SIMD-ONLY0-NEXT:    [[TOBOOL4923:%.*]] = icmp ne i64 [[TMP3623]], 0
49637 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4923]], label [[IF_THEN4924:%.*]], label [[IF_ELSE4925:%.*]]
49638 // SIMD-ONLY0:       if.then4924:
49639 // SIMD-ONLY0-NEXT:    [[TMP3624:%.*]] = load i64, ptr [[LLD]], align 8
49640 // SIMD-ONLY0-NEXT:    store i64 [[TMP3624]], ptr [[LLX]], align 8
49641 // SIMD-ONLY0-NEXT:    br label [[IF_END4926:%.*]]
49642 // SIMD-ONLY0:       if.else4925:
49643 // SIMD-ONLY0-NEXT:    [[TMP3625:%.*]] = load i64, ptr [[LLX]], align 8
49644 // SIMD-ONLY0-NEXT:    store i64 [[TMP3625]], ptr [[LLV]], align 8
49645 // SIMD-ONLY0-NEXT:    br label [[IF_END4926]]
49646 // SIMD-ONLY0:       if.end4926:
49647 // SIMD-ONLY0-NEXT:    [[TMP3626:%.*]] = load i64, ptr [[LLX]], align 8
49648 // SIMD-ONLY0-NEXT:    store i64 [[TMP3626]], ptr [[LLV]], align 8
49649 // SIMD-ONLY0-NEXT:    [[TMP3627:%.*]] = load i64, ptr [[LLE]], align 8
49650 // SIMD-ONLY0-NEXT:    [[TMP3628:%.*]] = load i64, ptr [[LLX]], align 8
49651 // SIMD-ONLY0-NEXT:    [[CMP4927:%.*]] = icmp sgt i64 [[TMP3627]], [[TMP3628]]
49652 // SIMD-ONLY0-NEXT:    br i1 [[CMP4927]], label [[IF_THEN4929:%.*]], label [[IF_END4930:%.*]]
49653 // SIMD-ONLY0:       if.then4929:
49654 // SIMD-ONLY0-NEXT:    [[TMP3629:%.*]] = load i64, ptr [[LLE]], align 8
49655 // SIMD-ONLY0-NEXT:    store i64 [[TMP3629]], ptr [[LLX]], align 8
49656 // SIMD-ONLY0-NEXT:    br label [[IF_END4930]]
49657 // SIMD-ONLY0:       if.end4930:
49658 // SIMD-ONLY0-NEXT:    [[TMP3630:%.*]] = load i64, ptr [[LLX]], align 8
49659 // SIMD-ONLY0-NEXT:    store i64 [[TMP3630]], ptr [[LLV]], align 8
49660 // SIMD-ONLY0-NEXT:    [[TMP3631:%.*]] = load i64, ptr [[LLX]], align 8
49661 // SIMD-ONLY0-NEXT:    [[TMP3632:%.*]] = load i64, ptr [[LLE]], align 8
49662 // SIMD-ONLY0-NEXT:    [[CMP4931:%.*]] = icmp sgt i64 [[TMP3631]], [[TMP3632]]
49663 // SIMD-ONLY0-NEXT:    br i1 [[CMP4931]], label [[IF_THEN4933:%.*]], label [[IF_END4934:%.*]]
49664 // SIMD-ONLY0:       if.then4933:
49665 // SIMD-ONLY0-NEXT:    [[TMP3633:%.*]] = load i64, ptr [[LLE]], align 8
49666 // SIMD-ONLY0-NEXT:    store i64 [[TMP3633]], ptr [[LLX]], align 8
49667 // SIMD-ONLY0-NEXT:    br label [[IF_END4934]]
49668 // SIMD-ONLY0:       if.end4934:
49669 // SIMD-ONLY0-NEXT:    [[TMP3634:%.*]] = load i64, ptr [[LLX]], align 8
49670 // SIMD-ONLY0-NEXT:    store i64 [[TMP3634]], ptr [[LLV]], align 8
49671 // SIMD-ONLY0-NEXT:    [[TMP3635:%.*]] = load i64, ptr [[LLE]], align 8
49672 // SIMD-ONLY0-NEXT:    [[TMP3636:%.*]] = load i64, ptr [[LLX]], align 8
49673 // SIMD-ONLY0-NEXT:    [[CMP4935:%.*]] = icmp slt i64 [[TMP3635]], [[TMP3636]]
49674 // SIMD-ONLY0-NEXT:    br i1 [[CMP4935]], label [[IF_THEN4937:%.*]], label [[IF_END4938:%.*]]
49675 // SIMD-ONLY0:       if.then4937:
49676 // SIMD-ONLY0-NEXT:    [[TMP3637:%.*]] = load i64, ptr [[LLE]], align 8
49677 // SIMD-ONLY0-NEXT:    store i64 [[TMP3637]], ptr [[LLX]], align 8
49678 // SIMD-ONLY0-NEXT:    br label [[IF_END4938]]
49679 // SIMD-ONLY0:       if.end4938:
49680 // SIMD-ONLY0-NEXT:    [[TMP3638:%.*]] = load i64, ptr [[LLX]], align 8
49681 // SIMD-ONLY0-NEXT:    store i64 [[TMP3638]], ptr [[LLV]], align 8
49682 // SIMD-ONLY0-NEXT:    [[TMP3639:%.*]] = load i64, ptr [[LLX]], align 8
49683 // SIMD-ONLY0-NEXT:    [[TMP3640:%.*]] = load i64, ptr [[LLE]], align 8
49684 // SIMD-ONLY0-NEXT:    [[CMP4939:%.*]] = icmp slt i64 [[TMP3639]], [[TMP3640]]
49685 // SIMD-ONLY0-NEXT:    br i1 [[CMP4939]], label [[IF_THEN4941:%.*]], label [[IF_END4942:%.*]]
49686 // SIMD-ONLY0:       if.then4941:
49687 // SIMD-ONLY0-NEXT:    [[TMP3641:%.*]] = load i64, ptr [[LLE]], align 8
49688 // SIMD-ONLY0-NEXT:    store i64 [[TMP3641]], ptr [[LLX]], align 8
49689 // SIMD-ONLY0-NEXT:    br label [[IF_END4942]]
49690 // SIMD-ONLY0:       if.end4942:
49691 // SIMD-ONLY0-NEXT:    [[TMP3642:%.*]] = load i64, ptr [[LLX]], align 8
49692 // SIMD-ONLY0-NEXT:    store i64 [[TMP3642]], ptr [[LLV]], align 8
49693 // SIMD-ONLY0-NEXT:    [[TMP3643:%.*]] = load i64, ptr [[LLX]], align 8
49694 // SIMD-ONLY0-NEXT:    [[TMP3644:%.*]] = load i64, ptr [[LLE]], align 8
49695 // SIMD-ONLY0-NEXT:    [[CMP4943:%.*]] = icmp eq i64 [[TMP3643]], [[TMP3644]]
49696 // SIMD-ONLY0-NEXT:    br i1 [[CMP4943]], label [[IF_THEN4945:%.*]], label [[IF_END4946:%.*]]
49697 // SIMD-ONLY0:       if.then4945:
49698 // SIMD-ONLY0-NEXT:    [[TMP3645:%.*]] = load i64, ptr [[LLD]], align 8
49699 // SIMD-ONLY0-NEXT:    store i64 [[TMP3645]], ptr [[LLX]], align 8
49700 // SIMD-ONLY0-NEXT:    br label [[IF_END4946]]
49701 // SIMD-ONLY0:       if.end4946:
49702 // SIMD-ONLY0-NEXT:    [[TMP3646:%.*]] = load i64, ptr [[LLX]], align 8
49703 // SIMD-ONLY0-NEXT:    store i64 [[TMP3646]], ptr [[LLV]], align 8
49704 // SIMD-ONLY0-NEXT:    [[TMP3647:%.*]] = load i64, ptr [[LLE]], align 8
49705 // SIMD-ONLY0-NEXT:    [[TMP3648:%.*]] = load i64, ptr [[LLX]], align 8
49706 // SIMD-ONLY0-NEXT:    [[CMP4947:%.*]] = icmp eq i64 [[TMP3647]], [[TMP3648]]
49707 // SIMD-ONLY0-NEXT:    br i1 [[CMP4947]], label [[IF_THEN4949:%.*]], label [[IF_END4950:%.*]]
49708 // SIMD-ONLY0:       if.then4949:
49709 // SIMD-ONLY0-NEXT:    [[TMP3649:%.*]] = load i64, ptr [[LLD]], align 8
49710 // SIMD-ONLY0-NEXT:    store i64 [[TMP3649]], ptr [[LLX]], align 8
49711 // SIMD-ONLY0-NEXT:    br label [[IF_END4950]]
49712 // SIMD-ONLY0:       if.end4950:
49713 // SIMD-ONLY0-NEXT:    [[TMP3650:%.*]] = load i64, ptr [[LLE]], align 8
49714 // SIMD-ONLY0-NEXT:    [[TMP3651:%.*]] = load i64, ptr [[LLX]], align 8
49715 // SIMD-ONLY0-NEXT:    [[CMP4951:%.*]] = icmp sgt i64 [[TMP3650]], [[TMP3651]]
49716 // SIMD-ONLY0-NEXT:    br i1 [[CMP4951]], label [[IF_THEN4953:%.*]], label [[IF_END4954:%.*]]
49717 // SIMD-ONLY0:       if.then4953:
49718 // SIMD-ONLY0-NEXT:    [[TMP3652:%.*]] = load i64, ptr [[LLE]], align 8
49719 // SIMD-ONLY0-NEXT:    store i64 [[TMP3652]], ptr [[LLX]], align 8
49720 // SIMD-ONLY0-NEXT:    br label [[IF_END4954]]
49721 // SIMD-ONLY0:       if.end4954:
49722 // SIMD-ONLY0-NEXT:    [[TMP3653:%.*]] = load i64, ptr [[LLX]], align 8
49723 // SIMD-ONLY0-NEXT:    store i64 [[TMP3653]], ptr [[LLV]], align 8
49724 // SIMD-ONLY0-NEXT:    [[TMP3654:%.*]] = load i64, ptr [[LLX]], align 8
49725 // SIMD-ONLY0-NEXT:    [[TMP3655:%.*]] = load i64, ptr [[LLE]], align 8
49726 // SIMD-ONLY0-NEXT:    [[CMP4955:%.*]] = icmp sgt i64 [[TMP3654]], [[TMP3655]]
49727 // SIMD-ONLY0-NEXT:    br i1 [[CMP4955]], label [[IF_THEN4957:%.*]], label [[IF_END4958:%.*]]
49728 // SIMD-ONLY0:       if.then4957:
49729 // SIMD-ONLY0-NEXT:    [[TMP3656:%.*]] = load i64, ptr [[LLE]], align 8
49730 // SIMD-ONLY0-NEXT:    store i64 [[TMP3656]], ptr [[LLX]], align 8
49731 // SIMD-ONLY0-NEXT:    br label [[IF_END4958]]
49732 // SIMD-ONLY0:       if.end4958:
49733 // SIMD-ONLY0-NEXT:    [[TMP3657:%.*]] = load i64, ptr [[LLX]], align 8
49734 // SIMD-ONLY0-NEXT:    store i64 [[TMP3657]], ptr [[LLV]], align 8
49735 // SIMD-ONLY0-NEXT:    [[TMP3658:%.*]] = load i64, ptr [[LLE]], align 8
49736 // SIMD-ONLY0-NEXT:    [[TMP3659:%.*]] = load i64, ptr [[LLX]], align 8
49737 // SIMD-ONLY0-NEXT:    [[CMP4959:%.*]] = icmp slt i64 [[TMP3658]], [[TMP3659]]
49738 // SIMD-ONLY0-NEXT:    br i1 [[CMP4959]], label [[IF_THEN4961:%.*]], label [[IF_END4962:%.*]]
49739 // SIMD-ONLY0:       if.then4961:
49740 // SIMD-ONLY0-NEXT:    [[TMP3660:%.*]] = load i64, ptr [[LLE]], align 8
49741 // SIMD-ONLY0-NEXT:    store i64 [[TMP3660]], ptr [[LLX]], align 8
49742 // SIMD-ONLY0-NEXT:    br label [[IF_END4962]]
49743 // SIMD-ONLY0:       if.end4962:
49744 // SIMD-ONLY0-NEXT:    [[TMP3661:%.*]] = load i64, ptr [[LLX]], align 8
49745 // SIMD-ONLY0-NEXT:    store i64 [[TMP3661]], ptr [[LLV]], align 8
49746 // SIMD-ONLY0-NEXT:    [[TMP3662:%.*]] = load i64, ptr [[LLX]], align 8
49747 // SIMD-ONLY0-NEXT:    [[TMP3663:%.*]] = load i64, ptr [[LLE]], align 8
49748 // SIMD-ONLY0-NEXT:    [[CMP4963:%.*]] = icmp slt i64 [[TMP3662]], [[TMP3663]]
49749 // SIMD-ONLY0-NEXT:    br i1 [[CMP4963]], label [[IF_THEN4965:%.*]], label [[IF_END4966:%.*]]
49750 // SIMD-ONLY0:       if.then4965:
49751 // SIMD-ONLY0-NEXT:    [[TMP3664:%.*]] = load i64, ptr [[LLE]], align 8
49752 // SIMD-ONLY0-NEXT:    store i64 [[TMP3664]], ptr [[LLX]], align 8
49753 // SIMD-ONLY0-NEXT:    br label [[IF_END4966]]
49754 // SIMD-ONLY0:       if.end4966:
49755 // SIMD-ONLY0-NEXT:    [[TMP3665:%.*]] = load i64, ptr [[LLX]], align 8
49756 // SIMD-ONLY0-NEXT:    store i64 [[TMP3665]], ptr [[LLV]], align 8
49757 // SIMD-ONLY0-NEXT:    [[TMP3666:%.*]] = load i64, ptr [[LLX]], align 8
49758 // SIMD-ONLY0-NEXT:    [[TMP3667:%.*]] = load i64, ptr [[LLE]], align 8
49759 // SIMD-ONLY0-NEXT:    [[CMP4967:%.*]] = icmp eq i64 [[TMP3666]], [[TMP3667]]
49760 // SIMD-ONLY0-NEXT:    br i1 [[CMP4967]], label [[IF_THEN4969:%.*]], label [[IF_END4970:%.*]]
49761 // SIMD-ONLY0:       if.then4969:
49762 // SIMD-ONLY0-NEXT:    [[TMP3668:%.*]] = load i64, ptr [[LLD]], align 8
49763 // SIMD-ONLY0-NEXT:    store i64 [[TMP3668]], ptr [[LLX]], align 8
49764 // SIMD-ONLY0-NEXT:    br label [[IF_END4970]]
49765 // SIMD-ONLY0:       if.end4970:
49766 // SIMD-ONLY0-NEXT:    [[TMP3669:%.*]] = load i64, ptr [[LLX]], align 8
49767 // SIMD-ONLY0-NEXT:    store i64 [[TMP3669]], ptr [[LLV]], align 8
49768 // SIMD-ONLY0-NEXT:    [[TMP3670:%.*]] = load i64, ptr [[LLE]], align 8
49769 // SIMD-ONLY0-NEXT:    [[TMP3671:%.*]] = load i64, ptr [[LLX]], align 8
49770 // SIMD-ONLY0-NEXT:    [[CMP4971:%.*]] = icmp eq i64 [[TMP3670]], [[TMP3671]]
49771 // SIMD-ONLY0-NEXT:    br i1 [[CMP4971]], label [[IF_THEN4973:%.*]], label [[IF_END4974:%.*]]
49772 // SIMD-ONLY0:       if.then4973:
49773 // SIMD-ONLY0-NEXT:    [[TMP3672:%.*]] = load i64, ptr [[LLD]], align 8
49774 // SIMD-ONLY0-NEXT:    store i64 [[TMP3672]], ptr [[LLX]], align 8
49775 // SIMD-ONLY0-NEXT:    br label [[IF_END4974]]
49776 // SIMD-ONLY0:       if.end4974:
49777 // SIMD-ONLY0-NEXT:    [[TMP3673:%.*]] = load i64, ptr [[LLX]], align 8
49778 // SIMD-ONLY0-NEXT:    store i64 [[TMP3673]], ptr [[LLV]], align 8
49779 // SIMD-ONLY0-NEXT:    [[TMP3674:%.*]] = load i64, ptr [[LLX]], align 8
49780 // SIMD-ONLY0-NEXT:    [[TMP3675:%.*]] = load i64, ptr [[LLE]], align 8
49781 // SIMD-ONLY0-NEXT:    [[CMP4975:%.*]] = icmp eq i64 [[TMP3674]], [[TMP3675]]
49782 // SIMD-ONLY0-NEXT:    br i1 [[CMP4975]], label [[IF_THEN4977:%.*]], label [[IF_ELSE4978:%.*]]
49783 // SIMD-ONLY0:       if.then4977:
49784 // SIMD-ONLY0-NEXT:    [[TMP3676:%.*]] = load i64, ptr [[LLD]], align 8
49785 // SIMD-ONLY0-NEXT:    store i64 [[TMP3676]], ptr [[LLX]], align 8
49786 // SIMD-ONLY0-NEXT:    br label [[IF_END4979:%.*]]
49787 // SIMD-ONLY0:       if.else4978:
49788 // SIMD-ONLY0-NEXT:    [[TMP3677:%.*]] = load i64, ptr [[LLX]], align 8
49789 // SIMD-ONLY0-NEXT:    store i64 [[TMP3677]], ptr [[LLV]], align 8
49790 // SIMD-ONLY0-NEXT:    br label [[IF_END4979]]
49791 // SIMD-ONLY0:       if.end4979:
49792 // SIMD-ONLY0-NEXT:    [[TMP3678:%.*]] = load i64, ptr [[LLE]], align 8
49793 // SIMD-ONLY0-NEXT:    [[TMP3679:%.*]] = load i64, ptr [[LLX]], align 8
49794 // SIMD-ONLY0-NEXT:    [[CMP4980:%.*]] = icmp eq i64 [[TMP3678]], [[TMP3679]]
49795 // SIMD-ONLY0-NEXT:    br i1 [[CMP4980]], label [[IF_THEN4982:%.*]], label [[IF_ELSE4983:%.*]]
49796 // SIMD-ONLY0:       if.then4982:
49797 // SIMD-ONLY0-NEXT:    [[TMP3680:%.*]] = load i64, ptr [[LLD]], align 8
49798 // SIMD-ONLY0-NEXT:    store i64 [[TMP3680]], ptr [[LLX]], align 8
49799 // SIMD-ONLY0-NEXT:    br label [[IF_END4984:%.*]]
49800 // SIMD-ONLY0:       if.else4983:
49801 // SIMD-ONLY0-NEXT:    [[TMP3681:%.*]] = load i64, ptr [[LLX]], align 8
49802 // SIMD-ONLY0-NEXT:    store i64 [[TMP3681]], ptr [[LLV]], align 8
49803 // SIMD-ONLY0-NEXT:    br label [[IF_END4984]]
49804 // SIMD-ONLY0:       if.end4984:
49805 // SIMD-ONLY0-NEXT:    [[TMP3682:%.*]] = load i64, ptr [[LLX]], align 8
49806 // SIMD-ONLY0-NEXT:    [[TMP3683:%.*]] = load i64, ptr [[LLE]], align 8
49807 // SIMD-ONLY0-NEXT:    [[CMP4985:%.*]] = icmp eq i64 [[TMP3682]], [[TMP3683]]
49808 // SIMD-ONLY0-NEXT:    [[CONV4986:%.*]] = zext i1 [[CMP4985]] to i32
49809 // SIMD-ONLY0-NEXT:    [[CONV4987:%.*]] = sext i32 [[CONV4986]] to i64
49810 // SIMD-ONLY0-NEXT:    store i64 [[CONV4987]], ptr [[LLR]], align 8
49811 // SIMD-ONLY0-NEXT:    [[TMP3684:%.*]] = load i64, ptr [[LLR]], align 8
49812 // SIMD-ONLY0-NEXT:    [[TOBOOL4988:%.*]] = icmp ne i64 [[TMP3684]], 0
49813 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4988]], label [[IF_THEN4989:%.*]], label [[IF_END4990:%.*]]
49814 // SIMD-ONLY0:       if.then4989:
49815 // SIMD-ONLY0-NEXT:    [[TMP3685:%.*]] = load i64, ptr [[LLD]], align 8
49816 // SIMD-ONLY0-NEXT:    store i64 [[TMP3685]], ptr [[LLX]], align 8
49817 // SIMD-ONLY0-NEXT:    br label [[IF_END4990]]
49818 // SIMD-ONLY0:       if.end4990:
49819 // SIMD-ONLY0-NEXT:    [[TMP3686:%.*]] = load i64, ptr [[LLE]], align 8
49820 // SIMD-ONLY0-NEXT:    [[TMP3687:%.*]] = load i64, ptr [[LLX]], align 8
49821 // SIMD-ONLY0-NEXT:    [[CMP4991:%.*]] = icmp eq i64 [[TMP3686]], [[TMP3687]]
49822 // SIMD-ONLY0-NEXT:    [[CONV4992:%.*]] = zext i1 [[CMP4991]] to i32
49823 // SIMD-ONLY0-NEXT:    [[CONV4993:%.*]] = sext i32 [[CONV4992]] to i64
49824 // SIMD-ONLY0-NEXT:    store i64 [[CONV4993]], ptr [[LLR]], align 8
49825 // SIMD-ONLY0-NEXT:    [[TMP3688:%.*]] = load i64, ptr [[LLR]], align 8
49826 // SIMD-ONLY0-NEXT:    [[TOBOOL4994:%.*]] = icmp ne i64 [[TMP3688]], 0
49827 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL4994]], label [[IF_THEN4995:%.*]], label [[IF_END4996:%.*]]
49828 // SIMD-ONLY0:       if.then4995:
49829 // SIMD-ONLY0-NEXT:    [[TMP3689:%.*]] = load i64, ptr [[LLD]], align 8
49830 // SIMD-ONLY0-NEXT:    store i64 [[TMP3689]], ptr [[LLX]], align 8
49831 // SIMD-ONLY0-NEXT:    br label [[IF_END4996]]
49832 // SIMD-ONLY0:       if.end4996:
49833 // SIMD-ONLY0-NEXT:    [[TMP3690:%.*]] = load i64, ptr [[LLX]], align 8
49834 // SIMD-ONLY0-NEXT:    [[TMP3691:%.*]] = load i64, ptr [[LLE]], align 8
49835 // SIMD-ONLY0-NEXT:    [[CMP4997:%.*]] = icmp eq i64 [[TMP3690]], [[TMP3691]]
49836 // SIMD-ONLY0-NEXT:    [[CONV4998:%.*]] = zext i1 [[CMP4997]] to i32
49837 // SIMD-ONLY0-NEXT:    [[CONV4999:%.*]] = sext i32 [[CONV4998]] to i64
49838 // SIMD-ONLY0-NEXT:    store i64 [[CONV4999]], ptr [[LLR]], align 8
49839 // SIMD-ONLY0-NEXT:    [[TMP3692:%.*]] = load i64, ptr [[LLR]], align 8
49840 // SIMD-ONLY0-NEXT:    [[TOBOOL5000:%.*]] = icmp ne i64 [[TMP3692]], 0
49841 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5000]], label [[IF_THEN5001:%.*]], label [[IF_ELSE5002:%.*]]
49842 // SIMD-ONLY0:       if.then5001:
49843 // SIMD-ONLY0-NEXT:    [[TMP3693:%.*]] = load i64, ptr [[LLD]], align 8
49844 // SIMD-ONLY0-NEXT:    store i64 [[TMP3693]], ptr [[LLX]], align 8
49845 // SIMD-ONLY0-NEXT:    br label [[IF_END5003:%.*]]
49846 // SIMD-ONLY0:       if.else5002:
49847 // SIMD-ONLY0-NEXT:    [[TMP3694:%.*]] = load i64, ptr [[LLX]], align 8
49848 // SIMD-ONLY0-NEXT:    store i64 [[TMP3694]], ptr [[LLV]], align 8
49849 // SIMD-ONLY0-NEXT:    br label [[IF_END5003]]
49850 // SIMD-ONLY0:       if.end5003:
49851 // SIMD-ONLY0-NEXT:    [[TMP3695:%.*]] = load i64, ptr [[LLE]], align 8
49852 // SIMD-ONLY0-NEXT:    [[TMP3696:%.*]] = load i64, ptr [[LLX]], align 8
49853 // SIMD-ONLY0-NEXT:    [[CMP5004:%.*]] = icmp eq i64 [[TMP3695]], [[TMP3696]]
49854 // SIMD-ONLY0-NEXT:    [[CONV5005:%.*]] = zext i1 [[CMP5004]] to i32
49855 // SIMD-ONLY0-NEXT:    [[CONV5006:%.*]] = sext i32 [[CONV5005]] to i64
49856 // SIMD-ONLY0-NEXT:    store i64 [[CONV5006]], ptr [[LLR]], align 8
49857 // SIMD-ONLY0-NEXT:    [[TMP3697:%.*]] = load i64, ptr [[LLR]], align 8
49858 // SIMD-ONLY0-NEXT:    [[TOBOOL5007:%.*]] = icmp ne i64 [[TMP3697]], 0
49859 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5007]], label [[IF_THEN5008:%.*]], label [[IF_ELSE5009:%.*]]
49860 // SIMD-ONLY0:       if.then5008:
49861 // SIMD-ONLY0-NEXT:    [[TMP3698:%.*]] = load i64, ptr [[LLD]], align 8
49862 // SIMD-ONLY0-NEXT:    store i64 [[TMP3698]], ptr [[LLX]], align 8
49863 // SIMD-ONLY0-NEXT:    br label [[IF_END5010:%.*]]
49864 // SIMD-ONLY0:       if.else5009:
49865 // SIMD-ONLY0-NEXT:    [[TMP3699:%.*]] = load i64, ptr [[LLX]], align 8
49866 // SIMD-ONLY0-NEXT:    store i64 [[TMP3699]], ptr [[LLV]], align 8
49867 // SIMD-ONLY0-NEXT:    br label [[IF_END5010]]
49868 // SIMD-ONLY0:       if.end5010:
49869 // SIMD-ONLY0-NEXT:    [[TMP3700:%.*]] = load i64, ptr [[LLX]], align 8
49870 // SIMD-ONLY0-NEXT:    store i64 [[TMP3700]], ptr [[LLV]], align 8
49871 // SIMD-ONLY0-NEXT:    [[TMP3701:%.*]] = load i64, ptr [[LLE]], align 8
49872 // SIMD-ONLY0-NEXT:    [[TMP3702:%.*]] = load i64, ptr [[LLX]], align 8
49873 // SIMD-ONLY0-NEXT:    [[CMP5011:%.*]] = icmp sgt i64 [[TMP3701]], [[TMP3702]]
49874 // SIMD-ONLY0-NEXT:    br i1 [[CMP5011]], label [[IF_THEN5013:%.*]], label [[IF_END5014:%.*]]
49875 // SIMD-ONLY0:       if.then5013:
49876 // SIMD-ONLY0-NEXT:    [[TMP3703:%.*]] = load i64, ptr [[LLE]], align 8
49877 // SIMD-ONLY0-NEXT:    store i64 [[TMP3703]], ptr [[LLX]], align 8
49878 // SIMD-ONLY0-NEXT:    br label [[IF_END5014]]
49879 // SIMD-ONLY0:       if.end5014:
49880 // SIMD-ONLY0-NEXT:    [[TMP3704:%.*]] = load i64, ptr [[LLX]], align 8
49881 // SIMD-ONLY0-NEXT:    store i64 [[TMP3704]], ptr [[LLV]], align 8
49882 // SIMD-ONLY0-NEXT:    [[TMP3705:%.*]] = load i64, ptr [[LLX]], align 8
49883 // SIMD-ONLY0-NEXT:    [[TMP3706:%.*]] = load i64, ptr [[LLE]], align 8
49884 // SIMD-ONLY0-NEXT:    [[CMP5015:%.*]] = icmp sgt i64 [[TMP3705]], [[TMP3706]]
49885 // SIMD-ONLY0-NEXT:    br i1 [[CMP5015]], label [[IF_THEN5017:%.*]], label [[IF_END5018:%.*]]
49886 // SIMD-ONLY0:       if.then5017:
49887 // SIMD-ONLY0-NEXT:    [[TMP3707:%.*]] = load i64, ptr [[LLE]], align 8
49888 // SIMD-ONLY0-NEXT:    store i64 [[TMP3707]], ptr [[LLX]], align 8
49889 // SIMD-ONLY0-NEXT:    br label [[IF_END5018]]
49890 // SIMD-ONLY0:       if.end5018:
49891 // SIMD-ONLY0-NEXT:    [[TMP3708:%.*]] = load i64, ptr [[LLX]], align 8
49892 // SIMD-ONLY0-NEXT:    store i64 [[TMP3708]], ptr [[LLV]], align 8
49893 // SIMD-ONLY0-NEXT:    [[TMP3709:%.*]] = load i64, ptr [[LLE]], align 8
49894 // SIMD-ONLY0-NEXT:    [[TMP3710:%.*]] = load i64, ptr [[LLX]], align 8
49895 // SIMD-ONLY0-NEXT:    [[CMP5019:%.*]] = icmp slt i64 [[TMP3709]], [[TMP3710]]
49896 // SIMD-ONLY0-NEXT:    br i1 [[CMP5019]], label [[IF_THEN5021:%.*]], label [[IF_END5022:%.*]]
49897 // SIMD-ONLY0:       if.then5021:
49898 // SIMD-ONLY0-NEXT:    [[TMP3711:%.*]] = load i64, ptr [[LLE]], align 8
49899 // SIMD-ONLY0-NEXT:    store i64 [[TMP3711]], ptr [[LLX]], align 8
49900 // SIMD-ONLY0-NEXT:    br label [[IF_END5022]]
49901 // SIMD-ONLY0:       if.end5022:
49902 // SIMD-ONLY0-NEXT:    [[TMP3712:%.*]] = load i64, ptr [[LLX]], align 8
49903 // SIMD-ONLY0-NEXT:    store i64 [[TMP3712]], ptr [[LLV]], align 8
49904 // SIMD-ONLY0-NEXT:    [[TMP3713:%.*]] = load i64, ptr [[LLX]], align 8
49905 // SIMD-ONLY0-NEXT:    [[TMP3714:%.*]] = load i64, ptr [[LLE]], align 8
49906 // SIMD-ONLY0-NEXT:    [[CMP5023:%.*]] = icmp slt i64 [[TMP3713]], [[TMP3714]]
49907 // SIMD-ONLY0-NEXT:    br i1 [[CMP5023]], label [[IF_THEN5025:%.*]], label [[IF_END5026:%.*]]
49908 // SIMD-ONLY0:       if.then5025:
49909 // SIMD-ONLY0-NEXT:    [[TMP3715:%.*]] = load i64, ptr [[LLE]], align 8
49910 // SIMD-ONLY0-NEXT:    store i64 [[TMP3715]], ptr [[LLX]], align 8
49911 // SIMD-ONLY0-NEXT:    br label [[IF_END5026]]
49912 // SIMD-ONLY0:       if.end5026:
49913 // SIMD-ONLY0-NEXT:    [[TMP3716:%.*]] = load i64, ptr [[LLX]], align 8
49914 // SIMD-ONLY0-NEXT:    store i64 [[TMP3716]], ptr [[LLV]], align 8
49915 // SIMD-ONLY0-NEXT:    [[TMP3717:%.*]] = load i64, ptr [[LLX]], align 8
49916 // SIMD-ONLY0-NEXT:    [[TMP3718:%.*]] = load i64, ptr [[LLE]], align 8
49917 // SIMD-ONLY0-NEXT:    [[CMP5027:%.*]] = icmp eq i64 [[TMP3717]], [[TMP3718]]
49918 // SIMD-ONLY0-NEXT:    br i1 [[CMP5027]], label [[IF_THEN5029:%.*]], label [[IF_END5030:%.*]]
49919 // SIMD-ONLY0:       if.then5029:
49920 // SIMD-ONLY0-NEXT:    [[TMP3719:%.*]] = load i64, ptr [[LLD]], align 8
49921 // SIMD-ONLY0-NEXT:    store i64 [[TMP3719]], ptr [[LLX]], align 8
49922 // SIMD-ONLY0-NEXT:    br label [[IF_END5030]]
49923 // SIMD-ONLY0:       if.end5030:
49924 // SIMD-ONLY0-NEXT:    [[TMP3720:%.*]] = load i64, ptr [[LLX]], align 8
49925 // SIMD-ONLY0-NEXT:    store i64 [[TMP3720]], ptr [[LLV]], align 8
49926 // SIMD-ONLY0-NEXT:    [[TMP3721:%.*]] = load i64, ptr [[LLE]], align 8
49927 // SIMD-ONLY0-NEXT:    [[TMP3722:%.*]] = load i64, ptr [[LLX]], align 8
49928 // SIMD-ONLY0-NEXT:    [[CMP5031:%.*]] = icmp eq i64 [[TMP3721]], [[TMP3722]]
49929 // SIMD-ONLY0-NEXT:    br i1 [[CMP5031]], label [[IF_THEN5033:%.*]], label [[IF_END5034:%.*]]
49930 // SIMD-ONLY0:       if.then5033:
49931 // SIMD-ONLY0-NEXT:    [[TMP3723:%.*]] = load i64, ptr [[LLD]], align 8
49932 // SIMD-ONLY0-NEXT:    store i64 [[TMP3723]], ptr [[LLX]], align 8
49933 // SIMD-ONLY0-NEXT:    br label [[IF_END5034]]
49934 // SIMD-ONLY0:       if.end5034:
49935 // SIMD-ONLY0-NEXT:    [[TMP3724:%.*]] = load i64, ptr [[LLE]], align 8
49936 // SIMD-ONLY0-NEXT:    [[TMP3725:%.*]] = load i64, ptr [[LLX]], align 8
49937 // SIMD-ONLY0-NEXT:    [[CMP5035:%.*]] = icmp sgt i64 [[TMP3724]], [[TMP3725]]
49938 // SIMD-ONLY0-NEXT:    br i1 [[CMP5035]], label [[IF_THEN5037:%.*]], label [[IF_END5038:%.*]]
49939 // SIMD-ONLY0:       if.then5037:
49940 // SIMD-ONLY0-NEXT:    [[TMP3726:%.*]] = load i64, ptr [[LLE]], align 8
49941 // SIMD-ONLY0-NEXT:    store i64 [[TMP3726]], ptr [[LLX]], align 8
49942 // SIMD-ONLY0-NEXT:    br label [[IF_END5038]]
49943 // SIMD-ONLY0:       if.end5038:
49944 // SIMD-ONLY0-NEXT:    [[TMP3727:%.*]] = load i64, ptr [[LLX]], align 8
49945 // SIMD-ONLY0-NEXT:    store i64 [[TMP3727]], ptr [[LLV]], align 8
49946 // SIMD-ONLY0-NEXT:    [[TMP3728:%.*]] = load i64, ptr [[LLX]], align 8
49947 // SIMD-ONLY0-NEXT:    [[TMP3729:%.*]] = load i64, ptr [[LLE]], align 8
49948 // SIMD-ONLY0-NEXT:    [[CMP5039:%.*]] = icmp sgt i64 [[TMP3728]], [[TMP3729]]
49949 // SIMD-ONLY0-NEXT:    br i1 [[CMP5039]], label [[IF_THEN5041:%.*]], label [[IF_END5042:%.*]]
49950 // SIMD-ONLY0:       if.then5041:
49951 // SIMD-ONLY0-NEXT:    [[TMP3730:%.*]] = load i64, ptr [[LLE]], align 8
49952 // SIMD-ONLY0-NEXT:    store i64 [[TMP3730]], ptr [[LLX]], align 8
49953 // SIMD-ONLY0-NEXT:    br label [[IF_END5042]]
49954 // SIMD-ONLY0:       if.end5042:
49955 // SIMD-ONLY0-NEXT:    [[TMP3731:%.*]] = load i64, ptr [[LLX]], align 8
49956 // SIMD-ONLY0-NEXT:    store i64 [[TMP3731]], ptr [[LLV]], align 8
49957 // SIMD-ONLY0-NEXT:    [[TMP3732:%.*]] = load i64, ptr [[LLE]], align 8
49958 // SIMD-ONLY0-NEXT:    [[TMP3733:%.*]] = load i64, ptr [[LLX]], align 8
49959 // SIMD-ONLY0-NEXT:    [[CMP5043:%.*]] = icmp slt i64 [[TMP3732]], [[TMP3733]]
49960 // SIMD-ONLY0-NEXT:    br i1 [[CMP5043]], label [[IF_THEN5045:%.*]], label [[IF_END5046:%.*]]
49961 // SIMD-ONLY0:       if.then5045:
49962 // SIMD-ONLY0-NEXT:    [[TMP3734:%.*]] = load i64, ptr [[LLE]], align 8
49963 // SIMD-ONLY0-NEXT:    store i64 [[TMP3734]], ptr [[LLX]], align 8
49964 // SIMD-ONLY0-NEXT:    br label [[IF_END5046]]
49965 // SIMD-ONLY0:       if.end5046:
49966 // SIMD-ONLY0-NEXT:    [[TMP3735:%.*]] = load i64, ptr [[LLX]], align 8
49967 // SIMD-ONLY0-NEXT:    store i64 [[TMP3735]], ptr [[LLV]], align 8
49968 // SIMD-ONLY0-NEXT:    [[TMP3736:%.*]] = load i64, ptr [[LLX]], align 8
49969 // SIMD-ONLY0-NEXT:    [[TMP3737:%.*]] = load i64, ptr [[LLE]], align 8
49970 // SIMD-ONLY0-NEXT:    [[CMP5047:%.*]] = icmp slt i64 [[TMP3736]], [[TMP3737]]
49971 // SIMD-ONLY0-NEXT:    br i1 [[CMP5047]], label [[IF_THEN5049:%.*]], label [[IF_END5050:%.*]]
49972 // SIMD-ONLY0:       if.then5049:
49973 // SIMD-ONLY0-NEXT:    [[TMP3738:%.*]] = load i64, ptr [[LLE]], align 8
49974 // SIMD-ONLY0-NEXT:    store i64 [[TMP3738]], ptr [[LLX]], align 8
49975 // SIMD-ONLY0-NEXT:    br label [[IF_END5050]]
49976 // SIMD-ONLY0:       if.end5050:
49977 // SIMD-ONLY0-NEXT:    [[TMP3739:%.*]] = load i64, ptr [[LLX]], align 8
49978 // SIMD-ONLY0-NEXT:    store i64 [[TMP3739]], ptr [[LLV]], align 8
49979 // SIMD-ONLY0-NEXT:    [[TMP3740:%.*]] = load i64, ptr [[LLX]], align 8
49980 // SIMD-ONLY0-NEXT:    [[TMP3741:%.*]] = load i64, ptr [[LLE]], align 8
49981 // SIMD-ONLY0-NEXT:    [[CMP5051:%.*]] = icmp eq i64 [[TMP3740]], [[TMP3741]]
49982 // SIMD-ONLY0-NEXT:    br i1 [[CMP5051]], label [[IF_THEN5053:%.*]], label [[IF_END5054:%.*]]
49983 // SIMD-ONLY0:       if.then5053:
49984 // SIMD-ONLY0-NEXT:    [[TMP3742:%.*]] = load i64, ptr [[LLD]], align 8
49985 // SIMD-ONLY0-NEXT:    store i64 [[TMP3742]], ptr [[LLX]], align 8
49986 // SIMD-ONLY0-NEXT:    br label [[IF_END5054]]
49987 // SIMD-ONLY0:       if.end5054:
49988 // SIMD-ONLY0-NEXT:    [[TMP3743:%.*]] = load i64, ptr [[LLX]], align 8
49989 // SIMD-ONLY0-NEXT:    store i64 [[TMP3743]], ptr [[LLV]], align 8
49990 // SIMD-ONLY0-NEXT:    [[TMP3744:%.*]] = load i64, ptr [[LLE]], align 8
49991 // SIMD-ONLY0-NEXT:    [[TMP3745:%.*]] = load i64, ptr [[LLX]], align 8
49992 // SIMD-ONLY0-NEXT:    [[CMP5055:%.*]] = icmp eq i64 [[TMP3744]], [[TMP3745]]
49993 // SIMD-ONLY0-NEXT:    br i1 [[CMP5055]], label [[IF_THEN5057:%.*]], label [[IF_END5058:%.*]]
49994 // SIMD-ONLY0:       if.then5057:
49995 // SIMD-ONLY0-NEXT:    [[TMP3746:%.*]] = load i64, ptr [[LLD]], align 8
49996 // SIMD-ONLY0-NEXT:    store i64 [[TMP3746]], ptr [[LLX]], align 8
49997 // SIMD-ONLY0-NEXT:    br label [[IF_END5058]]
49998 // SIMD-ONLY0:       if.end5058:
49999 // SIMD-ONLY0-NEXT:    [[TMP3747:%.*]] = load i64, ptr [[LLX]], align 8
50000 // SIMD-ONLY0-NEXT:    store i64 [[TMP3747]], ptr [[LLV]], align 8
50001 // SIMD-ONLY0-NEXT:    [[TMP3748:%.*]] = load i64, ptr [[LLX]], align 8
50002 // SIMD-ONLY0-NEXT:    [[TMP3749:%.*]] = load i64, ptr [[LLE]], align 8
50003 // SIMD-ONLY0-NEXT:    [[CMP5059:%.*]] = icmp eq i64 [[TMP3748]], [[TMP3749]]
50004 // SIMD-ONLY0-NEXT:    br i1 [[CMP5059]], label [[IF_THEN5061:%.*]], label [[IF_ELSE5062:%.*]]
50005 // SIMD-ONLY0:       if.then5061:
50006 // SIMD-ONLY0-NEXT:    [[TMP3750:%.*]] = load i64, ptr [[LLD]], align 8
50007 // SIMD-ONLY0-NEXT:    store i64 [[TMP3750]], ptr [[LLX]], align 8
50008 // SIMD-ONLY0-NEXT:    br label [[IF_END5063:%.*]]
50009 // SIMD-ONLY0:       if.else5062:
50010 // SIMD-ONLY0-NEXT:    [[TMP3751:%.*]] = load i64, ptr [[LLX]], align 8
50011 // SIMD-ONLY0-NEXT:    store i64 [[TMP3751]], ptr [[LLV]], align 8
50012 // SIMD-ONLY0-NEXT:    br label [[IF_END5063]]
50013 // SIMD-ONLY0:       if.end5063:
50014 // SIMD-ONLY0-NEXT:    [[TMP3752:%.*]] = load i64, ptr [[LLE]], align 8
50015 // SIMD-ONLY0-NEXT:    [[TMP3753:%.*]] = load i64, ptr [[LLX]], align 8
50016 // SIMD-ONLY0-NEXT:    [[CMP5064:%.*]] = icmp eq i64 [[TMP3752]], [[TMP3753]]
50017 // SIMD-ONLY0-NEXT:    br i1 [[CMP5064]], label [[IF_THEN5066:%.*]], label [[IF_ELSE5067:%.*]]
50018 // SIMD-ONLY0:       if.then5066:
50019 // SIMD-ONLY0-NEXT:    [[TMP3754:%.*]] = load i64, ptr [[LLD]], align 8
50020 // SIMD-ONLY0-NEXT:    store i64 [[TMP3754]], ptr [[LLX]], align 8
50021 // SIMD-ONLY0-NEXT:    br label [[IF_END5068:%.*]]
50022 // SIMD-ONLY0:       if.else5067:
50023 // SIMD-ONLY0-NEXT:    [[TMP3755:%.*]] = load i64, ptr [[LLX]], align 8
50024 // SIMD-ONLY0-NEXT:    store i64 [[TMP3755]], ptr [[LLV]], align 8
50025 // SIMD-ONLY0-NEXT:    br label [[IF_END5068]]
50026 // SIMD-ONLY0:       if.end5068:
50027 // SIMD-ONLY0-NEXT:    [[TMP3756:%.*]] = load i64, ptr [[LLX]], align 8
50028 // SIMD-ONLY0-NEXT:    [[TMP3757:%.*]] = load i64, ptr [[LLE]], align 8
50029 // SIMD-ONLY0-NEXT:    [[CMP5069:%.*]] = icmp eq i64 [[TMP3756]], [[TMP3757]]
50030 // SIMD-ONLY0-NEXT:    [[CONV5070:%.*]] = zext i1 [[CMP5069]] to i32
50031 // SIMD-ONLY0-NEXT:    [[CONV5071:%.*]] = sext i32 [[CONV5070]] to i64
50032 // SIMD-ONLY0-NEXT:    store i64 [[CONV5071]], ptr [[LLR]], align 8
50033 // SIMD-ONLY0-NEXT:    [[TMP3758:%.*]] = load i64, ptr [[LLR]], align 8
50034 // SIMD-ONLY0-NEXT:    [[TOBOOL5072:%.*]] = icmp ne i64 [[TMP3758]], 0
50035 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5072]], label [[IF_THEN5073:%.*]], label [[IF_END5074:%.*]]
50036 // SIMD-ONLY0:       if.then5073:
50037 // SIMD-ONLY0-NEXT:    [[TMP3759:%.*]] = load i64, ptr [[LLD]], align 8
50038 // SIMD-ONLY0-NEXT:    store i64 [[TMP3759]], ptr [[LLX]], align 8
50039 // SIMD-ONLY0-NEXT:    br label [[IF_END5074]]
50040 // SIMD-ONLY0:       if.end5074:
50041 // SIMD-ONLY0-NEXT:    [[TMP3760:%.*]] = load i64, ptr [[LLE]], align 8
50042 // SIMD-ONLY0-NEXT:    [[TMP3761:%.*]] = load i64, ptr [[LLX]], align 8
50043 // SIMD-ONLY0-NEXT:    [[CMP5075:%.*]] = icmp eq i64 [[TMP3760]], [[TMP3761]]
50044 // SIMD-ONLY0-NEXT:    [[CONV5076:%.*]] = zext i1 [[CMP5075]] to i32
50045 // SIMD-ONLY0-NEXT:    [[CONV5077:%.*]] = sext i32 [[CONV5076]] to i64
50046 // SIMD-ONLY0-NEXT:    store i64 [[CONV5077]], ptr [[LLR]], align 8
50047 // SIMD-ONLY0-NEXT:    [[TMP3762:%.*]] = load i64, ptr [[LLR]], align 8
50048 // SIMD-ONLY0-NEXT:    [[TOBOOL5078:%.*]] = icmp ne i64 [[TMP3762]], 0
50049 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5078]], label [[IF_THEN5079:%.*]], label [[IF_END5080:%.*]]
50050 // SIMD-ONLY0:       if.then5079:
50051 // SIMD-ONLY0-NEXT:    [[TMP3763:%.*]] = load i64, ptr [[LLD]], align 8
50052 // SIMD-ONLY0-NEXT:    store i64 [[TMP3763]], ptr [[LLX]], align 8
50053 // SIMD-ONLY0-NEXT:    br label [[IF_END5080]]
50054 // SIMD-ONLY0:       if.end5080:
50055 // SIMD-ONLY0-NEXT:    [[TMP3764:%.*]] = load i64, ptr [[LLX]], align 8
50056 // SIMD-ONLY0-NEXT:    [[TMP3765:%.*]] = load i64, ptr [[LLE]], align 8
50057 // SIMD-ONLY0-NEXT:    [[CMP5081:%.*]] = icmp eq i64 [[TMP3764]], [[TMP3765]]
50058 // SIMD-ONLY0-NEXT:    [[CONV5082:%.*]] = zext i1 [[CMP5081]] to i32
50059 // SIMD-ONLY0-NEXT:    [[CONV5083:%.*]] = sext i32 [[CONV5082]] to i64
50060 // SIMD-ONLY0-NEXT:    store i64 [[CONV5083]], ptr [[LLR]], align 8
50061 // SIMD-ONLY0-NEXT:    [[TMP3766:%.*]] = load i64, ptr [[LLR]], align 8
50062 // SIMD-ONLY0-NEXT:    [[TOBOOL5084:%.*]] = icmp ne i64 [[TMP3766]], 0
50063 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5084]], label [[IF_THEN5085:%.*]], label [[IF_ELSE5086:%.*]]
50064 // SIMD-ONLY0:       if.then5085:
50065 // SIMD-ONLY0-NEXT:    [[TMP3767:%.*]] = load i64, ptr [[LLD]], align 8
50066 // SIMD-ONLY0-NEXT:    store i64 [[TMP3767]], ptr [[LLX]], align 8
50067 // SIMD-ONLY0-NEXT:    br label [[IF_END5087:%.*]]
50068 // SIMD-ONLY0:       if.else5086:
50069 // SIMD-ONLY0-NEXT:    [[TMP3768:%.*]] = load i64, ptr [[LLX]], align 8
50070 // SIMD-ONLY0-NEXT:    store i64 [[TMP3768]], ptr [[LLV]], align 8
50071 // SIMD-ONLY0-NEXT:    br label [[IF_END5087]]
50072 // SIMD-ONLY0:       if.end5087:
50073 // SIMD-ONLY0-NEXT:    [[TMP3769:%.*]] = load i64, ptr [[LLE]], align 8
50074 // SIMD-ONLY0-NEXT:    [[TMP3770:%.*]] = load i64, ptr [[LLX]], align 8
50075 // SIMD-ONLY0-NEXT:    [[CMP5088:%.*]] = icmp eq i64 [[TMP3769]], [[TMP3770]]
50076 // SIMD-ONLY0-NEXT:    [[CONV5089:%.*]] = zext i1 [[CMP5088]] to i32
50077 // SIMD-ONLY0-NEXT:    [[CONV5090:%.*]] = sext i32 [[CONV5089]] to i64
50078 // SIMD-ONLY0-NEXT:    store i64 [[CONV5090]], ptr [[LLR]], align 8
50079 // SIMD-ONLY0-NEXT:    [[TMP3771:%.*]] = load i64, ptr [[LLR]], align 8
50080 // SIMD-ONLY0-NEXT:    [[TOBOOL5091:%.*]] = icmp ne i64 [[TMP3771]], 0
50081 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5091]], label [[IF_THEN5092:%.*]], label [[IF_ELSE5093:%.*]]
50082 // SIMD-ONLY0:       if.then5092:
50083 // SIMD-ONLY0-NEXT:    [[TMP3772:%.*]] = load i64, ptr [[LLD]], align 8
50084 // SIMD-ONLY0-NEXT:    store i64 [[TMP3772]], ptr [[LLX]], align 8
50085 // SIMD-ONLY0-NEXT:    br label [[IF_END5094:%.*]]
50086 // SIMD-ONLY0:       if.else5093:
50087 // SIMD-ONLY0-NEXT:    [[TMP3773:%.*]] = load i64, ptr [[LLX]], align 8
50088 // SIMD-ONLY0-NEXT:    store i64 [[TMP3773]], ptr [[LLV]], align 8
50089 // SIMD-ONLY0-NEXT:    br label [[IF_END5094]]
50090 // SIMD-ONLY0:       if.end5094:
50091 // SIMD-ONLY0-NEXT:    [[TMP3774:%.*]] = load i64, ptr [[LLX]], align 8
50092 // SIMD-ONLY0-NEXT:    store i64 [[TMP3774]], ptr [[LLV]], align 8
50093 // SIMD-ONLY0-NEXT:    [[TMP3775:%.*]] = load i64, ptr [[LLE]], align 8
50094 // SIMD-ONLY0-NEXT:    [[TMP3776:%.*]] = load i64, ptr [[LLX]], align 8
50095 // SIMD-ONLY0-NEXT:    [[CMP5095:%.*]] = icmp sgt i64 [[TMP3775]], [[TMP3776]]
50096 // SIMD-ONLY0-NEXT:    br i1 [[CMP5095]], label [[IF_THEN5097:%.*]], label [[IF_END5098:%.*]]
50097 // SIMD-ONLY0:       if.then5097:
50098 // SIMD-ONLY0-NEXT:    [[TMP3777:%.*]] = load i64, ptr [[LLE]], align 8
50099 // SIMD-ONLY0-NEXT:    store i64 [[TMP3777]], ptr [[LLX]], align 8
50100 // SIMD-ONLY0-NEXT:    br label [[IF_END5098]]
50101 // SIMD-ONLY0:       if.end5098:
50102 // SIMD-ONLY0-NEXT:    [[TMP3778:%.*]] = load i64, ptr [[LLX]], align 8
50103 // SIMD-ONLY0-NEXT:    store i64 [[TMP3778]], ptr [[LLV]], align 8
50104 // SIMD-ONLY0-NEXT:    [[TMP3779:%.*]] = load i64, ptr [[LLX]], align 8
50105 // SIMD-ONLY0-NEXT:    [[TMP3780:%.*]] = load i64, ptr [[LLE]], align 8
50106 // SIMD-ONLY0-NEXT:    [[CMP5099:%.*]] = icmp sgt i64 [[TMP3779]], [[TMP3780]]
50107 // SIMD-ONLY0-NEXT:    br i1 [[CMP5099]], label [[IF_THEN5101:%.*]], label [[IF_END5102:%.*]]
50108 // SIMD-ONLY0:       if.then5101:
50109 // SIMD-ONLY0-NEXT:    [[TMP3781:%.*]] = load i64, ptr [[LLE]], align 8
50110 // SIMD-ONLY0-NEXT:    store i64 [[TMP3781]], ptr [[LLX]], align 8
50111 // SIMD-ONLY0-NEXT:    br label [[IF_END5102]]
50112 // SIMD-ONLY0:       if.end5102:
50113 // SIMD-ONLY0-NEXT:    [[TMP3782:%.*]] = load i64, ptr [[LLX]], align 8
50114 // SIMD-ONLY0-NEXT:    store i64 [[TMP3782]], ptr [[LLV]], align 8
50115 // SIMD-ONLY0-NEXT:    [[TMP3783:%.*]] = load i64, ptr [[LLE]], align 8
50116 // SIMD-ONLY0-NEXT:    [[TMP3784:%.*]] = load i64, ptr [[LLX]], align 8
50117 // SIMD-ONLY0-NEXT:    [[CMP5103:%.*]] = icmp slt i64 [[TMP3783]], [[TMP3784]]
50118 // SIMD-ONLY0-NEXT:    br i1 [[CMP5103]], label [[IF_THEN5105:%.*]], label [[IF_END5106:%.*]]
50119 // SIMD-ONLY0:       if.then5105:
50120 // SIMD-ONLY0-NEXT:    [[TMP3785:%.*]] = load i64, ptr [[LLE]], align 8
50121 // SIMD-ONLY0-NEXT:    store i64 [[TMP3785]], ptr [[LLX]], align 8
50122 // SIMD-ONLY0-NEXT:    br label [[IF_END5106]]
50123 // SIMD-ONLY0:       if.end5106:
50124 // SIMD-ONLY0-NEXT:    [[TMP3786:%.*]] = load i64, ptr [[LLX]], align 8
50125 // SIMD-ONLY0-NEXT:    store i64 [[TMP3786]], ptr [[LLV]], align 8
50126 // SIMD-ONLY0-NEXT:    [[TMP3787:%.*]] = load i64, ptr [[LLX]], align 8
50127 // SIMD-ONLY0-NEXT:    [[TMP3788:%.*]] = load i64, ptr [[LLE]], align 8
50128 // SIMD-ONLY0-NEXT:    [[CMP5107:%.*]] = icmp slt i64 [[TMP3787]], [[TMP3788]]
50129 // SIMD-ONLY0-NEXT:    br i1 [[CMP5107]], label [[IF_THEN5109:%.*]], label [[IF_END5110:%.*]]
50130 // SIMD-ONLY0:       if.then5109:
50131 // SIMD-ONLY0-NEXT:    [[TMP3789:%.*]] = load i64, ptr [[LLE]], align 8
50132 // SIMD-ONLY0-NEXT:    store i64 [[TMP3789]], ptr [[LLX]], align 8
50133 // SIMD-ONLY0-NEXT:    br label [[IF_END5110]]
50134 // SIMD-ONLY0:       if.end5110:
50135 // SIMD-ONLY0-NEXT:    [[TMP3790:%.*]] = load i64, ptr [[LLX]], align 8
50136 // SIMD-ONLY0-NEXT:    store i64 [[TMP3790]], ptr [[LLV]], align 8
50137 // SIMD-ONLY0-NEXT:    [[TMP3791:%.*]] = load i64, ptr [[LLX]], align 8
50138 // SIMD-ONLY0-NEXT:    [[TMP3792:%.*]] = load i64, ptr [[LLE]], align 8
50139 // SIMD-ONLY0-NEXT:    [[CMP5111:%.*]] = icmp eq i64 [[TMP3791]], [[TMP3792]]
50140 // SIMD-ONLY0-NEXT:    br i1 [[CMP5111]], label [[IF_THEN5113:%.*]], label [[IF_END5114:%.*]]
50141 // SIMD-ONLY0:       if.then5113:
50142 // SIMD-ONLY0-NEXT:    [[TMP3793:%.*]] = load i64, ptr [[LLD]], align 8
50143 // SIMD-ONLY0-NEXT:    store i64 [[TMP3793]], ptr [[LLX]], align 8
50144 // SIMD-ONLY0-NEXT:    br label [[IF_END5114]]
50145 // SIMD-ONLY0:       if.end5114:
50146 // SIMD-ONLY0-NEXT:    [[TMP3794:%.*]] = load i64, ptr [[LLX]], align 8
50147 // SIMD-ONLY0-NEXT:    store i64 [[TMP3794]], ptr [[LLV]], align 8
50148 // SIMD-ONLY0-NEXT:    [[TMP3795:%.*]] = load i64, ptr [[LLE]], align 8
50149 // SIMD-ONLY0-NEXT:    [[TMP3796:%.*]] = load i64, ptr [[LLX]], align 8
50150 // SIMD-ONLY0-NEXT:    [[CMP5115:%.*]] = icmp eq i64 [[TMP3795]], [[TMP3796]]
50151 // SIMD-ONLY0-NEXT:    br i1 [[CMP5115]], label [[IF_THEN5117:%.*]], label [[IF_END5118:%.*]]
50152 // SIMD-ONLY0:       if.then5117:
50153 // SIMD-ONLY0-NEXT:    [[TMP3797:%.*]] = load i64, ptr [[LLD]], align 8
50154 // SIMD-ONLY0-NEXT:    store i64 [[TMP3797]], ptr [[LLX]], align 8
50155 // SIMD-ONLY0-NEXT:    br label [[IF_END5118]]
50156 // SIMD-ONLY0:       if.end5118:
50157 // SIMD-ONLY0-NEXT:    [[TMP3798:%.*]] = load i64, ptr [[LLE]], align 8
50158 // SIMD-ONLY0-NEXT:    [[TMP3799:%.*]] = load i64, ptr [[LLX]], align 8
50159 // SIMD-ONLY0-NEXT:    [[CMP5119:%.*]] = icmp sgt i64 [[TMP3798]], [[TMP3799]]
50160 // SIMD-ONLY0-NEXT:    br i1 [[CMP5119]], label [[IF_THEN5121:%.*]], label [[IF_END5122:%.*]]
50161 // SIMD-ONLY0:       if.then5121:
50162 // SIMD-ONLY0-NEXT:    [[TMP3800:%.*]] = load i64, ptr [[LLE]], align 8
50163 // SIMD-ONLY0-NEXT:    store i64 [[TMP3800]], ptr [[LLX]], align 8
50164 // SIMD-ONLY0-NEXT:    br label [[IF_END5122]]
50165 // SIMD-ONLY0:       if.end5122:
50166 // SIMD-ONLY0-NEXT:    [[TMP3801:%.*]] = load i64, ptr [[LLX]], align 8
50167 // SIMD-ONLY0-NEXT:    store i64 [[TMP3801]], ptr [[LLV]], align 8
50168 // SIMD-ONLY0-NEXT:    [[TMP3802:%.*]] = load i64, ptr [[LLX]], align 8
50169 // SIMD-ONLY0-NEXT:    [[TMP3803:%.*]] = load i64, ptr [[LLE]], align 8
50170 // SIMD-ONLY0-NEXT:    [[CMP5123:%.*]] = icmp sgt i64 [[TMP3802]], [[TMP3803]]
50171 // SIMD-ONLY0-NEXT:    br i1 [[CMP5123]], label [[IF_THEN5125:%.*]], label [[IF_END5126:%.*]]
50172 // SIMD-ONLY0:       if.then5125:
50173 // SIMD-ONLY0-NEXT:    [[TMP3804:%.*]] = load i64, ptr [[LLE]], align 8
50174 // SIMD-ONLY0-NEXT:    store i64 [[TMP3804]], ptr [[LLX]], align 8
50175 // SIMD-ONLY0-NEXT:    br label [[IF_END5126]]
50176 // SIMD-ONLY0:       if.end5126:
50177 // SIMD-ONLY0-NEXT:    [[TMP3805:%.*]] = load i64, ptr [[LLX]], align 8
50178 // SIMD-ONLY0-NEXT:    store i64 [[TMP3805]], ptr [[LLV]], align 8
50179 // SIMD-ONLY0-NEXT:    [[TMP3806:%.*]] = load i64, ptr [[LLE]], align 8
50180 // SIMD-ONLY0-NEXT:    [[TMP3807:%.*]] = load i64, ptr [[LLX]], align 8
50181 // SIMD-ONLY0-NEXT:    [[CMP5127:%.*]] = icmp slt i64 [[TMP3806]], [[TMP3807]]
50182 // SIMD-ONLY0-NEXT:    br i1 [[CMP5127]], label [[IF_THEN5129:%.*]], label [[IF_END5130:%.*]]
50183 // SIMD-ONLY0:       if.then5129:
50184 // SIMD-ONLY0-NEXT:    [[TMP3808:%.*]] = load i64, ptr [[LLE]], align 8
50185 // SIMD-ONLY0-NEXT:    store i64 [[TMP3808]], ptr [[LLX]], align 8
50186 // SIMD-ONLY0-NEXT:    br label [[IF_END5130]]
50187 // SIMD-ONLY0:       if.end5130:
50188 // SIMD-ONLY0-NEXT:    [[TMP3809:%.*]] = load i64, ptr [[LLX]], align 8
50189 // SIMD-ONLY0-NEXT:    store i64 [[TMP3809]], ptr [[LLV]], align 8
50190 // SIMD-ONLY0-NEXT:    [[TMP3810:%.*]] = load i64, ptr [[LLX]], align 8
50191 // SIMD-ONLY0-NEXT:    [[TMP3811:%.*]] = load i64, ptr [[LLE]], align 8
50192 // SIMD-ONLY0-NEXT:    [[CMP5131:%.*]] = icmp slt i64 [[TMP3810]], [[TMP3811]]
50193 // SIMD-ONLY0-NEXT:    br i1 [[CMP5131]], label [[IF_THEN5133:%.*]], label [[IF_END5134:%.*]]
50194 // SIMD-ONLY0:       if.then5133:
50195 // SIMD-ONLY0-NEXT:    [[TMP3812:%.*]] = load i64, ptr [[LLE]], align 8
50196 // SIMD-ONLY0-NEXT:    store i64 [[TMP3812]], ptr [[LLX]], align 8
50197 // SIMD-ONLY0-NEXT:    br label [[IF_END5134]]
50198 // SIMD-ONLY0:       if.end5134:
50199 // SIMD-ONLY0-NEXT:    [[TMP3813:%.*]] = load i64, ptr [[LLX]], align 8
50200 // SIMD-ONLY0-NEXT:    store i64 [[TMP3813]], ptr [[LLV]], align 8
50201 // SIMD-ONLY0-NEXT:    [[TMP3814:%.*]] = load i64, ptr [[LLX]], align 8
50202 // SIMD-ONLY0-NEXT:    [[TMP3815:%.*]] = load i64, ptr [[LLE]], align 8
50203 // SIMD-ONLY0-NEXT:    [[CMP5135:%.*]] = icmp eq i64 [[TMP3814]], [[TMP3815]]
50204 // SIMD-ONLY0-NEXT:    br i1 [[CMP5135]], label [[IF_THEN5137:%.*]], label [[IF_END5138:%.*]]
50205 // SIMD-ONLY0:       if.then5137:
50206 // SIMD-ONLY0-NEXT:    [[TMP3816:%.*]] = load i64, ptr [[LLD]], align 8
50207 // SIMD-ONLY0-NEXT:    store i64 [[TMP3816]], ptr [[LLX]], align 8
50208 // SIMD-ONLY0-NEXT:    br label [[IF_END5138]]
50209 // SIMD-ONLY0:       if.end5138:
50210 // SIMD-ONLY0-NEXT:    [[TMP3817:%.*]] = load i64, ptr [[LLX]], align 8
50211 // SIMD-ONLY0-NEXT:    store i64 [[TMP3817]], ptr [[LLV]], align 8
50212 // SIMD-ONLY0-NEXT:    [[TMP3818:%.*]] = load i64, ptr [[LLE]], align 8
50213 // SIMD-ONLY0-NEXT:    [[TMP3819:%.*]] = load i64, ptr [[LLX]], align 8
50214 // SIMD-ONLY0-NEXT:    [[CMP5139:%.*]] = icmp eq i64 [[TMP3818]], [[TMP3819]]
50215 // SIMD-ONLY0-NEXT:    br i1 [[CMP5139]], label [[IF_THEN5141:%.*]], label [[IF_END5142:%.*]]
50216 // SIMD-ONLY0:       if.then5141:
50217 // SIMD-ONLY0-NEXT:    [[TMP3820:%.*]] = load i64, ptr [[LLD]], align 8
50218 // SIMD-ONLY0-NEXT:    store i64 [[TMP3820]], ptr [[LLX]], align 8
50219 // SIMD-ONLY0-NEXT:    br label [[IF_END5142]]
50220 // SIMD-ONLY0:       if.end5142:
50221 // SIMD-ONLY0-NEXT:    [[TMP3821:%.*]] = load i64, ptr [[LLX]], align 8
50222 // SIMD-ONLY0-NEXT:    store i64 [[TMP3821]], ptr [[LLV]], align 8
50223 // SIMD-ONLY0-NEXT:    [[TMP3822:%.*]] = load i64, ptr [[LLX]], align 8
50224 // SIMD-ONLY0-NEXT:    [[TMP3823:%.*]] = load i64, ptr [[LLE]], align 8
50225 // SIMD-ONLY0-NEXT:    [[CMP5143:%.*]] = icmp eq i64 [[TMP3822]], [[TMP3823]]
50226 // SIMD-ONLY0-NEXT:    br i1 [[CMP5143]], label [[IF_THEN5145:%.*]], label [[IF_ELSE5146:%.*]]
50227 // SIMD-ONLY0:       if.then5145:
50228 // SIMD-ONLY0-NEXT:    [[TMP3824:%.*]] = load i64, ptr [[LLD]], align 8
50229 // SIMD-ONLY0-NEXT:    store i64 [[TMP3824]], ptr [[LLX]], align 8
50230 // SIMD-ONLY0-NEXT:    br label [[IF_END5147:%.*]]
50231 // SIMD-ONLY0:       if.else5146:
50232 // SIMD-ONLY0-NEXT:    [[TMP3825:%.*]] = load i64, ptr [[LLX]], align 8
50233 // SIMD-ONLY0-NEXT:    store i64 [[TMP3825]], ptr [[LLV]], align 8
50234 // SIMD-ONLY0-NEXT:    br label [[IF_END5147]]
50235 // SIMD-ONLY0:       if.end5147:
50236 // SIMD-ONLY0-NEXT:    [[TMP3826:%.*]] = load i64, ptr [[LLE]], align 8
50237 // SIMD-ONLY0-NEXT:    [[TMP3827:%.*]] = load i64, ptr [[LLX]], align 8
50238 // SIMD-ONLY0-NEXT:    [[CMP5148:%.*]] = icmp eq i64 [[TMP3826]], [[TMP3827]]
50239 // SIMD-ONLY0-NEXT:    br i1 [[CMP5148]], label [[IF_THEN5150:%.*]], label [[IF_ELSE5151:%.*]]
50240 // SIMD-ONLY0:       if.then5150:
50241 // SIMD-ONLY0-NEXT:    [[TMP3828:%.*]] = load i64, ptr [[LLD]], align 8
50242 // SIMD-ONLY0-NEXT:    store i64 [[TMP3828]], ptr [[LLX]], align 8
50243 // SIMD-ONLY0-NEXT:    br label [[IF_END5152:%.*]]
50244 // SIMD-ONLY0:       if.else5151:
50245 // SIMD-ONLY0-NEXT:    [[TMP3829:%.*]] = load i64, ptr [[LLX]], align 8
50246 // SIMD-ONLY0-NEXT:    store i64 [[TMP3829]], ptr [[LLV]], align 8
50247 // SIMD-ONLY0-NEXT:    br label [[IF_END5152]]
50248 // SIMD-ONLY0:       if.end5152:
50249 // SIMD-ONLY0-NEXT:    [[TMP3830:%.*]] = load i64, ptr [[LLX]], align 8
50250 // SIMD-ONLY0-NEXT:    [[TMP3831:%.*]] = load i64, ptr [[LLE]], align 8
50251 // SIMD-ONLY0-NEXT:    [[CMP5153:%.*]] = icmp eq i64 [[TMP3830]], [[TMP3831]]
50252 // SIMD-ONLY0-NEXT:    [[CONV5154:%.*]] = zext i1 [[CMP5153]] to i32
50253 // SIMD-ONLY0-NEXT:    [[CONV5155:%.*]] = sext i32 [[CONV5154]] to i64
50254 // SIMD-ONLY0-NEXT:    store i64 [[CONV5155]], ptr [[LLR]], align 8
50255 // SIMD-ONLY0-NEXT:    [[TMP3832:%.*]] = load i64, ptr [[LLR]], align 8
50256 // SIMD-ONLY0-NEXT:    [[TOBOOL5156:%.*]] = icmp ne i64 [[TMP3832]], 0
50257 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5156]], label [[IF_THEN5157:%.*]], label [[IF_END5158:%.*]]
50258 // SIMD-ONLY0:       if.then5157:
50259 // SIMD-ONLY0-NEXT:    [[TMP3833:%.*]] = load i64, ptr [[LLD]], align 8
50260 // SIMD-ONLY0-NEXT:    store i64 [[TMP3833]], ptr [[LLX]], align 8
50261 // SIMD-ONLY0-NEXT:    br label [[IF_END5158]]
50262 // SIMD-ONLY0:       if.end5158:
50263 // SIMD-ONLY0-NEXT:    [[TMP3834:%.*]] = load i64, ptr [[LLE]], align 8
50264 // SIMD-ONLY0-NEXT:    [[TMP3835:%.*]] = load i64, ptr [[LLX]], align 8
50265 // SIMD-ONLY0-NEXT:    [[CMP5159:%.*]] = icmp eq i64 [[TMP3834]], [[TMP3835]]
50266 // SIMD-ONLY0-NEXT:    [[CONV5160:%.*]] = zext i1 [[CMP5159]] to i32
50267 // SIMD-ONLY0-NEXT:    [[CONV5161:%.*]] = sext i32 [[CONV5160]] to i64
50268 // SIMD-ONLY0-NEXT:    store i64 [[CONV5161]], ptr [[LLR]], align 8
50269 // SIMD-ONLY0-NEXT:    [[TMP3836:%.*]] = load i64, ptr [[LLR]], align 8
50270 // SIMD-ONLY0-NEXT:    [[TOBOOL5162:%.*]] = icmp ne i64 [[TMP3836]], 0
50271 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5162]], label [[IF_THEN5163:%.*]], label [[IF_END5164:%.*]]
50272 // SIMD-ONLY0:       if.then5163:
50273 // SIMD-ONLY0-NEXT:    [[TMP3837:%.*]] = load i64, ptr [[LLD]], align 8
50274 // SIMD-ONLY0-NEXT:    store i64 [[TMP3837]], ptr [[LLX]], align 8
50275 // SIMD-ONLY0-NEXT:    br label [[IF_END5164]]
50276 // SIMD-ONLY0:       if.end5164:
50277 // SIMD-ONLY0-NEXT:    [[TMP3838:%.*]] = load i64, ptr [[LLX]], align 8
50278 // SIMD-ONLY0-NEXT:    [[TMP3839:%.*]] = load i64, ptr [[LLE]], align 8
50279 // SIMD-ONLY0-NEXT:    [[CMP5165:%.*]] = icmp eq i64 [[TMP3838]], [[TMP3839]]
50280 // SIMD-ONLY0-NEXT:    [[CONV5166:%.*]] = zext i1 [[CMP5165]] to i32
50281 // SIMD-ONLY0-NEXT:    [[CONV5167:%.*]] = sext i32 [[CONV5166]] to i64
50282 // SIMD-ONLY0-NEXT:    store i64 [[CONV5167]], ptr [[LLR]], align 8
50283 // SIMD-ONLY0-NEXT:    [[TMP3840:%.*]] = load i64, ptr [[LLR]], align 8
50284 // SIMD-ONLY0-NEXT:    [[TOBOOL5168:%.*]] = icmp ne i64 [[TMP3840]], 0
50285 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5168]], label [[IF_THEN5169:%.*]], label [[IF_ELSE5170:%.*]]
50286 // SIMD-ONLY0:       if.then5169:
50287 // SIMD-ONLY0-NEXT:    [[TMP3841:%.*]] = load i64, ptr [[LLD]], align 8
50288 // SIMD-ONLY0-NEXT:    store i64 [[TMP3841]], ptr [[LLX]], align 8
50289 // SIMD-ONLY0-NEXT:    br label [[IF_END5171:%.*]]
50290 // SIMD-ONLY0:       if.else5170:
50291 // SIMD-ONLY0-NEXT:    [[TMP3842:%.*]] = load i64, ptr [[LLX]], align 8
50292 // SIMD-ONLY0-NEXT:    store i64 [[TMP3842]], ptr [[LLV]], align 8
50293 // SIMD-ONLY0-NEXT:    br label [[IF_END5171]]
50294 // SIMD-ONLY0:       if.end5171:
50295 // SIMD-ONLY0-NEXT:    [[TMP3843:%.*]] = load i64, ptr [[LLE]], align 8
50296 // SIMD-ONLY0-NEXT:    [[TMP3844:%.*]] = load i64, ptr [[LLX]], align 8
50297 // SIMD-ONLY0-NEXT:    [[CMP5172:%.*]] = icmp eq i64 [[TMP3843]], [[TMP3844]]
50298 // SIMD-ONLY0-NEXT:    [[CONV5173:%.*]] = zext i1 [[CMP5172]] to i32
50299 // SIMD-ONLY0-NEXT:    [[CONV5174:%.*]] = sext i32 [[CONV5173]] to i64
50300 // SIMD-ONLY0-NEXT:    store i64 [[CONV5174]], ptr [[LLR]], align 8
50301 // SIMD-ONLY0-NEXT:    [[TMP3845:%.*]] = load i64, ptr [[LLR]], align 8
50302 // SIMD-ONLY0-NEXT:    [[TOBOOL5175:%.*]] = icmp ne i64 [[TMP3845]], 0
50303 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5175]], label [[IF_THEN5176:%.*]], label [[IF_ELSE5177:%.*]]
50304 // SIMD-ONLY0:       if.then5176:
50305 // SIMD-ONLY0-NEXT:    [[TMP3846:%.*]] = load i64, ptr [[LLD]], align 8
50306 // SIMD-ONLY0-NEXT:    store i64 [[TMP3846]], ptr [[LLX]], align 8
50307 // SIMD-ONLY0-NEXT:    br label [[IF_END5178:%.*]]
50308 // SIMD-ONLY0:       if.else5177:
50309 // SIMD-ONLY0-NEXT:    [[TMP3847:%.*]] = load i64, ptr [[LLX]], align 8
50310 // SIMD-ONLY0-NEXT:    store i64 [[TMP3847]], ptr [[LLV]], align 8
50311 // SIMD-ONLY0-NEXT:    br label [[IF_END5178]]
50312 // SIMD-ONLY0:       if.end5178:
50313 // SIMD-ONLY0-NEXT:    [[TMP3848:%.*]] = load i64, ptr [[LLX]], align 8
50314 // SIMD-ONLY0-NEXT:    store i64 [[TMP3848]], ptr [[LLV]], align 8
50315 // SIMD-ONLY0-NEXT:    [[TMP3849:%.*]] = load i64, ptr [[LLE]], align 8
50316 // SIMD-ONLY0-NEXT:    [[TMP3850:%.*]] = load i64, ptr [[LLX]], align 8
50317 // SIMD-ONLY0-NEXT:    [[CMP5179:%.*]] = icmp sgt i64 [[TMP3849]], [[TMP3850]]
50318 // SIMD-ONLY0-NEXT:    br i1 [[CMP5179]], label [[IF_THEN5181:%.*]], label [[IF_END5182:%.*]]
50319 // SIMD-ONLY0:       if.then5181:
50320 // SIMD-ONLY0-NEXT:    [[TMP3851:%.*]] = load i64, ptr [[LLE]], align 8
50321 // SIMD-ONLY0-NEXT:    store i64 [[TMP3851]], ptr [[LLX]], align 8
50322 // SIMD-ONLY0-NEXT:    br label [[IF_END5182]]
50323 // SIMD-ONLY0:       if.end5182:
50324 // SIMD-ONLY0-NEXT:    [[TMP3852:%.*]] = load i64, ptr [[LLX]], align 8
50325 // SIMD-ONLY0-NEXT:    store i64 [[TMP3852]], ptr [[LLV]], align 8
50326 // SIMD-ONLY0-NEXT:    [[TMP3853:%.*]] = load i64, ptr [[LLX]], align 8
50327 // SIMD-ONLY0-NEXT:    [[TMP3854:%.*]] = load i64, ptr [[LLE]], align 8
50328 // SIMD-ONLY0-NEXT:    [[CMP5183:%.*]] = icmp sgt i64 [[TMP3853]], [[TMP3854]]
50329 // SIMD-ONLY0-NEXT:    br i1 [[CMP5183]], label [[IF_THEN5185:%.*]], label [[IF_END5186:%.*]]
50330 // SIMD-ONLY0:       if.then5185:
50331 // SIMD-ONLY0-NEXT:    [[TMP3855:%.*]] = load i64, ptr [[LLE]], align 8
50332 // SIMD-ONLY0-NEXT:    store i64 [[TMP3855]], ptr [[LLX]], align 8
50333 // SIMD-ONLY0-NEXT:    br label [[IF_END5186]]
50334 // SIMD-ONLY0:       if.end5186:
50335 // SIMD-ONLY0-NEXT:    [[TMP3856:%.*]] = load i64, ptr [[LLX]], align 8
50336 // SIMD-ONLY0-NEXT:    store i64 [[TMP3856]], ptr [[LLV]], align 8
50337 // SIMD-ONLY0-NEXT:    [[TMP3857:%.*]] = load i64, ptr [[LLE]], align 8
50338 // SIMD-ONLY0-NEXT:    [[TMP3858:%.*]] = load i64, ptr [[LLX]], align 8
50339 // SIMD-ONLY0-NEXT:    [[CMP5187:%.*]] = icmp slt i64 [[TMP3857]], [[TMP3858]]
50340 // SIMD-ONLY0-NEXT:    br i1 [[CMP5187]], label [[IF_THEN5189:%.*]], label [[IF_END5190:%.*]]
50341 // SIMD-ONLY0:       if.then5189:
50342 // SIMD-ONLY0-NEXT:    [[TMP3859:%.*]] = load i64, ptr [[LLE]], align 8
50343 // SIMD-ONLY0-NEXT:    store i64 [[TMP3859]], ptr [[LLX]], align 8
50344 // SIMD-ONLY0-NEXT:    br label [[IF_END5190]]
50345 // SIMD-ONLY0:       if.end5190:
50346 // SIMD-ONLY0-NEXT:    [[TMP3860:%.*]] = load i64, ptr [[LLX]], align 8
50347 // SIMD-ONLY0-NEXT:    store i64 [[TMP3860]], ptr [[LLV]], align 8
50348 // SIMD-ONLY0-NEXT:    [[TMP3861:%.*]] = load i64, ptr [[LLX]], align 8
50349 // SIMD-ONLY0-NEXT:    [[TMP3862:%.*]] = load i64, ptr [[LLE]], align 8
50350 // SIMD-ONLY0-NEXT:    [[CMP5191:%.*]] = icmp slt i64 [[TMP3861]], [[TMP3862]]
50351 // SIMD-ONLY0-NEXT:    br i1 [[CMP5191]], label [[IF_THEN5193:%.*]], label [[IF_END5194:%.*]]
50352 // SIMD-ONLY0:       if.then5193:
50353 // SIMD-ONLY0-NEXT:    [[TMP3863:%.*]] = load i64, ptr [[LLE]], align 8
50354 // SIMD-ONLY0-NEXT:    store i64 [[TMP3863]], ptr [[LLX]], align 8
50355 // SIMD-ONLY0-NEXT:    br label [[IF_END5194]]
50356 // SIMD-ONLY0:       if.end5194:
50357 // SIMD-ONLY0-NEXT:    [[TMP3864:%.*]] = load i64, ptr [[LLX]], align 8
50358 // SIMD-ONLY0-NEXT:    store i64 [[TMP3864]], ptr [[LLV]], align 8
50359 // SIMD-ONLY0-NEXT:    [[TMP3865:%.*]] = load i64, ptr [[LLX]], align 8
50360 // SIMD-ONLY0-NEXT:    [[TMP3866:%.*]] = load i64, ptr [[LLE]], align 8
50361 // SIMD-ONLY0-NEXT:    [[CMP5195:%.*]] = icmp eq i64 [[TMP3865]], [[TMP3866]]
50362 // SIMD-ONLY0-NEXT:    br i1 [[CMP5195]], label [[IF_THEN5197:%.*]], label [[IF_END5198:%.*]]
50363 // SIMD-ONLY0:       if.then5197:
50364 // SIMD-ONLY0-NEXT:    [[TMP3867:%.*]] = load i64, ptr [[LLD]], align 8
50365 // SIMD-ONLY0-NEXT:    store i64 [[TMP3867]], ptr [[LLX]], align 8
50366 // SIMD-ONLY0-NEXT:    br label [[IF_END5198]]
50367 // SIMD-ONLY0:       if.end5198:
50368 // SIMD-ONLY0-NEXT:    [[TMP3868:%.*]] = load i64, ptr [[LLX]], align 8
50369 // SIMD-ONLY0-NEXT:    store i64 [[TMP3868]], ptr [[LLV]], align 8
50370 // SIMD-ONLY0-NEXT:    [[TMP3869:%.*]] = load i64, ptr [[LLE]], align 8
50371 // SIMD-ONLY0-NEXT:    [[TMP3870:%.*]] = load i64, ptr [[LLX]], align 8
50372 // SIMD-ONLY0-NEXT:    [[CMP5199:%.*]] = icmp eq i64 [[TMP3869]], [[TMP3870]]
50373 // SIMD-ONLY0-NEXT:    br i1 [[CMP5199]], label [[IF_THEN5201:%.*]], label [[IF_END5202:%.*]]
50374 // SIMD-ONLY0:       if.then5201:
50375 // SIMD-ONLY0-NEXT:    [[TMP3871:%.*]] = load i64, ptr [[LLD]], align 8
50376 // SIMD-ONLY0-NEXT:    store i64 [[TMP3871]], ptr [[LLX]], align 8
50377 // SIMD-ONLY0-NEXT:    br label [[IF_END5202]]
50378 // SIMD-ONLY0:       if.end5202:
50379 // SIMD-ONLY0-NEXT:    [[TMP3872:%.*]] = load i64, ptr [[LLE]], align 8
50380 // SIMD-ONLY0-NEXT:    [[TMP3873:%.*]] = load i64, ptr [[LLX]], align 8
50381 // SIMD-ONLY0-NEXT:    [[CMP5203:%.*]] = icmp sgt i64 [[TMP3872]], [[TMP3873]]
50382 // SIMD-ONLY0-NEXT:    br i1 [[CMP5203]], label [[IF_THEN5205:%.*]], label [[IF_END5206:%.*]]
50383 // SIMD-ONLY0:       if.then5205:
50384 // SIMD-ONLY0-NEXT:    [[TMP3874:%.*]] = load i64, ptr [[LLE]], align 8
50385 // SIMD-ONLY0-NEXT:    store i64 [[TMP3874]], ptr [[LLX]], align 8
50386 // SIMD-ONLY0-NEXT:    br label [[IF_END5206]]
50387 // SIMD-ONLY0:       if.end5206:
50388 // SIMD-ONLY0-NEXT:    [[TMP3875:%.*]] = load i64, ptr [[LLX]], align 8
50389 // SIMD-ONLY0-NEXT:    store i64 [[TMP3875]], ptr [[LLV]], align 8
50390 // SIMD-ONLY0-NEXT:    [[TMP3876:%.*]] = load i64, ptr [[LLX]], align 8
50391 // SIMD-ONLY0-NEXT:    [[TMP3877:%.*]] = load i64, ptr [[LLE]], align 8
50392 // SIMD-ONLY0-NEXT:    [[CMP5207:%.*]] = icmp sgt i64 [[TMP3876]], [[TMP3877]]
50393 // SIMD-ONLY0-NEXT:    br i1 [[CMP5207]], label [[IF_THEN5209:%.*]], label [[IF_END5210:%.*]]
50394 // SIMD-ONLY0:       if.then5209:
50395 // SIMD-ONLY0-NEXT:    [[TMP3878:%.*]] = load i64, ptr [[LLE]], align 8
50396 // SIMD-ONLY0-NEXT:    store i64 [[TMP3878]], ptr [[LLX]], align 8
50397 // SIMD-ONLY0-NEXT:    br label [[IF_END5210]]
50398 // SIMD-ONLY0:       if.end5210:
50399 // SIMD-ONLY0-NEXT:    [[TMP3879:%.*]] = load i64, ptr [[LLX]], align 8
50400 // SIMD-ONLY0-NEXT:    store i64 [[TMP3879]], ptr [[LLV]], align 8
50401 // SIMD-ONLY0-NEXT:    [[TMP3880:%.*]] = load i64, ptr [[LLE]], align 8
50402 // SIMD-ONLY0-NEXT:    [[TMP3881:%.*]] = load i64, ptr [[LLX]], align 8
50403 // SIMD-ONLY0-NEXT:    [[CMP5211:%.*]] = icmp slt i64 [[TMP3880]], [[TMP3881]]
50404 // SIMD-ONLY0-NEXT:    br i1 [[CMP5211]], label [[IF_THEN5213:%.*]], label [[IF_END5214:%.*]]
50405 // SIMD-ONLY0:       if.then5213:
50406 // SIMD-ONLY0-NEXT:    [[TMP3882:%.*]] = load i64, ptr [[LLE]], align 8
50407 // SIMD-ONLY0-NEXT:    store i64 [[TMP3882]], ptr [[LLX]], align 8
50408 // SIMD-ONLY0-NEXT:    br label [[IF_END5214]]
50409 // SIMD-ONLY0:       if.end5214:
50410 // SIMD-ONLY0-NEXT:    [[TMP3883:%.*]] = load i64, ptr [[LLX]], align 8
50411 // SIMD-ONLY0-NEXT:    store i64 [[TMP3883]], ptr [[LLV]], align 8
50412 // SIMD-ONLY0-NEXT:    [[TMP3884:%.*]] = load i64, ptr [[LLX]], align 8
50413 // SIMD-ONLY0-NEXT:    [[TMP3885:%.*]] = load i64, ptr [[LLE]], align 8
50414 // SIMD-ONLY0-NEXT:    [[CMP5215:%.*]] = icmp slt i64 [[TMP3884]], [[TMP3885]]
50415 // SIMD-ONLY0-NEXT:    br i1 [[CMP5215]], label [[IF_THEN5217:%.*]], label [[IF_END5218:%.*]]
50416 // SIMD-ONLY0:       if.then5217:
50417 // SIMD-ONLY0-NEXT:    [[TMP3886:%.*]] = load i64, ptr [[LLE]], align 8
50418 // SIMD-ONLY0-NEXT:    store i64 [[TMP3886]], ptr [[LLX]], align 8
50419 // SIMD-ONLY0-NEXT:    br label [[IF_END5218]]
50420 // SIMD-ONLY0:       if.end5218:
50421 // SIMD-ONLY0-NEXT:    [[TMP3887:%.*]] = load i64, ptr [[LLX]], align 8
50422 // SIMD-ONLY0-NEXT:    store i64 [[TMP3887]], ptr [[LLV]], align 8
50423 // SIMD-ONLY0-NEXT:    [[TMP3888:%.*]] = load i64, ptr [[LLX]], align 8
50424 // SIMD-ONLY0-NEXT:    [[TMP3889:%.*]] = load i64, ptr [[LLE]], align 8
50425 // SIMD-ONLY0-NEXT:    [[CMP5219:%.*]] = icmp eq i64 [[TMP3888]], [[TMP3889]]
50426 // SIMD-ONLY0-NEXT:    br i1 [[CMP5219]], label [[IF_THEN5221:%.*]], label [[IF_END5222:%.*]]
50427 // SIMD-ONLY0:       if.then5221:
50428 // SIMD-ONLY0-NEXT:    [[TMP3890:%.*]] = load i64, ptr [[LLD]], align 8
50429 // SIMD-ONLY0-NEXT:    store i64 [[TMP3890]], ptr [[LLX]], align 8
50430 // SIMD-ONLY0-NEXT:    br label [[IF_END5222]]
50431 // SIMD-ONLY0:       if.end5222:
50432 // SIMD-ONLY0-NEXT:    [[TMP3891:%.*]] = load i64, ptr [[LLX]], align 8
50433 // SIMD-ONLY0-NEXT:    store i64 [[TMP3891]], ptr [[LLV]], align 8
50434 // SIMD-ONLY0-NEXT:    [[TMP3892:%.*]] = load i64, ptr [[LLE]], align 8
50435 // SIMD-ONLY0-NEXT:    [[TMP3893:%.*]] = load i64, ptr [[LLX]], align 8
50436 // SIMD-ONLY0-NEXT:    [[CMP5223:%.*]] = icmp eq i64 [[TMP3892]], [[TMP3893]]
50437 // SIMD-ONLY0-NEXT:    br i1 [[CMP5223]], label [[IF_THEN5225:%.*]], label [[IF_END5226:%.*]]
50438 // SIMD-ONLY0:       if.then5225:
50439 // SIMD-ONLY0-NEXT:    [[TMP3894:%.*]] = load i64, ptr [[LLD]], align 8
50440 // SIMD-ONLY0-NEXT:    store i64 [[TMP3894]], ptr [[LLX]], align 8
50441 // SIMD-ONLY0-NEXT:    br label [[IF_END5226]]
50442 // SIMD-ONLY0:       if.end5226:
50443 // SIMD-ONLY0-NEXT:    [[TMP3895:%.*]] = load i64, ptr [[LLX]], align 8
50444 // SIMD-ONLY0-NEXT:    store i64 [[TMP3895]], ptr [[LLV]], align 8
50445 // SIMD-ONLY0-NEXT:    [[TMP3896:%.*]] = load i64, ptr [[LLX]], align 8
50446 // SIMD-ONLY0-NEXT:    [[TMP3897:%.*]] = load i64, ptr [[LLE]], align 8
50447 // SIMD-ONLY0-NEXT:    [[CMP5227:%.*]] = icmp eq i64 [[TMP3896]], [[TMP3897]]
50448 // SIMD-ONLY0-NEXT:    br i1 [[CMP5227]], label [[IF_THEN5229:%.*]], label [[IF_ELSE5230:%.*]]
50449 // SIMD-ONLY0:       if.then5229:
50450 // SIMD-ONLY0-NEXT:    [[TMP3898:%.*]] = load i64, ptr [[LLD]], align 8
50451 // SIMD-ONLY0-NEXT:    store i64 [[TMP3898]], ptr [[LLX]], align 8
50452 // SIMD-ONLY0-NEXT:    br label [[IF_END5231:%.*]]
50453 // SIMD-ONLY0:       if.else5230:
50454 // SIMD-ONLY0-NEXT:    [[TMP3899:%.*]] = load i64, ptr [[LLX]], align 8
50455 // SIMD-ONLY0-NEXT:    store i64 [[TMP3899]], ptr [[LLV]], align 8
50456 // SIMD-ONLY0-NEXT:    br label [[IF_END5231]]
50457 // SIMD-ONLY0:       if.end5231:
50458 // SIMD-ONLY0-NEXT:    [[TMP3900:%.*]] = load i64, ptr [[LLE]], align 8
50459 // SIMD-ONLY0-NEXT:    [[TMP3901:%.*]] = load i64, ptr [[LLX]], align 8
50460 // SIMD-ONLY0-NEXT:    [[CMP5232:%.*]] = icmp eq i64 [[TMP3900]], [[TMP3901]]
50461 // SIMD-ONLY0-NEXT:    br i1 [[CMP5232]], label [[IF_THEN5234:%.*]], label [[IF_ELSE5235:%.*]]
50462 // SIMD-ONLY0:       if.then5234:
50463 // SIMD-ONLY0-NEXT:    [[TMP3902:%.*]] = load i64, ptr [[LLD]], align 8
50464 // SIMD-ONLY0-NEXT:    store i64 [[TMP3902]], ptr [[LLX]], align 8
50465 // SIMD-ONLY0-NEXT:    br label [[IF_END5236:%.*]]
50466 // SIMD-ONLY0:       if.else5235:
50467 // SIMD-ONLY0-NEXT:    [[TMP3903:%.*]] = load i64, ptr [[LLX]], align 8
50468 // SIMD-ONLY0-NEXT:    store i64 [[TMP3903]], ptr [[LLV]], align 8
50469 // SIMD-ONLY0-NEXT:    br label [[IF_END5236]]
50470 // SIMD-ONLY0:       if.end5236:
50471 // SIMD-ONLY0-NEXT:    [[TMP3904:%.*]] = load i64, ptr [[LLX]], align 8
50472 // SIMD-ONLY0-NEXT:    [[TMP3905:%.*]] = load i64, ptr [[LLE]], align 8
50473 // SIMD-ONLY0-NEXT:    [[CMP5237:%.*]] = icmp eq i64 [[TMP3904]], [[TMP3905]]
50474 // SIMD-ONLY0-NEXT:    [[CONV5238:%.*]] = zext i1 [[CMP5237]] to i32
50475 // SIMD-ONLY0-NEXT:    [[CONV5239:%.*]] = sext i32 [[CONV5238]] to i64
50476 // SIMD-ONLY0-NEXT:    store i64 [[CONV5239]], ptr [[LLR]], align 8
50477 // SIMD-ONLY0-NEXT:    [[TMP3906:%.*]] = load i64, ptr [[LLR]], align 8
50478 // SIMD-ONLY0-NEXT:    [[TOBOOL5240:%.*]] = icmp ne i64 [[TMP3906]], 0
50479 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5240]], label [[IF_THEN5241:%.*]], label [[IF_END5242:%.*]]
50480 // SIMD-ONLY0:       if.then5241:
50481 // SIMD-ONLY0-NEXT:    [[TMP3907:%.*]] = load i64, ptr [[LLD]], align 8
50482 // SIMD-ONLY0-NEXT:    store i64 [[TMP3907]], ptr [[LLX]], align 8
50483 // SIMD-ONLY0-NEXT:    br label [[IF_END5242]]
50484 // SIMD-ONLY0:       if.end5242:
50485 // SIMD-ONLY0-NEXT:    [[TMP3908:%.*]] = load i64, ptr [[LLE]], align 8
50486 // SIMD-ONLY0-NEXT:    [[TMP3909:%.*]] = load i64, ptr [[LLX]], align 8
50487 // SIMD-ONLY0-NEXT:    [[CMP5243:%.*]] = icmp eq i64 [[TMP3908]], [[TMP3909]]
50488 // SIMD-ONLY0-NEXT:    [[CONV5244:%.*]] = zext i1 [[CMP5243]] to i32
50489 // SIMD-ONLY0-NEXT:    [[CONV5245:%.*]] = sext i32 [[CONV5244]] to i64
50490 // SIMD-ONLY0-NEXT:    store i64 [[CONV5245]], ptr [[LLR]], align 8
50491 // SIMD-ONLY0-NEXT:    [[TMP3910:%.*]] = load i64, ptr [[LLR]], align 8
50492 // SIMD-ONLY0-NEXT:    [[TOBOOL5246:%.*]] = icmp ne i64 [[TMP3910]], 0
50493 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5246]], label [[IF_THEN5247:%.*]], label [[IF_END5248:%.*]]
50494 // SIMD-ONLY0:       if.then5247:
50495 // SIMD-ONLY0-NEXT:    [[TMP3911:%.*]] = load i64, ptr [[LLD]], align 8
50496 // SIMD-ONLY0-NEXT:    store i64 [[TMP3911]], ptr [[LLX]], align 8
50497 // SIMD-ONLY0-NEXT:    br label [[IF_END5248]]
50498 // SIMD-ONLY0:       if.end5248:
50499 // SIMD-ONLY0-NEXT:    [[TMP3912:%.*]] = load i64, ptr [[LLX]], align 8
50500 // SIMD-ONLY0-NEXT:    [[TMP3913:%.*]] = load i64, ptr [[LLE]], align 8
50501 // SIMD-ONLY0-NEXT:    [[CMP5249:%.*]] = icmp eq i64 [[TMP3912]], [[TMP3913]]
50502 // SIMD-ONLY0-NEXT:    [[CONV5250:%.*]] = zext i1 [[CMP5249]] to i32
50503 // SIMD-ONLY0-NEXT:    [[CONV5251:%.*]] = sext i32 [[CONV5250]] to i64
50504 // SIMD-ONLY0-NEXT:    store i64 [[CONV5251]], ptr [[LLR]], align 8
50505 // SIMD-ONLY0-NEXT:    [[TMP3914:%.*]] = load i64, ptr [[LLR]], align 8
50506 // SIMD-ONLY0-NEXT:    [[TOBOOL5252:%.*]] = icmp ne i64 [[TMP3914]], 0
50507 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5252]], label [[IF_THEN5253:%.*]], label [[IF_ELSE5254:%.*]]
50508 // SIMD-ONLY0:       if.then5253:
50509 // SIMD-ONLY0-NEXT:    [[TMP3915:%.*]] = load i64, ptr [[LLD]], align 8
50510 // SIMD-ONLY0-NEXT:    store i64 [[TMP3915]], ptr [[LLX]], align 8
50511 // SIMD-ONLY0-NEXT:    br label [[IF_END5255:%.*]]
50512 // SIMD-ONLY0:       if.else5254:
50513 // SIMD-ONLY0-NEXT:    [[TMP3916:%.*]] = load i64, ptr [[LLX]], align 8
50514 // SIMD-ONLY0-NEXT:    store i64 [[TMP3916]], ptr [[LLV]], align 8
50515 // SIMD-ONLY0-NEXT:    br label [[IF_END5255]]
50516 // SIMD-ONLY0:       if.end5255:
50517 // SIMD-ONLY0-NEXT:    [[TMP3917:%.*]] = load i64, ptr [[LLE]], align 8
50518 // SIMD-ONLY0-NEXT:    [[TMP3918:%.*]] = load i64, ptr [[LLX]], align 8
50519 // SIMD-ONLY0-NEXT:    [[CMP5256:%.*]] = icmp eq i64 [[TMP3917]], [[TMP3918]]
50520 // SIMD-ONLY0-NEXT:    [[CONV5257:%.*]] = zext i1 [[CMP5256]] to i32
50521 // SIMD-ONLY0-NEXT:    [[CONV5258:%.*]] = sext i32 [[CONV5257]] to i64
50522 // SIMD-ONLY0-NEXT:    store i64 [[CONV5258]], ptr [[LLR]], align 8
50523 // SIMD-ONLY0-NEXT:    [[TMP3919:%.*]] = load i64, ptr [[LLR]], align 8
50524 // SIMD-ONLY0-NEXT:    [[TOBOOL5259:%.*]] = icmp ne i64 [[TMP3919]], 0
50525 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5259]], label [[IF_THEN5260:%.*]], label [[IF_ELSE5261:%.*]]
50526 // SIMD-ONLY0:       if.then5260:
50527 // SIMD-ONLY0-NEXT:    [[TMP3920:%.*]] = load i64, ptr [[LLD]], align 8
50528 // SIMD-ONLY0-NEXT:    store i64 [[TMP3920]], ptr [[LLX]], align 8
50529 // SIMD-ONLY0-NEXT:    br label [[IF_END5262:%.*]]
50530 // SIMD-ONLY0:       if.else5261:
50531 // SIMD-ONLY0-NEXT:    [[TMP3921:%.*]] = load i64, ptr [[LLX]], align 8
50532 // SIMD-ONLY0-NEXT:    store i64 [[TMP3921]], ptr [[LLV]], align 8
50533 // SIMD-ONLY0-NEXT:    br label [[IF_END5262]]
50534 // SIMD-ONLY0:       if.end5262:
50535 // SIMD-ONLY0-NEXT:    [[TMP3922:%.*]] = load i64, ptr [[LLX]], align 8
50536 // SIMD-ONLY0-NEXT:    store i64 [[TMP3922]], ptr [[LLV]], align 8
50537 // SIMD-ONLY0-NEXT:    [[TMP3923:%.*]] = load i64, ptr [[LLE]], align 8
50538 // SIMD-ONLY0-NEXT:    [[TMP3924:%.*]] = load i64, ptr [[LLX]], align 8
50539 // SIMD-ONLY0-NEXT:    [[CMP5263:%.*]] = icmp sgt i64 [[TMP3923]], [[TMP3924]]
50540 // SIMD-ONLY0-NEXT:    br i1 [[CMP5263]], label [[IF_THEN5265:%.*]], label [[IF_END5266:%.*]]
50541 // SIMD-ONLY0:       if.then5265:
50542 // SIMD-ONLY0-NEXT:    [[TMP3925:%.*]] = load i64, ptr [[LLE]], align 8
50543 // SIMD-ONLY0-NEXT:    store i64 [[TMP3925]], ptr [[LLX]], align 8
50544 // SIMD-ONLY0-NEXT:    br label [[IF_END5266]]
50545 // SIMD-ONLY0:       if.end5266:
50546 // SIMD-ONLY0-NEXT:    [[TMP3926:%.*]] = load i64, ptr [[LLX]], align 8
50547 // SIMD-ONLY0-NEXT:    store i64 [[TMP3926]], ptr [[LLV]], align 8
50548 // SIMD-ONLY0-NEXT:    [[TMP3927:%.*]] = load i64, ptr [[LLX]], align 8
50549 // SIMD-ONLY0-NEXT:    [[TMP3928:%.*]] = load i64, ptr [[LLE]], align 8
50550 // SIMD-ONLY0-NEXT:    [[CMP5267:%.*]] = icmp sgt i64 [[TMP3927]], [[TMP3928]]
50551 // SIMD-ONLY0-NEXT:    br i1 [[CMP5267]], label [[IF_THEN5269:%.*]], label [[IF_END5270:%.*]]
50552 // SIMD-ONLY0:       if.then5269:
50553 // SIMD-ONLY0-NEXT:    [[TMP3929:%.*]] = load i64, ptr [[LLE]], align 8
50554 // SIMD-ONLY0-NEXT:    store i64 [[TMP3929]], ptr [[LLX]], align 8
50555 // SIMD-ONLY0-NEXT:    br label [[IF_END5270]]
50556 // SIMD-ONLY0:       if.end5270:
50557 // SIMD-ONLY0-NEXT:    [[TMP3930:%.*]] = load i64, ptr [[LLX]], align 8
50558 // SIMD-ONLY0-NEXT:    store i64 [[TMP3930]], ptr [[LLV]], align 8
50559 // SIMD-ONLY0-NEXT:    [[TMP3931:%.*]] = load i64, ptr [[LLE]], align 8
50560 // SIMD-ONLY0-NEXT:    [[TMP3932:%.*]] = load i64, ptr [[LLX]], align 8
50561 // SIMD-ONLY0-NEXT:    [[CMP5271:%.*]] = icmp slt i64 [[TMP3931]], [[TMP3932]]
50562 // SIMD-ONLY0-NEXT:    br i1 [[CMP5271]], label [[IF_THEN5273:%.*]], label [[IF_END5274:%.*]]
50563 // SIMD-ONLY0:       if.then5273:
50564 // SIMD-ONLY0-NEXT:    [[TMP3933:%.*]] = load i64, ptr [[LLE]], align 8
50565 // SIMD-ONLY0-NEXT:    store i64 [[TMP3933]], ptr [[LLX]], align 8
50566 // SIMD-ONLY0-NEXT:    br label [[IF_END5274]]
50567 // SIMD-ONLY0:       if.end5274:
50568 // SIMD-ONLY0-NEXT:    [[TMP3934:%.*]] = load i64, ptr [[LLX]], align 8
50569 // SIMD-ONLY0-NEXT:    store i64 [[TMP3934]], ptr [[LLV]], align 8
50570 // SIMD-ONLY0-NEXT:    [[TMP3935:%.*]] = load i64, ptr [[LLX]], align 8
50571 // SIMD-ONLY0-NEXT:    [[TMP3936:%.*]] = load i64, ptr [[LLE]], align 8
50572 // SIMD-ONLY0-NEXT:    [[CMP5275:%.*]] = icmp slt i64 [[TMP3935]], [[TMP3936]]
50573 // SIMD-ONLY0-NEXT:    br i1 [[CMP5275]], label [[IF_THEN5277:%.*]], label [[IF_END5278:%.*]]
50574 // SIMD-ONLY0:       if.then5277:
50575 // SIMD-ONLY0-NEXT:    [[TMP3937:%.*]] = load i64, ptr [[LLE]], align 8
50576 // SIMD-ONLY0-NEXT:    store i64 [[TMP3937]], ptr [[LLX]], align 8
50577 // SIMD-ONLY0-NEXT:    br label [[IF_END5278]]
50578 // SIMD-ONLY0:       if.end5278:
50579 // SIMD-ONLY0-NEXT:    [[TMP3938:%.*]] = load i64, ptr [[LLX]], align 8
50580 // SIMD-ONLY0-NEXT:    store i64 [[TMP3938]], ptr [[LLV]], align 8
50581 // SIMD-ONLY0-NEXT:    [[TMP3939:%.*]] = load i64, ptr [[LLX]], align 8
50582 // SIMD-ONLY0-NEXT:    [[TMP3940:%.*]] = load i64, ptr [[LLE]], align 8
50583 // SIMD-ONLY0-NEXT:    [[CMP5279:%.*]] = icmp eq i64 [[TMP3939]], [[TMP3940]]
50584 // SIMD-ONLY0-NEXT:    br i1 [[CMP5279]], label [[IF_THEN5281:%.*]], label [[IF_END5282:%.*]]
50585 // SIMD-ONLY0:       if.then5281:
50586 // SIMD-ONLY0-NEXT:    [[TMP3941:%.*]] = load i64, ptr [[LLD]], align 8
50587 // SIMD-ONLY0-NEXT:    store i64 [[TMP3941]], ptr [[LLX]], align 8
50588 // SIMD-ONLY0-NEXT:    br label [[IF_END5282]]
50589 // SIMD-ONLY0:       if.end5282:
50590 // SIMD-ONLY0-NEXT:    [[TMP3942:%.*]] = load i64, ptr [[LLX]], align 8
50591 // SIMD-ONLY0-NEXT:    store i64 [[TMP3942]], ptr [[LLV]], align 8
50592 // SIMD-ONLY0-NEXT:    [[TMP3943:%.*]] = load i64, ptr [[LLE]], align 8
50593 // SIMD-ONLY0-NEXT:    [[TMP3944:%.*]] = load i64, ptr [[LLX]], align 8
50594 // SIMD-ONLY0-NEXT:    [[CMP5283:%.*]] = icmp eq i64 [[TMP3943]], [[TMP3944]]
50595 // SIMD-ONLY0-NEXT:    br i1 [[CMP5283]], label [[IF_THEN5285:%.*]], label [[IF_END5286:%.*]]
50596 // SIMD-ONLY0:       if.then5285:
50597 // SIMD-ONLY0-NEXT:    [[TMP3945:%.*]] = load i64, ptr [[LLD]], align 8
50598 // SIMD-ONLY0-NEXT:    store i64 [[TMP3945]], ptr [[LLX]], align 8
50599 // SIMD-ONLY0-NEXT:    br label [[IF_END5286]]
50600 // SIMD-ONLY0:       if.end5286:
50601 // SIMD-ONLY0-NEXT:    [[TMP3946:%.*]] = load i64, ptr [[LLE]], align 8
50602 // SIMD-ONLY0-NEXT:    [[TMP3947:%.*]] = load i64, ptr [[LLX]], align 8
50603 // SIMD-ONLY0-NEXT:    [[CMP5287:%.*]] = icmp sgt i64 [[TMP3946]], [[TMP3947]]
50604 // SIMD-ONLY0-NEXT:    br i1 [[CMP5287]], label [[IF_THEN5289:%.*]], label [[IF_END5290:%.*]]
50605 // SIMD-ONLY0:       if.then5289:
50606 // SIMD-ONLY0-NEXT:    [[TMP3948:%.*]] = load i64, ptr [[LLE]], align 8
50607 // SIMD-ONLY0-NEXT:    store i64 [[TMP3948]], ptr [[LLX]], align 8
50608 // SIMD-ONLY0-NEXT:    br label [[IF_END5290]]
50609 // SIMD-ONLY0:       if.end5290:
50610 // SIMD-ONLY0-NEXT:    [[TMP3949:%.*]] = load i64, ptr [[LLX]], align 8
50611 // SIMD-ONLY0-NEXT:    store i64 [[TMP3949]], ptr [[LLV]], align 8
50612 // SIMD-ONLY0-NEXT:    [[TMP3950:%.*]] = load i64, ptr [[LLX]], align 8
50613 // SIMD-ONLY0-NEXT:    [[TMP3951:%.*]] = load i64, ptr [[LLE]], align 8
50614 // SIMD-ONLY0-NEXT:    [[CMP5291:%.*]] = icmp sgt i64 [[TMP3950]], [[TMP3951]]
50615 // SIMD-ONLY0-NEXT:    br i1 [[CMP5291]], label [[IF_THEN5293:%.*]], label [[IF_END5294:%.*]]
50616 // SIMD-ONLY0:       if.then5293:
50617 // SIMD-ONLY0-NEXT:    [[TMP3952:%.*]] = load i64, ptr [[LLE]], align 8
50618 // SIMD-ONLY0-NEXT:    store i64 [[TMP3952]], ptr [[LLX]], align 8
50619 // SIMD-ONLY0-NEXT:    br label [[IF_END5294]]
50620 // SIMD-ONLY0:       if.end5294:
50621 // SIMD-ONLY0-NEXT:    [[TMP3953:%.*]] = load i64, ptr [[LLX]], align 8
50622 // SIMD-ONLY0-NEXT:    store i64 [[TMP3953]], ptr [[LLV]], align 8
50623 // SIMD-ONLY0-NEXT:    [[TMP3954:%.*]] = load i64, ptr [[LLE]], align 8
50624 // SIMD-ONLY0-NEXT:    [[TMP3955:%.*]] = load i64, ptr [[LLX]], align 8
50625 // SIMD-ONLY0-NEXT:    [[CMP5295:%.*]] = icmp slt i64 [[TMP3954]], [[TMP3955]]
50626 // SIMD-ONLY0-NEXT:    br i1 [[CMP5295]], label [[IF_THEN5297:%.*]], label [[IF_END5298:%.*]]
50627 // SIMD-ONLY0:       if.then5297:
50628 // SIMD-ONLY0-NEXT:    [[TMP3956:%.*]] = load i64, ptr [[LLE]], align 8
50629 // SIMD-ONLY0-NEXT:    store i64 [[TMP3956]], ptr [[LLX]], align 8
50630 // SIMD-ONLY0-NEXT:    br label [[IF_END5298]]
50631 // SIMD-ONLY0:       if.end5298:
50632 // SIMD-ONLY0-NEXT:    [[TMP3957:%.*]] = load i64, ptr [[LLX]], align 8
50633 // SIMD-ONLY0-NEXT:    store i64 [[TMP3957]], ptr [[LLV]], align 8
50634 // SIMD-ONLY0-NEXT:    [[TMP3958:%.*]] = load i64, ptr [[LLX]], align 8
50635 // SIMD-ONLY0-NEXT:    [[TMP3959:%.*]] = load i64, ptr [[LLE]], align 8
50636 // SIMD-ONLY0-NEXT:    [[CMP5299:%.*]] = icmp slt i64 [[TMP3958]], [[TMP3959]]
50637 // SIMD-ONLY0-NEXT:    br i1 [[CMP5299]], label [[IF_THEN5301:%.*]], label [[IF_END5302:%.*]]
50638 // SIMD-ONLY0:       if.then5301:
50639 // SIMD-ONLY0-NEXT:    [[TMP3960:%.*]] = load i64, ptr [[LLE]], align 8
50640 // SIMD-ONLY0-NEXT:    store i64 [[TMP3960]], ptr [[LLX]], align 8
50641 // SIMD-ONLY0-NEXT:    br label [[IF_END5302]]
50642 // SIMD-ONLY0:       if.end5302:
50643 // SIMD-ONLY0-NEXT:    [[TMP3961:%.*]] = load i64, ptr [[LLX]], align 8
50644 // SIMD-ONLY0-NEXT:    store i64 [[TMP3961]], ptr [[LLV]], align 8
50645 // SIMD-ONLY0-NEXT:    [[TMP3962:%.*]] = load i64, ptr [[LLX]], align 8
50646 // SIMD-ONLY0-NEXT:    [[TMP3963:%.*]] = load i64, ptr [[LLE]], align 8
50647 // SIMD-ONLY0-NEXT:    [[CMP5303:%.*]] = icmp eq i64 [[TMP3962]], [[TMP3963]]
50648 // SIMD-ONLY0-NEXT:    br i1 [[CMP5303]], label [[IF_THEN5305:%.*]], label [[IF_END5306:%.*]]
50649 // SIMD-ONLY0:       if.then5305:
50650 // SIMD-ONLY0-NEXT:    [[TMP3964:%.*]] = load i64, ptr [[LLD]], align 8
50651 // SIMD-ONLY0-NEXT:    store i64 [[TMP3964]], ptr [[LLX]], align 8
50652 // SIMD-ONLY0-NEXT:    br label [[IF_END5306]]
50653 // SIMD-ONLY0:       if.end5306:
50654 // SIMD-ONLY0-NEXT:    [[TMP3965:%.*]] = load i64, ptr [[LLX]], align 8
50655 // SIMD-ONLY0-NEXT:    store i64 [[TMP3965]], ptr [[LLV]], align 8
50656 // SIMD-ONLY0-NEXT:    [[TMP3966:%.*]] = load i64, ptr [[LLE]], align 8
50657 // SIMD-ONLY0-NEXT:    [[TMP3967:%.*]] = load i64, ptr [[LLX]], align 8
50658 // SIMD-ONLY0-NEXT:    [[CMP5307:%.*]] = icmp eq i64 [[TMP3966]], [[TMP3967]]
50659 // SIMD-ONLY0-NEXT:    br i1 [[CMP5307]], label [[IF_THEN5309:%.*]], label [[IF_END5310:%.*]]
50660 // SIMD-ONLY0:       if.then5309:
50661 // SIMD-ONLY0-NEXT:    [[TMP3968:%.*]] = load i64, ptr [[LLD]], align 8
50662 // SIMD-ONLY0-NEXT:    store i64 [[TMP3968]], ptr [[LLX]], align 8
50663 // SIMD-ONLY0-NEXT:    br label [[IF_END5310]]
50664 // SIMD-ONLY0:       if.end5310:
50665 // SIMD-ONLY0-NEXT:    [[TMP3969:%.*]] = load i64, ptr [[LLX]], align 8
50666 // SIMD-ONLY0-NEXT:    store i64 [[TMP3969]], ptr [[LLV]], align 8
50667 // SIMD-ONLY0-NEXT:    [[TMP3970:%.*]] = load i64, ptr [[LLX]], align 8
50668 // SIMD-ONLY0-NEXT:    [[TMP3971:%.*]] = load i64, ptr [[LLE]], align 8
50669 // SIMD-ONLY0-NEXT:    [[CMP5311:%.*]] = icmp eq i64 [[TMP3970]], [[TMP3971]]
50670 // SIMD-ONLY0-NEXT:    br i1 [[CMP5311]], label [[IF_THEN5313:%.*]], label [[IF_ELSE5314:%.*]]
50671 // SIMD-ONLY0:       if.then5313:
50672 // SIMD-ONLY0-NEXT:    [[TMP3972:%.*]] = load i64, ptr [[LLD]], align 8
50673 // SIMD-ONLY0-NEXT:    store i64 [[TMP3972]], ptr [[LLX]], align 8
50674 // SIMD-ONLY0-NEXT:    br label [[IF_END5315:%.*]]
50675 // SIMD-ONLY0:       if.else5314:
50676 // SIMD-ONLY0-NEXT:    [[TMP3973:%.*]] = load i64, ptr [[LLX]], align 8
50677 // SIMD-ONLY0-NEXT:    store i64 [[TMP3973]], ptr [[LLV]], align 8
50678 // SIMD-ONLY0-NEXT:    br label [[IF_END5315]]
50679 // SIMD-ONLY0:       if.end5315:
50680 // SIMD-ONLY0-NEXT:    [[TMP3974:%.*]] = load i64, ptr [[LLE]], align 8
50681 // SIMD-ONLY0-NEXT:    [[TMP3975:%.*]] = load i64, ptr [[LLX]], align 8
50682 // SIMD-ONLY0-NEXT:    [[CMP5316:%.*]] = icmp eq i64 [[TMP3974]], [[TMP3975]]
50683 // SIMD-ONLY0-NEXT:    br i1 [[CMP5316]], label [[IF_THEN5318:%.*]], label [[IF_ELSE5319:%.*]]
50684 // SIMD-ONLY0:       if.then5318:
50685 // SIMD-ONLY0-NEXT:    [[TMP3976:%.*]] = load i64, ptr [[LLD]], align 8
50686 // SIMD-ONLY0-NEXT:    store i64 [[TMP3976]], ptr [[LLX]], align 8
50687 // SIMD-ONLY0-NEXT:    br label [[IF_END5320:%.*]]
50688 // SIMD-ONLY0:       if.else5319:
50689 // SIMD-ONLY0-NEXT:    [[TMP3977:%.*]] = load i64, ptr [[LLX]], align 8
50690 // SIMD-ONLY0-NEXT:    store i64 [[TMP3977]], ptr [[LLV]], align 8
50691 // SIMD-ONLY0-NEXT:    br label [[IF_END5320]]
50692 // SIMD-ONLY0:       if.end5320:
50693 // SIMD-ONLY0-NEXT:    [[TMP3978:%.*]] = load i64, ptr [[LLX]], align 8
50694 // SIMD-ONLY0-NEXT:    [[TMP3979:%.*]] = load i64, ptr [[LLE]], align 8
50695 // SIMD-ONLY0-NEXT:    [[CMP5321:%.*]] = icmp eq i64 [[TMP3978]], [[TMP3979]]
50696 // SIMD-ONLY0-NEXT:    [[CONV5322:%.*]] = zext i1 [[CMP5321]] to i32
50697 // SIMD-ONLY0-NEXT:    [[CONV5323:%.*]] = sext i32 [[CONV5322]] to i64
50698 // SIMD-ONLY0-NEXT:    store i64 [[CONV5323]], ptr [[LLR]], align 8
50699 // SIMD-ONLY0-NEXT:    [[TMP3980:%.*]] = load i64, ptr [[LLR]], align 8
50700 // SIMD-ONLY0-NEXT:    [[TOBOOL5324:%.*]] = icmp ne i64 [[TMP3980]], 0
50701 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5324]], label [[IF_THEN5325:%.*]], label [[IF_END5326:%.*]]
50702 // SIMD-ONLY0:       if.then5325:
50703 // SIMD-ONLY0-NEXT:    [[TMP3981:%.*]] = load i64, ptr [[LLD]], align 8
50704 // SIMD-ONLY0-NEXT:    store i64 [[TMP3981]], ptr [[LLX]], align 8
50705 // SIMD-ONLY0-NEXT:    br label [[IF_END5326]]
50706 // SIMD-ONLY0:       if.end5326:
50707 // SIMD-ONLY0-NEXT:    [[TMP3982:%.*]] = load i64, ptr [[LLE]], align 8
50708 // SIMD-ONLY0-NEXT:    [[TMP3983:%.*]] = load i64, ptr [[LLX]], align 8
50709 // SIMD-ONLY0-NEXT:    [[CMP5327:%.*]] = icmp eq i64 [[TMP3982]], [[TMP3983]]
50710 // SIMD-ONLY0-NEXT:    [[CONV5328:%.*]] = zext i1 [[CMP5327]] to i32
50711 // SIMD-ONLY0-NEXT:    [[CONV5329:%.*]] = sext i32 [[CONV5328]] to i64
50712 // SIMD-ONLY0-NEXT:    store i64 [[CONV5329]], ptr [[LLR]], align 8
50713 // SIMD-ONLY0-NEXT:    [[TMP3984:%.*]] = load i64, ptr [[LLR]], align 8
50714 // SIMD-ONLY0-NEXT:    [[TOBOOL5330:%.*]] = icmp ne i64 [[TMP3984]], 0
50715 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5330]], label [[IF_THEN5331:%.*]], label [[IF_END5332:%.*]]
50716 // SIMD-ONLY0:       if.then5331:
50717 // SIMD-ONLY0-NEXT:    [[TMP3985:%.*]] = load i64, ptr [[LLD]], align 8
50718 // SIMD-ONLY0-NEXT:    store i64 [[TMP3985]], ptr [[LLX]], align 8
50719 // SIMD-ONLY0-NEXT:    br label [[IF_END5332]]
50720 // SIMD-ONLY0:       if.end5332:
50721 // SIMD-ONLY0-NEXT:    [[TMP3986:%.*]] = load i64, ptr [[LLX]], align 8
50722 // SIMD-ONLY0-NEXT:    [[TMP3987:%.*]] = load i64, ptr [[LLE]], align 8
50723 // SIMD-ONLY0-NEXT:    [[CMP5333:%.*]] = icmp eq i64 [[TMP3986]], [[TMP3987]]
50724 // SIMD-ONLY0-NEXT:    [[CONV5334:%.*]] = zext i1 [[CMP5333]] to i32
50725 // SIMD-ONLY0-NEXT:    [[CONV5335:%.*]] = sext i32 [[CONV5334]] to i64
50726 // SIMD-ONLY0-NEXT:    store i64 [[CONV5335]], ptr [[LLR]], align 8
50727 // SIMD-ONLY0-NEXT:    [[TMP3988:%.*]] = load i64, ptr [[LLR]], align 8
50728 // SIMD-ONLY0-NEXT:    [[TOBOOL5336:%.*]] = icmp ne i64 [[TMP3988]], 0
50729 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5336]], label [[IF_THEN5337:%.*]], label [[IF_ELSE5338:%.*]]
50730 // SIMD-ONLY0:       if.then5337:
50731 // SIMD-ONLY0-NEXT:    [[TMP3989:%.*]] = load i64, ptr [[LLD]], align 8
50732 // SIMD-ONLY0-NEXT:    store i64 [[TMP3989]], ptr [[LLX]], align 8
50733 // SIMD-ONLY0-NEXT:    br label [[IF_END5339:%.*]]
50734 // SIMD-ONLY0:       if.else5338:
50735 // SIMD-ONLY0-NEXT:    [[TMP3990:%.*]] = load i64, ptr [[LLX]], align 8
50736 // SIMD-ONLY0-NEXT:    store i64 [[TMP3990]], ptr [[LLV]], align 8
50737 // SIMD-ONLY0-NEXT:    br label [[IF_END5339]]
50738 // SIMD-ONLY0:       if.end5339:
50739 // SIMD-ONLY0-NEXT:    [[TMP3991:%.*]] = load i64, ptr [[LLE]], align 8
50740 // SIMD-ONLY0-NEXT:    [[TMP3992:%.*]] = load i64, ptr [[LLX]], align 8
50741 // SIMD-ONLY0-NEXT:    [[CMP5340:%.*]] = icmp eq i64 [[TMP3991]], [[TMP3992]]
50742 // SIMD-ONLY0-NEXT:    [[CONV5341:%.*]] = zext i1 [[CMP5340]] to i32
50743 // SIMD-ONLY0-NEXT:    [[CONV5342:%.*]] = sext i32 [[CONV5341]] to i64
50744 // SIMD-ONLY0-NEXT:    store i64 [[CONV5342]], ptr [[LLR]], align 8
50745 // SIMD-ONLY0-NEXT:    [[TMP3993:%.*]] = load i64, ptr [[LLR]], align 8
50746 // SIMD-ONLY0-NEXT:    [[TOBOOL5343:%.*]] = icmp ne i64 [[TMP3993]], 0
50747 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5343]], label [[IF_THEN5344:%.*]], label [[IF_ELSE5345:%.*]]
50748 // SIMD-ONLY0:       if.then5344:
50749 // SIMD-ONLY0-NEXT:    [[TMP3994:%.*]] = load i64, ptr [[LLD]], align 8
50750 // SIMD-ONLY0-NEXT:    store i64 [[TMP3994]], ptr [[LLX]], align 8
50751 // SIMD-ONLY0-NEXT:    br label [[IF_END5346:%.*]]
50752 // SIMD-ONLY0:       if.else5345:
50753 // SIMD-ONLY0-NEXT:    [[TMP3995:%.*]] = load i64, ptr [[LLX]], align 8
50754 // SIMD-ONLY0-NEXT:    store i64 [[TMP3995]], ptr [[LLV]], align 8
50755 // SIMD-ONLY0-NEXT:    br label [[IF_END5346]]
50756 // SIMD-ONLY0:       if.end5346:
50757 // SIMD-ONLY0-NEXT:    [[TMP3996:%.*]] = load i64, ptr [[ULLX]], align 8
50758 // SIMD-ONLY0-NEXT:    store i64 [[TMP3996]], ptr [[ULLV]], align 8
50759 // SIMD-ONLY0-NEXT:    [[TMP3997:%.*]] = load i64, ptr [[ULLE]], align 8
50760 // SIMD-ONLY0-NEXT:    [[TMP3998:%.*]] = load i64, ptr [[ULLX]], align 8
50761 // SIMD-ONLY0-NEXT:    [[CMP5347:%.*]] = icmp ugt i64 [[TMP3997]], [[TMP3998]]
50762 // SIMD-ONLY0-NEXT:    br i1 [[CMP5347]], label [[IF_THEN5349:%.*]], label [[IF_END5350:%.*]]
50763 // SIMD-ONLY0:       if.then5349:
50764 // SIMD-ONLY0-NEXT:    [[TMP3999:%.*]] = load i64, ptr [[ULLE]], align 8
50765 // SIMD-ONLY0-NEXT:    store i64 [[TMP3999]], ptr [[ULLX]], align 8
50766 // SIMD-ONLY0-NEXT:    br label [[IF_END5350]]
50767 // SIMD-ONLY0:       if.end5350:
50768 // SIMD-ONLY0-NEXT:    [[TMP4000:%.*]] = load i64, ptr [[ULLX]], align 8
50769 // SIMD-ONLY0-NEXT:    store i64 [[TMP4000]], ptr [[ULLV]], align 8
50770 // SIMD-ONLY0-NEXT:    [[TMP4001:%.*]] = load i64, ptr [[ULLX]], align 8
50771 // SIMD-ONLY0-NEXT:    [[TMP4002:%.*]] = load i64, ptr [[ULLE]], align 8
50772 // SIMD-ONLY0-NEXT:    [[CMP5351:%.*]] = icmp ugt i64 [[TMP4001]], [[TMP4002]]
50773 // SIMD-ONLY0-NEXT:    br i1 [[CMP5351]], label [[IF_THEN5353:%.*]], label [[IF_END5354:%.*]]
50774 // SIMD-ONLY0:       if.then5353:
50775 // SIMD-ONLY0-NEXT:    [[TMP4003:%.*]] = load i64, ptr [[ULLE]], align 8
50776 // SIMD-ONLY0-NEXT:    store i64 [[TMP4003]], ptr [[ULLX]], align 8
50777 // SIMD-ONLY0-NEXT:    br label [[IF_END5354]]
50778 // SIMD-ONLY0:       if.end5354:
50779 // SIMD-ONLY0-NEXT:    [[TMP4004:%.*]] = load i64, ptr [[ULLX]], align 8
50780 // SIMD-ONLY0-NEXT:    store i64 [[TMP4004]], ptr [[ULLV]], align 8
50781 // SIMD-ONLY0-NEXT:    [[TMP4005:%.*]] = load i64, ptr [[ULLE]], align 8
50782 // SIMD-ONLY0-NEXT:    [[TMP4006:%.*]] = load i64, ptr [[ULLX]], align 8
50783 // SIMD-ONLY0-NEXT:    [[CMP5355:%.*]] = icmp ult i64 [[TMP4005]], [[TMP4006]]
50784 // SIMD-ONLY0-NEXT:    br i1 [[CMP5355]], label [[IF_THEN5357:%.*]], label [[IF_END5358:%.*]]
50785 // SIMD-ONLY0:       if.then5357:
50786 // SIMD-ONLY0-NEXT:    [[TMP4007:%.*]] = load i64, ptr [[ULLE]], align 8
50787 // SIMD-ONLY0-NEXT:    store i64 [[TMP4007]], ptr [[ULLX]], align 8
50788 // SIMD-ONLY0-NEXT:    br label [[IF_END5358]]
50789 // SIMD-ONLY0:       if.end5358:
50790 // SIMD-ONLY0-NEXT:    [[TMP4008:%.*]] = load i64, ptr [[ULLX]], align 8
50791 // SIMD-ONLY0-NEXT:    store i64 [[TMP4008]], ptr [[ULLV]], align 8
50792 // SIMD-ONLY0-NEXT:    [[TMP4009:%.*]] = load i64, ptr [[ULLX]], align 8
50793 // SIMD-ONLY0-NEXT:    [[TMP4010:%.*]] = load i64, ptr [[ULLE]], align 8
50794 // SIMD-ONLY0-NEXT:    [[CMP5359:%.*]] = icmp ult i64 [[TMP4009]], [[TMP4010]]
50795 // SIMD-ONLY0-NEXT:    br i1 [[CMP5359]], label [[IF_THEN5361:%.*]], label [[IF_END5362:%.*]]
50796 // SIMD-ONLY0:       if.then5361:
50797 // SIMD-ONLY0-NEXT:    [[TMP4011:%.*]] = load i64, ptr [[ULLE]], align 8
50798 // SIMD-ONLY0-NEXT:    store i64 [[TMP4011]], ptr [[ULLX]], align 8
50799 // SIMD-ONLY0-NEXT:    br label [[IF_END5362]]
50800 // SIMD-ONLY0:       if.end5362:
50801 // SIMD-ONLY0-NEXT:    [[TMP4012:%.*]] = load i64, ptr [[ULLX]], align 8
50802 // SIMD-ONLY0-NEXT:    store i64 [[TMP4012]], ptr [[ULLV]], align 8
50803 // SIMD-ONLY0-NEXT:    [[TMP4013:%.*]] = load i64, ptr [[ULLX]], align 8
50804 // SIMD-ONLY0-NEXT:    [[TMP4014:%.*]] = load i64, ptr [[ULLE]], align 8
50805 // SIMD-ONLY0-NEXT:    [[CMP5363:%.*]] = icmp eq i64 [[TMP4013]], [[TMP4014]]
50806 // SIMD-ONLY0-NEXT:    br i1 [[CMP5363]], label [[IF_THEN5365:%.*]], label [[IF_END5366:%.*]]
50807 // SIMD-ONLY0:       if.then5365:
50808 // SIMD-ONLY0-NEXT:    [[TMP4015:%.*]] = load i64, ptr [[ULLD]], align 8
50809 // SIMD-ONLY0-NEXT:    store i64 [[TMP4015]], ptr [[ULLX]], align 8
50810 // SIMD-ONLY0-NEXT:    br label [[IF_END5366]]
50811 // SIMD-ONLY0:       if.end5366:
50812 // SIMD-ONLY0-NEXT:    [[TMP4016:%.*]] = load i64, ptr [[ULLX]], align 8
50813 // SIMD-ONLY0-NEXT:    store i64 [[TMP4016]], ptr [[ULLV]], align 8
50814 // SIMD-ONLY0-NEXT:    [[TMP4017:%.*]] = load i64, ptr [[ULLE]], align 8
50815 // SIMD-ONLY0-NEXT:    [[TMP4018:%.*]] = load i64, ptr [[ULLX]], align 8
50816 // SIMD-ONLY0-NEXT:    [[CMP5367:%.*]] = icmp eq i64 [[TMP4017]], [[TMP4018]]
50817 // SIMD-ONLY0-NEXT:    br i1 [[CMP5367]], label [[IF_THEN5369:%.*]], label [[IF_END5370:%.*]]
50818 // SIMD-ONLY0:       if.then5369:
50819 // SIMD-ONLY0-NEXT:    [[TMP4019:%.*]] = load i64, ptr [[ULLD]], align 8
50820 // SIMD-ONLY0-NEXT:    store i64 [[TMP4019]], ptr [[ULLX]], align 8
50821 // SIMD-ONLY0-NEXT:    br label [[IF_END5370]]
50822 // SIMD-ONLY0:       if.end5370:
50823 // SIMD-ONLY0-NEXT:    [[TMP4020:%.*]] = load i64, ptr [[ULLE]], align 8
50824 // SIMD-ONLY0-NEXT:    [[TMP4021:%.*]] = load i64, ptr [[ULLX]], align 8
50825 // SIMD-ONLY0-NEXT:    [[CMP5371:%.*]] = icmp ugt i64 [[TMP4020]], [[TMP4021]]
50826 // SIMD-ONLY0-NEXT:    br i1 [[CMP5371]], label [[IF_THEN5373:%.*]], label [[IF_END5374:%.*]]
50827 // SIMD-ONLY0:       if.then5373:
50828 // SIMD-ONLY0-NEXT:    [[TMP4022:%.*]] = load i64, ptr [[ULLE]], align 8
50829 // SIMD-ONLY0-NEXT:    store i64 [[TMP4022]], ptr [[ULLX]], align 8
50830 // SIMD-ONLY0-NEXT:    br label [[IF_END5374]]
50831 // SIMD-ONLY0:       if.end5374:
50832 // SIMD-ONLY0-NEXT:    [[TMP4023:%.*]] = load i64, ptr [[ULLX]], align 8
50833 // SIMD-ONLY0-NEXT:    store i64 [[TMP4023]], ptr [[ULLV]], align 8
50834 // SIMD-ONLY0-NEXT:    [[TMP4024:%.*]] = load i64, ptr [[ULLX]], align 8
50835 // SIMD-ONLY0-NEXT:    [[TMP4025:%.*]] = load i64, ptr [[ULLE]], align 8
50836 // SIMD-ONLY0-NEXT:    [[CMP5375:%.*]] = icmp ugt i64 [[TMP4024]], [[TMP4025]]
50837 // SIMD-ONLY0-NEXT:    br i1 [[CMP5375]], label [[IF_THEN5377:%.*]], label [[IF_END5378:%.*]]
50838 // SIMD-ONLY0:       if.then5377:
50839 // SIMD-ONLY0-NEXT:    [[TMP4026:%.*]] = load i64, ptr [[ULLE]], align 8
50840 // SIMD-ONLY0-NEXT:    store i64 [[TMP4026]], ptr [[ULLX]], align 8
50841 // SIMD-ONLY0-NEXT:    br label [[IF_END5378]]
50842 // SIMD-ONLY0:       if.end5378:
50843 // SIMD-ONLY0-NEXT:    [[TMP4027:%.*]] = load i64, ptr [[ULLX]], align 8
50844 // SIMD-ONLY0-NEXT:    store i64 [[TMP4027]], ptr [[ULLV]], align 8
50845 // SIMD-ONLY0-NEXT:    [[TMP4028:%.*]] = load i64, ptr [[ULLE]], align 8
50846 // SIMD-ONLY0-NEXT:    [[TMP4029:%.*]] = load i64, ptr [[ULLX]], align 8
50847 // SIMD-ONLY0-NEXT:    [[CMP5379:%.*]] = icmp ult i64 [[TMP4028]], [[TMP4029]]
50848 // SIMD-ONLY0-NEXT:    br i1 [[CMP5379]], label [[IF_THEN5381:%.*]], label [[IF_END5382:%.*]]
50849 // SIMD-ONLY0:       if.then5381:
50850 // SIMD-ONLY0-NEXT:    [[TMP4030:%.*]] = load i64, ptr [[ULLE]], align 8
50851 // SIMD-ONLY0-NEXT:    store i64 [[TMP4030]], ptr [[ULLX]], align 8
50852 // SIMD-ONLY0-NEXT:    br label [[IF_END5382]]
50853 // SIMD-ONLY0:       if.end5382:
50854 // SIMD-ONLY0-NEXT:    [[TMP4031:%.*]] = load i64, ptr [[ULLX]], align 8
50855 // SIMD-ONLY0-NEXT:    store i64 [[TMP4031]], ptr [[ULLV]], align 8
50856 // SIMD-ONLY0-NEXT:    [[TMP4032:%.*]] = load i64, ptr [[ULLX]], align 8
50857 // SIMD-ONLY0-NEXT:    [[TMP4033:%.*]] = load i64, ptr [[ULLE]], align 8
50858 // SIMD-ONLY0-NEXT:    [[CMP5383:%.*]] = icmp ult i64 [[TMP4032]], [[TMP4033]]
50859 // SIMD-ONLY0-NEXT:    br i1 [[CMP5383]], label [[IF_THEN5385:%.*]], label [[IF_END5386:%.*]]
50860 // SIMD-ONLY0:       if.then5385:
50861 // SIMD-ONLY0-NEXT:    [[TMP4034:%.*]] = load i64, ptr [[ULLE]], align 8
50862 // SIMD-ONLY0-NEXT:    store i64 [[TMP4034]], ptr [[ULLX]], align 8
50863 // SIMD-ONLY0-NEXT:    br label [[IF_END5386]]
50864 // SIMD-ONLY0:       if.end5386:
50865 // SIMD-ONLY0-NEXT:    [[TMP4035:%.*]] = load i64, ptr [[ULLX]], align 8
50866 // SIMD-ONLY0-NEXT:    store i64 [[TMP4035]], ptr [[ULLV]], align 8
50867 // SIMD-ONLY0-NEXT:    [[TMP4036:%.*]] = load i64, ptr [[ULLX]], align 8
50868 // SIMD-ONLY0-NEXT:    [[TMP4037:%.*]] = load i64, ptr [[ULLE]], align 8
50869 // SIMD-ONLY0-NEXT:    [[CMP5387:%.*]] = icmp eq i64 [[TMP4036]], [[TMP4037]]
50870 // SIMD-ONLY0-NEXT:    br i1 [[CMP5387]], label [[IF_THEN5389:%.*]], label [[IF_END5390:%.*]]
50871 // SIMD-ONLY0:       if.then5389:
50872 // SIMD-ONLY0-NEXT:    [[TMP4038:%.*]] = load i64, ptr [[ULLD]], align 8
50873 // SIMD-ONLY0-NEXT:    store i64 [[TMP4038]], ptr [[ULLX]], align 8
50874 // SIMD-ONLY0-NEXT:    br label [[IF_END5390]]
50875 // SIMD-ONLY0:       if.end5390:
50876 // SIMD-ONLY0-NEXT:    [[TMP4039:%.*]] = load i64, ptr [[ULLX]], align 8
50877 // SIMD-ONLY0-NEXT:    store i64 [[TMP4039]], ptr [[ULLV]], align 8
50878 // SIMD-ONLY0-NEXT:    [[TMP4040:%.*]] = load i64, ptr [[ULLE]], align 8
50879 // SIMD-ONLY0-NEXT:    [[TMP4041:%.*]] = load i64, ptr [[ULLX]], align 8
50880 // SIMD-ONLY0-NEXT:    [[CMP5391:%.*]] = icmp eq i64 [[TMP4040]], [[TMP4041]]
50881 // SIMD-ONLY0-NEXT:    br i1 [[CMP5391]], label [[IF_THEN5393:%.*]], label [[IF_END5394:%.*]]
50882 // SIMD-ONLY0:       if.then5393:
50883 // SIMD-ONLY0-NEXT:    [[TMP4042:%.*]] = load i64, ptr [[ULLD]], align 8
50884 // SIMD-ONLY0-NEXT:    store i64 [[TMP4042]], ptr [[ULLX]], align 8
50885 // SIMD-ONLY0-NEXT:    br label [[IF_END5394]]
50886 // SIMD-ONLY0:       if.end5394:
50887 // SIMD-ONLY0-NEXT:    [[TMP4043:%.*]] = load i64, ptr [[ULLX]], align 8
50888 // SIMD-ONLY0-NEXT:    store i64 [[TMP4043]], ptr [[ULLV]], align 8
50889 // SIMD-ONLY0-NEXT:    [[TMP4044:%.*]] = load i64, ptr [[ULLX]], align 8
50890 // SIMD-ONLY0-NEXT:    [[TMP4045:%.*]] = load i64, ptr [[ULLE]], align 8
50891 // SIMD-ONLY0-NEXT:    [[CMP5395:%.*]] = icmp eq i64 [[TMP4044]], [[TMP4045]]
50892 // SIMD-ONLY0-NEXT:    br i1 [[CMP5395]], label [[IF_THEN5397:%.*]], label [[IF_ELSE5398:%.*]]
50893 // SIMD-ONLY0:       if.then5397:
50894 // SIMD-ONLY0-NEXT:    [[TMP4046:%.*]] = load i64, ptr [[ULLD]], align 8
50895 // SIMD-ONLY0-NEXT:    store i64 [[TMP4046]], ptr [[ULLX]], align 8
50896 // SIMD-ONLY0-NEXT:    br label [[IF_END5399:%.*]]
50897 // SIMD-ONLY0:       if.else5398:
50898 // SIMD-ONLY0-NEXT:    [[TMP4047:%.*]] = load i64, ptr [[ULLX]], align 8
50899 // SIMD-ONLY0-NEXT:    store i64 [[TMP4047]], ptr [[ULLV]], align 8
50900 // SIMD-ONLY0-NEXT:    br label [[IF_END5399]]
50901 // SIMD-ONLY0:       if.end5399:
50902 // SIMD-ONLY0-NEXT:    [[TMP4048:%.*]] = load i64, ptr [[ULLE]], align 8
50903 // SIMD-ONLY0-NEXT:    [[TMP4049:%.*]] = load i64, ptr [[ULLX]], align 8
50904 // SIMD-ONLY0-NEXT:    [[CMP5400:%.*]] = icmp eq i64 [[TMP4048]], [[TMP4049]]
50905 // SIMD-ONLY0-NEXT:    br i1 [[CMP5400]], label [[IF_THEN5402:%.*]], label [[IF_ELSE5403:%.*]]
50906 // SIMD-ONLY0:       if.then5402:
50907 // SIMD-ONLY0-NEXT:    [[TMP4050:%.*]] = load i64, ptr [[ULLD]], align 8
50908 // SIMD-ONLY0-NEXT:    store i64 [[TMP4050]], ptr [[ULLX]], align 8
50909 // SIMD-ONLY0-NEXT:    br label [[IF_END5404:%.*]]
50910 // SIMD-ONLY0:       if.else5403:
50911 // SIMD-ONLY0-NEXT:    [[TMP4051:%.*]] = load i64, ptr [[ULLX]], align 8
50912 // SIMD-ONLY0-NEXT:    store i64 [[TMP4051]], ptr [[ULLV]], align 8
50913 // SIMD-ONLY0-NEXT:    br label [[IF_END5404]]
50914 // SIMD-ONLY0:       if.end5404:
50915 // SIMD-ONLY0-NEXT:    [[TMP4052:%.*]] = load i64, ptr [[ULLX]], align 8
50916 // SIMD-ONLY0-NEXT:    [[TMP4053:%.*]] = load i64, ptr [[ULLE]], align 8
50917 // SIMD-ONLY0-NEXT:    [[CMP5405:%.*]] = icmp eq i64 [[TMP4052]], [[TMP4053]]
50918 // SIMD-ONLY0-NEXT:    [[CONV5406:%.*]] = zext i1 [[CMP5405]] to i32
50919 // SIMD-ONLY0-NEXT:    [[CONV5407:%.*]] = sext i32 [[CONV5406]] to i64
50920 // SIMD-ONLY0-NEXT:    store i64 [[CONV5407]], ptr [[ULLR]], align 8
50921 // SIMD-ONLY0-NEXT:    [[TMP4054:%.*]] = load i64, ptr [[ULLR]], align 8
50922 // SIMD-ONLY0-NEXT:    [[TOBOOL5408:%.*]] = icmp ne i64 [[TMP4054]], 0
50923 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5408]], label [[IF_THEN5409:%.*]], label [[IF_END5410:%.*]]
50924 // SIMD-ONLY0:       if.then5409:
50925 // SIMD-ONLY0-NEXT:    [[TMP4055:%.*]] = load i64, ptr [[ULLD]], align 8
50926 // SIMD-ONLY0-NEXT:    store i64 [[TMP4055]], ptr [[ULLX]], align 8
50927 // SIMD-ONLY0-NEXT:    br label [[IF_END5410]]
50928 // SIMD-ONLY0:       if.end5410:
50929 // SIMD-ONLY0-NEXT:    [[TMP4056:%.*]] = load i64, ptr [[ULLE]], align 8
50930 // SIMD-ONLY0-NEXT:    [[TMP4057:%.*]] = load i64, ptr [[ULLX]], align 8
50931 // SIMD-ONLY0-NEXT:    [[CMP5411:%.*]] = icmp eq i64 [[TMP4056]], [[TMP4057]]
50932 // SIMD-ONLY0-NEXT:    [[CONV5412:%.*]] = zext i1 [[CMP5411]] to i32
50933 // SIMD-ONLY0-NEXT:    [[CONV5413:%.*]] = sext i32 [[CONV5412]] to i64
50934 // SIMD-ONLY0-NEXT:    store i64 [[CONV5413]], ptr [[ULLR]], align 8
50935 // SIMD-ONLY0-NEXT:    [[TMP4058:%.*]] = load i64, ptr [[ULLR]], align 8
50936 // SIMD-ONLY0-NEXT:    [[TOBOOL5414:%.*]] = icmp ne i64 [[TMP4058]], 0
50937 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5414]], label [[IF_THEN5415:%.*]], label [[IF_END5416:%.*]]
50938 // SIMD-ONLY0:       if.then5415:
50939 // SIMD-ONLY0-NEXT:    [[TMP4059:%.*]] = load i64, ptr [[ULLD]], align 8
50940 // SIMD-ONLY0-NEXT:    store i64 [[TMP4059]], ptr [[ULLX]], align 8
50941 // SIMD-ONLY0-NEXT:    br label [[IF_END5416]]
50942 // SIMD-ONLY0:       if.end5416:
50943 // SIMD-ONLY0-NEXT:    [[TMP4060:%.*]] = load i64, ptr [[ULLX]], align 8
50944 // SIMD-ONLY0-NEXT:    [[TMP4061:%.*]] = load i64, ptr [[ULLE]], align 8
50945 // SIMD-ONLY0-NEXT:    [[CMP5417:%.*]] = icmp eq i64 [[TMP4060]], [[TMP4061]]
50946 // SIMD-ONLY0-NEXT:    [[CONV5418:%.*]] = zext i1 [[CMP5417]] to i32
50947 // SIMD-ONLY0-NEXT:    [[CONV5419:%.*]] = sext i32 [[CONV5418]] to i64
50948 // SIMD-ONLY0-NEXT:    store i64 [[CONV5419]], ptr [[ULLR]], align 8
50949 // SIMD-ONLY0-NEXT:    [[TMP4062:%.*]] = load i64, ptr [[ULLR]], align 8
50950 // SIMD-ONLY0-NEXT:    [[TOBOOL5420:%.*]] = icmp ne i64 [[TMP4062]], 0
50951 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5420]], label [[IF_THEN5421:%.*]], label [[IF_ELSE5422:%.*]]
50952 // SIMD-ONLY0:       if.then5421:
50953 // SIMD-ONLY0-NEXT:    [[TMP4063:%.*]] = load i64, ptr [[ULLD]], align 8
50954 // SIMD-ONLY0-NEXT:    store i64 [[TMP4063]], ptr [[ULLX]], align 8
50955 // SIMD-ONLY0-NEXT:    br label [[IF_END5423:%.*]]
50956 // SIMD-ONLY0:       if.else5422:
50957 // SIMD-ONLY0-NEXT:    [[TMP4064:%.*]] = load i64, ptr [[ULLX]], align 8
50958 // SIMD-ONLY0-NEXT:    store i64 [[TMP4064]], ptr [[ULLV]], align 8
50959 // SIMD-ONLY0-NEXT:    br label [[IF_END5423]]
50960 // SIMD-ONLY0:       if.end5423:
50961 // SIMD-ONLY0-NEXT:    [[TMP4065:%.*]] = load i64, ptr [[ULLE]], align 8
50962 // SIMD-ONLY0-NEXT:    [[TMP4066:%.*]] = load i64, ptr [[ULLX]], align 8
50963 // SIMD-ONLY0-NEXT:    [[CMP5424:%.*]] = icmp eq i64 [[TMP4065]], [[TMP4066]]
50964 // SIMD-ONLY0-NEXT:    [[CONV5425:%.*]] = zext i1 [[CMP5424]] to i32
50965 // SIMD-ONLY0-NEXT:    [[CONV5426:%.*]] = sext i32 [[CONV5425]] to i64
50966 // SIMD-ONLY0-NEXT:    store i64 [[CONV5426]], ptr [[ULLR]], align 8
50967 // SIMD-ONLY0-NEXT:    [[TMP4067:%.*]] = load i64, ptr [[ULLR]], align 8
50968 // SIMD-ONLY0-NEXT:    [[TOBOOL5427:%.*]] = icmp ne i64 [[TMP4067]], 0
50969 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5427]], label [[IF_THEN5428:%.*]], label [[IF_ELSE5429:%.*]]
50970 // SIMD-ONLY0:       if.then5428:
50971 // SIMD-ONLY0-NEXT:    [[TMP4068:%.*]] = load i64, ptr [[ULLD]], align 8
50972 // SIMD-ONLY0-NEXT:    store i64 [[TMP4068]], ptr [[ULLX]], align 8
50973 // SIMD-ONLY0-NEXT:    br label [[IF_END5430:%.*]]
50974 // SIMD-ONLY0:       if.else5429:
50975 // SIMD-ONLY0-NEXT:    [[TMP4069:%.*]] = load i64, ptr [[ULLX]], align 8
50976 // SIMD-ONLY0-NEXT:    store i64 [[TMP4069]], ptr [[ULLV]], align 8
50977 // SIMD-ONLY0-NEXT:    br label [[IF_END5430]]
50978 // SIMD-ONLY0:       if.end5430:
50979 // SIMD-ONLY0-NEXT:    [[TMP4070:%.*]] = load i64, ptr [[ULLX]], align 8
50980 // SIMD-ONLY0-NEXT:    store i64 [[TMP4070]], ptr [[ULLV]], align 8
50981 // SIMD-ONLY0-NEXT:    [[TMP4071:%.*]] = load i64, ptr [[ULLE]], align 8
50982 // SIMD-ONLY0-NEXT:    [[TMP4072:%.*]] = load i64, ptr [[ULLX]], align 8
50983 // SIMD-ONLY0-NEXT:    [[CMP5431:%.*]] = icmp ugt i64 [[TMP4071]], [[TMP4072]]
50984 // SIMD-ONLY0-NEXT:    br i1 [[CMP5431]], label [[IF_THEN5433:%.*]], label [[IF_END5434:%.*]]
50985 // SIMD-ONLY0:       if.then5433:
50986 // SIMD-ONLY0-NEXT:    [[TMP4073:%.*]] = load i64, ptr [[ULLE]], align 8
50987 // SIMD-ONLY0-NEXT:    store i64 [[TMP4073]], ptr [[ULLX]], align 8
50988 // SIMD-ONLY0-NEXT:    br label [[IF_END5434]]
50989 // SIMD-ONLY0:       if.end5434:
50990 // SIMD-ONLY0-NEXT:    [[TMP4074:%.*]] = load i64, ptr [[ULLX]], align 8
50991 // SIMD-ONLY0-NEXT:    store i64 [[TMP4074]], ptr [[ULLV]], align 8
50992 // SIMD-ONLY0-NEXT:    [[TMP4075:%.*]] = load i64, ptr [[ULLX]], align 8
50993 // SIMD-ONLY0-NEXT:    [[TMP4076:%.*]] = load i64, ptr [[ULLE]], align 8
50994 // SIMD-ONLY0-NEXT:    [[CMP5435:%.*]] = icmp ugt i64 [[TMP4075]], [[TMP4076]]
50995 // SIMD-ONLY0-NEXT:    br i1 [[CMP5435]], label [[IF_THEN5437:%.*]], label [[IF_END5438:%.*]]
50996 // SIMD-ONLY0:       if.then5437:
50997 // SIMD-ONLY0-NEXT:    [[TMP4077:%.*]] = load i64, ptr [[ULLE]], align 8
50998 // SIMD-ONLY0-NEXT:    store i64 [[TMP4077]], ptr [[ULLX]], align 8
50999 // SIMD-ONLY0-NEXT:    br label [[IF_END5438]]
51000 // SIMD-ONLY0:       if.end5438:
51001 // SIMD-ONLY0-NEXT:    [[TMP4078:%.*]] = load i64, ptr [[ULLX]], align 8
51002 // SIMD-ONLY0-NEXT:    store i64 [[TMP4078]], ptr [[ULLV]], align 8
51003 // SIMD-ONLY0-NEXT:    [[TMP4079:%.*]] = load i64, ptr [[ULLE]], align 8
51004 // SIMD-ONLY0-NEXT:    [[TMP4080:%.*]] = load i64, ptr [[ULLX]], align 8
51005 // SIMD-ONLY0-NEXT:    [[CMP5439:%.*]] = icmp ult i64 [[TMP4079]], [[TMP4080]]
51006 // SIMD-ONLY0-NEXT:    br i1 [[CMP5439]], label [[IF_THEN5441:%.*]], label [[IF_END5442:%.*]]
51007 // SIMD-ONLY0:       if.then5441:
51008 // SIMD-ONLY0-NEXT:    [[TMP4081:%.*]] = load i64, ptr [[ULLE]], align 8
51009 // SIMD-ONLY0-NEXT:    store i64 [[TMP4081]], ptr [[ULLX]], align 8
51010 // SIMD-ONLY0-NEXT:    br label [[IF_END5442]]
51011 // SIMD-ONLY0:       if.end5442:
51012 // SIMD-ONLY0-NEXT:    [[TMP4082:%.*]] = load i64, ptr [[ULLX]], align 8
51013 // SIMD-ONLY0-NEXT:    store i64 [[TMP4082]], ptr [[ULLV]], align 8
51014 // SIMD-ONLY0-NEXT:    [[TMP4083:%.*]] = load i64, ptr [[ULLX]], align 8
51015 // SIMD-ONLY0-NEXT:    [[TMP4084:%.*]] = load i64, ptr [[ULLE]], align 8
51016 // SIMD-ONLY0-NEXT:    [[CMP5443:%.*]] = icmp ult i64 [[TMP4083]], [[TMP4084]]
51017 // SIMD-ONLY0-NEXT:    br i1 [[CMP5443]], label [[IF_THEN5445:%.*]], label [[IF_END5446:%.*]]
51018 // SIMD-ONLY0:       if.then5445:
51019 // SIMD-ONLY0-NEXT:    [[TMP4085:%.*]] = load i64, ptr [[ULLE]], align 8
51020 // SIMD-ONLY0-NEXT:    store i64 [[TMP4085]], ptr [[ULLX]], align 8
51021 // SIMD-ONLY0-NEXT:    br label [[IF_END5446]]
51022 // SIMD-ONLY0:       if.end5446:
51023 // SIMD-ONLY0-NEXT:    [[TMP4086:%.*]] = load i64, ptr [[ULLX]], align 8
51024 // SIMD-ONLY0-NEXT:    store i64 [[TMP4086]], ptr [[ULLV]], align 8
51025 // SIMD-ONLY0-NEXT:    [[TMP4087:%.*]] = load i64, ptr [[ULLX]], align 8
51026 // SIMD-ONLY0-NEXT:    [[TMP4088:%.*]] = load i64, ptr [[ULLE]], align 8
51027 // SIMD-ONLY0-NEXT:    [[CMP5447:%.*]] = icmp eq i64 [[TMP4087]], [[TMP4088]]
51028 // SIMD-ONLY0-NEXT:    br i1 [[CMP5447]], label [[IF_THEN5449:%.*]], label [[IF_END5450:%.*]]
51029 // SIMD-ONLY0:       if.then5449:
51030 // SIMD-ONLY0-NEXT:    [[TMP4089:%.*]] = load i64, ptr [[ULLD]], align 8
51031 // SIMD-ONLY0-NEXT:    store i64 [[TMP4089]], ptr [[ULLX]], align 8
51032 // SIMD-ONLY0-NEXT:    br label [[IF_END5450]]
51033 // SIMD-ONLY0:       if.end5450:
51034 // SIMD-ONLY0-NEXT:    [[TMP4090:%.*]] = load i64, ptr [[ULLX]], align 8
51035 // SIMD-ONLY0-NEXT:    store i64 [[TMP4090]], ptr [[ULLV]], align 8
51036 // SIMD-ONLY0-NEXT:    [[TMP4091:%.*]] = load i64, ptr [[ULLE]], align 8
51037 // SIMD-ONLY0-NEXT:    [[TMP4092:%.*]] = load i64, ptr [[ULLX]], align 8
51038 // SIMD-ONLY0-NEXT:    [[CMP5451:%.*]] = icmp eq i64 [[TMP4091]], [[TMP4092]]
51039 // SIMD-ONLY0-NEXT:    br i1 [[CMP5451]], label [[IF_THEN5453:%.*]], label [[IF_END5454:%.*]]
51040 // SIMD-ONLY0:       if.then5453:
51041 // SIMD-ONLY0-NEXT:    [[TMP4093:%.*]] = load i64, ptr [[ULLD]], align 8
51042 // SIMD-ONLY0-NEXT:    store i64 [[TMP4093]], ptr [[ULLX]], align 8
51043 // SIMD-ONLY0-NEXT:    br label [[IF_END5454]]
51044 // SIMD-ONLY0:       if.end5454:
51045 // SIMD-ONLY0-NEXT:    [[TMP4094:%.*]] = load i64, ptr [[ULLE]], align 8
51046 // SIMD-ONLY0-NEXT:    [[TMP4095:%.*]] = load i64, ptr [[ULLX]], align 8
51047 // SIMD-ONLY0-NEXT:    [[CMP5455:%.*]] = icmp ugt i64 [[TMP4094]], [[TMP4095]]
51048 // SIMD-ONLY0-NEXT:    br i1 [[CMP5455]], label [[IF_THEN5457:%.*]], label [[IF_END5458:%.*]]
51049 // SIMD-ONLY0:       if.then5457:
51050 // SIMD-ONLY0-NEXT:    [[TMP4096:%.*]] = load i64, ptr [[ULLE]], align 8
51051 // SIMD-ONLY0-NEXT:    store i64 [[TMP4096]], ptr [[ULLX]], align 8
51052 // SIMD-ONLY0-NEXT:    br label [[IF_END5458]]
51053 // SIMD-ONLY0:       if.end5458:
51054 // SIMD-ONLY0-NEXT:    [[TMP4097:%.*]] = load i64, ptr [[ULLX]], align 8
51055 // SIMD-ONLY0-NEXT:    store i64 [[TMP4097]], ptr [[ULLV]], align 8
51056 // SIMD-ONLY0-NEXT:    [[TMP4098:%.*]] = load i64, ptr [[ULLX]], align 8
51057 // SIMD-ONLY0-NEXT:    [[TMP4099:%.*]] = load i64, ptr [[ULLE]], align 8
51058 // SIMD-ONLY0-NEXT:    [[CMP5459:%.*]] = icmp ugt i64 [[TMP4098]], [[TMP4099]]
51059 // SIMD-ONLY0-NEXT:    br i1 [[CMP5459]], label [[IF_THEN5461:%.*]], label [[IF_END5462:%.*]]
51060 // SIMD-ONLY0:       if.then5461:
51061 // SIMD-ONLY0-NEXT:    [[TMP4100:%.*]] = load i64, ptr [[ULLE]], align 8
51062 // SIMD-ONLY0-NEXT:    store i64 [[TMP4100]], ptr [[ULLX]], align 8
51063 // SIMD-ONLY0-NEXT:    br label [[IF_END5462]]
51064 // SIMD-ONLY0:       if.end5462:
51065 // SIMD-ONLY0-NEXT:    [[TMP4101:%.*]] = load i64, ptr [[ULLX]], align 8
51066 // SIMD-ONLY0-NEXT:    store i64 [[TMP4101]], ptr [[ULLV]], align 8
51067 // SIMD-ONLY0-NEXT:    [[TMP4102:%.*]] = load i64, ptr [[ULLE]], align 8
51068 // SIMD-ONLY0-NEXT:    [[TMP4103:%.*]] = load i64, ptr [[ULLX]], align 8
51069 // SIMD-ONLY0-NEXT:    [[CMP5463:%.*]] = icmp ult i64 [[TMP4102]], [[TMP4103]]
51070 // SIMD-ONLY0-NEXT:    br i1 [[CMP5463]], label [[IF_THEN5465:%.*]], label [[IF_END5466:%.*]]
51071 // SIMD-ONLY0:       if.then5465:
51072 // SIMD-ONLY0-NEXT:    [[TMP4104:%.*]] = load i64, ptr [[ULLE]], align 8
51073 // SIMD-ONLY0-NEXT:    store i64 [[TMP4104]], ptr [[ULLX]], align 8
51074 // SIMD-ONLY0-NEXT:    br label [[IF_END5466]]
51075 // SIMD-ONLY0:       if.end5466:
51076 // SIMD-ONLY0-NEXT:    [[TMP4105:%.*]] = load i64, ptr [[ULLX]], align 8
51077 // SIMD-ONLY0-NEXT:    store i64 [[TMP4105]], ptr [[ULLV]], align 8
51078 // SIMD-ONLY0-NEXT:    [[TMP4106:%.*]] = load i64, ptr [[ULLX]], align 8
51079 // SIMD-ONLY0-NEXT:    [[TMP4107:%.*]] = load i64, ptr [[ULLE]], align 8
51080 // SIMD-ONLY0-NEXT:    [[CMP5467:%.*]] = icmp ult i64 [[TMP4106]], [[TMP4107]]
51081 // SIMD-ONLY0-NEXT:    br i1 [[CMP5467]], label [[IF_THEN5469:%.*]], label [[IF_END5470:%.*]]
51082 // SIMD-ONLY0:       if.then5469:
51083 // SIMD-ONLY0-NEXT:    [[TMP4108:%.*]] = load i64, ptr [[ULLE]], align 8
51084 // SIMD-ONLY0-NEXT:    store i64 [[TMP4108]], ptr [[ULLX]], align 8
51085 // SIMD-ONLY0-NEXT:    br label [[IF_END5470]]
51086 // SIMD-ONLY0:       if.end5470:
51087 // SIMD-ONLY0-NEXT:    [[TMP4109:%.*]] = load i64, ptr [[ULLX]], align 8
51088 // SIMD-ONLY0-NEXT:    store i64 [[TMP4109]], ptr [[ULLV]], align 8
51089 // SIMD-ONLY0-NEXT:    [[TMP4110:%.*]] = load i64, ptr [[ULLX]], align 8
51090 // SIMD-ONLY0-NEXT:    [[TMP4111:%.*]] = load i64, ptr [[ULLE]], align 8
51091 // SIMD-ONLY0-NEXT:    [[CMP5471:%.*]] = icmp eq i64 [[TMP4110]], [[TMP4111]]
51092 // SIMD-ONLY0-NEXT:    br i1 [[CMP5471]], label [[IF_THEN5473:%.*]], label [[IF_END5474:%.*]]
51093 // SIMD-ONLY0:       if.then5473:
51094 // SIMD-ONLY0-NEXT:    [[TMP4112:%.*]] = load i64, ptr [[ULLD]], align 8
51095 // SIMD-ONLY0-NEXT:    store i64 [[TMP4112]], ptr [[ULLX]], align 8
51096 // SIMD-ONLY0-NEXT:    br label [[IF_END5474]]
51097 // SIMD-ONLY0:       if.end5474:
51098 // SIMD-ONLY0-NEXT:    [[TMP4113:%.*]] = load i64, ptr [[ULLX]], align 8
51099 // SIMD-ONLY0-NEXT:    store i64 [[TMP4113]], ptr [[ULLV]], align 8
51100 // SIMD-ONLY0-NEXT:    [[TMP4114:%.*]] = load i64, ptr [[ULLE]], align 8
51101 // SIMD-ONLY0-NEXT:    [[TMP4115:%.*]] = load i64, ptr [[ULLX]], align 8
51102 // SIMD-ONLY0-NEXT:    [[CMP5475:%.*]] = icmp eq i64 [[TMP4114]], [[TMP4115]]
51103 // SIMD-ONLY0-NEXT:    br i1 [[CMP5475]], label [[IF_THEN5477:%.*]], label [[IF_END5478:%.*]]
51104 // SIMD-ONLY0:       if.then5477:
51105 // SIMD-ONLY0-NEXT:    [[TMP4116:%.*]] = load i64, ptr [[ULLD]], align 8
51106 // SIMD-ONLY0-NEXT:    store i64 [[TMP4116]], ptr [[ULLX]], align 8
51107 // SIMD-ONLY0-NEXT:    br label [[IF_END5478]]
51108 // SIMD-ONLY0:       if.end5478:
51109 // SIMD-ONLY0-NEXT:    [[TMP4117:%.*]] = load i64, ptr [[ULLX]], align 8
51110 // SIMD-ONLY0-NEXT:    store i64 [[TMP4117]], ptr [[ULLV]], align 8
51111 // SIMD-ONLY0-NEXT:    [[TMP4118:%.*]] = load i64, ptr [[ULLX]], align 8
51112 // SIMD-ONLY0-NEXT:    [[TMP4119:%.*]] = load i64, ptr [[ULLE]], align 8
51113 // SIMD-ONLY0-NEXT:    [[CMP5479:%.*]] = icmp eq i64 [[TMP4118]], [[TMP4119]]
51114 // SIMD-ONLY0-NEXT:    br i1 [[CMP5479]], label [[IF_THEN5481:%.*]], label [[IF_ELSE5482:%.*]]
51115 // SIMD-ONLY0:       if.then5481:
51116 // SIMD-ONLY0-NEXT:    [[TMP4120:%.*]] = load i64, ptr [[ULLD]], align 8
51117 // SIMD-ONLY0-NEXT:    store i64 [[TMP4120]], ptr [[ULLX]], align 8
51118 // SIMD-ONLY0-NEXT:    br label [[IF_END5483:%.*]]
51119 // SIMD-ONLY0:       if.else5482:
51120 // SIMD-ONLY0-NEXT:    [[TMP4121:%.*]] = load i64, ptr [[ULLX]], align 8
51121 // SIMD-ONLY0-NEXT:    store i64 [[TMP4121]], ptr [[ULLV]], align 8
51122 // SIMD-ONLY0-NEXT:    br label [[IF_END5483]]
51123 // SIMD-ONLY0:       if.end5483:
51124 // SIMD-ONLY0-NEXT:    [[TMP4122:%.*]] = load i64, ptr [[ULLE]], align 8
51125 // SIMD-ONLY0-NEXT:    [[TMP4123:%.*]] = load i64, ptr [[ULLX]], align 8
51126 // SIMD-ONLY0-NEXT:    [[CMP5484:%.*]] = icmp eq i64 [[TMP4122]], [[TMP4123]]
51127 // SIMD-ONLY0-NEXT:    br i1 [[CMP5484]], label [[IF_THEN5486:%.*]], label [[IF_ELSE5487:%.*]]
51128 // SIMD-ONLY0:       if.then5486:
51129 // SIMD-ONLY0-NEXT:    [[TMP4124:%.*]] = load i64, ptr [[ULLD]], align 8
51130 // SIMD-ONLY0-NEXT:    store i64 [[TMP4124]], ptr [[ULLX]], align 8
51131 // SIMD-ONLY0-NEXT:    br label [[IF_END5488:%.*]]
51132 // SIMD-ONLY0:       if.else5487:
51133 // SIMD-ONLY0-NEXT:    [[TMP4125:%.*]] = load i64, ptr [[ULLX]], align 8
51134 // SIMD-ONLY0-NEXT:    store i64 [[TMP4125]], ptr [[ULLV]], align 8
51135 // SIMD-ONLY0-NEXT:    br label [[IF_END5488]]
51136 // SIMD-ONLY0:       if.end5488:
51137 // SIMD-ONLY0-NEXT:    [[TMP4126:%.*]] = load i64, ptr [[ULLX]], align 8
51138 // SIMD-ONLY0-NEXT:    [[TMP4127:%.*]] = load i64, ptr [[ULLE]], align 8
51139 // SIMD-ONLY0-NEXT:    [[CMP5489:%.*]] = icmp eq i64 [[TMP4126]], [[TMP4127]]
51140 // SIMD-ONLY0-NEXT:    [[CONV5490:%.*]] = zext i1 [[CMP5489]] to i32
51141 // SIMD-ONLY0-NEXT:    [[CONV5491:%.*]] = sext i32 [[CONV5490]] to i64
51142 // SIMD-ONLY0-NEXT:    store i64 [[CONV5491]], ptr [[ULLR]], align 8
51143 // SIMD-ONLY0-NEXT:    [[TMP4128:%.*]] = load i64, ptr [[ULLR]], align 8
51144 // SIMD-ONLY0-NEXT:    [[TOBOOL5492:%.*]] = icmp ne i64 [[TMP4128]], 0
51145 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5492]], label [[IF_THEN5493:%.*]], label [[IF_END5494:%.*]]
51146 // SIMD-ONLY0:       if.then5493:
51147 // SIMD-ONLY0-NEXT:    [[TMP4129:%.*]] = load i64, ptr [[ULLD]], align 8
51148 // SIMD-ONLY0-NEXT:    store i64 [[TMP4129]], ptr [[ULLX]], align 8
51149 // SIMD-ONLY0-NEXT:    br label [[IF_END5494]]
51150 // SIMD-ONLY0:       if.end5494:
51151 // SIMD-ONLY0-NEXT:    [[TMP4130:%.*]] = load i64, ptr [[ULLE]], align 8
51152 // SIMD-ONLY0-NEXT:    [[TMP4131:%.*]] = load i64, ptr [[ULLX]], align 8
51153 // SIMD-ONLY0-NEXT:    [[CMP5495:%.*]] = icmp eq i64 [[TMP4130]], [[TMP4131]]
51154 // SIMD-ONLY0-NEXT:    [[CONV5496:%.*]] = zext i1 [[CMP5495]] to i32
51155 // SIMD-ONLY0-NEXT:    [[CONV5497:%.*]] = sext i32 [[CONV5496]] to i64
51156 // SIMD-ONLY0-NEXT:    store i64 [[CONV5497]], ptr [[ULLR]], align 8
51157 // SIMD-ONLY0-NEXT:    [[TMP4132:%.*]] = load i64, ptr [[ULLR]], align 8
51158 // SIMD-ONLY0-NEXT:    [[TOBOOL5498:%.*]] = icmp ne i64 [[TMP4132]], 0
51159 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5498]], label [[IF_THEN5499:%.*]], label [[IF_END5500:%.*]]
51160 // SIMD-ONLY0:       if.then5499:
51161 // SIMD-ONLY0-NEXT:    [[TMP4133:%.*]] = load i64, ptr [[ULLD]], align 8
51162 // SIMD-ONLY0-NEXT:    store i64 [[TMP4133]], ptr [[ULLX]], align 8
51163 // SIMD-ONLY0-NEXT:    br label [[IF_END5500]]
51164 // SIMD-ONLY0:       if.end5500:
51165 // SIMD-ONLY0-NEXT:    [[TMP4134:%.*]] = load i64, ptr [[ULLX]], align 8
51166 // SIMD-ONLY0-NEXT:    [[TMP4135:%.*]] = load i64, ptr [[ULLE]], align 8
51167 // SIMD-ONLY0-NEXT:    [[CMP5501:%.*]] = icmp eq i64 [[TMP4134]], [[TMP4135]]
51168 // SIMD-ONLY0-NEXT:    [[CONV5502:%.*]] = zext i1 [[CMP5501]] to i32
51169 // SIMD-ONLY0-NEXT:    [[CONV5503:%.*]] = sext i32 [[CONV5502]] to i64
51170 // SIMD-ONLY0-NEXT:    store i64 [[CONV5503]], ptr [[ULLR]], align 8
51171 // SIMD-ONLY0-NEXT:    [[TMP4136:%.*]] = load i64, ptr [[ULLR]], align 8
51172 // SIMD-ONLY0-NEXT:    [[TOBOOL5504:%.*]] = icmp ne i64 [[TMP4136]], 0
51173 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5504]], label [[IF_THEN5505:%.*]], label [[IF_ELSE5506:%.*]]
51174 // SIMD-ONLY0:       if.then5505:
51175 // SIMD-ONLY0-NEXT:    [[TMP4137:%.*]] = load i64, ptr [[ULLD]], align 8
51176 // SIMD-ONLY0-NEXT:    store i64 [[TMP4137]], ptr [[ULLX]], align 8
51177 // SIMD-ONLY0-NEXT:    br label [[IF_END5507:%.*]]
51178 // SIMD-ONLY0:       if.else5506:
51179 // SIMD-ONLY0-NEXT:    [[TMP4138:%.*]] = load i64, ptr [[ULLX]], align 8
51180 // SIMD-ONLY0-NEXT:    store i64 [[TMP4138]], ptr [[ULLV]], align 8
51181 // SIMD-ONLY0-NEXT:    br label [[IF_END5507]]
51182 // SIMD-ONLY0:       if.end5507:
51183 // SIMD-ONLY0-NEXT:    [[TMP4139:%.*]] = load i64, ptr [[ULLE]], align 8
51184 // SIMD-ONLY0-NEXT:    [[TMP4140:%.*]] = load i64, ptr [[ULLX]], align 8
51185 // SIMD-ONLY0-NEXT:    [[CMP5508:%.*]] = icmp eq i64 [[TMP4139]], [[TMP4140]]
51186 // SIMD-ONLY0-NEXT:    [[CONV5509:%.*]] = zext i1 [[CMP5508]] to i32
51187 // SIMD-ONLY0-NEXT:    [[CONV5510:%.*]] = sext i32 [[CONV5509]] to i64
51188 // SIMD-ONLY0-NEXT:    store i64 [[CONV5510]], ptr [[ULLR]], align 8
51189 // SIMD-ONLY0-NEXT:    [[TMP4141:%.*]] = load i64, ptr [[ULLR]], align 8
51190 // SIMD-ONLY0-NEXT:    [[TOBOOL5511:%.*]] = icmp ne i64 [[TMP4141]], 0
51191 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5511]], label [[IF_THEN5512:%.*]], label [[IF_ELSE5513:%.*]]
51192 // SIMD-ONLY0:       if.then5512:
51193 // SIMD-ONLY0-NEXT:    [[TMP4142:%.*]] = load i64, ptr [[ULLD]], align 8
51194 // SIMD-ONLY0-NEXT:    store i64 [[TMP4142]], ptr [[ULLX]], align 8
51195 // SIMD-ONLY0-NEXT:    br label [[IF_END5514:%.*]]
51196 // SIMD-ONLY0:       if.else5513:
51197 // SIMD-ONLY0-NEXT:    [[TMP4143:%.*]] = load i64, ptr [[ULLX]], align 8
51198 // SIMD-ONLY0-NEXT:    store i64 [[TMP4143]], ptr [[ULLV]], align 8
51199 // SIMD-ONLY0-NEXT:    br label [[IF_END5514]]
51200 // SIMD-ONLY0:       if.end5514:
51201 // SIMD-ONLY0-NEXT:    [[TMP4144:%.*]] = load i64, ptr [[ULLX]], align 8
51202 // SIMD-ONLY0-NEXT:    store i64 [[TMP4144]], ptr [[ULLV]], align 8
51203 // SIMD-ONLY0-NEXT:    [[TMP4145:%.*]] = load i64, ptr [[ULLE]], align 8
51204 // SIMD-ONLY0-NEXT:    [[TMP4146:%.*]] = load i64, ptr [[ULLX]], align 8
51205 // SIMD-ONLY0-NEXT:    [[CMP5515:%.*]] = icmp ugt i64 [[TMP4145]], [[TMP4146]]
51206 // SIMD-ONLY0-NEXT:    br i1 [[CMP5515]], label [[IF_THEN5517:%.*]], label [[IF_END5518:%.*]]
51207 // SIMD-ONLY0:       if.then5517:
51208 // SIMD-ONLY0-NEXT:    [[TMP4147:%.*]] = load i64, ptr [[ULLE]], align 8
51209 // SIMD-ONLY0-NEXT:    store i64 [[TMP4147]], ptr [[ULLX]], align 8
51210 // SIMD-ONLY0-NEXT:    br label [[IF_END5518]]
51211 // SIMD-ONLY0:       if.end5518:
51212 // SIMD-ONLY0-NEXT:    [[TMP4148:%.*]] = load i64, ptr [[ULLX]], align 8
51213 // SIMD-ONLY0-NEXT:    store i64 [[TMP4148]], ptr [[ULLV]], align 8
51214 // SIMD-ONLY0-NEXT:    [[TMP4149:%.*]] = load i64, ptr [[ULLX]], align 8
51215 // SIMD-ONLY0-NEXT:    [[TMP4150:%.*]] = load i64, ptr [[ULLE]], align 8
51216 // SIMD-ONLY0-NEXT:    [[CMP5519:%.*]] = icmp ugt i64 [[TMP4149]], [[TMP4150]]
51217 // SIMD-ONLY0-NEXT:    br i1 [[CMP5519]], label [[IF_THEN5521:%.*]], label [[IF_END5522:%.*]]
51218 // SIMD-ONLY0:       if.then5521:
51219 // SIMD-ONLY0-NEXT:    [[TMP4151:%.*]] = load i64, ptr [[ULLE]], align 8
51220 // SIMD-ONLY0-NEXT:    store i64 [[TMP4151]], ptr [[ULLX]], align 8
51221 // SIMD-ONLY0-NEXT:    br label [[IF_END5522]]
51222 // SIMD-ONLY0:       if.end5522:
51223 // SIMD-ONLY0-NEXT:    [[TMP4152:%.*]] = load i64, ptr [[ULLX]], align 8
51224 // SIMD-ONLY0-NEXT:    store i64 [[TMP4152]], ptr [[ULLV]], align 8
51225 // SIMD-ONLY0-NEXT:    [[TMP4153:%.*]] = load i64, ptr [[ULLE]], align 8
51226 // SIMD-ONLY0-NEXT:    [[TMP4154:%.*]] = load i64, ptr [[ULLX]], align 8
51227 // SIMD-ONLY0-NEXT:    [[CMP5523:%.*]] = icmp ult i64 [[TMP4153]], [[TMP4154]]
51228 // SIMD-ONLY0-NEXT:    br i1 [[CMP5523]], label [[IF_THEN5525:%.*]], label [[IF_END5526:%.*]]
51229 // SIMD-ONLY0:       if.then5525:
51230 // SIMD-ONLY0-NEXT:    [[TMP4155:%.*]] = load i64, ptr [[ULLE]], align 8
51231 // SIMD-ONLY0-NEXT:    store i64 [[TMP4155]], ptr [[ULLX]], align 8
51232 // SIMD-ONLY0-NEXT:    br label [[IF_END5526]]
51233 // SIMD-ONLY0:       if.end5526:
51234 // SIMD-ONLY0-NEXT:    [[TMP4156:%.*]] = load i64, ptr [[ULLX]], align 8
51235 // SIMD-ONLY0-NEXT:    store i64 [[TMP4156]], ptr [[ULLV]], align 8
51236 // SIMD-ONLY0-NEXT:    [[TMP4157:%.*]] = load i64, ptr [[ULLX]], align 8
51237 // SIMD-ONLY0-NEXT:    [[TMP4158:%.*]] = load i64, ptr [[ULLE]], align 8
51238 // SIMD-ONLY0-NEXT:    [[CMP5527:%.*]] = icmp ult i64 [[TMP4157]], [[TMP4158]]
51239 // SIMD-ONLY0-NEXT:    br i1 [[CMP5527]], label [[IF_THEN5529:%.*]], label [[IF_END5530:%.*]]
51240 // SIMD-ONLY0:       if.then5529:
51241 // SIMD-ONLY0-NEXT:    [[TMP4159:%.*]] = load i64, ptr [[ULLE]], align 8
51242 // SIMD-ONLY0-NEXT:    store i64 [[TMP4159]], ptr [[ULLX]], align 8
51243 // SIMD-ONLY0-NEXT:    br label [[IF_END5530]]
51244 // SIMD-ONLY0:       if.end5530:
51245 // SIMD-ONLY0-NEXT:    [[TMP4160:%.*]] = load i64, ptr [[ULLX]], align 8
51246 // SIMD-ONLY0-NEXT:    store i64 [[TMP4160]], ptr [[ULLV]], align 8
51247 // SIMD-ONLY0-NEXT:    [[TMP4161:%.*]] = load i64, ptr [[ULLX]], align 8
51248 // SIMD-ONLY0-NEXT:    [[TMP4162:%.*]] = load i64, ptr [[ULLE]], align 8
51249 // SIMD-ONLY0-NEXT:    [[CMP5531:%.*]] = icmp eq i64 [[TMP4161]], [[TMP4162]]
51250 // SIMD-ONLY0-NEXT:    br i1 [[CMP5531]], label [[IF_THEN5533:%.*]], label [[IF_END5534:%.*]]
51251 // SIMD-ONLY0:       if.then5533:
51252 // SIMD-ONLY0-NEXT:    [[TMP4163:%.*]] = load i64, ptr [[ULLD]], align 8
51253 // SIMD-ONLY0-NEXT:    store i64 [[TMP4163]], ptr [[ULLX]], align 8
51254 // SIMD-ONLY0-NEXT:    br label [[IF_END5534]]
51255 // SIMD-ONLY0:       if.end5534:
51256 // SIMD-ONLY0-NEXT:    [[TMP4164:%.*]] = load i64, ptr [[ULLX]], align 8
51257 // SIMD-ONLY0-NEXT:    store i64 [[TMP4164]], ptr [[ULLV]], align 8
51258 // SIMD-ONLY0-NEXT:    [[TMP4165:%.*]] = load i64, ptr [[ULLE]], align 8
51259 // SIMD-ONLY0-NEXT:    [[TMP4166:%.*]] = load i64, ptr [[ULLX]], align 8
51260 // SIMD-ONLY0-NEXT:    [[CMP5535:%.*]] = icmp eq i64 [[TMP4165]], [[TMP4166]]
51261 // SIMD-ONLY0-NEXT:    br i1 [[CMP5535]], label [[IF_THEN5537:%.*]], label [[IF_END5538:%.*]]
51262 // SIMD-ONLY0:       if.then5537:
51263 // SIMD-ONLY0-NEXT:    [[TMP4167:%.*]] = load i64, ptr [[ULLD]], align 8
51264 // SIMD-ONLY0-NEXT:    store i64 [[TMP4167]], ptr [[ULLX]], align 8
51265 // SIMD-ONLY0-NEXT:    br label [[IF_END5538]]
51266 // SIMD-ONLY0:       if.end5538:
51267 // SIMD-ONLY0-NEXT:    [[TMP4168:%.*]] = load i64, ptr [[ULLE]], align 8
51268 // SIMD-ONLY0-NEXT:    [[TMP4169:%.*]] = load i64, ptr [[ULLX]], align 8
51269 // SIMD-ONLY0-NEXT:    [[CMP5539:%.*]] = icmp ugt i64 [[TMP4168]], [[TMP4169]]
51270 // SIMD-ONLY0-NEXT:    br i1 [[CMP5539]], label [[IF_THEN5541:%.*]], label [[IF_END5542:%.*]]
51271 // SIMD-ONLY0:       if.then5541:
51272 // SIMD-ONLY0-NEXT:    [[TMP4170:%.*]] = load i64, ptr [[ULLE]], align 8
51273 // SIMD-ONLY0-NEXT:    store i64 [[TMP4170]], ptr [[ULLX]], align 8
51274 // SIMD-ONLY0-NEXT:    br label [[IF_END5542]]
51275 // SIMD-ONLY0:       if.end5542:
51276 // SIMD-ONLY0-NEXT:    [[TMP4171:%.*]] = load i64, ptr [[ULLX]], align 8
51277 // SIMD-ONLY0-NEXT:    store i64 [[TMP4171]], ptr [[ULLV]], align 8
51278 // SIMD-ONLY0-NEXT:    [[TMP4172:%.*]] = load i64, ptr [[ULLX]], align 8
51279 // SIMD-ONLY0-NEXT:    [[TMP4173:%.*]] = load i64, ptr [[ULLE]], align 8
51280 // SIMD-ONLY0-NEXT:    [[CMP5543:%.*]] = icmp ugt i64 [[TMP4172]], [[TMP4173]]
51281 // SIMD-ONLY0-NEXT:    br i1 [[CMP5543]], label [[IF_THEN5545:%.*]], label [[IF_END5546:%.*]]
51282 // SIMD-ONLY0:       if.then5545:
51283 // SIMD-ONLY0-NEXT:    [[TMP4174:%.*]] = load i64, ptr [[ULLE]], align 8
51284 // SIMD-ONLY0-NEXT:    store i64 [[TMP4174]], ptr [[ULLX]], align 8
51285 // SIMD-ONLY0-NEXT:    br label [[IF_END5546]]
51286 // SIMD-ONLY0:       if.end5546:
51287 // SIMD-ONLY0-NEXT:    [[TMP4175:%.*]] = load i64, ptr [[ULLX]], align 8
51288 // SIMD-ONLY0-NEXT:    store i64 [[TMP4175]], ptr [[ULLV]], align 8
51289 // SIMD-ONLY0-NEXT:    [[TMP4176:%.*]] = load i64, ptr [[ULLE]], align 8
51290 // SIMD-ONLY0-NEXT:    [[TMP4177:%.*]] = load i64, ptr [[ULLX]], align 8
51291 // SIMD-ONLY0-NEXT:    [[CMP5547:%.*]] = icmp ult i64 [[TMP4176]], [[TMP4177]]
51292 // SIMD-ONLY0-NEXT:    br i1 [[CMP5547]], label [[IF_THEN5549:%.*]], label [[IF_END5550:%.*]]
51293 // SIMD-ONLY0:       if.then5549:
51294 // SIMD-ONLY0-NEXT:    [[TMP4178:%.*]] = load i64, ptr [[ULLE]], align 8
51295 // SIMD-ONLY0-NEXT:    store i64 [[TMP4178]], ptr [[ULLX]], align 8
51296 // SIMD-ONLY0-NEXT:    br label [[IF_END5550]]
51297 // SIMD-ONLY0:       if.end5550:
51298 // SIMD-ONLY0-NEXT:    [[TMP4179:%.*]] = load i64, ptr [[ULLX]], align 8
51299 // SIMD-ONLY0-NEXT:    store i64 [[TMP4179]], ptr [[ULLV]], align 8
51300 // SIMD-ONLY0-NEXT:    [[TMP4180:%.*]] = load i64, ptr [[ULLX]], align 8
51301 // SIMD-ONLY0-NEXT:    [[TMP4181:%.*]] = load i64, ptr [[ULLE]], align 8
51302 // SIMD-ONLY0-NEXT:    [[CMP5551:%.*]] = icmp ult i64 [[TMP4180]], [[TMP4181]]
51303 // SIMD-ONLY0-NEXT:    br i1 [[CMP5551]], label [[IF_THEN5553:%.*]], label [[IF_END5554:%.*]]
51304 // SIMD-ONLY0:       if.then5553:
51305 // SIMD-ONLY0-NEXT:    [[TMP4182:%.*]] = load i64, ptr [[ULLE]], align 8
51306 // SIMD-ONLY0-NEXT:    store i64 [[TMP4182]], ptr [[ULLX]], align 8
51307 // SIMD-ONLY0-NEXT:    br label [[IF_END5554]]
51308 // SIMD-ONLY0:       if.end5554:
51309 // SIMD-ONLY0-NEXT:    [[TMP4183:%.*]] = load i64, ptr [[ULLX]], align 8
51310 // SIMD-ONLY0-NEXT:    store i64 [[TMP4183]], ptr [[ULLV]], align 8
51311 // SIMD-ONLY0-NEXT:    [[TMP4184:%.*]] = load i64, ptr [[ULLX]], align 8
51312 // SIMD-ONLY0-NEXT:    [[TMP4185:%.*]] = load i64, ptr [[ULLE]], align 8
51313 // SIMD-ONLY0-NEXT:    [[CMP5555:%.*]] = icmp eq i64 [[TMP4184]], [[TMP4185]]
51314 // SIMD-ONLY0-NEXT:    br i1 [[CMP5555]], label [[IF_THEN5557:%.*]], label [[IF_END5558:%.*]]
51315 // SIMD-ONLY0:       if.then5557:
51316 // SIMD-ONLY0-NEXT:    [[TMP4186:%.*]] = load i64, ptr [[ULLD]], align 8
51317 // SIMD-ONLY0-NEXT:    store i64 [[TMP4186]], ptr [[ULLX]], align 8
51318 // SIMD-ONLY0-NEXT:    br label [[IF_END5558]]
51319 // SIMD-ONLY0:       if.end5558:
51320 // SIMD-ONLY0-NEXT:    [[TMP4187:%.*]] = load i64, ptr [[ULLX]], align 8
51321 // SIMD-ONLY0-NEXT:    store i64 [[TMP4187]], ptr [[ULLV]], align 8
51322 // SIMD-ONLY0-NEXT:    [[TMP4188:%.*]] = load i64, ptr [[ULLE]], align 8
51323 // SIMD-ONLY0-NEXT:    [[TMP4189:%.*]] = load i64, ptr [[ULLX]], align 8
51324 // SIMD-ONLY0-NEXT:    [[CMP5559:%.*]] = icmp eq i64 [[TMP4188]], [[TMP4189]]
51325 // SIMD-ONLY0-NEXT:    br i1 [[CMP5559]], label [[IF_THEN5561:%.*]], label [[IF_END5562:%.*]]
51326 // SIMD-ONLY0:       if.then5561:
51327 // SIMD-ONLY0-NEXT:    [[TMP4190:%.*]] = load i64, ptr [[ULLD]], align 8
51328 // SIMD-ONLY0-NEXT:    store i64 [[TMP4190]], ptr [[ULLX]], align 8
51329 // SIMD-ONLY0-NEXT:    br label [[IF_END5562]]
51330 // SIMD-ONLY0:       if.end5562:
51331 // SIMD-ONLY0-NEXT:    [[TMP4191:%.*]] = load i64, ptr [[ULLX]], align 8
51332 // SIMD-ONLY0-NEXT:    store i64 [[TMP4191]], ptr [[ULLV]], align 8
51333 // SIMD-ONLY0-NEXT:    [[TMP4192:%.*]] = load i64, ptr [[ULLX]], align 8
51334 // SIMD-ONLY0-NEXT:    [[TMP4193:%.*]] = load i64, ptr [[ULLE]], align 8
51335 // SIMD-ONLY0-NEXT:    [[CMP5563:%.*]] = icmp eq i64 [[TMP4192]], [[TMP4193]]
51336 // SIMD-ONLY0-NEXT:    br i1 [[CMP5563]], label [[IF_THEN5565:%.*]], label [[IF_ELSE5566:%.*]]
51337 // SIMD-ONLY0:       if.then5565:
51338 // SIMD-ONLY0-NEXT:    [[TMP4194:%.*]] = load i64, ptr [[ULLD]], align 8
51339 // SIMD-ONLY0-NEXT:    store i64 [[TMP4194]], ptr [[ULLX]], align 8
51340 // SIMD-ONLY0-NEXT:    br label [[IF_END5567:%.*]]
51341 // SIMD-ONLY0:       if.else5566:
51342 // SIMD-ONLY0-NEXT:    [[TMP4195:%.*]] = load i64, ptr [[ULLX]], align 8
51343 // SIMD-ONLY0-NEXT:    store i64 [[TMP4195]], ptr [[ULLV]], align 8
51344 // SIMD-ONLY0-NEXT:    br label [[IF_END5567]]
51345 // SIMD-ONLY0:       if.end5567:
51346 // SIMD-ONLY0-NEXT:    [[TMP4196:%.*]] = load i64, ptr [[ULLE]], align 8
51347 // SIMD-ONLY0-NEXT:    [[TMP4197:%.*]] = load i64, ptr [[ULLX]], align 8
51348 // SIMD-ONLY0-NEXT:    [[CMP5568:%.*]] = icmp eq i64 [[TMP4196]], [[TMP4197]]
51349 // SIMD-ONLY0-NEXT:    br i1 [[CMP5568]], label [[IF_THEN5570:%.*]], label [[IF_ELSE5571:%.*]]
51350 // SIMD-ONLY0:       if.then5570:
51351 // SIMD-ONLY0-NEXT:    [[TMP4198:%.*]] = load i64, ptr [[ULLD]], align 8
51352 // SIMD-ONLY0-NEXT:    store i64 [[TMP4198]], ptr [[ULLX]], align 8
51353 // SIMD-ONLY0-NEXT:    br label [[IF_END5572:%.*]]
51354 // SIMD-ONLY0:       if.else5571:
51355 // SIMD-ONLY0-NEXT:    [[TMP4199:%.*]] = load i64, ptr [[ULLX]], align 8
51356 // SIMD-ONLY0-NEXT:    store i64 [[TMP4199]], ptr [[ULLV]], align 8
51357 // SIMD-ONLY0-NEXT:    br label [[IF_END5572]]
51358 // SIMD-ONLY0:       if.end5572:
51359 // SIMD-ONLY0-NEXT:    [[TMP4200:%.*]] = load i64, ptr [[ULLX]], align 8
51360 // SIMD-ONLY0-NEXT:    [[TMP4201:%.*]] = load i64, ptr [[ULLE]], align 8
51361 // SIMD-ONLY0-NEXT:    [[CMP5573:%.*]] = icmp eq i64 [[TMP4200]], [[TMP4201]]
51362 // SIMD-ONLY0-NEXT:    [[CONV5574:%.*]] = zext i1 [[CMP5573]] to i32
51363 // SIMD-ONLY0-NEXT:    [[CONV5575:%.*]] = sext i32 [[CONV5574]] to i64
51364 // SIMD-ONLY0-NEXT:    store i64 [[CONV5575]], ptr [[ULLR]], align 8
51365 // SIMD-ONLY0-NEXT:    [[TMP4202:%.*]] = load i64, ptr [[ULLR]], align 8
51366 // SIMD-ONLY0-NEXT:    [[TOBOOL5576:%.*]] = icmp ne i64 [[TMP4202]], 0
51367 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5576]], label [[IF_THEN5577:%.*]], label [[IF_END5578:%.*]]
51368 // SIMD-ONLY0:       if.then5577:
51369 // SIMD-ONLY0-NEXT:    [[TMP4203:%.*]] = load i64, ptr [[ULLD]], align 8
51370 // SIMD-ONLY0-NEXT:    store i64 [[TMP4203]], ptr [[ULLX]], align 8
51371 // SIMD-ONLY0-NEXT:    br label [[IF_END5578]]
51372 // SIMD-ONLY0:       if.end5578:
51373 // SIMD-ONLY0-NEXT:    [[TMP4204:%.*]] = load i64, ptr [[ULLE]], align 8
51374 // SIMD-ONLY0-NEXT:    [[TMP4205:%.*]] = load i64, ptr [[ULLX]], align 8
51375 // SIMD-ONLY0-NEXT:    [[CMP5579:%.*]] = icmp eq i64 [[TMP4204]], [[TMP4205]]
51376 // SIMD-ONLY0-NEXT:    [[CONV5580:%.*]] = zext i1 [[CMP5579]] to i32
51377 // SIMD-ONLY0-NEXT:    [[CONV5581:%.*]] = sext i32 [[CONV5580]] to i64
51378 // SIMD-ONLY0-NEXT:    store i64 [[CONV5581]], ptr [[ULLR]], align 8
51379 // SIMD-ONLY0-NEXT:    [[TMP4206:%.*]] = load i64, ptr [[ULLR]], align 8
51380 // SIMD-ONLY0-NEXT:    [[TOBOOL5582:%.*]] = icmp ne i64 [[TMP4206]], 0
51381 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5582]], label [[IF_THEN5583:%.*]], label [[IF_END5584:%.*]]
51382 // SIMD-ONLY0:       if.then5583:
51383 // SIMD-ONLY0-NEXT:    [[TMP4207:%.*]] = load i64, ptr [[ULLD]], align 8
51384 // SIMD-ONLY0-NEXT:    store i64 [[TMP4207]], ptr [[ULLX]], align 8
51385 // SIMD-ONLY0-NEXT:    br label [[IF_END5584]]
51386 // SIMD-ONLY0:       if.end5584:
51387 // SIMD-ONLY0-NEXT:    [[TMP4208:%.*]] = load i64, ptr [[ULLX]], align 8
51388 // SIMD-ONLY0-NEXT:    [[TMP4209:%.*]] = load i64, ptr [[ULLE]], align 8
51389 // SIMD-ONLY0-NEXT:    [[CMP5585:%.*]] = icmp eq i64 [[TMP4208]], [[TMP4209]]
51390 // SIMD-ONLY0-NEXT:    [[CONV5586:%.*]] = zext i1 [[CMP5585]] to i32
51391 // SIMD-ONLY0-NEXT:    [[CONV5587:%.*]] = sext i32 [[CONV5586]] to i64
51392 // SIMD-ONLY0-NEXT:    store i64 [[CONV5587]], ptr [[ULLR]], align 8
51393 // SIMD-ONLY0-NEXT:    [[TMP4210:%.*]] = load i64, ptr [[ULLR]], align 8
51394 // SIMD-ONLY0-NEXT:    [[TOBOOL5588:%.*]] = icmp ne i64 [[TMP4210]], 0
51395 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5588]], label [[IF_THEN5589:%.*]], label [[IF_ELSE5590:%.*]]
51396 // SIMD-ONLY0:       if.then5589:
51397 // SIMD-ONLY0-NEXT:    [[TMP4211:%.*]] = load i64, ptr [[ULLD]], align 8
51398 // SIMD-ONLY0-NEXT:    store i64 [[TMP4211]], ptr [[ULLX]], align 8
51399 // SIMD-ONLY0-NEXT:    br label [[IF_END5591:%.*]]
51400 // SIMD-ONLY0:       if.else5590:
51401 // SIMD-ONLY0-NEXT:    [[TMP4212:%.*]] = load i64, ptr [[ULLX]], align 8
51402 // SIMD-ONLY0-NEXT:    store i64 [[TMP4212]], ptr [[ULLV]], align 8
51403 // SIMD-ONLY0-NEXT:    br label [[IF_END5591]]
51404 // SIMD-ONLY0:       if.end5591:
51405 // SIMD-ONLY0-NEXT:    [[TMP4213:%.*]] = load i64, ptr [[ULLE]], align 8
51406 // SIMD-ONLY0-NEXT:    [[TMP4214:%.*]] = load i64, ptr [[ULLX]], align 8
51407 // SIMD-ONLY0-NEXT:    [[CMP5592:%.*]] = icmp eq i64 [[TMP4213]], [[TMP4214]]
51408 // SIMD-ONLY0-NEXT:    [[CONV5593:%.*]] = zext i1 [[CMP5592]] to i32
51409 // SIMD-ONLY0-NEXT:    [[CONV5594:%.*]] = sext i32 [[CONV5593]] to i64
51410 // SIMD-ONLY0-NEXT:    store i64 [[CONV5594]], ptr [[ULLR]], align 8
51411 // SIMD-ONLY0-NEXT:    [[TMP4215:%.*]] = load i64, ptr [[ULLR]], align 8
51412 // SIMD-ONLY0-NEXT:    [[TOBOOL5595:%.*]] = icmp ne i64 [[TMP4215]], 0
51413 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5595]], label [[IF_THEN5596:%.*]], label [[IF_ELSE5597:%.*]]
51414 // SIMD-ONLY0:       if.then5596:
51415 // SIMD-ONLY0-NEXT:    [[TMP4216:%.*]] = load i64, ptr [[ULLD]], align 8
51416 // SIMD-ONLY0-NEXT:    store i64 [[TMP4216]], ptr [[ULLX]], align 8
51417 // SIMD-ONLY0-NEXT:    br label [[IF_END5598:%.*]]
51418 // SIMD-ONLY0:       if.else5597:
51419 // SIMD-ONLY0-NEXT:    [[TMP4217:%.*]] = load i64, ptr [[ULLX]], align 8
51420 // SIMD-ONLY0-NEXT:    store i64 [[TMP4217]], ptr [[ULLV]], align 8
51421 // SIMD-ONLY0-NEXT:    br label [[IF_END5598]]
51422 // SIMD-ONLY0:       if.end5598:
51423 // SIMD-ONLY0-NEXT:    [[TMP4218:%.*]] = load i64, ptr [[ULLX]], align 8
51424 // SIMD-ONLY0-NEXT:    store i64 [[TMP4218]], ptr [[ULLV]], align 8
51425 // SIMD-ONLY0-NEXT:    [[TMP4219:%.*]] = load i64, ptr [[ULLE]], align 8
51426 // SIMD-ONLY0-NEXT:    [[TMP4220:%.*]] = load i64, ptr [[ULLX]], align 8
51427 // SIMD-ONLY0-NEXT:    [[CMP5599:%.*]] = icmp ugt i64 [[TMP4219]], [[TMP4220]]
51428 // SIMD-ONLY0-NEXT:    br i1 [[CMP5599]], label [[IF_THEN5601:%.*]], label [[IF_END5602:%.*]]
51429 // SIMD-ONLY0:       if.then5601:
51430 // SIMD-ONLY0-NEXT:    [[TMP4221:%.*]] = load i64, ptr [[ULLE]], align 8
51431 // SIMD-ONLY0-NEXT:    store i64 [[TMP4221]], ptr [[ULLX]], align 8
51432 // SIMD-ONLY0-NEXT:    br label [[IF_END5602]]
51433 // SIMD-ONLY0:       if.end5602:
51434 // SIMD-ONLY0-NEXT:    [[TMP4222:%.*]] = load i64, ptr [[ULLX]], align 8
51435 // SIMD-ONLY0-NEXT:    store i64 [[TMP4222]], ptr [[ULLV]], align 8
51436 // SIMD-ONLY0-NEXT:    [[TMP4223:%.*]] = load i64, ptr [[ULLX]], align 8
51437 // SIMD-ONLY0-NEXT:    [[TMP4224:%.*]] = load i64, ptr [[ULLE]], align 8
51438 // SIMD-ONLY0-NEXT:    [[CMP5603:%.*]] = icmp ugt i64 [[TMP4223]], [[TMP4224]]
51439 // SIMD-ONLY0-NEXT:    br i1 [[CMP5603]], label [[IF_THEN5605:%.*]], label [[IF_END5606:%.*]]
51440 // SIMD-ONLY0:       if.then5605:
51441 // SIMD-ONLY0-NEXT:    [[TMP4225:%.*]] = load i64, ptr [[ULLE]], align 8
51442 // SIMD-ONLY0-NEXT:    store i64 [[TMP4225]], ptr [[ULLX]], align 8
51443 // SIMD-ONLY0-NEXT:    br label [[IF_END5606]]
51444 // SIMD-ONLY0:       if.end5606:
51445 // SIMD-ONLY0-NEXT:    [[TMP4226:%.*]] = load i64, ptr [[ULLX]], align 8
51446 // SIMD-ONLY0-NEXT:    store i64 [[TMP4226]], ptr [[ULLV]], align 8
51447 // SIMD-ONLY0-NEXT:    [[TMP4227:%.*]] = load i64, ptr [[ULLE]], align 8
51448 // SIMD-ONLY0-NEXT:    [[TMP4228:%.*]] = load i64, ptr [[ULLX]], align 8
51449 // SIMD-ONLY0-NEXT:    [[CMP5607:%.*]] = icmp ult i64 [[TMP4227]], [[TMP4228]]
51450 // SIMD-ONLY0-NEXT:    br i1 [[CMP5607]], label [[IF_THEN5609:%.*]], label [[IF_END5610:%.*]]
51451 // SIMD-ONLY0:       if.then5609:
51452 // SIMD-ONLY0-NEXT:    [[TMP4229:%.*]] = load i64, ptr [[ULLE]], align 8
51453 // SIMD-ONLY0-NEXT:    store i64 [[TMP4229]], ptr [[ULLX]], align 8
51454 // SIMD-ONLY0-NEXT:    br label [[IF_END5610]]
51455 // SIMD-ONLY0:       if.end5610:
51456 // SIMD-ONLY0-NEXT:    [[TMP4230:%.*]] = load i64, ptr [[ULLX]], align 8
51457 // SIMD-ONLY0-NEXT:    store i64 [[TMP4230]], ptr [[ULLV]], align 8
51458 // SIMD-ONLY0-NEXT:    [[TMP4231:%.*]] = load i64, ptr [[ULLX]], align 8
51459 // SIMD-ONLY0-NEXT:    [[TMP4232:%.*]] = load i64, ptr [[ULLE]], align 8
51460 // SIMD-ONLY0-NEXT:    [[CMP5611:%.*]] = icmp ult i64 [[TMP4231]], [[TMP4232]]
51461 // SIMD-ONLY0-NEXT:    br i1 [[CMP5611]], label [[IF_THEN5613:%.*]], label [[IF_END5614:%.*]]
51462 // SIMD-ONLY0:       if.then5613:
51463 // SIMD-ONLY0-NEXT:    [[TMP4233:%.*]] = load i64, ptr [[ULLE]], align 8
51464 // SIMD-ONLY0-NEXT:    store i64 [[TMP4233]], ptr [[ULLX]], align 8
51465 // SIMD-ONLY0-NEXT:    br label [[IF_END5614]]
51466 // SIMD-ONLY0:       if.end5614:
51467 // SIMD-ONLY0-NEXT:    [[TMP4234:%.*]] = load i64, ptr [[ULLX]], align 8
51468 // SIMD-ONLY0-NEXT:    store i64 [[TMP4234]], ptr [[ULLV]], align 8
51469 // SIMD-ONLY0-NEXT:    [[TMP4235:%.*]] = load i64, ptr [[ULLX]], align 8
51470 // SIMD-ONLY0-NEXT:    [[TMP4236:%.*]] = load i64, ptr [[ULLE]], align 8
51471 // SIMD-ONLY0-NEXT:    [[CMP5615:%.*]] = icmp eq i64 [[TMP4235]], [[TMP4236]]
51472 // SIMD-ONLY0-NEXT:    br i1 [[CMP5615]], label [[IF_THEN5617:%.*]], label [[IF_END5618:%.*]]
51473 // SIMD-ONLY0:       if.then5617:
51474 // SIMD-ONLY0-NEXT:    [[TMP4237:%.*]] = load i64, ptr [[ULLD]], align 8
51475 // SIMD-ONLY0-NEXT:    store i64 [[TMP4237]], ptr [[ULLX]], align 8
51476 // SIMD-ONLY0-NEXT:    br label [[IF_END5618]]
51477 // SIMD-ONLY0:       if.end5618:
51478 // SIMD-ONLY0-NEXT:    [[TMP4238:%.*]] = load i64, ptr [[ULLX]], align 8
51479 // SIMD-ONLY0-NEXT:    store i64 [[TMP4238]], ptr [[ULLV]], align 8
51480 // SIMD-ONLY0-NEXT:    [[TMP4239:%.*]] = load i64, ptr [[ULLE]], align 8
51481 // SIMD-ONLY0-NEXT:    [[TMP4240:%.*]] = load i64, ptr [[ULLX]], align 8
51482 // SIMD-ONLY0-NEXT:    [[CMP5619:%.*]] = icmp eq i64 [[TMP4239]], [[TMP4240]]
51483 // SIMD-ONLY0-NEXT:    br i1 [[CMP5619]], label [[IF_THEN5621:%.*]], label [[IF_END5622:%.*]]
51484 // SIMD-ONLY0:       if.then5621:
51485 // SIMD-ONLY0-NEXT:    [[TMP4241:%.*]] = load i64, ptr [[ULLD]], align 8
51486 // SIMD-ONLY0-NEXT:    store i64 [[TMP4241]], ptr [[ULLX]], align 8
51487 // SIMD-ONLY0-NEXT:    br label [[IF_END5622]]
51488 // SIMD-ONLY0:       if.end5622:
51489 // SIMD-ONLY0-NEXT:    [[TMP4242:%.*]] = load i64, ptr [[ULLE]], align 8
51490 // SIMD-ONLY0-NEXT:    [[TMP4243:%.*]] = load i64, ptr [[ULLX]], align 8
51491 // SIMD-ONLY0-NEXT:    [[CMP5623:%.*]] = icmp ugt i64 [[TMP4242]], [[TMP4243]]
51492 // SIMD-ONLY0-NEXT:    br i1 [[CMP5623]], label [[IF_THEN5625:%.*]], label [[IF_END5626:%.*]]
51493 // SIMD-ONLY0:       if.then5625:
51494 // SIMD-ONLY0-NEXT:    [[TMP4244:%.*]] = load i64, ptr [[ULLE]], align 8
51495 // SIMD-ONLY0-NEXT:    store i64 [[TMP4244]], ptr [[ULLX]], align 8
51496 // SIMD-ONLY0-NEXT:    br label [[IF_END5626]]
51497 // SIMD-ONLY0:       if.end5626:
51498 // SIMD-ONLY0-NEXT:    [[TMP4245:%.*]] = load i64, ptr [[ULLX]], align 8
51499 // SIMD-ONLY0-NEXT:    store i64 [[TMP4245]], ptr [[ULLV]], align 8
51500 // SIMD-ONLY0-NEXT:    [[TMP4246:%.*]] = load i64, ptr [[ULLX]], align 8
51501 // SIMD-ONLY0-NEXT:    [[TMP4247:%.*]] = load i64, ptr [[ULLE]], align 8
51502 // SIMD-ONLY0-NEXT:    [[CMP5627:%.*]] = icmp ugt i64 [[TMP4246]], [[TMP4247]]
51503 // SIMD-ONLY0-NEXT:    br i1 [[CMP5627]], label [[IF_THEN5629:%.*]], label [[IF_END5630:%.*]]
51504 // SIMD-ONLY0:       if.then5629:
51505 // SIMD-ONLY0-NEXT:    [[TMP4248:%.*]] = load i64, ptr [[ULLE]], align 8
51506 // SIMD-ONLY0-NEXT:    store i64 [[TMP4248]], ptr [[ULLX]], align 8
51507 // SIMD-ONLY0-NEXT:    br label [[IF_END5630]]
51508 // SIMD-ONLY0:       if.end5630:
51509 // SIMD-ONLY0-NEXT:    [[TMP4249:%.*]] = load i64, ptr [[ULLX]], align 8
51510 // SIMD-ONLY0-NEXT:    store i64 [[TMP4249]], ptr [[ULLV]], align 8
51511 // SIMD-ONLY0-NEXT:    [[TMP4250:%.*]] = load i64, ptr [[ULLE]], align 8
51512 // SIMD-ONLY0-NEXT:    [[TMP4251:%.*]] = load i64, ptr [[ULLX]], align 8
51513 // SIMD-ONLY0-NEXT:    [[CMP5631:%.*]] = icmp ult i64 [[TMP4250]], [[TMP4251]]
51514 // SIMD-ONLY0-NEXT:    br i1 [[CMP5631]], label [[IF_THEN5633:%.*]], label [[IF_END5634:%.*]]
51515 // SIMD-ONLY0:       if.then5633:
51516 // SIMD-ONLY0-NEXT:    [[TMP4252:%.*]] = load i64, ptr [[ULLE]], align 8
51517 // SIMD-ONLY0-NEXT:    store i64 [[TMP4252]], ptr [[ULLX]], align 8
51518 // SIMD-ONLY0-NEXT:    br label [[IF_END5634]]
51519 // SIMD-ONLY0:       if.end5634:
51520 // SIMD-ONLY0-NEXT:    [[TMP4253:%.*]] = load i64, ptr [[ULLX]], align 8
51521 // SIMD-ONLY0-NEXT:    store i64 [[TMP4253]], ptr [[ULLV]], align 8
51522 // SIMD-ONLY0-NEXT:    [[TMP4254:%.*]] = load i64, ptr [[ULLX]], align 8
51523 // SIMD-ONLY0-NEXT:    [[TMP4255:%.*]] = load i64, ptr [[ULLE]], align 8
51524 // SIMD-ONLY0-NEXT:    [[CMP5635:%.*]] = icmp ult i64 [[TMP4254]], [[TMP4255]]
51525 // SIMD-ONLY0-NEXT:    br i1 [[CMP5635]], label [[IF_THEN5637:%.*]], label [[IF_END5638:%.*]]
51526 // SIMD-ONLY0:       if.then5637:
51527 // SIMD-ONLY0-NEXT:    [[TMP4256:%.*]] = load i64, ptr [[ULLE]], align 8
51528 // SIMD-ONLY0-NEXT:    store i64 [[TMP4256]], ptr [[ULLX]], align 8
51529 // SIMD-ONLY0-NEXT:    br label [[IF_END5638]]
51530 // SIMD-ONLY0:       if.end5638:
51531 // SIMD-ONLY0-NEXT:    [[TMP4257:%.*]] = load i64, ptr [[ULLX]], align 8
51532 // SIMD-ONLY0-NEXT:    store i64 [[TMP4257]], ptr [[ULLV]], align 8
51533 // SIMD-ONLY0-NEXT:    [[TMP4258:%.*]] = load i64, ptr [[ULLX]], align 8
51534 // SIMD-ONLY0-NEXT:    [[TMP4259:%.*]] = load i64, ptr [[ULLE]], align 8
51535 // SIMD-ONLY0-NEXT:    [[CMP5639:%.*]] = icmp eq i64 [[TMP4258]], [[TMP4259]]
51536 // SIMD-ONLY0-NEXT:    br i1 [[CMP5639]], label [[IF_THEN5641:%.*]], label [[IF_END5642:%.*]]
51537 // SIMD-ONLY0:       if.then5641:
51538 // SIMD-ONLY0-NEXT:    [[TMP4260:%.*]] = load i64, ptr [[ULLD]], align 8
51539 // SIMD-ONLY0-NEXT:    store i64 [[TMP4260]], ptr [[ULLX]], align 8
51540 // SIMD-ONLY0-NEXT:    br label [[IF_END5642]]
51541 // SIMD-ONLY0:       if.end5642:
51542 // SIMD-ONLY0-NEXT:    [[TMP4261:%.*]] = load i64, ptr [[ULLX]], align 8
51543 // SIMD-ONLY0-NEXT:    store i64 [[TMP4261]], ptr [[ULLV]], align 8
51544 // SIMD-ONLY0-NEXT:    [[TMP4262:%.*]] = load i64, ptr [[ULLE]], align 8
51545 // SIMD-ONLY0-NEXT:    [[TMP4263:%.*]] = load i64, ptr [[ULLX]], align 8
51546 // SIMD-ONLY0-NEXT:    [[CMP5643:%.*]] = icmp eq i64 [[TMP4262]], [[TMP4263]]
51547 // SIMD-ONLY0-NEXT:    br i1 [[CMP5643]], label [[IF_THEN5645:%.*]], label [[IF_END5646:%.*]]
51548 // SIMD-ONLY0:       if.then5645:
51549 // SIMD-ONLY0-NEXT:    [[TMP4264:%.*]] = load i64, ptr [[ULLD]], align 8
51550 // SIMD-ONLY0-NEXT:    store i64 [[TMP4264]], ptr [[ULLX]], align 8
51551 // SIMD-ONLY0-NEXT:    br label [[IF_END5646]]
51552 // SIMD-ONLY0:       if.end5646:
51553 // SIMD-ONLY0-NEXT:    [[TMP4265:%.*]] = load i64, ptr [[ULLX]], align 8
51554 // SIMD-ONLY0-NEXT:    store i64 [[TMP4265]], ptr [[ULLV]], align 8
51555 // SIMD-ONLY0-NEXT:    [[TMP4266:%.*]] = load i64, ptr [[ULLX]], align 8
51556 // SIMD-ONLY0-NEXT:    [[TMP4267:%.*]] = load i64, ptr [[ULLE]], align 8
51557 // SIMD-ONLY0-NEXT:    [[CMP5647:%.*]] = icmp eq i64 [[TMP4266]], [[TMP4267]]
51558 // SIMD-ONLY0-NEXT:    br i1 [[CMP5647]], label [[IF_THEN5649:%.*]], label [[IF_ELSE5650:%.*]]
51559 // SIMD-ONLY0:       if.then5649:
51560 // SIMD-ONLY0-NEXT:    [[TMP4268:%.*]] = load i64, ptr [[ULLD]], align 8
51561 // SIMD-ONLY0-NEXT:    store i64 [[TMP4268]], ptr [[ULLX]], align 8
51562 // SIMD-ONLY0-NEXT:    br label [[IF_END5651:%.*]]
51563 // SIMD-ONLY0:       if.else5650:
51564 // SIMD-ONLY0-NEXT:    [[TMP4269:%.*]] = load i64, ptr [[ULLX]], align 8
51565 // SIMD-ONLY0-NEXT:    store i64 [[TMP4269]], ptr [[ULLV]], align 8
51566 // SIMD-ONLY0-NEXT:    br label [[IF_END5651]]
51567 // SIMD-ONLY0:       if.end5651:
51568 // SIMD-ONLY0-NEXT:    [[TMP4270:%.*]] = load i64, ptr [[ULLE]], align 8
51569 // SIMD-ONLY0-NEXT:    [[TMP4271:%.*]] = load i64, ptr [[ULLX]], align 8
51570 // SIMD-ONLY0-NEXT:    [[CMP5652:%.*]] = icmp eq i64 [[TMP4270]], [[TMP4271]]
51571 // SIMD-ONLY0-NEXT:    br i1 [[CMP5652]], label [[IF_THEN5654:%.*]], label [[IF_ELSE5655:%.*]]
51572 // SIMD-ONLY0:       if.then5654:
51573 // SIMD-ONLY0-NEXT:    [[TMP4272:%.*]] = load i64, ptr [[ULLD]], align 8
51574 // SIMD-ONLY0-NEXT:    store i64 [[TMP4272]], ptr [[ULLX]], align 8
51575 // SIMD-ONLY0-NEXT:    br label [[IF_END5656:%.*]]
51576 // SIMD-ONLY0:       if.else5655:
51577 // SIMD-ONLY0-NEXT:    [[TMP4273:%.*]] = load i64, ptr [[ULLX]], align 8
51578 // SIMD-ONLY0-NEXT:    store i64 [[TMP4273]], ptr [[ULLV]], align 8
51579 // SIMD-ONLY0-NEXT:    br label [[IF_END5656]]
51580 // SIMD-ONLY0:       if.end5656:
51581 // SIMD-ONLY0-NEXT:    [[TMP4274:%.*]] = load i64, ptr [[ULLX]], align 8
51582 // SIMD-ONLY0-NEXT:    [[TMP4275:%.*]] = load i64, ptr [[ULLE]], align 8
51583 // SIMD-ONLY0-NEXT:    [[CMP5657:%.*]] = icmp eq i64 [[TMP4274]], [[TMP4275]]
51584 // SIMD-ONLY0-NEXT:    [[CONV5658:%.*]] = zext i1 [[CMP5657]] to i32
51585 // SIMD-ONLY0-NEXT:    [[CONV5659:%.*]] = sext i32 [[CONV5658]] to i64
51586 // SIMD-ONLY0-NEXT:    store i64 [[CONV5659]], ptr [[ULLR]], align 8
51587 // SIMD-ONLY0-NEXT:    [[TMP4276:%.*]] = load i64, ptr [[ULLR]], align 8
51588 // SIMD-ONLY0-NEXT:    [[TOBOOL5660:%.*]] = icmp ne i64 [[TMP4276]], 0
51589 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5660]], label [[IF_THEN5661:%.*]], label [[IF_END5662:%.*]]
51590 // SIMD-ONLY0:       if.then5661:
51591 // SIMD-ONLY0-NEXT:    [[TMP4277:%.*]] = load i64, ptr [[ULLD]], align 8
51592 // SIMD-ONLY0-NEXT:    store i64 [[TMP4277]], ptr [[ULLX]], align 8
51593 // SIMD-ONLY0-NEXT:    br label [[IF_END5662]]
51594 // SIMD-ONLY0:       if.end5662:
51595 // SIMD-ONLY0-NEXT:    [[TMP4278:%.*]] = load i64, ptr [[ULLE]], align 8
51596 // SIMD-ONLY0-NEXT:    [[TMP4279:%.*]] = load i64, ptr [[ULLX]], align 8
51597 // SIMD-ONLY0-NEXT:    [[CMP5663:%.*]] = icmp eq i64 [[TMP4278]], [[TMP4279]]
51598 // SIMD-ONLY0-NEXT:    [[CONV5664:%.*]] = zext i1 [[CMP5663]] to i32
51599 // SIMD-ONLY0-NEXT:    [[CONV5665:%.*]] = sext i32 [[CONV5664]] to i64
51600 // SIMD-ONLY0-NEXT:    store i64 [[CONV5665]], ptr [[ULLR]], align 8
51601 // SIMD-ONLY0-NEXT:    [[TMP4280:%.*]] = load i64, ptr [[ULLR]], align 8
51602 // SIMD-ONLY0-NEXT:    [[TOBOOL5666:%.*]] = icmp ne i64 [[TMP4280]], 0
51603 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5666]], label [[IF_THEN5667:%.*]], label [[IF_END5668:%.*]]
51604 // SIMD-ONLY0:       if.then5667:
51605 // SIMD-ONLY0-NEXT:    [[TMP4281:%.*]] = load i64, ptr [[ULLD]], align 8
51606 // SIMD-ONLY0-NEXT:    store i64 [[TMP4281]], ptr [[ULLX]], align 8
51607 // SIMD-ONLY0-NEXT:    br label [[IF_END5668]]
51608 // SIMD-ONLY0:       if.end5668:
51609 // SIMD-ONLY0-NEXT:    [[TMP4282:%.*]] = load i64, ptr [[ULLX]], align 8
51610 // SIMD-ONLY0-NEXT:    [[TMP4283:%.*]] = load i64, ptr [[ULLE]], align 8
51611 // SIMD-ONLY0-NEXT:    [[CMP5669:%.*]] = icmp eq i64 [[TMP4282]], [[TMP4283]]
51612 // SIMD-ONLY0-NEXT:    [[CONV5670:%.*]] = zext i1 [[CMP5669]] to i32
51613 // SIMD-ONLY0-NEXT:    [[CONV5671:%.*]] = sext i32 [[CONV5670]] to i64
51614 // SIMD-ONLY0-NEXT:    store i64 [[CONV5671]], ptr [[ULLR]], align 8
51615 // SIMD-ONLY0-NEXT:    [[TMP4284:%.*]] = load i64, ptr [[ULLR]], align 8
51616 // SIMD-ONLY0-NEXT:    [[TOBOOL5672:%.*]] = icmp ne i64 [[TMP4284]], 0
51617 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5672]], label [[IF_THEN5673:%.*]], label [[IF_ELSE5674:%.*]]
51618 // SIMD-ONLY0:       if.then5673:
51619 // SIMD-ONLY0-NEXT:    [[TMP4285:%.*]] = load i64, ptr [[ULLD]], align 8
51620 // SIMD-ONLY0-NEXT:    store i64 [[TMP4285]], ptr [[ULLX]], align 8
51621 // SIMD-ONLY0-NEXT:    br label [[IF_END5675:%.*]]
51622 // SIMD-ONLY0:       if.else5674:
51623 // SIMD-ONLY0-NEXT:    [[TMP4286:%.*]] = load i64, ptr [[ULLX]], align 8
51624 // SIMD-ONLY0-NEXT:    store i64 [[TMP4286]], ptr [[ULLV]], align 8
51625 // SIMD-ONLY0-NEXT:    br label [[IF_END5675]]
51626 // SIMD-ONLY0:       if.end5675:
51627 // SIMD-ONLY0-NEXT:    [[TMP4287:%.*]] = load i64, ptr [[ULLE]], align 8
51628 // SIMD-ONLY0-NEXT:    [[TMP4288:%.*]] = load i64, ptr [[ULLX]], align 8
51629 // SIMD-ONLY0-NEXT:    [[CMP5676:%.*]] = icmp eq i64 [[TMP4287]], [[TMP4288]]
51630 // SIMD-ONLY0-NEXT:    [[CONV5677:%.*]] = zext i1 [[CMP5676]] to i32
51631 // SIMD-ONLY0-NEXT:    [[CONV5678:%.*]] = sext i32 [[CONV5677]] to i64
51632 // SIMD-ONLY0-NEXT:    store i64 [[CONV5678]], ptr [[ULLR]], align 8
51633 // SIMD-ONLY0-NEXT:    [[TMP4289:%.*]] = load i64, ptr [[ULLR]], align 8
51634 // SIMD-ONLY0-NEXT:    [[TOBOOL5679:%.*]] = icmp ne i64 [[TMP4289]], 0
51635 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5679]], label [[IF_THEN5680:%.*]], label [[IF_ELSE5681:%.*]]
51636 // SIMD-ONLY0:       if.then5680:
51637 // SIMD-ONLY0-NEXT:    [[TMP4290:%.*]] = load i64, ptr [[ULLD]], align 8
51638 // SIMD-ONLY0-NEXT:    store i64 [[TMP4290]], ptr [[ULLX]], align 8
51639 // SIMD-ONLY0-NEXT:    br label [[IF_END5682:%.*]]
51640 // SIMD-ONLY0:       if.else5681:
51641 // SIMD-ONLY0-NEXT:    [[TMP4291:%.*]] = load i64, ptr [[ULLX]], align 8
51642 // SIMD-ONLY0-NEXT:    store i64 [[TMP4291]], ptr [[ULLV]], align 8
51643 // SIMD-ONLY0-NEXT:    br label [[IF_END5682]]
51644 // SIMD-ONLY0:       if.end5682:
51645 // SIMD-ONLY0-NEXT:    [[TMP4292:%.*]] = load i64, ptr [[ULLX]], align 8
51646 // SIMD-ONLY0-NEXT:    store i64 [[TMP4292]], ptr [[ULLV]], align 8
51647 // SIMD-ONLY0-NEXT:    [[TMP4293:%.*]] = load i64, ptr [[ULLE]], align 8
51648 // SIMD-ONLY0-NEXT:    [[TMP4294:%.*]] = load i64, ptr [[ULLX]], align 8
51649 // SIMD-ONLY0-NEXT:    [[CMP5683:%.*]] = icmp ugt i64 [[TMP4293]], [[TMP4294]]
51650 // SIMD-ONLY0-NEXT:    br i1 [[CMP5683]], label [[IF_THEN5685:%.*]], label [[IF_END5686:%.*]]
51651 // SIMD-ONLY0:       if.then5685:
51652 // SIMD-ONLY0-NEXT:    [[TMP4295:%.*]] = load i64, ptr [[ULLE]], align 8
51653 // SIMD-ONLY0-NEXT:    store i64 [[TMP4295]], ptr [[ULLX]], align 8
51654 // SIMD-ONLY0-NEXT:    br label [[IF_END5686]]
51655 // SIMD-ONLY0:       if.end5686:
51656 // SIMD-ONLY0-NEXT:    [[TMP4296:%.*]] = load i64, ptr [[ULLX]], align 8
51657 // SIMD-ONLY0-NEXT:    store i64 [[TMP4296]], ptr [[ULLV]], align 8
51658 // SIMD-ONLY0-NEXT:    [[TMP4297:%.*]] = load i64, ptr [[ULLX]], align 8
51659 // SIMD-ONLY0-NEXT:    [[TMP4298:%.*]] = load i64, ptr [[ULLE]], align 8
51660 // SIMD-ONLY0-NEXT:    [[CMP5687:%.*]] = icmp ugt i64 [[TMP4297]], [[TMP4298]]
51661 // SIMD-ONLY0-NEXT:    br i1 [[CMP5687]], label [[IF_THEN5689:%.*]], label [[IF_END5690:%.*]]
51662 // SIMD-ONLY0:       if.then5689:
51663 // SIMD-ONLY0-NEXT:    [[TMP4299:%.*]] = load i64, ptr [[ULLE]], align 8
51664 // SIMD-ONLY0-NEXT:    store i64 [[TMP4299]], ptr [[ULLX]], align 8
51665 // SIMD-ONLY0-NEXT:    br label [[IF_END5690]]
51666 // SIMD-ONLY0:       if.end5690:
51667 // SIMD-ONLY0-NEXT:    [[TMP4300:%.*]] = load i64, ptr [[ULLX]], align 8
51668 // SIMD-ONLY0-NEXT:    store i64 [[TMP4300]], ptr [[ULLV]], align 8
51669 // SIMD-ONLY0-NEXT:    [[TMP4301:%.*]] = load i64, ptr [[ULLE]], align 8
51670 // SIMD-ONLY0-NEXT:    [[TMP4302:%.*]] = load i64, ptr [[ULLX]], align 8
51671 // SIMD-ONLY0-NEXT:    [[CMP5691:%.*]] = icmp ult i64 [[TMP4301]], [[TMP4302]]
51672 // SIMD-ONLY0-NEXT:    br i1 [[CMP5691]], label [[IF_THEN5693:%.*]], label [[IF_END5694:%.*]]
51673 // SIMD-ONLY0:       if.then5693:
51674 // SIMD-ONLY0-NEXT:    [[TMP4303:%.*]] = load i64, ptr [[ULLE]], align 8
51675 // SIMD-ONLY0-NEXT:    store i64 [[TMP4303]], ptr [[ULLX]], align 8
51676 // SIMD-ONLY0-NEXT:    br label [[IF_END5694]]
51677 // SIMD-ONLY0:       if.end5694:
51678 // SIMD-ONLY0-NEXT:    [[TMP4304:%.*]] = load i64, ptr [[ULLX]], align 8
51679 // SIMD-ONLY0-NEXT:    store i64 [[TMP4304]], ptr [[ULLV]], align 8
51680 // SIMD-ONLY0-NEXT:    [[TMP4305:%.*]] = load i64, ptr [[ULLX]], align 8
51681 // SIMD-ONLY0-NEXT:    [[TMP4306:%.*]] = load i64, ptr [[ULLE]], align 8
51682 // SIMD-ONLY0-NEXT:    [[CMP5695:%.*]] = icmp ult i64 [[TMP4305]], [[TMP4306]]
51683 // SIMD-ONLY0-NEXT:    br i1 [[CMP5695]], label [[IF_THEN5697:%.*]], label [[IF_END5698:%.*]]
51684 // SIMD-ONLY0:       if.then5697:
51685 // SIMD-ONLY0-NEXT:    [[TMP4307:%.*]] = load i64, ptr [[ULLE]], align 8
51686 // SIMD-ONLY0-NEXT:    store i64 [[TMP4307]], ptr [[ULLX]], align 8
51687 // SIMD-ONLY0-NEXT:    br label [[IF_END5698]]
51688 // SIMD-ONLY0:       if.end5698:
51689 // SIMD-ONLY0-NEXT:    [[TMP4308:%.*]] = load i64, ptr [[ULLX]], align 8
51690 // SIMD-ONLY0-NEXT:    store i64 [[TMP4308]], ptr [[ULLV]], align 8
51691 // SIMD-ONLY0-NEXT:    [[TMP4309:%.*]] = load i64, ptr [[ULLX]], align 8
51692 // SIMD-ONLY0-NEXT:    [[TMP4310:%.*]] = load i64, ptr [[ULLE]], align 8
51693 // SIMD-ONLY0-NEXT:    [[CMP5699:%.*]] = icmp eq i64 [[TMP4309]], [[TMP4310]]
51694 // SIMD-ONLY0-NEXT:    br i1 [[CMP5699]], label [[IF_THEN5701:%.*]], label [[IF_END5702:%.*]]
51695 // SIMD-ONLY0:       if.then5701:
51696 // SIMD-ONLY0-NEXT:    [[TMP4311:%.*]] = load i64, ptr [[ULLD]], align 8
51697 // SIMD-ONLY0-NEXT:    store i64 [[TMP4311]], ptr [[ULLX]], align 8
51698 // SIMD-ONLY0-NEXT:    br label [[IF_END5702]]
51699 // SIMD-ONLY0:       if.end5702:
51700 // SIMD-ONLY0-NEXT:    [[TMP4312:%.*]] = load i64, ptr [[ULLX]], align 8
51701 // SIMD-ONLY0-NEXT:    store i64 [[TMP4312]], ptr [[ULLV]], align 8
51702 // SIMD-ONLY0-NEXT:    [[TMP4313:%.*]] = load i64, ptr [[ULLE]], align 8
51703 // SIMD-ONLY0-NEXT:    [[TMP4314:%.*]] = load i64, ptr [[ULLX]], align 8
51704 // SIMD-ONLY0-NEXT:    [[CMP5703:%.*]] = icmp eq i64 [[TMP4313]], [[TMP4314]]
51705 // SIMD-ONLY0-NEXT:    br i1 [[CMP5703]], label [[IF_THEN5705:%.*]], label [[IF_END5706:%.*]]
51706 // SIMD-ONLY0:       if.then5705:
51707 // SIMD-ONLY0-NEXT:    [[TMP4315:%.*]] = load i64, ptr [[ULLD]], align 8
51708 // SIMD-ONLY0-NEXT:    store i64 [[TMP4315]], ptr [[ULLX]], align 8
51709 // SIMD-ONLY0-NEXT:    br label [[IF_END5706]]
51710 // SIMD-ONLY0:       if.end5706:
51711 // SIMD-ONLY0-NEXT:    [[TMP4316:%.*]] = load i64, ptr [[ULLE]], align 8
51712 // SIMD-ONLY0-NEXT:    [[TMP4317:%.*]] = load i64, ptr [[ULLX]], align 8
51713 // SIMD-ONLY0-NEXT:    [[CMP5707:%.*]] = icmp ugt i64 [[TMP4316]], [[TMP4317]]
51714 // SIMD-ONLY0-NEXT:    br i1 [[CMP5707]], label [[IF_THEN5709:%.*]], label [[IF_END5710:%.*]]
51715 // SIMD-ONLY0:       if.then5709:
51716 // SIMD-ONLY0-NEXT:    [[TMP4318:%.*]] = load i64, ptr [[ULLE]], align 8
51717 // SIMD-ONLY0-NEXT:    store i64 [[TMP4318]], ptr [[ULLX]], align 8
51718 // SIMD-ONLY0-NEXT:    br label [[IF_END5710]]
51719 // SIMD-ONLY0:       if.end5710:
51720 // SIMD-ONLY0-NEXT:    [[TMP4319:%.*]] = load i64, ptr [[ULLX]], align 8
51721 // SIMD-ONLY0-NEXT:    store i64 [[TMP4319]], ptr [[ULLV]], align 8
51722 // SIMD-ONLY0-NEXT:    [[TMP4320:%.*]] = load i64, ptr [[ULLX]], align 8
51723 // SIMD-ONLY0-NEXT:    [[TMP4321:%.*]] = load i64, ptr [[ULLE]], align 8
51724 // SIMD-ONLY0-NEXT:    [[CMP5711:%.*]] = icmp ugt i64 [[TMP4320]], [[TMP4321]]
51725 // SIMD-ONLY0-NEXT:    br i1 [[CMP5711]], label [[IF_THEN5713:%.*]], label [[IF_END5714:%.*]]
51726 // SIMD-ONLY0:       if.then5713:
51727 // SIMD-ONLY0-NEXT:    [[TMP4322:%.*]] = load i64, ptr [[ULLE]], align 8
51728 // SIMD-ONLY0-NEXT:    store i64 [[TMP4322]], ptr [[ULLX]], align 8
51729 // SIMD-ONLY0-NEXT:    br label [[IF_END5714]]
51730 // SIMD-ONLY0:       if.end5714:
51731 // SIMD-ONLY0-NEXT:    [[TMP4323:%.*]] = load i64, ptr [[ULLX]], align 8
51732 // SIMD-ONLY0-NEXT:    store i64 [[TMP4323]], ptr [[ULLV]], align 8
51733 // SIMD-ONLY0-NEXT:    [[TMP4324:%.*]] = load i64, ptr [[ULLE]], align 8
51734 // SIMD-ONLY0-NEXT:    [[TMP4325:%.*]] = load i64, ptr [[ULLX]], align 8
51735 // SIMD-ONLY0-NEXT:    [[CMP5715:%.*]] = icmp ult i64 [[TMP4324]], [[TMP4325]]
51736 // SIMD-ONLY0-NEXT:    br i1 [[CMP5715]], label [[IF_THEN5717:%.*]], label [[IF_END5718:%.*]]
51737 // SIMD-ONLY0:       if.then5717:
51738 // SIMD-ONLY0-NEXT:    [[TMP4326:%.*]] = load i64, ptr [[ULLE]], align 8
51739 // SIMD-ONLY0-NEXT:    store i64 [[TMP4326]], ptr [[ULLX]], align 8
51740 // SIMD-ONLY0-NEXT:    br label [[IF_END5718]]
51741 // SIMD-ONLY0:       if.end5718:
51742 // SIMD-ONLY0-NEXT:    [[TMP4327:%.*]] = load i64, ptr [[ULLX]], align 8
51743 // SIMD-ONLY0-NEXT:    store i64 [[TMP4327]], ptr [[ULLV]], align 8
51744 // SIMD-ONLY0-NEXT:    [[TMP4328:%.*]] = load i64, ptr [[ULLX]], align 8
51745 // SIMD-ONLY0-NEXT:    [[TMP4329:%.*]] = load i64, ptr [[ULLE]], align 8
51746 // SIMD-ONLY0-NEXT:    [[CMP5719:%.*]] = icmp ult i64 [[TMP4328]], [[TMP4329]]
51747 // SIMD-ONLY0-NEXT:    br i1 [[CMP5719]], label [[IF_THEN5721:%.*]], label [[IF_END5722:%.*]]
51748 // SIMD-ONLY0:       if.then5721:
51749 // SIMD-ONLY0-NEXT:    [[TMP4330:%.*]] = load i64, ptr [[ULLE]], align 8
51750 // SIMD-ONLY0-NEXT:    store i64 [[TMP4330]], ptr [[ULLX]], align 8
51751 // SIMD-ONLY0-NEXT:    br label [[IF_END5722]]
51752 // SIMD-ONLY0:       if.end5722:
51753 // SIMD-ONLY0-NEXT:    [[TMP4331:%.*]] = load i64, ptr [[ULLX]], align 8
51754 // SIMD-ONLY0-NEXT:    store i64 [[TMP4331]], ptr [[ULLV]], align 8
51755 // SIMD-ONLY0-NEXT:    [[TMP4332:%.*]] = load i64, ptr [[ULLX]], align 8
51756 // SIMD-ONLY0-NEXT:    [[TMP4333:%.*]] = load i64, ptr [[ULLE]], align 8
51757 // SIMD-ONLY0-NEXT:    [[CMP5723:%.*]] = icmp eq i64 [[TMP4332]], [[TMP4333]]
51758 // SIMD-ONLY0-NEXT:    br i1 [[CMP5723]], label [[IF_THEN5725:%.*]], label [[IF_END5726:%.*]]
51759 // SIMD-ONLY0:       if.then5725:
51760 // SIMD-ONLY0-NEXT:    [[TMP4334:%.*]] = load i64, ptr [[ULLD]], align 8
51761 // SIMD-ONLY0-NEXT:    store i64 [[TMP4334]], ptr [[ULLX]], align 8
51762 // SIMD-ONLY0-NEXT:    br label [[IF_END5726]]
51763 // SIMD-ONLY0:       if.end5726:
51764 // SIMD-ONLY0-NEXT:    [[TMP4335:%.*]] = load i64, ptr [[ULLX]], align 8
51765 // SIMD-ONLY0-NEXT:    store i64 [[TMP4335]], ptr [[ULLV]], align 8
51766 // SIMD-ONLY0-NEXT:    [[TMP4336:%.*]] = load i64, ptr [[ULLE]], align 8
51767 // SIMD-ONLY0-NEXT:    [[TMP4337:%.*]] = load i64, ptr [[ULLX]], align 8
51768 // SIMD-ONLY0-NEXT:    [[CMP5727:%.*]] = icmp eq i64 [[TMP4336]], [[TMP4337]]
51769 // SIMD-ONLY0-NEXT:    br i1 [[CMP5727]], label [[IF_THEN5729:%.*]], label [[IF_END5730:%.*]]
51770 // SIMD-ONLY0:       if.then5729:
51771 // SIMD-ONLY0-NEXT:    [[TMP4338:%.*]] = load i64, ptr [[ULLD]], align 8
51772 // SIMD-ONLY0-NEXT:    store i64 [[TMP4338]], ptr [[ULLX]], align 8
51773 // SIMD-ONLY0-NEXT:    br label [[IF_END5730]]
51774 // SIMD-ONLY0:       if.end5730:
51775 // SIMD-ONLY0-NEXT:    [[TMP4339:%.*]] = load i64, ptr [[ULLX]], align 8
51776 // SIMD-ONLY0-NEXT:    store i64 [[TMP4339]], ptr [[ULLV]], align 8
51777 // SIMD-ONLY0-NEXT:    [[TMP4340:%.*]] = load i64, ptr [[ULLX]], align 8
51778 // SIMD-ONLY0-NEXT:    [[TMP4341:%.*]] = load i64, ptr [[ULLE]], align 8
51779 // SIMD-ONLY0-NEXT:    [[CMP5731:%.*]] = icmp eq i64 [[TMP4340]], [[TMP4341]]
51780 // SIMD-ONLY0-NEXT:    br i1 [[CMP5731]], label [[IF_THEN5733:%.*]], label [[IF_ELSE5734:%.*]]
51781 // SIMD-ONLY0:       if.then5733:
51782 // SIMD-ONLY0-NEXT:    [[TMP4342:%.*]] = load i64, ptr [[ULLD]], align 8
51783 // SIMD-ONLY0-NEXT:    store i64 [[TMP4342]], ptr [[ULLX]], align 8
51784 // SIMD-ONLY0-NEXT:    br label [[IF_END5735:%.*]]
51785 // SIMD-ONLY0:       if.else5734:
51786 // SIMD-ONLY0-NEXT:    [[TMP4343:%.*]] = load i64, ptr [[ULLX]], align 8
51787 // SIMD-ONLY0-NEXT:    store i64 [[TMP4343]], ptr [[ULLV]], align 8
51788 // SIMD-ONLY0-NEXT:    br label [[IF_END5735]]
51789 // SIMD-ONLY0:       if.end5735:
51790 // SIMD-ONLY0-NEXT:    [[TMP4344:%.*]] = load i64, ptr [[ULLE]], align 8
51791 // SIMD-ONLY0-NEXT:    [[TMP4345:%.*]] = load i64, ptr [[ULLX]], align 8
51792 // SIMD-ONLY0-NEXT:    [[CMP5736:%.*]] = icmp eq i64 [[TMP4344]], [[TMP4345]]
51793 // SIMD-ONLY0-NEXT:    br i1 [[CMP5736]], label [[IF_THEN5738:%.*]], label [[IF_ELSE5739:%.*]]
51794 // SIMD-ONLY0:       if.then5738:
51795 // SIMD-ONLY0-NEXT:    [[TMP4346:%.*]] = load i64, ptr [[ULLD]], align 8
51796 // SIMD-ONLY0-NEXT:    store i64 [[TMP4346]], ptr [[ULLX]], align 8
51797 // SIMD-ONLY0-NEXT:    br label [[IF_END5740:%.*]]
51798 // SIMD-ONLY0:       if.else5739:
51799 // SIMD-ONLY0-NEXT:    [[TMP4347:%.*]] = load i64, ptr [[ULLX]], align 8
51800 // SIMD-ONLY0-NEXT:    store i64 [[TMP4347]], ptr [[ULLV]], align 8
51801 // SIMD-ONLY0-NEXT:    br label [[IF_END5740]]
51802 // SIMD-ONLY0:       if.end5740:
51803 // SIMD-ONLY0-NEXT:    [[TMP4348:%.*]] = load i64, ptr [[ULLX]], align 8
51804 // SIMD-ONLY0-NEXT:    [[TMP4349:%.*]] = load i64, ptr [[ULLE]], align 8
51805 // SIMD-ONLY0-NEXT:    [[CMP5741:%.*]] = icmp eq i64 [[TMP4348]], [[TMP4349]]
51806 // SIMD-ONLY0-NEXT:    [[CONV5742:%.*]] = zext i1 [[CMP5741]] to i32
51807 // SIMD-ONLY0-NEXT:    [[CONV5743:%.*]] = sext i32 [[CONV5742]] to i64
51808 // SIMD-ONLY0-NEXT:    store i64 [[CONV5743]], ptr [[ULLR]], align 8
51809 // SIMD-ONLY0-NEXT:    [[TMP4350:%.*]] = load i64, ptr [[ULLR]], align 8
51810 // SIMD-ONLY0-NEXT:    [[TOBOOL5744:%.*]] = icmp ne i64 [[TMP4350]], 0
51811 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5744]], label [[IF_THEN5745:%.*]], label [[IF_END5746:%.*]]
51812 // SIMD-ONLY0:       if.then5745:
51813 // SIMD-ONLY0-NEXT:    [[TMP4351:%.*]] = load i64, ptr [[ULLD]], align 8
51814 // SIMD-ONLY0-NEXT:    store i64 [[TMP4351]], ptr [[ULLX]], align 8
51815 // SIMD-ONLY0-NEXT:    br label [[IF_END5746]]
51816 // SIMD-ONLY0:       if.end5746:
51817 // SIMD-ONLY0-NEXT:    [[TMP4352:%.*]] = load i64, ptr [[ULLE]], align 8
51818 // SIMD-ONLY0-NEXT:    [[TMP4353:%.*]] = load i64, ptr [[ULLX]], align 8
51819 // SIMD-ONLY0-NEXT:    [[CMP5747:%.*]] = icmp eq i64 [[TMP4352]], [[TMP4353]]
51820 // SIMD-ONLY0-NEXT:    [[CONV5748:%.*]] = zext i1 [[CMP5747]] to i32
51821 // SIMD-ONLY0-NEXT:    [[CONV5749:%.*]] = sext i32 [[CONV5748]] to i64
51822 // SIMD-ONLY0-NEXT:    store i64 [[CONV5749]], ptr [[ULLR]], align 8
51823 // SIMD-ONLY0-NEXT:    [[TMP4354:%.*]] = load i64, ptr [[ULLR]], align 8
51824 // SIMD-ONLY0-NEXT:    [[TOBOOL5750:%.*]] = icmp ne i64 [[TMP4354]], 0
51825 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5750]], label [[IF_THEN5751:%.*]], label [[IF_END5752:%.*]]
51826 // SIMD-ONLY0:       if.then5751:
51827 // SIMD-ONLY0-NEXT:    [[TMP4355:%.*]] = load i64, ptr [[ULLD]], align 8
51828 // SIMD-ONLY0-NEXT:    store i64 [[TMP4355]], ptr [[ULLX]], align 8
51829 // SIMD-ONLY0-NEXT:    br label [[IF_END5752]]
51830 // SIMD-ONLY0:       if.end5752:
51831 // SIMD-ONLY0-NEXT:    [[TMP4356:%.*]] = load i64, ptr [[ULLX]], align 8
51832 // SIMD-ONLY0-NEXT:    [[TMP4357:%.*]] = load i64, ptr [[ULLE]], align 8
51833 // SIMD-ONLY0-NEXT:    [[CMP5753:%.*]] = icmp eq i64 [[TMP4356]], [[TMP4357]]
51834 // SIMD-ONLY0-NEXT:    [[CONV5754:%.*]] = zext i1 [[CMP5753]] to i32
51835 // SIMD-ONLY0-NEXT:    [[CONV5755:%.*]] = sext i32 [[CONV5754]] to i64
51836 // SIMD-ONLY0-NEXT:    store i64 [[CONV5755]], ptr [[ULLR]], align 8
51837 // SIMD-ONLY0-NEXT:    [[TMP4358:%.*]] = load i64, ptr [[ULLR]], align 8
51838 // SIMD-ONLY0-NEXT:    [[TOBOOL5756:%.*]] = icmp ne i64 [[TMP4358]], 0
51839 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5756]], label [[IF_THEN5757:%.*]], label [[IF_ELSE5758:%.*]]
51840 // SIMD-ONLY0:       if.then5757:
51841 // SIMD-ONLY0-NEXT:    [[TMP4359:%.*]] = load i64, ptr [[ULLD]], align 8
51842 // SIMD-ONLY0-NEXT:    store i64 [[TMP4359]], ptr [[ULLX]], align 8
51843 // SIMD-ONLY0-NEXT:    br label [[IF_END5759:%.*]]
51844 // SIMD-ONLY0:       if.else5758:
51845 // SIMD-ONLY0-NEXT:    [[TMP4360:%.*]] = load i64, ptr [[ULLX]], align 8
51846 // SIMD-ONLY0-NEXT:    store i64 [[TMP4360]], ptr [[ULLV]], align 8
51847 // SIMD-ONLY0-NEXT:    br label [[IF_END5759]]
51848 // SIMD-ONLY0:       if.end5759:
51849 // SIMD-ONLY0-NEXT:    [[TMP4361:%.*]] = load i64, ptr [[ULLE]], align 8
51850 // SIMD-ONLY0-NEXT:    [[TMP4362:%.*]] = load i64, ptr [[ULLX]], align 8
51851 // SIMD-ONLY0-NEXT:    [[CMP5760:%.*]] = icmp eq i64 [[TMP4361]], [[TMP4362]]
51852 // SIMD-ONLY0-NEXT:    [[CONV5761:%.*]] = zext i1 [[CMP5760]] to i32
51853 // SIMD-ONLY0-NEXT:    [[CONV5762:%.*]] = sext i32 [[CONV5761]] to i64
51854 // SIMD-ONLY0-NEXT:    store i64 [[CONV5762]], ptr [[ULLR]], align 8
51855 // SIMD-ONLY0-NEXT:    [[TMP4363:%.*]] = load i64, ptr [[ULLR]], align 8
51856 // SIMD-ONLY0-NEXT:    [[TOBOOL5763:%.*]] = icmp ne i64 [[TMP4363]], 0
51857 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5763]], label [[IF_THEN5764:%.*]], label [[IF_ELSE5765:%.*]]
51858 // SIMD-ONLY0:       if.then5764:
51859 // SIMD-ONLY0-NEXT:    [[TMP4364:%.*]] = load i64, ptr [[ULLD]], align 8
51860 // SIMD-ONLY0-NEXT:    store i64 [[TMP4364]], ptr [[ULLX]], align 8
51861 // SIMD-ONLY0-NEXT:    br label [[IF_END5766:%.*]]
51862 // SIMD-ONLY0:       if.else5765:
51863 // SIMD-ONLY0-NEXT:    [[TMP4365:%.*]] = load i64, ptr [[ULLX]], align 8
51864 // SIMD-ONLY0-NEXT:    store i64 [[TMP4365]], ptr [[ULLV]], align 8
51865 // SIMD-ONLY0-NEXT:    br label [[IF_END5766]]
51866 // SIMD-ONLY0:       if.end5766:
51867 // SIMD-ONLY0-NEXT:    [[TMP4366:%.*]] = load i64, ptr [[ULLX]], align 8
51868 // SIMD-ONLY0-NEXT:    store i64 [[TMP4366]], ptr [[ULLV]], align 8
51869 // SIMD-ONLY0-NEXT:    [[TMP4367:%.*]] = load i64, ptr [[ULLE]], align 8
51870 // SIMD-ONLY0-NEXT:    [[TMP4368:%.*]] = load i64, ptr [[ULLX]], align 8
51871 // SIMD-ONLY0-NEXT:    [[CMP5767:%.*]] = icmp ugt i64 [[TMP4367]], [[TMP4368]]
51872 // SIMD-ONLY0-NEXT:    br i1 [[CMP5767]], label [[IF_THEN5769:%.*]], label [[IF_END5770:%.*]]
51873 // SIMD-ONLY0:       if.then5769:
51874 // SIMD-ONLY0-NEXT:    [[TMP4369:%.*]] = load i64, ptr [[ULLE]], align 8
51875 // SIMD-ONLY0-NEXT:    store i64 [[TMP4369]], ptr [[ULLX]], align 8
51876 // SIMD-ONLY0-NEXT:    br label [[IF_END5770]]
51877 // SIMD-ONLY0:       if.end5770:
51878 // SIMD-ONLY0-NEXT:    [[TMP4370:%.*]] = load i64, ptr [[ULLX]], align 8
51879 // SIMD-ONLY0-NEXT:    store i64 [[TMP4370]], ptr [[ULLV]], align 8
51880 // SIMD-ONLY0-NEXT:    [[TMP4371:%.*]] = load i64, ptr [[ULLX]], align 8
51881 // SIMD-ONLY0-NEXT:    [[TMP4372:%.*]] = load i64, ptr [[ULLE]], align 8
51882 // SIMD-ONLY0-NEXT:    [[CMP5771:%.*]] = icmp ugt i64 [[TMP4371]], [[TMP4372]]
51883 // SIMD-ONLY0-NEXT:    br i1 [[CMP5771]], label [[IF_THEN5773:%.*]], label [[IF_END5774:%.*]]
51884 // SIMD-ONLY0:       if.then5773:
51885 // SIMD-ONLY0-NEXT:    [[TMP4373:%.*]] = load i64, ptr [[ULLE]], align 8
51886 // SIMD-ONLY0-NEXT:    store i64 [[TMP4373]], ptr [[ULLX]], align 8
51887 // SIMD-ONLY0-NEXT:    br label [[IF_END5774]]
51888 // SIMD-ONLY0:       if.end5774:
51889 // SIMD-ONLY0-NEXT:    [[TMP4374:%.*]] = load i64, ptr [[ULLX]], align 8
51890 // SIMD-ONLY0-NEXT:    store i64 [[TMP4374]], ptr [[ULLV]], align 8
51891 // SIMD-ONLY0-NEXT:    [[TMP4375:%.*]] = load i64, ptr [[ULLE]], align 8
51892 // SIMD-ONLY0-NEXT:    [[TMP4376:%.*]] = load i64, ptr [[ULLX]], align 8
51893 // SIMD-ONLY0-NEXT:    [[CMP5775:%.*]] = icmp ult i64 [[TMP4375]], [[TMP4376]]
51894 // SIMD-ONLY0-NEXT:    br i1 [[CMP5775]], label [[IF_THEN5777:%.*]], label [[IF_END5778:%.*]]
51895 // SIMD-ONLY0:       if.then5777:
51896 // SIMD-ONLY0-NEXT:    [[TMP4377:%.*]] = load i64, ptr [[ULLE]], align 8
51897 // SIMD-ONLY0-NEXT:    store i64 [[TMP4377]], ptr [[ULLX]], align 8
51898 // SIMD-ONLY0-NEXT:    br label [[IF_END5778]]
51899 // SIMD-ONLY0:       if.end5778:
51900 // SIMD-ONLY0-NEXT:    [[TMP4378:%.*]] = load i64, ptr [[ULLX]], align 8
51901 // SIMD-ONLY0-NEXT:    store i64 [[TMP4378]], ptr [[ULLV]], align 8
51902 // SIMD-ONLY0-NEXT:    [[TMP4379:%.*]] = load i64, ptr [[ULLX]], align 8
51903 // SIMD-ONLY0-NEXT:    [[TMP4380:%.*]] = load i64, ptr [[ULLE]], align 8
51904 // SIMD-ONLY0-NEXT:    [[CMP5779:%.*]] = icmp ult i64 [[TMP4379]], [[TMP4380]]
51905 // SIMD-ONLY0-NEXT:    br i1 [[CMP5779]], label [[IF_THEN5781:%.*]], label [[IF_END5782:%.*]]
51906 // SIMD-ONLY0:       if.then5781:
51907 // SIMD-ONLY0-NEXT:    [[TMP4381:%.*]] = load i64, ptr [[ULLE]], align 8
51908 // SIMD-ONLY0-NEXT:    store i64 [[TMP4381]], ptr [[ULLX]], align 8
51909 // SIMD-ONLY0-NEXT:    br label [[IF_END5782]]
51910 // SIMD-ONLY0:       if.end5782:
51911 // SIMD-ONLY0-NEXT:    [[TMP4382:%.*]] = load i64, ptr [[ULLX]], align 8
51912 // SIMD-ONLY0-NEXT:    store i64 [[TMP4382]], ptr [[ULLV]], align 8
51913 // SIMD-ONLY0-NEXT:    [[TMP4383:%.*]] = load i64, ptr [[ULLX]], align 8
51914 // SIMD-ONLY0-NEXT:    [[TMP4384:%.*]] = load i64, ptr [[ULLE]], align 8
51915 // SIMD-ONLY0-NEXT:    [[CMP5783:%.*]] = icmp eq i64 [[TMP4383]], [[TMP4384]]
51916 // SIMD-ONLY0-NEXT:    br i1 [[CMP5783]], label [[IF_THEN5785:%.*]], label [[IF_END5786:%.*]]
51917 // SIMD-ONLY0:       if.then5785:
51918 // SIMD-ONLY0-NEXT:    [[TMP4385:%.*]] = load i64, ptr [[ULLD]], align 8
51919 // SIMD-ONLY0-NEXT:    store i64 [[TMP4385]], ptr [[ULLX]], align 8
51920 // SIMD-ONLY0-NEXT:    br label [[IF_END5786]]
51921 // SIMD-ONLY0:       if.end5786:
51922 // SIMD-ONLY0-NEXT:    [[TMP4386:%.*]] = load i64, ptr [[ULLX]], align 8
51923 // SIMD-ONLY0-NEXT:    store i64 [[TMP4386]], ptr [[ULLV]], align 8
51924 // SIMD-ONLY0-NEXT:    [[TMP4387:%.*]] = load i64, ptr [[ULLE]], align 8
51925 // SIMD-ONLY0-NEXT:    [[TMP4388:%.*]] = load i64, ptr [[ULLX]], align 8
51926 // SIMD-ONLY0-NEXT:    [[CMP5787:%.*]] = icmp eq i64 [[TMP4387]], [[TMP4388]]
51927 // SIMD-ONLY0-NEXT:    br i1 [[CMP5787]], label [[IF_THEN5789:%.*]], label [[IF_END5790:%.*]]
51928 // SIMD-ONLY0:       if.then5789:
51929 // SIMD-ONLY0-NEXT:    [[TMP4389:%.*]] = load i64, ptr [[ULLD]], align 8
51930 // SIMD-ONLY0-NEXT:    store i64 [[TMP4389]], ptr [[ULLX]], align 8
51931 // SIMD-ONLY0-NEXT:    br label [[IF_END5790]]
51932 // SIMD-ONLY0:       if.end5790:
51933 // SIMD-ONLY0-NEXT:    [[TMP4390:%.*]] = load i64, ptr [[ULLE]], align 8
51934 // SIMD-ONLY0-NEXT:    [[TMP4391:%.*]] = load i64, ptr [[ULLX]], align 8
51935 // SIMD-ONLY0-NEXT:    [[CMP5791:%.*]] = icmp ugt i64 [[TMP4390]], [[TMP4391]]
51936 // SIMD-ONLY0-NEXT:    br i1 [[CMP5791]], label [[IF_THEN5793:%.*]], label [[IF_END5794:%.*]]
51937 // SIMD-ONLY0:       if.then5793:
51938 // SIMD-ONLY0-NEXT:    [[TMP4392:%.*]] = load i64, ptr [[ULLE]], align 8
51939 // SIMD-ONLY0-NEXT:    store i64 [[TMP4392]], ptr [[ULLX]], align 8
51940 // SIMD-ONLY0-NEXT:    br label [[IF_END5794]]
51941 // SIMD-ONLY0:       if.end5794:
51942 // SIMD-ONLY0-NEXT:    [[TMP4393:%.*]] = load i64, ptr [[ULLX]], align 8
51943 // SIMD-ONLY0-NEXT:    store i64 [[TMP4393]], ptr [[ULLV]], align 8
51944 // SIMD-ONLY0-NEXT:    [[TMP4394:%.*]] = load i64, ptr [[ULLX]], align 8
51945 // SIMD-ONLY0-NEXT:    [[TMP4395:%.*]] = load i64, ptr [[ULLE]], align 8
51946 // SIMD-ONLY0-NEXT:    [[CMP5795:%.*]] = icmp ugt i64 [[TMP4394]], [[TMP4395]]
51947 // SIMD-ONLY0-NEXT:    br i1 [[CMP5795]], label [[IF_THEN5797:%.*]], label [[IF_END5798:%.*]]
51948 // SIMD-ONLY0:       if.then5797:
51949 // SIMD-ONLY0-NEXT:    [[TMP4396:%.*]] = load i64, ptr [[ULLE]], align 8
51950 // SIMD-ONLY0-NEXT:    store i64 [[TMP4396]], ptr [[ULLX]], align 8
51951 // SIMD-ONLY0-NEXT:    br label [[IF_END5798]]
51952 // SIMD-ONLY0:       if.end5798:
51953 // SIMD-ONLY0-NEXT:    [[TMP4397:%.*]] = load i64, ptr [[ULLX]], align 8
51954 // SIMD-ONLY0-NEXT:    store i64 [[TMP4397]], ptr [[ULLV]], align 8
51955 // SIMD-ONLY0-NEXT:    [[TMP4398:%.*]] = load i64, ptr [[ULLE]], align 8
51956 // SIMD-ONLY0-NEXT:    [[TMP4399:%.*]] = load i64, ptr [[ULLX]], align 8
51957 // SIMD-ONLY0-NEXT:    [[CMP5799:%.*]] = icmp ult i64 [[TMP4398]], [[TMP4399]]
51958 // SIMD-ONLY0-NEXT:    br i1 [[CMP5799]], label [[IF_THEN5801:%.*]], label [[IF_END5802:%.*]]
51959 // SIMD-ONLY0:       if.then5801:
51960 // SIMD-ONLY0-NEXT:    [[TMP4400:%.*]] = load i64, ptr [[ULLE]], align 8
51961 // SIMD-ONLY0-NEXT:    store i64 [[TMP4400]], ptr [[ULLX]], align 8
51962 // SIMD-ONLY0-NEXT:    br label [[IF_END5802]]
51963 // SIMD-ONLY0:       if.end5802:
51964 // SIMD-ONLY0-NEXT:    [[TMP4401:%.*]] = load i64, ptr [[ULLX]], align 8
51965 // SIMD-ONLY0-NEXT:    store i64 [[TMP4401]], ptr [[ULLV]], align 8
51966 // SIMD-ONLY0-NEXT:    [[TMP4402:%.*]] = load i64, ptr [[ULLX]], align 8
51967 // SIMD-ONLY0-NEXT:    [[TMP4403:%.*]] = load i64, ptr [[ULLE]], align 8
51968 // SIMD-ONLY0-NEXT:    [[CMP5803:%.*]] = icmp ult i64 [[TMP4402]], [[TMP4403]]
51969 // SIMD-ONLY0-NEXT:    br i1 [[CMP5803]], label [[IF_THEN5805:%.*]], label [[IF_END5806:%.*]]
51970 // SIMD-ONLY0:       if.then5805:
51971 // SIMD-ONLY0-NEXT:    [[TMP4404:%.*]] = load i64, ptr [[ULLE]], align 8
51972 // SIMD-ONLY0-NEXT:    store i64 [[TMP4404]], ptr [[ULLX]], align 8
51973 // SIMD-ONLY0-NEXT:    br label [[IF_END5806]]
51974 // SIMD-ONLY0:       if.end5806:
51975 // SIMD-ONLY0-NEXT:    [[TMP4405:%.*]] = load i64, ptr [[ULLX]], align 8
51976 // SIMD-ONLY0-NEXT:    store i64 [[TMP4405]], ptr [[ULLV]], align 8
51977 // SIMD-ONLY0-NEXT:    [[TMP4406:%.*]] = load i64, ptr [[ULLX]], align 8
51978 // SIMD-ONLY0-NEXT:    [[TMP4407:%.*]] = load i64, ptr [[ULLE]], align 8
51979 // SIMD-ONLY0-NEXT:    [[CMP5807:%.*]] = icmp eq i64 [[TMP4406]], [[TMP4407]]
51980 // SIMD-ONLY0-NEXT:    br i1 [[CMP5807]], label [[IF_THEN5809:%.*]], label [[IF_END5810:%.*]]
51981 // SIMD-ONLY0:       if.then5809:
51982 // SIMD-ONLY0-NEXT:    [[TMP4408:%.*]] = load i64, ptr [[ULLD]], align 8
51983 // SIMD-ONLY0-NEXT:    store i64 [[TMP4408]], ptr [[ULLX]], align 8
51984 // SIMD-ONLY0-NEXT:    br label [[IF_END5810]]
51985 // SIMD-ONLY0:       if.end5810:
51986 // SIMD-ONLY0-NEXT:    [[TMP4409:%.*]] = load i64, ptr [[ULLX]], align 8
51987 // SIMD-ONLY0-NEXT:    store i64 [[TMP4409]], ptr [[ULLV]], align 8
51988 // SIMD-ONLY0-NEXT:    [[TMP4410:%.*]] = load i64, ptr [[ULLE]], align 8
51989 // SIMD-ONLY0-NEXT:    [[TMP4411:%.*]] = load i64, ptr [[ULLX]], align 8
51990 // SIMD-ONLY0-NEXT:    [[CMP5811:%.*]] = icmp eq i64 [[TMP4410]], [[TMP4411]]
51991 // SIMD-ONLY0-NEXT:    br i1 [[CMP5811]], label [[IF_THEN5813:%.*]], label [[IF_END5814:%.*]]
51992 // SIMD-ONLY0:       if.then5813:
51993 // SIMD-ONLY0-NEXT:    [[TMP4412:%.*]] = load i64, ptr [[ULLD]], align 8
51994 // SIMD-ONLY0-NEXT:    store i64 [[TMP4412]], ptr [[ULLX]], align 8
51995 // SIMD-ONLY0-NEXT:    br label [[IF_END5814]]
51996 // SIMD-ONLY0:       if.end5814:
51997 // SIMD-ONLY0-NEXT:    [[TMP4413:%.*]] = load i64, ptr [[ULLX]], align 8
51998 // SIMD-ONLY0-NEXT:    store i64 [[TMP4413]], ptr [[ULLV]], align 8
51999 // SIMD-ONLY0-NEXT:    [[TMP4414:%.*]] = load i64, ptr [[ULLX]], align 8
52000 // SIMD-ONLY0-NEXT:    [[TMP4415:%.*]] = load i64, ptr [[ULLE]], align 8
52001 // SIMD-ONLY0-NEXT:    [[CMP5815:%.*]] = icmp eq i64 [[TMP4414]], [[TMP4415]]
52002 // SIMD-ONLY0-NEXT:    br i1 [[CMP5815]], label [[IF_THEN5817:%.*]], label [[IF_ELSE5818:%.*]]
52003 // SIMD-ONLY0:       if.then5817:
52004 // SIMD-ONLY0-NEXT:    [[TMP4416:%.*]] = load i64, ptr [[ULLD]], align 8
52005 // SIMD-ONLY0-NEXT:    store i64 [[TMP4416]], ptr [[ULLX]], align 8
52006 // SIMD-ONLY0-NEXT:    br label [[IF_END5819:%.*]]
52007 // SIMD-ONLY0:       if.else5818:
52008 // SIMD-ONLY0-NEXT:    [[TMP4417:%.*]] = load i64, ptr [[ULLX]], align 8
52009 // SIMD-ONLY0-NEXT:    store i64 [[TMP4417]], ptr [[ULLV]], align 8
52010 // SIMD-ONLY0-NEXT:    br label [[IF_END5819]]
52011 // SIMD-ONLY0:       if.end5819:
52012 // SIMD-ONLY0-NEXT:    [[TMP4418:%.*]] = load i64, ptr [[ULLE]], align 8
52013 // SIMD-ONLY0-NEXT:    [[TMP4419:%.*]] = load i64, ptr [[ULLX]], align 8
52014 // SIMD-ONLY0-NEXT:    [[CMP5820:%.*]] = icmp eq i64 [[TMP4418]], [[TMP4419]]
52015 // SIMD-ONLY0-NEXT:    br i1 [[CMP5820]], label [[IF_THEN5822:%.*]], label [[IF_ELSE5823:%.*]]
52016 // SIMD-ONLY0:       if.then5822:
52017 // SIMD-ONLY0-NEXT:    [[TMP4420:%.*]] = load i64, ptr [[ULLD]], align 8
52018 // SIMD-ONLY0-NEXT:    store i64 [[TMP4420]], ptr [[ULLX]], align 8
52019 // SIMD-ONLY0-NEXT:    br label [[IF_END5824:%.*]]
52020 // SIMD-ONLY0:       if.else5823:
52021 // SIMD-ONLY0-NEXT:    [[TMP4421:%.*]] = load i64, ptr [[ULLX]], align 8
52022 // SIMD-ONLY0-NEXT:    store i64 [[TMP4421]], ptr [[ULLV]], align 8
52023 // SIMD-ONLY0-NEXT:    br label [[IF_END5824]]
52024 // SIMD-ONLY0:       if.end5824:
52025 // SIMD-ONLY0-NEXT:    [[TMP4422:%.*]] = load i64, ptr [[ULLX]], align 8
52026 // SIMD-ONLY0-NEXT:    [[TMP4423:%.*]] = load i64, ptr [[ULLE]], align 8
52027 // SIMD-ONLY0-NEXT:    [[CMP5825:%.*]] = icmp eq i64 [[TMP4422]], [[TMP4423]]
52028 // SIMD-ONLY0-NEXT:    [[CONV5826:%.*]] = zext i1 [[CMP5825]] to i32
52029 // SIMD-ONLY0-NEXT:    [[CONV5827:%.*]] = sext i32 [[CONV5826]] to i64
52030 // SIMD-ONLY0-NEXT:    store i64 [[CONV5827]], ptr [[ULLR]], align 8
52031 // SIMD-ONLY0-NEXT:    [[TMP4424:%.*]] = load i64, ptr [[ULLR]], align 8
52032 // SIMD-ONLY0-NEXT:    [[TOBOOL5828:%.*]] = icmp ne i64 [[TMP4424]], 0
52033 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5828]], label [[IF_THEN5829:%.*]], label [[IF_END5830:%.*]]
52034 // SIMD-ONLY0:       if.then5829:
52035 // SIMD-ONLY0-NEXT:    [[TMP4425:%.*]] = load i64, ptr [[ULLD]], align 8
52036 // SIMD-ONLY0-NEXT:    store i64 [[TMP4425]], ptr [[ULLX]], align 8
52037 // SIMD-ONLY0-NEXT:    br label [[IF_END5830]]
52038 // SIMD-ONLY0:       if.end5830:
52039 // SIMD-ONLY0-NEXT:    [[TMP4426:%.*]] = load i64, ptr [[ULLE]], align 8
52040 // SIMD-ONLY0-NEXT:    [[TMP4427:%.*]] = load i64, ptr [[ULLX]], align 8
52041 // SIMD-ONLY0-NEXT:    [[CMP5831:%.*]] = icmp eq i64 [[TMP4426]], [[TMP4427]]
52042 // SIMD-ONLY0-NEXT:    [[CONV5832:%.*]] = zext i1 [[CMP5831]] to i32
52043 // SIMD-ONLY0-NEXT:    [[CONV5833:%.*]] = sext i32 [[CONV5832]] to i64
52044 // SIMD-ONLY0-NEXT:    store i64 [[CONV5833]], ptr [[ULLR]], align 8
52045 // SIMD-ONLY0-NEXT:    [[TMP4428:%.*]] = load i64, ptr [[ULLR]], align 8
52046 // SIMD-ONLY0-NEXT:    [[TOBOOL5834:%.*]] = icmp ne i64 [[TMP4428]], 0
52047 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5834]], label [[IF_THEN5835:%.*]], label [[IF_END5836:%.*]]
52048 // SIMD-ONLY0:       if.then5835:
52049 // SIMD-ONLY0-NEXT:    [[TMP4429:%.*]] = load i64, ptr [[ULLD]], align 8
52050 // SIMD-ONLY0-NEXT:    store i64 [[TMP4429]], ptr [[ULLX]], align 8
52051 // SIMD-ONLY0-NEXT:    br label [[IF_END5836]]
52052 // SIMD-ONLY0:       if.end5836:
52053 // SIMD-ONLY0-NEXT:    [[TMP4430:%.*]] = load i64, ptr [[ULLX]], align 8
52054 // SIMD-ONLY0-NEXT:    [[TMP4431:%.*]] = load i64, ptr [[ULLE]], align 8
52055 // SIMD-ONLY0-NEXT:    [[CMP5837:%.*]] = icmp eq i64 [[TMP4430]], [[TMP4431]]
52056 // SIMD-ONLY0-NEXT:    [[CONV5838:%.*]] = zext i1 [[CMP5837]] to i32
52057 // SIMD-ONLY0-NEXT:    [[CONV5839:%.*]] = sext i32 [[CONV5838]] to i64
52058 // SIMD-ONLY0-NEXT:    store i64 [[CONV5839]], ptr [[ULLR]], align 8
52059 // SIMD-ONLY0-NEXT:    [[TMP4432:%.*]] = load i64, ptr [[ULLR]], align 8
52060 // SIMD-ONLY0-NEXT:    [[TOBOOL5840:%.*]] = icmp ne i64 [[TMP4432]], 0
52061 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5840]], label [[IF_THEN5841:%.*]], label [[IF_ELSE5842:%.*]]
52062 // SIMD-ONLY0:       if.then5841:
52063 // SIMD-ONLY0-NEXT:    [[TMP4433:%.*]] = load i64, ptr [[ULLD]], align 8
52064 // SIMD-ONLY0-NEXT:    store i64 [[TMP4433]], ptr [[ULLX]], align 8
52065 // SIMD-ONLY0-NEXT:    br label [[IF_END5843:%.*]]
52066 // SIMD-ONLY0:       if.else5842:
52067 // SIMD-ONLY0-NEXT:    [[TMP4434:%.*]] = load i64, ptr [[ULLX]], align 8
52068 // SIMD-ONLY0-NEXT:    store i64 [[TMP4434]], ptr [[ULLV]], align 8
52069 // SIMD-ONLY0-NEXT:    br label [[IF_END5843]]
52070 // SIMD-ONLY0:       if.end5843:
52071 // SIMD-ONLY0-NEXT:    [[TMP4435:%.*]] = load i64, ptr [[ULLE]], align 8
52072 // SIMD-ONLY0-NEXT:    [[TMP4436:%.*]] = load i64, ptr [[ULLX]], align 8
52073 // SIMD-ONLY0-NEXT:    [[CMP5844:%.*]] = icmp eq i64 [[TMP4435]], [[TMP4436]]
52074 // SIMD-ONLY0-NEXT:    [[CONV5845:%.*]] = zext i1 [[CMP5844]] to i32
52075 // SIMD-ONLY0-NEXT:    [[CONV5846:%.*]] = sext i32 [[CONV5845]] to i64
52076 // SIMD-ONLY0-NEXT:    store i64 [[CONV5846]], ptr [[ULLR]], align 8
52077 // SIMD-ONLY0-NEXT:    [[TMP4437:%.*]] = load i64, ptr [[ULLR]], align 8
52078 // SIMD-ONLY0-NEXT:    [[TOBOOL5847:%.*]] = icmp ne i64 [[TMP4437]], 0
52079 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5847]], label [[IF_THEN5848:%.*]], label [[IF_ELSE5849:%.*]]
52080 // SIMD-ONLY0:       if.then5848:
52081 // SIMD-ONLY0-NEXT:    [[TMP4438:%.*]] = load i64, ptr [[ULLD]], align 8
52082 // SIMD-ONLY0-NEXT:    store i64 [[TMP4438]], ptr [[ULLX]], align 8
52083 // SIMD-ONLY0-NEXT:    br label [[IF_END5850:%.*]]
52084 // SIMD-ONLY0:       if.else5849:
52085 // SIMD-ONLY0-NEXT:    [[TMP4439:%.*]] = load i64, ptr [[ULLX]], align 8
52086 // SIMD-ONLY0-NEXT:    store i64 [[TMP4439]], ptr [[ULLV]], align 8
52087 // SIMD-ONLY0-NEXT:    br label [[IF_END5850]]
52088 // SIMD-ONLY0:       if.end5850:
52089 // SIMD-ONLY0-NEXT:    [[TMP4440:%.*]] = load float, ptr [[FX]], align 4
52090 // SIMD-ONLY0-NEXT:    store float [[TMP4440]], ptr [[FV]], align 4
52091 // SIMD-ONLY0-NEXT:    [[TMP4441:%.*]] = load float, ptr [[FE]], align 4
52092 // SIMD-ONLY0-NEXT:    [[TMP4442:%.*]] = load float, ptr [[FX]], align 4
52093 // SIMD-ONLY0-NEXT:    [[CMP5851:%.*]] = fcmp ogt float [[TMP4441]], [[TMP4442]]
52094 // SIMD-ONLY0-NEXT:    br i1 [[CMP5851]], label [[IF_THEN5853:%.*]], label [[IF_END5854:%.*]]
52095 // SIMD-ONLY0:       if.then5853:
52096 // SIMD-ONLY0-NEXT:    [[TMP4443:%.*]] = load float, ptr [[FE]], align 4
52097 // SIMD-ONLY0-NEXT:    store float [[TMP4443]], ptr [[FX]], align 4
52098 // SIMD-ONLY0-NEXT:    br label [[IF_END5854]]
52099 // SIMD-ONLY0:       if.end5854:
52100 // SIMD-ONLY0-NEXT:    [[TMP4444:%.*]] = load float, ptr [[FX]], align 4
52101 // SIMD-ONLY0-NEXT:    store float [[TMP4444]], ptr [[FV]], align 4
52102 // SIMD-ONLY0-NEXT:    [[TMP4445:%.*]] = load float, ptr [[FX]], align 4
52103 // SIMD-ONLY0-NEXT:    [[TMP4446:%.*]] = load float, ptr [[FE]], align 4
52104 // SIMD-ONLY0-NEXT:    [[CMP5855:%.*]] = fcmp ogt float [[TMP4445]], [[TMP4446]]
52105 // SIMD-ONLY0-NEXT:    br i1 [[CMP5855]], label [[IF_THEN5857:%.*]], label [[IF_END5858:%.*]]
52106 // SIMD-ONLY0:       if.then5857:
52107 // SIMD-ONLY0-NEXT:    [[TMP4447:%.*]] = load float, ptr [[FE]], align 4
52108 // SIMD-ONLY0-NEXT:    store float [[TMP4447]], ptr [[FX]], align 4
52109 // SIMD-ONLY0-NEXT:    br label [[IF_END5858]]
52110 // SIMD-ONLY0:       if.end5858:
52111 // SIMD-ONLY0-NEXT:    [[TMP4448:%.*]] = load float, ptr [[FX]], align 4
52112 // SIMD-ONLY0-NEXT:    store float [[TMP4448]], ptr [[FV]], align 4
52113 // SIMD-ONLY0-NEXT:    [[TMP4449:%.*]] = load float, ptr [[FE]], align 4
52114 // SIMD-ONLY0-NEXT:    [[TMP4450:%.*]] = load float, ptr [[FX]], align 4
52115 // SIMD-ONLY0-NEXT:    [[CMP5859:%.*]] = fcmp olt float [[TMP4449]], [[TMP4450]]
52116 // SIMD-ONLY0-NEXT:    br i1 [[CMP5859]], label [[IF_THEN5861:%.*]], label [[IF_END5862:%.*]]
52117 // SIMD-ONLY0:       if.then5861:
52118 // SIMD-ONLY0-NEXT:    [[TMP4451:%.*]] = load float, ptr [[FE]], align 4
52119 // SIMD-ONLY0-NEXT:    store float [[TMP4451]], ptr [[FX]], align 4
52120 // SIMD-ONLY0-NEXT:    br label [[IF_END5862]]
52121 // SIMD-ONLY0:       if.end5862:
52122 // SIMD-ONLY0-NEXT:    [[TMP4452:%.*]] = load float, ptr [[FX]], align 4
52123 // SIMD-ONLY0-NEXT:    store float [[TMP4452]], ptr [[FV]], align 4
52124 // SIMD-ONLY0-NEXT:    [[TMP4453:%.*]] = load float, ptr [[FX]], align 4
52125 // SIMD-ONLY0-NEXT:    [[TMP4454:%.*]] = load float, ptr [[FE]], align 4
52126 // SIMD-ONLY0-NEXT:    [[CMP5863:%.*]] = fcmp olt float [[TMP4453]], [[TMP4454]]
52127 // SIMD-ONLY0-NEXT:    br i1 [[CMP5863]], label [[IF_THEN5865:%.*]], label [[IF_END5866:%.*]]
52128 // SIMD-ONLY0:       if.then5865:
52129 // SIMD-ONLY0-NEXT:    [[TMP4455:%.*]] = load float, ptr [[FE]], align 4
52130 // SIMD-ONLY0-NEXT:    store float [[TMP4455]], ptr [[FX]], align 4
52131 // SIMD-ONLY0-NEXT:    br label [[IF_END5866]]
52132 // SIMD-ONLY0:       if.end5866:
52133 // SIMD-ONLY0-NEXT:    [[TMP4456:%.*]] = load float, ptr [[FX]], align 4
52134 // SIMD-ONLY0-NEXT:    store float [[TMP4456]], ptr [[FV]], align 4
52135 // SIMD-ONLY0-NEXT:    [[TMP4457:%.*]] = load float, ptr [[FX]], align 4
52136 // SIMD-ONLY0-NEXT:    [[TMP4458:%.*]] = load float, ptr [[FE]], align 4
52137 // SIMD-ONLY0-NEXT:    [[CMP5867:%.*]] = fcmp oeq float [[TMP4457]], [[TMP4458]]
52138 // SIMD-ONLY0-NEXT:    br i1 [[CMP5867]], label [[IF_THEN5869:%.*]], label [[IF_END5870:%.*]]
52139 // SIMD-ONLY0:       if.then5869:
52140 // SIMD-ONLY0-NEXT:    [[TMP4459:%.*]] = load float, ptr [[FD]], align 4
52141 // SIMD-ONLY0-NEXT:    store float [[TMP4459]], ptr [[FX]], align 4
52142 // SIMD-ONLY0-NEXT:    br label [[IF_END5870]]
52143 // SIMD-ONLY0:       if.end5870:
52144 // SIMD-ONLY0-NEXT:    [[TMP4460:%.*]] = load float, ptr [[FX]], align 4
52145 // SIMD-ONLY0-NEXT:    store float [[TMP4460]], ptr [[FV]], align 4
52146 // SIMD-ONLY0-NEXT:    [[TMP4461:%.*]] = load float, ptr [[FE]], align 4
52147 // SIMD-ONLY0-NEXT:    [[TMP4462:%.*]] = load float, ptr [[FX]], align 4
52148 // SIMD-ONLY0-NEXT:    [[CMP5871:%.*]] = fcmp oeq float [[TMP4461]], [[TMP4462]]
52149 // SIMD-ONLY0-NEXT:    br i1 [[CMP5871]], label [[IF_THEN5873:%.*]], label [[IF_END5874:%.*]]
52150 // SIMD-ONLY0:       if.then5873:
52151 // SIMD-ONLY0-NEXT:    [[TMP4463:%.*]] = load float, ptr [[FD]], align 4
52152 // SIMD-ONLY0-NEXT:    store float [[TMP4463]], ptr [[FX]], align 4
52153 // SIMD-ONLY0-NEXT:    br label [[IF_END5874]]
52154 // SIMD-ONLY0:       if.end5874:
52155 // SIMD-ONLY0-NEXT:    [[TMP4464:%.*]] = load float, ptr [[FE]], align 4
52156 // SIMD-ONLY0-NEXT:    [[TMP4465:%.*]] = load float, ptr [[FX]], align 4
52157 // SIMD-ONLY0-NEXT:    [[CMP5875:%.*]] = fcmp ogt float [[TMP4464]], [[TMP4465]]
52158 // SIMD-ONLY0-NEXT:    br i1 [[CMP5875]], label [[IF_THEN5877:%.*]], label [[IF_END5878:%.*]]
52159 // SIMD-ONLY0:       if.then5877:
52160 // SIMD-ONLY0-NEXT:    [[TMP4466:%.*]] = load float, ptr [[FE]], align 4
52161 // SIMD-ONLY0-NEXT:    store float [[TMP4466]], ptr [[FX]], align 4
52162 // SIMD-ONLY0-NEXT:    br label [[IF_END5878]]
52163 // SIMD-ONLY0:       if.end5878:
52164 // SIMD-ONLY0-NEXT:    [[TMP4467:%.*]] = load float, ptr [[FX]], align 4
52165 // SIMD-ONLY0-NEXT:    store float [[TMP4467]], ptr [[FV]], align 4
52166 // SIMD-ONLY0-NEXT:    [[TMP4468:%.*]] = load float, ptr [[FX]], align 4
52167 // SIMD-ONLY0-NEXT:    [[TMP4469:%.*]] = load float, ptr [[FE]], align 4
52168 // SIMD-ONLY0-NEXT:    [[CMP5879:%.*]] = fcmp ogt float [[TMP4468]], [[TMP4469]]
52169 // SIMD-ONLY0-NEXT:    br i1 [[CMP5879]], label [[IF_THEN5881:%.*]], label [[IF_END5882:%.*]]
52170 // SIMD-ONLY0:       if.then5881:
52171 // SIMD-ONLY0-NEXT:    [[TMP4470:%.*]] = load float, ptr [[FE]], align 4
52172 // SIMD-ONLY0-NEXT:    store float [[TMP4470]], ptr [[FX]], align 4
52173 // SIMD-ONLY0-NEXT:    br label [[IF_END5882]]
52174 // SIMD-ONLY0:       if.end5882:
52175 // SIMD-ONLY0-NEXT:    [[TMP4471:%.*]] = load float, ptr [[FX]], align 4
52176 // SIMD-ONLY0-NEXT:    store float [[TMP4471]], ptr [[FV]], align 4
52177 // SIMD-ONLY0-NEXT:    [[TMP4472:%.*]] = load float, ptr [[FE]], align 4
52178 // SIMD-ONLY0-NEXT:    [[TMP4473:%.*]] = load float, ptr [[FX]], align 4
52179 // SIMD-ONLY0-NEXT:    [[CMP5883:%.*]] = fcmp olt float [[TMP4472]], [[TMP4473]]
52180 // SIMD-ONLY0-NEXT:    br i1 [[CMP5883]], label [[IF_THEN5885:%.*]], label [[IF_END5886:%.*]]
52181 // SIMD-ONLY0:       if.then5885:
52182 // SIMD-ONLY0-NEXT:    [[TMP4474:%.*]] = load float, ptr [[FE]], align 4
52183 // SIMD-ONLY0-NEXT:    store float [[TMP4474]], ptr [[FX]], align 4
52184 // SIMD-ONLY0-NEXT:    br label [[IF_END5886]]
52185 // SIMD-ONLY0:       if.end5886:
52186 // SIMD-ONLY0-NEXT:    [[TMP4475:%.*]] = load float, ptr [[FX]], align 4
52187 // SIMD-ONLY0-NEXT:    store float [[TMP4475]], ptr [[FV]], align 4
52188 // SIMD-ONLY0-NEXT:    [[TMP4476:%.*]] = load float, ptr [[FX]], align 4
52189 // SIMD-ONLY0-NEXT:    [[TMP4477:%.*]] = load float, ptr [[FE]], align 4
52190 // SIMD-ONLY0-NEXT:    [[CMP5887:%.*]] = fcmp olt float [[TMP4476]], [[TMP4477]]
52191 // SIMD-ONLY0-NEXT:    br i1 [[CMP5887]], label [[IF_THEN5889:%.*]], label [[IF_END5890:%.*]]
52192 // SIMD-ONLY0:       if.then5889:
52193 // SIMD-ONLY0-NEXT:    [[TMP4478:%.*]] = load float, ptr [[FE]], align 4
52194 // SIMD-ONLY0-NEXT:    store float [[TMP4478]], ptr [[FX]], align 4
52195 // SIMD-ONLY0-NEXT:    br label [[IF_END5890]]
52196 // SIMD-ONLY0:       if.end5890:
52197 // SIMD-ONLY0-NEXT:    [[TMP4479:%.*]] = load float, ptr [[FX]], align 4
52198 // SIMD-ONLY0-NEXT:    store float [[TMP4479]], ptr [[FV]], align 4
52199 // SIMD-ONLY0-NEXT:    [[TMP4480:%.*]] = load float, ptr [[FX]], align 4
52200 // SIMD-ONLY0-NEXT:    [[TMP4481:%.*]] = load float, ptr [[FE]], align 4
52201 // SIMD-ONLY0-NEXT:    [[CMP5891:%.*]] = fcmp oeq float [[TMP4480]], [[TMP4481]]
52202 // SIMD-ONLY0-NEXT:    br i1 [[CMP5891]], label [[IF_THEN5893:%.*]], label [[IF_END5894:%.*]]
52203 // SIMD-ONLY0:       if.then5893:
52204 // SIMD-ONLY0-NEXT:    [[TMP4482:%.*]] = load float, ptr [[FD]], align 4
52205 // SIMD-ONLY0-NEXT:    store float [[TMP4482]], ptr [[FX]], align 4
52206 // SIMD-ONLY0-NEXT:    br label [[IF_END5894]]
52207 // SIMD-ONLY0:       if.end5894:
52208 // SIMD-ONLY0-NEXT:    [[TMP4483:%.*]] = load float, ptr [[FX]], align 4
52209 // SIMD-ONLY0-NEXT:    store float [[TMP4483]], ptr [[FV]], align 4
52210 // SIMD-ONLY0-NEXT:    [[TMP4484:%.*]] = load float, ptr [[FE]], align 4
52211 // SIMD-ONLY0-NEXT:    [[TMP4485:%.*]] = load float, ptr [[FX]], align 4
52212 // SIMD-ONLY0-NEXT:    [[CMP5895:%.*]] = fcmp oeq float [[TMP4484]], [[TMP4485]]
52213 // SIMD-ONLY0-NEXT:    br i1 [[CMP5895]], label [[IF_THEN5897:%.*]], label [[IF_END5898:%.*]]
52214 // SIMD-ONLY0:       if.then5897:
52215 // SIMD-ONLY0-NEXT:    [[TMP4486:%.*]] = load float, ptr [[FD]], align 4
52216 // SIMD-ONLY0-NEXT:    store float [[TMP4486]], ptr [[FX]], align 4
52217 // SIMD-ONLY0-NEXT:    br label [[IF_END5898]]
52218 // SIMD-ONLY0:       if.end5898:
52219 // SIMD-ONLY0-NEXT:    [[TMP4487:%.*]] = load float, ptr [[FX]], align 4
52220 // SIMD-ONLY0-NEXT:    store float [[TMP4487]], ptr [[FV]], align 4
52221 // SIMD-ONLY0-NEXT:    [[TMP4488:%.*]] = load float, ptr [[FX]], align 4
52222 // SIMD-ONLY0-NEXT:    [[TMP4489:%.*]] = load float, ptr [[FE]], align 4
52223 // SIMD-ONLY0-NEXT:    [[CMP5899:%.*]] = fcmp oeq float [[TMP4488]], [[TMP4489]]
52224 // SIMD-ONLY0-NEXT:    br i1 [[CMP5899]], label [[IF_THEN5901:%.*]], label [[IF_ELSE5902:%.*]]
52225 // SIMD-ONLY0:       if.then5901:
52226 // SIMD-ONLY0-NEXT:    [[TMP4490:%.*]] = load float, ptr [[FD]], align 4
52227 // SIMD-ONLY0-NEXT:    store float [[TMP4490]], ptr [[FX]], align 4
52228 // SIMD-ONLY0-NEXT:    br label [[IF_END5903:%.*]]
52229 // SIMD-ONLY0:       if.else5902:
52230 // SIMD-ONLY0-NEXT:    [[TMP4491:%.*]] = load float, ptr [[FX]], align 4
52231 // SIMD-ONLY0-NEXT:    store float [[TMP4491]], ptr [[FV]], align 4
52232 // SIMD-ONLY0-NEXT:    br label [[IF_END5903]]
52233 // SIMD-ONLY0:       if.end5903:
52234 // SIMD-ONLY0-NEXT:    [[TMP4492:%.*]] = load float, ptr [[FE]], align 4
52235 // SIMD-ONLY0-NEXT:    [[TMP4493:%.*]] = load float, ptr [[FX]], align 4
52236 // SIMD-ONLY0-NEXT:    [[CMP5904:%.*]] = fcmp oeq float [[TMP4492]], [[TMP4493]]
52237 // SIMD-ONLY0-NEXT:    br i1 [[CMP5904]], label [[IF_THEN5906:%.*]], label [[IF_ELSE5907:%.*]]
52238 // SIMD-ONLY0:       if.then5906:
52239 // SIMD-ONLY0-NEXT:    [[TMP4494:%.*]] = load float, ptr [[FD]], align 4
52240 // SIMD-ONLY0-NEXT:    store float [[TMP4494]], ptr [[FX]], align 4
52241 // SIMD-ONLY0-NEXT:    br label [[IF_END5908:%.*]]
52242 // SIMD-ONLY0:       if.else5907:
52243 // SIMD-ONLY0-NEXT:    [[TMP4495:%.*]] = load float, ptr [[FX]], align 4
52244 // SIMD-ONLY0-NEXT:    store float [[TMP4495]], ptr [[FV]], align 4
52245 // SIMD-ONLY0-NEXT:    br label [[IF_END5908]]
52246 // SIMD-ONLY0:       if.end5908:
52247 // SIMD-ONLY0-NEXT:    [[TMP4496:%.*]] = load float, ptr [[FX]], align 4
52248 // SIMD-ONLY0-NEXT:    [[TMP4497:%.*]] = load float, ptr [[FE]], align 4
52249 // SIMD-ONLY0-NEXT:    [[CMP5909:%.*]] = fcmp oeq float [[TMP4496]], [[TMP4497]]
52250 // SIMD-ONLY0-NEXT:    [[CONV5910:%.*]] = zext i1 [[CMP5909]] to i32
52251 // SIMD-ONLY0-NEXT:    store i32 [[CONV5910]], ptr [[IR]], align 4
52252 // SIMD-ONLY0-NEXT:    [[TMP4498:%.*]] = load i32, ptr [[IR]], align 4
52253 // SIMD-ONLY0-NEXT:    [[TOBOOL5911:%.*]] = icmp ne i32 [[TMP4498]], 0
52254 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5911]], label [[IF_THEN5912:%.*]], label [[IF_END5913:%.*]]
52255 // SIMD-ONLY0:       if.then5912:
52256 // SIMD-ONLY0-NEXT:    [[TMP4499:%.*]] = load float, ptr [[FD]], align 4
52257 // SIMD-ONLY0-NEXT:    store float [[TMP4499]], ptr [[FX]], align 4
52258 // SIMD-ONLY0-NEXT:    br label [[IF_END5913]]
52259 // SIMD-ONLY0:       if.end5913:
52260 // SIMD-ONLY0-NEXT:    [[TMP4500:%.*]] = load float, ptr [[FE]], align 4
52261 // SIMD-ONLY0-NEXT:    [[TMP4501:%.*]] = load float, ptr [[FX]], align 4
52262 // SIMD-ONLY0-NEXT:    [[CMP5914:%.*]] = fcmp oeq float [[TMP4500]], [[TMP4501]]
52263 // SIMD-ONLY0-NEXT:    [[CONV5915:%.*]] = zext i1 [[CMP5914]] to i32
52264 // SIMD-ONLY0-NEXT:    store i32 [[CONV5915]], ptr [[IR]], align 4
52265 // SIMD-ONLY0-NEXT:    [[TMP4502:%.*]] = load i32, ptr [[IR]], align 4
52266 // SIMD-ONLY0-NEXT:    [[TOBOOL5916:%.*]] = icmp ne i32 [[TMP4502]], 0
52267 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5916]], label [[IF_THEN5917:%.*]], label [[IF_END5918:%.*]]
52268 // SIMD-ONLY0:       if.then5917:
52269 // SIMD-ONLY0-NEXT:    [[TMP4503:%.*]] = load float, ptr [[FD]], align 4
52270 // SIMD-ONLY0-NEXT:    store float [[TMP4503]], ptr [[FX]], align 4
52271 // SIMD-ONLY0-NEXT:    br label [[IF_END5918]]
52272 // SIMD-ONLY0:       if.end5918:
52273 // SIMD-ONLY0-NEXT:    [[TMP4504:%.*]] = load float, ptr [[FX]], align 4
52274 // SIMD-ONLY0-NEXT:    [[TMP4505:%.*]] = load float, ptr [[FE]], align 4
52275 // SIMD-ONLY0-NEXT:    [[CMP5919:%.*]] = fcmp oeq float [[TMP4504]], [[TMP4505]]
52276 // SIMD-ONLY0-NEXT:    [[CONV5920:%.*]] = zext i1 [[CMP5919]] to i32
52277 // SIMD-ONLY0-NEXT:    store i32 [[CONV5920]], ptr [[IR]], align 4
52278 // SIMD-ONLY0-NEXT:    [[TMP4506:%.*]] = load i32, ptr [[IR]], align 4
52279 // SIMD-ONLY0-NEXT:    [[TOBOOL5921:%.*]] = icmp ne i32 [[TMP4506]], 0
52280 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5921]], label [[IF_THEN5922:%.*]], label [[IF_ELSE5923:%.*]]
52281 // SIMD-ONLY0:       if.then5922:
52282 // SIMD-ONLY0-NEXT:    [[TMP4507:%.*]] = load float, ptr [[FD]], align 4
52283 // SIMD-ONLY0-NEXT:    store float [[TMP4507]], ptr [[FX]], align 4
52284 // SIMD-ONLY0-NEXT:    br label [[IF_END5924:%.*]]
52285 // SIMD-ONLY0:       if.else5923:
52286 // SIMD-ONLY0-NEXT:    [[TMP4508:%.*]] = load float, ptr [[FX]], align 4
52287 // SIMD-ONLY0-NEXT:    store float [[TMP4508]], ptr [[FV]], align 4
52288 // SIMD-ONLY0-NEXT:    br label [[IF_END5924]]
52289 // SIMD-ONLY0:       if.end5924:
52290 // SIMD-ONLY0-NEXT:    [[TMP4509:%.*]] = load float, ptr [[FE]], align 4
52291 // SIMD-ONLY0-NEXT:    [[TMP4510:%.*]] = load float, ptr [[FX]], align 4
52292 // SIMD-ONLY0-NEXT:    [[CMP5925:%.*]] = fcmp oeq float [[TMP4509]], [[TMP4510]]
52293 // SIMD-ONLY0-NEXT:    [[CONV5926:%.*]] = zext i1 [[CMP5925]] to i32
52294 // SIMD-ONLY0-NEXT:    store i32 [[CONV5926]], ptr [[IR]], align 4
52295 // SIMD-ONLY0-NEXT:    [[TMP4511:%.*]] = load i32, ptr [[IR]], align 4
52296 // SIMD-ONLY0-NEXT:    [[TOBOOL5927:%.*]] = icmp ne i32 [[TMP4511]], 0
52297 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5927]], label [[IF_THEN5928:%.*]], label [[IF_ELSE5929:%.*]]
52298 // SIMD-ONLY0:       if.then5928:
52299 // SIMD-ONLY0-NEXT:    [[TMP4512:%.*]] = load float, ptr [[FD]], align 4
52300 // SIMD-ONLY0-NEXT:    store float [[TMP4512]], ptr [[FX]], align 4
52301 // SIMD-ONLY0-NEXT:    br label [[IF_END5930:%.*]]
52302 // SIMD-ONLY0:       if.else5929:
52303 // SIMD-ONLY0-NEXT:    [[TMP4513:%.*]] = load float, ptr [[FX]], align 4
52304 // SIMD-ONLY0-NEXT:    store float [[TMP4513]], ptr [[FV]], align 4
52305 // SIMD-ONLY0-NEXT:    br label [[IF_END5930]]
52306 // SIMD-ONLY0:       if.end5930:
52307 // SIMD-ONLY0-NEXT:    [[TMP4514:%.*]] = load float, ptr [[FX]], align 4
52308 // SIMD-ONLY0-NEXT:    store float [[TMP4514]], ptr [[FV]], align 4
52309 // SIMD-ONLY0-NEXT:    [[TMP4515:%.*]] = load float, ptr [[FE]], align 4
52310 // SIMD-ONLY0-NEXT:    [[TMP4516:%.*]] = load float, ptr [[FX]], align 4
52311 // SIMD-ONLY0-NEXT:    [[CMP5931:%.*]] = fcmp ogt float [[TMP4515]], [[TMP4516]]
52312 // SIMD-ONLY0-NEXT:    br i1 [[CMP5931]], label [[IF_THEN5933:%.*]], label [[IF_END5934:%.*]]
52313 // SIMD-ONLY0:       if.then5933:
52314 // SIMD-ONLY0-NEXT:    [[TMP4517:%.*]] = load float, ptr [[FE]], align 4
52315 // SIMD-ONLY0-NEXT:    store float [[TMP4517]], ptr [[FX]], align 4
52316 // SIMD-ONLY0-NEXT:    br label [[IF_END5934]]
52317 // SIMD-ONLY0:       if.end5934:
52318 // SIMD-ONLY0-NEXT:    [[TMP4518:%.*]] = load float, ptr [[FX]], align 4
52319 // SIMD-ONLY0-NEXT:    store float [[TMP4518]], ptr [[FV]], align 4
52320 // SIMD-ONLY0-NEXT:    [[TMP4519:%.*]] = load float, ptr [[FX]], align 4
52321 // SIMD-ONLY0-NEXT:    [[TMP4520:%.*]] = load float, ptr [[FE]], align 4
52322 // SIMD-ONLY0-NEXT:    [[CMP5935:%.*]] = fcmp ogt float [[TMP4519]], [[TMP4520]]
52323 // SIMD-ONLY0-NEXT:    br i1 [[CMP5935]], label [[IF_THEN5937:%.*]], label [[IF_END5938:%.*]]
52324 // SIMD-ONLY0:       if.then5937:
52325 // SIMD-ONLY0-NEXT:    [[TMP4521:%.*]] = load float, ptr [[FE]], align 4
52326 // SIMD-ONLY0-NEXT:    store float [[TMP4521]], ptr [[FX]], align 4
52327 // SIMD-ONLY0-NEXT:    br label [[IF_END5938]]
52328 // SIMD-ONLY0:       if.end5938:
52329 // SIMD-ONLY0-NEXT:    [[TMP4522:%.*]] = load float, ptr [[FX]], align 4
52330 // SIMD-ONLY0-NEXT:    store float [[TMP4522]], ptr [[FV]], align 4
52331 // SIMD-ONLY0-NEXT:    [[TMP4523:%.*]] = load float, ptr [[FE]], align 4
52332 // SIMD-ONLY0-NEXT:    [[TMP4524:%.*]] = load float, ptr [[FX]], align 4
52333 // SIMD-ONLY0-NEXT:    [[CMP5939:%.*]] = fcmp olt float [[TMP4523]], [[TMP4524]]
52334 // SIMD-ONLY0-NEXT:    br i1 [[CMP5939]], label [[IF_THEN5941:%.*]], label [[IF_END5942:%.*]]
52335 // SIMD-ONLY0:       if.then5941:
52336 // SIMD-ONLY0-NEXT:    [[TMP4525:%.*]] = load float, ptr [[FE]], align 4
52337 // SIMD-ONLY0-NEXT:    store float [[TMP4525]], ptr [[FX]], align 4
52338 // SIMD-ONLY0-NEXT:    br label [[IF_END5942]]
52339 // SIMD-ONLY0:       if.end5942:
52340 // SIMD-ONLY0-NEXT:    [[TMP4526:%.*]] = load float, ptr [[FX]], align 4
52341 // SIMD-ONLY0-NEXT:    store float [[TMP4526]], ptr [[FV]], align 4
52342 // SIMD-ONLY0-NEXT:    [[TMP4527:%.*]] = load float, ptr [[FX]], align 4
52343 // SIMD-ONLY0-NEXT:    [[TMP4528:%.*]] = load float, ptr [[FE]], align 4
52344 // SIMD-ONLY0-NEXT:    [[CMP5943:%.*]] = fcmp olt float [[TMP4527]], [[TMP4528]]
52345 // SIMD-ONLY0-NEXT:    br i1 [[CMP5943]], label [[IF_THEN5945:%.*]], label [[IF_END5946:%.*]]
52346 // SIMD-ONLY0:       if.then5945:
52347 // SIMD-ONLY0-NEXT:    [[TMP4529:%.*]] = load float, ptr [[FE]], align 4
52348 // SIMD-ONLY0-NEXT:    store float [[TMP4529]], ptr [[FX]], align 4
52349 // SIMD-ONLY0-NEXT:    br label [[IF_END5946]]
52350 // SIMD-ONLY0:       if.end5946:
52351 // SIMD-ONLY0-NEXT:    [[TMP4530:%.*]] = load float, ptr [[FX]], align 4
52352 // SIMD-ONLY0-NEXT:    store float [[TMP4530]], ptr [[FV]], align 4
52353 // SIMD-ONLY0-NEXT:    [[TMP4531:%.*]] = load float, ptr [[FX]], align 4
52354 // SIMD-ONLY0-NEXT:    [[TMP4532:%.*]] = load float, ptr [[FE]], align 4
52355 // SIMD-ONLY0-NEXT:    [[CMP5947:%.*]] = fcmp oeq float [[TMP4531]], [[TMP4532]]
52356 // SIMD-ONLY0-NEXT:    br i1 [[CMP5947]], label [[IF_THEN5949:%.*]], label [[IF_END5950:%.*]]
52357 // SIMD-ONLY0:       if.then5949:
52358 // SIMD-ONLY0-NEXT:    [[TMP4533:%.*]] = load float, ptr [[FD]], align 4
52359 // SIMD-ONLY0-NEXT:    store float [[TMP4533]], ptr [[FX]], align 4
52360 // SIMD-ONLY0-NEXT:    br label [[IF_END5950]]
52361 // SIMD-ONLY0:       if.end5950:
52362 // SIMD-ONLY0-NEXT:    [[TMP4534:%.*]] = load float, ptr [[FX]], align 4
52363 // SIMD-ONLY0-NEXT:    store float [[TMP4534]], ptr [[FV]], align 4
52364 // SIMD-ONLY0-NEXT:    [[TMP4535:%.*]] = load float, ptr [[FE]], align 4
52365 // SIMD-ONLY0-NEXT:    [[TMP4536:%.*]] = load float, ptr [[FX]], align 4
52366 // SIMD-ONLY0-NEXT:    [[CMP5951:%.*]] = fcmp oeq float [[TMP4535]], [[TMP4536]]
52367 // SIMD-ONLY0-NEXT:    br i1 [[CMP5951]], label [[IF_THEN5953:%.*]], label [[IF_END5954:%.*]]
52368 // SIMD-ONLY0:       if.then5953:
52369 // SIMD-ONLY0-NEXT:    [[TMP4537:%.*]] = load float, ptr [[FD]], align 4
52370 // SIMD-ONLY0-NEXT:    store float [[TMP4537]], ptr [[FX]], align 4
52371 // SIMD-ONLY0-NEXT:    br label [[IF_END5954]]
52372 // SIMD-ONLY0:       if.end5954:
52373 // SIMD-ONLY0-NEXT:    [[TMP4538:%.*]] = load float, ptr [[FE]], align 4
52374 // SIMD-ONLY0-NEXT:    [[TMP4539:%.*]] = load float, ptr [[FX]], align 4
52375 // SIMD-ONLY0-NEXT:    [[CMP5955:%.*]] = fcmp ogt float [[TMP4538]], [[TMP4539]]
52376 // SIMD-ONLY0-NEXT:    br i1 [[CMP5955]], label [[IF_THEN5957:%.*]], label [[IF_END5958:%.*]]
52377 // SIMD-ONLY0:       if.then5957:
52378 // SIMD-ONLY0-NEXT:    [[TMP4540:%.*]] = load float, ptr [[FE]], align 4
52379 // SIMD-ONLY0-NEXT:    store float [[TMP4540]], ptr [[FX]], align 4
52380 // SIMD-ONLY0-NEXT:    br label [[IF_END5958]]
52381 // SIMD-ONLY0:       if.end5958:
52382 // SIMD-ONLY0-NEXT:    [[TMP4541:%.*]] = load float, ptr [[FX]], align 4
52383 // SIMD-ONLY0-NEXT:    store float [[TMP4541]], ptr [[FV]], align 4
52384 // SIMD-ONLY0-NEXT:    [[TMP4542:%.*]] = load float, ptr [[FX]], align 4
52385 // SIMD-ONLY0-NEXT:    [[TMP4543:%.*]] = load float, ptr [[FE]], align 4
52386 // SIMD-ONLY0-NEXT:    [[CMP5959:%.*]] = fcmp ogt float [[TMP4542]], [[TMP4543]]
52387 // SIMD-ONLY0-NEXT:    br i1 [[CMP5959]], label [[IF_THEN5961:%.*]], label [[IF_END5962:%.*]]
52388 // SIMD-ONLY0:       if.then5961:
52389 // SIMD-ONLY0-NEXT:    [[TMP4544:%.*]] = load float, ptr [[FE]], align 4
52390 // SIMD-ONLY0-NEXT:    store float [[TMP4544]], ptr [[FX]], align 4
52391 // SIMD-ONLY0-NEXT:    br label [[IF_END5962]]
52392 // SIMD-ONLY0:       if.end5962:
52393 // SIMD-ONLY0-NEXT:    [[TMP4545:%.*]] = load float, ptr [[FX]], align 4
52394 // SIMD-ONLY0-NEXT:    store float [[TMP4545]], ptr [[FV]], align 4
52395 // SIMD-ONLY0-NEXT:    [[TMP4546:%.*]] = load float, ptr [[FE]], align 4
52396 // SIMD-ONLY0-NEXT:    [[TMP4547:%.*]] = load float, ptr [[FX]], align 4
52397 // SIMD-ONLY0-NEXT:    [[CMP5963:%.*]] = fcmp olt float [[TMP4546]], [[TMP4547]]
52398 // SIMD-ONLY0-NEXT:    br i1 [[CMP5963]], label [[IF_THEN5965:%.*]], label [[IF_END5966:%.*]]
52399 // SIMD-ONLY0:       if.then5965:
52400 // SIMD-ONLY0-NEXT:    [[TMP4548:%.*]] = load float, ptr [[FE]], align 4
52401 // SIMD-ONLY0-NEXT:    store float [[TMP4548]], ptr [[FX]], align 4
52402 // SIMD-ONLY0-NEXT:    br label [[IF_END5966]]
52403 // SIMD-ONLY0:       if.end5966:
52404 // SIMD-ONLY0-NEXT:    [[TMP4549:%.*]] = load float, ptr [[FX]], align 4
52405 // SIMD-ONLY0-NEXT:    store float [[TMP4549]], ptr [[FV]], align 4
52406 // SIMD-ONLY0-NEXT:    [[TMP4550:%.*]] = load float, ptr [[FX]], align 4
52407 // SIMD-ONLY0-NEXT:    [[TMP4551:%.*]] = load float, ptr [[FE]], align 4
52408 // SIMD-ONLY0-NEXT:    [[CMP5967:%.*]] = fcmp olt float [[TMP4550]], [[TMP4551]]
52409 // SIMD-ONLY0-NEXT:    br i1 [[CMP5967]], label [[IF_THEN5969:%.*]], label [[IF_END5970:%.*]]
52410 // SIMD-ONLY0:       if.then5969:
52411 // SIMD-ONLY0-NEXT:    [[TMP4552:%.*]] = load float, ptr [[FE]], align 4
52412 // SIMD-ONLY0-NEXT:    store float [[TMP4552]], ptr [[FX]], align 4
52413 // SIMD-ONLY0-NEXT:    br label [[IF_END5970]]
52414 // SIMD-ONLY0:       if.end5970:
52415 // SIMD-ONLY0-NEXT:    [[TMP4553:%.*]] = load float, ptr [[FX]], align 4
52416 // SIMD-ONLY0-NEXT:    store float [[TMP4553]], ptr [[FV]], align 4
52417 // SIMD-ONLY0-NEXT:    [[TMP4554:%.*]] = load float, ptr [[FX]], align 4
52418 // SIMD-ONLY0-NEXT:    [[TMP4555:%.*]] = load float, ptr [[FE]], align 4
52419 // SIMD-ONLY0-NEXT:    [[CMP5971:%.*]] = fcmp oeq float [[TMP4554]], [[TMP4555]]
52420 // SIMD-ONLY0-NEXT:    br i1 [[CMP5971]], label [[IF_THEN5973:%.*]], label [[IF_END5974:%.*]]
52421 // SIMD-ONLY0:       if.then5973:
52422 // SIMD-ONLY0-NEXT:    [[TMP4556:%.*]] = load float, ptr [[FD]], align 4
52423 // SIMD-ONLY0-NEXT:    store float [[TMP4556]], ptr [[FX]], align 4
52424 // SIMD-ONLY0-NEXT:    br label [[IF_END5974]]
52425 // SIMD-ONLY0:       if.end5974:
52426 // SIMD-ONLY0-NEXT:    [[TMP4557:%.*]] = load float, ptr [[FX]], align 4
52427 // SIMD-ONLY0-NEXT:    store float [[TMP4557]], ptr [[FV]], align 4
52428 // SIMD-ONLY0-NEXT:    [[TMP4558:%.*]] = load float, ptr [[FE]], align 4
52429 // SIMD-ONLY0-NEXT:    [[TMP4559:%.*]] = load float, ptr [[FX]], align 4
52430 // SIMD-ONLY0-NEXT:    [[CMP5975:%.*]] = fcmp oeq float [[TMP4558]], [[TMP4559]]
52431 // SIMD-ONLY0-NEXT:    br i1 [[CMP5975]], label [[IF_THEN5977:%.*]], label [[IF_END5978:%.*]]
52432 // SIMD-ONLY0:       if.then5977:
52433 // SIMD-ONLY0-NEXT:    [[TMP4560:%.*]] = load float, ptr [[FD]], align 4
52434 // SIMD-ONLY0-NEXT:    store float [[TMP4560]], ptr [[FX]], align 4
52435 // SIMD-ONLY0-NEXT:    br label [[IF_END5978]]
52436 // SIMD-ONLY0:       if.end5978:
52437 // SIMD-ONLY0-NEXT:    [[TMP4561:%.*]] = load float, ptr [[FX]], align 4
52438 // SIMD-ONLY0-NEXT:    store float [[TMP4561]], ptr [[FV]], align 4
52439 // SIMD-ONLY0-NEXT:    [[TMP4562:%.*]] = load float, ptr [[FX]], align 4
52440 // SIMD-ONLY0-NEXT:    [[TMP4563:%.*]] = load float, ptr [[FE]], align 4
52441 // SIMD-ONLY0-NEXT:    [[CMP5979:%.*]] = fcmp oeq float [[TMP4562]], [[TMP4563]]
52442 // SIMD-ONLY0-NEXT:    br i1 [[CMP5979]], label [[IF_THEN5981:%.*]], label [[IF_ELSE5982:%.*]]
52443 // SIMD-ONLY0:       if.then5981:
52444 // SIMD-ONLY0-NEXT:    [[TMP4564:%.*]] = load float, ptr [[FD]], align 4
52445 // SIMD-ONLY0-NEXT:    store float [[TMP4564]], ptr [[FX]], align 4
52446 // SIMD-ONLY0-NEXT:    br label [[IF_END5983:%.*]]
52447 // SIMD-ONLY0:       if.else5982:
52448 // SIMD-ONLY0-NEXT:    [[TMP4565:%.*]] = load float, ptr [[FX]], align 4
52449 // SIMD-ONLY0-NEXT:    store float [[TMP4565]], ptr [[FV]], align 4
52450 // SIMD-ONLY0-NEXT:    br label [[IF_END5983]]
52451 // SIMD-ONLY0:       if.end5983:
52452 // SIMD-ONLY0-NEXT:    [[TMP4566:%.*]] = load float, ptr [[FE]], align 4
52453 // SIMD-ONLY0-NEXT:    [[TMP4567:%.*]] = load float, ptr [[FX]], align 4
52454 // SIMD-ONLY0-NEXT:    [[CMP5984:%.*]] = fcmp oeq float [[TMP4566]], [[TMP4567]]
52455 // SIMD-ONLY0-NEXT:    br i1 [[CMP5984]], label [[IF_THEN5986:%.*]], label [[IF_ELSE5987:%.*]]
52456 // SIMD-ONLY0:       if.then5986:
52457 // SIMD-ONLY0-NEXT:    [[TMP4568:%.*]] = load float, ptr [[FD]], align 4
52458 // SIMD-ONLY0-NEXT:    store float [[TMP4568]], ptr [[FX]], align 4
52459 // SIMD-ONLY0-NEXT:    br label [[IF_END5988:%.*]]
52460 // SIMD-ONLY0:       if.else5987:
52461 // SIMD-ONLY0-NEXT:    [[TMP4569:%.*]] = load float, ptr [[FX]], align 4
52462 // SIMD-ONLY0-NEXT:    store float [[TMP4569]], ptr [[FV]], align 4
52463 // SIMD-ONLY0-NEXT:    br label [[IF_END5988]]
52464 // SIMD-ONLY0:       if.end5988:
52465 // SIMD-ONLY0-NEXT:    [[TMP4570:%.*]] = load float, ptr [[FX]], align 4
52466 // SIMD-ONLY0-NEXT:    [[TMP4571:%.*]] = load float, ptr [[FE]], align 4
52467 // SIMD-ONLY0-NEXT:    [[CMP5989:%.*]] = fcmp oeq float [[TMP4570]], [[TMP4571]]
52468 // SIMD-ONLY0-NEXT:    [[CONV5990:%.*]] = zext i1 [[CMP5989]] to i32
52469 // SIMD-ONLY0-NEXT:    store i32 [[CONV5990]], ptr [[IR]], align 4
52470 // SIMD-ONLY0-NEXT:    [[TMP4572:%.*]] = load i32, ptr [[IR]], align 4
52471 // SIMD-ONLY0-NEXT:    [[TOBOOL5991:%.*]] = icmp ne i32 [[TMP4572]], 0
52472 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5991]], label [[IF_THEN5992:%.*]], label [[IF_END5993:%.*]]
52473 // SIMD-ONLY0:       if.then5992:
52474 // SIMD-ONLY0-NEXT:    [[TMP4573:%.*]] = load float, ptr [[FD]], align 4
52475 // SIMD-ONLY0-NEXT:    store float [[TMP4573]], ptr [[FX]], align 4
52476 // SIMD-ONLY0-NEXT:    br label [[IF_END5993]]
52477 // SIMD-ONLY0:       if.end5993:
52478 // SIMD-ONLY0-NEXT:    [[TMP4574:%.*]] = load float, ptr [[FE]], align 4
52479 // SIMD-ONLY0-NEXT:    [[TMP4575:%.*]] = load float, ptr [[FX]], align 4
52480 // SIMD-ONLY0-NEXT:    [[CMP5994:%.*]] = fcmp oeq float [[TMP4574]], [[TMP4575]]
52481 // SIMD-ONLY0-NEXT:    [[CONV5995:%.*]] = zext i1 [[CMP5994]] to i32
52482 // SIMD-ONLY0-NEXT:    store i32 [[CONV5995]], ptr [[IR]], align 4
52483 // SIMD-ONLY0-NEXT:    [[TMP4576:%.*]] = load i32, ptr [[IR]], align 4
52484 // SIMD-ONLY0-NEXT:    [[TOBOOL5996:%.*]] = icmp ne i32 [[TMP4576]], 0
52485 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL5996]], label [[IF_THEN5997:%.*]], label [[IF_END5998:%.*]]
52486 // SIMD-ONLY0:       if.then5997:
52487 // SIMD-ONLY0-NEXT:    [[TMP4577:%.*]] = load float, ptr [[FD]], align 4
52488 // SIMD-ONLY0-NEXT:    store float [[TMP4577]], ptr [[FX]], align 4
52489 // SIMD-ONLY0-NEXT:    br label [[IF_END5998]]
52490 // SIMD-ONLY0:       if.end5998:
52491 // SIMD-ONLY0-NEXT:    [[TMP4578:%.*]] = load float, ptr [[FX]], align 4
52492 // SIMD-ONLY0-NEXT:    [[TMP4579:%.*]] = load float, ptr [[FE]], align 4
52493 // SIMD-ONLY0-NEXT:    [[CMP5999:%.*]] = fcmp oeq float [[TMP4578]], [[TMP4579]]
52494 // SIMD-ONLY0-NEXT:    [[CONV6000:%.*]] = zext i1 [[CMP5999]] to i32
52495 // SIMD-ONLY0-NEXT:    store i32 [[CONV6000]], ptr [[IR]], align 4
52496 // SIMD-ONLY0-NEXT:    [[TMP4580:%.*]] = load i32, ptr [[IR]], align 4
52497 // SIMD-ONLY0-NEXT:    [[TOBOOL6001:%.*]] = icmp ne i32 [[TMP4580]], 0
52498 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6001]], label [[IF_THEN6002:%.*]], label [[IF_ELSE6003:%.*]]
52499 // SIMD-ONLY0:       if.then6002:
52500 // SIMD-ONLY0-NEXT:    [[TMP4581:%.*]] = load float, ptr [[FD]], align 4
52501 // SIMD-ONLY0-NEXT:    store float [[TMP4581]], ptr [[FX]], align 4
52502 // SIMD-ONLY0-NEXT:    br label [[IF_END6004:%.*]]
52503 // SIMD-ONLY0:       if.else6003:
52504 // SIMD-ONLY0-NEXT:    [[TMP4582:%.*]] = load float, ptr [[FX]], align 4
52505 // SIMD-ONLY0-NEXT:    store float [[TMP4582]], ptr [[FV]], align 4
52506 // SIMD-ONLY0-NEXT:    br label [[IF_END6004]]
52507 // SIMD-ONLY0:       if.end6004:
52508 // SIMD-ONLY0-NEXT:    [[TMP4583:%.*]] = load float, ptr [[FE]], align 4
52509 // SIMD-ONLY0-NEXT:    [[TMP4584:%.*]] = load float, ptr [[FX]], align 4
52510 // SIMD-ONLY0-NEXT:    [[CMP6005:%.*]] = fcmp oeq float [[TMP4583]], [[TMP4584]]
52511 // SIMD-ONLY0-NEXT:    [[CONV6006:%.*]] = zext i1 [[CMP6005]] to i32
52512 // SIMD-ONLY0-NEXT:    store i32 [[CONV6006]], ptr [[IR]], align 4
52513 // SIMD-ONLY0-NEXT:    [[TMP4585:%.*]] = load i32, ptr [[IR]], align 4
52514 // SIMD-ONLY0-NEXT:    [[TOBOOL6007:%.*]] = icmp ne i32 [[TMP4585]], 0
52515 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6007]], label [[IF_THEN6008:%.*]], label [[IF_ELSE6009:%.*]]
52516 // SIMD-ONLY0:       if.then6008:
52517 // SIMD-ONLY0-NEXT:    [[TMP4586:%.*]] = load float, ptr [[FD]], align 4
52518 // SIMD-ONLY0-NEXT:    store float [[TMP4586]], ptr [[FX]], align 4
52519 // SIMD-ONLY0-NEXT:    br label [[IF_END6010:%.*]]
52520 // SIMD-ONLY0:       if.else6009:
52521 // SIMD-ONLY0-NEXT:    [[TMP4587:%.*]] = load float, ptr [[FX]], align 4
52522 // SIMD-ONLY0-NEXT:    store float [[TMP4587]], ptr [[FV]], align 4
52523 // SIMD-ONLY0-NEXT:    br label [[IF_END6010]]
52524 // SIMD-ONLY0:       if.end6010:
52525 // SIMD-ONLY0-NEXT:    [[TMP4588:%.*]] = load float, ptr [[FX]], align 4
52526 // SIMD-ONLY0-NEXT:    store float [[TMP4588]], ptr [[FV]], align 4
52527 // SIMD-ONLY0-NEXT:    [[TMP4589:%.*]] = load float, ptr [[FE]], align 4
52528 // SIMD-ONLY0-NEXT:    [[TMP4590:%.*]] = load float, ptr [[FX]], align 4
52529 // SIMD-ONLY0-NEXT:    [[CMP6011:%.*]] = fcmp ogt float [[TMP4589]], [[TMP4590]]
52530 // SIMD-ONLY0-NEXT:    br i1 [[CMP6011]], label [[IF_THEN6013:%.*]], label [[IF_END6014:%.*]]
52531 // SIMD-ONLY0:       if.then6013:
52532 // SIMD-ONLY0-NEXT:    [[TMP4591:%.*]] = load float, ptr [[FE]], align 4
52533 // SIMD-ONLY0-NEXT:    store float [[TMP4591]], ptr [[FX]], align 4
52534 // SIMD-ONLY0-NEXT:    br label [[IF_END6014]]
52535 // SIMD-ONLY0:       if.end6014:
52536 // SIMD-ONLY0-NEXT:    [[TMP4592:%.*]] = load float, ptr [[FX]], align 4
52537 // SIMD-ONLY0-NEXT:    store float [[TMP4592]], ptr [[FV]], align 4
52538 // SIMD-ONLY0-NEXT:    [[TMP4593:%.*]] = load float, ptr [[FX]], align 4
52539 // SIMD-ONLY0-NEXT:    [[TMP4594:%.*]] = load float, ptr [[FE]], align 4
52540 // SIMD-ONLY0-NEXT:    [[CMP6015:%.*]] = fcmp ogt float [[TMP4593]], [[TMP4594]]
52541 // SIMD-ONLY0-NEXT:    br i1 [[CMP6015]], label [[IF_THEN6017:%.*]], label [[IF_END6018:%.*]]
52542 // SIMD-ONLY0:       if.then6017:
52543 // SIMD-ONLY0-NEXT:    [[TMP4595:%.*]] = load float, ptr [[FE]], align 4
52544 // SIMD-ONLY0-NEXT:    store float [[TMP4595]], ptr [[FX]], align 4
52545 // SIMD-ONLY0-NEXT:    br label [[IF_END6018]]
52546 // SIMD-ONLY0:       if.end6018:
52547 // SIMD-ONLY0-NEXT:    [[TMP4596:%.*]] = load float, ptr [[FX]], align 4
52548 // SIMD-ONLY0-NEXT:    store float [[TMP4596]], ptr [[FV]], align 4
52549 // SIMD-ONLY0-NEXT:    [[TMP4597:%.*]] = load float, ptr [[FE]], align 4
52550 // SIMD-ONLY0-NEXT:    [[TMP4598:%.*]] = load float, ptr [[FX]], align 4
52551 // SIMD-ONLY0-NEXT:    [[CMP6019:%.*]] = fcmp olt float [[TMP4597]], [[TMP4598]]
52552 // SIMD-ONLY0-NEXT:    br i1 [[CMP6019]], label [[IF_THEN6021:%.*]], label [[IF_END6022:%.*]]
52553 // SIMD-ONLY0:       if.then6021:
52554 // SIMD-ONLY0-NEXT:    [[TMP4599:%.*]] = load float, ptr [[FE]], align 4
52555 // SIMD-ONLY0-NEXT:    store float [[TMP4599]], ptr [[FX]], align 4
52556 // SIMD-ONLY0-NEXT:    br label [[IF_END6022]]
52557 // SIMD-ONLY0:       if.end6022:
52558 // SIMD-ONLY0-NEXT:    [[TMP4600:%.*]] = load float, ptr [[FX]], align 4
52559 // SIMD-ONLY0-NEXT:    store float [[TMP4600]], ptr [[FV]], align 4
52560 // SIMD-ONLY0-NEXT:    [[TMP4601:%.*]] = load float, ptr [[FX]], align 4
52561 // SIMD-ONLY0-NEXT:    [[TMP4602:%.*]] = load float, ptr [[FE]], align 4
52562 // SIMD-ONLY0-NEXT:    [[CMP6023:%.*]] = fcmp olt float [[TMP4601]], [[TMP4602]]
52563 // SIMD-ONLY0-NEXT:    br i1 [[CMP6023]], label [[IF_THEN6025:%.*]], label [[IF_END6026:%.*]]
52564 // SIMD-ONLY0:       if.then6025:
52565 // SIMD-ONLY0-NEXT:    [[TMP4603:%.*]] = load float, ptr [[FE]], align 4
52566 // SIMD-ONLY0-NEXT:    store float [[TMP4603]], ptr [[FX]], align 4
52567 // SIMD-ONLY0-NEXT:    br label [[IF_END6026]]
52568 // SIMD-ONLY0:       if.end6026:
52569 // SIMD-ONLY0-NEXT:    [[TMP4604:%.*]] = load float, ptr [[FX]], align 4
52570 // SIMD-ONLY0-NEXT:    store float [[TMP4604]], ptr [[FV]], align 4
52571 // SIMD-ONLY0-NEXT:    [[TMP4605:%.*]] = load float, ptr [[FX]], align 4
52572 // SIMD-ONLY0-NEXT:    [[TMP4606:%.*]] = load float, ptr [[FE]], align 4
52573 // SIMD-ONLY0-NEXT:    [[CMP6027:%.*]] = fcmp oeq float [[TMP4605]], [[TMP4606]]
52574 // SIMD-ONLY0-NEXT:    br i1 [[CMP6027]], label [[IF_THEN6029:%.*]], label [[IF_END6030:%.*]]
52575 // SIMD-ONLY0:       if.then6029:
52576 // SIMD-ONLY0-NEXT:    [[TMP4607:%.*]] = load float, ptr [[FD]], align 4
52577 // SIMD-ONLY0-NEXT:    store float [[TMP4607]], ptr [[FX]], align 4
52578 // SIMD-ONLY0-NEXT:    br label [[IF_END6030]]
52579 // SIMD-ONLY0:       if.end6030:
52580 // SIMD-ONLY0-NEXT:    [[TMP4608:%.*]] = load float, ptr [[FX]], align 4
52581 // SIMD-ONLY0-NEXT:    store float [[TMP4608]], ptr [[FV]], align 4
52582 // SIMD-ONLY0-NEXT:    [[TMP4609:%.*]] = load float, ptr [[FE]], align 4
52583 // SIMD-ONLY0-NEXT:    [[TMP4610:%.*]] = load float, ptr [[FX]], align 4
52584 // SIMD-ONLY0-NEXT:    [[CMP6031:%.*]] = fcmp oeq float [[TMP4609]], [[TMP4610]]
52585 // SIMD-ONLY0-NEXT:    br i1 [[CMP6031]], label [[IF_THEN6033:%.*]], label [[IF_END6034:%.*]]
52586 // SIMD-ONLY0:       if.then6033:
52587 // SIMD-ONLY0-NEXT:    [[TMP4611:%.*]] = load float, ptr [[FD]], align 4
52588 // SIMD-ONLY0-NEXT:    store float [[TMP4611]], ptr [[FX]], align 4
52589 // SIMD-ONLY0-NEXT:    br label [[IF_END6034]]
52590 // SIMD-ONLY0:       if.end6034:
52591 // SIMD-ONLY0-NEXT:    [[TMP4612:%.*]] = load float, ptr [[FE]], align 4
52592 // SIMD-ONLY0-NEXT:    [[TMP4613:%.*]] = load float, ptr [[FX]], align 4
52593 // SIMD-ONLY0-NEXT:    [[CMP6035:%.*]] = fcmp ogt float [[TMP4612]], [[TMP4613]]
52594 // SIMD-ONLY0-NEXT:    br i1 [[CMP6035]], label [[IF_THEN6037:%.*]], label [[IF_END6038:%.*]]
52595 // SIMD-ONLY0:       if.then6037:
52596 // SIMD-ONLY0-NEXT:    [[TMP4614:%.*]] = load float, ptr [[FE]], align 4
52597 // SIMD-ONLY0-NEXT:    store float [[TMP4614]], ptr [[FX]], align 4
52598 // SIMD-ONLY0-NEXT:    br label [[IF_END6038]]
52599 // SIMD-ONLY0:       if.end6038:
52600 // SIMD-ONLY0-NEXT:    [[TMP4615:%.*]] = load float, ptr [[FX]], align 4
52601 // SIMD-ONLY0-NEXT:    store float [[TMP4615]], ptr [[FV]], align 4
52602 // SIMD-ONLY0-NEXT:    [[TMP4616:%.*]] = load float, ptr [[FX]], align 4
52603 // SIMD-ONLY0-NEXT:    [[TMP4617:%.*]] = load float, ptr [[FE]], align 4
52604 // SIMD-ONLY0-NEXT:    [[CMP6039:%.*]] = fcmp ogt float [[TMP4616]], [[TMP4617]]
52605 // SIMD-ONLY0-NEXT:    br i1 [[CMP6039]], label [[IF_THEN6041:%.*]], label [[IF_END6042:%.*]]
52606 // SIMD-ONLY0:       if.then6041:
52607 // SIMD-ONLY0-NEXT:    [[TMP4618:%.*]] = load float, ptr [[FE]], align 4
52608 // SIMD-ONLY0-NEXT:    store float [[TMP4618]], ptr [[FX]], align 4
52609 // SIMD-ONLY0-NEXT:    br label [[IF_END6042]]
52610 // SIMD-ONLY0:       if.end6042:
52611 // SIMD-ONLY0-NEXT:    [[TMP4619:%.*]] = load float, ptr [[FX]], align 4
52612 // SIMD-ONLY0-NEXT:    store float [[TMP4619]], ptr [[FV]], align 4
52613 // SIMD-ONLY0-NEXT:    [[TMP4620:%.*]] = load float, ptr [[FE]], align 4
52614 // SIMD-ONLY0-NEXT:    [[TMP4621:%.*]] = load float, ptr [[FX]], align 4
52615 // SIMD-ONLY0-NEXT:    [[CMP6043:%.*]] = fcmp olt float [[TMP4620]], [[TMP4621]]
52616 // SIMD-ONLY0-NEXT:    br i1 [[CMP6043]], label [[IF_THEN6045:%.*]], label [[IF_END6046:%.*]]
52617 // SIMD-ONLY0:       if.then6045:
52618 // SIMD-ONLY0-NEXT:    [[TMP4622:%.*]] = load float, ptr [[FE]], align 4
52619 // SIMD-ONLY0-NEXT:    store float [[TMP4622]], ptr [[FX]], align 4
52620 // SIMD-ONLY0-NEXT:    br label [[IF_END6046]]
52621 // SIMD-ONLY0:       if.end6046:
52622 // SIMD-ONLY0-NEXT:    [[TMP4623:%.*]] = load float, ptr [[FX]], align 4
52623 // SIMD-ONLY0-NEXT:    store float [[TMP4623]], ptr [[FV]], align 4
52624 // SIMD-ONLY0-NEXT:    [[TMP4624:%.*]] = load float, ptr [[FX]], align 4
52625 // SIMD-ONLY0-NEXT:    [[TMP4625:%.*]] = load float, ptr [[FE]], align 4
52626 // SIMD-ONLY0-NEXT:    [[CMP6047:%.*]] = fcmp olt float [[TMP4624]], [[TMP4625]]
52627 // SIMD-ONLY0-NEXT:    br i1 [[CMP6047]], label [[IF_THEN6049:%.*]], label [[IF_END6050:%.*]]
52628 // SIMD-ONLY0:       if.then6049:
52629 // SIMD-ONLY0-NEXT:    [[TMP4626:%.*]] = load float, ptr [[FE]], align 4
52630 // SIMD-ONLY0-NEXT:    store float [[TMP4626]], ptr [[FX]], align 4
52631 // SIMD-ONLY0-NEXT:    br label [[IF_END6050]]
52632 // SIMD-ONLY0:       if.end6050:
52633 // SIMD-ONLY0-NEXT:    [[TMP4627:%.*]] = load float, ptr [[FX]], align 4
52634 // SIMD-ONLY0-NEXT:    store float [[TMP4627]], ptr [[FV]], align 4
52635 // SIMD-ONLY0-NEXT:    [[TMP4628:%.*]] = load float, ptr [[FX]], align 4
52636 // SIMD-ONLY0-NEXT:    [[TMP4629:%.*]] = load float, ptr [[FE]], align 4
52637 // SIMD-ONLY0-NEXT:    [[CMP6051:%.*]] = fcmp oeq float [[TMP4628]], [[TMP4629]]
52638 // SIMD-ONLY0-NEXT:    br i1 [[CMP6051]], label [[IF_THEN6053:%.*]], label [[IF_END6054:%.*]]
52639 // SIMD-ONLY0:       if.then6053:
52640 // SIMD-ONLY0-NEXT:    [[TMP4630:%.*]] = load float, ptr [[FD]], align 4
52641 // SIMD-ONLY0-NEXT:    store float [[TMP4630]], ptr [[FX]], align 4
52642 // SIMD-ONLY0-NEXT:    br label [[IF_END6054]]
52643 // SIMD-ONLY0:       if.end6054:
52644 // SIMD-ONLY0-NEXT:    [[TMP4631:%.*]] = load float, ptr [[FX]], align 4
52645 // SIMD-ONLY0-NEXT:    store float [[TMP4631]], ptr [[FV]], align 4
52646 // SIMD-ONLY0-NEXT:    [[TMP4632:%.*]] = load float, ptr [[FE]], align 4
52647 // SIMD-ONLY0-NEXT:    [[TMP4633:%.*]] = load float, ptr [[FX]], align 4
52648 // SIMD-ONLY0-NEXT:    [[CMP6055:%.*]] = fcmp oeq float [[TMP4632]], [[TMP4633]]
52649 // SIMD-ONLY0-NEXT:    br i1 [[CMP6055]], label [[IF_THEN6057:%.*]], label [[IF_END6058:%.*]]
52650 // SIMD-ONLY0:       if.then6057:
52651 // SIMD-ONLY0-NEXT:    [[TMP4634:%.*]] = load float, ptr [[FD]], align 4
52652 // SIMD-ONLY0-NEXT:    store float [[TMP4634]], ptr [[FX]], align 4
52653 // SIMD-ONLY0-NEXT:    br label [[IF_END6058]]
52654 // SIMD-ONLY0:       if.end6058:
52655 // SIMD-ONLY0-NEXT:    [[TMP4635:%.*]] = load float, ptr [[FX]], align 4
52656 // SIMD-ONLY0-NEXT:    store float [[TMP4635]], ptr [[FV]], align 4
52657 // SIMD-ONLY0-NEXT:    [[TMP4636:%.*]] = load float, ptr [[FX]], align 4
52658 // SIMD-ONLY0-NEXT:    [[TMP4637:%.*]] = load float, ptr [[FE]], align 4
52659 // SIMD-ONLY0-NEXT:    [[CMP6059:%.*]] = fcmp oeq float [[TMP4636]], [[TMP4637]]
52660 // SIMD-ONLY0-NEXT:    br i1 [[CMP6059]], label [[IF_THEN6061:%.*]], label [[IF_ELSE6062:%.*]]
52661 // SIMD-ONLY0:       if.then6061:
52662 // SIMD-ONLY0-NEXT:    [[TMP4638:%.*]] = load float, ptr [[FD]], align 4
52663 // SIMD-ONLY0-NEXT:    store float [[TMP4638]], ptr [[FX]], align 4
52664 // SIMD-ONLY0-NEXT:    br label [[IF_END6063:%.*]]
52665 // SIMD-ONLY0:       if.else6062:
52666 // SIMD-ONLY0-NEXT:    [[TMP4639:%.*]] = load float, ptr [[FX]], align 4
52667 // SIMD-ONLY0-NEXT:    store float [[TMP4639]], ptr [[FV]], align 4
52668 // SIMD-ONLY0-NEXT:    br label [[IF_END6063]]
52669 // SIMD-ONLY0:       if.end6063:
52670 // SIMD-ONLY0-NEXT:    [[TMP4640:%.*]] = load float, ptr [[FE]], align 4
52671 // SIMD-ONLY0-NEXT:    [[TMP4641:%.*]] = load float, ptr [[FX]], align 4
52672 // SIMD-ONLY0-NEXT:    [[CMP6064:%.*]] = fcmp oeq float [[TMP4640]], [[TMP4641]]
52673 // SIMD-ONLY0-NEXT:    br i1 [[CMP6064]], label [[IF_THEN6066:%.*]], label [[IF_ELSE6067:%.*]]
52674 // SIMD-ONLY0:       if.then6066:
52675 // SIMD-ONLY0-NEXT:    [[TMP4642:%.*]] = load float, ptr [[FD]], align 4
52676 // SIMD-ONLY0-NEXT:    store float [[TMP4642]], ptr [[FX]], align 4
52677 // SIMD-ONLY0-NEXT:    br label [[IF_END6068:%.*]]
52678 // SIMD-ONLY0:       if.else6067:
52679 // SIMD-ONLY0-NEXT:    [[TMP4643:%.*]] = load float, ptr [[FX]], align 4
52680 // SIMD-ONLY0-NEXT:    store float [[TMP4643]], ptr [[FV]], align 4
52681 // SIMD-ONLY0-NEXT:    br label [[IF_END6068]]
52682 // SIMD-ONLY0:       if.end6068:
52683 // SIMD-ONLY0-NEXT:    [[TMP4644:%.*]] = load float, ptr [[FX]], align 4
52684 // SIMD-ONLY0-NEXT:    [[TMP4645:%.*]] = load float, ptr [[FE]], align 4
52685 // SIMD-ONLY0-NEXT:    [[CMP6069:%.*]] = fcmp oeq float [[TMP4644]], [[TMP4645]]
52686 // SIMD-ONLY0-NEXT:    [[CONV6070:%.*]] = zext i1 [[CMP6069]] to i32
52687 // SIMD-ONLY0-NEXT:    store i32 [[CONV6070]], ptr [[IR]], align 4
52688 // SIMD-ONLY0-NEXT:    [[TMP4646:%.*]] = load i32, ptr [[IR]], align 4
52689 // SIMD-ONLY0-NEXT:    [[TOBOOL6071:%.*]] = icmp ne i32 [[TMP4646]], 0
52690 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6071]], label [[IF_THEN6072:%.*]], label [[IF_END6073:%.*]]
52691 // SIMD-ONLY0:       if.then6072:
52692 // SIMD-ONLY0-NEXT:    [[TMP4647:%.*]] = load float, ptr [[FD]], align 4
52693 // SIMD-ONLY0-NEXT:    store float [[TMP4647]], ptr [[FX]], align 4
52694 // SIMD-ONLY0-NEXT:    br label [[IF_END6073]]
52695 // SIMD-ONLY0:       if.end6073:
52696 // SIMD-ONLY0-NEXT:    [[TMP4648:%.*]] = load float, ptr [[FE]], align 4
52697 // SIMD-ONLY0-NEXT:    [[TMP4649:%.*]] = load float, ptr [[FX]], align 4
52698 // SIMD-ONLY0-NEXT:    [[CMP6074:%.*]] = fcmp oeq float [[TMP4648]], [[TMP4649]]
52699 // SIMD-ONLY0-NEXT:    [[CONV6075:%.*]] = zext i1 [[CMP6074]] to i32
52700 // SIMD-ONLY0-NEXT:    store i32 [[CONV6075]], ptr [[IR]], align 4
52701 // SIMD-ONLY0-NEXT:    [[TMP4650:%.*]] = load i32, ptr [[IR]], align 4
52702 // SIMD-ONLY0-NEXT:    [[TOBOOL6076:%.*]] = icmp ne i32 [[TMP4650]], 0
52703 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6076]], label [[IF_THEN6077:%.*]], label [[IF_END6078:%.*]]
52704 // SIMD-ONLY0:       if.then6077:
52705 // SIMD-ONLY0-NEXT:    [[TMP4651:%.*]] = load float, ptr [[FD]], align 4
52706 // SIMD-ONLY0-NEXT:    store float [[TMP4651]], ptr [[FX]], align 4
52707 // SIMD-ONLY0-NEXT:    br label [[IF_END6078]]
52708 // SIMD-ONLY0:       if.end6078:
52709 // SIMD-ONLY0-NEXT:    [[TMP4652:%.*]] = load float, ptr [[FX]], align 4
52710 // SIMD-ONLY0-NEXT:    [[TMP4653:%.*]] = load float, ptr [[FE]], align 4
52711 // SIMD-ONLY0-NEXT:    [[CMP6079:%.*]] = fcmp oeq float [[TMP4652]], [[TMP4653]]
52712 // SIMD-ONLY0-NEXT:    [[CONV6080:%.*]] = zext i1 [[CMP6079]] to i32
52713 // SIMD-ONLY0-NEXT:    store i32 [[CONV6080]], ptr [[IR]], align 4
52714 // SIMD-ONLY0-NEXT:    [[TMP4654:%.*]] = load i32, ptr [[IR]], align 4
52715 // SIMD-ONLY0-NEXT:    [[TOBOOL6081:%.*]] = icmp ne i32 [[TMP4654]], 0
52716 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6081]], label [[IF_THEN6082:%.*]], label [[IF_ELSE6083:%.*]]
52717 // SIMD-ONLY0:       if.then6082:
52718 // SIMD-ONLY0-NEXT:    [[TMP4655:%.*]] = load float, ptr [[FD]], align 4
52719 // SIMD-ONLY0-NEXT:    store float [[TMP4655]], ptr [[FX]], align 4
52720 // SIMD-ONLY0-NEXT:    br label [[IF_END6084:%.*]]
52721 // SIMD-ONLY0:       if.else6083:
52722 // SIMD-ONLY0-NEXT:    [[TMP4656:%.*]] = load float, ptr [[FX]], align 4
52723 // SIMD-ONLY0-NEXT:    store float [[TMP4656]], ptr [[FV]], align 4
52724 // SIMD-ONLY0-NEXT:    br label [[IF_END6084]]
52725 // SIMD-ONLY0:       if.end6084:
52726 // SIMD-ONLY0-NEXT:    [[TMP4657:%.*]] = load float, ptr [[FE]], align 4
52727 // SIMD-ONLY0-NEXT:    [[TMP4658:%.*]] = load float, ptr [[FX]], align 4
52728 // SIMD-ONLY0-NEXT:    [[CMP6085:%.*]] = fcmp oeq float [[TMP4657]], [[TMP4658]]
52729 // SIMD-ONLY0-NEXT:    [[CONV6086:%.*]] = zext i1 [[CMP6085]] to i32
52730 // SIMD-ONLY0-NEXT:    store i32 [[CONV6086]], ptr [[IR]], align 4
52731 // SIMD-ONLY0-NEXT:    [[TMP4659:%.*]] = load i32, ptr [[IR]], align 4
52732 // SIMD-ONLY0-NEXT:    [[TOBOOL6087:%.*]] = icmp ne i32 [[TMP4659]], 0
52733 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6087]], label [[IF_THEN6088:%.*]], label [[IF_ELSE6089:%.*]]
52734 // SIMD-ONLY0:       if.then6088:
52735 // SIMD-ONLY0-NEXT:    [[TMP4660:%.*]] = load float, ptr [[FD]], align 4
52736 // SIMD-ONLY0-NEXT:    store float [[TMP4660]], ptr [[FX]], align 4
52737 // SIMD-ONLY0-NEXT:    br label [[IF_END6090:%.*]]
52738 // SIMD-ONLY0:       if.else6089:
52739 // SIMD-ONLY0-NEXT:    [[TMP4661:%.*]] = load float, ptr [[FX]], align 4
52740 // SIMD-ONLY0-NEXT:    store float [[TMP4661]], ptr [[FV]], align 4
52741 // SIMD-ONLY0-NEXT:    br label [[IF_END6090]]
52742 // SIMD-ONLY0:       if.end6090:
52743 // SIMD-ONLY0-NEXT:    [[TMP4662:%.*]] = load float, ptr [[FX]], align 4
52744 // SIMD-ONLY0-NEXT:    store float [[TMP4662]], ptr [[FV]], align 4
52745 // SIMD-ONLY0-NEXT:    [[TMP4663:%.*]] = load float, ptr [[FE]], align 4
52746 // SIMD-ONLY0-NEXT:    [[TMP4664:%.*]] = load float, ptr [[FX]], align 4
52747 // SIMD-ONLY0-NEXT:    [[CMP6091:%.*]] = fcmp ogt float [[TMP4663]], [[TMP4664]]
52748 // SIMD-ONLY0-NEXT:    br i1 [[CMP6091]], label [[IF_THEN6093:%.*]], label [[IF_END6094:%.*]]
52749 // SIMD-ONLY0:       if.then6093:
52750 // SIMD-ONLY0-NEXT:    [[TMP4665:%.*]] = load float, ptr [[FE]], align 4
52751 // SIMD-ONLY0-NEXT:    store float [[TMP4665]], ptr [[FX]], align 4
52752 // SIMD-ONLY0-NEXT:    br label [[IF_END6094]]
52753 // SIMD-ONLY0:       if.end6094:
52754 // SIMD-ONLY0-NEXT:    [[TMP4666:%.*]] = load float, ptr [[FX]], align 4
52755 // SIMD-ONLY0-NEXT:    store float [[TMP4666]], ptr [[FV]], align 4
52756 // SIMD-ONLY0-NEXT:    [[TMP4667:%.*]] = load float, ptr [[FX]], align 4
52757 // SIMD-ONLY0-NEXT:    [[TMP4668:%.*]] = load float, ptr [[FE]], align 4
52758 // SIMD-ONLY0-NEXT:    [[CMP6095:%.*]] = fcmp ogt float [[TMP4667]], [[TMP4668]]
52759 // SIMD-ONLY0-NEXT:    br i1 [[CMP6095]], label [[IF_THEN6097:%.*]], label [[IF_END6098:%.*]]
52760 // SIMD-ONLY0:       if.then6097:
52761 // SIMD-ONLY0-NEXT:    [[TMP4669:%.*]] = load float, ptr [[FE]], align 4
52762 // SIMD-ONLY0-NEXT:    store float [[TMP4669]], ptr [[FX]], align 4
52763 // SIMD-ONLY0-NEXT:    br label [[IF_END6098]]
52764 // SIMD-ONLY0:       if.end6098:
52765 // SIMD-ONLY0-NEXT:    [[TMP4670:%.*]] = load float, ptr [[FX]], align 4
52766 // SIMD-ONLY0-NEXT:    store float [[TMP4670]], ptr [[FV]], align 4
52767 // SIMD-ONLY0-NEXT:    [[TMP4671:%.*]] = load float, ptr [[FE]], align 4
52768 // SIMD-ONLY0-NEXT:    [[TMP4672:%.*]] = load float, ptr [[FX]], align 4
52769 // SIMD-ONLY0-NEXT:    [[CMP6099:%.*]] = fcmp olt float [[TMP4671]], [[TMP4672]]
52770 // SIMD-ONLY0-NEXT:    br i1 [[CMP6099]], label [[IF_THEN6101:%.*]], label [[IF_END6102:%.*]]
52771 // SIMD-ONLY0:       if.then6101:
52772 // SIMD-ONLY0-NEXT:    [[TMP4673:%.*]] = load float, ptr [[FE]], align 4
52773 // SIMD-ONLY0-NEXT:    store float [[TMP4673]], ptr [[FX]], align 4
52774 // SIMD-ONLY0-NEXT:    br label [[IF_END6102]]
52775 // SIMD-ONLY0:       if.end6102:
52776 // SIMD-ONLY0-NEXT:    [[TMP4674:%.*]] = load float, ptr [[FX]], align 4
52777 // SIMD-ONLY0-NEXT:    store float [[TMP4674]], ptr [[FV]], align 4
52778 // SIMD-ONLY0-NEXT:    [[TMP4675:%.*]] = load float, ptr [[FX]], align 4
52779 // SIMD-ONLY0-NEXT:    [[TMP4676:%.*]] = load float, ptr [[FE]], align 4
52780 // SIMD-ONLY0-NEXT:    [[CMP6103:%.*]] = fcmp olt float [[TMP4675]], [[TMP4676]]
52781 // SIMD-ONLY0-NEXT:    br i1 [[CMP6103]], label [[IF_THEN6105:%.*]], label [[IF_END6106:%.*]]
52782 // SIMD-ONLY0:       if.then6105:
52783 // SIMD-ONLY0-NEXT:    [[TMP4677:%.*]] = load float, ptr [[FE]], align 4
52784 // SIMD-ONLY0-NEXT:    store float [[TMP4677]], ptr [[FX]], align 4
52785 // SIMD-ONLY0-NEXT:    br label [[IF_END6106]]
52786 // SIMD-ONLY0:       if.end6106:
52787 // SIMD-ONLY0-NEXT:    [[TMP4678:%.*]] = load float, ptr [[FX]], align 4
52788 // SIMD-ONLY0-NEXT:    store float [[TMP4678]], ptr [[FV]], align 4
52789 // SIMD-ONLY0-NEXT:    [[TMP4679:%.*]] = load float, ptr [[FX]], align 4
52790 // SIMD-ONLY0-NEXT:    [[TMP4680:%.*]] = load float, ptr [[FE]], align 4
52791 // SIMD-ONLY0-NEXT:    [[CMP6107:%.*]] = fcmp oeq float [[TMP4679]], [[TMP4680]]
52792 // SIMD-ONLY0-NEXT:    br i1 [[CMP6107]], label [[IF_THEN6109:%.*]], label [[IF_END6110:%.*]]
52793 // SIMD-ONLY0:       if.then6109:
52794 // SIMD-ONLY0-NEXT:    [[TMP4681:%.*]] = load float, ptr [[FD]], align 4
52795 // SIMD-ONLY0-NEXT:    store float [[TMP4681]], ptr [[FX]], align 4
52796 // SIMD-ONLY0-NEXT:    br label [[IF_END6110]]
52797 // SIMD-ONLY0:       if.end6110:
52798 // SIMD-ONLY0-NEXT:    [[TMP4682:%.*]] = load float, ptr [[FX]], align 4
52799 // SIMD-ONLY0-NEXT:    store float [[TMP4682]], ptr [[FV]], align 4
52800 // SIMD-ONLY0-NEXT:    [[TMP4683:%.*]] = load float, ptr [[FE]], align 4
52801 // SIMD-ONLY0-NEXT:    [[TMP4684:%.*]] = load float, ptr [[FX]], align 4
52802 // SIMD-ONLY0-NEXT:    [[CMP6111:%.*]] = fcmp oeq float [[TMP4683]], [[TMP4684]]
52803 // SIMD-ONLY0-NEXT:    br i1 [[CMP6111]], label [[IF_THEN6113:%.*]], label [[IF_END6114:%.*]]
52804 // SIMD-ONLY0:       if.then6113:
52805 // SIMD-ONLY0-NEXT:    [[TMP4685:%.*]] = load float, ptr [[FD]], align 4
52806 // SIMD-ONLY0-NEXT:    store float [[TMP4685]], ptr [[FX]], align 4
52807 // SIMD-ONLY0-NEXT:    br label [[IF_END6114]]
52808 // SIMD-ONLY0:       if.end6114:
52809 // SIMD-ONLY0-NEXT:    [[TMP4686:%.*]] = load float, ptr [[FE]], align 4
52810 // SIMD-ONLY0-NEXT:    [[TMP4687:%.*]] = load float, ptr [[FX]], align 4
52811 // SIMD-ONLY0-NEXT:    [[CMP6115:%.*]] = fcmp ogt float [[TMP4686]], [[TMP4687]]
52812 // SIMD-ONLY0-NEXT:    br i1 [[CMP6115]], label [[IF_THEN6117:%.*]], label [[IF_END6118:%.*]]
52813 // SIMD-ONLY0:       if.then6117:
52814 // SIMD-ONLY0-NEXT:    [[TMP4688:%.*]] = load float, ptr [[FE]], align 4
52815 // SIMD-ONLY0-NEXT:    store float [[TMP4688]], ptr [[FX]], align 4
52816 // SIMD-ONLY0-NEXT:    br label [[IF_END6118]]
52817 // SIMD-ONLY0:       if.end6118:
52818 // SIMD-ONLY0-NEXT:    [[TMP4689:%.*]] = load float, ptr [[FX]], align 4
52819 // SIMD-ONLY0-NEXT:    store float [[TMP4689]], ptr [[FV]], align 4
52820 // SIMD-ONLY0-NEXT:    [[TMP4690:%.*]] = load float, ptr [[FX]], align 4
52821 // SIMD-ONLY0-NEXT:    [[TMP4691:%.*]] = load float, ptr [[FE]], align 4
52822 // SIMD-ONLY0-NEXT:    [[CMP6119:%.*]] = fcmp ogt float [[TMP4690]], [[TMP4691]]
52823 // SIMD-ONLY0-NEXT:    br i1 [[CMP6119]], label [[IF_THEN6121:%.*]], label [[IF_END6122:%.*]]
52824 // SIMD-ONLY0:       if.then6121:
52825 // SIMD-ONLY0-NEXT:    [[TMP4692:%.*]] = load float, ptr [[FE]], align 4
52826 // SIMD-ONLY0-NEXT:    store float [[TMP4692]], ptr [[FX]], align 4
52827 // SIMD-ONLY0-NEXT:    br label [[IF_END6122]]
52828 // SIMD-ONLY0:       if.end6122:
52829 // SIMD-ONLY0-NEXT:    [[TMP4693:%.*]] = load float, ptr [[FX]], align 4
52830 // SIMD-ONLY0-NEXT:    store float [[TMP4693]], ptr [[FV]], align 4
52831 // SIMD-ONLY0-NEXT:    [[TMP4694:%.*]] = load float, ptr [[FE]], align 4
52832 // SIMD-ONLY0-NEXT:    [[TMP4695:%.*]] = load float, ptr [[FX]], align 4
52833 // SIMD-ONLY0-NEXT:    [[CMP6123:%.*]] = fcmp olt float [[TMP4694]], [[TMP4695]]
52834 // SIMD-ONLY0-NEXT:    br i1 [[CMP6123]], label [[IF_THEN6125:%.*]], label [[IF_END6126:%.*]]
52835 // SIMD-ONLY0:       if.then6125:
52836 // SIMD-ONLY0-NEXT:    [[TMP4696:%.*]] = load float, ptr [[FE]], align 4
52837 // SIMD-ONLY0-NEXT:    store float [[TMP4696]], ptr [[FX]], align 4
52838 // SIMD-ONLY0-NEXT:    br label [[IF_END6126]]
52839 // SIMD-ONLY0:       if.end6126:
52840 // SIMD-ONLY0-NEXT:    [[TMP4697:%.*]] = load float, ptr [[FX]], align 4
52841 // SIMD-ONLY0-NEXT:    store float [[TMP4697]], ptr [[FV]], align 4
52842 // SIMD-ONLY0-NEXT:    [[TMP4698:%.*]] = load float, ptr [[FX]], align 4
52843 // SIMD-ONLY0-NEXT:    [[TMP4699:%.*]] = load float, ptr [[FE]], align 4
52844 // SIMD-ONLY0-NEXT:    [[CMP6127:%.*]] = fcmp olt float [[TMP4698]], [[TMP4699]]
52845 // SIMD-ONLY0-NEXT:    br i1 [[CMP6127]], label [[IF_THEN6129:%.*]], label [[IF_END6130:%.*]]
52846 // SIMD-ONLY0:       if.then6129:
52847 // SIMD-ONLY0-NEXT:    [[TMP4700:%.*]] = load float, ptr [[FE]], align 4
52848 // SIMD-ONLY0-NEXT:    store float [[TMP4700]], ptr [[FX]], align 4
52849 // SIMD-ONLY0-NEXT:    br label [[IF_END6130]]
52850 // SIMD-ONLY0:       if.end6130:
52851 // SIMD-ONLY0-NEXT:    [[TMP4701:%.*]] = load float, ptr [[FX]], align 4
52852 // SIMD-ONLY0-NEXT:    store float [[TMP4701]], ptr [[FV]], align 4
52853 // SIMD-ONLY0-NEXT:    [[TMP4702:%.*]] = load float, ptr [[FX]], align 4
52854 // SIMD-ONLY0-NEXT:    [[TMP4703:%.*]] = load float, ptr [[FE]], align 4
52855 // SIMD-ONLY0-NEXT:    [[CMP6131:%.*]] = fcmp oeq float [[TMP4702]], [[TMP4703]]
52856 // SIMD-ONLY0-NEXT:    br i1 [[CMP6131]], label [[IF_THEN6133:%.*]], label [[IF_END6134:%.*]]
52857 // SIMD-ONLY0:       if.then6133:
52858 // SIMD-ONLY0-NEXT:    [[TMP4704:%.*]] = load float, ptr [[FD]], align 4
52859 // SIMD-ONLY0-NEXT:    store float [[TMP4704]], ptr [[FX]], align 4
52860 // SIMD-ONLY0-NEXT:    br label [[IF_END6134]]
52861 // SIMD-ONLY0:       if.end6134:
52862 // SIMD-ONLY0-NEXT:    [[TMP4705:%.*]] = load float, ptr [[FX]], align 4
52863 // SIMD-ONLY0-NEXT:    store float [[TMP4705]], ptr [[FV]], align 4
52864 // SIMD-ONLY0-NEXT:    [[TMP4706:%.*]] = load float, ptr [[FE]], align 4
52865 // SIMD-ONLY0-NEXT:    [[TMP4707:%.*]] = load float, ptr [[FX]], align 4
52866 // SIMD-ONLY0-NEXT:    [[CMP6135:%.*]] = fcmp oeq float [[TMP4706]], [[TMP4707]]
52867 // SIMD-ONLY0-NEXT:    br i1 [[CMP6135]], label [[IF_THEN6137:%.*]], label [[IF_END6138:%.*]]
52868 // SIMD-ONLY0:       if.then6137:
52869 // SIMD-ONLY0-NEXT:    [[TMP4708:%.*]] = load float, ptr [[FD]], align 4
52870 // SIMD-ONLY0-NEXT:    store float [[TMP4708]], ptr [[FX]], align 4
52871 // SIMD-ONLY0-NEXT:    br label [[IF_END6138]]
52872 // SIMD-ONLY0:       if.end6138:
52873 // SIMD-ONLY0-NEXT:    [[TMP4709:%.*]] = load float, ptr [[FX]], align 4
52874 // SIMD-ONLY0-NEXT:    store float [[TMP4709]], ptr [[FV]], align 4
52875 // SIMD-ONLY0-NEXT:    [[TMP4710:%.*]] = load float, ptr [[FX]], align 4
52876 // SIMD-ONLY0-NEXT:    [[TMP4711:%.*]] = load float, ptr [[FE]], align 4
52877 // SIMD-ONLY0-NEXT:    [[CMP6139:%.*]] = fcmp oeq float [[TMP4710]], [[TMP4711]]
52878 // SIMD-ONLY0-NEXT:    br i1 [[CMP6139]], label [[IF_THEN6141:%.*]], label [[IF_ELSE6142:%.*]]
52879 // SIMD-ONLY0:       if.then6141:
52880 // SIMD-ONLY0-NEXT:    [[TMP4712:%.*]] = load float, ptr [[FD]], align 4
52881 // SIMD-ONLY0-NEXT:    store float [[TMP4712]], ptr [[FX]], align 4
52882 // SIMD-ONLY0-NEXT:    br label [[IF_END6143:%.*]]
52883 // SIMD-ONLY0:       if.else6142:
52884 // SIMD-ONLY0-NEXT:    [[TMP4713:%.*]] = load float, ptr [[FX]], align 4
52885 // SIMD-ONLY0-NEXT:    store float [[TMP4713]], ptr [[FV]], align 4
52886 // SIMD-ONLY0-NEXT:    br label [[IF_END6143]]
52887 // SIMD-ONLY0:       if.end6143:
52888 // SIMD-ONLY0-NEXT:    [[TMP4714:%.*]] = load float, ptr [[FE]], align 4
52889 // SIMD-ONLY0-NEXT:    [[TMP4715:%.*]] = load float, ptr [[FX]], align 4
52890 // SIMD-ONLY0-NEXT:    [[CMP6144:%.*]] = fcmp oeq float [[TMP4714]], [[TMP4715]]
52891 // SIMD-ONLY0-NEXT:    br i1 [[CMP6144]], label [[IF_THEN6146:%.*]], label [[IF_ELSE6147:%.*]]
52892 // SIMD-ONLY0:       if.then6146:
52893 // SIMD-ONLY0-NEXT:    [[TMP4716:%.*]] = load float, ptr [[FD]], align 4
52894 // SIMD-ONLY0-NEXT:    store float [[TMP4716]], ptr [[FX]], align 4
52895 // SIMD-ONLY0-NEXT:    br label [[IF_END6148:%.*]]
52896 // SIMD-ONLY0:       if.else6147:
52897 // SIMD-ONLY0-NEXT:    [[TMP4717:%.*]] = load float, ptr [[FX]], align 4
52898 // SIMD-ONLY0-NEXT:    store float [[TMP4717]], ptr [[FV]], align 4
52899 // SIMD-ONLY0-NEXT:    br label [[IF_END6148]]
52900 // SIMD-ONLY0:       if.end6148:
52901 // SIMD-ONLY0-NEXT:    [[TMP4718:%.*]] = load float, ptr [[FX]], align 4
52902 // SIMD-ONLY0-NEXT:    [[TMP4719:%.*]] = load float, ptr [[FE]], align 4
52903 // SIMD-ONLY0-NEXT:    [[CMP6149:%.*]] = fcmp oeq float [[TMP4718]], [[TMP4719]]
52904 // SIMD-ONLY0-NEXT:    [[CONV6150:%.*]] = zext i1 [[CMP6149]] to i32
52905 // SIMD-ONLY0-NEXT:    store i32 [[CONV6150]], ptr [[IR]], align 4
52906 // SIMD-ONLY0-NEXT:    [[TMP4720:%.*]] = load i32, ptr [[IR]], align 4
52907 // SIMD-ONLY0-NEXT:    [[TOBOOL6151:%.*]] = icmp ne i32 [[TMP4720]], 0
52908 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6151]], label [[IF_THEN6152:%.*]], label [[IF_END6153:%.*]]
52909 // SIMD-ONLY0:       if.then6152:
52910 // SIMD-ONLY0-NEXT:    [[TMP4721:%.*]] = load float, ptr [[FD]], align 4
52911 // SIMD-ONLY0-NEXT:    store float [[TMP4721]], ptr [[FX]], align 4
52912 // SIMD-ONLY0-NEXT:    br label [[IF_END6153]]
52913 // SIMD-ONLY0:       if.end6153:
52914 // SIMD-ONLY0-NEXT:    [[TMP4722:%.*]] = load float, ptr [[FE]], align 4
52915 // SIMD-ONLY0-NEXT:    [[TMP4723:%.*]] = load float, ptr [[FX]], align 4
52916 // SIMD-ONLY0-NEXT:    [[CMP6154:%.*]] = fcmp oeq float [[TMP4722]], [[TMP4723]]
52917 // SIMD-ONLY0-NEXT:    [[CONV6155:%.*]] = zext i1 [[CMP6154]] to i32
52918 // SIMD-ONLY0-NEXT:    store i32 [[CONV6155]], ptr [[IR]], align 4
52919 // SIMD-ONLY0-NEXT:    [[TMP4724:%.*]] = load i32, ptr [[IR]], align 4
52920 // SIMD-ONLY0-NEXT:    [[TOBOOL6156:%.*]] = icmp ne i32 [[TMP4724]], 0
52921 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6156]], label [[IF_THEN6157:%.*]], label [[IF_END6158:%.*]]
52922 // SIMD-ONLY0:       if.then6157:
52923 // SIMD-ONLY0-NEXT:    [[TMP4725:%.*]] = load float, ptr [[FD]], align 4
52924 // SIMD-ONLY0-NEXT:    store float [[TMP4725]], ptr [[FX]], align 4
52925 // SIMD-ONLY0-NEXT:    br label [[IF_END6158]]
52926 // SIMD-ONLY0:       if.end6158:
52927 // SIMD-ONLY0-NEXT:    [[TMP4726:%.*]] = load float, ptr [[FX]], align 4
52928 // SIMD-ONLY0-NEXT:    [[TMP4727:%.*]] = load float, ptr [[FE]], align 4
52929 // SIMD-ONLY0-NEXT:    [[CMP6159:%.*]] = fcmp oeq float [[TMP4726]], [[TMP4727]]
52930 // SIMD-ONLY0-NEXT:    [[CONV6160:%.*]] = zext i1 [[CMP6159]] to i32
52931 // SIMD-ONLY0-NEXT:    store i32 [[CONV6160]], ptr [[IR]], align 4
52932 // SIMD-ONLY0-NEXT:    [[TMP4728:%.*]] = load i32, ptr [[IR]], align 4
52933 // SIMD-ONLY0-NEXT:    [[TOBOOL6161:%.*]] = icmp ne i32 [[TMP4728]], 0
52934 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6161]], label [[IF_THEN6162:%.*]], label [[IF_ELSE6163:%.*]]
52935 // SIMD-ONLY0:       if.then6162:
52936 // SIMD-ONLY0-NEXT:    [[TMP4729:%.*]] = load float, ptr [[FD]], align 4
52937 // SIMD-ONLY0-NEXT:    store float [[TMP4729]], ptr [[FX]], align 4
52938 // SIMD-ONLY0-NEXT:    br label [[IF_END6164:%.*]]
52939 // SIMD-ONLY0:       if.else6163:
52940 // SIMD-ONLY0-NEXT:    [[TMP4730:%.*]] = load float, ptr [[FX]], align 4
52941 // SIMD-ONLY0-NEXT:    store float [[TMP4730]], ptr [[FV]], align 4
52942 // SIMD-ONLY0-NEXT:    br label [[IF_END6164]]
52943 // SIMD-ONLY0:       if.end6164:
52944 // SIMD-ONLY0-NEXT:    [[TMP4731:%.*]] = load float, ptr [[FE]], align 4
52945 // SIMD-ONLY0-NEXT:    [[TMP4732:%.*]] = load float, ptr [[FX]], align 4
52946 // SIMD-ONLY0-NEXT:    [[CMP6165:%.*]] = fcmp oeq float [[TMP4731]], [[TMP4732]]
52947 // SIMD-ONLY0-NEXT:    [[CONV6166:%.*]] = zext i1 [[CMP6165]] to i32
52948 // SIMD-ONLY0-NEXT:    store i32 [[CONV6166]], ptr [[IR]], align 4
52949 // SIMD-ONLY0-NEXT:    [[TMP4733:%.*]] = load i32, ptr [[IR]], align 4
52950 // SIMD-ONLY0-NEXT:    [[TOBOOL6167:%.*]] = icmp ne i32 [[TMP4733]], 0
52951 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6167]], label [[IF_THEN6168:%.*]], label [[IF_ELSE6169:%.*]]
52952 // SIMD-ONLY0:       if.then6168:
52953 // SIMD-ONLY0-NEXT:    [[TMP4734:%.*]] = load float, ptr [[FD]], align 4
52954 // SIMD-ONLY0-NEXT:    store float [[TMP4734]], ptr [[FX]], align 4
52955 // SIMD-ONLY0-NEXT:    br label [[IF_END6170:%.*]]
52956 // SIMD-ONLY0:       if.else6169:
52957 // SIMD-ONLY0-NEXT:    [[TMP4735:%.*]] = load float, ptr [[FX]], align 4
52958 // SIMD-ONLY0-NEXT:    store float [[TMP4735]], ptr [[FV]], align 4
52959 // SIMD-ONLY0-NEXT:    br label [[IF_END6170]]
52960 // SIMD-ONLY0:       if.end6170:
52961 // SIMD-ONLY0-NEXT:    [[TMP4736:%.*]] = load float, ptr [[FX]], align 4
52962 // SIMD-ONLY0-NEXT:    store float [[TMP4736]], ptr [[FV]], align 4
52963 // SIMD-ONLY0-NEXT:    [[TMP4737:%.*]] = load float, ptr [[FE]], align 4
52964 // SIMD-ONLY0-NEXT:    [[TMP4738:%.*]] = load float, ptr [[FX]], align 4
52965 // SIMD-ONLY0-NEXT:    [[CMP6171:%.*]] = fcmp ogt float [[TMP4737]], [[TMP4738]]
52966 // SIMD-ONLY0-NEXT:    br i1 [[CMP6171]], label [[IF_THEN6173:%.*]], label [[IF_END6174:%.*]]
52967 // SIMD-ONLY0:       if.then6173:
52968 // SIMD-ONLY0-NEXT:    [[TMP4739:%.*]] = load float, ptr [[FE]], align 4
52969 // SIMD-ONLY0-NEXT:    store float [[TMP4739]], ptr [[FX]], align 4
52970 // SIMD-ONLY0-NEXT:    br label [[IF_END6174]]
52971 // SIMD-ONLY0:       if.end6174:
52972 // SIMD-ONLY0-NEXT:    [[TMP4740:%.*]] = load float, ptr [[FX]], align 4
52973 // SIMD-ONLY0-NEXT:    store float [[TMP4740]], ptr [[FV]], align 4
52974 // SIMD-ONLY0-NEXT:    [[TMP4741:%.*]] = load float, ptr [[FX]], align 4
52975 // SIMD-ONLY0-NEXT:    [[TMP4742:%.*]] = load float, ptr [[FE]], align 4
52976 // SIMD-ONLY0-NEXT:    [[CMP6175:%.*]] = fcmp ogt float [[TMP4741]], [[TMP4742]]
52977 // SIMD-ONLY0-NEXT:    br i1 [[CMP6175]], label [[IF_THEN6177:%.*]], label [[IF_END6178:%.*]]
52978 // SIMD-ONLY0:       if.then6177:
52979 // SIMD-ONLY0-NEXT:    [[TMP4743:%.*]] = load float, ptr [[FE]], align 4
52980 // SIMD-ONLY0-NEXT:    store float [[TMP4743]], ptr [[FX]], align 4
52981 // SIMD-ONLY0-NEXT:    br label [[IF_END6178]]
52982 // SIMD-ONLY0:       if.end6178:
52983 // SIMD-ONLY0-NEXT:    [[TMP4744:%.*]] = load float, ptr [[FX]], align 4
52984 // SIMD-ONLY0-NEXT:    store float [[TMP4744]], ptr [[FV]], align 4
52985 // SIMD-ONLY0-NEXT:    [[TMP4745:%.*]] = load float, ptr [[FE]], align 4
52986 // SIMD-ONLY0-NEXT:    [[TMP4746:%.*]] = load float, ptr [[FX]], align 4
52987 // SIMD-ONLY0-NEXT:    [[CMP6179:%.*]] = fcmp olt float [[TMP4745]], [[TMP4746]]
52988 // SIMD-ONLY0-NEXT:    br i1 [[CMP6179]], label [[IF_THEN6181:%.*]], label [[IF_END6182:%.*]]
52989 // SIMD-ONLY0:       if.then6181:
52990 // SIMD-ONLY0-NEXT:    [[TMP4747:%.*]] = load float, ptr [[FE]], align 4
52991 // SIMD-ONLY0-NEXT:    store float [[TMP4747]], ptr [[FX]], align 4
52992 // SIMD-ONLY0-NEXT:    br label [[IF_END6182]]
52993 // SIMD-ONLY0:       if.end6182:
52994 // SIMD-ONLY0-NEXT:    [[TMP4748:%.*]] = load float, ptr [[FX]], align 4
52995 // SIMD-ONLY0-NEXT:    store float [[TMP4748]], ptr [[FV]], align 4
52996 // SIMD-ONLY0-NEXT:    [[TMP4749:%.*]] = load float, ptr [[FX]], align 4
52997 // SIMD-ONLY0-NEXT:    [[TMP4750:%.*]] = load float, ptr [[FE]], align 4
52998 // SIMD-ONLY0-NEXT:    [[CMP6183:%.*]] = fcmp olt float [[TMP4749]], [[TMP4750]]
52999 // SIMD-ONLY0-NEXT:    br i1 [[CMP6183]], label [[IF_THEN6185:%.*]], label [[IF_END6186:%.*]]
53000 // SIMD-ONLY0:       if.then6185:
53001 // SIMD-ONLY0-NEXT:    [[TMP4751:%.*]] = load float, ptr [[FE]], align 4
53002 // SIMD-ONLY0-NEXT:    store float [[TMP4751]], ptr [[FX]], align 4
53003 // SIMD-ONLY0-NEXT:    br label [[IF_END6186]]
53004 // SIMD-ONLY0:       if.end6186:
53005 // SIMD-ONLY0-NEXT:    [[TMP4752:%.*]] = load float, ptr [[FX]], align 4
53006 // SIMD-ONLY0-NEXT:    store float [[TMP4752]], ptr [[FV]], align 4
53007 // SIMD-ONLY0-NEXT:    [[TMP4753:%.*]] = load float, ptr [[FX]], align 4
53008 // SIMD-ONLY0-NEXT:    [[TMP4754:%.*]] = load float, ptr [[FE]], align 4
53009 // SIMD-ONLY0-NEXT:    [[CMP6187:%.*]] = fcmp oeq float [[TMP4753]], [[TMP4754]]
53010 // SIMD-ONLY0-NEXT:    br i1 [[CMP6187]], label [[IF_THEN6189:%.*]], label [[IF_END6190:%.*]]
53011 // SIMD-ONLY0:       if.then6189:
53012 // SIMD-ONLY0-NEXT:    [[TMP4755:%.*]] = load float, ptr [[FD]], align 4
53013 // SIMD-ONLY0-NEXT:    store float [[TMP4755]], ptr [[FX]], align 4
53014 // SIMD-ONLY0-NEXT:    br label [[IF_END6190]]
53015 // SIMD-ONLY0:       if.end6190:
53016 // SIMD-ONLY0-NEXT:    [[TMP4756:%.*]] = load float, ptr [[FX]], align 4
53017 // SIMD-ONLY0-NEXT:    store float [[TMP4756]], ptr [[FV]], align 4
53018 // SIMD-ONLY0-NEXT:    [[TMP4757:%.*]] = load float, ptr [[FE]], align 4
53019 // SIMD-ONLY0-NEXT:    [[TMP4758:%.*]] = load float, ptr [[FX]], align 4
53020 // SIMD-ONLY0-NEXT:    [[CMP6191:%.*]] = fcmp oeq float [[TMP4757]], [[TMP4758]]
53021 // SIMD-ONLY0-NEXT:    br i1 [[CMP6191]], label [[IF_THEN6193:%.*]], label [[IF_END6194:%.*]]
53022 // SIMD-ONLY0:       if.then6193:
53023 // SIMD-ONLY0-NEXT:    [[TMP4759:%.*]] = load float, ptr [[FD]], align 4
53024 // SIMD-ONLY0-NEXT:    store float [[TMP4759]], ptr [[FX]], align 4
53025 // SIMD-ONLY0-NEXT:    br label [[IF_END6194]]
53026 // SIMD-ONLY0:       if.end6194:
53027 // SIMD-ONLY0-NEXT:    [[TMP4760:%.*]] = load float, ptr [[FE]], align 4
53028 // SIMD-ONLY0-NEXT:    [[TMP4761:%.*]] = load float, ptr [[FX]], align 4
53029 // SIMD-ONLY0-NEXT:    [[CMP6195:%.*]] = fcmp ogt float [[TMP4760]], [[TMP4761]]
53030 // SIMD-ONLY0-NEXT:    br i1 [[CMP6195]], label [[IF_THEN6197:%.*]], label [[IF_END6198:%.*]]
53031 // SIMD-ONLY0:       if.then6197:
53032 // SIMD-ONLY0-NEXT:    [[TMP4762:%.*]] = load float, ptr [[FE]], align 4
53033 // SIMD-ONLY0-NEXT:    store float [[TMP4762]], ptr [[FX]], align 4
53034 // SIMD-ONLY0-NEXT:    br label [[IF_END6198]]
53035 // SIMD-ONLY0:       if.end6198:
53036 // SIMD-ONLY0-NEXT:    [[TMP4763:%.*]] = load float, ptr [[FX]], align 4
53037 // SIMD-ONLY0-NEXT:    store float [[TMP4763]], ptr [[FV]], align 4
53038 // SIMD-ONLY0-NEXT:    [[TMP4764:%.*]] = load float, ptr [[FX]], align 4
53039 // SIMD-ONLY0-NEXT:    [[TMP4765:%.*]] = load float, ptr [[FE]], align 4
53040 // SIMD-ONLY0-NEXT:    [[CMP6199:%.*]] = fcmp ogt float [[TMP4764]], [[TMP4765]]
53041 // SIMD-ONLY0-NEXT:    br i1 [[CMP6199]], label [[IF_THEN6201:%.*]], label [[IF_END6202:%.*]]
53042 // SIMD-ONLY0:       if.then6201:
53043 // SIMD-ONLY0-NEXT:    [[TMP4766:%.*]] = load float, ptr [[FE]], align 4
53044 // SIMD-ONLY0-NEXT:    store float [[TMP4766]], ptr [[FX]], align 4
53045 // SIMD-ONLY0-NEXT:    br label [[IF_END6202]]
53046 // SIMD-ONLY0:       if.end6202:
53047 // SIMD-ONLY0-NEXT:    [[TMP4767:%.*]] = load float, ptr [[FX]], align 4
53048 // SIMD-ONLY0-NEXT:    store float [[TMP4767]], ptr [[FV]], align 4
53049 // SIMD-ONLY0-NEXT:    [[TMP4768:%.*]] = load float, ptr [[FE]], align 4
53050 // SIMD-ONLY0-NEXT:    [[TMP4769:%.*]] = load float, ptr [[FX]], align 4
53051 // SIMD-ONLY0-NEXT:    [[CMP6203:%.*]] = fcmp olt float [[TMP4768]], [[TMP4769]]
53052 // SIMD-ONLY0-NEXT:    br i1 [[CMP6203]], label [[IF_THEN6205:%.*]], label [[IF_END6206:%.*]]
53053 // SIMD-ONLY0:       if.then6205:
53054 // SIMD-ONLY0-NEXT:    [[TMP4770:%.*]] = load float, ptr [[FE]], align 4
53055 // SIMD-ONLY0-NEXT:    store float [[TMP4770]], ptr [[FX]], align 4
53056 // SIMD-ONLY0-NEXT:    br label [[IF_END6206]]
53057 // SIMD-ONLY0:       if.end6206:
53058 // SIMD-ONLY0-NEXT:    [[TMP4771:%.*]] = load float, ptr [[FX]], align 4
53059 // SIMD-ONLY0-NEXT:    store float [[TMP4771]], ptr [[FV]], align 4
53060 // SIMD-ONLY0-NEXT:    [[TMP4772:%.*]] = load float, ptr [[FX]], align 4
53061 // SIMD-ONLY0-NEXT:    [[TMP4773:%.*]] = load float, ptr [[FE]], align 4
53062 // SIMD-ONLY0-NEXT:    [[CMP6207:%.*]] = fcmp olt float [[TMP4772]], [[TMP4773]]
53063 // SIMD-ONLY0-NEXT:    br i1 [[CMP6207]], label [[IF_THEN6209:%.*]], label [[IF_END6210:%.*]]
53064 // SIMD-ONLY0:       if.then6209:
53065 // SIMD-ONLY0-NEXT:    [[TMP4774:%.*]] = load float, ptr [[FE]], align 4
53066 // SIMD-ONLY0-NEXT:    store float [[TMP4774]], ptr [[FX]], align 4
53067 // SIMD-ONLY0-NEXT:    br label [[IF_END6210]]
53068 // SIMD-ONLY0:       if.end6210:
53069 // SIMD-ONLY0-NEXT:    [[TMP4775:%.*]] = load float, ptr [[FX]], align 4
53070 // SIMD-ONLY0-NEXT:    store float [[TMP4775]], ptr [[FV]], align 4
53071 // SIMD-ONLY0-NEXT:    [[TMP4776:%.*]] = load float, ptr [[FX]], align 4
53072 // SIMD-ONLY0-NEXT:    [[TMP4777:%.*]] = load float, ptr [[FE]], align 4
53073 // SIMD-ONLY0-NEXT:    [[CMP6211:%.*]] = fcmp oeq float [[TMP4776]], [[TMP4777]]
53074 // SIMD-ONLY0-NEXT:    br i1 [[CMP6211]], label [[IF_THEN6213:%.*]], label [[IF_END6214:%.*]]
53075 // SIMD-ONLY0:       if.then6213:
53076 // SIMD-ONLY0-NEXT:    [[TMP4778:%.*]] = load float, ptr [[FD]], align 4
53077 // SIMD-ONLY0-NEXT:    store float [[TMP4778]], ptr [[FX]], align 4
53078 // SIMD-ONLY0-NEXT:    br label [[IF_END6214]]
53079 // SIMD-ONLY0:       if.end6214:
53080 // SIMD-ONLY0-NEXT:    [[TMP4779:%.*]] = load float, ptr [[FX]], align 4
53081 // SIMD-ONLY0-NEXT:    store float [[TMP4779]], ptr [[FV]], align 4
53082 // SIMD-ONLY0-NEXT:    [[TMP4780:%.*]] = load float, ptr [[FE]], align 4
53083 // SIMD-ONLY0-NEXT:    [[TMP4781:%.*]] = load float, ptr [[FX]], align 4
53084 // SIMD-ONLY0-NEXT:    [[CMP6215:%.*]] = fcmp oeq float [[TMP4780]], [[TMP4781]]
53085 // SIMD-ONLY0-NEXT:    br i1 [[CMP6215]], label [[IF_THEN6217:%.*]], label [[IF_END6218:%.*]]
53086 // SIMD-ONLY0:       if.then6217:
53087 // SIMD-ONLY0-NEXT:    [[TMP4782:%.*]] = load float, ptr [[FD]], align 4
53088 // SIMD-ONLY0-NEXT:    store float [[TMP4782]], ptr [[FX]], align 4
53089 // SIMD-ONLY0-NEXT:    br label [[IF_END6218]]
53090 // SIMD-ONLY0:       if.end6218:
53091 // SIMD-ONLY0-NEXT:    [[TMP4783:%.*]] = load float, ptr [[FX]], align 4
53092 // SIMD-ONLY0-NEXT:    store float [[TMP4783]], ptr [[FV]], align 4
53093 // SIMD-ONLY0-NEXT:    [[TMP4784:%.*]] = load float, ptr [[FX]], align 4
53094 // SIMD-ONLY0-NEXT:    [[TMP4785:%.*]] = load float, ptr [[FE]], align 4
53095 // SIMD-ONLY0-NEXT:    [[CMP6219:%.*]] = fcmp oeq float [[TMP4784]], [[TMP4785]]
53096 // SIMD-ONLY0-NEXT:    br i1 [[CMP6219]], label [[IF_THEN6221:%.*]], label [[IF_ELSE6222:%.*]]
53097 // SIMD-ONLY0:       if.then6221:
53098 // SIMD-ONLY0-NEXT:    [[TMP4786:%.*]] = load float, ptr [[FD]], align 4
53099 // SIMD-ONLY0-NEXT:    store float [[TMP4786]], ptr [[FX]], align 4
53100 // SIMD-ONLY0-NEXT:    br label [[IF_END6223:%.*]]
53101 // SIMD-ONLY0:       if.else6222:
53102 // SIMD-ONLY0-NEXT:    [[TMP4787:%.*]] = load float, ptr [[FX]], align 4
53103 // SIMD-ONLY0-NEXT:    store float [[TMP4787]], ptr [[FV]], align 4
53104 // SIMD-ONLY0-NEXT:    br label [[IF_END6223]]
53105 // SIMD-ONLY0:       if.end6223:
53106 // SIMD-ONLY0-NEXT:    [[TMP4788:%.*]] = load float, ptr [[FE]], align 4
53107 // SIMD-ONLY0-NEXT:    [[TMP4789:%.*]] = load float, ptr [[FX]], align 4
53108 // SIMD-ONLY0-NEXT:    [[CMP6224:%.*]] = fcmp oeq float [[TMP4788]], [[TMP4789]]
53109 // SIMD-ONLY0-NEXT:    br i1 [[CMP6224]], label [[IF_THEN6226:%.*]], label [[IF_ELSE6227:%.*]]
53110 // SIMD-ONLY0:       if.then6226:
53111 // SIMD-ONLY0-NEXT:    [[TMP4790:%.*]] = load float, ptr [[FD]], align 4
53112 // SIMD-ONLY0-NEXT:    store float [[TMP4790]], ptr [[FX]], align 4
53113 // SIMD-ONLY0-NEXT:    br label [[IF_END6228:%.*]]
53114 // SIMD-ONLY0:       if.else6227:
53115 // SIMD-ONLY0-NEXT:    [[TMP4791:%.*]] = load float, ptr [[FX]], align 4
53116 // SIMD-ONLY0-NEXT:    store float [[TMP4791]], ptr [[FV]], align 4
53117 // SIMD-ONLY0-NEXT:    br label [[IF_END6228]]
53118 // SIMD-ONLY0:       if.end6228:
53119 // SIMD-ONLY0-NEXT:    [[TMP4792:%.*]] = load float, ptr [[FX]], align 4
53120 // SIMD-ONLY0-NEXT:    [[TMP4793:%.*]] = load float, ptr [[FE]], align 4
53121 // SIMD-ONLY0-NEXT:    [[CMP6229:%.*]] = fcmp oeq float [[TMP4792]], [[TMP4793]]
53122 // SIMD-ONLY0-NEXT:    [[CONV6230:%.*]] = zext i1 [[CMP6229]] to i32
53123 // SIMD-ONLY0-NEXT:    store i32 [[CONV6230]], ptr [[IR]], align 4
53124 // SIMD-ONLY0-NEXT:    [[TMP4794:%.*]] = load i32, ptr [[IR]], align 4
53125 // SIMD-ONLY0-NEXT:    [[TOBOOL6231:%.*]] = icmp ne i32 [[TMP4794]], 0
53126 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6231]], label [[IF_THEN6232:%.*]], label [[IF_END6233:%.*]]
53127 // SIMD-ONLY0:       if.then6232:
53128 // SIMD-ONLY0-NEXT:    [[TMP4795:%.*]] = load float, ptr [[FD]], align 4
53129 // SIMD-ONLY0-NEXT:    store float [[TMP4795]], ptr [[FX]], align 4
53130 // SIMD-ONLY0-NEXT:    br label [[IF_END6233]]
53131 // SIMD-ONLY0:       if.end6233:
53132 // SIMD-ONLY0-NEXT:    [[TMP4796:%.*]] = load float, ptr [[FE]], align 4
53133 // SIMD-ONLY0-NEXT:    [[TMP4797:%.*]] = load float, ptr [[FX]], align 4
53134 // SIMD-ONLY0-NEXT:    [[CMP6234:%.*]] = fcmp oeq float [[TMP4796]], [[TMP4797]]
53135 // SIMD-ONLY0-NEXT:    [[CONV6235:%.*]] = zext i1 [[CMP6234]] to i32
53136 // SIMD-ONLY0-NEXT:    store i32 [[CONV6235]], ptr [[IR]], align 4
53137 // SIMD-ONLY0-NEXT:    [[TMP4798:%.*]] = load i32, ptr [[IR]], align 4
53138 // SIMD-ONLY0-NEXT:    [[TOBOOL6236:%.*]] = icmp ne i32 [[TMP4798]], 0
53139 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6236]], label [[IF_THEN6237:%.*]], label [[IF_END6238:%.*]]
53140 // SIMD-ONLY0:       if.then6237:
53141 // SIMD-ONLY0-NEXT:    [[TMP4799:%.*]] = load float, ptr [[FD]], align 4
53142 // SIMD-ONLY0-NEXT:    store float [[TMP4799]], ptr [[FX]], align 4
53143 // SIMD-ONLY0-NEXT:    br label [[IF_END6238]]
53144 // SIMD-ONLY0:       if.end6238:
53145 // SIMD-ONLY0-NEXT:    [[TMP4800:%.*]] = load float, ptr [[FX]], align 4
53146 // SIMD-ONLY0-NEXT:    [[TMP4801:%.*]] = load float, ptr [[FE]], align 4
53147 // SIMD-ONLY0-NEXT:    [[CMP6239:%.*]] = fcmp oeq float [[TMP4800]], [[TMP4801]]
53148 // SIMD-ONLY0-NEXT:    [[CONV6240:%.*]] = zext i1 [[CMP6239]] to i32
53149 // SIMD-ONLY0-NEXT:    store i32 [[CONV6240]], ptr [[IR]], align 4
53150 // SIMD-ONLY0-NEXT:    [[TMP4802:%.*]] = load i32, ptr [[IR]], align 4
53151 // SIMD-ONLY0-NEXT:    [[TOBOOL6241:%.*]] = icmp ne i32 [[TMP4802]], 0
53152 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6241]], label [[IF_THEN6242:%.*]], label [[IF_ELSE6243:%.*]]
53153 // SIMD-ONLY0:       if.then6242:
53154 // SIMD-ONLY0-NEXT:    [[TMP4803:%.*]] = load float, ptr [[FD]], align 4
53155 // SIMD-ONLY0-NEXT:    store float [[TMP4803]], ptr [[FX]], align 4
53156 // SIMD-ONLY0-NEXT:    br label [[IF_END6244:%.*]]
53157 // SIMD-ONLY0:       if.else6243:
53158 // SIMD-ONLY0-NEXT:    [[TMP4804:%.*]] = load float, ptr [[FX]], align 4
53159 // SIMD-ONLY0-NEXT:    store float [[TMP4804]], ptr [[FV]], align 4
53160 // SIMD-ONLY0-NEXT:    br label [[IF_END6244]]
53161 // SIMD-ONLY0:       if.end6244:
53162 // SIMD-ONLY0-NEXT:    [[TMP4805:%.*]] = load float, ptr [[FE]], align 4
53163 // SIMD-ONLY0-NEXT:    [[TMP4806:%.*]] = load float, ptr [[FX]], align 4
53164 // SIMD-ONLY0-NEXT:    [[CMP6245:%.*]] = fcmp oeq float [[TMP4805]], [[TMP4806]]
53165 // SIMD-ONLY0-NEXT:    [[CONV6246:%.*]] = zext i1 [[CMP6245]] to i32
53166 // SIMD-ONLY0-NEXT:    store i32 [[CONV6246]], ptr [[IR]], align 4
53167 // SIMD-ONLY0-NEXT:    [[TMP4807:%.*]] = load i32, ptr [[IR]], align 4
53168 // SIMD-ONLY0-NEXT:    [[TOBOOL6247:%.*]] = icmp ne i32 [[TMP4807]], 0
53169 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6247]], label [[IF_THEN6248:%.*]], label [[IF_ELSE6249:%.*]]
53170 // SIMD-ONLY0:       if.then6248:
53171 // SIMD-ONLY0-NEXT:    [[TMP4808:%.*]] = load float, ptr [[FD]], align 4
53172 // SIMD-ONLY0-NEXT:    store float [[TMP4808]], ptr [[FX]], align 4
53173 // SIMD-ONLY0-NEXT:    br label [[IF_END6250:%.*]]
53174 // SIMD-ONLY0:       if.else6249:
53175 // SIMD-ONLY0-NEXT:    [[TMP4809:%.*]] = load float, ptr [[FX]], align 4
53176 // SIMD-ONLY0-NEXT:    store float [[TMP4809]], ptr [[FV]], align 4
53177 // SIMD-ONLY0-NEXT:    br label [[IF_END6250]]
53178 // SIMD-ONLY0:       if.end6250:
53179 // SIMD-ONLY0-NEXT:    [[TMP4810:%.*]] = load float, ptr [[FX]], align 4
53180 // SIMD-ONLY0-NEXT:    store float [[TMP4810]], ptr [[FV]], align 4
53181 // SIMD-ONLY0-NEXT:    [[TMP4811:%.*]] = load float, ptr [[FE]], align 4
53182 // SIMD-ONLY0-NEXT:    [[TMP4812:%.*]] = load float, ptr [[FX]], align 4
53183 // SIMD-ONLY0-NEXT:    [[CMP6251:%.*]] = fcmp ogt float [[TMP4811]], [[TMP4812]]
53184 // SIMD-ONLY0-NEXT:    br i1 [[CMP6251]], label [[IF_THEN6253:%.*]], label [[IF_END6254:%.*]]
53185 // SIMD-ONLY0:       if.then6253:
53186 // SIMD-ONLY0-NEXT:    [[TMP4813:%.*]] = load float, ptr [[FE]], align 4
53187 // SIMD-ONLY0-NEXT:    store float [[TMP4813]], ptr [[FX]], align 4
53188 // SIMD-ONLY0-NEXT:    br label [[IF_END6254]]
53189 // SIMD-ONLY0:       if.end6254:
53190 // SIMD-ONLY0-NEXT:    [[TMP4814:%.*]] = load float, ptr [[FX]], align 4
53191 // SIMD-ONLY0-NEXT:    store float [[TMP4814]], ptr [[FV]], align 4
53192 // SIMD-ONLY0-NEXT:    [[TMP4815:%.*]] = load float, ptr [[FX]], align 4
53193 // SIMD-ONLY0-NEXT:    [[TMP4816:%.*]] = load float, ptr [[FE]], align 4
53194 // SIMD-ONLY0-NEXT:    [[CMP6255:%.*]] = fcmp ogt float [[TMP4815]], [[TMP4816]]
53195 // SIMD-ONLY0-NEXT:    br i1 [[CMP6255]], label [[IF_THEN6257:%.*]], label [[IF_END6258:%.*]]
53196 // SIMD-ONLY0:       if.then6257:
53197 // SIMD-ONLY0-NEXT:    [[TMP4817:%.*]] = load float, ptr [[FE]], align 4
53198 // SIMD-ONLY0-NEXT:    store float [[TMP4817]], ptr [[FX]], align 4
53199 // SIMD-ONLY0-NEXT:    br label [[IF_END6258]]
53200 // SIMD-ONLY0:       if.end6258:
53201 // SIMD-ONLY0-NEXT:    [[TMP4818:%.*]] = load float, ptr [[FX]], align 4
53202 // SIMD-ONLY0-NEXT:    store float [[TMP4818]], ptr [[FV]], align 4
53203 // SIMD-ONLY0-NEXT:    [[TMP4819:%.*]] = load float, ptr [[FE]], align 4
53204 // SIMD-ONLY0-NEXT:    [[TMP4820:%.*]] = load float, ptr [[FX]], align 4
53205 // SIMD-ONLY0-NEXT:    [[CMP6259:%.*]] = fcmp olt float [[TMP4819]], [[TMP4820]]
53206 // SIMD-ONLY0-NEXT:    br i1 [[CMP6259]], label [[IF_THEN6261:%.*]], label [[IF_END6262:%.*]]
53207 // SIMD-ONLY0:       if.then6261:
53208 // SIMD-ONLY0-NEXT:    [[TMP4821:%.*]] = load float, ptr [[FE]], align 4
53209 // SIMD-ONLY0-NEXT:    store float [[TMP4821]], ptr [[FX]], align 4
53210 // SIMD-ONLY0-NEXT:    br label [[IF_END6262]]
53211 // SIMD-ONLY0:       if.end6262:
53212 // SIMD-ONLY0-NEXT:    [[TMP4822:%.*]] = load float, ptr [[FX]], align 4
53213 // SIMD-ONLY0-NEXT:    store float [[TMP4822]], ptr [[FV]], align 4
53214 // SIMD-ONLY0-NEXT:    [[TMP4823:%.*]] = load float, ptr [[FX]], align 4
53215 // SIMD-ONLY0-NEXT:    [[TMP4824:%.*]] = load float, ptr [[FE]], align 4
53216 // SIMD-ONLY0-NEXT:    [[CMP6263:%.*]] = fcmp olt float [[TMP4823]], [[TMP4824]]
53217 // SIMD-ONLY0-NEXT:    br i1 [[CMP6263]], label [[IF_THEN6265:%.*]], label [[IF_END6266:%.*]]
53218 // SIMD-ONLY0:       if.then6265:
53219 // SIMD-ONLY0-NEXT:    [[TMP4825:%.*]] = load float, ptr [[FE]], align 4
53220 // SIMD-ONLY0-NEXT:    store float [[TMP4825]], ptr [[FX]], align 4
53221 // SIMD-ONLY0-NEXT:    br label [[IF_END6266]]
53222 // SIMD-ONLY0:       if.end6266:
53223 // SIMD-ONLY0-NEXT:    [[TMP4826:%.*]] = load float, ptr [[FX]], align 4
53224 // SIMD-ONLY0-NEXT:    store float [[TMP4826]], ptr [[FV]], align 4
53225 // SIMD-ONLY0-NEXT:    [[TMP4827:%.*]] = load float, ptr [[FX]], align 4
53226 // SIMD-ONLY0-NEXT:    [[TMP4828:%.*]] = load float, ptr [[FE]], align 4
53227 // SIMD-ONLY0-NEXT:    [[CMP6267:%.*]] = fcmp oeq float [[TMP4827]], [[TMP4828]]
53228 // SIMD-ONLY0-NEXT:    br i1 [[CMP6267]], label [[IF_THEN6269:%.*]], label [[IF_END6270:%.*]]
53229 // SIMD-ONLY0:       if.then6269:
53230 // SIMD-ONLY0-NEXT:    [[TMP4829:%.*]] = load float, ptr [[FD]], align 4
53231 // SIMD-ONLY0-NEXT:    store float [[TMP4829]], ptr [[FX]], align 4
53232 // SIMD-ONLY0-NEXT:    br label [[IF_END6270]]
53233 // SIMD-ONLY0:       if.end6270:
53234 // SIMD-ONLY0-NEXT:    [[TMP4830:%.*]] = load float, ptr [[FX]], align 4
53235 // SIMD-ONLY0-NEXT:    store float [[TMP4830]], ptr [[FV]], align 4
53236 // SIMD-ONLY0-NEXT:    [[TMP4831:%.*]] = load float, ptr [[FE]], align 4
53237 // SIMD-ONLY0-NEXT:    [[TMP4832:%.*]] = load float, ptr [[FX]], align 4
53238 // SIMD-ONLY0-NEXT:    [[CMP6271:%.*]] = fcmp oeq float [[TMP4831]], [[TMP4832]]
53239 // SIMD-ONLY0-NEXT:    br i1 [[CMP6271]], label [[IF_THEN6273:%.*]], label [[IF_END6274:%.*]]
53240 // SIMD-ONLY0:       if.then6273:
53241 // SIMD-ONLY0-NEXT:    [[TMP4833:%.*]] = load float, ptr [[FD]], align 4
53242 // SIMD-ONLY0-NEXT:    store float [[TMP4833]], ptr [[FX]], align 4
53243 // SIMD-ONLY0-NEXT:    br label [[IF_END6274]]
53244 // SIMD-ONLY0:       if.end6274:
53245 // SIMD-ONLY0-NEXT:    [[TMP4834:%.*]] = load float, ptr [[FE]], align 4
53246 // SIMD-ONLY0-NEXT:    [[TMP4835:%.*]] = load float, ptr [[FX]], align 4
53247 // SIMD-ONLY0-NEXT:    [[CMP6275:%.*]] = fcmp ogt float [[TMP4834]], [[TMP4835]]
53248 // SIMD-ONLY0-NEXT:    br i1 [[CMP6275]], label [[IF_THEN6277:%.*]], label [[IF_END6278:%.*]]
53249 // SIMD-ONLY0:       if.then6277:
53250 // SIMD-ONLY0-NEXT:    [[TMP4836:%.*]] = load float, ptr [[FE]], align 4
53251 // SIMD-ONLY0-NEXT:    store float [[TMP4836]], ptr [[FX]], align 4
53252 // SIMD-ONLY0-NEXT:    br label [[IF_END6278]]
53253 // SIMD-ONLY0:       if.end6278:
53254 // SIMD-ONLY0-NEXT:    [[TMP4837:%.*]] = load float, ptr [[FX]], align 4
53255 // SIMD-ONLY0-NEXT:    store float [[TMP4837]], ptr [[FV]], align 4
53256 // SIMD-ONLY0-NEXT:    [[TMP4838:%.*]] = load float, ptr [[FX]], align 4
53257 // SIMD-ONLY0-NEXT:    [[TMP4839:%.*]] = load float, ptr [[FE]], align 4
53258 // SIMD-ONLY0-NEXT:    [[CMP6279:%.*]] = fcmp ogt float [[TMP4838]], [[TMP4839]]
53259 // SIMD-ONLY0-NEXT:    br i1 [[CMP6279]], label [[IF_THEN6281:%.*]], label [[IF_END6282:%.*]]
53260 // SIMD-ONLY0:       if.then6281:
53261 // SIMD-ONLY0-NEXT:    [[TMP4840:%.*]] = load float, ptr [[FE]], align 4
53262 // SIMD-ONLY0-NEXT:    store float [[TMP4840]], ptr [[FX]], align 4
53263 // SIMD-ONLY0-NEXT:    br label [[IF_END6282]]
53264 // SIMD-ONLY0:       if.end6282:
53265 // SIMD-ONLY0-NEXT:    [[TMP4841:%.*]] = load float, ptr [[FX]], align 4
53266 // SIMD-ONLY0-NEXT:    store float [[TMP4841]], ptr [[FV]], align 4
53267 // SIMD-ONLY0-NEXT:    [[TMP4842:%.*]] = load float, ptr [[FE]], align 4
53268 // SIMD-ONLY0-NEXT:    [[TMP4843:%.*]] = load float, ptr [[FX]], align 4
53269 // SIMD-ONLY0-NEXT:    [[CMP6283:%.*]] = fcmp olt float [[TMP4842]], [[TMP4843]]
53270 // SIMD-ONLY0-NEXT:    br i1 [[CMP6283]], label [[IF_THEN6285:%.*]], label [[IF_END6286:%.*]]
53271 // SIMD-ONLY0:       if.then6285:
53272 // SIMD-ONLY0-NEXT:    [[TMP4844:%.*]] = load float, ptr [[FE]], align 4
53273 // SIMD-ONLY0-NEXT:    store float [[TMP4844]], ptr [[FX]], align 4
53274 // SIMD-ONLY0-NEXT:    br label [[IF_END6286]]
53275 // SIMD-ONLY0:       if.end6286:
53276 // SIMD-ONLY0-NEXT:    [[TMP4845:%.*]] = load float, ptr [[FX]], align 4
53277 // SIMD-ONLY0-NEXT:    store float [[TMP4845]], ptr [[FV]], align 4
53278 // SIMD-ONLY0-NEXT:    [[TMP4846:%.*]] = load float, ptr [[FX]], align 4
53279 // SIMD-ONLY0-NEXT:    [[TMP4847:%.*]] = load float, ptr [[FE]], align 4
53280 // SIMD-ONLY0-NEXT:    [[CMP6287:%.*]] = fcmp olt float [[TMP4846]], [[TMP4847]]
53281 // SIMD-ONLY0-NEXT:    br i1 [[CMP6287]], label [[IF_THEN6289:%.*]], label [[IF_END6290:%.*]]
53282 // SIMD-ONLY0:       if.then6289:
53283 // SIMD-ONLY0-NEXT:    [[TMP4848:%.*]] = load float, ptr [[FE]], align 4
53284 // SIMD-ONLY0-NEXT:    store float [[TMP4848]], ptr [[FX]], align 4
53285 // SIMD-ONLY0-NEXT:    br label [[IF_END6290]]
53286 // SIMD-ONLY0:       if.end6290:
53287 // SIMD-ONLY0-NEXT:    [[TMP4849:%.*]] = load float, ptr [[FX]], align 4
53288 // SIMD-ONLY0-NEXT:    store float [[TMP4849]], ptr [[FV]], align 4
53289 // SIMD-ONLY0-NEXT:    [[TMP4850:%.*]] = load float, ptr [[FX]], align 4
53290 // SIMD-ONLY0-NEXT:    [[TMP4851:%.*]] = load float, ptr [[FE]], align 4
53291 // SIMD-ONLY0-NEXT:    [[CMP6291:%.*]] = fcmp oeq float [[TMP4850]], [[TMP4851]]
53292 // SIMD-ONLY0-NEXT:    br i1 [[CMP6291]], label [[IF_THEN6293:%.*]], label [[IF_END6294:%.*]]
53293 // SIMD-ONLY0:       if.then6293:
53294 // SIMD-ONLY0-NEXT:    [[TMP4852:%.*]] = load float, ptr [[FD]], align 4
53295 // SIMD-ONLY0-NEXT:    store float [[TMP4852]], ptr [[FX]], align 4
53296 // SIMD-ONLY0-NEXT:    br label [[IF_END6294]]
53297 // SIMD-ONLY0:       if.end6294:
53298 // SIMD-ONLY0-NEXT:    [[TMP4853:%.*]] = load float, ptr [[FX]], align 4
53299 // SIMD-ONLY0-NEXT:    store float [[TMP4853]], ptr [[FV]], align 4
53300 // SIMD-ONLY0-NEXT:    [[TMP4854:%.*]] = load float, ptr [[FE]], align 4
53301 // SIMD-ONLY0-NEXT:    [[TMP4855:%.*]] = load float, ptr [[FX]], align 4
53302 // SIMD-ONLY0-NEXT:    [[CMP6295:%.*]] = fcmp oeq float [[TMP4854]], [[TMP4855]]
53303 // SIMD-ONLY0-NEXT:    br i1 [[CMP6295]], label [[IF_THEN6297:%.*]], label [[IF_END6298:%.*]]
53304 // SIMD-ONLY0:       if.then6297:
53305 // SIMD-ONLY0-NEXT:    [[TMP4856:%.*]] = load float, ptr [[FD]], align 4
53306 // SIMD-ONLY0-NEXT:    store float [[TMP4856]], ptr [[FX]], align 4
53307 // SIMD-ONLY0-NEXT:    br label [[IF_END6298]]
53308 // SIMD-ONLY0:       if.end6298:
53309 // SIMD-ONLY0-NEXT:    [[TMP4857:%.*]] = load float, ptr [[FX]], align 4
53310 // SIMD-ONLY0-NEXT:    store float [[TMP4857]], ptr [[FV]], align 4
53311 // SIMD-ONLY0-NEXT:    [[TMP4858:%.*]] = load float, ptr [[FX]], align 4
53312 // SIMD-ONLY0-NEXT:    [[TMP4859:%.*]] = load float, ptr [[FE]], align 4
53313 // SIMD-ONLY0-NEXT:    [[CMP6299:%.*]] = fcmp oeq float [[TMP4858]], [[TMP4859]]
53314 // SIMD-ONLY0-NEXT:    br i1 [[CMP6299]], label [[IF_THEN6301:%.*]], label [[IF_ELSE6302:%.*]]
53315 // SIMD-ONLY0:       if.then6301:
53316 // SIMD-ONLY0-NEXT:    [[TMP4860:%.*]] = load float, ptr [[FD]], align 4
53317 // SIMD-ONLY0-NEXT:    store float [[TMP4860]], ptr [[FX]], align 4
53318 // SIMD-ONLY0-NEXT:    br label [[IF_END6303:%.*]]
53319 // SIMD-ONLY0:       if.else6302:
53320 // SIMD-ONLY0-NEXT:    [[TMP4861:%.*]] = load float, ptr [[FX]], align 4
53321 // SIMD-ONLY0-NEXT:    store float [[TMP4861]], ptr [[FV]], align 4
53322 // SIMD-ONLY0-NEXT:    br label [[IF_END6303]]
53323 // SIMD-ONLY0:       if.end6303:
53324 // SIMD-ONLY0-NEXT:    [[TMP4862:%.*]] = load float, ptr [[FE]], align 4
53325 // SIMD-ONLY0-NEXT:    [[TMP4863:%.*]] = load float, ptr [[FX]], align 4
53326 // SIMD-ONLY0-NEXT:    [[CMP6304:%.*]] = fcmp oeq float [[TMP4862]], [[TMP4863]]
53327 // SIMD-ONLY0-NEXT:    br i1 [[CMP6304]], label [[IF_THEN6306:%.*]], label [[IF_ELSE6307:%.*]]
53328 // SIMD-ONLY0:       if.then6306:
53329 // SIMD-ONLY0-NEXT:    [[TMP4864:%.*]] = load float, ptr [[FD]], align 4
53330 // SIMD-ONLY0-NEXT:    store float [[TMP4864]], ptr [[FX]], align 4
53331 // SIMD-ONLY0-NEXT:    br label [[IF_END6308:%.*]]
53332 // SIMD-ONLY0:       if.else6307:
53333 // SIMD-ONLY0-NEXT:    [[TMP4865:%.*]] = load float, ptr [[FX]], align 4
53334 // SIMD-ONLY0-NEXT:    store float [[TMP4865]], ptr [[FV]], align 4
53335 // SIMD-ONLY0-NEXT:    br label [[IF_END6308]]
53336 // SIMD-ONLY0:       if.end6308:
53337 // SIMD-ONLY0-NEXT:    [[TMP4866:%.*]] = load float, ptr [[FX]], align 4
53338 // SIMD-ONLY0-NEXT:    [[TMP4867:%.*]] = load float, ptr [[FE]], align 4
53339 // SIMD-ONLY0-NEXT:    [[CMP6309:%.*]] = fcmp oeq float [[TMP4866]], [[TMP4867]]
53340 // SIMD-ONLY0-NEXT:    [[CONV6310:%.*]] = zext i1 [[CMP6309]] to i32
53341 // SIMD-ONLY0-NEXT:    store i32 [[CONV6310]], ptr [[IR]], align 4
53342 // SIMD-ONLY0-NEXT:    [[TMP4868:%.*]] = load i32, ptr [[IR]], align 4
53343 // SIMD-ONLY0-NEXT:    [[TOBOOL6311:%.*]] = icmp ne i32 [[TMP4868]], 0
53344 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6311]], label [[IF_THEN6312:%.*]], label [[IF_END6313:%.*]]
53345 // SIMD-ONLY0:       if.then6312:
53346 // SIMD-ONLY0-NEXT:    [[TMP4869:%.*]] = load float, ptr [[FD]], align 4
53347 // SIMD-ONLY0-NEXT:    store float [[TMP4869]], ptr [[FX]], align 4
53348 // SIMD-ONLY0-NEXT:    br label [[IF_END6313]]
53349 // SIMD-ONLY0:       if.end6313:
53350 // SIMD-ONLY0-NEXT:    [[TMP4870:%.*]] = load float, ptr [[FE]], align 4
53351 // SIMD-ONLY0-NEXT:    [[TMP4871:%.*]] = load float, ptr [[FX]], align 4
53352 // SIMD-ONLY0-NEXT:    [[CMP6314:%.*]] = fcmp oeq float [[TMP4870]], [[TMP4871]]
53353 // SIMD-ONLY0-NEXT:    [[CONV6315:%.*]] = zext i1 [[CMP6314]] to i32
53354 // SIMD-ONLY0-NEXT:    store i32 [[CONV6315]], ptr [[IR]], align 4
53355 // SIMD-ONLY0-NEXT:    [[TMP4872:%.*]] = load i32, ptr [[IR]], align 4
53356 // SIMD-ONLY0-NEXT:    [[TOBOOL6316:%.*]] = icmp ne i32 [[TMP4872]], 0
53357 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6316]], label [[IF_THEN6317:%.*]], label [[IF_END6318:%.*]]
53358 // SIMD-ONLY0:       if.then6317:
53359 // SIMD-ONLY0-NEXT:    [[TMP4873:%.*]] = load float, ptr [[FD]], align 4
53360 // SIMD-ONLY0-NEXT:    store float [[TMP4873]], ptr [[FX]], align 4
53361 // SIMD-ONLY0-NEXT:    br label [[IF_END6318]]
53362 // SIMD-ONLY0:       if.end6318:
53363 // SIMD-ONLY0-NEXT:    [[TMP4874:%.*]] = load float, ptr [[FX]], align 4
53364 // SIMD-ONLY0-NEXT:    [[TMP4875:%.*]] = load float, ptr [[FE]], align 4
53365 // SIMD-ONLY0-NEXT:    [[CMP6319:%.*]] = fcmp oeq float [[TMP4874]], [[TMP4875]]
53366 // SIMD-ONLY0-NEXT:    [[CONV6320:%.*]] = zext i1 [[CMP6319]] to i32
53367 // SIMD-ONLY0-NEXT:    store i32 [[CONV6320]], ptr [[IR]], align 4
53368 // SIMD-ONLY0-NEXT:    [[TMP4876:%.*]] = load i32, ptr [[IR]], align 4
53369 // SIMD-ONLY0-NEXT:    [[TOBOOL6321:%.*]] = icmp ne i32 [[TMP4876]], 0
53370 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6321]], label [[IF_THEN6322:%.*]], label [[IF_ELSE6323:%.*]]
53371 // SIMD-ONLY0:       if.then6322:
53372 // SIMD-ONLY0-NEXT:    [[TMP4877:%.*]] = load float, ptr [[FD]], align 4
53373 // SIMD-ONLY0-NEXT:    store float [[TMP4877]], ptr [[FX]], align 4
53374 // SIMD-ONLY0-NEXT:    br label [[IF_END6324:%.*]]
53375 // SIMD-ONLY0:       if.else6323:
53376 // SIMD-ONLY0-NEXT:    [[TMP4878:%.*]] = load float, ptr [[FX]], align 4
53377 // SIMD-ONLY0-NEXT:    store float [[TMP4878]], ptr [[FV]], align 4
53378 // SIMD-ONLY0-NEXT:    br label [[IF_END6324]]
53379 // SIMD-ONLY0:       if.end6324:
53380 // SIMD-ONLY0-NEXT:    [[TMP4879:%.*]] = load float, ptr [[FE]], align 4
53381 // SIMD-ONLY0-NEXT:    [[TMP4880:%.*]] = load float, ptr [[FX]], align 4
53382 // SIMD-ONLY0-NEXT:    [[CMP6325:%.*]] = fcmp oeq float [[TMP4879]], [[TMP4880]]
53383 // SIMD-ONLY0-NEXT:    [[CONV6326:%.*]] = zext i1 [[CMP6325]] to i32
53384 // SIMD-ONLY0-NEXT:    store i32 [[CONV6326]], ptr [[IR]], align 4
53385 // SIMD-ONLY0-NEXT:    [[TMP4881:%.*]] = load i32, ptr [[IR]], align 4
53386 // SIMD-ONLY0-NEXT:    [[TOBOOL6327:%.*]] = icmp ne i32 [[TMP4881]], 0
53387 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6327]], label [[IF_THEN6328:%.*]], label [[IF_ELSE6329:%.*]]
53388 // SIMD-ONLY0:       if.then6328:
53389 // SIMD-ONLY0-NEXT:    [[TMP4882:%.*]] = load float, ptr [[FD]], align 4
53390 // SIMD-ONLY0-NEXT:    store float [[TMP4882]], ptr [[FX]], align 4
53391 // SIMD-ONLY0-NEXT:    br label [[IF_END6330:%.*]]
53392 // SIMD-ONLY0:       if.else6329:
53393 // SIMD-ONLY0-NEXT:    [[TMP4883:%.*]] = load float, ptr [[FX]], align 4
53394 // SIMD-ONLY0-NEXT:    store float [[TMP4883]], ptr [[FV]], align 4
53395 // SIMD-ONLY0-NEXT:    br label [[IF_END6330]]
53396 // SIMD-ONLY0:       if.end6330:
53397 // SIMD-ONLY0-NEXT:    [[TMP4884:%.*]] = load double, ptr [[DX]], align 8
53398 // SIMD-ONLY0-NEXT:    store double [[TMP4884]], ptr [[DV]], align 8
53399 // SIMD-ONLY0-NEXT:    [[TMP4885:%.*]] = load double, ptr [[DE]], align 8
53400 // SIMD-ONLY0-NEXT:    [[TMP4886:%.*]] = load double, ptr [[DX]], align 8
53401 // SIMD-ONLY0-NEXT:    [[CMP6331:%.*]] = fcmp ogt double [[TMP4885]], [[TMP4886]]
53402 // SIMD-ONLY0-NEXT:    br i1 [[CMP6331]], label [[IF_THEN6333:%.*]], label [[IF_END6334:%.*]]
53403 // SIMD-ONLY0:       if.then6333:
53404 // SIMD-ONLY0-NEXT:    [[TMP4887:%.*]] = load double, ptr [[DE]], align 8
53405 // SIMD-ONLY0-NEXT:    store double [[TMP4887]], ptr [[DX]], align 8
53406 // SIMD-ONLY0-NEXT:    br label [[IF_END6334]]
53407 // SIMD-ONLY0:       if.end6334:
53408 // SIMD-ONLY0-NEXT:    [[TMP4888:%.*]] = load double, ptr [[DX]], align 8
53409 // SIMD-ONLY0-NEXT:    store double [[TMP4888]], ptr [[DV]], align 8
53410 // SIMD-ONLY0-NEXT:    [[TMP4889:%.*]] = load double, ptr [[DX]], align 8
53411 // SIMD-ONLY0-NEXT:    [[TMP4890:%.*]] = load double, ptr [[DE]], align 8
53412 // SIMD-ONLY0-NEXT:    [[CMP6335:%.*]] = fcmp ogt double [[TMP4889]], [[TMP4890]]
53413 // SIMD-ONLY0-NEXT:    br i1 [[CMP6335]], label [[IF_THEN6337:%.*]], label [[IF_END6338:%.*]]
53414 // SIMD-ONLY0:       if.then6337:
53415 // SIMD-ONLY0-NEXT:    [[TMP4891:%.*]] = load double, ptr [[DE]], align 8
53416 // SIMD-ONLY0-NEXT:    store double [[TMP4891]], ptr [[DX]], align 8
53417 // SIMD-ONLY0-NEXT:    br label [[IF_END6338]]
53418 // SIMD-ONLY0:       if.end6338:
53419 // SIMD-ONLY0-NEXT:    [[TMP4892:%.*]] = load double, ptr [[DX]], align 8
53420 // SIMD-ONLY0-NEXT:    store double [[TMP4892]], ptr [[DV]], align 8
53421 // SIMD-ONLY0-NEXT:    [[TMP4893:%.*]] = load double, ptr [[DE]], align 8
53422 // SIMD-ONLY0-NEXT:    [[TMP4894:%.*]] = load double, ptr [[DX]], align 8
53423 // SIMD-ONLY0-NEXT:    [[CMP6339:%.*]] = fcmp olt double [[TMP4893]], [[TMP4894]]
53424 // SIMD-ONLY0-NEXT:    br i1 [[CMP6339]], label [[IF_THEN6341:%.*]], label [[IF_END6342:%.*]]
53425 // SIMD-ONLY0:       if.then6341:
53426 // SIMD-ONLY0-NEXT:    [[TMP4895:%.*]] = load double, ptr [[DE]], align 8
53427 // SIMD-ONLY0-NEXT:    store double [[TMP4895]], ptr [[DX]], align 8
53428 // SIMD-ONLY0-NEXT:    br label [[IF_END6342]]
53429 // SIMD-ONLY0:       if.end6342:
53430 // SIMD-ONLY0-NEXT:    [[TMP4896:%.*]] = load double, ptr [[DX]], align 8
53431 // SIMD-ONLY0-NEXT:    store double [[TMP4896]], ptr [[DV]], align 8
53432 // SIMD-ONLY0-NEXT:    [[TMP4897:%.*]] = load double, ptr [[DX]], align 8
53433 // SIMD-ONLY0-NEXT:    [[TMP4898:%.*]] = load double, ptr [[DE]], align 8
53434 // SIMD-ONLY0-NEXT:    [[CMP6343:%.*]] = fcmp olt double [[TMP4897]], [[TMP4898]]
53435 // SIMD-ONLY0-NEXT:    br i1 [[CMP6343]], label [[IF_THEN6345:%.*]], label [[IF_END6346:%.*]]
53436 // SIMD-ONLY0:       if.then6345:
53437 // SIMD-ONLY0-NEXT:    [[TMP4899:%.*]] = load double, ptr [[DE]], align 8
53438 // SIMD-ONLY0-NEXT:    store double [[TMP4899]], ptr [[DX]], align 8
53439 // SIMD-ONLY0-NEXT:    br label [[IF_END6346]]
53440 // SIMD-ONLY0:       if.end6346:
53441 // SIMD-ONLY0-NEXT:    [[TMP4900:%.*]] = load double, ptr [[DX]], align 8
53442 // SIMD-ONLY0-NEXT:    store double [[TMP4900]], ptr [[DV]], align 8
53443 // SIMD-ONLY0-NEXT:    [[TMP4901:%.*]] = load double, ptr [[DX]], align 8
53444 // SIMD-ONLY0-NEXT:    [[TMP4902:%.*]] = load double, ptr [[DE]], align 8
53445 // SIMD-ONLY0-NEXT:    [[CMP6347:%.*]] = fcmp oeq double [[TMP4901]], [[TMP4902]]
53446 // SIMD-ONLY0-NEXT:    br i1 [[CMP6347]], label [[IF_THEN6349:%.*]], label [[IF_END6350:%.*]]
53447 // SIMD-ONLY0:       if.then6349:
53448 // SIMD-ONLY0-NEXT:    [[TMP4903:%.*]] = load double, ptr [[DD]], align 8
53449 // SIMD-ONLY0-NEXT:    store double [[TMP4903]], ptr [[DX]], align 8
53450 // SIMD-ONLY0-NEXT:    br label [[IF_END6350]]
53451 // SIMD-ONLY0:       if.end6350:
53452 // SIMD-ONLY0-NEXT:    [[TMP4904:%.*]] = load double, ptr [[DX]], align 8
53453 // SIMD-ONLY0-NEXT:    store double [[TMP4904]], ptr [[DV]], align 8
53454 // SIMD-ONLY0-NEXT:    [[TMP4905:%.*]] = load double, ptr [[DE]], align 8
53455 // SIMD-ONLY0-NEXT:    [[TMP4906:%.*]] = load double, ptr [[DX]], align 8
53456 // SIMD-ONLY0-NEXT:    [[CMP6351:%.*]] = fcmp oeq double [[TMP4905]], [[TMP4906]]
53457 // SIMD-ONLY0-NEXT:    br i1 [[CMP6351]], label [[IF_THEN6353:%.*]], label [[IF_END6354:%.*]]
53458 // SIMD-ONLY0:       if.then6353:
53459 // SIMD-ONLY0-NEXT:    [[TMP4907:%.*]] = load double, ptr [[DD]], align 8
53460 // SIMD-ONLY0-NEXT:    store double [[TMP4907]], ptr [[DX]], align 8
53461 // SIMD-ONLY0-NEXT:    br label [[IF_END6354]]
53462 // SIMD-ONLY0:       if.end6354:
53463 // SIMD-ONLY0-NEXT:    [[TMP4908:%.*]] = load double, ptr [[DE]], align 8
53464 // SIMD-ONLY0-NEXT:    [[TMP4909:%.*]] = load double, ptr [[DX]], align 8
53465 // SIMD-ONLY0-NEXT:    [[CMP6355:%.*]] = fcmp ogt double [[TMP4908]], [[TMP4909]]
53466 // SIMD-ONLY0-NEXT:    br i1 [[CMP6355]], label [[IF_THEN6357:%.*]], label [[IF_END6358:%.*]]
53467 // SIMD-ONLY0:       if.then6357:
53468 // SIMD-ONLY0-NEXT:    [[TMP4910:%.*]] = load double, ptr [[DE]], align 8
53469 // SIMD-ONLY0-NEXT:    store double [[TMP4910]], ptr [[DX]], align 8
53470 // SIMD-ONLY0-NEXT:    br label [[IF_END6358]]
53471 // SIMD-ONLY0:       if.end6358:
53472 // SIMD-ONLY0-NEXT:    [[TMP4911:%.*]] = load double, ptr [[DX]], align 8
53473 // SIMD-ONLY0-NEXT:    store double [[TMP4911]], ptr [[DV]], align 8
53474 // SIMD-ONLY0-NEXT:    [[TMP4912:%.*]] = load double, ptr [[DX]], align 8
53475 // SIMD-ONLY0-NEXT:    [[TMP4913:%.*]] = load double, ptr [[DE]], align 8
53476 // SIMD-ONLY0-NEXT:    [[CMP6359:%.*]] = fcmp ogt double [[TMP4912]], [[TMP4913]]
53477 // SIMD-ONLY0-NEXT:    br i1 [[CMP6359]], label [[IF_THEN6361:%.*]], label [[IF_END6362:%.*]]
53478 // SIMD-ONLY0:       if.then6361:
53479 // SIMD-ONLY0-NEXT:    [[TMP4914:%.*]] = load double, ptr [[DE]], align 8
53480 // SIMD-ONLY0-NEXT:    store double [[TMP4914]], ptr [[DX]], align 8
53481 // SIMD-ONLY0-NEXT:    br label [[IF_END6362]]
53482 // SIMD-ONLY0:       if.end6362:
53483 // SIMD-ONLY0-NEXT:    [[TMP4915:%.*]] = load double, ptr [[DX]], align 8
53484 // SIMD-ONLY0-NEXT:    store double [[TMP4915]], ptr [[DV]], align 8
53485 // SIMD-ONLY0-NEXT:    [[TMP4916:%.*]] = load double, ptr [[DE]], align 8
53486 // SIMD-ONLY0-NEXT:    [[TMP4917:%.*]] = load double, ptr [[DX]], align 8
53487 // SIMD-ONLY0-NEXT:    [[CMP6363:%.*]] = fcmp olt double [[TMP4916]], [[TMP4917]]
53488 // SIMD-ONLY0-NEXT:    br i1 [[CMP6363]], label [[IF_THEN6365:%.*]], label [[IF_END6366:%.*]]
53489 // SIMD-ONLY0:       if.then6365:
53490 // SIMD-ONLY0-NEXT:    [[TMP4918:%.*]] = load double, ptr [[DE]], align 8
53491 // SIMD-ONLY0-NEXT:    store double [[TMP4918]], ptr [[DX]], align 8
53492 // SIMD-ONLY0-NEXT:    br label [[IF_END6366]]
53493 // SIMD-ONLY0:       if.end6366:
53494 // SIMD-ONLY0-NEXT:    [[TMP4919:%.*]] = load double, ptr [[DX]], align 8
53495 // SIMD-ONLY0-NEXT:    store double [[TMP4919]], ptr [[DV]], align 8
53496 // SIMD-ONLY0-NEXT:    [[TMP4920:%.*]] = load double, ptr [[DX]], align 8
53497 // SIMD-ONLY0-NEXT:    [[TMP4921:%.*]] = load double, ptr [[DE]], align 8
53498 // SIMD-ONLY0-NEXT:    [[CMP6367:%.*]] = fcmp olt double [[TMP4920]], [[TMP4921]]
53499 // SIMD-ONLY0-NEXT:    br i1 [[CMP6367]], label [[IF_THEN6369:%.*]], label [[IF_END6370:%.*]]
53500 // SIMD-ONLY0:       if.then6369:
53501 // SIMD-ONLY0-NEXT:    [[TMP4922:%.*]] = load double, ptr [[DE]], align 8
53502 // SIMD-ONLY0-NEXT:    store double [[TMP4922]], ptr [[DX]], align 8
53503 // SIMD-ONLY0-NEXT:    br label [[IF_END6370]]
53504 // SIMD-ONLY0:       if.end6370:
53505 // SIMD-ONLY0-NEXT:    [[TMP4923:%.*]] = load double, ptr [[DX]], align 8
53506 // SIMD-ONLY0-NEXT:    store double [[TMP4923]], ptr [[DV]], align 8
53507 // SIMD-ONLY0-NEXT:    [[TMP4924:%.*]] = load double, ptr [[DX]], align 8
53508 // SIMD-ONLY0-NEXT:    [[TMP4925:%.*]] = load double, ptr [[DE]], align 8
53509 // SIMD-ONLY0-NEXT:    [[CMP6371:%.*]] = fcmp oeq double [[TMP4924]], [[TMP4925]]
53510 // SIMD-ONLY0-NEXT:    br i1 [[CMP6371]], label [[IF_THEN6373:%.*]], label [[IF_END6374:%.*]]
53511 // SIMD-ONLY0:       if.then6373:
53512 // SIMD-ONLY0-NEXT:    [[TMP4926:%.*]] = load double, ptr [[DD]], align 8
53513 // SIMD-ONLY0-NEXT:    store double [[TMP4926]], ptr [[DX]], align 8
53514 // SIMD-ONLY0-NEXT:    br label [[IF_END6374]]
53515 // SIMD-ONLY0:       if.end6374:
53516 // SIMD-ONLY0-NEXT:    [[TMP4927:%.*]] = load double, ptr [[DX]], align 8
53517 // SIMD-ONLY0-NEXT:    store double [[TMP4927]], ptr [[DV]], align 8
53518 // SIMD-ONLY0-NEXT:    [[TMP4928:%.*]] = load double, ptr [[DE]], align 8
53519 // SIMD-ONLY0-NEXT:    [[TMP4929:%.*]] = load double, ptr [[DX]], align 8
53520 // SIMD-ONLY0-NEXT:    [[CMP6375:%.*]] = fcmp oeq double [[TMP4928]], [[TMP4929]]
53521 // SIMD-ONLY0-NEXT:    br i1 [[CMP6375]], label [[IF_THEN6377:%.*]], label [[IF_END6378:%.*]]
53522 // SIMD-ONLY0:       if.then6377:
53523 // SIMD-ONLY0-NEXT:    [[TMP4930:%.*]] = load double, ptr [[DD]], align 8
53524 // SIMD-ONLY0-NEXT:    store double [[TMP4930]], ptr [[DX]], align 8
53525 // SIMD-ONLY0-NEXT:    br label [[IF_END6378]]
53526 // SIMD-ONLY0:       if.end6378:
53527 // SIMD-ONLY0-NEXT:    [[TMP4931:%.*]] = load double, ptr [[DX]], align 8
53528 // SIMD-ONLY0-NEXT:    store double [[TMP4931]], ptr [[DV]], align 8
53529 // SIMD-ONLY0-NEXT:    [[TMP4932:%.*]] = load double, ptr [[DX]], align 8
53530 // SIMD-ONLY0-NEXT:    [[TMP4933:%.*]] = load double, ptr [[DE]], align 8
53531 // SIMD-ONLY0-NEXT:    [[CMP6379:%.*]] = fcmp oeq double [[TMP4932]], [[TMP4933]]
53532 // SIMD-ONLY0-NEXT:    br i1 [[CMP6379]], label [[IF_THEN6381:%.*]], label [[IF_ELSE6382:%.*]]
53533 // SIMD-ONLY0:       if.then6381:
53534 // SIMD-ONLY0-NEXT:    [[TMP4934:%.*]] = load double, ptr [[DD]], align 8
53535 // SIMD-ONLY0-NEXT:    store double [[TMP4934]], ptr [[DX]], align 8
53536 // SIMD-ONLY0-NEXT:    br label [[IF_END6383:%.*]]
53537 // SIMD-ONLY0:       if.else6382:
53538 // SIMD-ONLY0-NEXT:    [[TMP4935:%.*]] = load double, ptr [[DX]], align 8
53539 // SIMD-ONLY0-NEXT:    store double [[TMP4935]], ptr [[DV]], align 8
53540 // SIMD-ONLY0-NEXT:    br label [[IF_END6383]]
53541 // SIMD-ONLY0:       if.end6383:
53542 // SIMD-ONLY0-NEXT:    [[TMP4936:%.*]] = load double, ptr [[DE]], align 8
53543 // SIMD-ONLY0-NEXT:    [[TMP4937:%.*]] = load double, ptr [[DX]], align 8
53544 // SIMD-ONLY0-NEXT:    [[CMP6384:%.*]] = fcmp oeq double [[TMP4936]], [[TMP4937]]
53545 // SIMD-ONLY0-NEXT:    br i1 [[CMP6384]], label [[IF_THEN6386:%.*]], label [[IF_ELSE6387:%.*]]
53546 // SIMD-ONLY0:       if.then6386:
53547 // SIMD-ONLY0-NEXT:    [[TMP4938:%.*]] = load double, ptr [[DD]], align 8
53548 // SIMD-ONLY0-NEXT:    store double [[TMP4938]], ptr [[DX]], align 8
53549 // SIMD-ONLY0-NEXT:    br label [[IF_END6388:%.*]]
53550 // SIMD-ONLY0:       if.else6387:
53551 // SIMD-ONLY0-NEXT:    [[TMP4939:%.*]] = load double, ptr [[DX]], align 8
53552 // SIMD-ONLY0-NEXT:    store double [[TMP4939]], ptr [[DV]], align 8
53553 // SIMD-ONLY0-NEXT:    br label [[IF_END6388]]
53554 // SIMD-ONLY0:       if.end6388:
53555 // SIMD-ONLY0-NEXT:    [[TMP4940:%.*]] = load double, ptr [[DX]], align 8
53556 // SIMD-ONLY0-NEXT:    [[TMP4941:%.*]] = load double, ptr [[DE]], align 8
53557 // SIMD-ONLY0-NEXT:    [[CMP6389:%.*]] = fcmp oeq double [[TMP4940]], [[TMP4941]]
53558 // SIMD-ONLY0-NEXT:    [[CONV6390:%.*]] = zext i1 [[CMP6389]] to i32
53559 // SIMD-ONLY0-NEXT:    store i32 [[CONV6390]], ptr [[IR]], align 4
53560 // SIMD-ONLY0-NEXT:    [[TMP4942:%.*]] = load i32, ptr [[IR]], align 4
53561 // SIMD-ONLY0-NEXT:    [[TOBOOL6391:%.*]] = icmp ne i32 [[TMP4942]], 0
53562 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6391]], label [[IF_THEN6392:%.*]], label [[IF_END6393:%.*]]
53563 // SIMD-ONLY0:       if.then6392:
53564 // SIMD-ONLY0-NEXT:    [[TMP4943:%.*]] = load double, ptr [[DD]], align 8
53565 // SIMD-ONLY0-NEXT:    store double [[TMP4943]], ptr [[DX]], align 8
53566 // SIMD-ONLY0-NEXT:    br label [[IF_END6393]]
53567 // SIMD-ONLY0:       if.end6393:
53568 // SIMD-ONLY0-NEXT:    [[TMP4944:%.*]] = load double, ptr [[DE]], align 8
53569 // SIMD-ONLY0-NEXT:    [[TMP4945:%.*]] = load double, ptr [[DX]], align 8
53570 // SIMD-ONLY0-NEXT:    [[CMP6394:%.*]] = fcmp oeq double [[TMP4944]], [[TMP4945]]
53571 // SIMD-ONLY0-NEXT:    [[CONV6395:%.*]] = zext i1 [[CMP6394]] to i32
53572 // SIMD-ONLY0-NEXT:    store i32 [[CONV6395]], ptr [[IR]], align 4
53573 // SIMD-ONLY0-NEXT:    [[TMP4946:%.*]] = load i32, ptr [[IR]], align 4
53574 // SIMD-ONLY0-NEXT:    [[TOBOOL6396:%.*]] = icmp ne i32 [[TMP4946]], 0
53575 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6396]], label [[IF_THEN6397:%.*]], label [[IF_END6398:%.*]]
53576 // SIMD-ONLY0:       if.then6397:
53577 // SIMD-ONLY0-NEXT:    [[TMP4947:%.*]] = load double, ptr [[DD]], align 8
53578 // SIMD-ONLY0-NEXT:    store double [[TMP4947]], ptr [[DX]], align 8
53579 // SIMD-ONLY0-NEXT:    br label [[IF_END6398]]
53580 // SIMD-ONLY0:       if.end6398:
53581 // SIMD-ONLY0-NEXT:    [[TMP4948:%.*]] = load double, ptr [[DX]], align 8
53582 // SIMD-ONLY0-NEXT:    [[TMP4949:%.*]] = load double, ptr [[DE]], align 8
53583 // SIMD-ONLY0-NEXT:    [[CMP6399:%.*]] = fcmp oeq double [[TMP4948]], [[TMP4949]]
53584 // SIMD-ONLY0-NEXT:    [[CONV6400:%.*]] = zext i1 [[CMP6399]] to i32
53585 // SIMD-ONLY0-NEXT:    store i32 [[CONV6400]], ptr [[IR]], align 4
53586 // SIMD-ONLY0-NEXT:    [[TMP4950:%.*]] = load i32, ptr [[IR]], align 4
53587 // SIMD-ONLY0-NEXT:    [[TOBOOL6401:%.*]] = icmp ne i32 [[TMP4950]], 0
53588 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6401]], label [[IF_THEN6402:%.*]], label [[IF_ELSE6403:%.*]]
53589 // SIMD-ONLY0:       if.then6402:
53590 // SIMD-ONLY0-NEXT:    [[TMP4951:%.*]] = load double, ptr [[DD]], align 8
53591 // SIMD-ONLY0-NEXT:    store double [[TMP4951]], ptr [[DX]], align 8
53592 // SIMD-ONLY0-NEXT:    br label [[IF_END6404:%.*]]
53593 // SIMD-ONLY0:       if.else6403:
53594 // SIMD-ONLY0-NEXT:    [[TMP4952:%.*]] = load double, ptr [[DX]], align 8
53595 // SIMD-ONLY0-NEXT:    store double [[TMP4952]], ptr [[DV]], align 8
53596 // SIMD-ONLY0-NEXT:    br label [[IF_END6404]]
53597 // SIMD-ONLY0:       if.end6404:
53598 // SIMD-ONLY0-NEXT:    [[TMP4953:%.*]] = load double, ptr [[DE]], align 8
53599 // SIMD-ONLY0-NEXT:    [[TMP4954:%.*]] = load double, ptr [[DX]], align 8
53600 // SIMD-ONLY0-NEXT:    [[CMP6405:%.*]] = fcmp oeq double [[TMP4953]], [[TMP4954]]
53601 // SIMD-ONLY0-NEXT:    [[CONV6406:%.*]] = zext i1 [[CMP6405]] to i32
53602 // SIMD-ONLY0-NEXT:    store i32 [[CONV6406]], ptr [[IR]], align 4
53603 // SIMD-ONLY0-NEXT:    [[TMP4955:%.*]] = load i32, ptr [[IR]], align 4
53604 // SIMD-ONLY0-NEXT:    [[TOBOOL6407:%.*]] = icmp ne i32 [[TMP4955]], 0
53605 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6407]], label [[IF_THEN6408:%.*]], label [[IF_ELSE6409:%.*]]
53606 // SIMD-ONLY0:       if.then6408:
53607 // SIMD-ONLY0-NEXT:    [[TMP4956:%.*]] = load double, ptr [[DD]], align 8
53608 // SIMD-ONLY0-NEXT:    store double [[TMP4956]], ptr [[DX]], align 8
53609 // SIMD-ONLY0-NEXT:    br label [[IF_END6410:%.*]]
53610 // SIMD-ONLY0:       if.else6409:
53611 // SIMD-ONLY0-NEXT:    [[TMP4957:%.*]] = load double, ptr [[DX]], align 8
53612 // SIMD-ONLY0-NEXT:    store double [[TMP4957]], ptr [[DV]], align 8
53613 // SIMD-ONLY0-NEXT:    br label [[IF_END6410]]
53614 // SIMD-ONLY0:       if.end6410:
53615 // SIMD-ONLY0-NEXT:    [[TMP4958:%.*]] = load double, ptr [[DX]], align 8
53616 // SIMD-ONLY0-NEXT:    store double [[TMP4958]], ptr [[DV]], align 8
53617 // SIMD-ONLY0-NEXT:    [[TMP4959:%.*]] = load double, ptr [[DE]], align 8
53618 // SIMD-ONLY0-NEXT:    [[TMP4960:%.*]] = load double, ptr [[DX]], align 8
53619 // SIMD-ONLY0-NEXT:    [[CMP6411:%.*]] = fcmp ogt double [[TMP4959]], [[TMP4960]]
53620 // SIMD-ONLY0-NEXT:    br i1 [[CMP6411]], label [[IF_THEN6413:%.*]], label [[IF_END6414:%.*]]
53621 // SIMD-ONLY0:       if.then6413:
53622 // SIMD-ONLY0-NEXT:    [[TMP4961:%.*]] = load double, ptr [[DE]], align 8
53623 // SIMD-ONLY0-NEXT:    store double [[TMP4961]], ptr [[DX]], align 8
53624 // SIMD-ONLY0-NEXT:    br label [[IF_END6414]]
53625 // SIMD-ONLY0:       if.end6414:
53626 // SIMD-ONLY0-NEXT:    [[TMP4962:%.*]] = load double, ptr [[DX]], align 8
53627 // SIMD-ONLY0-NEXT:    store double [[TMP4962]], ptr [[DV]], align 8
53628 // SIMD-ONLY0-NEXT:    [[TMP4963:%.*]] = load double, ptr [[DX]], align 8
53629 // SIMD-ONLY0-NEXT:    [[TMP4964:%.*]] = load double, ptr [[DE]], align 8
53630 // SIMD-ONLY0-NEXT:    [[CMP6415:%.*]] = fcmp ogt double [[TMP4963]], [[TMP4964]]
53631 // SIMD-ONLY0-NEXT:    br i1 [[CMP6415]], label [[IF_THEN6417:%.*]], label [[IF_END6418:%.*]]
53632 // SIMD-ONLY0:       if.then6417:
53633 // SIMD-ONLY0-NEXT:    [[TMP4965:%.*]] = load double, ptr [[DE]], align 8
53634 // SIMD-ONLY0-NEXT:    store double [[TMP4965]], ptr [[DX]], align 8
53635 // SIMD-ONLY0-NEXT:    br label [[IF_END6418]]
53636 // SIMD-ONLY0:       if.end6418:
53637 // SIMD-ONLY0-NEXT:    [[TMP4966:%.*]] = load double, ptr [[DX]], align 8
53638 // SIMD-ONLY0-NEXT:    store double [[TMP4966]], ptr [[DV]], align 8
53639 // SIMD-ONLY0-NEXT:    [[TMP4967:%.*]] = load double, ptr [[DE]], align 8
53640 // SIMD-ONLY0-NEXT:    [[TMP4968:%.*]] = load double, ptr [[DX]], align 8
53641 // SIMD-ONLY0-NEXT:    [[CMP6419:%.*]] = fcmp olt double [[TMP4967]], [[TMP4968]]
53642 // SIMD-ONLY0-NEXT:    br i1 [[CMP6419]], label [[IF_THEN6421:%.*]], label [[IF_END6422:%.*]]
53643 // SIMD-ONLY0:       if.then6421:
53644 // SIMD-ONLY0-NEXT:    [[TMP4969:%.*]] = load double, ptr [[DE]], align 8
53645 // SIMD-ONLY0-NEXT:    store double [[TMP4969]], ptr [[DX]], align 8
53646 // SIMD-ONLY0-NEXT:    br label [[IF_END6422]]
53647 // SIMD-ONLY0:       if.end6422:
53648 // SIMD-ONLY0-NEXT:    [[TMP4970:%.*]] = load double, ptr [[DX]], align 8
53649 // SIMD-ONLY0-NEXT:    store double [[TMP4970]], ptr [[DV]], align 8
53650 // SIMD-ONLY0-NEXT:    [[TMP4971:%.*]] = load double, ptr [[DX]], align 8
53651 // SIMD-ONLY0-NEXT:    [[TMP4972:%.*]] = load double, ptr [[DE]], align 8
53652 // SIMD-ONLY0-NEXT:    [[CMP6423:%.*]] = fcmp olt double [[TMP4971]], [[TMP4972]]
53653 // SIMD-ONLY0-NEXT:    br i1 [[CMP6423]], label [[IF_THEN6425:%.*]], label [[IF_END6426:%.*]]
53654 // SIMD-ONLY0:       if.then6425:
53655 // SIMD-ONLY0-NEXT:    [[TMP4973:%.*]] = load double, ptr [[DE]], align 8
53656 // SIMD-ONLY0-NEXT:    store double [[TMP4973]], ptr [[DX]], align 8
53657 // SIMD-ONLY0-NEXT:    br label [[IF_END6426]]
53658 // SIMD-ONLY0:       if.end6426:
53659 // SIMD-ONLY0-NEXT:    [[TMP4974:%.*]] = load double, ptr [[DX]], align 8
53660 // SIMD-ONLY0-NEXT:    store double [[TMP4974]], ptr [[DV]], align 8
53661 // SIMD-ONLY0-NEXT:    [[TMP4975:%.*]] = load double, ptr [[DX]], align 8
53662 // SIMD-ONLY0-NEXT:    [[TMP4976:%.*]] = load double, ptr [[DE]], align 8
53663 // SIMD-ONLY0-NEXT:    [[CMP6427:%.*]] = fcmp oeq double [[TMP4975]], [[TMP4976]]
53664 // SIMD-ONLY0-NEXT:    br i1 [[CMP6427]], label [[IF_THEN6429:%.*]], label [[IF_END6430:%.*]]
53665 // SIMD-ONLY0:       if.then6429:
53666 // SIMD-ONLY0-NEXT:    [[TMP4977:%.*]] = load double, ptr [[DD]], align 8
53667 // SIMD-ONLY0-NEXT:    store double [[TMP4977]], ptr [[DX]], align 8
53668 // SIMD-ONLY0-NEXT:    br label [[IF_END6430]]
53669 // SIMD-ONLY0:       if.end6430:
53670 // SIMD-ONLY0-NEXT:    [[TMP4978:%.*]] = load double, ptr [[DX]], align 8
53671 // SIMD-ONLY0-NEXT:    store double [[TMP4978]], ptr [[DV]], align 8
53672 // SIMD-ONLY0-NEXT:    [[TMP4979:%.*]] = load double, ptr [[DE]], align 8
53673 // SIMD-ONLY0-NEXT:    [[TMP4980:%.*]] = load double, ptr [[DX]], align 8
53674 // SIMD-ONLY0-NEXT:    [[CMP6431:%.*]] = fcmp oeq double [[TMP4979]], [[TMP4980]]
53675 // SIMD-ONLY0-NEXT:    br i1 [[CMP6431]], label [[IF_THEN6433:%.*]], label [[IF_END6434:%.*]]
53676 // SIMD-ONLY0:       if.then6433:
53677 // SIMD-ONLY0-NEXT:    [[TMP4981:%.*]] = load double, ptr [[DD]], align 8
53678 // SIMD-ONLY0-NEXT:    store double [[TMP4981]], ptr [[DX]], align 8
53679 // SIMD-ONLY0-NEXT:    br label [[IF_END6434]]
53680 // SIMD-ONLY0:       if.end6434:
53681 // SIMD-ONLY0-NEXT:    [[TMP4982:%.*]] = load double, ptr [[DE]], align 8
53682 // SIMD-ONLY0-NEXT:    [[TMP4983:%.*]] = load double, ptr [[DX]], align 8
53683 // SIMD-ONLY0-NEXT:    [[CMP6435:%.*]] = fcmp ogt double [[TMP4982]], [[TMP4983]]
53684 // SIMD-ONLY0-NEXT:    br i1 [[CMP6435]], label [[IF_THEN6437:%.*]], label [[IF_END6438:%.*]]
53685 // SIMD-ONLY0:       if.then6437:
53686 // SIMD-ONLY0-NEXT:    [[TMP4984:%.*]] = load double, ptr [[DE]], align 8
53687 // SIMD-ONLY0-NEXT:    store double [[TMP4984]], ptr [[DX]], align 8
53688 // SIMD-ONLY0-NEXT:    br label [[IF_END6438]]
53689 // SIMD-ONLY0:       if.end6438:
53690 // SIMD-ONLY0-NEXT:    [[TMP4985:%.*]] = load double, ptr [[DX]], align 8
53691 // SIMD-ONLY0-NEXT:    store double [[TMP4985]], ptr [[DV]], align 8
53692 // SIMD-ONLY0-NEXT:    [[TMP4986:%.*]] = load double, ptr [[DX]], align 8
53693 // SIMD-ONLY0-NEXT:    [[TMP4987:%.*]] = load double, ptr [[DE]], align 8
53694 // SIMD-ONLY0-NEXT:    [[CMP6439:%.*]] = fcmp ogt double [[TMP4986]], [[TMP4987]]
53695 // SIMD-ONLY0-NEXT:    br i1 [[CMP6439]], label [[IF_THEN6441:%.*]], label [[IF_END6442:%.*]]
53696 // SIMD-ONLY0:       if.then6441:
53697 // SIMD-ONLY0-NEXT:    [[TMP4988:%.*]] = load double, ptr [[DE]], align 8
53698 // SIMD-ONLY0-NEXT:    store double [[TMP4988]], ptr [[DX]], align 8
53699 // SIMD-ONLY0-NEXT:    br label [[IF_END6442]]
53700 // SIMD-ONLY0:       if.end6442:
53701 // SIMD-ONLY0-NEXT:    [[TMP4989:%.*]] = load double, ptr [[DX]], align 8
53702 // SIMD-ONLY0-NEXT:    store double [[TMP4989]], ptr [[DV]], align 8
53703 // SIMD-ONLY0-NEXT:    [[TMP4990:%.*]] = load double, ptr [[DE]], align 8
53704 // SIMD-ONLY0-NEXT:    [[TMP4991:%.*]] = load double, ptr [[DX]], align 8
53705 // SIMD-ONLY0-NEXT:    [[CMP6443:%.*]] = fcmp olt double [[TMP4990]], [[TMP4991]]
53706 // SIMD-ONLY0-NEXT:    br i1 [[CMP6443]], label [[IF_THEN6445:%.*]], label [[IF_END6446:%.*]]
53707 // SIMD-ONLY0:       if.then6445:
53708 // SIMD-ONLY0-NEXT:    [[TMP4992:%.*]] = load double, ptr [[DE]], align 8
53709 // SIMD-ONLY0-NEXT:    store double [[TMP4992]], ptr [[DX]], align 8
53710 // SIMD-ONLY0-NEXT:    br label [[IF_END6446]]
53711 // SIMD-ONLY0:       if.end6446:
53712 // SIMD-ONLY0-NEXT:    [[TMP4993:%.*]] = load double, ptr [[DX]], align 8
53713 // SIMD-ONLY0-NEXT:    store double [[TMP4993]], ptr [[DV]], align 8
53714 // SIMD-ONLY0-NEXT:    [[TMP4994:%.*]] = load double, ptr [[DX]], align 8
53715 // SIMD-ONLY0-NEXT:    [[TMP4995:%.*]] = load double, ptr [[DE]], align 8
53716 // SIMD-ONLY0-NEXT:    [[CMP6447:%.*]] = fcmp olt double [[TMP4994]], [[TMP4995]]
53717 // SIMD-ONLY0-NEXT:    br i1 [[CMP6447]], label [[IF_THEN6449:%.*]], label [[IF_END6450:%.*]]
53718 // SIMD-ONLY0:       if.then6449:
53719 // SIMD-ONLY0-NEXT:    [[TMP4996:%.*]] = load double, ptr [[DE]], align 8
53720 // SIMD-ONLY0-NEXT:    store double [[TMP4996]], ptr [[DX]], align 8
53721 // SIMD-ONLY0-NEXT:    br label [[IF_END6450]]
53722 // SIMD-ONLY0:       if.end6450:
53723 // SIMD-ONLY0-NEXT:    [[TMP4997:%.*]] = load double, ptr [[DX]], align 8
53724 // SIMD-ONLY0-NEXT:    store double [[TMP4997]], ptr [[DV]], align 8
53725 // SIMD-ONLY0-NEXT:    [[TMP4998:%.*]] = load double, ptr [[DX]], align 8
53726 // SIMD-ONLY0-NEXT:    [[TMP4999:%.*]] = load double, ptr [[DE]], align 8
53727 // SIMD-ONLY0-NEXT:    [[CMP6451:%.*]] = fcmp oeq double [[TMP4998]], [[TMP4999]]
53728 // SIMD-ONLY0-NEXT:    br i1 [[CMP6451]], label [[IF_THEN6453:%.*]], label [[IF_END6454:%.*]]
53729 // SIMD-ONLY0:       if.then6453:
53730 // SIMD-ONLY0-NEXT:    [[TMP5000:%.*]] = load double, ptr [[DD]], align 8
53731 // SIMD-ONLY0-NEXT:    store double [[TMP5000]], ptr [[DX]], align 8
53732 // SIMD-ONLY0-NEXT:    br label [[IF_END6454]]
53733 // SIMD-ONLY0:       if.end6454:
53734 // SIMD-ONLY0-NEXT:    [[TMP5001:%.*]] = load double, ptr [[DX]], align 8
53735 // SIMD-ONLY0-NEXT:    store double [[TMP5001]], ptr [[DV]], align 8
53736 // SIMD-ONLY0-NEXT:    [[TMP5002:%.*]] = load double, ptr [[DE]], align 8
53737 // SIMD-ONLY0-NEXT:    [[TMP5003:%.*]] = load double, ptr [[DX]], align 8
53738 // SIMD-ONLY0-NEXT:    [[CMP6455:%.*]] = fcmp oeq double [[TMP5002]], [[TMP5003]]
53739 // SIMD-ONLY0-NEXT:    br i1 [[CMP6455]], label [[IF_THEN6457:%.*]], label [[IF_END6458:%.*]]
53740 // SIMD-ONLY0:       if.then6457:
53741 // SIMD-ONLY0-NEXT:    [[TMP5004:%.*]] = load double, ptr [[DD]], align 8
53742 // SIMD-ONLY0-NEXT:    store double [[TMP5004]], ptr [[DX]], align 8
53743 // SIMD-ONLY0-NEXT:    br label [[IF_END6458]]
53744 // SIMD-ONLY0:       if.end6458:
53745 // SIMD-ONLY0-NEXT:    [[TMP5005:%.*]] = load double, ptr [[DX]], align 8
53746 // SIMD-ONLY0-NEXT:    store double [[TMP5005]], ptr [[DV]], align 8
53747 // SIMD-ONLY0-NEXT:    [[TMP5006:%.*]] = load double, ptr [[DX]], align 8
53748 // SIMD-ONLY0-NEXT:    [[TMP5007:%.*]] = load double, ptr [[DE]], align 8
53749 // SIMD-ONLY0-NEXT:    [[CMP6459:%.*]] = fcmp oeq double [[TMP5006]], [[TMP5007]]
53750 // SIMD-ONLY0-NEXT:    br i1 [[CMP6459]], label [[IF_THEN6461:%.*]], label [[IF_ELSE6462:%.*]]
53751 // SIMD-ONLY0:       if.then6461:
53752 // SIMD-ONLY0-NEXT:    [[TMP5008:%.*]] = load double, ptr [[DD]], align 8
53753 // SIMD-ONLY0-NEXT:    store double [[TMP5008]], ptr [[DX]], align 8
53754 // SIMD-ONLY0-NEXT:    br label [[IF_END6463:%.*]]
53755 // SIMD-ONLY0:       if.else6462:
53756 // SIMD-ONLY0-NEXT:    [[TMP5009:%.*]] = load double, ptr [[DX]], align 8
53757 // SIMD-ONLY0-NEXT:    store double [[TMP5009]], ptr [[DV]], align 8
53758 // SIMD-ONLY0-NEXT:    br label [[IF_END6463]]
53759 // SIMD-ONLY0:       if.end6463:
53760 // SIMD-ONLY0-NEXT:    [[TMP5010:%.*]] = load double, ptr [[DE]], align 8
53761 // SIMD-ONLY0-NEXT:    [[TMP5011:%.*]] = load double, ptr [[DX]], align 8
53762 // SIMD-ONLY0-NEXT:    [[CMP6464:%.*]] = fcmp oeq double [[TMP5010]], [[TMP5011]]
53763 // SIMD-ONLY0-NEXT:    br i1 [[CMP6464]], label [[IF_THEN6466:%.*]], label [[IF_ELSE6467:%.*]]
53764 // SIMD-ONLY0:       if.then6466:
53765 // SIMD-ONLY0-NEXT:    [[TMP5012:%.*]] = load double, ptr [[DD]], align 8
53766 // SIMD-ONLY0-NEXT:    store double [[TMP5012]], ptr [[DX]], align 8
53767 // SIMD-ONLY0-NEXT:    br label [[IF_END6468:%.*]]
53768 // SIMD-ONLY0:       if.else6467:
53769 // SIMD-ONLY0-NEXT:    [[TMP5013:%.*]] = load double, ptr [[DX]], align 8
53770 // SIMD-ONLY0-NEXT:    store double [[TMP5013]], ptr [[DV]], align 8
53771 // SIMD-ONLY0-NEXT:    br label [[IF_END6468]]
53772 // SIMD-ONLY0:       if.end6468:
53773 // SIMD-ONLY0-NEXT:    [[TMP5014:%.*]] = load double, ptr [[DX]], align 8
53774 // SIMD-ONLY0-NEXT:    [[TMP5015:%.*]] = load double, ptr [[DE]], align 8
53775 // SIMD-ONLY0-NEXT:    [[CMP6469:%.*]] = fcmp oeq double [[TMP5014]], [[TMP5015]]
53776 // SIMD-ONLY0-NEXT:    [[CONV6470:%.*]] = zext i1 [[CMP6469]] to i32
53777 // SIMD-ONLY0-NEXT:    store i32 [[CONV6470]], ptr [[IR]], align 4
53778 // SIMD-ONLY0-NEXT:    [[TMP5016:%.*]] = load i32, ptr [[IR]], align 4
53779 // SIMD-ONLY0-NEXT:    [[TOBOOL6471:%.*]] = icmp ne i32 [[TMP5016]], 0
53780 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6471]], label [[IF_THEN6472:%.*]], label [[IF_END6473:%.*]]
53781 // SIMD-ONLY0:       if.then6472:
53782 // SIMD-ONLY0-NEXT:    [[TMP5017:%.*]] = load double, ptr [[DD]], align 8
53783 // SIMD-ONLY0-NEXT:    store double [[TMP5017]], ptr [[DX]], align 8
53784 // SIMD-ONLY0-NEXT:    br label [[IF_END6473]]
53785 // SIMD-ONLY0:       if.end6473:
53786 // SIMD-ONLY0-NEXT:    [[TMP5018:%.*]] = load double, ptr [[DE]], align 8
53787 // SIMD-ONLY0-NEXT:    [[TMP5019:%.*]] = load double, ptr [[DX]], align 8
53788 // SIMD-ONLY0-NEXT:    [[CMP6474:%.*]] = fcmp oeq double [[TMP5018]], [[TMP5019]]
53789 // SIMD-ONLY0-NEXT:    [[CONV6475:%.*]] = zext i1 [[CMP6474]] to i32
53790 // SIMD-ONLY0-NEXT:    store i32 [[CONV6475]], ptr [[IR]], align 4
53791 // SIMD-ONLY0-NEXT:    [[TMP5020:%.*]] = load i32, ptr [[IR]], align 4
53792 // SIMD-ONLY0-NEXT:    [[TOBOOL6476:%.*]] = icmp ne i32 [[TMP5020]], 0
53793 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6476]], label [[IF_THEN6477:%.*]], label [[IF_END6478:%.*]]
53794 // SIMD-ONLY0:       if.then6477:
53795 // SIMD-ONLY0-NEXT:    [[TMP5021:%.*]] = load double, ptr [[DD]], align 8
53796 // SIMD-ONLY0-NEXT:    store double [[TMP5021]], ptr [[DX]], align 8
53797 // SIMD-ONLY0-NEXT:    br label [[IF_END6478]]
53798 // SIMD-ONLY0:       if.end6478:
53799 // SIMD-ONLY0-NEXT:    [[TMP5022:%.*]] = load double, ptr [[DX]], align 8
53800 // SIMD-ONLY0-NEXT:    [[TMP5023:%.*]] = load double, ptr [[DE]], align 8
53801 // SIMD-ONLY0-NEXT:    [[CMP6479:%.*]] = fcmp oeq double [[TMP5022]], [[TMP5023]]
53802 // SIMD-ONLY0-NEXT:    [[CONV6480:%.*]] = zext i1 [[CMP6479]] to i32
53803 // SIMD-ONLY0-NEXT:    store i32 [[CONV6480]], ptr [[IR]], align 4
53804 // SIMD-ONLY0-NEXT:    [[TMP5024:%.*]] = load i32, ptr [[IR]], align 4
53805 // SIMD-ONLY0-NEXT:    [[TOBOOL6481:%.*]] = icmp ne i32 [[TMP5024]], 0
53806 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6481]], label [[IF_THEN6482:%.*]], label [[IF_ELSE6483:%.*]]
53807 // SIMD-ONLY0:       if.then6482:
53808 // SIMD-ONLY0-NEXT:    [[TMP5025:%.*]] = load double, ptr [[DD]], align 8
53809 // SIMD-ONLY0-NEXT:    store double [[TMP5025]], ptr [[DX]], align 8
53810 // SIMD-ONLY0-NEXT:    br label [[IF_END6484:%.*]]
53811 // SIMD-ONLY0:       if.else6483:
53812 // SIMD-ONLY0-NEXT:    [[TMP5026:%.*]] = load double, ptr [[DX]], align 8
53813 // SIMD-ONLY0-NEXT:    store double [[TMP5026]], ptr [[DV]], align 8
53814 // SIMD-ONLY0-NEXT:    br label [[IF_END6484]]
53815 // SIMD-ONLY0:       if.end6484:
53816 // SIMD-ONLY0-NEXT:    [[TMP5027:%.*]] = load double, ptr [[DE]], align 8
53817 // SIMD-ONLY0-NEXT:    [[TMP5028:%.*]] = load double, ptr [[DX]], align 8
53818 // SIMD-ONLY0-NEXT:    [[CMP6485:%.*]] = fcmp oeq double [[TMP5027]], [[TMP5028]]
53819 // SIMD-ONLY0-NEXT:    [[CONV6486:%.*]] = zext i1 [[CMP6485]] to i32
53820 // SIMD-ONLY0-NEXT:    store i32 [[CONV6486]], ptr [[IR]], align 4
53821 // SIMD-ONLY0-NEXT:    [[TMP5029:%.*]] = load i32, ptr [[IR]], align 4
53822 // SIMD-ONLY0-NEXT:    [[TOBOOL6487:%.*]] = icmp ne i32 [[TMP5029]], 0
53823 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6487]], label [[IF_THEN6488:%.*]], label [[IF_ELSE6489:%.*]]
53824 // SIMD-ONLY0:       if.then6488:
53825 // SIMD-ONLY0-NEXT:    [[TMP5030:%.*]] = load double, ptr [[DD]], align 8
53826 // SIMD-ONLY0-NEXT:    store double [[TMP5030]], ptr [[DX]], align 8
53827 // SIMD-ONLY0-NEXT:    br label [[IF_END6490:%.*]]
53828 // SIMD-ONLY0:       if.else6489:
53829 // SIMD-ONLY0-NEXT:    [[TMP5031:%.*]] = load double, ptr [[DX]], align 8
53830 // SIMD-ONLY0-NEXT:    store double [[TMP5031]], ptr [[DV]], align 8
53831 // SIMD-ONLY0-NEXT:    br label [[IF_END6490]]
53832 // SIMD-ONLY0:       if.end6490:
53833 // SIMD-ONLY0-NEXT:    [[TMP5032:%.*]] = load double, ptr [[DX]], align 8
53834 // SIMD-ONLY0-NEXT:    store double [[TMP5032]], ptr [[DV]], align 8
53835 // SIMD-ONLY0-NEXT:    [[TMP5033:%.*]] = load double, ptr [[DE]], align 8
53836 // SIMD-ONLY0-NEXT:    [[TMP5034:%.*]] = load double, ptr [[DX]], align 8
53837 // SIMD-ONLY0-NEXT:    [[CMP6491:%.*]] = fcmp ogt double [[TMP5033]], [[TMP5034]]
53838 // SIMD-ONLY0-NEXT:    br i1 [[CMP6491]], label [[IF_THEN6493:%.*]], label [[IF_END6494:%.*]]
53839 // SIMD-ONLY0:       if.then6493:
53840 // SIMD-ONLY0-NEXT:    [[TMP5035:%.*]] = load double, ptr [[DE]], align 8
53841 // SIMD-ONLY0-NEXT:    store double [[TMP5035]], ptr [[DX]], align 8
53842 // SIMD-ONLY0-NEXT:    br label [[IF_END6494]]
53843 // SIMD-ONLY0:       if.end6494:
53844 // SIMD-ONLY0-NEXT:    [[TMP5036:%.*]] = load double, ptr [[DX]], align 8
53845 // SIMD-ONLY0-NEXT:    store double [[TMP5036]], ptr [[DV]], align 8
53846 // SIMD-ONLY0-NEXT:    [[TMP5037:%.*]] = load double, ptr [[DX]], align 8
53847 // SIMD-ONLY0-NEXT:    [[TMP5038:%.*]] = load double, ptr [[DE]], align 8
53848 // SIMD-ONLY0-NEXT:    [[CMP6495:%.*]] = fcmp ogt double [[TMP5037]], [[TMP5038]]
53849 // SIMD-ONLY0-NEXT:    br i1 [[CMP6495]], label [[IF_THEN6497:%.*]], label [[IF_END6498:%.*]]
53850 // SIMD-ONLY0:       if.then6497:
53851 // SIMD-ONLY0-NEXT:    [[TMP5039:%.*]] = load double, ptr [[DE]], align 8
53852 // SIMD-ONLY0-NEXT:    store double [[TMP5039]], ptr [[DX]], align 8
53853 // SIMD-ONLY0-NEXT:    br label [[IF_END6498]]
53854 // SIMD-ONLY0:       if.end6498:
53855 // SIMD-ONLY0-NEXT:    [[TMP5040:%.*]] = load double, ptr [[DX]], align 8
53856 // SIMD-ONLY0-NEXT:    store double [[TMP5040]], ptr [[DV]], align 8
53857 // SIMD-ONLY0-NEXT:    [[TMP5041:%.*]] = load double, ptr [[DE]], align 8
53858 // SIMD-ONLY0-NEXT:    [[TMP5042:%.*]] = load double, ptr [[DX]], align 8
53859 // SIMD-ONLY0-NEXT:    [[CMP6499:%.*]] = fcmp olt double [[TMP5041]], [[TMP5042]]
53860 // SIMD-ONLY0-NEXT:    br i1 [[CMP6499]], label [[IF_THEN6501:%.*]], label [[IF_END6502:%.*]]
53861 // SIMD-ONLY0:       if.then6501:
53862 // SIMD-ONLY0-NEXT:    [[TMP5043:%.*]] = load double, ptr [[DE]], align 8
53863 // SIMD-ONLY0-NEXT:    store double [[TMP5043]], ptr [[DX]], align 8
53864 // SIMD-ONLY0-NEXT:    br label [[IF_END6502]]
53865 // SIMD-ONLY0:       if.end6502:
53866 // SIMD-ONLY0-NEXT:    [[TMP5044:%.*]] = load double, ptr [[DX]], align 8
53867 // SIMD-ONLY0-NEXT:    store double [[TMP5044]], ptr [[DV]], align 8
53868 // SIMD-ONLY0-NEXT:    [[TMP5045:%.*]] = load double, ptr [[DX]], align 8
53869 // SIMD-ONLY0-NEXT:    [[TMP5046:%.*]] = load double, ptr [[DE]], align 8
53870 // SIMD-ONLY0-NEXT:    [[CMP6503:%.*]] = fcmp olt double [[TMP5045]], [[TMP5046]]
53871 // SIMD-ONLY0-NEXT:    br i1 [[CMP6503]], label [[IF_THEN6505:%.*]], label [[IF_END6506:%.*]]
53872 // SIMD-ONLY0:       if.then6505:
53873 // SIMD-ONLY0-NEXT:    [[TMP5047:%.*]] = load double, ptr [[DE]], align 8
53874 // SIMD-ONLY0-NEXT:    store double [[TMP5047]], ptr [[DX]], align 8
53875 // SIMD-ONLY0-NEXT:    br label [[IF_END6506]]
53876 // SIMD-ONLY0:       if.end6506:
53877 // SIMD-ONLY0-NEXT:    [[TMP5048:%.*]] = load double, ptr [[DX]], align 8
53878 // SIMD-ONLY0-NEXT:    store double [[TMP5048]], ptr [[DV]], align 8
53879 // SIMD-ONLY0-NEXT:    [[TMP5049:%.*]] = load double, ptr [[DX]], align 8
53880 // SIMD-ONLY0-NEXT:    [[TMP5050:%.*]] = load double, ptr [[DE]], align 8
53881 // SIMD-ONLY0-NEXT:    [[CMP6507:%.*]] = fcmp oeq double [[TMP5049]], [[TMP5050]]
53882 // SIMD-ONLY0-NEXT:    br i1 [[CMP6507]], label [[IF_THEN6509:%.*]], label [[IF_END6510:%.*]]
53883 // SIMD-ONLY0:       if.then6509:
53884 // SIMD-ONLY0-NEXT:    [[TMP5051:%.*]] = load double, ptr [[DD]], align 8
53885 // SIMD-ONLY0-NEXT:    store double [[TMP5051]], ptr [[DX]], align 8
53886 // SIMD-ONLY0-NEXT:    br label [[IF_END6510]]
53887 // SIMD-ONLY0:       if.end6510:
53888 // SIMD-ONLY0-NEXT:    [[TMP5052:%.*]] = load double, ptr [[DX]], align 8
53889 // SIMD-ONLY0-NEXT:    store double [[TMP5052]], ptr [[DV]], align 8
53890 // SIMD-ONLY0-NEXT:    [[TMP5053:%.*]] = load double, ptr [[DE]], align 8
53891 // SIMD-ONLY0-NEXT:    [[TMP5054:%.*]] = load double, ptr [[DX]], align 8
53892 // SIMD-ONLY0-NEXT:    [[CMP6511:%.*]] = fcmp oeq double [[TMP5053]], [[TMP5054]]
53893 // SIMD-ONLY0-NEXT:    br i1 [[CMP6511]], label [[IF_THEN6513:%.*]], label [[IF_END6514:%.*]]
53894 // SIMD-ONLY0:       if.then6513:
53895 // SIMD-ONLY0-NEXT:    [[TMP5055:%.*]] = load double, ptr [[DD]], align 8
53896 // SIMD-ONLY0-NEXT:    store double [[TMP5055]], ptr [[DX]], align 8
53897 // SIMD-ONLY0-NEXT:    br label [[IF_END6514]]
53898 // SIMD-ONLY0:       if.end6514:
53899 // SIMD-ONLY0-NEXT:    [[TMP5056:%.*]] = load double, ptr [[DE]], align 8
53900 // SIMD-ONLY0-NEXT:    [[TMP5057:%.*]] = load double, ptr [[DX]], align 8
53901 // SIMD-ONLY0-NEXT:    [[CMP6515:%.*]] = fcmp ogt double [[TMP5056]], [[TMP5057]]
53902 // SIMD-ONLY0-NEXT:    br i1 [[CMP6515]], label [[IF_THEN6517:%.*]], label [[IF_END6518:%.*]]
53903 // SIMD-ONLY0:       if.then6517:
53904 // SIMD-ONLY0-NEXT:    [[TMP5058:%.*]] = load double, ptr [[DE]], align 8
53905 // SIMD-ONLY0-NEXT:    store double [[TMP5058]], ptr [[DX]], align 8
53906 // SIMD-ONLY0-NEXT:    br label [[IF_END6518]]
53907 // SIMD-ONLY0:       if.end6518:
53908 // SIMD-ONLY0-NEXT:    [[TMP5059:%.*]] = load double, ptr [[DX]], align 8
53909 // SIMD-ONLY0-NEXT:    store double [[TMP5059]], ptr [[DV]], align 8
53910 // SIMD-ONLY0-NEXT:    [[TMP5060:%.*]] = load double, ptr [[DX]], align 8
53911 // SIMD-ONLY0-NEXT:    [[TMP5061:%.*]] = load double, ptr [[DE]], align 8
53912 // SIMD-ONLY0-NEXT:    [[CMP6519:%.*]] = fcmp ogt double [[TMP5060]], [[TMP5061]]
53913 // SIMD-ONLY0-NEXT:    br i1 [[CMP6519]], label [[IF_THEN6521:%.*]], label [[IF_END6522:%.*]]
53914 // SIMD-ONLY0:       if.then6521:
53915 // SIMD-ONLY0-NEXT:    [[TMP5062:%.*]] = load double, ptr [[DE]], align 8
53916 // SIMD-ONLY0-NEXT:    store double [[TMP5062]], ptr [[DX]], align 8
53917 // SIMD-ONLY0-NEXT:    br label [[IF_END6522]]
53918 // SIMD-ONLY0:       if.end6522:
53919 // SIMD-ONLY0-NEXT:    [[TMP5063:%.*]] = load double, ptr [[DX]], align 8
53920 // SIMD-ONLY0-NEXT:    store double [[TMP5063]], ptr [[DV]], align 8
53921 // SIMD-ONLY0-NEXT:    [[TMP5064:%.*]] = load double, ptr [[DE]], align 8
53922 // SIMD-ONLY0-NEXT:    [[TMP5065:%.*]] = load double, ptr [[DX]], align 8
53923 // SIMD-ONLY0-NEXT:    [[CMP6523:%.*]] = fcmp olt double [[TMP5064]], [[TMP5065]]
53924 // SIMD-ONLY0-NEXT:    br i1 [[CMP6523]], label [[IF_THEN6525:%.*]], label [[IF_END6526:%.*]]
53925 // SIMD-ONLY0:       if.then6525:
53926 // SIMD-ONLY0-NEXT:    [[TMP5066:%.*]] = load double, ptr [[DE]], align 8
53927 // SIMD-ONLY0-NEXT:    store double [[TMP5066]], ptr [[DX]], align 8
53928 // SIMD-ONLY0-NEXT:    br label [[IF_END6526]]
53929 // SIMD-ONLY0:       if.end6526:
53930 // SIMD-ONLY0-NEXT:    [[TMP5067:%.*]] = load double, ptr [[DX]], align 8
53931 // SIMD-ONLY0-NEXT:    store double [[TMP5067]], ptr [[DV]], align 8
53932 // SIMD-ONLY0-NEXT:    [[TMP5068:%.*]] = load double, ptr [[DX]], align 8
53933 // SIMD-ONLY0-NEXT:    [[TMP5069:%.*]] = load double, ptr [[DE]], align 8
53934 // SIMD-ONLY0-NEXT:    [[CMP6527:%.*]] = fcmp olt double [[TMP5068]], [[TMP5069]]
53935 // SIMD-ONLY0-NEXT:    br i1 [[CMP6527]], label [[IF_THEN6529:%.*]], label [[IF_END6530:%.*]]
53936 // SIMD-ONLY0:       if.then6529:
53937 // SIMD-ONLY0-NEXT:    [[TMP5070:%.*]] = load double, ptr [[DE]], align 8
53938 // SIMD-ONLY0-NEXT:    store double [[TMP5070]], ptr [[DX]], align 8
53939 // SIMD-ONLY0-NEXT:    br label [[IF_END6530]]
53940 // SIMD-ONLY0:       if.end6530:
53941 // SIMD-ONLY0-NEXT:    [[TMP5071:%.*]] = load double, ptr [[DX]], align 8
53942 // SIMD-ONLY0-NEXT:    store double [[TMP5071]], ptr [[DV]], align 8
53943 // SIMD-ONLY0-NEXT:    [[TMP5072:%.*]] = load double, ptr [[DX]], align 8
53944 // SIMD-ONLY0-NEXT:    [[TMP5073:%.*]] = load double, ptr [[DE]], align 8
53945 // SIMD-ONLY0-NEXT:    [[CMP6531:%.*]] = fcmp oeq double [[TMP5072]], [[TMP5073]]
53946 // SIMD-ONLY0-NEXT:    br i1 [[CMP6531]], label [[IF_THEN6533:%.*]], label [[IF_END6534:%.*]]
53947 // SIMD-ONLY0:       if.then6533:
53948 // SIMD-ONLY0-NEXT:    [[TMP5074:%.*]] = load double, ptr [[DD]], align 8
53949 // SIMD-ONLY0-NEXT:    store double [[TMP5074]], ptr [[DX]], align 8
53950 // SIMD-ONLY0-NEXT:    br label [[IF_END6534]]
53951 // SIMD-ONLY0:       if.end6534:
53952 // SIMD-ONLY0-NEXT:    [[TMP5075:%.*]] = load double, ptr [[DX]], align 8
53953 // SIMD-ONLY0-NEXT:    store double [[TMP5075]], ptr [[DV]], align 8
53954 // SIMD-ONLY0-NEXT:    [[TMP5076:%.*]] = load double, ptr [[DE]], align 8
53955 // SIMD-ONLY0-NEXT:    [[TMP5077:%.*]] = load double, ptr [[DX]], align 8
53956 // SIMD-ONLY0-NEXT:    [[CMP6535:%.*]] = fcmp oeq double [[TMP5076]], [[TMP5077]]
53957 // SIMD-ONLY0-NEXT:    br i1 [[CMP6535]], label [[IF_THEN6537:%.*]], label [[IF_END6538:%.*]]
53958 // SIMD-ONLY0:       if.then6537:
53959 // SIMD-ONLY0-NEXT:    [[TMP5078:%.*]] = load double, ptr [[DD]], align 8
53960 // SIMD-ONLY0-NEXT:    store double [[TMP5078]], ptr [[DX]], align 8
53961 // SIMD-ONLY0-NEXT:    br label [[IF_END6538]]
53962 // SIMD-ONLY0:       if.end6538:
53963 // SIMD-ONLY0-NEXT:    [[TMP5079:%.*]] = load double, ptr [[DX]], align 8
53964 // SIMD-ONLY0-NEXT:    store double [[TMP5079]], ptr [[DV]], align 8
53965 // SIMD-ONLY0-NEXT:    [[TMP5080:%.*]] = load double, ptr [[DX]], align 8
53966 // SIMD-ONLY0-NEXT:    [[TMP5081:%.*]] = load double, ptr [[DE]], align 8
53967 // SIMD-ONLY0-NEXT:    [[CMP6539:%.*]] = fcmp oeq double [[TMP5080]], [[TMP5081]]
53968 // SIMD-ONLY0-NEXT:    br i1 [[CMP6539]], label [[IF_THEN6541:%.*]], label [[IF_ELSE6542:%.*]]
53969 // SIMD-ONLY0:       if.then6541:
53970 // SIMD-ONLY0-NEXT:    [[TMP5082:%.*]] = load double, ptr [[DD]], align 8
53971 // SIMD-ONLY0-NEXT:    store double [[TMP5082]], ptr [[DX]], align 8
53972 // SIMD-ONLY0-NEXT:    br label [[IF_END6543:%.*]]
53973 // SIMD-ONLY0:       if.else6542:
53974 // SIMD-ONLY0-NEXT:    [[TMP5083:%.*]] = load double, ptr [[DX]], align 8
53975 // SIMD-ONLY0-NEXT:    store double [[TMP5083]], ptr [[DV]], align 8
53976 // SIMD-ONLY0-NEXT:    br label [[IF_END6543]]
53977 // SIMD-ONLY0:       if.end6543:
53978 // SIMD-ONLY0-NEXT:    [[TMP5084:%.*]] = load double, ptr [[DE]], align 8
53979 // SIMD-ONLY0-NEXT:    [[TMP5085:%.*]] = load double, ptr [[DX]], align 8
53980 // SIMD-ONLY0-NEXT:    [[CMP6544:%.*]] = fcmp oeq double [[TMP5084]], [[TMP5085]]
53981 // SIMD-ONLY0-NEXT:    br i1 [[CMP6544]], label [[IF_THEN6546:%.*]], label [[IF_ELSE6547:%.*]]
53982 // SIMD-ONLY0:       if.then6546:
53983 // SIMD-ONLY0-NEXT:    [[TMP5086:%.*]] = load double, ptr [[DD]], align 8
53984 // SIMD-ONLY0-NEXT:    store double [[TMP5086]], ptr [[DX]], align 8
53985 // SIMD-ONLY0-NEXT:    br label [[IF_END6548:%.*]]
53986 // SIMD-ONLY0:       if.else6547:
53987 // SIMD-ONLY0-NEXT:    [[TMP5087:%.*]] = load double, ptr [[DX]], align 8
53988 // SIMD-ONLY0-NEXT:    store double [[TMP5087]], ptr [[DV]], align 8
53989 // SIMD-ONLY0-NEXT:    br label [[IF_END6548]]
53990 // SIMD-ONLY0:       if.end6548:
53991 // SIMD-ONLY0-NEXT:    [[TMP5088:%.*]] = load double, ptr [[DX]], align 8
53992 // SIMD-ONLY0-NEXT:    [[TMP5089:%.*]] = load double, ptr [[DE]], align 8
53993 // SIMD-ONLY0-NEXT:    [[CMP6549:%.*]] = fcmp oeq double [[TMP5088]], [[TMP5089]]
53994 // SIMD-ONLY0-NEXT:    [[CONV6550:%.*]] = zext i1 [[CMP6549]] to i32
53995 // SIMD-ONLY0-NEXT:    store i32 [[CONV6550]], ptr [[IR]], align 4
53996 // SIMD-ONLY0-NEXT:    [[TMP5090:%.*]] = load i32, ptr [[IR]], align 4
53997 // SIMD-ONLY0-NEXT:    [[TOBOOL6551:%.*]] = icmp ne i32 [[TMP5090]], 0
53998 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6551]], label [[IF_THEN6552:%.*]], label [[IF_END6553:%.*]]
53999 // SIMD-ONLY0:       if.then6552:
54000 // SIMD-ONLY0-NEXT:    [[TMP5091:%.*]] = load double, ptr [[DD]], align 8
54001 // SIMD-ONLY0-NEXT:    store double [[TMP5091]], ptr [[DX]], align 8
54002 // SIMD-ONLY0-NEXT:    br label [[IF_END6553]]
54003 // SIMD-ONLY0:       if.end6553:
54004 // SIMD-ONLY0-NEXT:    [[TMP5092:%.*]] = load double, ptr [[DE]], align 8
54005 // SIMD-ONLY0-NEXT:    [[TMP5093:%.*]] = load double, ptr [[DX]], align 8
54006 // SIMD-ONLY0-NEXT:    [[CMP6554:%.*]] = fcmp oeq double [[TMP5092]], [[TMP5093]]
54007 // SIMD-ONLY0-NEXT:    [[CONV6555:%.*]] = zext i1 [[CMP6554]] to i32
54008 // SIMD-ONLY0-NEXT:    store i32 [[CONV6555]], ptr [[IR]], align 4
54009 // SIMD-ONLY0-NEXT:    [[TMP5094:%.*]] = load i32, ptr [[IR]], align 4
54010 // SIMD-ONLY0-NEXT:    [[TOBOOL6556:%.*]] = icmp ne i32 [[TMP5094]], 0
54011 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6556]], label [[IF_THEN6557:%.*]], label [[IF_END6558:%.*]]
54012 // SIMD-ONLY0:       if.then6557:
54013 // SIMD-ONLY0-NEXT:    [[TMP5095:%.*]] = load double, ptr [[DD]], align 8
54014 // SIMD-ONLY0-NEXT:    store double [[TMP5095]], ptr [[DX]], align 8
54015 // SIMD-ONLY0-NEXT:    br label [[IF_END6558]]
54016 // SIMD-ONLY0:       if.end6558:
54017 // SIMD-ONLY0-NEXT:    [[TMP5096:%.*]] = load double, ptr [[DX]], align 8
54018 // SIMD-ONLY0-NEXT:    [[TMP5097:%.*]] = load double, ptr [[DE]], align 8
54019 // SIMD-ONLY0-NEXT:    [[CMP6559:%.*]] = fcmp oeq double [[TMP5096]], [[TMP5097]]
54020 // SIMD-ONLY0-NEXT:    [[CONV6560:%.*]] = zext i1 [[CMP6559]] to i32
54021 // SIMD-ONLY0-NEXT:    store i32 [[CONV6560]], ptr [[IR]], align 4
54022 // SIMD-ONLY0-NEXT:    [[TMP5098:%.*]] = load i32, ptr [[IR]], align 4
54023 // SIMD-ONLY0-NEXT:    [[TOBOOL6561:%.*]] = icmp ne i32 [[TMP5098]], 0
54024 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6561]], label [[IF_THEN6562:%.*]], label [[IF_ELSE6563:%.*]]
54025 // SIMD-ONLY0:       if.then6562:
54026 // SIMD-ONLY0-NEXT:    [[TMP5099:%.*]] = load double, ptr [[DD]], align 8
54027 // SIMD-ONLY0-NEXT:    store double [[TMP5099]], ptr [[DX]], align 8
54028 // SIMD-ONLY0-NEXT:    br label [[IF_END6564:%.*]]
54029 // SIMD-ONLY0:       if.else6563:
54030 // SIMD-ONLY0-NEXT:    [[TMP5100:%.*]] = load double, ptr [[DX]], align 8
54031 // SIMD-ONLY0-NEXT:    store double [[TMP5100]], ptr [[DV]], align 8
54032 // SIMD-ONLY0-NEXT:    br label [[IF_END6564]]
54033 // SIMD-ONLY0:       if.end6564:
54034 // SIMD-ONLY0-NEXT:    [[TMP5101:%.*]] = load double, ptr [[DE]], align 8
54035 // SIMD-ONLY0-NEXT:    [[TMP5102:%.*]] = load double, ptr [[DX]], align 8
54036 // SIMD-ONLY0-NEXT:    [[CMP6565:%.*]] = fcmp oeq double [[TMP5101]], [[TMP5102]]
54037 // SIMD-ONLY0-NEXT:    [[CONV6566:%.*]] = zext i1 [[CMP6565]] to i32
54038 // SIMD-ONLY0-NEXT:    store i32 [[CONV6566]], ptr [[IR]], align 4
54039 // SIMD-ONLY0-NEXT:    [[TMP5103:%.*]] = load i32, ptr [[IR]], align 4
54040 // SIMD-ONLY0-NEXT:    [[TOBOOL6567:%.*]] = icmp ne i32 [[TMP5103]], 0
54041 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6567]], label [[IF_THEN6568:%.*]], label [[IF_ELSE6569:%.*]]
54042 // SIMD-ONLY0:       if.then6568:
54043 // SIMD-ONLY0-NEXT:    [[TMP5104:%.*]] = load double, ptr [[DD]], align 8
54044 // SIMD-ONLY0-NEXT:    store double [[TMP5104]], ptr [[DX]], align 8
54045 // SIMD-ONLY0-NEXT:    br label [[IF_END6570:%.*]]
54046 // SIMD-ONLY0:       if.else6569:
54047 // SIMD-ONLY0-NEXT:    [[TMP5105:%.*]] = load double, ptr [[DX]], align 8
54048 // SIMD-ONLY0-NEXT:    store double [[TMP5105]], ptr [[DV]], align 8
54049 // SIMD-ONLY0-NEXT:    br label [[IF_END6570]]
54050 // SIMD-ONLY0:       if.end6570:
54051 // SIMD-ONLY0-NEXT:    [[TMP5106:%.*]] = load double, ptr [[DX]], align 8
54052 // SIMD-ONLY0-NEXT:    store double [[TMP5106]], ptr [[DV]], align 8
54053 // SIMD-ONLY0-NEXT:    [[TMP5107:%.*]] = load double, ptr [[DE]], align 8
54054 // SIMD-ONLY0-NEXT:    [[TMP5108:%.*]] = load double, ptr [[DX]], align 8
54055 // SIMD-ONLY0-NEXT:    [[CMP6571:%.*]] = fcmp ogt double [[TMP5107]], [[TMP5108]]
54056 // SIMD-ONLY0-NEXT:    br i1 [[CMP6571]], label [[IF_THEN6573:%.*]], label [[IF_END6574:%.*]]
54057 // SIMD-ONLY0:       if.then6573:
54058 // SIMD-ONLY0-NEXT:    [[TMP5109:%.*]] = load double, ptr [[DE]], align 8
54059 // SIMD-ONLY0-NEXT:    store double [[TMP5109]], ptr [[DX]], align 8
54060 // SIMD-ONLY0-NEXT:    br label [[IF_END6574]]
54061 // SIMD-ONLY0:       if.end6574:
54062 // SIMD-ONLY0-NEXT:    [[TMP5110:%.*]] = load double, ptr [[DX]], align 8
54063 // SIMD-ONLY0-NEXT:    store double [[TMP5110]], ptr [[DV]], align 8
54064 // SIMD-ONLY0-NEXT:    [[TMP5111:%.*]] = load double, ptr [[DX]], align 8
54065 // SIMD-ONLY0-NEXT:    [[TMP5112:%.*]] = load double, ptr [[DE]], align 8
54066 // SIMD-ONLY0-NEXT:    [[CMP6575:%.*]] = fcmp ogt double [[TMP5111]], [[TMP5112]]
54067 // SIMD-ONLY0-NEXT:    br i1 [[CMP6575]], label [[IF_THEN6577:%.*]], label [[IF_END6578:%.*]]
54068 // SIMD-ONLY0:       if.then6577:
54069 // SIMD-ONLY0-NEXT:    [[TMP5113:%.*]] = load double, ptr [[DE]], align 8
54070 // SIMD-ONLY0-NEXT:    store double [[TMP5113]], ptr [[DX]], align 8
54071 // SIMD-ONLY0-NEXT:    br label [[IF_END6578]]
54072 // SIMD-ONLY0:       if.end6578:
54073 // SIMD-ONLY0-NEXT:    [[TMP5114:%.*]] = load double, ptr [[DX]], align 8
54074 // SIMD-ONLY0-NEXT:    store double [[TMP5114]], ptr [[DV]], align 8
54075 // SIMD-ONLY0-NEXT:    [[TMP5115:%.*]] = load double, ptr [[DE]], align 8
54076 // SIMD-ONLY0-NEXT:    [[TMP5116:%.*]] = load double, ptr [[DX]], align 8
54077 // SIMD-ONLY0-NEXT:    [[CMP6579:%.*]] = fcmp olt double [[TMP5115]], [[TMP5116]]
54078 // SIMD-ONLY0-NEXT:    br i1 [[CMP6579]], label [[IF_THEN6581:%.*]], label [[IF_END6582:%.*]]
54079 // SIMD-ONLY0:       if.then6581:
54080 // SIMD-ONLY0-NEXT:    [[TMP5117:%.*]] = load double, ptr [[DE]], align 8
54081 // SIMD-ONLY0-NEXT:    store double [[TMP5117]], ptr [[DX]], align 8
54082 // SIMD-ONLY0-NEXT:    br label [[IF_END6582]]
54083 // SIMD-ONLY0:       if.end6582:
54084 // SIMD-ONLY0-NEXT:    [[TMP5118:%.*]] = load double, ptr [[DX]], align 8
54085 // SIMD-ONLY0-NEXT:    store double [[TMP5118]], ptr [[DV]], align 8
54086 // SIMD-ONLY0-NEXT:    [[TMP5119:%.*]] = load double, ptr [[DX]], align 8
54087 // SIMD-ONLY0-NEXT:    [[TMP5120:%.*]] = load double, ptr [[DE]], align 8
54088 // SIMD-ONLY0-NEXT:    [[CMP6583:%.*]] = fcmp olt double [[TMP5119]], [[TMP5120]]
54089 // SIMD-ONLY0-NEXT:    br i1 [[CMP6583]], label [[IF_THEN6585:%.*]], label [[IF_END6586:%.*]]
54090 // SIMD-ONLY0:       if.then6585:
54091 // SIMD-ONLY0-NEXT:    [[TMP5121:%.*]] = load double, ptr [[DE]], align 8
54092 // SIMD-ONLY0-NEXT:    store double [[TMP5121]], ptr [[DX]], align 8
54093 // SIMD-ONLY0-NEXT:    br label [[IF_END6586]]
54094 // SIMD-ONLY0:       if.end6586:
54095 // SIMD-ONLY0-NEXT:    [[TMP5122:%.*]] = load double, ptr [[DX]], align 8
54096 // SIMD-ONLY0-NEXT:    store double [[TMP5122]], ptr [[DV]], align 8
54097 // SIMD-ONLY0-NEXT:    [[TMP5123:%.*]] = load double, ptr [[DX]], align 8
54098 // SIMD-ONLY0-NEXT:    [[TMP5124:%.*]] = load double, ptr [[DE]], align 8
54099 // SIMD-ONLY0-NEXT:    [[CMP6587:%.*]] = fcmp oeq double [[TMP5123]], [[TMP5124]]
54100 // SIMD-ONLY0-NEXT:    br i1 [[CMP6587]], label [[IF_THEN6589:%.*]], label [[IF_END6590:%.*]]
54101 // SIMD-ONLY0:       if.then6589:
54102 // SIMD-ONLY0-NEXT:    [[TMP5125:%.*]] = load double, ptr [[DD]], align 8
54103 // SIMD-ONLY0-NEXT:    store double [[TMP5125]], ptr [[DX]], align 8
54104 // SIMD-ONLY0-NEXT:    br label [[IF_END6590]]
54105 // SIMD-ONLY0:       if.end6590:
54106 // SIMD-ONLY0-NEXT:    [[TMP5126:%.*]] = load double, ptr [[DX]], align 8
54107 // SIMD-ONLY0-NEXT:    store double [[TMP5126]], ptr [[DV]], align 8
54108 // SIMD-ONLY0-NEXT:    [[TMP5127:%.*]] = load double, ptr [[DE]], align 8
54109 // SIMD-ONLY0-NEXT:    [[TMP5128:%.*]] = load double, ptr [[DX]], align 8
54110 // SIMD-ONLY0-NEXT:    [[CMP6591:%.*]] = fcmp oeq double [[TMP5127]], [[TMP5128]]
54111 // SIMD-ONLY0-NEXT:    br i1 [[CMP6591]], label [[IF_THEN6593:%.*]], label [[IF_END6594:%.*]]
54112 // SIMD-ONLY0:       if.then6593:
54113 // SIMD-ONLY0-NEXT:    [[TMP5129:%.*]] = load double, ptr [[DD]], align 8
54114 // SIMD-ONLY0-NEXT:    store double [[TMP5129]], ptr [[DX]], align 8
54115 // SIMD-ONLY0-NEXT:    br label [[IF_END6594]]
54116 // SIMD-ONLY0:       if.end6594:
54117 // SIMD-ONLY0-NEXT:    [[TMP5130:%.*]] = load double, ptr [[DE]], align 8
54118 // SIMD-ONLY0-NEXT:    [[TMP5131:%.*]] = load double, ptr [[DX]], align 8
54119 // SIMD-ONLY0-NEXT:    [[CMP6595:%.*]] = fcmp ogt double [[TMP5130]], [[TMP5131]]
54120 // SIMD-ONLY0-NEXT:    br i1 [[CMP6595]], label [[IF_THEN6597:%.*]], label [[IF_END6598:%.*]]
54121 // SIMD-ONLY0:       if.then6597:
54122 // SIMD-ONLY0-NEXT:    [[TMP5132:%.*]] = load double, ptr [[DE]], align 8
54123 // SIMD-ONLY0-NEXT:    store double [[TMP5132]], ptr [[DX]], align 8
54124 // SIMD-ONLY0-NEXT:    br label [[IF_END6598]]
54125 // SIMD-ONLY0:       if.end6598:
54126 // SIMD-ONLY0-NEXT:    [[TMP5133:%.*]] = load double, ptr [[DX]], align 8
54127 // SIMD-ONLY0-NEXT:    store double [[TMP5133]], ptr [[DV]], align 8
54128 // SIMD-ONLY0-NEXT:    [[TMP5134:%.*]] = load double, ptr [[DX]], align 8
54129 // SIMD-ONLY0-NEXT:    [[TMP5135:%.*]] = load double, ptr [[DE]], align 8
54130 // SIMD-ONLY0-NEXT:    [[CMP6599:%.*]] = fcmp ogt double [[TMP5134]], [[TMP5135]]
54131 // SIMD-ONLY0-NEXT:    br i1 [[CMP6599]], label [[IF_THEN6601:%.*]], label [[IF_END6602:%.*]]
54132 // SIMD-ONLY0:       if.then6601:
54133 // SIMD-ONLY0-NEXT:    [[TMP5136:%.*]] = load double, ptr [[DE]], align 8
54134 // SIMD-ONLY0-NEXT:    store double [[TMP5136]], ptr [[DX]], align 8
54135 // SIMD-ONLY0-NEXT:    br label [[IF_END6602]]
54136 // SIMD-ONLY0:       if.end6602:
54137 // SIMD-ONLY0-NEXT:    [[TMP5137:%.*]] = load double, ptr [[DX]], align 8
54138 // SIMD-ONLY0-NEXT:    store double [[TMP5137]], ptr [[DV]], align 8
54139 // SIMD-ONLY0-NEXT:    [[TMP5138:%.*]] = load double, ptr [[DE]], align 8
54140 // SIMD-ONLY0-NEXT:    [[TMP5139:%.*]] = load double, ptr [[DX]], align 8
54141 // SIMD-ONLY0-NEXT:    [[CMP6603:%.*]] = fcmp olt double [[TMP5138]], [[TMP5139]]
54142 // SIMD-ONLY0-NEXT:    br i1 [[CMP6603]], label [[IF_THEN6605:%.*]], label [[IF_END6606:%.*]]
54143 // SIMD-ONLY0:       if.then6605:
54144 // SIMD-ONLY0-NEXT:    [[TMP5140:%.*]] = load double, ptr [[DE]], align 8
54145 // SIMD-ONLY0-NEXT:    store double [[TMP5140]], ptr [[DX]], align 8
54146 // SIMD-ONLY0-NEXT:    br label [[IF_END6606]]
54147 // SIMD-ONLY0:       if.end6606:
54148 // SIMD-ONLY0-NEXT:    [[TMP5141:%.*]] = load double, ptr [[DX]], align 8
54149 // SIMD-ONLY0-NEXT:    store double [[TMP5141]], ptr [[DV]], align 8
54150 // SIMD-ONLY0-NEXT:    [[TMP5142:%.*]] = load double, ptr [[DX]], align 8
54151 // SIMD-ONLY0-NEXT:    [[TMP5143:%.*]] = load double, ptr [[DE]], align 8
54152 // SIMD-ONLY0-NEXT:    [[CMP6607:%.*]] = fcmp olt double [[TMP5142]], [[TMP5143]]
54153 // SIMD-ONLY0-NEXT:    br i1 [[CMP6607]], label [[IF_THEN6609:%.*]], label [[IF_END6610:%.*]]
54154 // SIMD-ONLY0:       if.then6609:
54155 // SIMD-ONLY0-NEXT:    [[TMP5144:%.*]] = load double, ptr [[DE]], align 8
54156 // SIMD-ONLY0-NEXT:    store double [[TMP5144]], ptr [[DX]], align 8
54157 // SIMD-ONLY0-NEXT:    br label [[IF_END6610]]
54158 // SIMD-ONLY0:       if.end6610:
54159 // SIMD-ONLY0-NEXT:    [[TMP5145:%.*]] = load double, ptr [[DX]], align 8
54160 // SIMD-ONLY0-NEXT:    store double [[TMP5145]], ptr [[DV]], align 8
54161 // SIMD-ONLY0-NEXT:    [[TMP5146:%.*]] = load double, ptr [[DX]], align 8
54162 // SIMD-ONLY0-NEXT:    [[TMP5147:%.*]] = load double, ptr [[DE]], align 8
54163 // SIMD-ONLY0-NEXT:    [[CMP6611:%.*]] = fcmp oeq double [[TMP5146]], [[TMP5147]]
54164 // SIMD-ONLY0-NEXT:    br i1 [[CMP6611]], label [[IF_THEN6613:%.*]], label [[IF_END6614:%.*]]
54165 // SIMD-ONLY0:       if.then6613:
54166 // SIMD-ONLY0-NEXT:    [[TMP5148:%.*]] = load double, ptr [[DD]], align 8
54167 // SIMD-ONLY0-NEXT:    store double [[TMP5148]], ptr [[DX]], align 8
54168 // SIMD-ONLY0-NEXT:    br label [[IF_END6614]]
54169 // SIMD-ONLY0:       if.end6614:
54170 // SIMD-ONLY0-NEXT:    [[TMP5149:%.*]] = load double, ptr [[DX]], align 8
54171 // SIMD-ONLY0-NEXT:    store double [[TMP5149]], ptr [[DV]], align 8
54172 // SIMD-ONLY0-NEXT:    [[TMP5150:%.*]] = load double, ptr [[DE]], align 8
54173 // SIMD-ONLY0-NEXT:    [[TMP5151:%.*]] = load double, ptr [[DX]], align 8
54174 // SIMD-ONLY0-NEXT:    [[CMP6615:%.*]] = fcmp oeq double [[TMP5150]], [[TMP5151]]
54175 // SIMD-ONLY0-NEXT:    br i1 [[CMP6615]], label [[IF_THEN6617:%.*]], label [[IF_END6618:%.*]]
54176 // SIMD-ONLY0:       if.then6617:
54177 // SIMD-ONLY0-NEXT:    [[TMP5152:%.*]] = load double, ptr [[DD]], align 8
54178 // SIMD-ONLY0-NEXT:    store double [[TMP5152]], ptr [[DX]], align 8
54179 // SIMD-ONLY0-NEXT:    br label [[IF_END6618]]
54180 // SIMD-ONLY0:       if.end6618:
54181 // SIMD-ONLY0-NEXT:    [[TMP5153:%.*]] = load double, ptr [[DX]], align 8
54182 // SIMD-ONLY0-NEXT:    store double [[TMP5153]], ptr [[DV]], align 8
54183 // SIMD-ONLY0-NEXT:    [[TMP5154:%.*]] = load double, ptr [[DX]], align 8
54184 // SIMD-ONLY0-NEXT:    [[TMP5155:%.*]] = load double, ptr [[DE]], align 8
54185 // SIMD-ONLY0-NEXT:    [[CMP6619:%.*]] = fcmp oeq double [[TMP5154]], [[TMP5155]]
54186 // SIMD-ONLY0-NEXT:    br i1 [[CMP6619]], label [[IF_THEN6621:%.*]], label [[IF_ELSE6622:%.*]]
54187 // SIMD-ONLY0:       if.then6621:
54188 // SIMD-ONLY0-NEXT:    [[TMP5156:%.*]] = load double, ptr [[DD]], align 8
54189 // SIMD-ONLY0-NEXT:    store double [[TMP5156]], ptr [[DX]], align 8
54190 // SIMD-ONLY0-NEXT:    br label [[IF_END6623:%.*]]
54191 // SIMD-ONLY0:       if.else6622:
54192 // SIMD-ONLY0-NEXT:    [[TMP5157:%.*]] = load double, ptr [[DX]], align 8
54193 // SIMD-ONLY0-NEXT:    store double [[TMP5157]], ptr [[DV]], align 8
54194 // SIMD-ONLY0-NEXT:    br label [[IF_END6623]]
54195 // SIMD-ONLY0:       if.end6623:
54196 // SIMD-ONLY0-NEXT:    [[TMP5158:%.*]] = load double, ptr [[DE]], align 8
54197 // SIMD-ONLY0-NEXT:    [[TMP5159:%.*]] = load double, ptr [[DX]], align 8
54198 // SIMD-ONLY0-NEXT:    [[CMP6624:%.*]] = fcmp oeq double [[TMP5158]], [[TMP5159]]
54199 // SIMD-ONLY0-NEXT:    br i1 [[CMP6624]], label [[IF_THEN6626:%.*]], label [[IF_ELSE6627:%.*]]
54200 // SIMD-ONLY0:       if.then6626:
54201 // SIMD-ONLY0-NEXT:    [[TMP5160:%.*]] = load double, ptr [[DD]], align 8
54202 // SIMD-ONLY0-NEXT:    store double [[TMP5160]], ptr [[DX]], align 8
54203 // SIMD-ONLY0-NEXT:    br label [[IF_END6628:%.*]]
54204 // SIMD-ONLY0:       if.else6627:
54205 // SIMD-ONLY0-NEXT:    [[TMP5161:%.*]] = load double, ptr [[DX]], align 8
54206 // SIMD-ONLY0-NEXT:    store double [[TMP5161]], ptr [[DV]], align 8
54207 // SIMD-ONLY0-NEXT:    br label [[IF_END6628]]
54208 // SIMD-ONLY0:       if.end6628:
54209 // SIMD-ONLY0-NEXT:    [[TMP5162:%.*]] = load double, ptr [[DX]], align 8
54210 // SIMD-ONLY0-NEXT:    [[TMP5163:%.*]] = load double, ptr [[DE]], align 8
54211 // SIMD-ONLY0-NEXT:    [[CMP6629:%.*]] = fcmp oeq double [[TMP5162]], [[TMP5163]]
54212 // SIMD-ONLY0-NEXT:    [[CONV6630:%.*]] = zext i1 [[CMP6629]] to i32
54213 // SIMD-ONLY0-NEXT:    store i32 [[CONV6630]], ptr [[IR]], align 4
54214 // SIMD-ONLY0-NEXT:    [[TMP5164:%.*]] = load i32, ptr [[IR]], align 4
54215 // SIMD-ONLY0-NEXT:    [[TOBOOL6631:%.*]] = icmp ne i32 [[TMP5164]], 0
54216 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6631]], label [[IF_THEN6632:%.*]], label [[IF_END6633:%.*]]
54217 // SIMD-ONLY0:       if.then6632:
54218 // SIMD-ONLY0-NEXT:    [[TMP5165:%.*]] = load double, ptr [[DD]], align 8
54219 // SIMD-ONLY0-NEXT:    store double [[TMP5165]], ptr [[DX]], align 8
54220 // SIMD-ONLY0-NEXT:    br label [[IF_END6633]]
54221 // SIMD-ONLY0:       if.end6633:
54222 // SIMD-ONLY0-NEXT:    [[TMP5166:%.*]] = load double, ptr [[DE]], align 8
54223 // SIMD-ONLY0-NEXT:    [[TMP5167:%.*]] = load double, ptr [[DX]], align 8
54224 // SIMD-ONLY0-NEXT:    [[CMP6634:%.*]] = fcmp oeq double [[TMP5166]], [[TMP5167]]
54225 // SIMD-ONLY0-NEXT:    [[CONV6635:%.*]] = zext i1 [[CMP6634]] to i32
54226 // SIMD-ONLY0-NEXT:    store i32 [[CONV6635]], ptr [[IR]], align 4
54227 // SIMD-ONLY0-NEXT:    [[TMP5168:%.*]] = load i32, ptr [[IR]], align 4
54228 // SIMD-ONLY0-NEXT:    [[TOBOOL6636:%.*]] = icmp ne i32 [[TMP5168]], 0
54229 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6636]], label [[IF_THEN6637:%.*]], label [[IF_END6638:%.*]]
54230 // SIMD-ONLY0:       if.then6637:
54231 // SIMD-ONLY0-NEXT:    [[TMP5169:%.*]] = load double, ptr [[DD]], align 8
54232 // SIMD-ONLY0-NEXT:    store double [[TMP5169]], ptr [[DX]], align 8
54233 // SIMD-ONLY0-NEXT:    br label [[IF_END6638]]
54234 // SIMD-ONLY0:       if.end6638:
54235 // SIMD-ONLY0-NEXT:    [[TMP5170:%.*]] = load double, ptr [[DX]], align 8
54236 // SIMD-ONLY0-NEXT:    [[TMP5171:%.*]] = load double, ptr [[DE]], align 8
54237 // SIMD-ONLY0-NEXT:    [[CMP6639:%.*]] = fcmp oeq double [[TMP5170]], [[TMP5171]]
54238 // SIMD-ONLY0-NEXT:    [[CONV6640:%.*]] = zext i1 [[CMP6639]] to i32
54239 // SIMD-ONLY0-NEXT:    store i32 [[CONV6640]], ptr [[IR]], align 4
54240 // SIMD-ONLY0-NEXT:    [[TMP5172:%.*]] = load i32, ptr [[IR]], align 4
54241 // SIMD-ONLY0-NEXT:    [[TOBOOL6641:%.*]] = icmp ne i32 [[TMP5172]], 0
54242 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6641]], label [[IF_THEN6642:%.*]], label [[IF_ELSE6643:%.*]]
54243 // SIMD-ONLY0:       if.then6642:
54244 // SIMD-ONLY0-NEXT:    [[TMP5173:%.*]] = load double, ptr [[DD]], align 8
54245 // SIMD-ONLY0-NEXT:    store double [[TMP5173]], ptr [[DX]], align 8
54246 // SIMD-ONLY0-NEXT:    br label [[IF_END6644:%.*]]
54247 // SIMD-ONLY0:       if.else6643:
54248 // SIMD-ONLY0-NEXT:    [[TMP5174:%.*]] = load double, ptr [[DX]], align 8
54249 // SIMD-ONLY0-NEXT:    store double [[TMP5174]], ptr [[DV]], align 8
54250 // SIMD-ONLY0-NEXT:    br label [[IF_END6644]]
54251 // SIMD-ONLY0:       if.end6644:
54252 // SIMD-ONLY0-NEXT:    [[TMP5175:%.*]] = load double, ptr [[DE]], align 8
54253 // SIMD-ONLY0-NEXT:    [[TMP5176:%.*]] = load double, ptr [[DX]], align 8
54254 // SIMD-ONLY0-NEXT:    [[CMP6645:%.*]] = fcmp oeq double [[TMP5175]], [[TMP5176]]
54255 // SIMD-ONLY0-NEXT:    [[CONV6646:%.*]] = zext i1 [[CMP6645]] to i32
54256 // SIMD-ONLY0-NEXT:    store i32 [[CONV6646]], ptr [[IR]], align 4
54257 // SIMD-ONLY0-NEXT:    [[TMP5177:%.*]] = load i32, ptr [[IR]], align 4
54258 // SIMD-ONLY0-NEXT:    [[TOBOOL6647:%.*]] = icmp ne i32 [[TMP5177]], 0
54259 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6647]], label [[IF_THEN6648:%.*]], label [[IF_ELSE6649:%.*]]
54260 // SIMD-ONLY0:       if.then6648:
54261 // SIMD-ONLY0-NEXT:    [[TMP5178:%.*]] = load double, ptr [[DD]], align 8
54262 // SIMD-ONLY0-NEXT:    store double [[TMP5178]], ptr [[DX]], align 8
54263 // SIMD-ONLY0-NEXT:    br label [[IF_END6650:%.*]]
54264 // SIMD-ONLY0:       if.else6649:
54265 // SIMD-ONLY0-NEXT:    [[TMP5179:%.*]] = load double, ptr [[DX]], align 8
54266 // SIMD-ONLY0-NEXT:    store double [[TMP5179]], ptr [[DV]], align 8
54267 // SIMD-ONLY0-NEXT:    br label [[IF_END6650]]
54268 // SIMD-ONLY0:       if.end6650:
54269 // SIMD-ONLY0-NEXT:    [[TMP5180:%.*]] = load double, ptr [[DX]], align 8
54270 // SIMD-ONLY0-NEXT:    store double [[TMP5180]], ptr [[DV]], align 8
54271 // SIMD-ONLY0-NEXT:    [[TMP5181:%.*]] = load double, ptr [[DE]], align 8
54272 // SIMD-ONLY0-NEXT:    [[TMP5182:%.*]] = load double, ptr [[DX]], align 8
54273 // SIMD-ONLY0-NEXT:    [[CMP6651:%.*]] = fcmp ogt double [[TMP5181]], [[TMP5182]]
54274 // SIMD-ONLY0-NEXT:    br i1 [[CMP6651]], label [[IF_THEN6653:%.*]], label [[IF_END6654:%.*]]
54275 // SIMD-ONLY0:       if.then6653:
54276 // SIMD-ONLY0-NEXT:    [[TMP5183:%.*]] = load double, ptr [[DE]], align 8
54277 // SIMD-ONLY0-NEXT:    store double [[TMP5183]], ptr [[DX]], align 8
54278 // SIMD-ONLY0-NEXT:    br label [[IF_END6654]]
54279 // SIMD-ONLY0:       if.end6654:
54280 // SIMD-ONLY0-NEXT:    [[TMP5184:%.*]] = load double, ptr [[DX]], align 8
54281 // SIMD-ONLY0-NEXT:    store double [[TMP5184]], ptr [[DV]], align 8
54282 // SIMD-ONLY0-NEXT:    [[TMP5185:%.*]] = load double, ptr [[DX]], align 8
54283 // SIMD-ONLY0-NEXT:    [[TMP5186:%.*]] = load double, ptr [[DE]], align 8
54284 // SIMD-ONLY0-NEXT:    [[CMP6655:%.*]] = fcmp ogt double [[TMP5185]], [[TMP5186]]
54285 // SIMD-ONLY0-NEXT:    br i1 [[CMP6655]], label [[IF_THEN6657:%.*]], label [[IF_END6658:%.*]]
54286 // SIMD-ONLY0:       if.then6657:
54287 // SIMD-ONLY0-NEXT:    [[TMP5187:%.*]] = load double, ptr [[DE]], align 8
54288 // SIMD-ONLY0-NEXT:    store double [[TMP5187]], ptr [[DX]], align 8
54289 // SIMD-ONLY0-NEXT:    br label [[IF_END6658]]
54290 // SIMD-ONLY0:       if.end6658:
54291 // SIMD-ONLY0-NEXT:    [[TMP5188:%.*]] = load double, ptr [[DX]], align 8
54292 // SIMD-ONLY0-NEXT:    store double [[TMP5188]], ptr [[DV]], align 8
54293 // SIMD-ONLY0-NEXT:    [[TMP5189:%.*]] = load double, ptr [[DE]], align 8
54294 // SIMD-ONLY0-NEXT:    [[TMP5190:%.*]] = load double, ptr [[DX]], align 8
54295 // SIMD-ONLY0-NEXT:    [[CMP6659:%.*]] = fcmp olt double [[TMP5189]], [[TMP5190]]
54296 // SIMD-ONLY0-NEXT:    br i1 [[CMP6659]], label [[IF_THEN6661:%.*]], label [[IF_END6662:%.*]]
54297 // SIMD-ONLY0:       if.then6661:
54298 // SIMD-ONLY0-NEXT:    [[TMP5191:%.*]] = load double, ptr [[DE]], align 8
54299 // SIMD-ONLY0-NEXT:    store double [[TMP5191]], ptr [[DX]], align 8
54300 // SIMD-ONLY0-NEXT:    br label [[IF_END6662]]
54301 // SIMD-ONLY0:       if.end6662:
54302 // SIMD-ONLY0-NEXT:    [[TMP5192:%.*]] = load double, ptr [[DX]], align 8
54303 // SIMD-ONLY0-NEXT:    store double [[TMP5192]], ptr [[DV]], align 8
54304 // SIMD-ONLY0-NEXT:    [[TMP5193:%.*]] = load double, ptr [[DX]], align 8
54305 // SIMD-ONLY0-NEXT:    [[TMP5194:%.*]] = load double, ptr [[DE]], align 8
54306 // SIMD-ONLY0-NEXT:    [[CMP6663:%.*]] = fcmp olt double [[TMP5193]], [[TMP5194]]
54307 // SIMD-ONLY0-NEXT:    br i1 [[CMP6663]], label [[IF_THEN6665:%.*]], label [[IF_END6666:%.*]]
54308 // SIMD-ONLY0:       if.then6665:
54309 // SIMD-ONLY0-NEXT:    [[TMP5195:%.*]] = load double, ptr [[DE]], align 8
54310 // SIMD-ONLY0-NEXT:    store double [[TMP5195]], ptr [[DX]], align 8
54311 // SIMD-ONLY0-NEXT:    br label [[IF_END6666]]
54312 // SIMD-ONLY0:       if.end6666:
54313 // SIMD-ONLY0-NEXT:    [[TMP5196:%.*]] = load double, ptr [[DX]], align 8
54314 // SIMD-ONLY0-NEXT:    store double [[TMP5196]], ptr [[DV]], align 8
54315 // SIMD-ONLY0-NEXT:    [[TMP5197:%.*]] = load double, ptr [[DX]], align 8
54316 // SIMD-ONLY0-NEXT:    [[TMP5198:%.*]] = load double, ptr [[DE]], align 8
54317 // SIMD-ONLY0-NEXT:    [[CMP6667:%.*]] = fcmp oeq double [[TMP5197]], [[TMP5198]]
54318 // SIMD-ONLY0-NEXT:    br i1 [[CMP6667]], label [[IF_THEN6669:%.*]], label [[IF_END6670:%.*]]
54319 // SIMD-ONLY0:       if.then6669:
54320 // SIMD-ONLY0-NEXT:    [[TMP5199:%.*]] = load double, ptr [[DD]], align 8
54321 // SIMD-ONLY0-NEXT:    store double [[TMP5199]], ptr [[DX]], align 8
54322 // SIMD-ONLY0-NEXT:    br label [[IF_END6670]]
54323 // SIMD-ONLY0:       if.end6670:
54324 // SIMD-ONLY0-NEXT:    [[TMP5200:%.*]] = load double, ptr [[DX]], align 8
54325 // SIMD-ONLY0-NEXT:    store double [[TMP5200]], ptr [[DV]], align 8
54326 // SIMD-ONLY0-NEXT:    [[TMP5201:%.*]] = load double, ptr [[DE]], align 8
54327 // SIMD-ONLY0-NEXT:    [[TMP5202:%.*]] = load double, ptr [[DX]], align 8
54328 // SIMD-ONLY0-NEXT:    [[CMP6671:%.*]] = fcmp oeq double [[TMP5201]], [[TMP5202]]
54329 // SIMD-ONLY0-NEXT:    br i1 [[CMP6671]], label [[IF_THEN6673:%.*]], label [[IF_END6674:%.*]]
54330 // SIMD-ONLY0:       if.then6673:
54331 // SIMD-ONLY0-NEXT:    [[TMP5203:%.*]] = load double, ptr [[DD]], align 8
54332 // SIMD-ONLY0-NEXT:    store double [[TMP5203]], ptr [[DX]], align 8
54333 // SIMD-ONLY0-NEXT:    br label [[IF_END6674]]
54334 // SIMD-ONLY0:       if.end6674:
54335 // SIMD-ONLY0-NEXT:    [[TMP5204:%.*]] = load double, ptr [[DE]], align 8
54336 // SIMD-ONLY0-NEXT:    [[TMP5205:%.*]] = load double, ptr [[DX]], align 8
54337 // SIMD-ONLY0-NEXT:    [[CMP6675:%.*]] = fcmp ogt double [[TMP5204]], [[TMP5205]]
54338 // SIMD-ONLY0-NEXT:    br i1 [[CMP6675]], label [[IF_THEN6677:%.*]], label [[IF_END6678:%.*]]
54339 // SIMD-ONLY0:       if.then6677:
54340 // SIMD-ONLY0-NEXT:    [[TMP5206:%.*]] = load double, ptr [[DE]], align 8
54341 // SIMD-ONLY0-NEXT:    store double [[TMP5206]], ptr [[DX]], align 8
54342 // SIMD-ONLY0-NEXT:    br label [[IF_END6678]]
54343 // SIMD-ONLY0:       if.end6678:
54344 // SIMD-ONLY0-NEXT:    [[TMP5207:%.*]] = load double, ptr [[DX]], align 8
54345 // SIMD-ONLY0-NEXT:    store double [[TMP5207]], ptr [[DV]], align 8
54346 // SIMD-ONLY0-NEXT:    [[TMP5208:%.*]] = load double, ptr [[DX]], align 8
54347 // SIMD-ONLY0-NEXT:    [[TMP5209:%.*]] = load double, ptr [[DE]], align 8
54348 // SIMD-ONLY0-NEXT:    [[CMP6679:%.*]] = fcmp ogt double [[TMP5208]], [[TMP5209]]
54349 // SIMD-ONLY0-NEXT:    br i1 [[CMP6679]], label [[IF_THEN6681:%.*]], label [[IF_END6682:%.*]]
54350 // SIMD-ONLY0:       if.then6681:
54351 // SIMD-ONLY0-NEXT:    [[TMP5210:%.*]] = load double, ptr [[DE]], align 8
54352 // SIMD-ONLY0-NEXT:    store double [[TMP5210]], ptr [[DX]], align 8
54353 // SIMD-ONLY0-NEXT:    br label [[IF_END6682]]
54354 // SIMD-ONLY0:       if.end6682:
54355 // SIMD-ONLY0-NEXT:    [[TMP5211:%.*]] = load double, ptr [[DX]], align 8
54356 // SIMD-ONLY0-NEXT:    store double [[TMP5211]], ptr [[DV]], align 8
54357 // SIMD-ONLY0-NEXT:    [[TMP5212:%.*]] = load double, ptr [[DE]], align 8
54358 // SIMD-ONLY0-NEXT:    [[TMP5213:%.*]] = load double, ptr [[DX]], align 8
54359 // SIMD-ONLY0-NEXT:    [[CMP6683:%.*]] = fcmp olt double [[TMP5212]], [[TMP5213]]
54360 // SIMD-ONLY0-NEXT:    br i1 [[CMP6683]], label [[IF_THEN6685:%.*]], label [[IF_END6686:%.*]]
54361 // SIMD-ONLY0:       if.then6685:
54362 // SIMD-ONLY0-NEXT:    [[TMP5214:%.*]] = load double, ptr [[DE]], align 8
54363 // SIMD-ONLY0-NEXT:    store double [[TMP5214]], ptr [[DX]], align 8
54364 // SIMD-ONLY0-NEXT:    br label [[IF_END6686]]
54365 // SIMD-ONLY0:       if.end6686:
54366 // SIMD-ONLY0-NEXT:    [[TMP5215:%.*]] = load double, ptr [[DX]], align 8
54367 // SIMD-ONLY0-NEXT:    store double [[TMP5215]], ptr [[DV]], align 8
54368 // SIMD-ONLY0-NEXT:    [[TMP5216:%.*]] = load double, ptr [[DX]], align 8
54369 // SIMD-ONLY0-NEXT:    [[TMP5217:%.*]] = load double, ptr [[DE]], align 8
54370 // SIMD-ONLY0-NEXT:    [[CMP6687:%.*]] = fcmp olt double [[TMP5216]], [[TMP5217]]
54371 // SIMD-ONLY0-NEXT:    br i1 [[CMP6687]], label [[IF_THEN6689:%.*]], label [[IF_END6690:%.*]]
54372 // SIMD-ONLY0:       if.then6689:
54373 // SIMD-ONLY0-NEXT:    [[TMP5218:%.*]] = load double, ptr [[DE]], align 8
54374 // SIMD-ONLY0-NEXT:    store double [[TMP5218]], ptr [[DX]], align 8
54375 // SIMD-ONLY0-NEXT:    br label [[IF_END6690]]
54376 // SIMD-ONLY0:       if.end6690:
54377 // SIMD-ONLY0-NEXT:    [[TMP5219:%.*]] = load double, ptr [[DX]], align 8
54378 // SIMD-ONLY0-NEXT:    store double [[TMP5219]], ptr [[DV]], align 8
54379 // SIMD-ONLY0-NEXT:    [[TMP5220:%.*]] = load double, ptr [[DX]], align 8
54380 // SIMD-ONLY0-NEXT:    [[TMP5221:%.*]] = load double, ptr [[DE]], align 8
54381 // SIMD-ONLY0-NEXT:    [[CMP6691:%.*]] = fcmp oeq double [[TMP5220]], [[TMP5221]]
54382 // SIMD-ONLY0-NEXT:    br i1 [[CMP6691]], label [[IF_THEN6693:%.*]], label [[IF_END6694:%.*]]
54383 // SIMD-ONLY0:       if.then6693:
54384 // SIMD-ONLY0-NEXT:    [[TMP5222:%.*]] = load double, ptr [[DD]], align 8
54385 // SIMD-ONLY0-NEXT:    store double [[TMP5222]], ptr [[DX]], align 8
54386 // SIMD-ONLY0-NEXT:    br label [[IF_END6694]]
54387 // SIMD-ONLY0:       if.end6694:
54388 // SIMD-ONLY0-NEXT:    [[TMP5223:%.*]] = load double, ptr [[DX]], align 8
54389 // SIMD-ONLY0-NEXT:    store double [[TMP5223]], ptr [[DV]], align 8
54390 // SIMD-ONLY0-NEXT:    [[TMP5224:%.*]] = load double, ptr [[DE]], align 8
54391 // SIMD-ONLY0-NEXT:    [[TMP5225:%.*]] = load double, ptr [[DX]], align 8
54392 // SIMD-ONLY0-NEXT:    [[CMP6695:%.*]] = fcmp oeq double [[TMP5224]], [[TMP5225]]
54393 // SIMD-ONLY0-NEXT:    br i1 [[CMP6695]], label [[IF_THEN6697:%.*]], label [[IF_END6698:%.*]]
54394 // SIMD-ONLY0:       if.then6697:
54395 // SIMD-ONLY0-NEXT:    [[TMP5226:%.*]] = load double, ptr [[DD]], align 8
54396 // SIMD-ONLY0-NEXT:    store double [[TMP5226]], ptr [[DX]], align 8
54397 // SIMD-ONLY0-NEXT:    br label [[IF_END6698]]
54398 // SIMD-ONLY0:       if.end6698:
54399 // SIMD-ONLY0-NEXT:    [[TMP5227:%.*]] = load double, ptr [[DX]], align 8
54400 // SIMD-ONLY0-NEXT:    store double [[TMP5227]], ptr [[DV]], align 8
54401 // SIMD-ONLY0-NEXT:    [[TMP5228:%.*]] = load double, ptr [[DX]], align 8
54402 // SIMD-ONLY0-NEXT:    [[TMP5229:%.*]] = load double, ptr [[DE]], align 8
54403 // SIMD-ONLY0-NEXT:    [[CMP6699:%.*]] = fcmp oeq double [[TMP5228]], [[TMP5229]]
54404 // SIMD-ONLY0-NEXT:    br i1 [[CMP6699]], label [[IF_THEN6701:%.*]], label [[IF_ELSE6702:%.*]]
54405 // SIMD-ONLY0:       if.then6701:
54406 // SIMD-ONLY0-NEXT:    [[TMP5230:%.*]] = load double, ptr [[DD]], align 8
54407 // SIMD-ONLY0-NEXT:    store double [[TMP5230]], ptr [[DX]], align 8
54408 // SIMD-ONLY0-NEXT:    br label [[IF_END6703:%.*]]
54409 // SIMD-ONLY0:       if.else6702:
54410 // SIMD-ONLY0-NEXT:    [[TMP5231:%.*]] = load double, ptr [[DX]], align 8
54411 // SIMD-ONLY0-NEXT:    store double [[TMP5231]], ptr [[DV]], align 8
54412 // SIMD-ONLY0-NEXT:    br label [[IF_END6703]]
54413 // SIMD-ONLY0:       if.end6703:
54414 // SIMD-ONLY0-NEXT:    [[TMP5232:%.*]] = load double, ptr [[DE]], align 8
54415 // SIMD-ONLY0-NEXT:    [[TMP5233:%.*]] = load double, ptr [[DX]], align 8
54416 // SIMD-ONLY0-NEXT:    [[CMP6704:%.*]] = fcmp oeq double [[TMP5232]], [[TMP5233]]
54417 // SIMD-ONLY0-NEXT:    br i1 [[CMP6704]], label [[IF_THEN6706:%.*]], label [[IF_ELSE6707:%.*]]
54418 // SIMD-ONLY0:       if.then6706:
54419 // SIMD-ONLY0-NEXT:    [[TMP5234:%.*]] = load double, ptr [[DD]], align 8
54420 // SIMD-ONLY0-NEXT:    store double [[TMP5234]], ptr [[DX]], align 8
54421 // SIMD-ONLY0-NEXT:    br label [[IF_END6708:%.*]]
54422 // SIMD-ONLY0:       if.else6707:
54423 // SIMD-ONLY0-NEXT:    [[TMP5235:%.*]] = load double, ptr [[DX]], align 8
54424 // SIMD-ONLY0-NEXT:    store double [[TMP5235]], ptr [[DV]], align 8
54425 // SIMD-ONLY0-NEXT:    br label [[IF_END6708]]
54426 // SIMD-ONLY0:       if.end6708:
54427 // SIMD-ONLY0-NEXT:    [[TMP5236:%.*]] = load double, ptr [[DX]], align 8
54428 // SIMD-ONLY0-NEXT:    [[TMP5237:%.*]] = load double, ptr [[DE]], align 8
54429 // SIMD-ONLY0-NEXT:    [[CMP6709:%.*]] = fcmp oeq double [[TMP5236]], [[TMP5237]]
54430 // SIMD-ONLY0-NEXT:    [[CONV6710:%.*]] = zext i1 [[CMP6709]] to i32
54431 // SIMD-ONLY0-NEXT:    store i32 [[CONV6710]], ptr [[IR]], align 4
54432 // SIMD-ONLY0-NEXT:    [[TMP5238:%.*]] = load i32, ptr [[IR]], align 4
54433 // SIMD-ONLY0-NEXT:    [[TOBOOL6711:%.*]] = icmp ne i32 [[TMP5238]], 0
54434 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6711]], label [[IF_THEN6712:%.*]], label [[IF_END6713:%.*]]
54435 // SIMD-ONLY0:       if.then6712:
54436 // SIMD-ONLY0-NEXT:    [[TMP5239:%.*]] = load double, ptr [[DD]], align 8
54437 // SIMD-ONLY0-NEXT:    store double [[TMP5239]], ptr [[DX]], align 8
54438 // SIMD-ONLY0-NEXT:    br label [[IF_END6713]]
54439 // SIMD-ONLY0:       if.end6713:
54440 // SIMD-ONLY0-NEXT:    [[TMP5240:%.*]] = load double, ptr [[DE]], align 8
54441 // SIMD-ONLY0-NEXT:    [[TMP5241:%.*]] = load double, ptr [[DX]], align 8
54442 // SIMD-ONLY0-NEXT:    [[CMP6714:%.*]] = fcmp oeq double [[TMP5240]], [[TMP5241]]
54443 // SIMD-ONLY0-NEXT:    [[CONV6715:%.*]] = zext i1 [[CMP6714]] to i32
54444 // SIMD-ONLY0-NEXT:    store i32 [[CONV6715]], ptr [[IR]], align 4
54445 // SIMD-ONLY0-NEXT:    [[TMP5242:%.*]] = load i32, ptr [[IR]], align 4
54446 // SIMD-ONLY0-NEXT:    [[TOBOOL6716:%.*]] = icmp ne i32 [[TMP5242]], 0
54447 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6716]], label [[IF_THEN6717:%.*]], label [[IF_END6718:%.*]]
54448 // SIMD-ONLY0:       if.then6717:
54449 // SIMD-ONLY0-NEXT:    [[TMP5243:%.*]] = load double, ptr [[DD]], align 8
54450 // SIMD-ONLY0-NEXT:    store double [[TMP5243]], ptr [[DX]], align 8
54451 // SIMD-ONLY0-NEXT:    br label [[IF_END6718]]
54452 // SIMD-ONLY0:       if.end6718:
54453 // SIMD-ONLY0-NEXT:    [[TMP5244:%.*]] = load double, ptr [[DX]], align 8
54454 // SIMD-ONLY0-NEXT:    [[TMP5245:%.*]] = load double, ptr [[DE]], align 8
54455 // SIMD-ONLY0-NEXT:    [[CMP6719:%.*]] = fcmp oeq double [[TMP5244]], [[TMP5245]]
54456 // SIMD-ONLY0-NEXT:    [[CONV6720:%.*]] = zext i1 [[CMP6719]] to i32
54457 // SIMD-ONLY0-NEXT:    store i32 [[CONV6720]], ptr [[IR]], align 4
54458 // SIMD-ONLY0-NEXT:    [[TMP5246:%.*]] = load i32, ptr [[IR]], align 4
54459 // SIMD-ONLY0-NEXT:    [[TOBOOL6721:%.*]] = icmp ne i32 [[TMP5246]], 0
54460 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6721]], label [[IF_THEN6722:%.*]], label [[IF_ELSE6723:%.*]]
54461 // SIMD-ONLY0:       if.then6722:
54462 // SIMD-ONLY0-NEXT:    [[TMP5247:%.*]] = load double, ptr [[DD]], align 8
54463 // SIMD-ONLY0-NEXT:    store double [[TMP5247]], ptr [[DX]], align 8
54464 // SIMD-ONLY0-NEXT:    br label [[IF_END6724:%.*]]
54465 // SIMD-ONLY0:       if.else6723:
54466 // SIMD-ONLY0-NEXT:    [[TMP5248:%.*]] = load double, ptr [[DX]], align 8
54467 // SIMD-ONLY0-NEXT:    store double [[TMP5248]], ptr [[DV]], align 8
54468 // SIMD-ONLY0-NEXT:    br label [[IF_END6724]]
54469 // SIMD-ONLY0:       if.end6724:
54470 // SIMD-ONLY0-NEXT:    [[TMP5249:%.*]] = load double, ptr [[DE]], align 8
54471 // SIMD-ONLY0-NEXT:    [[TMP5250:%.*]] = load double, ptr [[DX]], align 8
54472 // SIMD-ONLY0-NEXT:    [[CMP6725:%.*]] = fcmp oeq double [[TMP5249]], [[TMP5250]]
54473 // SIMD-ONLY0-NEXT:    [[CONV6726:%.*]] = zext i1 [[CMP6725]] to i32
54474 // SIMD-ONLY0-NEXT:    store i32 [[CONV6726]], ptr [[IR]], align 4
54475 // SIMD-ONLY0-NEXT:    [[TMP5251:%.*]] = load i32, ptr [[IR]], align 4
54476 // SIMD-ONLY0-NEXT:    [[TOBOOL6727:%.*]] = icmp ne i32 [[TMP5251]], 0
54477 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6727]], label [[IF_THEN6728:%.*]], label [[IF_ELSE6729:%.*]]
54478 // SIMD-ONLY0:       if.then6728:
54479 // SIMD-ONLY0-NEXT:    [[TMP5252:%.*]] = load double, ptr [[DD]], align 8
54480 // SIMD-ONLY0-NEXT:    store double [[TMP5252]], ptr [[DX]], align 8
54481 // SIMD-ONLY0-NEXT:    br label [[IF_END6730:%.*]]
54482 // SIMD-ONLY0:       if.else6729:
54483 // SIMD-ONLY0-NEXT:    [[TMP5253:%.*]] = load double, ptr [[DX]], align 8
54484 // SIMD-ONLY0-NEXT:    store double [[TMP5253]], ptr [[DV]], align 8
54485 // SIMD-ONLY0-NEXT:    br label [[IF_END6730]]
54486 // SIMD-ONLY0:       if.end6730:
54487 // SIMD-ONLY0-NEXT:    [[TMP5254:%.*]] = load double, ptr [[DX]], align 8
54488 // SIMD-ONLY0-NEXT:    store double [[TMP5254]], ptr [[DV]], align 8
54489 // SIMD-ONLY0-NEXT:    [[TMP5255:%.*]] = load double, ptr [[DE]], align 8
54490 // SIMD-ONLY0-NEXT:    [[TMP5256:%.*]] = load double, ptr [[DX]], align 8
54491 // SIMD-ONLY0-NEXT:    [[CMP6731:%.*]] = fcmp ogt double [[TMP5255]], [[TMP5256]]
54492 // SIMD-ONLY0-NEXT:    br i1 [[CMP6731]], label [[IF_THEN6733:%.*]], label [[IF_END6734:%.*]]
54493 // SIMD-ONLY0:       if.then6733:
54494 // SIMD-ONLY0-NEXT:    [[TMP5257:%.*]] = load double, ptr [[DE]], align 8
54495 // SIMD-ONLY0-NEXT:    store double [[TMP5257]], ptr [[DX]], align 8
54496 // SIMD-ONLY0-NEXT:    br label [[IF_END6734]]
54497 // SIMD-ONLY0:       if.end6734:
54498 // SIMD-ONLY0-NEXT:    [[TMP5258:%.*]] = load double, ptr [[DX]], align 8
54499 // SIMD-ONLY0-NEXT:    store double [[TMP5258]], ptr [[DV]], align 8
54500 // SIMD-ONLY0-NEXT:    [[TMP5259:%.*]] = load double, ptr [[DX]], align 8
54501 // SIMD-ONLY0-NEXT:    [[TMP5260:%.*]] = load double, ptr [[DE]], align 8
54502 // SIMD-ONLY0-NEXT:    [[CMP6735:%.*]] = fcmp ogt double [[TMP5259]], [[TMP5260]]
54503 // SIMD-ONLY0-NEXT:    br i1 [[CMP6735]], label [[IF_THEN6737:%.*]], label [[IF_END6738:%.*]]
54504 // SIMD-ONLY0:       if.then6737:
54505 // SIMD-ONLY0-NEXT:    [[TMP5261:%.*]] = load double, ptr [[DE]], align 8
54506 // SIMD-ONLY0-NEXT:    store double [[TMP5261]], ptr [[DX]], align 8
54507 // SIMD-ONLY0-NEXT:    br label [[IF_END6738]]
54508 // SIMD-ONLY0:       if.end6738:
54509 // SIMD-ONLY0-NEXT:    [[TMP5262:%.*]] = load double, ptr [[DX]], align 8
54510 // SIMD-ONLY0-NEXT:    store double [[TMP5262]], ptr [[DV]], align 8
54511 // SIMD-ONLY0-NEXT:    [[TMP5263:%.*]] = load double, ptr [[DE]], align 8
54512 // SIMD-ONLY0-NEXT:    [[TMP5264:%.*]] = load double, ptr [[DX]], align 8
54513 // SIMD-ONLY0-NEXT:    [[CMP6739:%.*]] = fcmp olt double [[TMP5263]], [[TMP5264]]
54514 // SIMD-ONLY0-NEXT:    br i1 [[CMP6739]], label [[IF_THEN6741:%.*]], label [[IF_END6742:%.*]]
54515 // SIMD-ONLY0:       if.then6741:
54516 // SIMD-ONLY0-NEXT:    [[TMP5265:%.*]] = load double, ptr [[DE]], align 8
54517 // SIMD-ONLY0-NEXT:    store double [[TMP5265]], ptr [[DX]], align 8
54518 // SIMD-ONLY0-NEXT:    br label [[IF_END6742]]
54519 // SIMD-ONLY0:       if.end6742:
54520 // SIMD-ONLY0-NEXT:    [[TMP5266:%.*]] = load double, ptr [[DX]], align 8
54521 // SIMD-ONLY0-NEXT:    store double [[TMP5266]], ptr [[DV]], align 8
54522 // SIMD-ONLY0-NEXT:    [[TMP5267:%.*]] = load double, ptr [[DX]], align 8
54523 // SIMD-ONLY0-NEXT:    [[TMP5268:%.*]] = load double, ptr [[DE]], align 8
54524 // SIMD-ONLY0-NEXT:    [[CMP6743:%.*]] = fcmp olt double [[TMP5267]], [[TMP5268]]
54525 // SIMD-ONLY0-NEXT:    br i1 [[CMP6743]], label [[IF_THEN6745:%.*]], label [[IF_END6746:%.*]]
54526 // SIMD-ONLY0:       if.then6745:
54527 // SIMD-ONLY0-NEXT:    [[TMP5269:%.*]] = load double, ptr [[DE]], align 8
54528 // SIMD-ONLY0-NEXT:    store double [[TMP5269]], ptr [[DX]], align 8
54529 // SIMD-ONLY0-NEXT:    br label [[IF_END6746]]
54530 // SIMD-ONLY0:       if.end6746:
54531 // SIMD-ONLY0-NEXT:    [[TMP5270:%.*]] = load double, ptr [[DX]], align 8
54532 // SIMD-ONLY0-NEXT:    store double [[TMP5270]], ptr [[DV]], align 8
54533 // SIMD-ONLY0-NEXT:    [[TMP5271:%.*]] = load double, ptr [[DX]], align 8
54534 // SIMD-ONLY0-NEXT:    [[TMP5272:%.*]] = load double, ptr [[DE]], align 8
54535 // SIMD-ONLY0-NEXT:    [[CMP6747:%.*]] = fcmp oeq double [[TMP5271]], [[TMP5272]]
54536 // SIMD-ONLY0-NEXT:    br i1 [[CMP6747]], label [[IF_THEN6749:%.*]], label [[IF_END6750:%.*]]
54537 // SIMD-ONLY0:       if.then6749:
54538 // SIMD-ONLY0-NEXT:    [[TMP5273:%.*]] = load double, ptr [[DD]], align 8
54539 // SIMD-ONLY0-NEXT:    store double [[TMP5273]], ptr [[DX]], align 8
54540 // SIMD-ONLY0-NEXT:    br label [[IF_END6750]]
54541 // SIMD-ONLY0:       if.end6750:
54542 // SIMD-ONLY0-NEXT:    [[TMP5274:%.*]] = load double, ptr [[DX]], align 8
54543 // SIMD-ONLY0-NEXT:    store double [[TMP5274]], ptr [[DV]], align 8
54544 // SIMD-ONLY0-NEXT:    [[TMP5275:%.*]] = load double, ptr [[DE]], align 8
54545 // SIMD-ONLY0-NEXT:    [[TMP5276:%.*]] = load double, ptr [[DX]], align 8
54546 // SIMD-ONLY0-NEXT:    [[CMP6751:%.*]] = fcmp oeq double [[TMP5275]], [[TMP5276]]
54547 // SIMD-ONLY0-NEXT:    br i1 [[CMP6751]], label [[IF_THEN6753:%.*]], label [[IF_END6754:%.*]]
54548 // SIMD-ONLY0:       if.then6753:
54549 // SIMD-ONLY0-NEXT:    [[TMP5277:%.*]] = load double, ptr [[DD]], align 8
54550 // SIMD-ONLY0-NEXT:    store double [[TMP5277]], ptr [[DX]], align 8
54551 // SIMD-ONLY0-NEXT:    br label [[IF_END6754]]
54552 // SIMD-ONLY0:       if.end6754:
54553 // SIMD-ONLY0-NEXT:    [[TMP5278:%.*]] = load double, ptr [[DE]], align 8
54554 // SIMD-ONLY0-NEXT:    [[TMP5279:%.*]] = load double, ptr [[DX]], align 8
54555 // SIMD-ONLY0-NEXT:    [[CMP6755:%.*]] = fcmp ogt double [[TMP5278]], [[TMP5279]]
54556 // SIMD-ONLY0-NEXT:    br i1 [[CMP6755]], label [[IF_THEN6757:%.*]], label [[IF_END6758:%.*]]
54557 // SIMD-ONLY0:       if.then6757:
54558 // SIMD-ONLY0-NEXT:    [[TMP5280:%.*]] = load double, ptr [[DE]], align 8
54559 // SIMD-ONLY0-NEXT:    store double [[TMP5280]], ptr [[DX]], align 8
54560 // SIMD-ONLY0-NEXT:    br label [[IF_END6758]]
54561 // SIMD-ONLY0:       if.end6758:
54562 // SIMD-ONLY0-NEXT:    [[TMP5281:%.*]] = load double, ptr [[DX]], align 8
54563 // SIMD-ONLY0-NEXT:    store double [[TMP5281]], ptr [[DV]], align 8
54564 // SIMD-ONLY0-NEXT:    [[TMP5282:%.*]] = load double, ptr [[DX]], align 8
54565 // SIMD-ONLY0-NEXT:    [[TMP5283:%.*]] = load double, ptr [[DE]], align 8
54566 // SIMD-ONLY0-NEXT:    [[CMP6759:%.*]] = fcmp ogt double [[TMP5282]], [[TMP5283]]
54567 // SIMD-ONLY0-NEXT:    br i1 [[CMP6759]], label [[IF_THEN6761:%.*]], label [[IF_END6762:%.*]]
54568 // SIMD-ONLY0:       if.then6761:
54569 // SIMD-ONLY0-NEXT:    [[TMP5284:%.*]] = load double, ptr [[DE]], align 8
54570 // SIMD-ONLY0-NEXT:    store double [[TMP5284]], ptr [[DX]], align 8
54571 // SIMD-ONLY0-NEXT:    br label [[IF_END6762]]
54572 // SIMD-ONLY0:       if.end6762:
54573 // SIMD-ONLY0-NEXT:    [[TMP5285:%.*]] = load double, ptr [[DX]], align 8
54574 // SIMD-ONLY0-NEXT:    store double [[TMP5285]], ptr [[DV]], align 8
54575 // SIMD-ONLY0-NEXT:    [[TMP5286:%.*]] = load double, ptr [[DE]], align 8
54576 // SIMD-ONLY0-NEXT:    [[TMP5287:%.*]] = load double, ptr [[DX]], align 8
54577 // SIMD-ONLY0-NEXT:    [[CMP6763:%.*]] = fcmp olt double [[TMP5286]], [[TMP5287]]
54578 // SIMD-ONLY0-NEXT:    br i1 [[CMP6763]], label [[IF_THEN6765:%.*]], label [[IF_END6766:%.*]]
54579 // SIMD-ONLY0:       if.then6765:
54580 // SIMD-ONLY0-NEXT:    [[TMP5288:%.*]] = load double, ptr [[DE]], align 8
54581 // SIMD-ONLY0-NEXT:    store double [[TMP5288]], ptr [[DX]], align 8
54582 // SIMD-ONLY0-NEXT:    br label [[IF_END6766]]
54583 // SIMD-ONLY0:       if.end6766:
54584 // SIMD-ONLY0-NEXT:    [[TMP5289:%.*]] = load double, ptr [[DX]], align 8
54585 // SIMD-ONLY0-NEXT:    store double [[TMP5289]], ptr [[DV]], align 8
54586 // SIMD-ONLY0-NEXT:    [[TMP5290:%.*]] = load double, ptr [[DX]], align 8
54587 // SIMD-ONLY0-NEXT:    [[TMP5291:%.*]] = load double, ptr [[DE]], align 8
54588 // SIMD-ONLY0-NEXT:    [[CMP6767:%.*]] = fcmp olt double [[TMP5290]], [[TMP5291]]
54589 // SIMD-ONLY0-NEXT:    br i1 [[CMP6767]], label [[IF_THEN6769:%.*]], label [[IF_END6770:%.*]]
54590 // SIMD-ONLY0:       if.then6769:
54591 // SIMD-ONLY0-NEXT:    [[TMP5292:%.*]] = load double, ptr [[DE]], align 8
54592 // SIMD-ONLY0-NEXT:    store double [[TMP5292]], ptr [[DX]], align 8
54593 // SIMD-ONLY0-NEXT:    br label [[IF_END6770]]
54594 // SIMD-ONLY0:       if.end6770:
54595 // SIMD-ONLY0-NEXT:    [[TMP5293:%.*]] = load double, ptr [[DX]], align 8
54596 // SIMD-ONLY0-NEXT:    store double [[TMP5293]], ptr [[DV]], align 8
54597 // SIMD-ONLY0-NEXT:    [[TMP5294:%.*]] = load double, ptr [[DX]], align 8
54598 // SIMD-ONLY0-NEXT:    [[TMP5295:%.*]] = load double, ptr [[DE]], align 8
54599 // SIMD-ONLY0-NEXT:    [[CMP6771:%.*]] = fcmp oeq double [[TMP5294]], [[TMP5295]]
54600 // SIMD-ONLY0-NEXT:    br i1 [[CMP6771]], label [[IF_THEN6773:%.*]], label [[IF_END6774:%.*]]
54601 // SIMD-ONLY0:       if.then6773:
54602 // SIMD-ONLY0-NEXT:    [[TMP5296:%.*]] = load double, ptr [[DD]], align 8
54603 // SIMD-ONLY0-NEXT:    store double [[TMP5296]], ptr [[DX]], align 8
54604 // SIMD-ONLY0-NEXT:    br label [[IF_END6774]]
54605 // SIMD-ONLY0:       if.end6774:
54606 // SIMD-ONLY0-NEXT:    [[TMP5297:%.*]] = load double, ptr [[DX]], align 8
54607 // SIMD-ONLY0-NEXT:    store double [[TMP5297]], ptr [[DV]], align 8
54608 // SIMD-ONLY0-NEXT:    [[TMP5298:%.*]] = load double, ptr [[DE]], align 8
54609 // SIMD-ONLY0-NEXT:    [[TMP5299:%.*]] = load double, ptr [[DX]], align 8
54610 // SIMD-ONLY0-NEXT:    [[CMP6775:%.*]] = fcmp oeq double [[TMP5298]], [[TMP5299]]
54611 // SIMD-ONLY0-NEXT:    br i1 [[CMP6775]], label [[IF_THEN6777:%.*]], label [[IF_END6778:%.*]]
54612 // SIMD-ONLY0:       if.then6777:
54613 // SIMD-ONLY0-NEXT:    [[TMP5300:%.*]] = load double, ptr [[DD]], align 8
54614 // SIMD-ONLY0-NEXT:    store double [[TMP5300]], ptr [[DX]], align 8
54615 // SIMD-ONLY0-NEXT:    br label [[IF_END6778]]
54616 // SIMD-ONLY0:       if.end6778:
54617 // SIMD-ONLY0-NEXT:    [[TMP5301:%.*]] = load double, ptr [[DX]], align 8
54618 // SIMD-ONLY0-NEXT:    store double [[TMP5301]], ptr [[DV]], align 8
54619 // SIMD-ONLY0-NEXT:    [[TMP5302:%.*]] = load double, ptr [[DX]], align 8
54620 // SIMD-ONLY0-NEXT:    [[TMP5303:%.*]] = load double, ptr [[DE]], align 8
54621 // SIMD-ONLY0-NEXT:    [[CMP6779:%.*]] = fcmp oeq double [[TMP5302]], [[TMP5303]]
54622 // SIMD-ONLY0-NEXT:    br i1 [[CMP6779]], label [[IF_THEN6781:%.*]], label [[IF_ELSE6782:%.*]]
54623 // SIMD-ONLY0:       if.then6781:
54624 // SIMD-ONLY0-NEXT:    [[TMP5304:%.*]] = load double, ptr [[DD]], align 8
54625 // SIMD-ONLY0-NEXT:    store double [[TMP5304]], ptr [[DX]], align 8
54626 // SIMD-ONLY0-NEXT:    br label [[IF_END6783:%.*]]
54627 // SIMD-ONLY0:       if.else6782:
54628 // SIMD-ONLY0-NEXT:    [[TMP5305:%.*]] = load double, ptr [[DX]], align 8
54629 // SIMD-ONLY0-NEXT:    store double [[TMP5305]], ptr [[DV]], align 8
54630 // SIMD-ONLY0-NEXT:    br label [[IF_END6783]]
54631 // SIMD-ONLY0:       if.end6783:
54632 // SIMD-ONLY0-NEXT:    [[TMP5306:%.*]] = load double, ptr [[DE]], align 8
54633 // SIMD-ONLY0-NEXT:    [[TMP5307:%.*]] = load double, ptr [[DX]], align 8
54634 // SIMD-ONLY0-NEXT:    [[CMP6784:%.*]] = fcmp oeq double [[TMP5306]], [[TMP5307]]
54635 // SIMD-ONLY0-NEXT:    br i1 [[CMP6784]], label [[IF_THEN6786:%.*]], label [[IF_ELSE6787:%.*]]
54636 // SIMD-ONLY0:       if.then6786:
54637 // SIMD-ONLY0-NEXT:    [[TMP5308:%.*]] = load double, ptr [[DD]], align 8
54638 // SIMD-ONLY0-NEXT:    store double [[TMP5308]], ptr [[DX]], align 8
54639 // SIMD-ONLY0-NEXT:    br label [[IF_END6788:%.*]]
54640 // SIMD-ONLY0:       if.else6787:
54641 // SIMD-ONLY0-NEXT:    [[TMP5309:%.*]] = load double, ptr [[DX]], align 8
54642 // SIMD-ONLY0-NEXT:    store double [[TMP5309]], ptr [[DV]], align 8
54643 // SIMD-ONLY0-NEXT:    br label [[IF_END6788]]
54644 // SIMD-ONLY0:       if.end6788:
54645 // SIMD-ONLY0-NEXT:    [[TMP5310:%.*]] = load double, ptr [[DX]], align 8
54646 // SIMD-ONLY0-NEXT:    [[TMP5311:%.*]] = load double, ptr [[DE]], align 8
54647 // SIMD-ONLY0-NEXT:    [[CMP6789:%.*]] = fcmp oeq double [[TMP5310]], [[TMP5311]]
54648 // SIMD-ONLY0-NEXT:    [[CONV6790:%.*]] = zext i1 [[CMP6789]] to i32
54649 // SIMD-ONLY0-NEXT:    store i32 [[CONV6790]], ptr [[IR]], align 4
54650 // SIMD-ONLY0-NEXT:    [[TMP5312:%.*]] = load i32, ptr [[IR]], align 4
54651 // SIMD-ONLY0-NEXT:    [[TOBOOL6791:%.*]] = icmp ne i32 [[TMP5312]], 0
54652 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6791]], label [[IF_THEN6792:%.*]], label [[IF_END6793:%.*]]
54653 // SIMD-ONLY0:       if.then6792:
54654 // SIMD-ONLY0-NEXT:    [[TMP5313:%.*]] = load double, ptr [[DD]], align 8
54655 // SIMD-ONLY0-NEXT:    store double [[TMP5313]], ptr [[DX]], align 8
54656 // SIMD-ONLY0-NEXT:    br label [[IF_END6793]]
54657 // SIMD-ONLY0:       if.end6793:
54658 // SIMD-ONLY0-NEXT:    [[TMP5314:%.*]] = load double, ptr [[DE]], align 8
54659 // SIMD-ONLY0-NEXT:    [[TMP5315:%.*]] = load double, ptr [[DX]], align 8
54660 // SIMD-ONLY0-NEXT:    [[CMP6794:%.*]] = fcmp oeq double [[TMP5314]], [[TMP5315]]
54661 // SIMD-ONLY0-NEXT:    [[CONV6795:%.*]] = zext i1 [[CMP6794]] to i32
54662 // SIMD-ONLY0-NEXT:    store i32 [[CONV6795]], ptr [[IR]], align 4
54663 // SIMD-ONLY0-NEXT:    [[TMP5316:%.*]] = load i32, ptr [[IR]], align 4
54664 // SIMD-ONLY0-NEXT:    [[TOBOOL6796:%.*]] = icmp ne i32 [[TMP5316]], 0
54665 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6796]], label [[IF_THEN6797:%.*]], label [[IF_END6798:%.*]]
54666 // SIMD-ONLY0:       if.then6797:
54667 // SIMD-ONLY0-NEXT:    [[TMP5317:%.*]] = load double, ptr [[DD]], align 8
54668 // SIMD-ONLY0-NEXT:    store double [[TMP5317]], ptr [[DX]], align 8
54669 // SIMD-ONLY0-NEXT:    br label [[IF_END6798]]
54670 // SIMD-ONLY0:       if.end6798:
54671 // SIMD-ONLY0-NEXT:    [[TMP5318:%.*]] = load double, ptr [[DX]], align 8
54672 // SIMD-ONLY0-NEXT:    [[TMP5319:%.*]] = load double, ptr [[DE]], align 8
54673 // SIMD-ONLY0-NEXT:    [[CMP6799:%.*]] = fcmp oeq double [[TMP5318]], [[TMP5319]]
54674 // SIMD-ONLY0-NEXT:    [[CONV6800:%.*]] = zext i1 [[CMP6799]] to i32
54675 // SIMD-ONLY0-NEXT:    store i32 [[CONV6800]], ptr [[IR]], align 4
54676 // SIMD-ONLY0-NEXT:    [[TMP5320:%.*]] = load i32, ptr [[IR]], align 4
54677 // SIMD-ONLY0-NEXT:    [[TOBOOL6801:%.*]] = icmp ne i32 [[TMP5320]], 0
54678 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6801]], label [[IF_THEN6802:%.*]], label [[IF_ELSE6803:%.*]]
54679 // SIMD-ONLY0:       if.then6802:
54680 // SIMD-ONLY0-NEXT:    [[TMP5321:%.*]] = load double, ptr [[DD]], align 8
54681 // SIMD-ONLY0-NEXT:    store double [[TMP5321]], ptr [[DX]], align 8
54682 // SIMD-ONLY0-NEXT:    br label [[IF_END6804:%.*]]
54683 // SIMD-ONLY0:       if.else6803:
54684 // SIMD-ONLY0-NEXT:    [[TMP5322:%.*]] = load double, ptr [[DX]], align 8
54685 // SIMD-ONLY0-NEXT:    store double [[TMP5322]], ptr [[DV]], align 8
54686 // SIMD-ONLY0-NEXT:    br label [[IF_END6804]]
54687 // SIMD-ONLY0:       if.end6804:
54688 // SIMD-ONLY0-NEXT:    [[TMP5323:%.*]] = load double, ptr [[DE]], align 8
54689 // SIMD-ONLY0-NEXT:    [[TMP5324:%.*]] = load double, ptr [[DX]], align 8
54690 // SIMD-ONLY0-NEXT:    [[CMP6805:%.*]] = fcmp oeq double [[TMP5323]], [[TMP5324]]
54691 // SIMD-ONLY0-NEXT:    [[CONV6806:%.*]] = zext i1 [[CMP6805]] to i32
54692 // SIMD-ONLY0-NEXT:    store i32 [[CONV6806]], ptr [[IR]], align 4
54693 // SIMD-ONLY0-NEXT:    [[TMP5325:%.*]] = load i32, ptr [[IR]], align 4
54694 // SIMD-ONLY0-NEXT:    [[TOBOOL6807:%.*]] = icmp ne i32 [[TMP5325]], 0
54695 // SIMD-ONLY0-NEXT:    br i1 [[TOBOOL6807]], label [[IF_THEN6808:%.*]], label [[IF_ELSE6809:%.*]]
54696 // SIMD-ONLY0:       if.then6808:
54697 // SIMD-ONLY0-NEXT:    [[TMP5326:%.*]] = load double, ptr [[DD]], align 8
54698 // SIMD-ONLY0-NEXT:    store double [[TMP5326]], ptr [[DX]], align 8
54699 // SIMD-ONLY0-NEXT:    br label [[IF_END6810:%.*]]
54700 // SIMD-ONLY0:       if.else6809:
54701 // SIMD-ONLY0-NEXT:    [[TMP5327:%.*]] = load double, ptr [[DX]], align 8
54702 // SIMD-ONLY0-NEXT:    store double [[TMP5327]], ptr [[DV]], align 8
54703 // SIMD-ONLY0-NEXT:    br label [[IF_END6810]]
54704 // SIMD-ONLY0:       if.end6810:
54705 // SIMD-ONLY0-NEXT:    ret void
54706 //
54707 //
54708 // SIMD-ONLY0-LABEL: @cxevd(
54709 // SIMD-ONLY0-NEXT:  entry:
54710 // SIMD-ONLY0-NEXT:    [[CX:%.*]] = alloca i8, align 1
54711 // SIMD-ONLY0-NEXT:    [[CV:%.*]] = alloca i8, align 1
54712 // SIMD-ONLY0-NEXT:    [[CE:%.*]] = alloca i8, align 1
54713 // SIMD-ONLY0-NEXT:    [[CD:%.*]] = alloca i8, align 1
54714 // SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = load i8, ptr [[CX]], align 1
54715 // SIMD-ONLY0-NEXT:    store i8 [[TMP0]], ptr [[CV]], align 1
54716 // SIMD-ONLY0-NEXT:    [[TMP1:%.*]] = load i8, ptr [[CX]], align 1
54717 // SIMD-ONLY0-NEXT:    [[CONV:%.*]] = sext i8 [[TMP1]] to i32
54718 // SIMD-ONLY0-NEXT:    [[TMP2:%.*]] = load i8, ptr [[CE]], align 1
54719 // SIMD-ONLY0-NEXT:    [[CONV1:%.*]] = sext i8 [[TMP2]] to i32
54720 // SIMD-ONLY0-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[CONV]], [[CONV1]]
54721 // SIMD-ONLY0-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
54722 // SIMD-ONLY0:       cond.true:
54723 // SIMD-ONLY0-NEXT:    [[TMP3:%.*]] = load i8, ptr [[CE]], align 1
54724 // SIMD-ONLY0-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
54725 // SIMD-ONLY0-NEXT:    br label [[COND_END:%.*]]
54726 // SIMD-ONLY0:       cond.false:
54727 // SIMD-ONLY0-NEXT:    [[TMP4:%.*]] = load i8, ptr [[CX]], align 1
54728 // SIMD-ONLY0-NEXT:    [[CONV4:%.*]] = sext i8 [[TMP4]] to i32
54729 // SIMD-ONLY0-NEXT:    br label [[COND_END]]
54730 // SIMD-ONLY0:       cond.end:
54731 // SIMD-ONLY0-NEXT:    [[COND:%.*]] = phi i32 [ [[CONV3]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ]
54732 // SIMD-ONLY0-NEXT:    [[CONV5:%.*]] = trunc i32 [[COND]] to i8
54733 // SIMD-ONLY0-NEXT:    store i8 [[CONV5]], ptr [[CX]], align 1
54734 // SIMD-ONLY0-NEXT:    [[TMP5:%.*]] = load i8, ptr [[CX]], align 1
54735 // SIMD-ONLY0-NEXT:    store i8 [[TMP5]], ptr [[CV]], align 1
54736 // SIMD-ONLY0-NEXT:    [[TMP6:%.*]] = load i8, ptr [[CX]], align 1
54737 // SIMD-ONLY0-NEXT:    [[CONV6:%.*]] = sext i8 [[TMP6]] to i32
54738 // SIMD-ONLY0-NEXT:    [[TMP7:%.*]] = load i8, ptr [[CE]], align 1
54739 // SIMD-ONLY0-NEXT:    [[CONV7:%.*]] = sext i8 [[TMP7]] to i32
54740 // SIMD-ONLY0-NEXT:    [[CMP8:%.*]] = icmp slt i32 [[CONV6]], [[CONV7]]
54741 // SIMD-ONLY0-NEXT:    br i1 [[CMP8]], label [[COND_TRUE10:%.*]], label [[COND_FALSE12:%.*]]
54742 // SIMD-ONLY0:       cond.true10:
54743 // SIMD-ONLY0-NEXT:    [[TMP8:%.*]] = load i8, ptr [[CE]], align 1
54744 // SIMD-ONLY0-NEXT:    [[CONV11:%.*]] = sext i8 [[TMP8]] to i32
54745 // SIMD-ONLY0-NEXT:    br label [[COND_END14:%.*]]
54746 // SIMD-ONLY0:       cond.false12:
54747 // SIMD-ONLY0-NEXT:    [[TMP9:%.*]] = load i8, ptr [[CX]], align 1
54748 // SIMD-ONLY0-NEXT:    [[CONV13:%.*]] = sext i8 [[TMP9]] to i32
54749 // SIMD-ONLY0-NEXT:    br label [[COND_END14]]
54750 // SIMD-ONLY0:       cond.end14:
54751 // SIMD-ONLY0-NEXT:    [[COND15:%.*]] = phi i32 [ [[CONV11]], [[COND_TRUE10]] ], [ [[CONV13]], [[COND_FALSE12]] ]
54752 // SIMD-ONLY0-NEXT:    [[CONV16:%.*]] = trunc i32 [[COND15]] to i8
54753 // SIMD-ONLY0-NEXT:    store i8 [[CONV16]], ptr [[CX]], align 1
54754 // SIMD-ONLY0-NEXT:    [[TMP10:%.*]] = load i8, ptr [[CX]], align 1
54755 // SIMD-ONLY0-NEXT:    store i8 [[TMP10]], ptr [[CV]], align 1
54756 // SIMD-ONLY0-NEXT:    [[TMP11:%.*]] = load i8, ptr [[CX]], align 1
54757 // SIMD-ONLY0-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP11]] to i32
54758 // SIMD-ONLY0-NEXT:    [[TMP12:%.*]] = load i8, ptr [[CE]], align 1
54759 // SIMD-ONLY0-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP12]] to i32
54760 // SIMD-ONLY0-NEXT:    [[CMP19:%.*]] = icmp eq i32 [[CONV17]], [[CONV18]]
54761 // SIMD-ONLY0-NEXT:    br i1 [[CMP19]], label [[COND_TRUE21:%.*]], label [[COND_FALSE23:%.*]]
54762 // SIMD-ONLY0:       cond.true21:
54763 // SIMD-ONLY0-NEXT:    [[TMP13:%.*]] = load i8, ptr [[CD]], align 1
54764 // SIMD-ONLY0-NEXT:    [[CONV22:%.*]] = sext i8 [[TMP13]] to i32
54765 // SIMD-ONLY0-NEXT:    br label [[COND_END25:%.*]]
54766 // SIMD-ONLY0:       cond.false23:
54767 // SIMD-ONLY0-NEXT:    [[TMP14:%.*]] = load i8, ptr [[CX]], align 1
54768 // SIMD-ONLY0-NEXT:    [[CONV24:%.*]] = sext i8 [[TMP14]] to i32
54769 // SIMD-ONLY0-NEXT:    br label [[COND_END25]]
54770 // SIMD-ONLY0:       cond.end25:
54771 // SIMD-ONLY0-NEXT:    [[COND26:%.*]] = phi i32 [ [[CONV22]], [[COND_TRUE21]] ], [ [[CONV24]], [[COND_FALSE23]] ]
54772 // SIMD-ONLY0-NEXT:    [[CONV27:%.*]] = trunc i32 [[COND26]] to i8
54773 // SIMD-ONLY0-NEXT:    store i8 [[CONV27]], ptr [[CX]], align 1
54774 // SIMD-ONLY0-NEXT:    [[TMP15:%.*]] = load i8, ptr [[CX]], align 1
54775 // SIMD-ONLY0-NEXT:    [[CONV28:%.*]] = sext i8 [[TMP15]] to i32
54776 // SIMD-ONLY0-NEXT:    [[TMP16:%.*]] = load i8, ptr [[CE]], align 1
54777 // SIMD-ONLY0-NEXT:    [[CONV29:%.*]] = sext i8 [[TMP16]] to i32
54778 // SIMD-ONLY0-NEXT:    [[CMP30:%.*]] = icmp sgt i32 [[CONV28]], [[CONV29]]
54779 // SIMD-ONLY0-NEXT:    br i1 [[CMP30]], label [[COND_TRUE32:%.*]], label [[COND_FALSE34:%.*]]
54780 // SIMD-ONLY0:       cond.true32:
54781 // SIMD-ONLY0-NEXT:    [[TMP17:%.*]] = load i8, ptr [[CE]], align 1
54782 // SIMD-ONLY0-NEXT:    [[CONV33:%.*]] = sext i8 [[TMP17]] to i32
54783 // SIMD-ONLY0-NEXT:    br label [[COND_END36:%.*]]
54784 // SIMD-ONLY0:       cond.false34:
54785 // SIMD-ONLY0-NEXT:    [[TMP18:%.*]] = load i8, ptr [[CX]], align 1
54786 // SIMD-ONLY0-NEXT:    [[CONV35:%.*]] = sext i8 [[TMP18]] to i32
54787 // SIMD-ONLY0-NEXT:    br label [[COND_END36]]
54788 // SIMD-ONLY0:       cond.end36:
54789 // SIMD-ONLY0-NEXT:    [[COND37:%.*]] = phi i32 [ [[CONV33]], [[COND_TRUE32]] ], [ [[CONV35]], [[COND_FALSE34]] ]
54790 // SIMD-ONLY0-NEXT:    [[CONV38:%.*]] = trunc i32 [[COND37]] to i8
54791 // SIMD-ONLY0-NEXT:    store i8 [[CONV38]], ptr [[CX]], align 1
54792 // SIMD-ONLY0-NEXT:    [[TMP19:%.*]] = load i8, ptr [[CX]], align 1
54793 // SIMD-ONLY0-NEXT:    store i8 [[TMP19]], ptr [[CV]], align 1
54794 // SIMD-ONLY0-NEXT:    [[TMP20:%.*]] = load i8, ptr [[CX]], align 1
54795 // SIMD-ONLY0-NEXT:    [[CONV39:%.*]] = sext i8 [[TMP20]] to i32
54796 // SIMD-ONLY0-NEXT:    [[TMP21:%.*]] = load i8, ptr [[CE]], align 1
54797 // SIMD-ONLY0-NEXT:    [[CONV40:%.*]] = sext i8 [[TMP21]] to i32
54798 // SIMD-ONLY0-NEXT:    [[CMP41:%.*]] = icmp slt i32 [[CONV39]], [[CONV40]]
54799 // SIMD-ONLY0-NEXT:    br i1 [[CMP41]], label [[COND_TRUE43:%.*]], label [[COND_FALSE45:%.*]]
54800 // SIMD-ONLY0:       cond.true43:
54801 // SIMD-ONLY0-NEXT:    [[TMP22:%.*]] = load i8, ptr [[CE]], align 1
54802 // SIMD-ONLY0-NEXT:    [[CONV44:%.*]] = sext i8 [[TMP22]] to i32
54803 // SIMD-ONLY0-NEXT:    br label [[COND_END47:%.*]]
54804 // SIMD-ONLY0:       cond.false45:
54805 // SIMD-ONLY0-NEXT:    [[TMP23:%.*]] = load i8, ptr [[CX]], align 1
54806 // SIMD-ONLY0-NEXT:    [[CONV46:%.*]] = sext i8 [[TMP23]] to i32
54807 // SIMD-ONLY0-NEXT:    br label [[COND_END47]]
54808 // SIMD-ONLY0:       cond.end47:
54809 // SIMD-ONLY0-NEXT:    [[COND48:%.*]] = phi i32 [ [[CONV44]], [[COND_TRUE43]] ], [ [[CONV46]], [[COND_FALSE45]] ]
54810 // SIMD-ONLY0-NEXT:    [[CONV49:%.*]] = trunc i32 [[COND48]] to i8
54811 // SIMD-ONLY0-NEXT:    store i8 [[CONV49]], ptr [[CX]], align 1
54812 // SIMD-ONLY0-NEXT:    [[TMP24:%.*]] = load i8, ptr [[CX]], align 1
54813 // SIMD-ONLY0-NEXT:    store i8 [[TMP24]], ptr [[CV]], align 1
54814 // SIMD-ONLY0-NEXT:    [[TMP25:%.*]] = load i8, ptr [[CX]], align 1
54815 // SIMD-ONLY0-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP25]] to i32
54816 // SIMD-ONLY0-NEXT:    [[TMP26:%.*]] = load i8, ptr [[CE]], align 1
54817 // SIMD-ONLY0-NEXT:    [[CONV51:%.*]] = sext i8 [[TMP26]] to i32
54818 // SIMD-ONLY0-NEXT:    [[CMP52:%.*]] = icmp eq i32 [[CONV50]], [[CONV51]]
54819 // SIMD-ONLY0-NEXT:    br i1 [[CMP52]], label [[COND_TRUE54:%.*]], label [[COND_FALSE56:%.*]]
54820 // SIMD-ONLY0:       cond.true54:
54821 // SIMD-ONLY0-NEXT:    [[TMP27:%.*]] = load i8, ptr [[CD]], align 1
54822 // SIMD-ONLY0-NEXT:    [[CONV55:%.*]] = sext i8 [[TMP27]] to i32
54823 // SIMD-ONLY0-NEXT:    br label [[COND_END58:%.*]]
54824 // SIMD-ONLY0:       cond.false56:
54825 // SIMD-ONLY0-NEXT:    [[TMP28:%.*]] = load i8, ptr [[CX]], align 1
54826 // SIMD-ONLY0-NEXT:    [[CONV57:%.*]] = sext i8 [[TMP28]] to i32
54827 // SIMD-ONLY0-NEXT:    br label [[COND_END58]]
54828 // SIMD-ONLY0:       cond.end58:
54829 // SIMD-ONLY0-NEXT:    [[COND59:%.*]] = phi i32 [ [[CONV55]], [[COND_TRUE54]] ], [ [[CONV57]], [[COND_FALSE56]] ]
54830 // SIMD-ONLY0-NEXT:    [[CONV60:%.*]] = trunc i32 [[COND59]] to i8
54831 // SIMD-ONLY0-NEXT:    store i8 [[CONV60]], ptr [[CX]], align 1
54832 // SIMD-ONLY0-NEXT:    [[TMP29:%.*]] = load i8, ptr [[CX]], align 1
54833 // SIMD-ONLY0-NEXT:    store i8 [[TMP29]], ptr [[CV]], align 1
54834 // SIMD-ONLY0-NEXT:    [[TMP30:%.*]] = load i8, ptr [[CX]], align 1
54835 // SIMD-ONLY0-NEXT:    store i8 [[TMP30]], ptr [[CV]], align 1
54836 // SIMD-ONLY0-NEXT:    [[TMP31:%.*]] = load i8, ptr [[CX]], align 1
54837 // SIMD-ONLY0-NEXT:    [[CONV61:%.*]] = sext i8 [[TMP31]] to i32
54838 // SIMD-ONLY0-NEXT:    [[TMP32:%.*]] = load i8, ptr [[CE]], align 1
54839 // SIMD-ONLY0-NEXT:    [[CONV62:%.*]] = sext i8 [[TMP32]] to i32
54840 // SIMD-ONLY0-NEXT:    [[CMP63:%.*]] = icmp sgt i32 [[CONV61]], [[CONV62]]
54841 // SIMD-ONLY0-NEXT:    br i1 [[CMP63]], label [[COND_TRUE65:%.*]], label [[COND_FALSE67:%.*]]
54842 // SIMD-ONLY0:       cond.true65:
54843 // SIMD-ONLY0-NEXT:    [[TMP33:%.*]] = load i8, ptr [[CE]], align 1
54844 // SIMD-ONLY0-NEXT:    [[CONV66:%.*]] = sext i8 [[TMP33]] to i32
54845 // SIMD-ONLY0-NEXT:    br label [[COND_END69:%.*]]
54846 // SIMD-ONLY0:       cond.false67:
54847 // SIMD-ONLY0-NEXT:    [[TMP34:%.*]] = load i8, ptr [[CX]], align 1
54848 // SIMD-ONLY0-NEXT:    [[CONV68:%.*]] = sext i8 [[TMP34]] to i32
54849 // SIMD-ONLY0-NEXT:    br label [[COND_END69]]
54850 // SIMD-ONLY0:       cond.end69:
54851 // SIMD-ONLY0-NEXT:    [[COND70:%.*]] = phi i32 [ [[CONV66]], [[COND_TRUE65]] ], [ [[CONV68]], [[COND_FALSE67]] ]
54852 // SIMD-ONLY0-NEXT:    [[CONV71:%.*]] = trunc i32 [[COND70]] to i8
54853 // SIMD-ONLY0-NEXT:    store i8 [[CONV71]], ptr [[CX]], align 1
54854 // SIMD-ONLY0-NEXT:    [[TMP35:%.*]] = load i8, ptr [[CX]], align 1
54855 // SIMD-ONLY0-NEXT:    store i8 [[TMP35]], ptr [[CV]], align 1
54856 // SIMD-ONLY0-NEXT:    [[TMP36:%.*]] = load i8, ptr [[CX]], align 1
54857 // SIMD-ONLY0-NEXT:    [[CONV72:%.*]] = sext i8 [[TMP36]] to i32
54858 // SIMD-ONLY0-NEXT:    [[TMP37:%.*]] = load i8, ptr [[CE]], align 1
54859 // SIMD-ONLY0-NEXT:    [[CONV73:%.*]] = sext i8 [[TMP37]] to i32
54860 // SIMD-ONLY0-NEXT:    [[CMP74:%.*]] = icmp slt i32 [[CONV72]], [[CONV73]]
54861 // SIMD-ONLY0-NEXT:    br i1 [[CMP74]], label [[COND_TRUE76:%.*]], label [[COND_FALSE78:%.*]]
54862 // SIMD-ONLY0:       cond.true76:
54863 // SIMD-ONLY0-NEXT:    [[TMP38:%.*]] = load i8, ptr [[CE]], align 1
54864 // SIMD-ONLY0-NEXT:    [[CONV77:%.*]] = sext i8 [[TMP38]] to i32
54865 // SIMD-ONLY0-NEXT:    br label [[COND_END80:%.*]]
54866 // SIMD-ONLY0:       cond.false78:
54867 // SIMD-ONLY0-NEXT:    [[TMP39:%.*]] = load i8, ptr [[CX]], align 1
54868 // SIMD-ONLY0-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP39]] to i32
54869 // SIMD-ONLY0-NEXT:    br label [[COND_END80]]
54870 // SIMD-ONLY0:       cond.end80:
54871 // SIMD-ONLY0-NEXT:    [[COND81:%.*]] = phi i32 [ [[CONV77]], [[COND_TRUE76]] ], [ [[CONV79]], [[COND_FALSE78]] ]
54872 // SIMD-ONLY0-NEXT:    [[CONV82:%.*]] = trunc i32 [[COND81]] to i8
54873 // SIMD-ONLY0-NEXT:    store i8 [[CONV82]], ptr [[CX]], align 1
54874 // SIMD-ONLY0-NEXT:    [[TMP40:%.*]] = load i8, ptr [[CX]], align 1
54875 // SIMD-ONLY0-NEXT:    store i8 [[TMP40]], ptr [[CV]], align 1
54876 // SIMD-ONLY0-NEXT:    [[TMP41:%.*]] = load i8, ptr [[CX]], align 1
54877 // SIMD-ONLY0-NEXT:    [[CONV83:%.*]] = sext i8 [[TMP41]] to i32
54878 // SIMD-ONLY0-NEXT:    [[TMP42:%.*]] = load i8, ptr [[CE]], align 1
54879 // SIMD-ONLY0-NEXT:    [[CONV84:%.*]] = sext i8 [[TMP42]] to i32
54880 // SIMD-ONLY0-NEXT:    [[CMP85:%.*]] = icmp eq i32 [[CONV83]], [[CONV84]]
54881 // SIMD-ONLY0-NEXT:    br i1 [[CMP85]], label [[COND_TRUE87:%.*]], label [[COND_FALSE89:%.*]]
54882 // SIMD-ONLY0:       cond.true87:
54883 // SIMD-ONLY0-NEXT:    [[TMP43:%.*]] = load i8, ptr [[CD]], align 1
54884 // SIMD-ONLY0-NEXT:    [[CONV88:%.*]] = sext i8 [[TMP43]] to i32
54885 // SIMD-ONLY0-NEXT:    br label [[COND_END91:%.*]]
54886 // SIMD-ONLY0:       cond.false89:
54887 // SIMD-ONLY0-NEXT:    [[TMP44:%.*]] = load i8, ptr [[CX]], align 1
54888 // SIMD-ONLY0-NEXT:    [[CONV90:%.*]] = sext i8 [[TMP44]] to i32
54889 // SIMD-ONLY0-NEXT:    br label [[COND_END91]]
54890 // SIMD-ONLY0:       cond.end91:
54891 // SIMD-ONLY0-NEXT:    [[COND92:%.*]] = phi i32 [ [[CONV88]], [[COND_TRUE87]] ], [ [[CONV90]], [[COND_FALSE89]] ]
54892 // SIMD-ONLY0-NEXT:    [[CONV93:%.*]] = trunc i32 [[COND92]] to i8
54893 // SIMD-ONLY0-NEXT:    store i8 [[CONV93]], ptr [[CX]], align 1
54894 // SIMD-ONLY0-NEXT:    [[TMP45:%.*]] = load i8, ptr [[CX]], align 1
54895 // SIMD-ONLY0-NEXT:    [[CONV94:%.*]] = sext i8 [[TMP45]] to i32
54896 // SIMD-ONLY0-NEXT:    [[TMP46:%.*]] = load i8, ptr [[CE]], align 1
54897 // SIMD-ONLY0-NEXT:    [[CONV95:%.*]] = sext i8 [[TMP46]] to i32
54898 // SIMD-ONLY0-NEXT:    [[CMP96:%.*]] = icmp sgt i32 [[CONV94]], [[CONV95]]
54899 // SIMD-ONLY0-NEXT:    br i1 [[CMP96]], label [[COND_TRUE98:%.*]], label [[COND_FALSE100:%.*]]
54900 // SIMD-ONLY0:       cond.true98:
54901 // SIMD-ONLY0-NEXT:    [[TMP47:%.*]] = load i8, ptr [[CE]], align 1
54902 // SIMD-ONLY0-NEXT:    [[CONV99:%.*]] = sext i8 [[TMP47]] to i32
54903 // SIMD-ONLY0-NEXT:    br label [[COND_END102:%.*]]
54904 // SIMD-ONLY0:       cond.false100:
54905 // SIMD-ONLY0-NEXT:    [[TMP48:%.*]] = load i8, ptr [[CX]], align 1
54906 // SIMD-ONLY0-NEXT:    [[CONV101:%.*]] = sext i8 [[TMP48]] to i32
54907 // SIMD-ONLY0-NEXT:    br label [[COND_END102]]
54908 // SIMD-ONLY0:       cond.end102:
54909 // SIMD-ONLY0-NEXT:    [[COND103:%.*]] = phi i32 [ [[CONV99]], [[COND_TRUE98]] ], [ [[CONV101]], [[COND_FALSE100]] ]
54910 // SIMD-ONLY0-NEXT:    [[CONV104:%.*]] = trunc i32 [[COND103]] to i8
54911 // SIMD-ONLY0-NEXT:    store i8 [[CONV104]], ptr [[CX]], align 1
54912 // SIMD-ONLY0-NEXT:    [[TMP49:%.*]] = load i8, ptr [[CX]], align 1
54913 // SIMD-ONLY0-NEXT:    store i8 [[TMP49]], ptr [[CV]], align 1
54914 // SIMD-ONLY0-NEXT:    [[TMP50:%.*]] = load i8, ptr [[CX]], align 1
54915 // SIMD-ONLY0-NEXT:    [[CONV105:%.*]] = sext i8 [[TMP50]] to i32
54916 // SIMD-ONLY0-NEXT:    [[TMP51:%.*]] = load i8, ptr [[CE]], align 1
54917 // SIMD-ONLY0-NEXT:    [[CONV106:%.*]] = sext i8 [[TMP51]] to i32
54918 // SIMD-ONLY0-NEXT:    [[CMP107:%.*]] = icmp slt i32 [[CONV105]], [[CONV106]]
54919 // SIMD-ONLY0-NEXT:    br i1 [[CMP107]], label [[COND_TRUE109:%.*]], label [[COND_FALSE111:%.*]]
54920 // SIMD-ONLY0:       cond.true109:
54921 // SIMD-ONLY0-NEXT:    [[TMP52:%.*]] = load i8, ptr [[CE]], align 1
54922 // SIMD-ONLY0-NEXT:    [[CONV110:%.*]] = sext i8 [[TMP52]] to i32
54923 // SIMD-ONLY0-NEXT:    br label [[COND_END113:%.*]]
54924 // SIMD-ONLY0:       cond.false111:
54925 // SIMD-ONLY0-NEXT:    [[TMP53:%.*]] = load i8, ptr [[CX]], align 1
54926 // SIMD-ONLY0-NEXT:    [[CONV112:%.*]] = sext i8 [[TMP53]] to i32
54927 // SIMD-ONLY0-NEXT:    br label [[COND_END113]]
54928 // SIMD-ONLY0:       cond.end113:
54929 // SIMD-ONLY0-NEXT:    [[COND114:%.*]] = phi i32 [ [[CONV110]], [[COND_TRUE109]] ], [ [[CONV112]], [[COND_FALSE111]] ]
54930 // SIMD-ONLY0-NEXT:    [[CONV115:%.*]] = trunc i32 [[COND114]] to i8
54931 // SIMD-ONLY0-NEXT:    store i8 [[CONV115]], ptr [[CX]], align 1
54932 // SIMD-ONLY0-NEXT:    [[TMP54:%.*]] = load i8, ptr [[CX]], align 1
54933 // SIMD-ONLY0-NEXT:    store i8 [[TMP54]], ptr [[CV]], align 1
54934 // SIMD-ONLY0-NEXT:    [[TMP55:%.*]] = load i8, ptr [[CX]], align 1
54935 // SIMD-ONLY0-NEXT:    [[CONV116:%.*]] = sext i8 [[TMP55]] to i32
54936 // SIMD-ONLY0-NEXT:    [[TMP56:%.*]] = load i8, ptr [[CE]], align 1
54937 // SIMD-ONLY0-NEXT:    [[CONV117:%.*]] = sext i8 [[TMP56]] to i32
54938 // SIMD-ONLY0-NEXT:    [[CMP118:%.*]] = icmp eq i32 [[CONV116]], [[CONV117]]
54939 // SIMD-ONLY0-NEXT:    br i1 [[CMP118]], label [[COND_TRUE120:%.*]], label [[COND_FALSE122:%.*]]
54940 // SIMD-ONLY0:       cond.true120:
54941 // SIMD-ONLY0-NEXT:    [[TMP57:%.*]] = load i8, ptr [[CD]], align 1
54942 // SIMD-ONLY0-NEXT:    [[CONV121:%.*]] = sext i8 [[TMP57]] to i32
54943 // SIMD-ONLY0-NEXT:    br label [[COND_END124:%.*]]
54944 // SIMD-ONLY0:       cond.false122:
54945 // SIMD-ONLY0-NEXT:    [[TMP58:%.*]] = load i8, ptr [[CX]], align 1
54946 // SIMD-ONLY0-NEXT:    [[CONV123:%.*]] = sext i8 [[TMP58]] to i32
54947 // SIMD-ONLY0-NEXT:    br label [[COND_END124]]
54948 // SIMD-ONLY0:       cond.end124:
54949 // SIMD-ONLY0-NEXT:    [[COND125:%.*]] = phi i32 [ [[CONV121]], [[COND_TRUE120]] ], [ [[CONV123]], [[COND_FALSE122]] ]
54950 // SIMD-ONLY0-NEXT:    [[CONV126:%.*]] = trunc i32 [[COND125]] to i8
54951 // SIMD-ONLY0-NEXT:    store i8 [[CONV126]], ptr [[CX]], align 1
54952 // SIMD-ONLY0-NEXT:    [[TMP59:%.*]] = load i8, ptr [[CX]], align 1
54953 // SIMD-ONLY0-NEXT:    store i8 [[TMP59]], ptr [[CV]], align 1
54954 // SIMD-ONLY0-NEXT:    [[TMP60:%.*]] = load i8, ptr [[CX]], align 1
54955 // SIMD-ONLY0-NEXT:    store i8 [[TMP60]], ptr [[CV]], align 1
54956 // SIMD-ONLY0-NEXT:    [[TMP61:%.*]] = load i8, ptr [[CX]], align 1
54957 // SIMD-ONLY0-NEXT:    [[CONV127:%.*]] = sext i8 [[TMP61]] to i32
54958 // SIMD-ONLY0-NEXT:    [[TMP62:%.*]] = load i8, ptr [[CE]], align 1
54959 // SIMD-ONLY0-NEXT:    [[CONV128:%.*]] = sext i8 [[TMP62]] to i32
54960 // SIMD-ONLY0-NEXT:    [[CMP129:%.*]] = icmp sgt i32 [[CONV127]], [[CONV128]]
54961 // SIMD-ONLY0-NEXT:    br i1 [[CMP129]], label [[COND_TRUE131:%.*]], label [[COND_FALSE133:%.*]]
54962 // SIMD-ONLY0:       cond.true131:
54963 // SIMD-ONLY0-NEXT:    [[TMP63:%.*]] = load i8, ptr [[CE]], align 1
54964 // SIMD-ONLY0-NEXT:    [[CONV132:%.*]] = sext i8 [[TMP63]] to i32
54965 // SIMD-ONLY0-NEXT:    br label [[COND_END135:%.*]]
54966 // SIMD-ONLY0:       cond.false133:
54967 // SIMD-ONLY0-NEXT:    [[TMP64:%.*]] = load i8, ptr [[CX]], align 1
54968 // SIMD-ONLY0-NEXT:    [[CONV134:%.*]] = sext i8 [[TMP64]] to i32
54969 // SIMD-ONLY0-NEXT:    br label [[COND_END135]]
54970 // SIMD-ONLY0:       cond.end135:
54971 // SIMD-ONLY0-NEXT:    [[COND136:%.*]] = phi i32 [ [[CONV132]], [[COND_TRUE131]] ], [ [[CONV134]], [[COND_FALSE133]] ]
54972 // SIMD-ONLY0-NEXT:    [[CONV137:%.*]] = trunc i32 [[COND136]] to i8
54973 // SIMD-ONLY0-NEXT:    store i8 [[CONV137]], ptr [[CX]], align 1
54974 // SIMD-ONLY0-NEXT:    [[TMP65:%.*]] = load i8, ptr [[CX]], align 1
54975 // SIMD-ONLY0-NEXT:    store i8 [[TMP65]], ptr [[CV]], align 1
54976 // SIMD-ONLY0-NEXT:    [[TMP66:%.*]] = load i8, ptr [[CX]], align 1
54977 // SIMD-ONLY0-NEXT:    [[CONV138:%.*]] = sext i8 [[TMP66]] to i32
54978 // SIMD-ONLY0-NEXT:    [[TMP67:%.*]] = load i8, ptr [[CE]], align 1
54979 // SIMD-ONLY0-NEXT:    [[CONV139:%.*]] = sext i8 [[TMP67]] to i32
54980 // SIMD-ONLY0-NEXT:    [[CMP140:%.*]] = icmp slt i32 [[CONV138]], [[CONV139]]
54981 // SIMD-ONLY0-NEXT:    br i1 [[CMP140]], label [[COND_TRUE142:%.*]], label [[COND_FALSE144:%.*]]
54982 // SIMD-ONLY0:       cond.true142:
54983 // SIMD-ONLY0-NEXT:    [[TMP68:%.*]] = load i8, ptr [[CE]], align 1
54984 // SIMD-ONLY0-NEXT:    [[CONV143:%.*]] = sext i8 [[TMP68]] to i32
54985 // SIMD-ONLY0-NEXT:    br label [[COND_END146:%.*]]
54986 // SIMD-ONLY0:       cond.false144:
54987 // SIMD-ONLY0-NEXT:    [[TMP69:%.*]] = load i8, ptr [[CX]], align 1
54988 // SIMD-ONLY0-NEXT:    [[CONV145:%.*]] = sext i8 [[TMP69]] to i32
54989 // SIMD-ONLY0-NEXT:    br label [[COND_END146]]
54990 // SIMD-ONLY0:       cond.end146:
54991 // SIMD-ONLY0-NEXT:    [[COND147:%.*]] = phi i32 [ [[CONV143]], [[COND_TRUE142]] ], [ [[CONV145]], [[COND_FALSE144]] ]
54992 // SIMD-ONLY0-NEXT:    [[CONV148:%.*]] = trunc i32 [[COND147]] to i8
54993 // SIMD-ONLY0-NEXT:    store i8 [[CONV148]], ptr [[CX]], align 1
54994 // SIMD-ONLY0-NEXT:    [[TMP70:%.*]] = load i8, ptr [[CX]], align 1
54995 // SIMD-ONLY0-NEXT:    store i8 [[TMP70]], ptr [[CV]], align 1
54996 // SIMD-ONLY0-NEXT:    [[TMP71:%.*]] = load i8, ptr [[CX]], align 1
54997 // SIMD-ONLY0-NEXT:    [[CONV149:%.*]] = sext i8 [[TMP71]] to i32
54998 // SIMD-ONLY0-NEXT:    [[TMP72:%.*]] = load i8, ptr [[CE]], align 1
54999 // SIMD-ONLY0-NEXT:    [[CONV150:%.*]] = sext i8 [[TMP72]] to i32
55000 // SIMD-ONLY0-NEXT:    [[CMP151:%.*]] = icmp eq i32 [[CONV149]], [[CONV150]]
55001 // SIMD-ONLY0-NEXT:    br i1 [[CMP151]], label [[COND_TRUE153:%.*]], label [[COND_FALSE155:%.*]]
55002 // SIMD-ONLY0:       cond.true153:
55003 // SIMD-ONLY0-NEXT:    [[TMP73:%.*]] = load i8, ptr [[CD]], align 1
55004 // SIMD-ONLY0-NEXT:    [[CONV154:%.*]] = sext i8 [[TMP73]] to i32
55005 // SIMD-ONLY0-NEXT:    br label [[COND_END157:%.*]]
55006 // SIMD-ONLY0:       cond.false155:
55007 // SIMD-ONLY0-NEXT:    [[TMP74:%.*]] = load i8, ptr [[CX]], align 1
55008 // SIMD-ONLY0-NEXT:    [[CONV156:%.*]] = sext i8 [[TMP74]] to i32
55009 // SIMD-ONLY0-NEXT:    br label [[COND_END157]]
55010 // SIMD-ONLY0:       cond.end157:
55011 // SIMD-ONLY0-NEXT:    [[COND158:%.*]] = phi i32 [ [[CONV154]], [[COND_TRUE153]] ], [ [[CONV156]], [[COND_FALSE155]] ]
55012 // SIMD-ONLY0-NEXT:    [[CONV159:%.*]] = trunc i32 [[COND158]] to i8
55013 // SIMD-ONLY0-NEXT:    store i8 [[CONV159]], ptr [[CX]], align 1
55014 // SIMD-ONLY0-NEXT:    [[TMP75:%.*]] = load i8, ptr [[CX]], align 1
55015 // SIMD-ONLY0-NEXT:    [[CONV160:%.*]] = sext i8 [[TMP75]] to i32
55016 // SIMD-ONLY0-NEXT:    [[TMP76:%.*]] = load i8, ptr [[CE]], align 1
55017 // SIMD-ONLY0-NEXT:    [[CONV161:%.*]] = sext i8 [[TMP76]] to i32
55018 // SIMD-ONLY0-NEXT:    [[CMP162:%.*]] = icmp sgt i32 [[CONV160]], [[CONV161]]
55019 // SIMD-ONLY0-NEXT:    br i1 [[CMP162]], label [[COND_TRUE164:%.*]], label [[COND_FALSE166:%.*]]
55020 // SIMD-ONLY0:       cond.true164:
55021 // SIMD-ONLY0-NEXT:    [[TMP77:%.*]] = load i8, ptr [[CE]], align 1
55022 // SIMD-ONLY0-NEXT:    [[CONV165:%.*]] = sext i8 [[TMP77]] to i32
55023 // SIMD-ONLY0-NEXT:    br label [[COND_END168:%.*]]
55024 // SIMD-ONLY0:       cond.false166:
55025 // SIMD-ONLY0-NEXT:    [[TMP78:%.*]] = load i8, ptr [[CX]], align 1
55026 // SIMD-ONLY0-NEXT:    [[CONV167:%.*]] = sext i8 [[TMP78]] to i32
55027 // SIMD-ONLY0-NEXT:    br label [[COND_END168]]
55028 // SIMD-ONLY0:       cond.end168:
55029 // SIMD-ONLY0-NEXT:    [[COND169:%.*]] = phi i32 [ [[CONV165]], [[COND_TRUE164]] ], [ [[CONV167]], [[COND_FALSE166]] ]
55030 // SIMD-ONLY0-NEXT:    [[CONV170:%.*]] = trunc i32 [[COND169]] to i8
55031 // SIMD-ONLY0-NEXT:    store i8 [[CONV170]], ptr [[CX]], align 1
55032 // SIMD-ONLY0-NEXT:    [[TMP79:%.*]] = load i8, ptr [[CX]], align 1
55033 // SIMD-ONLY0-NEXT:    store i8 [[TMP79]], ptr [[CV]], align 1
55034 // SIMD-ONLY0-NEXT:    [[TMP80:%.*]] = load i8, ptr [[CX]], align 1
55035 // SIMD-ONLY0-NEXT:    [[CONV171:%.*]] = sext i8 [[TMP80]] to i32
55036 // SIMD-ONLY0-NEXT:    [[TMP81:%.*]] = load i8, ptr [[CE]], align 1
55037 // SIMD-ONLY0-NEXT:    [[CONV172:%.*]] = sext i8 [[TMP81]] to i32
55038 // SIMD-ONLY0-NEXT:    [[CMP173:%.*]] = icmp slt i32 [[CONV171]], [[CONV172]]
55039 // SIMD-ONLY0-NEXT:    br i1 [[CMP173]], label [[COND_TRUE175:%.*]], label [[COND_FALSE177:%.*]]
55040 // SIMD-ONLY0:       cond.true175:
55041 // SIMD-ONLY0-NEXT:    [[TMP82:%.*]] = load i8, ptr [[CE]], align 1
55042 // SIMD-ONLY0-NEXT:    [[CONV176:%.*]] = sext i8 [[TMP82]] to i32
55043 // SIMD-ONLY0-NEXT:    br label [[COND_END179:%.*]]
55044 // SIMD-ONLY0:       cond.false177:
55045 // SIMD-ONLY0-NEXT:    [[TMP83:%.*]] = load i8, ptr [[CX]], align 1
55046 // SIMD-ONLY0-NEXT:    [[CONV178:%.*]] = sext i8 [[TMP83]] to i32
55047 // SIMD-ONLY0-NEXT:    br label [[COND_END179]]
55048 // SIMD-ONLY0:       cond.end179:
55049 // SIMD-ONLY0-NEXT:    [[COND180:%.*]] = phi i32 [ [[CONV176]], [[COND_TRUE175]] ], [ [[CONV178]], [[COND_FALSE177]] ]
55050 // SIMD-ONLY0-NEXT:    [[CONV181:%.*]] = trunc i32 [[COND180]] to i8
55051 // SIMD-ONLY0-NEXT:    store i8 [[CONV181]], ptr [[CX]], align 1
55052 // SIMD-ONLY0-NEXT:    [[TMP84:%.*]] = load i8, ptr [[CX]], align 1
55053 // SIMD-ONLY0-NEXT:    store i8 [[TMP84]], ptr [[CV]], align 1
55054 // SIMD-ONLY0-NEXT:    [[TMP85:%.*]] = load i8, ptr [[CX]], align 1
55055 // SIMD-ONLY0-NEXT:    [[CONV182:%.*]] = sext i8 [[TMP85]] to i32
55056 // SIMD-ONLY0-NEXT:    [[TMP86:%.*]] = load i8, ptr [[CE]], align 1
55057 // SIMD-ONLY0-NEXT:    [[CONV183:%.*]] = sext i8 [[TMP86]] to i32
55058 // SIMD-ONLY0-NEXT:    [[CMP184:%.*]] = icmp eq i32 [[CONV182]], [[CONV183]]
55059 // SIMD-ONLY0-NEXT:    br i1 [[CMP184]], label [[COND_TRUE186:%.*]], label [[COND_FALSE188:%.*]]
55060 // SIMD-ONLY0:       cond.true186:
55061 // SIMD-ONLY0-NEXT:    [[TMP87:%.*]] = load i8, ptr [[CD]], align 1
55062 // SIMD-ONLY0-NEXT:    [[CONV187:%.*]] = sext i8 [[TMP87]] to i32
55063 // SIMD-ONLY0-NEXT:    br label [[COND_END190:%.*]]
55064 // SIMD-ONLY0:       cond.false188:
55065 // SIMD-ONLY0-NEXT:    [[TMP88:%.*]] = load i8, ptr [[CX]], align 1
55066 // SIMD-ONLY0-NEXT:    [[CONV189:%.*]] = sext i8 [[TMP88]] to i32
55067 // SIMD-ONLY0-NEXT:    br label [[COND_END190]]
55068 // SIMD-ONLY0:       cond.end190:
55069 // SIMD-ONLY0-NEXT:    [[COND191:%.*]] = phi i32 [ [[CONV187]], [[COND_TRUE186]] ], [ [[CONV189]], [[COND_FALSE188]] ]
55070 // SIMD-ONLY0-NEXT:    [[CONV192:%.*]] = trunc i32 [[COND191]] to i8
55071 // SIMD-ONLY0-NEXT:    store i8 [[CONV192]], ptr [[CX]], align 1
55072 // SIMD-ONLY0-NEXT:    [[TMP89:%.*]] = load i8, ptr [[CX]], align 1
55073 // SIMD-ONLY0-NEXT:    store i8 [[TMP89]], ptr [[CV]], align 1
55074 // SIMD-ONLY0-NEXT:    [[TMP90:%.*]] = load i8, ptr [[CX]], align 1
55075 // SIMD-ONLY0-NEXT:    store i8 [[TMP90]], ptr [[CV]], align 1
55076 // SIMD-ONLY0-NEXT:    [[TMP91:%.*]] = load i8, ptr [[CX]], align 1
55077 // SIMD-ONLY0-NEXT:    [[CONV193:%.*]] = sext i8 [[TMP91]] to i32
55078 // SIMD-ONLY0-NEXT:    [[TMP92:%.*]] = load i8, ptr [[CE]], align 1
55079 // SIMD-ONLY0-NEXT:    [[CONV194:%.*]] = sext i8 [[TMP92]] to i32
55080 // SIMD-ONLY0-NEXT:    [[CMP195:%.*]] = icmp sgt i32 [[CONV193]], [[CONV194]]
55081 // SIMD-ONLY0-NEXT:    br i1 [[CMP195]], label [[COND_TRUE197:%.*]], label [[COND_FALSE199:%.*]]
55082 // SIMD-ONLY0:       cond.true197:
55083 // SIMD-ONLY0-NEXT:    [[TMP93:%.*]] = load i8, ptr [[CE]], align 1
55084 // SIMD-ONLY0-NEXT:    [[CONV198:%.*]] = sext i8 [[TMP93]] to i32
55085 // SIMD-ONLY0-NEXT:    br label [[COND_END201:%.*]]
55086 // SIMD-ONLY0:       cond.false199:
55087 // SIMD-ONLY0-NEXT:    [[TMP94:%.*]] = load i8, ptr [[CX]], align 1
55088 // SIMD-ONLY0-NEXT:    [[CONV200:%.*]] = sext i8 [[TMP94]] to i32
55089 // SIMD-ONLY0-NEXT:    br label [[COND_END201]]
55090 // SIMD-ONLY0:       cond.end201:
55091 // SIMD-ONLY0-NEXT:    [[COND202:%.*]] = phi i32 [ [[CONV198]], [[COND_TRUE197]] ], [ [[CONV200]], [[COND_FALSE199]] ]
55092 // SIMD-ONLY0-NEXT:    [[CONV203:%.*]] = trunc i32 [[COND202]] to i8
55093 // SIMD-ONLY0-NEXT:    store i8 [[CONV203]], ptr [[CX]], align 1
55094 // SIMD-ONLY0-NEXT:    [[TMP95:%.*]] = load i8, ptr [[CX]], align 1
55095 // SIMD-ONLY0-NEXT:    store i8 [[TMP95]], ptr [[CV]], align 1
55096 // SIMD-ONLY0-NEXT:    [[TMP96:%.*]] = load i8, ptr [[CX]], align 1
55097 // SIMD-ONLY0-NEXT:    [[CONV204:%.*]] = sext i8 [[TMP96]] to i32
55098 // SIMD-ONLY0-NEXT:    [[TMP97:%.*]] = load i8, ptr [[CE]], align 1
55099 // SIMD-ONLY0-NEXT:    [[CONV205:%.*]] = sext i8 [[TMP97]] to i32
55100 // SIMD-ONLY0-NEXT:    [[CMP206:%.*]] = icmp slt i32 [[CONV204]], [[CONV205]]
55101 // SIMD-ONLY0-NEXT:    br i1 [[CMP206]], label [[COND_TRUE208:%.*]], label [[COND_FALSE210:%.*]]
55102 // SIMD-ONLY0:       cond.true208:
55103 // SIMD-ONLY0-NEXT:    [[TMP98:%.*]] = load i8, ptr [[CE]], align 1
55104 // SIMD-ONLY0-NEXT:    [[CONV209:%.*]] = sext i8 [[TMP98]] to i32
55105 // SIMD-ONLY0-NEXT:    br label [[COND_END212:%.*]]
55106 // SIMD-ONLY0:       cond.false210:
55107 // SIMD-ONLY0-NEXT:    [[TMP99:%.*]] = load i8, ptr [[CX]], align 1
55108 // SIMD-ONLY0-NEXT:    [[CONV211:%.*]] = sext i8 [[TMP99]] to i32
55109 // SIMD-ONLY0-NEXT:    br label [[COND_END212]]
55110 // SIMD-ONLY0:       cond.end212:
55111 // SIMD-ONLY0-NEXT:    [[COND213:%.*]] = phi i32 [ [[CONV209]], [[COND_TRUE208]] ], [ [[CONV211]], [[COND_FALSE210]] ]
55112 // SIMD-ONLY0-NEXT:    [[CONV214:%.*]] = trunc i32 [[COND213]] to i8
55113 // SIMD-ONLY0-NEXT:    store i8 [[CONV214]], ptr [[CX]], align 1
55114 // SIMD-ONLY0-NEXT:    [[TMP100:%.*]] = load i8, ptr [[CX]], align 1
55115 // SIMD-ONLY0-NEXT:    store i8 [[TMP100]], ptr [[CV]], align 1
55116 // SIMD-ONLY0-NEXT:    [[TMP101:%.*]] = load i8, ptr [[CX]], align 1
55117 // SIMD-ONLY0-NEXT:    [[CONV215:%.*]] = sext i8 [[TMP101]] to i32
55118 // SIMD-ONLY0-NEXT:    [[TMP102:%.*]] = load i8, ptr [[CE]], align 1
55119 // SIMD-ONLY0-NEXT:    [[CONV216:%.*]] = sext i8 [[TMP102]] to i32
55120 // SIMD-ONLY0-NEXT:    [[CMP217:%.*]] = icmp eq i32 [[CONV215]], [[CONV216]]
55121 // SIMD-ONLY0-NEXT:    br i1 [[CMP217]], label [[COND_TRUE219:%.*]], label [[COND_FALSE221:%.*]]
55122 // SIMD-ONLY0:       cond.true219:
55123 // SIMD-ONLY0-NEXT:    [[TMP103:%.*]] = load i8, ptr [[CD]], align 1
55124 // SIMD-ONLY0-NEXT:    [[CONV220:%.*]] = sext i8 [[TMP103]] to i32
55125 // SIMD-ONLY0-NEXT:    br label [[COND_END223:%.*]]
55126 // SIMD-ONLY0:       cond.false221:
55127 // SIMD-ONLY0-NEXT:    [[TMP104:%.*]] = load i8, ptr [[CX]], align 1
55128 // SIMD-ONLY0-NEXT:    [[CONV222:%.*]] = sext i8 [[TMP104]] to i32
55129 // SIMD-ONLY0-NEXT:    br label [[COND_END223]]
55130 // SIMD-ONLY0:       cond.end223:
55131 // SIMD-ONLY0-NEXT:    [[COND224:%.*]] = phi i32 [ [[CONV220]], [[COND_TRUE219]] ], [ [[CONV222]], [[COND_FALSE221]] ]
55132 // SIMD-ONLY0-NEXT:    [[CONV225:%.*]] = trunc i32 [[COND224]] to i8
55133 // SIMD-ONLY0-NEXT:    store i8 [[CONV225]], ptr [[CX]], align 1
55134 // SIMD-ONLY0-NEXT:    [[TMP105:%.*]] = load i8, ptr [[CX]], align 1
55135 // SIMD-ONLY0-NEXT:    [[CONV226:%.*]] = sext i8 [[TMP105]] to i32
55136 // SIMD-ONLY0-NEXT:    [[TMP106:%.*]] = load i8, ptr [[CE]], align 1
55137 // SIMD-ONLY0-NEXT:    [[CONV227:%.*]] = sext i8 [[TMP106]] to i32
55138 // SIMD-ONLY0-NEXT:    [[CMP228:%.*]] = icmp sgt i32 [[CONV226]], [[CONV227]]
55139 // SIMD-ONLY0-NEXT:    br i1 [[CMP228]], label [[COND_TRUE230:%.*]], label [[COND_FALSE232:%.*]]
55140 // SIMD-ONLY0:       cond.true230:
55141 // SIMD-ONLY0-NEXT:    [[TMP107:%.*]] = load i8, ptr [[CE]], align 1
55142 // SIMD-ONLY0-NEXT:    [[CONV231:%.*]] = sext i8 [[TMP107]] to i32
55143 // SIMD-ONLY0-NEXT:    br label [[COND_END234:%.*]]
55144 // SIMD-ONLY0:       cond.false232:
55145 // SIMD-ONLY0-NEXT:    [[TMP108:%.*]] = load i8, ptr [[CX]], align 1
55146 // SIMD-ONLY0-NEXT:    [[CONV233:%.*]] = sext i8 [[TMP108]] to i32
55147 // SIMD-ONLY0-NEXT:    br label [[COND_END234]]
55148 // SIMD-ONLY0:       cond.end234:
55149 // SIMD-ONLY0-NEXT:    [[COND235:%.*]] = phi i32 [ [[CONV231]], [[COND_TRUE230]] ], [ [[CONV233]], [[COND_FALSE232]] ]
55150 // SIMD-ONLY0-NEXT:    [[CONV236:%.*]] = trunc i32 [[COND235]] to i8
55151 // SIMD-ONLY0-NEXT:    store i8 [[CONV236]], ptr [[CX]], align 1
55152 // SIMD-ONLY0-NEXT:    [[TMP109:%.*]] = load i8, ptr [[CX]], align 1
55153 // SIMD-ONLY0-NEXT:    store i8 [[TMP109]], ptr [[CV]], align 1
55154 // SIMD-ONLY0-NEXT:    [[TMP110:%.*]] = load i8, ptr [[CX]], align 1
55155 // SIMD-ONLY0-NEXT:    [[CONV237:%.*]] = sext i8 [[TMP110]] to i32
55156 // SIMD-ONLY0-NEXT:    [[TMP111:%.*]] = load i8, ptr [[CE]], align 1
55157 // SIMD-ONLY0-NEXT:    [[CONV238:%.*]] = sext i8 [[TMP111]] to i32
55158 // SIMD-ONLY0-NEXT:    [[CMP239:%.*]] = icmp slt i32 [[CONV237]], [[CONV238]]
55159 // SIMD-ONLY0-NEXT:    br i1 [[CMP239]], label [[COND_TRUE241:%.*]], label [[COND_FALSE243:%.*]]
55160 // SIMD-ONLY0:       cond.true241:
55161 // SIMD-ONLY0-NEXT:    [[TMP112:%.*]] = load i8, ptr [[CE]], align 1
55162 // SIMD-ONLY0-NEXT:    [[CONV242:%.*]] = sext i8 [[TMP112]] to i32
55163 // SIMD-ONLY0-NEXT:    br label [[COND_END245:%.*]]
55164 // SIMD-ONLY0:       cond.false243:
55165 // SIMD-ONLY0-NEXT:    [[TMP113:%.*]] = load i8, ptr [[CX]], align 1
55166 // SIMD-ONLY0-NEXT:    [[CONV244:%.*]] = sext i8 [[TMP113]] to i32
55167 // SIMD-ONLY0-NEXT:    br label [[COND_END245]]
55168 // SIMD-ONLY0:       cond.end245:
55169 // SIMD-ONLY0-NEXT:    [[COND246:%.*]] = phi i32 [ [[CONV242]], [[COND_TRUE241]] ], [ [[CONV244]], [[COND_FALSE243]] ]
55170 // SIMD-ONLY0-NEXT:    [[CONV247:%.*]] = trunc i32 [[COND246]] to i8
55171 // SIMD-ONLY0-NEXT:    store i8 [[CONV247]], ptr [[CX]], align 1
55172 // SIMD-ONLY0-NEXT:    [[TMP114:%.*]] = load i8, ptr [[CX]], align 1
55173 // SIMD-ONLY0-NEXT:    store i8 [[TMP114]], ptr [[CV]], align 1
55174 // SIMD-ONLY0-NEXT:    [[TMP115:%.*]] = load i8, ptr [[CX]], align 1
55175 // SIMD-ONLY0-NEXT:    [[CONV248:%.*]] = sext i8 [[TMP115]] to i32
55176 // SIMD-ONLY0-NEXT:    [[TMP116:%.*]] = load i8, ptr [[CE]], align 1
55177 // SIMD-ONLY0-NEXT:    [[CONV249:%.*]] = sext i8 [[TMP116]] to i32
55178 // SIMD-ONLY0-NEXT:    [[CMP250:%.*]] = icmp eq i32 [[CONV248]], [[CONV249]]
55179 // SIMD-ONLY0-NEXT:    br i1 [[CMP250]], label [[COND_TRUE252:%.*]], label [[COND_FALSE254:%.*]]
55180 // SIMD-ONLY0:       cond.true252:
55181 // SIMD-ONLY0-NEXT:    [[TMP117:%.*]] = load i8, ptr [[CD]], align 1
55182 // SIMD-ONLY0-NEXT:    [[CONV253:%.*]] = sext i8 [[TMP117]] to i32
55183 // SIMD-ONLY0-NEXT:    br label [[COND_END256:%.*]]
55184 // SIMD-ONLY0:       cond.false254:
55185 // SIMD-ONLY0-NEXT:    [[TMP118:%.*]] = load i8, ptr [[CX]], align 1
55186 // SIMD-ONLY0-NEXT:    [[CONV255:%.*]] = sext i8 [[TMP118]] to i32
55187 // SIMD-ONLY0-NEXT:    br label [[COND_END256]]
55188 // SIMD-ONLY0:       cond.end256:
55189 // SIMD-ONLY0-NEXT:    [[COND257:%.*]] = phi i32 [ [[CONV253]], [[COND_TRUE252]] ], [ [[CONV255]], [[COND_FALSE254]] ]
55190 // SIMD-ONLY0-NEXT:    [[CONV258:%.*]] = trunc i32 [[COND257]] to i8
55191 // SIMD-ONLY0-NEXT:    store i8 [[CONV258]], ptr [[CX]], align 1
55192 // SIMD-ONLY0-NEXT:    [[TMP119:%.*]] = load i8, ptr [[CX]], align 1
55193 // SIMD-ONLY0-NEXT:    store i8 [[TMP119]], ptr [[CV]], align 1
55194 // SIMD-ONLY0-NEXT:    [[TMP120:%.*]] = load i8, ptr [[CX]], align 1
55195 // SIMD-ONLY0-NEXT:    store i8 [[TMP120]], ptr [[CV]], align 1
55196 // SIMD-ONLY0-NEXT:    [[TMP121:%.*]] = load i8, ptr [[CX]], align 1
55197 // SIMD-ONLY0-NEXT:    [[CONV259:%.*]] = sext i8 [[TMP121]] to i32
55198 // SIMD-ONLY0-NEXT:    [[TMP122:%.*]] = load i8, ptr [[CE]], align 1
55199 // SIMD-ONLY0-NEXT:    [[CONV260:%.*]] = sext i8 [[TMP122]] to i32
55200 // SIMD-ONLY0-NEXT:    [[CMP261:%.*]] = icmp sgt i32 [[CONV259]], [[CONV260]]
55201 // SIMD-ONLY0-NEXT:    br i1 [[CMP261]], label [[COND_TRUE263:%.*]], label [[COND_FALSE265:%.*]]
55202 // SIMD-ONLY0:       cond.true263:
55203 // SIMD-ONLY0-NEXT:    [[TMP123:%.*]] = load i8, ptr [[CE]], align 1
55204 // SIMD-ONLY0-NEXT:    [[CONV264:%.*]] = sext i8 [[TMP123]] to i32
55205 // SIMD-ONLY0-NEXT:    br label [[COND_END267:%.*]]
55206 // SIMD-ONLY0:       cond.false265:
55207 // SIMD-ONLY0-NEXT:    [[TMP124:%.*]] = load i8, ptr [[CX]], align 1
55208 // SIMD-ONLY0-NEXT:    [[CONV266:%.*]] = sext i8 [[TMP124]] to i32
55209 // SIMD-ONLY0-NEXT:    br label [[COND_END267]]
55210 // SIMD-ONLY0:       cond.end267:
55211 // SIMD-ONLY0-NEXT:    [[COND268:%.*]] = phi i32 [ [[CONV264]], [[COND_TRUE263]] ], [ [[CONV266]], [[COND_FALSE265]] ]
55212 // SIMD-ONLY0-NEXT:    [[CONV269:%.*]] = trunc i32 [[COND268]] to i8
55213 // SIMD-ONLY0-NEXT:    store i8 [[CONV269]], ptr [[CX]], align 1
55214 // SIMD-ONLY0-NEXT:    [[TMP125:%.*]] = load i8, ptr [[CX]], align 1
55215 // SIMD-ONLY0-NEXT:    store i8 [[TMP125]], ptr [[CV]], align 1
55216 // SIMD-ONLY0-NEXT:    [[TMP126:%.*]] = load i8, ptr [[CX]], align 1
55217 // SIMD-ONLY0-NEXT:    [[CONV270:%.*]] = sext i8 [[TMP126]] to i32
55218 // SIMD-ONLY0-NEXT:    [[TMP127:%.*]] = load i8, ptr [[CE]], align 1
55219 // SIMD-ONLY0-NEXT:    [[CONV271:%.*]] = sext i8 [[TMP127]] to i32
55220 // SIMD-ONLY0-NEXT:    [[CMP272:%.*]] = icmp slt i32 [[CONV270]], [[CONV271]]
55221 // SIMD-ONLY0-NEXT:    br i1 [[CMP272]], label [[COND_TRUE274:%.*]], label [[COND_FALSE276:%.*]]
55222 // SIMD-ONLY0:       cond.true274:
55223 // SIMD-ONLY0-NEXT:    [[TMP128:%.*]] = load i8, ptr [[CE]], align 1
55224 // SIMD-ONLY0-NEXT:    [[CONV275:%.*]] = sext i8 [[TMP128]] to i32
55225 // SIMD-ONLY0-NEXT:    br label [[COND_END278:%.*]]
55226 // SIMD-ONLY0:       cond.false276:
55227 // SIMD-ONLY0-NEXT:    [[TMP129:%.*]] = load i8, ptr [[CX]], align 1
55228 // SIMD-ONLY0-NEXT:    [[CONV277:%.*]] = sext i8 [[TMP129]] to i32
55229 // SIMD-ONLY0-NEXT:    br label [[COND_END278]]
55230 // SIMD-ONLY0:       cond.end278:
55231 // SIMD-ONLY0-NEXT:    [[COND279:%.*]] = phi i32 [ [[CONV275]], [[COND_TRUE274]] ], [ [[CONV277]], [[COND_FALSE276]] ]
55232 // SIMD-ONLY0-NEXT:    [[CONV280:%.*]] = trunc i32 [[COND279]] to i8
55233 // SIMD-ONLY0-NEXT:    store i8 [[CONV280]], ptr [[CX]], align 1
55234 // SIMD-ONLY0-NEXT:    [[TMP130:%.*]] = load i8, ptr [[CX]], align 1
55235 // SIMD-ONLY0-NEXT:    store i8 [[TMP130]], ptr [[CV]], align 1
55236 // SIMD-ONLY0-NEXT:    [[TMP131:%.*]] = load i8, ptr [[CX]], align 1
55237 // SIMD-ONLY0-NEXT:    [[CONV281:%.*]] = sext i8 [[TMP131]] to i32
55238 // SIMD-ONLY0-NEXT:    [[TMP132:%.*]] = load i8, ptr [[CE]], align 1
55239 // SIMD-ONLY0-NEXT:    [[CONV282:%.*]] = sext i8 [[TMP132]] to i32
55240 // SIMD-ONLY0-NEXT:    [[CMP283:%.*]] = icmp eq i32 [[CONV281]], [[CONV282]]
55241 // SIMD-ONLY0-NEXT:    br i1 [[CMP283]], label [[COND_TRUE285:%.*]], label [[COND_FALSE287:%.*]]
55242 // SIMD-ONLY0:       cond.true285:
55243 // SIMD-ONLY0-NEXT:    [[TMP133:%.*]] = load i8, ptr [[CD]], align 1
55244 // SIMD-ONLY0-NEXT:    [[CONV286:%.*]] = sext i8 [[TMP133]] to i32
55245 // SIMD-ONLY0-NEXT:    br label [[COND_END289:%.*]]
55246 // SIMD-ONLY0:       cond.false287:
55247 // SIMD-ONLY0-NEXT:    [[TMP134:%.*]] = load i8, ptr [[CX]], align 1
55248 // SIMD-ONLY0-NEXT:    [[CONV288:%.*]] = sext i8 [[TMP134]] to i32
55249 // SIMD-ONLY0-NEXT:    br label [[COND_END289]]
55250 // SIMD-ONLY0:       cond.end289:
55251 // SIMD-ONLY0-NEXT:    [[COND290:%.*]] = phi i32 [ [[CONV286]], [[COND_TRUE285]] ], [ [[CONV288]], [[COND_FALSE287]] ]
55252 // SIMD-ONLY0-NEXT:    [[CONV291:%.*]] = trunc i32 [[COND290]] to i8
55253 // SIMD-ONLY0-NEXT:    store i8 [[CONV291]], ptr [[CX]], align 1
55254 // SIMD-ONLY0-NEXT:    [[TMP135:%.*]] = load i8, ptr [[CX]], align 1
55255 // SIMD-ONLY0-NEXT:    [[CONV292:%.*]] = sext i8 [[TMP135]] to i32
55256 // SIMD-ONLY0-NEXT:    [[TMP136:%.*]] = load i8, ptr [[CE]], align 1
55257 // SIMD-ONLY0-NEXT:    [[CONV293:%.*]] = sext i8 [[TMP136]] to i32
55258 // SIMD-ONLY0-NEXT:    [[CMP294:%.*]] = icmp sgt i32 [[CONV292]], [[CONV293]]
55259 // SIMD-ONLY0-NEXT:    br i1 [[CMP294]], label [[COND_TRUE296:%.*]], label [[COND_FALSE298:%.*]]
55260 // SIMD-ONLY0:       cond.true296:
55261 // SIMD-ONLY0-NEXT:    [[TMP137:%.*]] = load i8, ptr [[CE]], align 1
55262 // SIMD-ONLY0-NEXT:    [[CONV297:%.*]] = sext i8 [[TMP137]] to i32
55263 // SIMD-ONLY0-NEXT:    br label [[COND_END300:%.*]]
55264 // SIMD-ONLY0:       cond.false298:
55265 // SIMD-ONLY0-NEXT:    [[TMP138:%.*]] = load i8, ptr [[CX]], align 1
55266 // SIMD-ONLY0-NEXT:    [[CONV299:%.*]] = sext i8 [[TMP138]] to i32
55267 // SIMD-ONLY0-NEXT:    br label [[COND_END300]]
55268 // SIMD-ONLY0:       cond.end300:
55269 // SIMD-ONLY0-NEXT:    [[COND301:%.*]] = phi i32 [ [[CONV297]], [[COND_TRUE296]] ], [ [[CONV299]], [[COND_FALSE298]] ]
55270 // SIMD-ONLY0-NEXT:    [[CONV302:%.*]] = trunc i32 [[COND301]] to i8
55271 // SIMD-ONLY0-NEXT:    store i8 [[CONV302]], ptr [[CX]], align 1
55272 // SIMD-ONLY0-NEXT:    [[TMP139:%.*]] = load i8, ptr [[CX]], align 1
55273 // SIMD-ONLY0-NEXT:    store i8 [[TMP139]], ptr [[CV]], align 1
55274 // SIMD-ONLY0-NEXT:    [[TMP140:%.*]] = load i8, ptr [[CX]], align 1
55275 // SIMD-ONLY0-NEXT:    [[CONV303:%.*]] = sext i8 [[TMP140]] to i32
55276 // SIMD-ONLY0-NEXT:    [[TMP141:%.*]] = load i8, ptr [[CE]], align 1
55277 // SIMD-ONLY0-NEXT:    [[CONV304:%.*]] = sext i8 [[TMP141]] to i32
55278 // SIMD-ONLY0-NEXT:    [[CMP305:%.*]] = icmp slt i32 [[CONV303]], [[CONV304]]
55279 // SIMD-ONLY0-NEXT:    br i1 [[CMP305]], label [[COND_TRUE307:%.*]], label [[COND_FALSE309:%.*]]
55280 // SIMD-ONLY0:       cond.true307:
55281 // SIMD-ONLY0-NEXT:    [[TMP142:%.*]] = load i8, ptr [[CE]], align 1
55282 // SIMD-ONLY0-NEXT:    [[CONV308:%.*]] = sext i8 [[TMP142]] to i32
55283 // SIMD-ONLY0-NEXT:    br label [[COND_END311:%.*]]
55284 // SIMD-ONLY0:       cond.false309:
55285 // SIMD-ONLY0-NEXT:    [[TMP143:%.*]] = load i8, ptr [[CX]], align 1
55286 // SIMD-ONLY0-NEXT:    [[CONV310:%.*]] = sext i8 [[TMP143]] to i32
55287 // SIMD-ONLY0-NEXT:    br label [[COND_END311]]
55288 // SIMD-ONLY0:       cond.end311:
55289 // SIMD-ONLY0-NEXT:    [[COND312:%.*]] = phi i32 [ [[CONV308]], [[COND_TRUE307]] ], [ [[CONV310]], [[COND_FALSE309]] ]
55290 // SIMD-ONLY0-NEXT:    [[CONV313:%.*]] = trunc i32 [[COND312]] to i8
55291 // SIMD-ONLY0-NEXT:    store i8 [[CONV313]], ptr [[CX]], align 1
55292 // SIMD-ONLY0-NEXT:    [[TMP144:%.*]] = load i8, ptr [[CX]], align 1
55293 // SIMD-ONLY0-NEXT:    store i8 [[TMP144]], ptr [[CV]], align 1
55294 // SIMD-ONLY0-NEXT:    [[TMP145:%.*]] = load i8, ptr [[CX]], align 1
55295 // SIMD-ONLY0-NEXT:    [[CONV314:%.*]] = sext i8 [[TMP145]] to i32
55296 // SIMD-ONLY0-NEXT:    [[TMP146:%.*]] = load i8, ptr [[CE]], align 1
55297 // SIMD-ONLY0-NEXT:    [[CONV315:%.*]] = sext i8 [[TMP146]] to i32
55298 // SIMD-ONLY0-NEXT:    [[CMP316:%.*]] = icmp eq i32 [[CONV314]], [[CONV315]]
55299 // SIMD-ONLY0-NEXT:    br i1 [[CMP316]], label [[COND_TRUE318:%.*]], label [[COND_FALSE320:%.*]]
55300 // SIMD-ONLY0:       cond.true318:
55301 // SIMD-ONLY0-NEXT:    [[TMP147:%.*]] = load i8, ptr [[CD]], align 1
55302 // SIMD-ONLY0-NEXT:    [[CONV319:%.*]] = sext i8 [[TMP147]] to i32
55303 // SIMD-ONLY0-NEXT:    br label [[COND_END322:%.*]]
55304 // SIMD-ONLY0:       cond.false320:
55305 // SIMD-ONLY0-NEXT:    [[TMP148:%.*]] = load i8, ptr [[CX]], align 1
55306 // SIMD-ONLY0-NEXT:    [[CONV321:%.*]] = sext i8 [[TMP148]] to i32
55307 // SIMD-ONLY0-NEXT:    br label [[COND_END322]]
55308 // SIMD-ONLY0:       cond.end322:
55309 // SIMD-ONLY0-NEXT:    [[COND323:%.*]] = phi i32 [ [[CONV319]], [[COND_TRUE318]] ], [ [[CONV321]], [[COND_FALSE320]] ]
55310 // SIMD-ONLY0-NEXT:    [[CONV324:%.*]] = trunc i32 [[COND323]] to i8
55311 // SIMD-ONLY0-NEXT:    store i8 [[CONV324]], ptr [[CX]], align 1
55312 // SIMD-ONLY0-NEXT:    [[TMP149:%.*]] = load i8, ptr [[CX]], align 1
55313 // SIMD-ONLY0-NEXT:    store i8 [[TMP149]], ptr [[CV]], align 1
55314 // SIMD-ONLY0-NEXT:    [[TMP150:%.*]] = load i8, ptr [[CX]], align 1
55315 // SIMD-ONLY0-NEXT:    store i8 [[TMP150]], ptr [[CV]], align 1
55316 // SIMD-ONLY0-NEXT:    [[TMP151:%.*]] = load i8, ptr [[CX]], align 1
55317 // SIMD-ONLY0-NEXT:    [[CONV325:%.*]] = sext i8 [[TMP151]] to i32
55318 // SIMD-ONLY0-NEXT:    [[TMP152:%.*]] = load i8, ptr [[CE]], align 1
55319 // SIMD-ONLY0-NEXT:    [[CONV326:%.*]] = sext i8 [[TMP152]] to i32
55320 // SIMD-ONLY0-NEXT:    [[CMP327:%.*]] = icmp sgt i32 [[CONV325]], [[CONV326]]
55321 // SIMD-ONLY0-NEXT:    br i1 [[CMP327]], label [[COND_TRUE329:%.*]], label [[COND_FALSE331:%.*]]
55322 // SIMD-ONLY0:       cond.true329:
55323 // SIMD-ONLY0-NEXT:    [[TMP153:%.*]] = load i8, ptr [[CE]], align 1
55324 // SIMD-ONLY0-NEXT:    [[CONV330:%.*]] = sext i8 [[TMP153]] to i32
55325 // SIMD-ONLY0-NEXT:    br label [[COND_END333:%.*]]
55326 // SIMD-ONLY0:       cond.false331:
55327 // SIMD-ONLY0-NEXT:    [[TMP154:%.*]] = load i8, ptr [[CX]], align 1
55328 // SIMD-ONLY0-NEXT:    [[CONV332:%.*]] = sext i8 [[TMP154]] to i32
55329 // SIMD-ONLY0-NEXT:    br label [[COND_END333]]
55330 // SIMD-ONLY0:       cond.end333:
55331 // SIMD-ONLY0-NEXT:    [[COND334:%.*]] = phi i32 [ [[CONV330]], [[COND_TRUE329]] ], [ [[CONV332]], [[COND_FALSE331]] ]
55332 // SIMD-ONLY0-NEXT:    [[CONV335:%.*]] = trunc i32 [[COND334]] to i8
55333 // SIMD-ONLY0-NEXT:    store i8 [[CONV335]], ptr [[CX]], align 1
55334 // SIMD-ONLY0-NEXT:    [[TMP155:%.*]] = load i8, ptr [[CX]], align 1
55335 // SIMD-ONLY0-NEXT:    store i8 [[TMP155]], ptr [[CV]], align 1
55336 // SIMD-ONLY0-NEXT:    [[TMP156:%.*]] = load i8, ptr [[CX]], align 1
55337 // SIMD-ONLY0-NEXT:    [[CONV336:%.*]] = sext i8 [[TMP156]] to i32
55338 // SIMD-ONLY0-NEXT:    [[TMP157:%.*]] = load i8, ptr [[CE]], align 1
55339 // SIMD-ONLY0-NEXT:    [[CONV337:%.*]] = sext i8 [[TMP157]] to i32
55340 // SIMD-ONLY0-NEXT:    [[CMP338:%.*]] = icmp slt i32 [[CONV336]], [[CONV337]]
55341 // SIMD-ONLY0-NEXT:    br i1 [[CMP338]], label [[COND_TRUE340:%.*]], label [[COND_FALSE342:%.*]]
55342 // SIMD-ONLY0:       cond.true340:
55343 // SIMD-ONLY0-NEXT:    [[TMP158:%.*]] = load i8, ptr [[CE]], align 1
55344 // SIMD-ONLY0-NEXT:    [[CONV341:%.*]] = sext i8 [[TMP158]] to i32
55345 // SIMD-ONLY0-NEXT:    br label [[COND_END344:%.*]]
55346 // SIMD-ONLY0:       cond.false342:
55347 // SIMD-ONLY0-NEXT:    [[TMP159:%.*]] = load i8, ptr [[CX]], align 1
55348 // SIMD-ONLY0-NEXT:    [[CONV343:%.*]] = sext i8 [[TMP159]] to i32
55349 // SIMD-ONLY0-NEXT:    br label [[COND_END344]]
55350 // SIMD-ONLY0:       cond.end344:
55351 // SIMD-ONLY0-NEXT:    [[COND345:%.*]] = phi i32 [ [[CONV341]], [[COND_TRUE340]] ], [ [[CONV343]], [[COND_FALSE342]] ]
55352 // SIMD-ONLY0-NEXT:    [[CONV346:%.*]] = trunc i32 [[COND345]] to i8
55353 // SIMD-ONLY0-NEXT:    store i8 [[CONV346]], ptr [[CX]], align 1
55354 // SIMD-ONLY0-NEXT:    [[TMP160:%.*]] = load i8, ptr [[CX]], align 1
55355 // SIMD-ONLY0-NEXT:    store i8 [[TMP160]], ptr [[CV]], align 1
55356 // SIMD-ONLY0-NEXT:    [[TMP161:%.*]] = load i8, ptr [[CX]], align 1
55357 // SIMD-ONLY0-NEXT:    [[CONV347:%.*]] = sext i8 [[TMP161]] to i32
55358 // SIMD-ONLY0-NEXT:    [[TMP162:%.*]] = load i8, ptr [[CE]], align 1
55359 // SIMD-ONLY0-NEXT:    [[CONV348:%.*]] = sext i8 [[TMP162]] to i32
55360 // SIMD-ONLY0-NEXT:    [[CMP349:%.*]] = icmp eq i32 [[CONV347]], [[CONV348]]
55361 // SIMD-ONLY0-NEXT:    br i1 [[CMP349]], label [[COND_TRUE351:%.*]], label [[COND_FALSE353:%.*]]
55362 // SIMD-ONLY0:       cond.true351:
55363 // SIMD-ONLY0-NEXT:    [[TMP163:%.*]] = load i8, ptr [[CD]], align 1
55364 // SIMD-ONLY0-NEXT:    [[CONV352:%.*]] = sext i8 [[TMP163]] to i32
55365 // SIMD-ONLY0-NEXT:    br label [[COND_END355:%.*]]
55366 // SIMD-ONLY0:       cond.false353:
55367 // SIMD-ONLY0-NEXT:    [[TMP164:%.*]] = load i8, ptr [[CX]], align 1
55368 // SIMD-ONLY0-NEXT:    [[CONV354:%.*]] = sext i8 [[TMP164]] to i32
55369 // SIMD-ONLY0-NEXT:    br label [[COND_END355]]
55370 // SIMD-ONLY0:       cond.end355:
55371 // SIMD-ONLY0-NEXT:    [[COND356:%.*]] = phi i32 [ [[CONV352]], [[COND_TRUE351]] ], [ [[CONV354]], [[COND_FALSE353]] ]
55372 // SIMD-ONLY0-NEXT:    [[CONV357:%.*]] = trunc i32 [[COND356]] to i8
55373 // SIMD-ONLY0-NEXT:    store i8 [[CONV357]], ptr [[CX]], align 1
55374 // SIMD-ONLY0-NEXT:    [[TMP165:%.*]] = load i8, ptr [[CX]], align 1
55375 // SIMD-ONLY0-NEXT:    [[CONV358:%.*]] = sext i8 [[TMP165]] to i32
55376 // SIMD-ONLY0-NEXT:    [[TMP166:%.*]] = load i8, ptr [[CE]], align 1
55377 // SIMD-ONLY0-NEXT:    [[CONV359:%.*]] = sext i8 [[TMP166]] to i32
55378 // SIMD-ONLY0-NEXT:    [[CMP360:%.*]] = icmp sgt i32 [[CONV358]], [[CONV359]]
55379 // SIMD-ONLY0-NEXT:    br i1 [[CMP360]], label [[COND_TRUE362:%.*]], label [[COND_FALSE364:%.*]]
55380 // SIMD-ONLY0:       cond.true362:
55381 // SIMD-ONLY0-NEXT:    [[TMP167:%.*]] = load i8, ptr [[CE]], align 1
55382 // SIMD-ONLY0-NEXT:    [[CONV363:%.*]] = sext i8 [[TMP167]] to i32
55383 // SIMD-ONLY0-NEXT:    br label [[COND_END366:%.*]]
55384 // SIMD-ONLY0:       cond.false364:
55385 // SIMD-ONLY0-NEXT:    [[TMP168:%.*]] = load i8, ptr [[CX]], align 1
55386 // SIMD-ONLY0-NEXT:    [[CONV365:%.*]] = sext i8 [[TMP168]] to i32
55387 // SIMD-ONLY0-NEXT:    br label [[COND_END366]]
55388 // SIMD-ONLY0:       cond.end366:
55389 // SIMD-ONLY0-NEXT:    [[COND367:%.*]] = phi i32 [ [[CONV363]], [[COND_TRUE362]] ], [ [[CONV365]], [[COND_FALSE364]] ]
55390 // SIMD-ONLY0-NEXT:    [[CONV368:%.*]] = trunc i32 [[COND367]] to i8
55391 // SIMD-ONLY0-NEXT:    store i8 [[CONV368]], ptr [[CX]], align 1
55392 // SIMD-ONLY0-NEXT:    [[TMP169:%.*]] = load i8, ptr [[CX]], align 1
55393 // SIMD-ONLY0-NEXT:    store i8 [[TMP169]], ptr [[CV]], align 1
55394 // SIMD-ONLY0-NEXT:    [[TMP170:%.*]] = load i8, ptr [[CX]], align 1
55395 // SIMD-ONLY0-NEXT:    [[CONV369:%.*]] = sext i8 [[TMP170]] to i32
55396 // SIMD-ONLY0-NEXT:    [[TMP171:%.*]] = load i8, ptr [[CE]], align 1
55397 // SIMD-ONLY0-NEXT:    [[CONV370:%.*]] = sext i8 [[TMP171]] to i32
55398 // SIMD-ONLY0-NEXT:    [[CMP371:%.*]] = icmp slt i32 [[CONV369]], [[CONV370]]
55399 // SIMD-ONLY0-NEXT:    br i1 [[CMP371]], label [[COND_TRUE373:%.*]], label [[COND_FALSE375:%.*]]
55400 // SIMD-ONLY0:       cond.true373:
55401 // SIMD-ONLY0-NEXT:    [[TMP172:%.*]] = load i8, ptr [[CE]], align 1
55402 // SIMD-ONLY0-NEXT:    [[CONV374:%.*]] = sext i8 [[TMP172]] to i32
55403 // SIMD-ONLY0-NEXT:    br label [[COND_END377:%.*]]
55404 // SIMD-ONLY0:       cond.false375:
55405 // SIMD-ONLY0-NEXT:    [[TMP173:%.*]] = load i8, ptr [[CX]], align 1
55406 // SIMD-ONLY0-NEXT:    [[CONV376:%.*]] = sext i8 [[TMP173]] to i32
55407 // SIMD-ONLY0-NEXT:    br label [[COND_END377]]
55408 // SIMD-ONLY0:       cond.end377:
55409 // SIMD-ONLY0-NEXT:    [[COND378:%.*]] = phi i32 [ [[CONV374]], [[COND_TRUE373]] ], [ [[CONV376]], [[COND_FALSE375]] ]
55410 // SIMD-ONLY0-NEXT:    [[CONV379:%.*]] = trunc i32 [[COND378]] to i8
55411 // SIMD-ONLY0-NEXT:    store i8 [[CONV379]], ptr [[CX]], align 1
55412 // SIMD-ONLY0-NEXT:    [[TMP174:%.*]] = load i8, ptr [[CX]], align 1
55413 // SIMD-ONLY0-NEXT:    store i8 [[TMP174]], ptr [[CV]], align 1
55414 // SIMD-ONLY0-NEXT:    [[TMP175:%.*]] = load i8, ptr [[CX]], align 1
55415 // SIMD-ONLY0-NEXT:    [[CONV380:%.*]] = sext i8 [[TMP175]] to i32
55416 // SIMD-ONLY0-NEXT:    [[TMP176:%.*]] = load i8, ptr [[CE]], align 1
55417 // SIMD-ONLY0-NEXT:    [[CONV381:%.*]] = sext i8 [[TMP176]] to i32
55418 // SIMD-ONLY0-NEXT:    [[CMP382:%.*]] = icmp eq i32 [[CONV380]], [[CONV381]]
55419 // SIMD-ONLY0-NEXT:    br i1 [[CMP382]], label [[COND_TRUE384:%.*]], label [[COND_FALSE386:%.*]]
55420 // SIMD-ONLY0:       cond.true384:
55421 // SIMD-ONLY0-NEXT:    [[TMP177:%.*]] = load i8, ptr [[CD]], align 1
55422 // SIMD-ONLY0-NEXT:    [[CONV385:%.*]] = sext i8 [[TMP177]] to i32
55423 // SIMD-ONLY0-NEXT:    br label [[COND_END388:%.*]]
55424 // SIMD-ONLY0:       cond.false386:
55425 // SIMD-ONLY0-NEXT:    [[TMP178:%.*]] = load i8, ptr [[CX]], align 1
55426 // SIMD-ONLY0-NEXT:    [[CONV387:%.*]] = sext i8 [[TMP178]] to i32
55427 // SIMD-ONLY0-NEXT:    br label [[COND_END388]]
55428 // SIMD-ONLY0:       cond.end388:
55429 // SIMD-ONLY0-NEXT:    [[COND389:%.*]] = phi i32 [ [[CONV385]], [[COND_TRUE384]] ], [ [[CONV387]], [[COND_FALSE386]] ]
55430 // SIMD-ONLY0-NEXT:    [[CONV390:%.*]] = trunc i32 [[COND389]] to i8
55431 // SIMD-ONLY0-NEXT:    store i8 [[CONV390]], ptr [[CX]], align 1
55432 // SIMD-ONLY0-NEXT:    [[TMP179:%.*]] = load i8, ptr [[CX]], align 1
55433 // SIMD-ONLY0-NEXT:    store i8 [[TMP179]], ptr [[CV]], align 1
55434 // SIMD-ONLY0-NEXT:    [[TMP180:%.*]] = load i8, ptr [[CV]], align 1
55435 // SIMD-ONLY0-NEXT:    ret i8 [[TMP180]]
55436 //
55437 //
55438 // SIMD-ONLY0-LABEL: @ucxevd(
55439 // SIMD-ONLY0-NEXT:  entry:
55440 // SIMD-ONLY0-NEXT:    [[UCX:%.*]] = alloca i8, align 1
55441 // SIMD-ONLY0-NEXT:    [[UCV:%.*]] = alloca i8, align 1
55442 // SIMD-ONLY0-NEXT:    [[UCE:%.*]] = alloca i8, align 1
55443 // SIMD-ONLY0-NEXT:    [[UCD:%.*]] = alloca i8, align 1
55444 // SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = load i8, ptr [[UCX]], align 1
55445 // SIMD-ONLY0-NEXT:    store i8 [[TMP0]], ptr [[UCV]], align 1
55446 // SIMD-ONLY0-NEXT:    [[TMP1:%.*]] = load i8, ptr [[UCX]], align 1
55447 // SIMD-ONLY0-NEXT:    [[CONV:%.*]] = zext i8 [[TMP1]] to i32
55448 // SIMD-ONLY0-NEXT:    [[TMP2:%.*]] = load i8, ptr [[UCE]], align 1
55449 // SIMD-ONLY0-NEXT:    [[CONV1:%.*]] = zext i8 [[TMP2]] to i32
55450 // SIMD-ONLY0-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[CONV]], [[CONV1]]
55451 // SIMD-ONLY0-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
55452 // SIMD-ONLY0:       cond.true:
55453 // SIMD-ONLY0-NEXT:    [[TMP3:%.*]] = load i8, ptr [[UCE]], align 1
55454 // SIMD-ONLY0-NEXT:    [[CONV3:%.*]] = zext i8 [[TMP3]] to i32
55455 // SIMD-ONLY0-NEXT:    br label [[COND_END:%.*]]
55456 // SIMD-ONLY0:       cond.false:
55457 // SIMD-ONLY0-NEXT:    [[TMP4:%.*]] = load i8, ptr [[UCX]], align 1
55458 // SIMD-ONLY0-NEXT:    [[CONV4:%.*]] = zext i8 [[TMP4]] to i32
55459 // SIMD-ONLY0-NEXT:    br label [[COND_END]]
55460 // SIMD-ONLY0:       cond.end:
55461 // SIMD-ONLY0-NEXT:    [[COND:%.*]] = phi i32 [ [[CONV3]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ]
55462 // SIMD-ONLY0-NEXT:    [[CONV5:%.*]] = trunc i32 [[COND]] to i8
55463 // SIMD-ONLY0-NEXT:    store i8 [[CONV5]], ptr [[UCX]], align 1
55464 // SIMD-ONLY0-NEXT:    [[TMP5:%.*]] = load i8, ptr [[UCX]], align 1
55465 // SIMD-ONLY0-NEXT:    store i8 [[TMP5]], ptr [[UCV]], align 1
55466 // SIMD-ONLY0-NEXT:    [[TMP6:%.*]] = load i8, ptr [[UCX]], align 1
55467 // SIMD-ONLY0-NEXT:    [[CONV6:%.*]] = zext i8 [[TMP6]] to i32
55468 // SIMD-ONLY0-NEXT:    [[TMP7:%.*]] = load i8, ptr [[UCE]], align 1
55469 // SIMD-ONLY0-NEXT:    [[CONV7:%.*]] = zext i8 [[TMP7]] to i32
55470 // SIMD-ONLY0-NEXT:    [[CMP8:%.*]] = icmp slt i32 [[CONV6]], [[CONV7]]
55471 // SIMD-ONLY0-NEXT:    br i1 [[CMP8]], label [[COND_TRUE10:%.*]], label [[COND_FALSE12:%.*]]
55472 // SIMD-ONLY0:       cond.true10:
55473 // SIMD-ONLY0-NEXT:    [[TMP8:%.*]] = load i8, ptr [[UCE]], align 1
55474 // SIMD-ONLY0-NEXT:    [[CONV11:%.*]] = zext i8 [[TMP8]] to i32
55475 // SIMD-ONLY0-NEXT:    br label [[COND_END14:%.*]]
55476 // SIMD-ONLY0:       cond.false12:
55477 // SIMD-ONLY0-NEXT:    [[TMP9:%.*]] = load i8, ptr [[UCX]], align 1
55478 // SIMD-ONLY0-NEXT:    [[CONV13:%.*]] = zext i8 [[TMP9]] to i32
55479 // SIMD-ONLY0-NEXT:    br label [[COND_END14]]
55480 // SIMD-ONLY0:       cond.end14:
55481 // SIMD-ONLY0-NEXT:    [[COND15:%.*]] = phi i32 [ [[CONV11]], [[COND_TRUE10]] ], [ [[CONV13]], [[COND_FALSE12]] ]
55482 // SIMD-ONLY0-NEXT:    [[CONV16:%.*]] = trunc i32 [[COND15]] to i8
55483 // SIMD-ONLY0-NEXT:    store i8 [[CONV16]], ptr [[UCX]], align 1
55484 // SIMD-ONLY0-NEXT:    [[TMP10:%.*]] = load i8, ptr [[UCX]], align 1
55485 // SIMD-ONLY0-NEXT:    store i8 [[TMP10]], ptr [[UCV]], align 1
55486 // SIMD-ONLY0-NEXT:    [[TMP11:%.*]] = load i8, ptr [[UCX]], align 1
55487 // SIMD-ONLY0-NEXT:    [[CONV17:%.*]] = zext i8 [[TMP11]] to i32
55488 // SIMD-ONLY0-NEXT:    [[TMP12:%.*]] = load i8, ptr [[UCE]], align 1
55489 // SIMD-ONLY0-NEXT:    [[CONV18:%.*]] = zext i8 [[TMP12]] to i32
55490 // SIMD-ONLY0-NEXT:    [[CMP19:%.*]] = icmp eq i32 [[CONV17]], [[CONV18]]
55491 // SIMD-ONLY0-NEXT:    br i1 [[CMP19]], label [[COND_TRUE21:%.*]], label [[COND_FALSE23:%.*]]
55492 // SIMD-ONLY0:       cond.true21:
55493 // SIMD-ONLY0-NEXT:    [[TMP13:%.*]] = load i8, ptr [[UCD]], align 1
55494 // SIMD-ONLY0-NEXT:    [[CONV22:%.*]] = zext i8 [[TMP13]] to i32
55495 // SIMD-ONLY0-NEXT:    br label [[COND_END25:%.*]]
55496 // SIMD-ONLY0:       cond.false23:
55497 // SIMD-ONLY0-NEXT:    [[TMP14:%.*]] = load i8, ptr [[UCX]], align 1
55498 // SIMD-ONLY0-NEXT:    [[CONV24:%.*]] = zext i8 [[TMP14]] to i32
55499 // SIMD-ONLY0-NEXT:    br label [[COND_END25]]
55500 // SIMD-ONLY0:       cond.end25:
55501 // SIMD-ONLY0-NEXT:    [[COND26:%.*]] = phi i32 [ [[CONV22]], [[COND_TRUE21]] ], [ [[CONV24]], [[COND_FALSE23]] ]
55502 // SIMD-ONLY0-NEXT:    [[CONV27:%.*]] = trunc i32 [[COND26]] to i8
55503 // SIMD-ONLY0-NEXT:    store i8 [[CONV27]], ptr [[UCX]], align 1
55504 // SIMD-ONLY0-NEXT:    [[TMP15:%.*]] = load i8, ptr [[UCX]], align 1
55505 // SIMD-ONLY0-NEXT:    [[CONV28:%.*]] = zext i8 [[TMP15]] to i32
55506 // SIMD-ONLY0-NEXT:    [[TMP16:%.*]] = load i8, ptr [[UCE]], align 1
55507 // SIMD-ONLY0-NEXT:    [[CONV29:%.*]] = zext i8 [[TMP16]] to i32
55508 // SIMD-ONLY0-NEXT:    [[CMP30:%.*]] = icmp sgt i32 [[CONV28]], [[CONV29]]
55509 // SIMD-ONLY0-NEXT:    br i1 [[CMP30]], label [[COND_TRUE32:%.*]], label [[COND_FALSE34:%.*]]
55510 // SIMD-ONLY0:       cond.true32:
55511 // SIMD-ONLY0-NEXT:    [[TMP17:%.*]] = load i8, ptr [[UCE]], align 1
55512 // SIMD-ONLY0-NEXT:    [[CONV33:%.*]] = zext i8 [[TMP17]] to i32
55513 // SIMD-ONLY0-NEXT:    br label [[COND_END36:%.*]]
55514 // SIMD-ONLY0:       cond.false34:
55515 // SIMD-ONLY0-NEXT:    [[TMP18:%.*]] = load i8, ptr [[UCX]], align 1
55516 // SIMD-ONLY0-NEXT:    [[CONV35:%.*]] = zext i8 [[TMP18]] to i32
55517 // SIMD-ONLY0-NEXT:    br label [[COND_END36]]
55518 // SIMD-ONLY0:       cond.end36:
55519 // SIMD-ONLY0-NEXT:    [[COND37:%.*]] = phi i32 [ [[CONV33]], [[COND_TRUE32]] ], [ [[CONV35]], [[COND_FALSE34]] ]
55520 // SIMD-ONLY0-NEXT:    [[CONV38:%.*]] = trunc i32 [[COND37]] to i8
55521 // SIMD-ONLY0-NEXT:    store i8 [[CONV38]], ptr [[UCX]], align 1
55522 // SIMD-ONLY0-NEXT:    [[TMP19:%.*]] = load i8, ptr [[UCX]], align 1
55523 // SIMD-ONLY0-NEXT:    store i8 [[TMP19]], ptr [[UCV]], align 1
55524 // SIMD-ONLY0-NEXT:    [[TMP20:%.*]] = load i8, ptr [[UCX]], align 1
55525 // SIMD-ONLY0-NEXT:    [[CONV39:%.*]] = zext i8 [[TMP20]] to i32
55526 // SIMD-ONLY0-NEXT:    [[TMP21:%.*]] = load i8, ptr [[UCE]], align 1
55527 // SIMD-ONLY0-NEXT:    [[CONV40:%.*]] = zext i8 [[TMP21]] to i32
55528 // SIMD-ONLY0-NEXT:    [[CMP41:%.*]] = icmp slt i32 [[CONV39]], [[CONV40]]
55529 // SIMD-ONLY0-NEXT:    br i1 [[CMP41]], label [[COND_TRUE43:%.*]], label [[COND_FALSE45:%.*]]
55530 // SIMD-ONLY0:       cond.true43:
55531 // SIMD-ONLY0-NEXT:    [[TMP22:%.*]] = load i8, ptr [[UCE]], align 1
55532 // SIMD-ONLY0-NEXT:    [[CONV44:%.*]] = zext i8 [[TMP22]] to i32
55533 // SIMD-ONLY0-NEXT:    br label [[COND_END47:%.*]]
55534 // SIMD-ONLY0:       cond.false45:
55535 // SIMD-ONLY0-NEXT:    [[TMP23:%.*]] = load i8, ptr [[UCX]], align 1
55536 // SIMD-ONLY0-NEXT:    [[CONV46:%.*]] = zext i8 [[TMP23]] to i32
55537 // SIMD-ONLY0-NEXT:    br label [[COND_END47]]
55538 // SIMD-ONLY0:       cond.end47:
55539 // SIMD-ONLY0-NEXT:    [[COND48:%.*]] = phi i32 [ [[CONV44]], [[COND_TRUE43]] ], [ [[CONV46]], [[COND_FALSE45]] ]
55540 // SIMD-ONLY0-NEXT:    [[CONV49:%.*]] = trunc i32 [[COND48]] to i8
55541 // SIMD-ONLY0-NEXT:    store i8 [[CONV49]], ptr [[UCX]], align 1
55542 // SIMD-ONLY0-NEXT:    [[TMP24:%.*]] = load i8, ptr [[UCX]], align 1
55543 // SIMD-ONLY0-NEXT:    store i8 [[TMP24]], ptr [[UCV]], align 1
55544 // SIMD-ONLY0-NEXT:    [[TMP25:%.*]] = load i8, ptr [[UCX]], align 1
55545 // SIMD-ONLY0-NEXT:    [[CONV50:%.*]] = zext i8 [[TMP25]] to i32
55546 // SIMD-ONLY0-NEXT:    [[TMP26:%.*]] = load i8, ptr [[UCE]], align 1
55547 // SIMD-ONLY0-NEXT:    [[CONV51:%.*]] = zext i8 [[TMP26]] to i32
55548 // SIMD-ONLY0-NEXT:    [[CMP52:%.*]] = icmp eq i32 [[CONV50]], [[CONV51]]
55549 // SIMD-ONLY0-NEXT:    br i1 [[CMP52]], label [[COND_TRUE54:%.*]], label [[COND_FALSE56:%.*]]
55550 // SIMD-ONLY0:       cond.true54:
55551 // SIMD-ONLY0-NEXT:    [[TMP27:%.*]] = load i8, ptr [[UCD]], align 1
55552 // SIMD-ONLY0-NEXT:    [[CONV55:%.*]] = zext i8 [[TMP27]] to i32
55553 // SIMD-ONLY0-NEXT:    br label [[COND_END58:%.*]]
55554 // SIMD-ONLY0:       cond.false56:
55555 // SIMD-ONLY0-NEXT:    [[TMP28:%.*]] = load i8, ptr [[UCX]], align 1
55556 // SIMD-ONLY0-NEXT:    [[CONV57:%.*]] = zext i8 [[TMP28]] to i32
55557 // SIMD-ONLY0-NEXT:    br label [[COND_END58]]
55558 // SIMD-ONLY0:       cond.end58:
55559 // SIMD-ONLY0-NEXT:    [[COND59:%.*]] = phi i32 [ [[CONV55]], [[COND_TRUE54]] ], [ [[CONV57]], [[COND_FALSE56]] ]
55560 // SIMD-ONLY0-NEXT:    [[CONV60:%.*]] = trunc i32 [[COND59]] to i8
55561 // SIMD-ONLY0-NEXT:    store i8 [[CONV60]], ptr [[UCX]], align 1
55562 // SIMD-ONLY0-NEXT:    [[TMP29:%.*]] = load i8, ptr [[UCX]], align 1
55563 // SIMD-ONLY0-NEXT:    store i8 [[TMP29]], ptr [[UCV]], align 1
55564 // SIMD-ONLY0-NEXT:    [[TMP30:%.*]] = load i8, ptr [[UCX]], align 1
55565 // SIMD-ONLY0-NEXT:    store i8 [[TMP30]], ptr [[UCV]], align 1
55566 // SIMD-ONLY0-NEXT:    [[TMP31:%.*]] = load i8, ptr [[UCX]], align 1
55567 // SIMD-ONLY0-NEXT:    [[CONV61:%.*]] = zext i8 [[TMP31]] to i32
55568 // SIMD-ONLY0-NEXT:    [[TMP32:%.*]] = load i8, ptr [[UCE]], align 1
55569 // SIMD-ONLY0-NEXT:    [[CONV62:%.*]] = zext i8 [[TMP32]] to i32
55570 // SIMD-ONLY0-NEXT:    [[CMP63:%.*]] = icmp sgt i32 [[CONV61]], [[CONV62]]
55571 // SIMD-ONLY0-NEXT:    br i1 [[CMP63]], label [[COND_TRUE65:%.*]], label [[COND_FALSE67:%.*]]
55572 // SIMD-ONLY0:       cond.true65:
55573 // SIMD-ONLY0-NEXT:    [[TMP33:%.*]] = load i8, ptr [[UCE]], align 1
55574 // SIMD-ONLY0-NEXT:    [[CONV66:%.*]] = zext i8 [[TMP33]] to i32
55575 // SIMD-ONLY0-NEXT:    br label [[COND_END69:%.*]]
55576 // SIMD-ONLY0:       cond.false67:
55577 // SIMD-ONLY0-NEXT:    [[TMP34:%.*]] = load i8, ptr [[UCX]], align 1
55578 // SIMD-ONLY0-NEXT:    [[CONV68:%.*]] = zext i8 [[TMP34]] to i32
55579 // SIMD-ONLY0-NEXT:    br label [[COND_END69]]
55580 // SIMD-ONLY0:       cond.end69:
55581 // SIMD-ONLY0-NEXT:    [[COND70:%.*]] = phi i32 [ [[CONV66]], [[COND_TRUE65]] ], [ [[CONV68]], [[COND_FALSE67]] ]
55582 // SIMD-ONLY0-NEXT:    [[CONV71:%.*]] = trunc i32 [[COND70]] to i8
55583 // SIMD-ONLY0-NEXT:    store i8 [[CONV71]], ptr [[UCX]], align 1
55584 // SIMD-ONLY0-NEXT:    [[TMP35:%.*]] = load i8, ptr [[UCX]], align 1
55585 // SIMD-ONLY0-NEXT:    store i8 [[TMP35]], ptr [[UCV]], align 1
55586 // SIMD-ONLY0-NEXT:    [[TMP36:%.*]] = load i8, ptr [[UCX]], align 1
55587 // SIMD-ONLY0-NEXT:    [[CONV72:%.*]] = zext i8 [[TMP36]] to i32
55588 // SIMD-ONLY0-NEXT:    [[TMP37:%.*]] = load i8, ptr [[UCE]], align 1
55589 // SIMD-ONLY0-NEXT:    [[CONV73:%.*]] = zext i8 [[TMP37]] to i32
55590 // SIMD-ONLY0-NEXT:    [[CMP74:%.*]] = icmp slt i32 [[CONV72]], [[CONV73]]
55591 // SIMD-ONLY0-NEXT:    br i1 [[CMP74]], label [[COND_TRUE76:%.*]], label [[COND_FALSE78:%.*]]
55592 // SIMD-ONLY0:       cond.true76:
55593 // SIMD-ONLY0-NEXT:    [[TMP38:%.*]] = load i8, ptr [[UCE]], align 1
55594 // SIMD-ONLY0-NEXT:    [[CONV77:%.*]] = zext i8 [[TMP38]] to i32
55595 // SIMD-ONLY0-NEXT:    br label [[COND_END80:%.*]]
55596 // SIMD-ONLY0:       cond.false78:
55597 // SIMD-ONLY0-NEXT:    [[TMP39:%.*]] = load i8, ptr [[UCX]], align 1
55598 // SIMD-ONLY0-NEXT:    [[CONV79:%.*]] = zext i8 [[TMP39]] to i32
55599 // SIMD-ONLY0-NEXT:    br label [[COND_END80]]
55600 // SIMD-ONLY0:       cond.end80:
55601 // SIMD-ONLY0-NEXT:    [[COND81:%.*]] = phi i32 [ [[CONV77]], [[COND_TRUE76]] ], [ [[CONV79]], [[COND_FALSE78]] ]
55602 // SIMD-ONLY0-NEXT:    [[CONV82:%.*]] = trunc i32 [[COND81]] to i8
55603 // SIMD-ONLY0-NEXT:    store i8 [[CONV82]], ptr [[UCX]], align 1
55604 // SIMD-ONLY0-NEXT:    [[TMP40:%.*]] = load i8, ptr [[UCX]], align 1
55605 // SIMD-ONLY0-NEXT:    store i8 [[TMP40]], ptr [[UCV]], align 1
55606 // SIMD-ONLY0-NEXT:    [[TMP41:%.*]] = load i8, ptr [[UCX]], align 1
55607 // SIMD-ONLY0-NEXT:    [[CONV83:%.*]] = zext i8 [[TMP41]] to i32
55608 // SIMD-ONLY0-NEXT:    [[TMP42:%.*]] = load i8, ptr [[UCE]], align 1
55609 // SIMD-ONLY0-NEXT:    [[CONV84:%.*]] = zext i8 [[TMP42]] to i32
55610 // SIMD-ONLY0-NEXT:    [[CMP85:%.*]] = icmp eq i32 [[CONV83]], [[CONV84]]
55611 // SIMD-ONLY0-NEXT:    br i1 [[CMP85]], label [[COND_TRUE87:%.*]], label [[COND_FALSE89:%.*]]
55612 // SIMD-ONLY0:       cond.true87:
55613 // SIMD-ONLY0-NEXT:    [[TMP43:%.*]] = load i8, ptr [[UCD]], align 1
55614 // SIMD-ONLY0-NEXT:    [[CONV88:%.*]] = zext i8 [[TMP43]] to i32
55615 // SIMD-ONLY0-NEXT:    br label [[COND_END91:%.*]]
55616 // SIMD-ONLY0:       cond.false89:
55617 // SIMD-ONLY0-NEXT:    [[TMP44:%.*]] = load i8, ptr [[UCX]], align 1
55618 // SIMD-ONLY0-NEXT:    [[CONV90:%.*]] = zext i8 [[TMP44]] to i32
55619 // SIMD-ONLY0-NEXT:    br label [[COND_END91]]
55620 // SIMD-ONLY0:       cond.end91:
55621 // SIMD-ONLY0-NEXT:    [[COND92:%.*]] = phi i32 [ [[CONV88]], [[COND_TRUE87]] ], [ [[CONV90]], [[COND_FALSE89]] ]
55622 // SIMD-ONLY0-NEXT:    [[CONV93:%.*]] = trunc i32 [[COND92]] to i8
55623 // SIMD-ONLY0-NEXT:    store i8 [[CONV93]], ptr [[UCX]], align 1
55624 // SIMD-ONLY0-NEXT:    [[TMP45:%.*]] = load i8, ptr [[UCX]], align 1
55625 // SIMD-ONLY0-NEXT:    [[CONV94:%.*]] = zext i8 [[TMP45]] to i32
55626 // SIMD-ONLY0-NEXT:    [[TMP46:%.*]] = load i8, ptr [[UCE]], align 1
55627 // SIMD-ONLY0-NEXT:    [[CONV95:%.*]] = zext i8 [[TMP46]] to i32
55628 // SIMD-ONLY0-NEXT:    [[CMP96:%.*]] = icmp sgt i32 [[CONV94]], [[CONV95]]
55629 // SIMD-ONLY0-NEXT:    br i1 [[CMP96]], label [[COND_TRUE98:%.*]], label [[COND_FALSE100:%.*]]
55630 // SIMD-ONLY0:       cond.true98:
55631 // SIMD-ONLY0-NEXT:    [[TMP47:%.*]] = load i8, ptr [[UCE]], align 1
55632 // SIMD-ONLY0-NEXT:    [[CONV99:%.*]] = zext i8 [[TMP47]] to i32
55633 // SIMD-ONLY0-NEXT:    br label [[COND_END102:%.*]]
55634 // SIMD-ONLY0:       cond.false100:
55635 // SIMD-ONLY0-NEXT:    [[TMP48:%.*]] = load i8, ptr [[UCX]], align 1
55636 // SIMD-ONLY0-NEXT:    [[CONV101:%.*]] = zext i8 [[TMP48]] to i32
55637 // SIMD-ONLY0-NEXT:    br label [[COND_END102]]
55638 // SIMD-ONLY0:       cond.end102:
55639 // SIMD-ONLY0-NEXT:    [[COND103:%.*]] = phi i32 [ [[CONV99]], [[COND_TRUE98]] ], [ [[CONV101]], [[COND_FALSE100]] ]
55640 // SIMD-ONLY0-NEXT:    [[CONV104:%.*]] = trunc i32 [[COND103]] to i8
55641 // SIMD-ONLY0-NEXT:    store i8 [[CONV104]], ptr [[UCX]], align 1
55642 // SIMD-ONLY0-NEXT:    [[TMP49:%.*]] = load i8, ptr [[UCX]], align 1
55643 // SIMD-ONLY0-NEXT:    store i8 [[TMP49]], ptr [[UCV]], align 1
55644 // SIMD-ONLY0-NEXT:    [[TMP50:%.*]] = load i8, ptr [[UCX]], align 1
55645 // SIMD-ONLY0-NEXT:    [[CONV105:%.*]] = zext i8 [[TMP50]] to i32
55646 // SIMD-ONLY0-NEXT:    [[TMP51:%.*]] = load i8, ptr [[UCE]], align 1
55647 // SIMD-ONLY0-NEXT:    [[CONV106:%.*]] = zext i8 [[TMP51]] to i32
55648 // SIMD-ONLY0-NEXT:    [[CMP107:%.*]] = icmp slt i32 [[CONV105]], [[CONV106]]
55649 // SIMD-ONLY0-NEXT:    br i1 [[CMP107]], label [[COND_TRUE109:%.*]], label [[COND_FALSE111:%.*]]
55650 // SIMD-ONLY0:       cond.true109:
55651 // SIMD-ONLY0-NEXT:    [[TMP52:%.*]] = load i8, ptr [[UCE]], align 1
55652 // SIMD-ONLY0-NEXT:    [[CONV110:%.*]] = zext i8 [[TMP52]] to i32
55653 // SIMD-ONLY0-NEXT:    br label [[COND_END113:%.*]]
55654 // SIMD-ONLY0:       cond.false111:
55655 // SIMD-ONLY0-NEXT:    [[TMP53:%.*]] = load i8, ptr [[UCX]], align 1
55656 // SIMD-ONLY0-NEXT:    [[CONV112:%.*]] = zext i8 [[TMP53]] to i32
55657 // SIMD-ONLY0-NEXT:    br label [[COND_END113]]
55658 // SIMD-ONLY0:       cond.end113:
55659 // SIMD-ONLY0-NEXT:    [[COND114:%.*]] = phi i32 [ [[CONV110]], [[COND_TRUE109]] ], [ [[CONV112]], [[COND_FALSE111]] ]
55660 // SIMD-ONLY0-NEXT:    [[CONV115:%.*]] = trunc i32 [[COND114]] to i8
55661 // SIMD-ONLY0-NEXT:    store i8 [[CONV115]], ptr [[UCX]], align 1
55662 // SIMD-ONLY0-NEXT:    [[TMP54:%.*]] = load i8, ptr [[UCX]], align 1
55663 // SIMD-ONLY0-NEXT:    store i8 [[TMP54]], ptr [[UCV]], align 1
55664 // SIMD-ONLY0-NEXT:    [[TMP55:%.*]] = load i8, ptr [[UCX]], align 1
55665 // SIMD-ONLY0-NEXT:    [[CONV116:%.*]] = zext i8 [[TMP55]] to i32
55666 // SIMD-ONLY0-NEXT:    [[TMP56:%.*]] = load i8, ptr [[UCE]], align 1
55667 // SIMD-ONLY0-NEXT:    [[CONV117:%.*]] = zext i8 [[TMP56]] to i32
55668 // SIMD-ONLY0-NEXT:    [[CMP118:%.*]] = icmp eq i32 [[CONV116]], [[CONV117]]
55669 // SIMD-ONLY0-NEXT:    br i1 [[CMP118]], label [[COND_TRUE120:%.*]], label [[COND_FALSE122:%.*]]
55670 // SIMD-ONLY0:       cond.true120:
55671 // SIMD-ONLY0-NEXT:    [[TMP57:%.*]] = load i8, ptr [[UCD]], align 1
55672 // SIMD-ONLY0-NEXT:    [[CONV121:%.*]] = zext i8 [[TMP57]] to i32
55673 // SIMD-ONLY0-NEXT:    br label [[COND_END124:%.*]]
55674 // SIMD-ONLY0:       cond.false122:
55675 // SIMD-ONLY0-NEXT:    [[TMP58:%.*]] = load i8, ptr [[UCX]], align 1
55676 // SIMD-ONLY0-NEXT:    [[CONV123:%.*]] = zext i8 [[TMP58]] to i32
55677 // SIMD-ONLY0-NEXT:    br label [[COND_END124]]
55678 // SIMD-ONLY0:       cond.end124:
55679 // SIMD-ONLY0-NEXT:    [[COND125:%.*]] = phi i32 [ [[CONV121]], [[COND_TRUE120]] ], [ [[CONV123]], [[COND_FALSE122]] ]
55680 // SIMD-ONLY0-NEXT:    [[CONV126:%.*]] = trunc i32 [[COND125]] to i8
55681 // SIMD-ONLY0-NEXT:    store i8 [[CONV126]], ptr [[UCX]], align 1
55682 // SIMD-ONLY0-NEXT:    [[TMP59:%.*]] = load i8, ptr [[UCX]], align 1
55683 // SIMD-ONLY0-NEXT:    store i8 [[TMP59]], ptr [[UCV]], align 1
55684 // SIMD-ONLY0-NEXT:    [[TMP60:%.*]] = load i8, ptr [[UCX]], align 1
55685 // SIMD-ONLY0-NEXT:    store i8 [[TMP60]], ptr [[UCV]], align 1
55686 // SIMD-ONLY0-NEXT:    [[TMP61:%.*]] = load i8, ptr [[UCX]], align 1
55687 // SIMD-ONLY0-NEXT:    [[CONV127:%.*]] = zext i8 [[TMP61]] to i32
55688 // SIMD-ONLY0-NEXT:    [[TMP62:%.*]] = load i8, ptr [[UCE]], align 1
55689 // SIMD-ONLY0-NEXT:    [[CONV128:%.*]] = zext i8 [[TMP62]] to i32
55690 // SIMD-ONLY0-NEXT:    [[CMP129:%.*]] = icmp sgt i32 [[CONV127]], [[CONV128]]
55691 // SIMD-ONLY0-NEXT:    br i1 [[CMP129]], label [[COND_TRUE131:%.*]], label [[COND_FALSE133:%.*]]
55692 // SIMD-ONLY0:       cond.true131:
55693 // SIMD-ONLY0-NEXT:    [[TMP63:%.*]] = load i8, ptr [[UCE]], align 1
55694 // SIMD-ONLY0-NEXT:    [[CONV132:%.*]] = zext i8 [[TMP63]] to i32
55695 // SIMD-ONLY0-NEXT:    br label [[COND_END135:%.*]]
55696 // SIMD-ONLY0:       cond.false133:
55697 // SIMD-ONLY0-NEXT:    [[TMP64:%.*]] = load i8, ptr [[UCX]], align 1
55698 // SIMD-ONLY0-NEXT:    [[CONV134:%.*]] = zext i8 [[TMP64]] to i32
55699 // SIMD-ONLY0-NEXT:    br label [[COND_END135]]
55700 // SIMD-ONLY0:       cond.end135:
55701 // SIMD-ONLY0-NEXT:    [[COND136:%.*]] = phi i32 [ [[CONV132]], [[COND_TRUE131]] ], [ [[CONV134]], [[COND_FALSE133]] ]
55702 // SIMD-ONLY0-NEXT:    [[CONV137:%.*]] = trunc i32 [[COND136]] to i8
55703 // SIMD-ONLY0-NEXT:    store i8 [[CONV137]], ptr [[UCX]], align 1
55704 // SIMD-ONLY0-NEXT:    [[TMP65:%.*]] = load i8, ptr [[UCX]], align 1
55705 // SIMD-ONLY0-NEXT:    store i8 [[TMP65]], ptr [[UCV]], align 1
55706 // SIMD-ONLY0-NEXT:    [[TMP66:%.*]] = load i8, ptr [[UCX]], align 1
55707 // SIMD-ONLY0-NEXT:    [[CONV138:%.*]] = zext i8 [[TMP66]] to i32
55708 // SIMD-ONLY0-NEXT:    [[TMP67:%.*]] = load i8, ptr [[UCE]], align 1
55709 // SIMD-ONLY0-NEXT:    [[CONV139:%.*]] = zext i8 [[TMP67]] to i32
55710 // SIMD-ONLY0-NEXT:    [[CMP140:%.*]] = icmp slt i32 [[CONV138]], [[CONV139]]
55711 // SIMD-ONLY0-NEXT:    br i1 [[CMP140]], label [[COND_TRUE142:%.*]], label [[COND_FALSE144:%.*]]
55712 // SIMD-ONLY0:       cond.true142:
55713 // SIMD-ONLY0-NEXT:    [[TMP68:%.*]] = load i8, ptr [[UCE]], align 1
55714 // SIMD-ONLY0-NEXT:    [[CONV143:%.*]] = zext i8 [[TMP68]] to i32
55715 // SIMD-ONLY0-NEXT:    br label [[COND_END146:%.*]]
55716 // SIMD-ONLY0:       cond.false144:
55717 // SIMD-ONLY0-NEXT:    [[TMP69:%.*]] = load i8, ptr [[UCX]], align 1
55718 // SIMD-ONLY0-NEXT:    [[CONV145:%.*]] = zext i8 [[TMP69]] to i32
55719 // SIMD-ONLY0-NEXT:    br label [[COND_END146]]
55720 // SIMD-ONLY0:       cond.end146:
55721 // SIMD-ONLY0-NEXT:    [[COND147:%.*]] = phi i32 [ [[CONV143]], [[COND_TRUE142]] ], [ [[CONV145]], [[COND_FALSE144]] ]
55722 // SIMD-ONLY0-NEXT:    [[CONV148:%.*]] = trunc i32 [[COND147]] to i8
55723 // SIMD-ONLY0-NEXT:    store i8 [[CONV148]], ptr [[UCX]], align 1
55724 // SIMD-ONLY0-NEXT:    [[TMP70:%.*]] = load i8, ptr [[UCX]], align 1
55725 // SIMD-ONLY0-NEXT:    store i8 [[TMP70]], ptr [[UCV]], align 1
55726 // SIMD-ONLY0-NEXT:    [[TMP71:%.*]] = load i8, ptr [[UCX]], align 1
55727 // SIMD-ONLY0-NEXT:    [[CONV149:%.*]] = zext i8 [[TMP71]] to i32
55728 // SIMD-ONLY0-NEXT:    [[TMP72:%.*]] = load i8, ptr [[UCE]], align 1
55729 // SIMD-ONLY0-NEXT:    [[CONV150:%.*]] = zext i8 [[TMP72]] to i32
55730 // SIMD-ONLY0-NEXT:    [[CMP151:%.*]] = icmp eq i32 [[CONV149]], [[CONV150]]
55731 // SIMD-ONLY0-NEXT:    br i1 [[CMP151]], label [[COND_TRUE153:%.*]], label [[COND_FALSE155:%.*]]
55732 // SIMD-ONLY0:       cond.true153:
55733 // SIMD-ONLY0-NEXT:    [[TMP73:%.*]] = load i8, ptr [[UCD]], align 1
55734 // SIMD-ONLY0-NEXT:    [[CONV154:%.*]] = zext i8 [[TMP73]] to i32
55735 // SIMD-ONLY0-NEXT:    br label [[COND_END157:%.*]]
55736 // SIMD-ONLY0:       cond.false155:
55737 // SIMD-ONLY0-NEXT:    [[TMP74:%.*]] = load i8, ptr [[UCX]], align 1
55738 // SIMD-ONLY0-NEXT:    [[CONV156:%.*]] = zext i8 [[TMP74]] to i32
55739 // SIMD-ONLY0-NEXT:    br label [[COND_END157]]
55740 // SIMD-ONLY0:       cond.end157:
55741 // SIMD-ONLY0-NEXT:    [[COND158:%.*]] = phi i32 [ [[CONV154]], [[COND_TRUE153]] ], [ [[CONV156]], [[COND_FALSE155]] ]
55742 // SIMD-ONLY0-NEXT:    [[CONV159:%.*]] = trunc i32 [[COND158]] to i8
55743 // SIMD-ONLY0-NEXT:    store i8 [[CONV159]], ptr [[UCX]], align 1
55744 // SIMD-ONLY0-NEXT:    [[TMP75:%.*]] = load i8, ptr [[UCX]], align 1
55745 // SIMD-ONLY0-NEXT:    [[CONV160:%.*]] = zext i8 [[TMP75]] to i32
55746 // SIMD-ONLY0-NEXT:    [[TMP76:%.*]] = load i8, ptr [[UCE]], align 1
55747 // SIMD-ONLY0-NEXT:    [[CONV161:%.*]] = zext i8 [[TMP76]] to i32
55748 // SIMD-ONLY0-NEXT:    [[CMP162:%.*]] = icmp sgt i32 [[CONV160]], [[CONV161]]
55749 // SIMD-ONLY0-NEXT:    br i1 [[CMP162]], label [[COND_TRUE164:%.*]], label [[COND_FALSE166:%.*]]
55750 // SIMD-ONLY0:       cond.true164:
55751 // SIMD-ONLY0-NEXT:    [[TMP77:%.*]] = load i8, ptr [[UCE]], align 1
55752 // SIMD-ONLY0-NEXT:    [[CONV165:%.*]] = zext i8 [[TMP77]] to i32
55753 // SIMD-ONLY0-NEXT:    br label [[COND_END168:%.*]]
55754 // SIMD-ONLY0:       cond.false166:
55755 // SIMD-ONLY0-NEXT:    [[TMP78:%.*]] = load i8, ptr [[UCX]], align 1
55756 // SIMD-ONLY0-NEXT:    [[CONV167:%.*]] = zext i8 [[TMP78]] to i32
55757 // SIMD-ONLY0-NEXT:    br label [[COND_END168]]
55758 // SIMD-ONLY0:       cond.end168:
55759 // SIMD-ONLY0-NEXT:    [[COND169:%.*]] = phi i32 [ [[CONV165]], [[COND_TRUE164]] ], [ [[CONV167]], [[COND_FALSE166]] ]
55760 // SIMD-ONLY0-NEXT:    [[CONV170:%.*]] = trunc i32 [[COND169]] to i8
55761 // SIMD-ONLY0-NEXT:    store i8 [[CONV170]], ptr [[UCX]], align 1
55762 // SIMD-ONLY0-NEXT:    [[TMP79:%.*]] = load i8, ptr [[UCX]], align 1
55763 // SIMD-ONLY0-NEXT:    store i8 [[TMP79]], ptr [[UCV]], align 1
55764 // SIMD-ONLY0-NEXT:    [[TMP80:%.*]] = load i8, ptr [[UCX]], align 1
55765 // SIMD-ONLY0-NEXT:    [[CONV171:%.*]] = zext i8 [[TMP80]] to i32
55766 // SIMD-ONLY0-NEXT:    [[TMP81:%.*]] = load i8, ptr [[UCE]], align 1
55767 // SIMD-ONLY0-NEXT:    [[CONV172:%.*]] = zext i8 [[TMP81]] to i32
55768 // SIMD-ONLY0-NEXT:    [[CMP173:%.*]] = icmp slt i32 [[CONV171]], [[CONV172]]
55769 // SIMD-ONLY0-NEXT:    br i1 [[CMP173]], label [[COND_TRUE175:%.*]], label [[COND_FALSE177:%.*]]
55770 // SIMD-ONLY0:       cond.true175:
55771 // SIMD-ONLY0-NEXT:    [[TMP82:%.*]] = load i8, ptr [[UCE]], align 1
55772 // SIMD-ONLY0-NEXT:    [[CONV176:%.*]] = zext i8 [[TMP82]] to i32
55773 // SIMD-ONLY0-NEXT:    br label [[COND_END179:%.*]]
55774 // SIMD-ONLY0:       cond.false177:
55775 // SIMD-ONLY0-NEXT:    [[TMP83:%.*]] = load i8, ptr [[UCX]], align 1
55776 // SIMD-ONLY0-NEXT:    [[CONV178:%.*]] = zext i8 [[TMP83]] to i32
55777 // SIMD-ONLY0-NEXT:    br label [[COND_END179]]
55778 // SIMD-ONLY0:       cond.end179:
55779 // SIMD-ONLY0-NEXT:    [[COND180:%.*]] = phi i32 [ [[CONV176]], [[COND_TRUE175]] ], [ [[CONV178]], [[COND_FALSE177]] ]
55780 // SIMD-ONLY0-NEXT:    [[CONV181:%.*]] = trunc i32 [[COND180]] to i8
55781 // SIMD-ONLY0-NEXT:    store i8 [[CONV181]], ptr [[UCX]], align 1
55782 // SIMD-ONLY0-NEXT:    [[TMP84:%.*]] = load i8, ptr [[UCX]], align 1
55783 // SIMD-ONLY0-NEXT:    store i8 [[TMP84]], ptr [[UCV]], align 1
55784 // SIMD-ONLY0-NEXT:    [[TMP85:%.*]] = load i8, ptr [[UCX]], align 1
55785 // SIMD-ONLY0-NEXT:    [[CONV182:%.*]] = zext i8 [[TMP85]] to i32
55786 // SIMD-ONLY0-NEXT:    [[TMP86:%.*]] = load i8, ptr [[UCE]], align 1
55787 // SIMD-ONLY0-NEXT:    [[CONV183:%.*]] = zext i8 [[TMP86]] to i32
55788 // SIMD-ONLY0-NEXT:    [[CMP184:%.*]] = icmp eq i32 [[CONV182]], [[CONV183]]
55789 // SIMD-ONLY0-NEXT:    br i1 [[CMP184]], label [[COND_TRUE186:%.*]], label [[COND_FALSE188:%.*]]
55790 // SIMD-ONLY0:       cond.true186:
55791 // SIMD-ONLY0-NEXT:    [[TMP87:%.*]] = load i8, ptr [[UCD]], align 1
55792 // SIMD-ONLY0-NEXT:    [[CONV187:%.*]] = zext i8 [[TMP87]] to i32
55793 // SIMD-ONLY0-NEXT:    br label [[COND_END190:%.*]]
55794 // SIMD-ONLY0:       cond.false188:
55795 // SIMD-ONLY0-NEXT:    [[TMP88:%.*]] = load i8, ptr [[UCX]], align 1
55796 // SIMD-ONLY0-NEXT:    [[CONV189:%.*]] = zext i8 [[TMP88]] to i32
55797 // SIMD-ONLY0-NEXT:    br label [[COND_END190]]
55798 // SIMD-ONLY0:       cond.end190:
55799 // SIMD-ONLY0-NEXT:    [[COND191:%.*]] = phi i32 [ [[CONV187]], [[COND_TRUE186]] ], [ [[CONV189]], [[COND_FALSE188]] ]
55800 // SIMD-ONLY0-NEXT:    [[CONV192:%.*]] = trunc i32 [[COND191]] to i8
55801 // SIMD-ONLY0-NEXT:    store i8 [[CONV192]], ptr [[UCX]], align 1
55802 // SIMD-ONLY0-NEXT:    [[TMP89:%.*]] = load i8, ptr [[UCX]], align 1
55803 // SIMD-ONLY0-NEXT:    store i8 [[TMP89]], ptr [[UCV]], align 1
55804 // SIMD-ONLY0-NEXT:    [[TMP90:%.*]] = load i8, ptr [[UCX]], align 1
55805 // SIMD-ONLY0-NEXT:    store i8 [[TMP90]], ptr [[UCV]], align 1
55806 // SIMD-ONLY0-NEXT:    [[TMP91:%.*]] = load i8, ptr [[UCX]], align 1
55807 // SIMD-ONLY0-NEXT:    [[CONV193:%.*]] = zext i8 [[TMP91]] to i32
55808 // SIMD-ONLY0-NEXT:    [[TMP92:%.*]] = load i8, ptr [[UCE]], align 1
55809 // SIMD-ONLY0-NEXT:    [[CONV194:%.*]] = zext i8 [[TMP92]] to i32
55810 // SIMD-ONLY0-NEXT:    [[CMP195:%.*]] = icmp sgt i32 [[CONV193]], [[CONV194]]
55811 // SIMD-ONLY0-NEXT:    br i1 [[CMP195]], label [[COND_TRUE197:%.*]], label [[COND_FALSE199:%.*]]
55812 // SIMD-ONLY0:       cond.true197:
55813 // SIMD-ONLY0-NEXT:    [[TMP93:%.*]] = load i8, ptr [[UCE]], align 1
55814 // SIMD-ONLY0-NEXT:    [[CONV198:%.*]] = zext i8 [[TMP93]] to i32
55815 // SIMD-ONLY0-NEXT:    br label [[COND_END201:%.*]]
55816 // SIMD-ONLY0:       cond.false199:
55817 // SIMD-ONLY0-NEXT:    [[TMP94:%.*]] = load i8, ptr [[UCX]], align 1
55818 // SIMD-ONLY0-NEXT:    [[CONV200:%.*]] = zext i8 [[TMP94]] to i32
55819 // SIMD-ONLY0-NEXT:    br label [[COND_END201]]
55820 // SIMD-ONLY0:       cond.end201:
55821 // SIMD-ONLY0-NEXT:    [[COND202:%.*]] = phi i32 [ [[CONV198]], [[COND_TRUE197]] ], [ [[CONV200]], [[COND_FALSE199]] ]
55822 // SIMD-ONLY0-NEXT:    [[CONV203:%.*]] = trunc i32 [[COND202]] to i8
55823 // SIMD-ONLY0-NEXT:    store i8 [[CONV203]], ptr [[UCX]], align 1
55824 // SIMD-ONLY0-NEXT:    [[TMP95:%.*]] = load i8, ptr [[UCX]], align 1
55825 // SIMD-ONLY0-NEXT:    store i8 [[TMP95]], ptr [[UCV]], align 1
55826 // SIMD-ONLY0-NEXT:    [[TMP96:%.*]] = load i8, ptr [[UCX]], align 1
55827 // SIMD-ONLY0-NEXT:    [[CONV204:%.*]] = zext i8 [[TMP96]] to i32
55828 // SIMD-ONLY0-NEXT:    [[TMP97:%.*]] = load i8, ptr [[UCE]], align 1
55829 // SIMD-ONLY0-NEXT:    [[CONV205:%.*]] = zext i8 [[TMP97]] to i32
55830 // SIMD-ONLY0-NEXT:    [[CMP206:%.*]] = icmp slt i32 [[CONV204]], [[CONV205]]
55831 // SIMD-ONLY0-NEXT:    br i1 [[CMP206]], label [[COND_TRUE208:%.*]], label [[COND_FALSE210:%.*]]
55832 // SIMD-ONLY0:       cond.true208:
55833 // SIMD-ONLY0-NEXT:    [[TMP98:%.*]] = load i8, ptr [[UCE]], align 1
55834 // SIMD-ONLY0-NEXT:    [[CONV209:%.*]] = zext i8 [[TMP98]] to i32
55835 // SIMD-ONLY0-NEXT:    br label [[COND_END212:%.*]]
55836 // SIMD-ONLY0:       cond.false210:
55837 // SIMD-ONLY0-NEXT:    [[TMP99:%.*]] = load i8, ptr [[UCX]], align 1
55838 // SIMD-ONLY0-NEXT:    [[CONV211:%.*]] = zext i8 [[TMP99]] to i32
55839 // SIMD-ONLY0-NEXT:    br label [[COND_END212]]
55840 // SIMD-ONLY0:       cond.end212:
55841 // SIMD-ONLY0-NEXT:    [[COND213:%.*]] = phi i32 [ [[CONV209]], [[COND_TRUE208]] ], [ [[CONV211]], [[COND_FALSE210]] ]
55842 // SIMD-ONLY0-NEXT:    [[CONV214:%.*]] = trunc i32 [[COND213]] to i8
55843 // SIMD-ONLY0-NEXT:    store i8 [[CONV214]], ptr [[UCX]], align 1
55844 // SIMD-ONLY0-NEXT:    [[TMP100:%.*]] = load i8, ptr [[UCX]], align 1
55845 // SIMD-ONLY0-NEXT:    store i8 [[TMP100]], ptr [[UCV]], align 1
55846 // SIMD-ONLY0-NEXT:    [[TMP101:%.*]] = load i8, ptr [[UCX]], align 1
55847 // SIMD-ONLY0-NEXT:    [[CONV215:%.*]] = zext i8 [[TMP101]] to i32
55848 // SIMD-ONLY0-NEXT:    [[TMP102:%.*]] = load i8, ptr [[UCE]], align 1
55849 // SIMD-ONLY0-NEXT:    [[CONV216:%.*]] = zext i8 [[TMP102]] to i32
55850 // SIMD-ONLY0-NEXT:    [[CMP217:%.*]] = icmp eq i32 [[CONV215]], [[CONV216]]
55851 // SIMD-ONLY0-NEXT:    br i1 [[CMP217]], label [[COND_TRUE219:%.*]], label [[COND_FALSE221:%.*]]
55852 // SIMD-ONLY0:       cond.true219:
55853 // SIMD-ONLY0-NEXT:    [[TMP103:%.*]] = load i8, ptr [[UCD]], align 1
55854 // SIMD-ONLY0-NEXT:    [[CONV220:%.*]] = zext i8 [[TMP103]] to i32
55855 // SIMD-ONLY0-NEXT:    br label [[COND_END223:%.*]]
55856 // SIMD-ONLY0:       cond.false221:
55857 // SIMD-ONLY0-NEXT:    [[TMP104:%.*]] = load i8, ptr [[UCX]], align 1
55858 // SIMD-ONLY0-NEXT:    [[CONV222:%.*]] = zext i8 [[TMP104]] to i32
55859 // SIMD-ONLY0-NEXT:    br label [[COND_END223]]
55860 // SIMD-ONLY0:       cond.end223:
55861 // SIMD-ONLY0-NEXT:    [[COND224:%.*]] = phi i32 [ [[CONV220]], [[COND_TRUE219]] ], [ [[CONV222]], [[COND_FALSE221]] ]
55862 // SIMD-ONLY0-NEXT:    [[CONV225:%.*]] = trunc i32 [[COND224]] to i8
55863 // SIMD-ONLY0-NEXT:    store i8 [[CONV225]], ptr [[UCX]], align 1
55864 // SIMD-ONLY0-NEXT:    [[TMP105:%.*]] = load i8, ptr [[UCX]], align 1
55865 // SIMD-ONLY0-NEXT:    [[CONV226:%.*]] = zext i8 [[TMP105]] to i32
55866 // SIMD-ONLY0-NEXT:    [[TMP106:%.*]] = load i8, ptr [[UCE]], align 1
55867 // SIMD-ONLY0-NEXT:    [[CONV227:%.*]] = zext i8 [[TMP106]] to i32
55868 // SIMD-ONLY0-NEXT:    [[CMP228:%.*]] = icmp sgt i32 [[CONV226]], [[CONV227]]
55869 // SIMD-ONLY0-NEXT:    br i1 [[CMP228]], label [[COND_TRUE230:%.*]], label [[COND_FALSE232:%.*]]
55870 // SIMD-ONLY0:       cond.true230:
55871 // SIMD-ONLY0-NEXT:    [[TMP107:%.*]] = load i8, ptr [[UCE]], align 1
55872 // SIMD-ONLY0-NEXT:    [[CONV231:%.*]] = zext i8 [[TMP107]] to i32
55873 // SIMD-ONLY0-NEXT:    br label [[COND_END234:%.*]]
55874 // SIMD-ONLY0:       cond.false232:
55875 // SIMD-ONLY0-NEXT:    [[TMP108:%.*]] = load i8, ptr [[UCX]], align 1
55876 // SIMD-ONLY0-NEXT:    [[CONV233:%.*]] = zext i8 [[TMP108]] to i32
55877 // SIMD-ONLY0-NEXT:    br label [[COND_END234]]
55878 // SIMD-ONLY0:       cond.end234:
55879 // SIMD-ONLY0-NEXT:    [[COND235:%.*]] = phi i32 [ [[CONV231]], [[COND_TRUE230]] ], [ [[CONV233]], [[COND_FALSE232]] ]
55880 // SIMD-ONLY0-NEXT:    [[CONV236:%.*]] = trunc i32 [[COND235]] to i8
55881 // SIMD-ONLY0-NEXT:    store i8 [[CONV236]], ptr [[UCX]], align 1
55882 // SIMD-ONLY0-NEXT:    [[TMP109:%.*]] = load i8, ptr [[UCX]], align 1
55883 // SIMD-ONLY0-NEXT:    store i8 [[TMP109]], ptr [[UCV]], align 1
55884 // SIMD-ONLY0-NEXT:    [[TMP110:%.*]] = load i8, ptr [[UCX]], align 1
55885 // SIMD-ONLY0-NEXT:    [[CONV237:%.*]] = zext i8 [[TMP110]] to i32
55886 // SIMD-ONLY0-NEXT:    [[TMP111:%.*]] = load i8, ptr [[UCE]], align 1
55887 // SIMD-ONLY0-NEXT:    [[CONV238:%.*]] = zext i8 [[TMP111]] to i32
55888 // SIMD-ONLY0-NEXT:    [[CMP239:%.*]] = icmp slt i32 [[CONV237]], [[CONV238]]
55889 // SIMD-ONLY0-NEXT:    br i1 [[CMP239]], label [[COND_TRUE241:%.*]], label [[COND_FALSE243:%.*]]
55890 // SIMD-ONLY0:       cond.true241:
55891 // SIMD-ONLY0-NEXT:    [[TMP112:%.*]] = load i8, ptr [[UCE]], align 1
55892 // SIMD-ONLY0-NEXT:    [[CONV242:%.*]] = zext i8 [[TMP112]] to i32
55893 // SIMD-ONLY0-NEXT:    br label [[COND_END245:%.*]]
55894 // SIMD-ONLY0:       cond.false243:
55895 // SIMD-ONLY0-NEXT:    [[TMP113:%.*]] = load i8, ptr [[UCX]], align 1
55896 // SIMD-ONLY0-NEXT:    [[CONV244:%.*]] = zext i8 [[TMP113]] to i32
55897 // SIMD-ONLY0-NEXT:    br label [[COND_END245]]
55898 // SIMD-ONLY0:       cond.end245:
55899 // SIMD-ONLY0-NEXT:    [[COND246:%.*]] = phi i32 [ [[CONV242]], [[COND_TRUE241]] ], [ [[CONV244]], [[COND_FALSE243]] ]
55900 // SIMD-ONLY0-NEXT:    [[CONV247:%.*]] = trunc i32 [[COND246]] to i8
55901 // SIMD-ONLY0-NEXT:    store i8 [[CONV247]], ptr [[UCX]], align 1
55902 // SIMD-ONLY0-NEXT:    [[TMP114:%.*]] = load i8, ptr [[UCX]], align 1
55903 // SIMD-ONLY0-NEXT:    store i8 [[TMP114]], ptr [[UCV]], align 1
55904 // SIMD-ONLY0-NEXT:    [[TMP115:%.*]] = load i8, ptr [[UCX]], align 1
55905 // SIMD-ONLY0-NEXT:    [[CONV248:%.*]] = zext i8 [[TMP115]] to i32
55906 // SIMD-ONLY0-NEXT:    [[TMP116:%.*]] = load i8, ptr [[UCE]], align 1
55907 // SIMD-ONLY0-NEXT:    [[CONV249:%.*]] = zext i8 [[TMP116]] to i32
55908 // SIMD-ONLY0-NEXT:    [[CMP250:%.*]] = icmp eq i32 [[CONV248]], [[CONV249]]
55909 // SIMD-ONLY0-NEXT:    br i1 [[CMP250]], label [[COND_TRUE252:%.*]], label [[COND_FALSE254:%.*]]
55910 // SIMD-ONLY0:       cond.true252:
55911 // SIMD-ONLY0-NEXT:    [[TMP117:%.*]] = load i8, ptr [[UCD]], align 1
55912 // SIMD-ONLY0-NEXT:    [[CONV253:%.*]] = zext i8 [[TMP117]] to i32
55913 // SIMD-ONLY0-NEXT:    br label [[COND_END256:%.*]]
55914 // SIMD-ONLY0:       cond.false254:
55915 // SIMD-ONLY0-NEXT:    [[TMP118:%.*]] = load i8, ptr [[UCX]], align 1
55916 // SIMD-ONLY0-NEXT:    [[CONV255:%.*]] = zext i8 [[TMP118]] to i32
55917 // SIMD-ONLY0-NEXT:    br label [[COND_END256]]
55918 // SIMD-ONLY0:       cond.end256:
55919 // SIMD-ONLY0-NEXT:    [[COND257:%.*]] = phi i32 [ [[CONV253]], [[COND_TRUE252]] ], [ [[CONV255]], [[COND_FALSE254]] ]
55920 // SIMD-ONLY0-NEXT:    [[CONV258:%.*]] = trunc i32 [[COND257]] to i8
55921 // SIMD-ONLY0-NEXT:    store i8 [[CONV258]], ptr [[UCX]], align 1
55922 // SIMD-ONLY0-NEXT:    [[TMP119:%.*]] = load i8, ptr [[UCX]], align 1
55923 // SIMD-ONLY0-NEXT:    store i8 [[TMP119]], ptr [[UCV]], align 1
55924 // SIMD-ONLY0-NEXT:    [[TMP120:%.*]] = load i8, ptr [[UCX]], align 1
55925 // SIMD-ONLY0-NEXT:    store i8 [[TMP120]], ptr [[UCV]], align 1
55926 // SIMD-ONLY0-NEXT:    [[TMP121:%.*]] = load i8, ptr [[UCX]], align 1
55927 // SIMD-ONLY0-NEXT:    [[CONV259:%.*]] = zext i8 [[TMP121]] to i32
55928 // SIMD-ONLY0-NEXT:    [[TMP122:%.*]] = load i8, ptr [[UCE]], align 1
55929 // SIMD-ONLY0-NEXT:    [[CONV260:%.*]] = zext i8 [[TMP122]] to i32
55930 // SIMD-ONLY0-NEXT:    [[CMP261:%.*]] = icmp sgt i32 [[CONV259]], [[CONV260]]
55931 // SIMD-ONLY0-NEXT:    br i1 [[CMP261]], label [[COND_TRUE263:%.*]], label [[COND_FALSE265:%.*]]
55932 // SIMD-ONLY0:       cond.true263:
55933 // SIMD-ONLY0-NEXT:    [[TMP123:%.*]] = load i8, ptr [[UCE]], align 1
55934 // SIMD-ONLY0-NEXT:    [[CONV264:%.*]] = zext i8 [[TMP123]] to i32
55935 // SIMD-ONLY0-NEXT:    br label [[COND_END267:%.*]]
55936 // SIMD-ONLY0:       cond.false265:
55937 // SIMD-ONLY0-NEXT:    [[TMP124:%.*]] = load i8, ptr [[UCX]], align 1
55938 // SIMD-ONLY0-NEXT:    [[CONV266:%.*]] = zext i8 [[TMP124]] to i32
55939 // SIMD-ONLY0-NEXT:    br label [[COND_END267]]
55940 // SIMD-ONLY0:       cond.end267:
55941 // SIMD-ONLY0-NEXT:    [[COND268:%.*]] = phi i32 [ [[CONV264]], [[COND_TRUE263]] ], [ [[CONV266]], [[COND_FALSE265]] ]
55942 // SIMD-ONLY0-NEXT:    [[CONV269:%.*]] = trunc i32 [[COND268]] to i8
55943 // SIMD-ONLY0-NEXT:    store i8 [[CONV269]], ptr [[UCX]], align 1
55944 // SIMD-ONLY0-NEXT:    [[TMP125:%.*]] = load i8, ptr [[UCX]], align 1
55945 // SIMD-ONLY0-NEXT:    store i8 [[TMP125]], ptr [[UCV]], align 1
55946 // SIMD-ONLY0-NEXT:    [[TMP126:%.*]] = load i8, ptr [[UCX]], align 1
55947 // SIMD-ONLY0-NEXT:    [[CONV270:%.*]] = zext i8 [[TMP126]] to i32
55948 // SIMD-ONLY0-NEXT:    [[TMP127:%.*]] = load i8, ptr [[UCE]], align 1
55949 // SIMD-ONLY0-NEXT:    [[CONV271:%.*]] = zext i8 [[TMP127]] to i32
55950 // SIMD-ONLY0-NEXT:    [[CMP272:%.*]] = icmp slt i32 [[CONV270]], [[CONV271]]
55951 // SIMD-ONLY0-NEXT:    br i1 [[CMP272]], label [[COND_TRUE274:%.*]], label [[COND_FALSE276:%.*]]
55952 // SIMD-ONLY0:       cond.true274:
55953 // SIMD-ONLY0-NEXT:    [[TMP128:%.*]] = load i8, ptr [[UCE]], align 1
55954 // SIMD-ONLY0-NEXT:    [[CONV275:%.*]] = zext i8 [[TMP128]] to i32
55955 // SIMD-ONLY0-NEXT:    br label [[COND_END278:%.*]]
55956 // SIMD-ONLY0:       cond.false276:
55957 // SIMD-ONLY0-NEXT:    [[TMP129:%.*]] = load i8, ptr [[UCX]], align 1
55958 // SIMD-ONLY0-NEXT:    [[CONV277:%.*]] = zext i8 [[TMP129]] to i32
55959 // SIMD-ONLY0-NEXT:    br label [[COND_END278]]
55960 // SIMD-ONLY0:       cond.end278:
55961 // SIMD-ONLY0-NEXT:    [[COND279:%.*]] = phi i32 [ [[CONV275]], [[COND_TRUE274]] ], [ [[CONV277]], [[COND_FALSE276]] ]
55962 // SIMD-ONLY0-NEXT:    [[CONV280:%.*]] = trunc i32 [[COND279]] to i8
55963 // SIMD-ONLY0-NEXT:    store i8 [[CONV280]], ptr [[UCX]], align 1
55964 // SIMD-ONLY0-NEXT:    [[TMP130:%.*]] = load i8, ptr [[UCX]], align 1
55965 // SIMD-ONLY0-NEXT:    store i8 [[TMP130]], ptr [[UCV]], align 1
55966 // SIMD-ONLY0-NEXT:    [[TMP131:%.*]] = load i8, ptr [[UCX]], align 1
55967 // SIMD-ONLY0-NEXT:    [[CONV281:%.*]] = zext i8 [[TMP131]] to i32
55968 // SIMD-ONLY0-NEXT:    [[TMP132:%.*]] = load i8, ptr [[UCE]], align 1
55969 // SIMD-ONLY0-NEXT:    [[CONV282:%.*]] = zext i8 [[TMP132]] to i32
55970 // SIMD-ONLY0-NEXT:    [[CMP283:%.*]] = icmp eq i32 [[CONV281]], [[CONV282]]
55971 // SIMD-ONLY0-NEXT:    br i1 [[CMP283]], label [[COND_TRUE285:%.*]], label [[COND_FALSE287:%.*]]
55972 // SIMD-ONLY0:       cond.true285:
55973 // SIMD-ONLY0-NEXT:    [[TMP133:%.*]] = load i8, ptr [[UCD]], align 1
55974 // SIMD-ONLY0-NEXT:    [[CONV286:%.*]] = zext i8 [[TMP133]] to i32
55975 // SIMD-ONLY0-NEXT:    br label [[COND_END289:%.*]]
55976 // SIMD-ONLY0:       cond.false287:
55977 // SIMD-ONLY0-NEXT:    [[TMP134:%.*]] = load i8, ptr [[UCX]], align 1
55978 // SIMD-ONLY0-NEXT:    [[CONV288:%.*]] = zext i8 [[TMP134]] to i32
55979 // SIMD-ONLY0-NEXT:    br label [[COND_END289]]
55980 // SIMD-ONLY0:       cond.end289:
55981 // SIMD-ONLY0-NEXT:    [[COND290:%.*]] = phi i32 [ [[CONV286]], [[COND_TRUE285]] ], [ [[CONV288]], [[COND_FALSE287]] ]
55982 // SIMD-ONLY0-NEXT:    [[CONV291:%.*]] = trunc i32 [[COND290]] to i8
55983 // SIMD-ONLY0-NEXT:    store i8 [[CONV291]], ptr [[UCX]], align 1
55984 // SIMD-ONLY0-NEXT:    [[TMP135:%.*]] = load i8, ptr [[UCX]], align 1
55985 // SIMD-ONLY0-NEXT:    [[CONV292:%.*]] = zext i8 [[TMP135]] to i32
55986 // SIMD-ONLY0-NEXT:    [[TMP136:%.*]] = load i8, ptr [[UCE]], align 1
55987 // SIMD-ONLY0-NEXT:    [[CONV293:%.*]] = zext i8 [[TMP136]] to i32
55988 // SIMD-ONLY0-NEXT:    [[CMP294:%.*]] = icmp sgt i32 [[CONV292]], [[CONV293]]
55989 // SIMD-ONLY0-NEXT:    br i1 [[CMP294]], label [[COND_TRUE296:%.*]], label [[COND_FALSE298:%.*]]
55990 // SIMD-ONLY0:       cond.true296:
55991 // SIMD-ONLY0-NEXT:    [[TMP137:%.*]] = load i8, ptr [[UCE]], align 1
55992 // SIMD-ONLY0-NEXT:    [[CONV297:%.*]] = zext i8 [[TMP137]] to i32
55993 // SIMD-ONLY0-NEXT:    br label [[COND_END300:%.*]]
55994 // SIMD-ONLY0:       cond.false298:
55995 // SIMD-ONLY0-NEXT:    [[TMP138:%.*]] = load i8, ptr [[UCX]], align 1
55996 // SIMD-ONLY0-NEXT:    [[CONV299:%.*]] = zext i8 [[TMP138]] to i32
55997 // SIMD-ONLY0-NEXT:    br label [[COND_END300]]
55998 // SIMD-ONLY0:       cond.end300:
55999 // SIMD-ONLY0-NEXT:    [[COND301:%.*]] = phi i32 [ [[CONV297]], [[COND_TRUE296]] ], [ [[CONV299]], [[COND_FALSE298]] ]
56000 // SIMD-ONLY0-NEXT:    [[CONV302:%.*]] = trunc i32 [[COND301]] to i8
56001 // SIMD-ONLY0-NEXT:    store i8 [[CONV302]], ptr [[UCX]], align 1
56002 // SIMD-ONLY0-NEXT:    [[TMP139:%.*]] = load i8, ptr [[UCX]], align 1
56003 // SIMD-ONLY0-NEXT:    store i8 [[TMP139]], ptr [[UCV]], align 1
56004 // SIMD-ONLY0-NEXT:    [[TMP140:%.*]] = load i8, ptr [[UCX]], align 1
56005 // SIMD-ONLY0-NEXT:    [[CONV303:%.*]] = zext i8 [[TMP140]] to i32
56006 // SIMD-ONLY0-NEXT:    [[TMP141:%.*]] = load i8, ptr [[UCE]], align 1
56007 // SIMD-ONLY0-NEXT:    [[CONV304:%.*]] = zext i8 [[TMP141]] to i32
56008 // SIMD-ONLY0-NEXT:    [[CMP305:%.*]] = icmp slt i32 [[CONV303]], [[CONV304]]
56009 // SIMD-ONLY0-NEXT:    br i1 [[CMP305]], label [[COND_TRUE307:%.*]], label [[COND_FALSE309:%.*]]
56010 // SIMD-ONLY0:       cond.true307:
56011 // SIMD-ONLY0-NEXT:    [[TMP142:%.*]] = load i8, ptr [[UCE]], align 1
56012 // SIMD-ONLY0-NEXT:    [[CONV308:%.*]] = zext i8 [[TMP142]] to i32
56013 // SIMD-ONLY0-NEXT:    br label [[COND_END311:%.*]]
56014 // SIMD-ONLY0:       cond.false309:
56015 // SIMD-ONLY0-NEXT:    [[TMP143:%.*]] = load i8, ptr [[UCX]], align 1
56016 // SIMD-ONLY0-NEXT:    [[CONV310:%.*]] = zext i8 [[TMP143]] to i32
56017 // SIMD-ONLY0-NEXT:    br label [[COND_END311]]
56018 // SIMD-ONLY0:       cond.end311:
56019 // SIMD-ONLY0-NEXT:    [[COND312:%.*]] = phi i32 [ [[CONV308]], [[COND_TRUE307]] ], [ [[CONV310]], [[COND_FALSE309]] ]
56020 // SIMD-ONLY0-NEXT:    [[CONV313:%.*]] = trunc i32 [[COND312]] to i8
56021 // SIMD-ONLY0-NEXT:    store i8 [[CONV313]], ptr [[UCX]], align 1
56022 // SIMD-ONLY0-NEXT:    [[TMP144:%.*]] = load i8, ptr [[UCX]], align 1
56023 // SIMD-ONLY0-NEXT:    store i8 [[TMP144]], ptr [[UCV]], align 1
56024 // SIMD-ONLY0-NEXT:    [[TMP145:%.*]] = load i8, ptr [[UCX]], align 1
56025 // SIMD-ONLY0-NEXT:    [[CONV314:%.*]] = zext i8 [[TMP145]] to i32
56026 // SIMD-ONLY0-NEXT:    [[TMP146:%.*]] = load i8, ptr [[UCE]], align 1
56027 // SIMD-ONLY0-NEXT:    [[CONV315:%.*]] = zext i8 [[TMP146]] to i32
56028 // SIMD-ONLY0-NEXT:    [[CMP316:%.*]] = icmp eq i32 [[CONV314]], [[CONV315]]
56029 // SIMD-ONLY0-NEXT:    br i1 [[CMP316]], label [[COND_TRUE318:%.*]], label [[COND_FALSE320:%.*]]
56030 // SIMD-ONLY0:       cond.true318:
56031 // SIMD-ONLY0-NEXT:    [[TMP147:%.*]] = load i8, ptr [[UCD]], align 1
56032 // SIMD-ONLY0-NEXT:    [[CONV319:%.*]] = zext i8 [[TMP147]] to i32
56033 // SIMD-ONLY0-NEXT:    br label [[COND_END322:%.*]]
56034 // SIMD-ONLY0:       cond.false320:
56035 // SIMD-ONLY0-NEXT:    [[TMP148:%.*]] = load i8, ptr [[UCX]], align 1
56036 // SIMD-ONLY0-NEXT:    [[CONV321:%.*]] = zext i8 [[TMP148]] to i32
56037 // SIMD-ONLY0-NEXT:    br label [[COND_END322]]
56038 // SIMD-ONLY0:       cond.end322:
56039 // SIMD-ONLY0-NEXT:    [[COND323:%.*]] = phi i32 [ [[CONV319]], [[COND_TRUE318]] ], [ [[CONV321]], [[COND_FALSE320]] ]
56040 // SIMD-ONLY0-NEXT:    [[CONV324:%.*]] = trunc i32 [[COND323]] to i8
56041 // SIMD-ONLY0-NEXT:    store i8 [[CONV324]], ptr [[UCX]], align 1
56042 // SIMD-ONLY0-NEXT:    [[TMP149:%.*]] = load i8, ptr [[UCX]], align 1
56043 // SIMD-ONLY0-NEXT:    store i8 [[TMP149]], ptr [[UCV]], align 1
56044 // SIMD-ONLY0-NEXT:    [[TMP150:%.*]] = load i8, ptr [[UCX]], align 1
56045 // SIMD-ONLY0-NEXT:    store i8 [[TMP150]], ptr [[UCV]], align 1
56046 // SIMD-ONLY0-NEXT:    [[TMP151:%.*]] = load i8, ptr [[UCX]], align 1
56047 // SIMD-ONLY0-NEXT:    [[CONV325:%.*]] = zext i8 [[TMP151]] to i32
56048 // SIMD-ONLY0-NEXT:    [[TMP152:%.*]] = load i8, ptr [[UCE]], align 1
56049 // SIMD-ONLY0-NEXT:    [[CONV326:%.*]] = zext i8 [[TMP152]] to i32
56050 // SIMD-ONLY0-NEXT:    [[CMP327:%.*]] = icmp sgt i32 [[CONV325]], [[CONV326]]
56051 // SIMD-ONLY0-NEXT:    br i1 [[CMP327]], label [[COND_TRUE329:%.*]], label [[COND_FALSE331:%.*]]
56052 // SIMD-ONLY0:       cond.true329:
56053 // SIMD-ONLY0-NEXT:    [[TMP153:%.*]] = load i8, ptr [[UCE]], align 1
56054 // SIMD-ONLY0-NEXT:    [[CONV330:%.*]] = zext i8 [[TMP153]] to i32
56055 // SIMD-ONLY0-NEXT:    br label [[COND_END333:%.*]]
56056 // SIMD-ONLY0:       cond.false331:
56057 // SIMD-ONLY0-NEXT:    [[TMP154:%.*]] = load i8, ptr [[UCX]], align 1
56058 // SIMD-ONLY0-NEXT:    [[CONV332:%.*]] = zext i8 [[TMP154]] to i32
56059 // SIMD-ONLY0-NEXT:    br label [[COND_END333]]
56060 // SIMD-ONLY0:       cond.end333:
56061 // SIMD-ONLY0-NEXT:    [[COND334:%.*]] = phi i32 [ [[CONV330]], [[COND_TRUE329]] ], [ [[CONV332]], [[COND_FALSE331]] ]
56062 // SIMD-ONLY0-NEXT:    [[CONV335:%.*]] = trunc i32 [[COND334]] to i8
56063 // SIMD-ONLY0-NEXT:    store i8 [[CONV335]], ptr [[UCX]], align 1
56064 // SIMD-ONLY0-NEXT:    [[TMP155:%.*]] = load i8, ptr [[UCX]], align 1
56065 // SIMD-ONLY0-NEXT:    store i8 [[TMP155]], ptr [[UCV]], align 1
56066 // SIMD-ONLY0-NEXT:    [[TMP156:%.*]] = load i8, ptr [[UCX]], align 1
56067 // SIMD-ONLY0-NEXT:    [[CONV336:%.*]] = zext i8 [[TMP156]] to i32
56068 // SIMD-ONLY0-NEXT:    [[TMP157:%.*]] = load i8, ptr [[UCE]], align 1
56069 // SIMD-ONLY0-NEXT:    [[CONV337:%.*]] = zext i8 [[TMP157]] to i32
56070 // SIMD-ONLY0-NEXT:    [[CMP338:%.*]] = icmp slt i32 [[CONV336]], [[CONV337]]
56071 // SIMD-ONLY0-NEXT:    br i1 [[CMP338]], label [[COND_TRUE340:%.*]], label [[COND_FALSE342:%.*]]
56072 // SIMD-ONLY0:       cond.true340:
56073 // SIMD-ONLY0-NEXT:    [[TMP158:%.*]] = load i8, ptr [[UCE]], align 1
56074 // SIMD-ONLY0-NEXT:    [[CONV341:%.*]] = zext i8 [[TMP158]] to i32
56075 // SIMD-ONLY0-NEXT:    br label [[COND_END344:%.*]]
56076 // SIMD-ONLY0:       cond.false342:
56077 // SIMD-ONLY0-NEXT:    [[TMP159:%.*]] = load i8, ptr [[UCX]], align 1
56078 // SIMD-ONLY0-NEXT:    [[CONV343:%.*]] = zext i8 [[TMP159]] to i32
56079 // SIMD-ONLY0-NEXT:    br label [[COND_END344]]
56080 // SIMD-ONLY0:       cond.end344:
56081 // SIMD-ONLY0-NEXT:    [[COND345:%.*]] = phi i32 [ [[CONV341]], [[COND_TRUE340]] ], [ [[CONV343]], [[COND_FALSE342]] ]
56082 // SIMD-ONLY0-NEXT:    [[CONV346:%.*]] = trunc i32 [[COND345]] to i8
56083 // SIMD-ONLY0-NEXT:    store i8 [[CONV346]], ptr [[UCX]], align 1
56084 // SIMD-ONLY0-NEXT:    [[TMP160:%.*]] = load i8, ptr [[UCX]], align 1
56085 // SIMD-ONLY0-NEXT:    store i8 [[TMP160]], ptr [[UCV]], align 1
56086 // SIMD-ONLY0-NEXT:    [[TMP161:%.*]] = load i8, ptr [[UCX]], align 1
56087 // SIMD-ONLY0-NEXT:    [[CONV347:%.*]] = zext i8 [[TMP161]] to i32
56088 // SIMD-ONLY0-NEXT:    [[TMP162:%.*]] = load i8, ptr [[UCE]], align 1
56089 // SIMD-ONLY0-NEXT:    [[CONV348:%.*]] = zext i8 [[TMP162]] to i32
56090 // SIMD-ONLY0-NEXT:    [[CMP349:%.*]] = icmp eq i32 [[CONV347]], [[CONV348]]
56091 // SIMD-ONLY0-NEXT:    br i1 [[CMP349]], label [[COND_TRUE351:%.*]], label [[COND_FALSE353:%.*]]
56092 // SIMD-ONLY0:       cond.true351:
56093 // SIMD-ONLY0-NEXT:    [[TMP163:%.*]] = load i8, ptr [[UCD]], align 1
56094 // SIMD-ONLY0-NEXT:    [[CONV352:%.*]] = zext i8 [[TMP163]] to i32
56095 // SIMD-ONLY0-NEXT:    br label [[COND_END355:%.*]]
56096 // SIMD-ONLY0:       cond.false353:
56097 // SIMD-ONLY0-NEXT:    [[TMP164:%.*]] = load i8, ptr [[UCX]], align 1
56098 // SIMD-ONLY0-NEXT:    [[CONV354:%.*]] = zext i8 [[TMP164]] to i32
56099 // SIMD-ONLY0-NEXT:    br label [[COND_END355]]
56100 // SIMD-ONLY0:       cond.end355:
56101 // SIMD-ONLY0-NEXT:    [[COND356:%.*]] = phi i32 [ [[CONV352]], [[COND_TRUE351]] ], [ [[CONV354]], [[COND_FALSE353]] ]
56102 // SIMD-ONLY0-NEXT:    [[CONV357:%.*]] = trunc i32 [[COND356]] to i8
56103 // SIMD-ONLY0-NEXT:    store i8 [[CONV357]], ptr [[UCX]], align 1
56104 // SIMD-ONLY0-NEXT:    [[TMP165:%.*]] = load i8, ptr [[UCX]], align 1
56105 // SIMD-ONLY0-NEXT:    [[CONV358:%.*]] = zext i8 [[TMP165]] to i32
56106 // SIMD-ONLY0-NEXT:    [[TMP166:%.*]] = load i8, ptr [[UCE]], align 1
56107 // SIMD-ONLY0-NEXT:    [[CONV359:%.*]] = zext i8 [[TMP166]] to i32
56108 // SIMD-ONLY0-NEXT:    [[CMP360:%.*]] = icmp sgt i32 [[CONV358]], [[CONV359]]
56109 // SIMD-ONLY0-NEXT:    br i1 [[CMP360]], label [[COND_TRUE362:%.*]], label [[COND_FALSE364:%.*]]
56110 // SIMD-ONLY0:       cond.true362:
56111 // SIMD-ONLY0-NEXT:    [[TMP167:%.*]] = load i8, ptr [[UCE]], align 1
56112 // SIMD-ONLY0-NEXT:    [[CONV363:%.*]] = zext i8 [[TMP167]] to i32
56113 // SIMD-ONLY0-NEXT:    br label [[COND_END366:%.*]]
56114 // SIMD-ONLY0:       cond.false364:
56115 // SIMD-ONLY0-NEXT:    [[TMP168:%.*]] = load i8, ptr [[UCX]], align 1
56116 // SIMD-ONLY0-NEXT:    [[CONV365:%.*]] = zext i8 [[TMP168]] to i32
56117 // SIMD-ONLY0-NEXT:    br label [[COND_END366]]
56118 // SIMD-ONLY0:       cond.end366:
56119 // SIMD-ONLY0-NEXT:    [[COND367:%.*]] = phi i32 [ [[CONV363]], [[COND_TRUE362]] ], [ [[CONV365]], [[COND_FALSE364]] ]
56120 // SIMD-ONLY0-NEXT:    [[CONV368:%.*]] = trunc i32 [[COND367]] to i8
56121 // SIMD-ONLY0-NEXT:    store i8 [[CONV368]], ptr [[UCX]], align 1
56122 // SIMD-ONLY0-NEXT:    [[TMP169:%.*]] = load i8, ptr [[UCX]], align 1
56123 // SIMD-ONLY0-NEXT:    store i8 [[TMP169]], ptr [[UCV]], align 1
56124 // SIMD-ONLY0-NEXT:    [[TMP170:%.*]] = load i8, ptr [[UCX]], align 1
56125 // SIMD-ONLY0-NEXT:    [[CONV369:%.*]] = zext i8 [[TMP170]] to i32
56126 // SIMD-ONLY0-NEXT:    [[TMP171:%.*]] = load i8, ptr [[UCE]], align 1
56127 // SIMD-ONLY0-NEXT:    [[CONV370:%.*]] = zext i8 [[TMP171]] to i32
56128 // SIMD-ONLY0-NEXT:    [[CMP371:%.*]] = icmp slt i32 [[CONV369]], [[CONV370]]
56129 // SIMD-ONLY0-NEXT:    br i1 [[CMP371]], label [[COND_TRUE373:%.*]], label [[COND_FALSE375:%.*]]
56130 // SIMD-ONLY0:       cond.true373:
56131 // SIMD-ONLY0-NEXT:    [[TMP172:%.*]] = load i8, ptr [[UCE]], align 1
56132 // SIMD-ONLY0-NEXT:    [[CONV374:%.*]] = zext i8 [[TMP172]] to i32
56133 // SIMD-ONLY0-NEXT:    br label [[COND_END377:%.*]]
56134 // SIMD-ONLY0:       cond.false375:
56135 // SIMD-ONLY0-NEXT:    [[TMP173:%.*]] = load i8, ptr [[UCX]], align 1
56136 // SIMD-ONLY0-NEXT:    [[CONV376:%.*]] = zext i8 [[TMP173]] to i32
56137 // SIMD-ONLY0-NEXT:    br label [[COND_END377]]
56138 // SIMD-ONLY0:       cond.end377:
56139 // SIMD-ONLY0-NEXT:    [[COND378:%.*]] = phi i32 [ [[CONV374]], [[COND_TRUE373]] ], [ [[CONV376]], [[COND_FALSE375]] ]
56140 // SIMD-ONLY0-NEXT:    [[CONV379:%.*]] = trunc i32 [[COND378]] to i8
56141 // SIMD-ONLY0-NEXT:    store i8 [[CONV379]], ptr [[UCX]], align 1
56142 // SIMD-ONLY0-NEXT:    [[TMP174:%.*]] = load i8, ptr [[UCX]], align 1
56143 // SIMD-ONLY0-NEXT:    store i8 [[TMP174]], ptr [[UCV]], align 1
56144 // SIMD-ONLY0-NEXT:    [[TMP175:%.*]] = load i8, ptr [[UCX]], align 1
56145 // SIMD-ONLY0-NEXT:    [[CONV380:%.*]] = zext i8 [[TMP175]] to i32
56146 // SIMD-ONLY0-NEXT:    [[TMP176:%.*]] = load i8, ptr [[UCE]], align 1
56147 // SIMD-ONLY0-NEXT:    [[CONV381:%.*]] = zext i8 [[TMP176]] to i32
56148 // SIMD-ONLY0-NEXT:    [[CMP382:%.*]] = icmp eq i32 [[CONV380]], [[CONV381]]
56149 // SIMD-ONLY0-NEXT:    br i1 [[CMP382]], label [[COND_TRUE384:%.*]], label [[COND_FALSE386:%.*]]
56150 // SIMD-ONLY0:       cond.true384:
56151 // SIMD-ONLY0-NEXT:    [[TMP177:%.*]] = load i8, ptr [[UCD]], align 1
56152 // SIMD-ONLY0-NEXT:    [[CONV385:%.*]] = zext i8 [[TMP177]] to i32
56153 // SIMD-ONLY0-NEXT:    br label [[COND_END388:%.*]]
56154 // SIMD-ONLY0:       cond.false386:
56155 // SIMD-ONLY0-NEXT:    [[TMP178:%.*]] = load i8, ptr [[UCX]], align 1
56156 // SIMD-ONLY0-NEXT:    [[CONV387:%.*]] = zext i8 [[TMP178]] to i32
56157 // SIMD-ONLY0-NEXT:    br label [[COND_END388]]
56158 // SIMD-ONLY0:       cond.end388:
56159 // SIMD-ONLY0-NEXT:    [[COND389:%.*]] = phi i32 [ [[CONV385]], [[COND_TRUE384]] ], [ [[CONV387]], [[COND_FALSE386]] ]
56160 // SIMD-ONLY0-NEXT:    [[CONV390:%.*]] = trunc i32 [[COND389]] to i8
56161 // SIMD-ONLY0-NEXT:    store i8 [[CONV390]], ptr [[UCX]], align 1
56162 // SIMD-ONLY0-NEXT:    [[TMP179:%.*]] = load i8, ptr [[UCX]], align 1
56163 // SIMD-ONLY0-NEXT:    store i8 [[TMP179]], ptr [[UCV]], align 1
56164 // SIMD-ONLY0-NEXT:    [[TMP180:%.*]] = load i8, ptr [[UCV]], align 1
56165 // SIMD-ONLY0-NEXT:    ret i8 [[TMP180]]
56166 //
56167 //
56168 // SIMD-ONLY0-LABEL: @sxevd(
56169 // SIMD-ONLY0-NEXT:  entry:
56170 // SIMD-ONLY0-NEXT:    [[SX:%.*]] = alloca i16, align 2
56171 // SIMD-ONLY0-NEXT:    [[SV:%.*]] = alloca i16, align 2
56172 // SIMD-ONLY0-NEXT:    [[SE:%.*]] = alloca i16, align 2
56173 // SIMD-ONLY0-NEXT:    [[SD:%.*]] = alloca i16, align 2
56174 // SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = load i16, ptr [[SX]], align 2
56175 // SIMD-ONLY0-NEXT:    store i16 [[TMP0]], ptr [[SV]], align 2
56176 // SIMD-ONLY0-NEXT:    [[TMP1:%.*]] = load i16, ptr [[SX]], align 2
56177 // SIMD-ONLY0-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
56178 // SIMD-ONLY0-NEXT:    [[TMP2:%.*]] = load i16, ptr [[SE]], align 2
56179 // SIMD-ONLY0-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
56180 // SIMD-ONLY0-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[CONV]], [[CONV1]]
56181 // SIMD-ONLY0-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
56182 // SIMD-ONLY0:       cond.true:
56183 // SIMD-ONLY0-NEXT:    [[TMP3:%.*]] = load i16, ptr [[SE]], align 2
56184 // SIMD-ONLY0-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP3]] to i32
56185 // SIMD-ONLY0-NEXT:    br label [[COND_END:%.*]]
56186 // SIMD-ONLY0:       cond.false:
56187 // SIMD-ONLY0-NEXT:    [[TMP4:%.*]] = load i16, ptr [[SX]], align 2
56188 // SIMD-ONLY0-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP4]] to i32
56189 // SIMD-ONLY0-NEXT:    br label [[COND_END]]
56190 // SIMD-ONLY0:       cond.end:
56191 // SIMD-ONLY0-NEXT:    [[COND:%.*]] = phi i32 [ [[CONV3]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ]
56192 // SIMD-ONLY0-NEXT:    [[CONV5:%.*]] = trunc i32 [[COND]] to i16
56193 // SIMD-ONLY0-NEXT:    store i16 [[CONV5]], ptr [[SX]], align 2
56194 // SIMD-ONLY0-NEXT:    [[TMP5:%.*]] = load i16, ptr [[SX]], align 2
56195 // SIMD-ONLY0-NEXT:    store i16 [[TMP5]], ptr [[SV]], align 2
56196 // SIMD-ONLY0-NEXT:    [[TMP6:%.*]] = load i16, ptr [[SX]], align 2
56197 // SIMD-ONLY0-NEXT:    [[CONV6:%.*]] = sext i16 [[TMP6]] to i32
56198 // SIMD-ONLY0-NEXT:    [[TMP7:%.*]] = load i16, ptr [[SE]], align 2
56199 // SIMD-ONLY0-NEXT:    [[CONV7:%.*]] = sext i16 [[TMP7]] to i32
56200 // SIMD-ONLY0-NEXT:    [[CMP8:%.*]] = icmp slt i32 [[CONV6]], [[CONV7]]
56201 // SIMD-ONLY0-NEXT:    br i1 [[CMP8]], label [[COND_TRUE10:%.*]], label [[COND_FALSE12:%.*]]
56202 // SIMD-ONLY0:       cond.true10:
56203 // SIMD-ONLY0-NEXT:    [[TMP8:%.*]] = load i16, ptr [[SE]], align 2
56204 // SIMD-ONLY0-NEXT:    [[CONV11:%.*]] = sext i16 [[TMP8]] to i32
56205 // SIMD-ONLY0-NEXT:    br label [[COND_END14:%.*]]
56206 // SIMD-ONLY0:       cond.false12:
56207 // SIMD-ONLY0-NEXT:    [[TMP9:%.*]] = load i16, ptr [[SX]], align 2
56208 // SIMD-ONLY0-NEXT:    [[CONV13:%.*]] = sext i16 [[TMP9]] to i32
56209 // SIMD-ONLY0-NEXT:    br label [[COND_END14]]
56210 // SIMD-ONLY0:       cond.end14:
56211 // SIMD-ONLY0-NEXT:    [[COND15:%.*]] = phi i32 [ [[CONV11]], [[COND_TRUE10]] ], [ [[CONV13]], [[COND_FALSE12]] ]
56212 // SIMD-ONLY0-NEXT:    [[CONV16:%.*]] = trunc i32 [[COND15]] to i16
56213 // SIMD-ONLY0-NEXT:    store i16 [[CONV16]], ptr [[SX]], align 2
56214 // SIMD-ONLY0-NEXT:    [[TMP10:%.*]] = load i16, ptr [[SX]], align 2
56215 // SIMD-ONLY0-NEXT:    store i16 [[TMP10]], ptr [[SV]], align 2
56216 // SIMD-ONLY0-NEXT:    [[TMP11:%.*]] = load i16, ptr [[SX]], align 2
56217 // SIMD-ONLY0-NEXT:    [[CONV17:%.*]] = sext i16 [[TMP11]] to i32
56218 // SIMD-ONLY0-NEXT:    [[TMP12:%.*]] = load i16, ptr [[SE]], align 2
56219 // SIMD-ONLY0-NEXT:    [[CONV18:%.*]] = sext i16 [[TMP12]] to i32
56220 // SIMD-ONLY0-NEXT:    [[CMP19:%.*]] = icmp eq i32 [[CONV17]], [[CONV18]]
56221 // SIMD-ONLY0-NEXT:    br i1 [[CMP19]], label [[COND_TRUE21:%.*]], label [[COND_FALSE23:%.*]]
56222 // SIMD-ONLY0:       cond.true21:
56223 // SIMD-ONLY0-NEXT:    [[TMP13:%.*]] = load i16, ptr [[SD]], align 2
56224 // SIMD-ONLY0-NEXT:    [[CONV22:%.*]] = sext i16 [[TMP13]] to i32
56225 // SIMD-ONLY0-NEXT:    br label [[COND_END25:%.*]]
56226 // SIMD-ONLY0:       cond.false23:
56227 // SIMD-ONLY0-NEXT:    [[TMP14:%.*]] = load i16, ptr [[SX]], align 2
56228 // SIMD-ONLY0-NEXT:    [[CONV24:%.*]] = sext i16 [[TMP14]] to i32
56229 // SIMD-ONLY0-NEXT:    br label [[COND_END25]]
56230 // SIMD-ONLY0:       cond.end25:
56231 // SIMD-ONLY0-NEXT:    [[COND26:%.*]] = phi i32 [ [[CONV22]], [[COND_TRUE21]] ], [ [[CONV24]], [[COND_FALSE23]] ]
56232 // SIMD-ONLY0-NEXT:    [[CONV27:%.*]] = trunc i32 [[COND26]] to i16
56233 // SIMD-ONLY0-NEXT:    store i16 [[CONV27]], ptr [[SX]], align 2
56234 // SIMD-ONLY0-NEXT:    [[TMP15:%.*]] = load i16, ptr [[SX]], align 2
56235 // SIMD-ONLY0-NEXT:    [[CONV28:%.*]] = sext i16 [[TMP15]] to i32
56236 // SIMD-ONLY0-NEXT:    [[TMP16:%.*]] = load i16, ptr [[SE]], align 2
56237 // SIMD-ONLY0-NEXT:    [[CONV29:%.*]] = sext i16 [[TMP16]] to i32
56238 // SIMD-ONLY0-NEXT:    [[CMP30:%.*]] = icmp sgt i32 [[CONV28]], [[CONV29]]
56239 // SIMD-ONLY0-NEXT:    br i1 [[CMP30]], label [[COND_TRUE32:%.*]], label [[COND_FALSE34:%.*]]
56240 // SIMD-ONLY0:       cond.true32:
56241 // SIMD-ONLY0-NEXT:    [[TMP17:%.*]] = load i16, ptr [[SE]], align 2
56242 // SIMD-ONLY0-NEXT:    [[CONV33:%.*]] = sext i16 [[TMP17]] to i32
56243 // SIMD-ONLY0-NEXT:    br label [[COND_END36:%.*]]
56244 // SIMD-ONLY0:       cond.false34:
56245 // SIMD-ONLY0-NEXT:    [[TMP18:%.*]] = load i16, ptr [[SX]], align 2
56246 // SIMD-ONLY0-NEXT:    [[CONV35:%.*]] = sext i16 [[TMP18]] to i32
56247 // SIMD-ONLY0-NEXT:    br label [[COND_END36]]
56248 // SIMD-ONLY0:       cond.end36:
56249 // SIMD-ONLY0-NEXT:    [[COND37:%.*]] = phi i32 [ [[CONV33]], [[COND_TRUE32]] ], [ [[CONV35]], [[COND_FALSE34]] ]
56250 // SIMD-ONLY0-NEXT:    [[CONV38:%.*]] = trunc i32 [[COND37]] to i16
56251 // SIMD-ONLY0-NEXT:    store i16 [[CONV38]], ptr [[SX]], align 2
56252 // SIMD-ONLY0-NEXT:    [[TMP19:%.*]] = load i16, ptr [[SX]], align 2
56253 // SIMD-ONLY0-NEXT:    store i16 [[TMP19]], ptr [[SV]], align 2
56254 // SIMD-ONLY0-NEXT:    [[TMP20:%.*]] = load i16, ptr [[SX]], align 2
56255 // SIMD-ONLY0-NEXT:    [[CONV39:%.*]] = sext i16 [[TMP20]] to i32
56256 // SIMD-ONLY0-NEXT:    [[TMP21:%.*]] = load i16, ptr [[SE]], align 2
56257 // SIMD-ONLY0-NEXT:    [[CONV40:%.*]] = sext i16 [[TMP21]] to i32
56258 // SIMD-ONLY0-NEXT:    [[CMP41:%.*]] = icmp slt i32 [[CONV39]], [[CONV40]]
56259 // SIMD-ONLY0-NEXT:    br i1 [[CMP41]], label [[COND_TRUE43:%.*]], label [[COND_FALSE45:%.*]]
56260 // SIMD-ONLY0:       cond.true43:
56261 // SIMD-ONLY0-NEXT:    [[TMP22:%.*]] = load i16, ptr [[SE]], align 2
56262 // SIMD-ONLY0-NEXT:    [[CONV44:%.*]] = sext i16 [[TMP22]] to i32
56263 // SIMD-ONLY0-NEXT:    br label [[COND_END47:%.*]]
56264 // SIMD-ONLY0:       cond.false45:
56265 // SIMD-ONLY0-NEXT:    [[TMP23:%.*]] = load i16, ptr [[SX]], align 2
56266 // SIMD-ONLY0-NEXT:    [[CONV46:%.*]] = sext i16 [[TMP23]] to i32
56267 // SIMD-ONLY0-NEXT:    br label [[COND_END47]]
56268 // SIMD-ONLY0:       cond.end47:
56269 // SIMD-ONLY0-NEXT:    [[COND48:%.*]] = phi i32 [ [[CONV44]], [[COND_TRUE43]] ], [ [[CONV46]], [[COND_FALSE45]] ]
56270 // SIMD-ONLY0-NEXT:    [[CONV49:%.*]] = trunc i32 [[COND48]] to i16
56271 // SIMD-ONLY0-NEXT:    store i16 [[CONV49]], ptr [[SX]], align 2
56272 // SIMD-ONLY0-NEXT:    [[TMP24:%.*]] = load i16, ptr [[SX]], align 2
56273 // SIMD-ONLY0-NEXT:    store i16 [[TMP24]], ptr [[SV]], align 2
56274 // SIMD-ONLY0-NEXT:    [[TMP25:%.*]] = load i16, ptr [[SX]], align 2
56275 // SIMD-ONLY0-NEXT:    [[CONV50:%.*]] = sext i16 [[TMP25]] to i32
56276 // SIMD-ONLY0-NEXT:    [[TMP26:%.*]] = load i16, ptr [[SE]], align 2
56277 // SIMD-ONLY0-NEXT:    [[CONV51:%.*]] = sext i16 [[TMP26]] to i32
56278 // SIMD-ONLY0-NEXT:    [[CMP52:%.*]] = icmp eq i32 [[CONV50]], [[CONV51]]
56279 // SIMD-ONLY0-NEXT:    br i1 [[CMP52]], label [[COND_TRUE54:%.*]], label [[COND_FALSE56:%.*]]
56280 // SIMD-ONLY0:       cond.true54:
56281 // SIMD-ONLY0-NEXT:    [[TMP27:%.*]] = load i16, ptr [[SD]], align 2
56282 // SIMD-ONLY0-NEXT:    [[CONV55:%.*]] = sext i16 [[TMP27]] to i32
56283 // SIMD-ONLY0-NEXT:    br label [[COND_END58:%.*]]
56284 // SIMD-ONLY0:       cond.false56:
56285 // SIMD-ONLY0-NEXT:    [[TMP28:%.*]] = load i16, ptr [[SX]], align 2
56286 // SIMD-ONLY0-NEXT:    [[CONV57:%.*]] = sext i16 [[TMP28]] to i32
56287 // SIMD-ONLY0-NEXT:    br label [[COND_END58]]
56288 // SIMD-ONLY0:       cond.end58:
56289 // SIMD-ONLY0-NEXT:    [[COND59:%.*]] = phi i32 [ [[CONV55]], [[COND_TRUE54]] ], [ [[CONV57]], [[COND_FALSE56]] ]
56290 // SIMD-ONLY0-NEXT:    [[CONV60:%.*]] = trunc i32 [[COND59]] to i16
56291 // SIMD-ONLY0-NEXT:    store i16 [[CONV60]], ptr [[SX]], align 2
56292 // SIMD-ONLY0-NEXT:    [[TMP29:%.*]] = load i16, ptr [[SX]], align 2
56293 // SIMD-ONLY0-NEXT:    store i16 [[TMP29]], ptr [[SV]], align 2
56294 // SIMD-ONLY0-NEXT:    [[TMP30:%.*]] = load i16, ptr [[SX]], align 2
56295 // SIMD-ONLY0-NEXT:    store i16 [[TMP30]], ptr [[SV]], align 2
56296 // SIMD-ONLY0-NEXT:    [[TMP31:%.*]] = load i16, ptr [[SX]], align 2
56297 // SIMD-ONLY0-NEXT:    [[CONV61:%.*]] = sext i16 [[TMP31]] to i32
56298 // SIMD-ONLY0-NEXT:    [[TMP32:%.*]] = load i16, ptr [[SE]], align 2
56299 // SIMD-ONLY0-NEXT:    [[CONV62:%.*]] = sext i16 [[TMP32]] to i32
56300 // SIMD-ONLY0-NEXT:    [[CMP63:%.*]] = icmp sgt i32 [[CONV61]], [[CONV62]]
56301 // SIMD-ONLY0-NEXT:    br i1 [[CMP63]], label [[COND_TRUE65:%.*]], label [[COND_FALSE67:%.*]]
56302 // SIMD-ONLY0:       cond.true65:
56303 // SIMD-ONLY0-NEXT:    [[TMP33:%.*]] = load i16, ptr [[SE]], align 2
56304 // SIMD-ONLY0-NEXT:    [[CONV66:%.*]] = sext i16 [[TMP33]] to i32
56305 // SIMD-ONLY0-NEXT:    br label [[COND_END69:%.*]]
56306 // SIMD-ONLY0:       cond.false67:
56307 // SIMD-ONLY0-NEXT:    [[TMP34:%.*]] = load i16, ptr [[SX]], align 2
56308 // SIMD-ONLY0-NEXT:    [[CONV68:%.*]] = sext i16 [[TMP34]] to i32
56309 // SIMD-ONLY0-NEXT:    br label [[COND_END69]]
56310 // SIMD-ONLY0:       cond.end69:
56311 // SIMD-ONLY0-NEXT:    [[COND70:%.*]] = phi i32 [ [[CONV66]], [[COND_TRUE65]] ], [ [[CONV68]], [[COND_FALSE67]] ]
56312 // SIMD-ONLY0-NEXT:    [[CONV71:%.*]] = trunc i32 [[COND70]] to i16
56313 // SIMD-ONLY0-NEXT:    store i16 [[CONV71]], ptr [[SX]], align 2
56314 // SIMD-ONLY0-NEXT:    [[TMP35:%.*]] = load i16, ptr [[SX]], align 2
56315 // SIMD-ONLY0-NEXT:    store i16 [[TMP35]], ptr [[SV]], align 2
56316 // SIMD-ONLY0-NEXT:    [[TMP36:%.*]] = load i16, ptr [[SX]], align 2
56317 // SIMD-ONLY0-NEXT:    [[CONV72:%.*]] = sext i16 [[TMP36]] to i32
56318 // SIMD-ONLY0-NEXT:    [[TMP37:%.*]] = load i16, ptr [[SE]], align 2
56319 // SIMD-ONLY0-NEXT:    [[CONV73:%.*]] = sext i16 [[TMP37]] to i32
56320 // SIMD-ONLY0-NEXT:    [[CMP74:%.*]] = icmp slt i32 [[CONV72]], [[CONV73]]
56321 // SIMD-ONLY0-NEXT:    br i1 [[CMP74]], label [[COND_TRUE76:%.*]], label [[COND_FALSE78:%.*]]
56322 // SIMD-ONLY0:       cond.true76:
56323 // SIMD-ONLY0-NEXT:    [[TMP38:%.*]] = load i16, ptr [[SE]], align 2
56324 // SIMD-ONLY0-NEXT:    [[CONV77:%.*]] = sext i16 [[TMP38]] to i32
56325 // SIMD-ONLY0-NEXT:    br label [[COND_END80:%.*]]
56326 // SIMD-ONLY0:       cond.false78:
56327 // SIMD-ONLY0-NEXT:    [[TMP39:%.*]] = load i16, ptr [[SX]], align 2
56328 // SIMD-ONLY0-NEXT:    [[CONV79:%.*]] = sext i16 [[TMP39]] to i32
56329 // SIMD-ONLY0-NEXT:    br label [[COND_END80]]
56330 // SIMD-ONLY0:       cond.end80:
56331 // SIMD-ONLY0-NEXT:    [[COND81:%.*]] = phi i32 [ [[CONV77]], [[COND_TRUE76]] ], [ [[CONV79]], [[COND_FALSE78]] ]
56332 // SIMD-ONLY0-NEXT:    [[CONV82:%.*]] = trunc i32 [[COND81]] to i16
56333 // SIMD-ONLY0-NEXT:    store i16 [[CONV82]], ptr [[SX]], align 2
56334 // SIMD-ONLY0-NEXT:    [[TMP40:%.*]] = load i16, ptr [[SX]], align 2
56335 // SIMD-ONLY0-NEXT:    store i16 [[TMP40]], ptr [[SV]], align 2
56336 // SIMD-ONLY0-NEXT:    [[TMP41:%.*]] = load i16, ptr [[SX]], align 2
56337 // SIMD-ONLY0-NEXT:    [[CONV83:%.*]] = sext i16 [[TMP41]] to i32
56338 // SIMD-ONLY0-NEXT:    [[TMP42:%.*]] = load i16, ptr [[SE]], align 2
56339 // SIMD-ONLY0-NEXT:    [[CONV84:%.*]] = sext i16 [[TMP42]] to i32
56340 // SIMD-ONLY0-NEXT:    [[CMP85:%.*]] = icmp eq i32 [[CONV83]], [[CONV84]]
56341 // SIMD-ONLY0-NEXT:    br i1 [[CMP85]], label [[COND_TRUE87:%.*]], label [[COND_FALSE89:%.*]]
56342 // SIMD-ONLY0:       cond.true87:
56343 // SIMD-ONLY0-NEXT:    [[TMP43:%.*]] = load i16, ptr [[SD]], align 2
56344 // SIMD-ONLY0-NEXT:    [[CONV88:%.*]] = sext i16 [[TMP43]] to i32
56345 // SIMD-ONLY0-NEXT:    br label [[COND_END91:%.*]]
56346 // SIMD-ONLY0:       cond.false89:
56347 // SIMD-ONLY0-NEXT:    [[TMP44:%.*]] = load i16, ptr [[SX]], align 2
56348 // SIMD-ONLY0-NEXT:    [[CONV90:%.*]] = sext i16 [[TMP44]] to i32
56349 // SIMD-ONLY0-NEXT:    br label [[COND_END91]]
56350 // SIMD-ONLY0:       cond.end91:
56351 // SIMD-ONLY0-NEXT:    [[COND92:%.*]] = phi i32 [ [[CONV88]], [[COND_TRUE87]] ], [ [[CONV90]], [[COND_FALSE89]] ]
56352 // SIMD-ONLY0-NEXT:    [[CONV93:%.*]] = trunc i32 [[COND92]] to i16
56353 // SIMD-ONLY0-NEXT:    store i16 [[CONV93]], ptr [[SX]], align 2
56354 // SIMD-ONLY0-NEXT:    [[TMP45:%.*]] = load i16, ptr [[SX]], align 2
56355 // SIMD-ONLY0-NEXT:    [[CONV94:%.*]] = sext i16 [[TMP45]] to i32
56356 // SIMD-ONLY0-NEXT:    [[TMP46:%.*]] = load i16, ptr [[SE]], align 2
56357 // SIMD-ONLY0-NEXT:    [[CONV95:%.*]] = sext i16 [[TMP46]] to i32
56358 // SIMD-ONLY0-NEXT:    [[CMP96:%.*]] = icmp sgt i32 [[CONV94]], [[CONV95]]
56359 // SIMD-ONLY0-NEXT:    br i1 [[CMP96]], label [[COND_TRUE98:%.*]], label [[COND_FALSE100:%.*]]
56360 // SIMD-ONLY0:       cond.true98:
56361 // SIMD-ONLY0-NEXT:    [[TMP47:%.*]] = load i16, ptr [[SE]], align 2
56362 // SIMD-ONLY0-NEXT:    [[CONV99:%.*]] = sext i16 [[TMP47]] to i32
56363 // SIMD-ONLY0-NEXT:    br label [[COND_END102:%.*]]
56364 // SIMD-ONLY0:       cond.false100:
56365 // SIMD-ONLY0-NEXT:    [[TMP48:%.*]] = load i16, ptr [[SX]], align 2
56366 // SIMD-ONLY0-NEXT:    [[CONV101:%.*]] = sext i16 [[TMP48]] to i32
56367 // SIMD-ONLY0-NEXT:    br label [[COND_END102]]
56368 // SIMD-ONLY0:       cond.end102:
56369 // SIMD-ONLY0-NEXT:    [[COND103:%.*]] = phi i32 [ [[CONV99]], [[COND_TRUE98]] ], [ [[CONV101]], [[COND_FALSE100]] ]
56370 // SIMD-ONLY0-NEXT:    [[CONV104:%.*]] = trunc i32 [[COND103]] to i16
56371 // SIMD-ONLY0-NEXT:    store i16 [[CONV104]], ptr [[SX]], align 2
56372 // SIMD-ONLY0-NEXT:    [[TMP49:%.*]] = load i16, ptr [[SX]], align 2
56373 // SIMD-ONLY0-NEXT:    store i16 [[TMP49]], ptr [[SV]], align 2
56374 // SIMD-ONLY0-NEXT:    [[TMP50:%.*]] = load i16, ptr [[SX]], align 2
56375 // SIMD-ONLY0-NEXT:    [[CONV105:%.*]] = sext i16 [[TMP50]] to i32
56376 // SIMD-ONLY0-NEXT:    [[TMP51:%.*]] = load i16, ptr [[SE]], align 2
56377 // SIMD-ONLY0-NEXT:    [[CONV106:%.*]] = sext i16 [[TMP51]] to i32
56378 // SIMD-ONLY0-NEXT:    [[CMP107:%.*]] = icmp slt i32 [[CONV105]], [[CONV106]]
56379 // SIMD-ONLY0-NEXT:    br i1 [[CMP107]], label [[COND_TRUE109:%.*]], label [[COND_FALSE111:%.*]]
56380 // SIMD-ONLY0:       cond.true109:
56381 // SIMD-ONLY0-NEXT:    [[TMP52:%.*]] = load i16, ptr [[SE]], align 2
56382 // SIMD-ONLY0-NEXT:    [[CONV110:%.*]] = sext i16 [[TMP52]] to i32
56383 // SIMD-ONLY0-NEXT:    br label [[COND_END113:%.*]]
56384 // SIMD-ONLY0:       cond.false111:
56385 // SIMD-ONLY0-NEXT:    [[TMP53:%.*]] = load i16, ptr [[SX]], align 2
56386 // SIMD-ONLY0-NEXT:    [[CONV112:%.*]] = sext i16 [[TMP53]] to i32
56387 // SIMD-ONLY0-NEXT:    br label [[COND_END113]]
56388 // SIMD-ONLY0:       cond.end113:
56389 // SIMD-ONLY0-NEXT:    [[COND114:%.*]] = phi i32 [ [[CONV110]], [[COND_TRUE109]] ], [ [[CONV112]], [[COND_FALSE111]] ]
56390 // SIMD-ONLY0-NEXT:    [[CONV115:%.*]] = trunc i32 [[COND114]] to i16
56391 // SIMD-ONLY0-NEXT:    store i16 [[CONV115]], ptr [[SX]], align 2
56392 // SIMD-ONLY0-NEXT:    [[TMP54:%.*]] = load i16, ptr [[SX]], align 2
56393 // SIMD-ONLY0-NEXT:    store i16 [[TMP54]], ptr [[SV]], align 2
56394 // SIMD-ONLY0-NEXT:    [[TMP55:%.*]] = load i16, ptr [[SX]], align 2
56395 // SIMD-ONLY0-NEXT:    [[CONV116:%.*]] = sext i16 [[TMP55]] to i32
56396 // SIMD-ONLY0-NEXT:    [[TMP56:%.*]] = load i16, ptr [[SE]], align 2
56397 // SIMD-ONLY0-NEXT:    [[CONV117:%.*]] = sext i16 [[TMP56]] to i32
56398 // SIMD-ONLY0-NEXT:    [[CMP118:%.*]] = icmp eq i32 [[CONV116]], [[CONV117]]
56399 // SIMD-ONLY0-NEXT:    br i1 [[CMP118]], label [[COND_TRUE120:%.*]], label [[COND_FALSE122:%.*]]
56400 // SIMD-ONLY0:       cond.true120:
56401 // SIMD-ONLY0-NEXT:    [[TMP57:%.*]] = load i16, ptr [[SD]], align 2
56402 // SIMD-ONLY0-NEXT:    [[CONV121:%.*]] = sext i16 [[TMP57]] to i32
56403 // SIMD-ONLY0-NEXT:    br label [[COND_END124:%.*]]
56404 // SIMD-ONLY0:       cond.false122:
56405 // SIMD-ONLY0-NEXT:    [[TMP58:%.*]] = load i16, ptr [[SX]], align 2
56406 // SIMD-ONLY0-NEXT:    [[CONV123:%.*]] = sext i16 [[TMP58]] to i32
56407 // SIMD-ONLY0-NEXT:    br label [[COND_END124]]
56408 // SIMD-ONLY0:       cond.end124:
56409 // SIMD-ONLY0-NEXT:    [[COND125:%.*]] = phi i32 [ [[CONV121]], [[COND_TRUE120]] ], [ [[CONV123]], [[COND_FALSE122]] ]
56410 // SIMD-ONLY0-NEXT:    [[CONV126:%.*]] = trunc i32 [[COND125]] to i16
56411 // SIMD-ONLY0-NEXT:    store i16 [[CONV126]], ptr [[SX]], align 2
56412 // SIMD-ONLY0-NEXT:    [[TMP59:%.*]] = load i16, ptr [[SX]], align 2
56413 // SIMD-ONLY0-NEXT:    store i16 [[TMP59]], ptr [[SV]], align 2
56414 // SIMD-ONLY0-NEXT:    [[TMP60:%.*]] = load i16, ptr [[SX]], align 2
56415 // SIMD-ONLY0-NEXT:    store i16 [[TMP60]], ptr [[SV]], align 2
56416 // SIMD-ONLY0-NEXT:    [[TMP61:%.*]] = load i16, ptr [[SX]], align 2
56417 // SIMD-ONLY0-NEXT:    [[CONV127:%.*]] = sext i16 [[TMP61]] to i32
56418 // SIMD-ONLY0-NEXT:    [[TMP62:%.*]] = load i16, ptr [[SE]], align 2
56419 // SIMD-ONLY0-NEXT:    [[CONV128:%.*]] = sext i16 [[TMP62]] to i32
56420 // SIMD-ONLY0-NEXT:    [[CMP129:%.*]] = icmp sgt i32 [[CONV127]], [[CONV128]]
56421 // SIMD-ONLY0-NEXT:    br i1 [[CMP129]], label [[COND_TRUE131:%.*]], label [[COND_FALSE133:%.*]]
56422 // SIMD-ONLY0:       cond.true131:
56423 // SIMD-ONLY0-NEXT:    [[TMP63:%.*]] = load i16, ptr [[SE]], align 2
56424 // SIMD-ONLY0-NEXT:    [[CONV132:%.*]] = sext i16 [[TMP63]] to i32
56425 // SIMD-ONLY0-NEXT:    br label [[COND_END135:%.*]]
56426 // SIMD-ONLY0:       cond.false133:
56427 // SIMD-ONLY0-NEXT:    [[TMP64:%.*]] = load i16, ptr [[SX]], align 2
56428 // SIMD-ONLY0-NEXT:    [[CONV134:%.*]] = sext i16 [[TMP64]] to i32
56429 // SIMD-ONLY0-NEXT:    br label [[COND_END135]]
56430 // SIMD-ONLY0:       cond.end135:
56431 // SIMD-ONLY0-NEXT:    [[COND136:%.*]] = phi i32 [ [[CONV132]], [[COND_TRUE131]] ], [ [[CONV134]], [[COND_FALSE133]] ]
56432 // SIMD-ONLY0-NEXT:    [[CONV137:%.*]] = trunc i32 [[COND136]] to i16
56433 // SIMD-ONLY0-NEXT:    store i16 [[CONV137]], ptr [[SX]], align 2
56434 // SIMD-ONLY0-NEXT:    [[TMP65:%.*]] = load i16, ptr [[SX]], align 2
56435 // SIMD-ONLY0-NEXT:    store i16 [[TMP65]], ptr [[SV]], align 2
56436 // SIMD-ONLY0-NEXT:    [[TMP66:%.*]] = load i16, ptr [[SX]], align 2
56437 // SIMD-ONLY0-NEXT:    [[CONV138:%.*]] = sext i16 [[TMP66]] to i32
56438 // SIMD-ONLY0-NEXT:    [[TMP67:%.*]] = load i16, ptr [[SE]], align 2
56439 // SIMD-ONLY0-NEXT:    [[CONV139:%.*]] = sext i16 [[TMP67]] to i32
56440 // SIMD-ONLY0-NEXT:    [[CMP140:%.*]] = icmp slt i32 [[CONV138]], [[CONV139]]
56441 // SIMD-ONLY0-NEXT:    br i1 [[CMP140]], label [[COND_TRUE142:%.*]], label [[COND_FALSE144:%.*]]
56442 // SIMD-ONLY0:       cond.true142:
56443 // SIMD-ONLY0-NEXT:    [[TMP68:%.*]] = load i16, ptr [[SE]], align 2
56444 // SIMD-ONLY0-NEXT:    [[CONV143:%.*]] = sext i16 [[TMP68]] to i32
56445 // SIMD-ONLY0-NEXT:    br label [[COND_END146:%.*]]
56446 // SIMD-ONLY0:       cond.false144:
56447 // SIMD-ONLY0-NEXT:    [[TMP69:%.*]] = load i16, ptr [[SX]], align 2
56448 // SIMD-ONLY0-NEXT:    [[CONV145:%.*]] = sext i16 [[TMP69]] to i32
56449 // SIMD-ONLY0-NEXT:    br label [[COND_END146]]
56450 // SIMD-ONLY0:       cond.end146:
56451 // SIMD-ONLY0-NEXT:    [[COND147:%.*]] = phi i32 [ [[CONV143]], [[COND_TRUE142]] ], [ [[CONV145]], [[COND_FALSE144]] ]
56452 // SIMD-ONLY0-NEXT:    [[CONV148:%.*]] = trunc i32 [[COND147]] to i16
56453 // SIMD-ONLY0-NEXT:    store i16 [[CONV148]], ptr [[SX]], align 2
56454 // SIMD-ONLY0-NEXT:    [[TMP70:%.*]] = load i16, ptr [[SX]], align 2
56455 // SIMD-ONLY0-NEXT:    store i16 [[TMP70]], ptr [[SV]], align 2
56456 // SIMD-ONLY0-NEXT:    [[TMP71:%.*]] = load i16, ptr [[SX]], align 2
56457 // SIMD-ONLY0-NEXT:    [[CONV149:%.*]] = sext i16 [[TMP71]] to i32
56458 // SIMD-ONLY0-NEXT:    [[TMP72:%.*]] = load i16, ptr [[SE]], align 2
56459 // SIMD-ONLY0-NEXT:    [[CONV150:%.*]] = sext i16 [[TMP72]] to i32
56460 // SIMD-ONLY0-NEXT:    [[CMP151:%.*]] = icmp eq i32 [[CONV149]], [[CONV150]]
56461 // SIMD-ONLY0-NEXT:    br i1 [[CMP151]], label [[COND_TRUE153:%.*]], label [[COND_FALSE155:%.*]]
56462 // SIMD-ONLY0:       cond.true153:
56463 // SIMD-ONLY0-NEXT:    [[TMP73:%.*]] = load i16, ptr [[SD]], align 2
56464 // SIMD-ONLY0-NEXT:    [[CONV154:%.*]] = sext i16 [[TMP73]] to i32
56465 // SIMD-ONLY0-NEXT:    br label [[COND_END157:%.*]]
56466 // SIMD-ONLY0:       cond.false155:
56467 // SIMD-ONLY0-NEXT:    [[TMP74:%.*]] = load i16, ptr [[SX]], align 2
56468 // SIMD-ONLY0-NEXT:    [[CONV156:%.*]] = sext i16 [[TMP74]] to i32
56469 // SIMD-ONLY0-NEXT:    br label [[COND_END157]]
56470 // SIMD-ONLY0:       cond.end157:
56471 // SIMD-ONLY0-NEXT:    [[COND158:%.*]] = phi i32 [ [[CONV154]], [[COND_TRUE153]] ], [ [[CONV156]], [[COND_FALSE155]] ]
56472 // SIMD-ONLY0-NEXT:    [[CONV159:%.*]] = trunc i32 [[COND158]] to i16
56473 // SIMD-ONLY0-NEXT:    store i16 [[CONV159]], ptr [[SX]], align 2
56474 // SIMD-ONLY0-NEXT:    [[TMP75:%.*]] = load i16, ptr [[SX]], align 2
56475 // SIMD-ONLY0-NEXT:    [[CONV160:%.*]] = sext i16 [[TMP75]] to i32
56476 // SIMD-ONLY0-NEXT:    [[TMP76:%.*]] = load i16, ptr [[SE]], align 2
56477 // SIMD-ONLY0-NEXT:    [[CONV161:%.*]] = sext i16 [[TMP76]] to i32
56478 // SIMD-ONLY0-NEXT:    [[CMP162:%.*]] = icmp sgt i32 [[CONV160]], [[CONV161]]
56479 // SIMD-ONLY0-NEXT:    br i1 [[CMP162]], label [[COND_TRUE164:%.*]], label [[COND_FALSE166:%.*]]
56480 // SIMD-ONLY0:       cond.true164:
56481 // SIMD-ONLY0-NEXT:    [[TMP77:%.*]] = load i16, ptr [[SE]], align 2
56482 // SIMD-ONLY0-NEXT:    [[CONV165:%.*]] = sext i16 [[TMP77]] to i32
56483 // SIMD-ONLY0-NEXT:    br label [[COND_END168:%.*]]
56484 // SIMD-ONLY0:       cond.false166:
56485 // SIMD-ONLY0-NEXT:    [[TMP78:%.*]] = load i16, ptr [[SX]], align 2
56486 // SIMD-ONLY0-NEXT:    [[CONV167:%.*]] = sext i16 [[TMP78]] to i32
56487 // SIMD-ONLY0-NEXT:    br label [[COND_END168]]
56488 // SIMD-ONLY0:       cond.end168:
56489 // SIMD-ONLY0-NEXT:    [[COND169:%.*]] = phi i32 [ [[CONV165]], [[COND_TRUE164]] ], [ [[CONV167]], [[COND_FALSE166]] ]
56490 // SIMD-ONLY0-NEXT:    [[CONV170:%.*]] = trunc i32 [[COND169]] to i16
56491 // SIMD-ONLY0-NEXT:    store i16 [[CONV170]], ptr [[SX]], align 2
56492 // SIMD-ONLY0-NEXT:    [[TMP79:%.*]] = load i16, ptr [[SX]], align 2
56493 // SIMD-ONLY0-NEXT:    store i16 [[TMP79]], ptr [[SV]], align 2
56494 // SIMD-ONLY0-NEXT:    [[TMP80:%.*]] = load i16, ptr [[SX]], align 2
56495 // SIMD-ONLY0-NEXT:    [[CONV171:%.*]] = sext i16 [[TMP80]] to i32
56496 // SIMD-ONLY0-NEXT:    [[TMP81:%.*]] = load i16, ptr [[SE]], align 2
56497 // SIMD-ONLY0-NEXT:    [[CONV172:%.*]] = sext i16 [[TMP81]] to i32
56498 // SIMD-ONLY0-NEXT:    [[CMP173:%.*]] = icmp slt i32 [[CONV171]], [[CONV172]]
56499 // SIMD-ONLY0-NEXT:    br i1 [[CMP173]], label [[COND_TRUE175:%.*]], label [[COND_FALSE177:%.*]]
56500 // SIMD-ONLY0:       cond.true175:
56501 // SIMD-ONLY0-NEXT:    [[TMP82:%.*]] = load i16, ptr [[SE]], align 2
56502 // SIMD-ONLY0-NEXT:    [[CONV176:%.*]] = sext i16 [[TMP82]] to i32
56503 // SIMD-ONLY0-NEXT:    br label [[COND_END179:%.*]]
56504 // SIMD-ONLY0:       cond.false177:
56505 // SIMD-ONLY0-NEXT:    [[TMP83:%.*]] = load i16, ptr [[SX]], align 2
56506 // SIMD-ONLY0-NEXT:    [[CONV178:%.*]] = sext i16 [[TMP83]] to i32
56507 // SIMD-ONLY0-NEXT:    br label [[COND_END179]]
56508 // SIMD-ONLY0:       cond.end179:
56509 // SIMD-ONLY0-NEXT:    [[COND180:%.*]] = phi i32 [ [[CONV176]], [[COND_TRUE175]] ], [ [[CONV178]], [[COND_FALSE177]] ]
56510 // SIMD-ONLY0-NEXT:    [[CONV181:%.*]] = trunc i32 [[COND180]] to i16
56511 // SIMD-ONLY0-NEXT:    store i16 [[CONV181]], ptr [[SX]], align 2
56512 // SIMD-ONLY0-NEXT:    [[TMP84:%.*]] = load i16, ptr [[SX]], align 2
56513 // SIMD-ONLY0-NEXT:    store i16 [[TMP84]], ptr [[SV]], align 2
56514 // SIMD-ONLY0-NEXT:    [[TMP85:%.*]] = load i16, ptr [[SX]], align 2
56515 // SIMD-ONLY0-NEXT:    [[CONV182:%.*]] = sext i16 [[TMP85]] to i32
56516 // SIMD-ONLY0-NEXT:    [[TMP86:%.*]] = load i16, ptr [[SE]], align 2
56517 // SIMD-ONLY0-NEXT:    [[CONV183:%.*]] = sext i16 [[TMP86]] to i32
56518 // SIMD-ONLY0-NEXT:    [[CMP184:%.*]] = icmp eq i32 [[CONV182]], [[CONV183]]
56519 // SIMD-ONLY0-NEXT:    br i1 [[CMP184]], label [[COND_TRUE186:%.*]], label [[COND_FALSE188:%.*]]
56520 // SIMD-ONLY0:       cond.true186:
56521 // SIMD-ONLY0-NEXT:    [[TMP87:%.*]] = load i16, ptr [[SD]], align 2
56522 // SIMD-ONLY0-NEXT:    [[CONV187:%.*]] = sext i16 [[TMP87]] to i32
56523 // SIMD-ONLY0-NEXT:    br label [[COND_END190:%.*]]
56524 // SIMD-ONLY0:       cond.false188:
56525 // SIMD-ONLY0-NEXT:    [[TMP88:%.*]] = load i16, ptr [[SX]], align 2
56526 // SIMD-ONLY0-NEXT:    [[CONV189:%.*]] = sext i16 [[TMP88]] to i32
56527 // SIMD-ONLY0-NEXT:    br label [[COND_END190]]
56528 // SIMD-ONLY0:       cond.end190:
56529 // SIMD-ONLY0-NEXT:    [[COND191:%.*]] = phi i32 [ [[CONV187]], [[COND_TRUE186]] ], [ [[CONV189]], [[COND_FALSE188]] ]
56530 // SIMD-ONLY0-NEXT:    [[CONV192:%.*]] = trunc i32 [[COND191]] to i16
56531 // SIMD-ONLY0-NEXT:    store i16 [[CONV192]], ptr [[SX]], align 2
56532 // SIMD-ONLY0-NEXT:    [[TMP89:%.*]] = load i16, ptr [[SX]], align 2
56533 // SIMD-ONLY0-NEXT:    store i16 [[TMP89]], ptr [[SV]], align 2
56534 // SIMD-ONLY0-NEXT:    [[TMP90:%.*]] = load i16, ptr [[SX]], align 2
56535 // SIMD-ONLY0-NEXT:    store i16 [[TMP90]], ptr [[SV]], align 2
56536 // SIMD-ONLY0-NEXT:    [[TMP91:%.*]] = load i16, ptr [[SX]], align 2
56537 // SIMD-ONLY0-NEXT:    [[CONV193:%.*]] = sext i16 [[TMP91]] to i32
56538 // SIMD-ONLY0-NEXT:    [[TMP92:%.*]] = load i16, ptr [[SE]], align 2
56539 // SIMD-ONLY0-NEXT:    [[CONV194:%.*]] = sext i16 [[TMP92]] to i32
56540 // SIMD-ONLY0-NEXT:    [[CMP195:%.*]] = icmp sgt i32 [[CONV193]], [[CONV194]]
56541 // SIMD-ONLY0-NEXT:    br i1 [[CMP195]], label [[COND_TRUE197:%.*]], label [[COND_FALSE199:%.*]]
56542 // SIMD-ONLY0:       cond.true197:
56543 // SIMD-ONLY0-NEXT:    [[TMP93:%.*]] = load i16, ptr [[SE]], align 2
56544 // SIMD-ONLY0-NEXT:    [[CONV198:%.*]] = sext i16 [[TMP93]] to i32
56545 // SIMD-ONLY0-NEXT:    br label [[COND_END201:%.*]]
56546 // SIMD-ONLY0:       cond.false199:
56547 // SIMD-ONLY0-NEXT:    [[TMP94:%.*]] = load i16, ptr [[SX]], align 2
56548 // SIMD-ONLY0-NEXT:    [[CONV200:%.*]] = sext i16 [[TMP94]] to i32
56549 // SIMD-ONLY0-NEXT:    br label [[COND_END201]]
56550 // SIMD-ONLY0:       cond.end201:
56551 // SIMD-ONLY0-NEXT:    [[COND202:%.*]] = phi i32 [ [[CONV198]], [[COND_TRUE197]] ], [ [[CONV200]], [[COND_FALSE199]] ]
56552 // SIMD-ONLY0-NEXT:    [[CONV203:%.*]] = trunc i32 [[COND202]] to i16
56553 // SIMD-ONLY0-NEXT:    store i16 [[CONV203]], ptr [[SX]], align 2
56554 // SIMD-ONLY0-NEXT:    [[TMP95:%.*]] = load i16, ptr [[SX]], align 2
56555 // SIMD-ONLY0-NEXT:    store i16 [[TMP95]], ptr [[SV]], align 2
56556 // SIMD-ONLY0-NEXT:    [[TMP96:%.*]] = load i16, ptr [[SX]], align 2
56557 // SIMD-ONLY0-NEXT:    [[CONV204:%.*]] = sext i16 [[TMP96]] to i32
56558 // SIMD-ONLY0-NEXT:    [[TMP97:%.*]] = load i16, ptr [[SE]], align 2
56559 // SIMD-ONLY0-NEXT:    [[CONV205:%.*]] = sext i16 [[TMP97]] to i32
56560 // SIMD-ONLY0-NEXT:    [[CMP206:%.*]] = icmp slt i32 [[CONV204]], [[CONV205]]
56561 // SIMD-ONLY0-NEXT:    br i1 [[CMP206]], label [[COND_TRUE208:%.*]], label [[COND_FALSE210:%.*]]
56562 // SIMD-ONLY0:       cond.true208:
56563 // SIMD-ONLY0-NEXT:    [[TMP98:%.*]] = load i16, ptr [[SE]], align 2
56564 // SIMD-ONLY0-NEXT:    [[CONV209:%.*]] = sext i16 [[TMP98]] to i32
56565 // SIMD-ONLY0-NEXT:    br label [[COND_END212:%.*]]
56566 // SIMD-ONLY0:       cond.false210:
56567 // SIMD-ONLY0-NEXT:    [[TMP99:%.*]] = load i16, ptr [[SX]], align 2
56568 // SIMD-ONLY0-NEXT:    [[CONV211:%.*]] = sext i16 [[TMP99]] to i32
56569 // SIMD-ONLY0-NEXT:    br label [[COND_END212]]
56570 // SIMD-ONLY0:       cond.end212:
56571 // SIMD-ONLY0-NEXT:    [[COND213:%.*]] = phi i32 [ [[CONV209]], [[COND_TRUE208]] ], [ [[CONV211]], [[COND_FALSE210]] ]
56572 // SIMD-ONLY0-NEXT:    [[CONV214:%.*]] = trunc i32 [[COND213]] to i16
56573 // SIMD-ONLY0-NEXT:    store i16 [[CONV214]], ptr [[SX]], align 2
56574 // SIMD-ONLY0-NEXT:    [[TMP100:%.*]] = load i16, ptr [[SX]], align 2
56575 // SIMD-ONLY0-NEXT:    store i16 [[TMP100]], ptr [[SV]], align 2
56576 // SIMD-ONLY0-NEXT:    [[TMP101:%.*]] = load i16, ptr [[SX]], align 2
56577 // SIMD-ONLY0-NEXT:    [[CONV215:%.*]] = sext i16 [[TMP101]] to i32
56578 // SIMD-ONLY0-NEXT:    [[TMP102:%.*]] = load i16, ptr [[SE]], align 2
56579 // SIMD-ONLY0-NEXT:    [[CONV216:%.*]] = sext i16 [[TMP102]] to i32
56580 // SIMD-ONLY0-NEXT:    [[CMP217:%.*]] = icmp eq i32 [[CONV215]], [[CONV216]]
56581 // SIMD-ONLY0-NEXT:    br i1 [[CMP217]], label [[COND_TRUE219:%.*]], label [[COND_FALSE221:%.*]]
56582 // SIMD-ONLY0:       cond.true219:
56583 // SIMD-ONLY0-NEXT:    [[TMP103:%.*]] = load i16, ptr [[SD]], align 2
56584 // SIMD-ONLY0-NEXT:    [[CONV220:%.*]] = sext i16 [[TMP103]] to i32
56585 // SIMD-ONLY0-NEXT:    br label [[COND_END223:%.*]]
56586 // SIMD-ONLY0:       cond.false221:
56587 // SIMD-ONLY0-NEXT:    [[TMP104:%.*]] = load i16, ptr [[SX]], align 2
56588 // SIMD-ONLY0-NEXT:    [[CONV222:%.*]] = sext i16 [[TMP104]] to i32
56589 // SIMD-ONLY0-NEXT:    br label [[COND_END223]]
56590 // SIMD-ONLY0:       cond.end223:
56591 // SIMD-ONLY0-NEXT:    [[COND224:%.*]] = phi i32 [ [[CONV220]], [[COND_TRUE219]] ], [ [[CONV222]], [[COND_FALSE221]] ]
56592 // SIMD-ONLY0-NEXT:    [[CONV225:%.*]] = trunc i32 [[COND224]] to i16
56593 // SIMD-ONLY0-NEXT:    store i16 [[CONV225]], ptr [[SX]], align 2
56594 // SIMD-ONLY0-NEXT:    [[TMP105:%.*]] = load i16, ptr [[SX]], align 2
56595 // SIMD-ONLY0-NEXT:    [[CONV226:%.*]] = sext i16 [[TMP105]] to i32
56596 // SIMD-ONLY0-NEXT:    [[TMP106:%.*]] = load i16, ptr [[SE]], align 2
56597 // SIMD-ONLY0-NEXT:    [[CONV227:%.*]] = sext i16 [[TMP106]] to i32
56598 // SIMD-ONLY0-NEXT:    [[CMP228:%.*]] = icmp sgt i32 [[CONV226]], [[CONV227]]
56599 // SIMD-ONLY0-NEXT:    br i1 [[CMP228]], label [[COND_TRUE230:%.*]], label [[COND_FALSE232:%.*]]
56600 // SIMD-ONLY0:       cond.true230:
56601 // SIMD-ONLY0-NEXT:    [[TMP107:%.*]] = load i16, ptr [[SE]], align 2
56602 // SIMD-ONLY0-NEXT:    [[CONV231:%.*]] = sext i16 [[TMP107]] to i32
56603 // SIMD-ONLY0-NEXT:    br label [[COND_END234:%.*]]
56604 // SIMD-ONLY0:       cond.false232:
56605 // SIMD-ONLY0-NEXT:    [[TMP108:%.*]] = load i16, ptr [[SX]], align 2
56606 // SIMD-ONLY0-NEXT:    [[CONV233:%.*]] = sext i16 [[TMP108]] to i32
56607 // SIMD-ONLY0-NEXT:    br label [[COND_END234]]
56608 // SIMD-ONLY0:       cond.end234:
56609 // SIMD-ONLY0-NEXT:    [[COND235:%.*]] = phi i32 [ [[CONV231]], [[COND_TRUE230]] ], [ [[CONV233]], [[COND_FALSE232]] ]
56610 // SIMD-ONLY0-NEXT:    [[CONV236:%.*]] = trunc i32 [[COND235]] to i16
56611 // SIMD-ONLY0-NEXT:    store i16 [[CONV236]], ptr [[SX]], align 2
56612 // SIMD-ONLY0-NEXT:    [[TMP109:%.*]] = load i16, ptr [[SX]], align 2
56613 // SIMD-ONLY0-NEXT:    store i16 [[TMP109]], ptr [[SV]], align 2
56614 // SIMD-ONLY0-NEXT:    [[TMP110:%.*]] = load i16, ptr [[SX]], align 2
56615 // SIMD-ONLY0-NEXT:    [[CONV237:%.*]] = sext i16 [[TMP110]] to i32
56616 // SIMD-ONLY0-NEXT:    [[TMP111:%.*]] = load i16, ptr [[SE]], align 2
56617 // SIMD-ONLY0-NEXT:    [[CONV238:%.*]] = sext i16 [[TMP111]] to i32
56618 // SIMD-ONLY0-NEXT:    [[CMP239:%.*]] = icmp slt i32 [[CONV237]], [[CONV238]]
56619 // SIMD-ONLY0-NEXT:    br i1 [[CMP239]], label [[COND_TRUE241:%.*]], label [[COND_FALSE243:%.*]]
56620 // SIMD-ONLY0:       cond.true241:
56621 // SIMD-ONLY0-NEXT:    [[TMP112:%.*]] = load i16, ptr [[SE]], align 2
56622 // SIMD-ONLY0-NEXT:    [[CONV242:%.*]] = sext i16 [[TMP112]] to i32
56623 // SIMD-ONLY0-NEXT:    br label [[COND_END245:%.*]]
56624 // SIMD-ONLY0:       cond.false243:
56625 // SIMD-ONLY0-NEXT:    [[TMP113:%.*]] = load i16, ptr [[SX]], align 2
56626 // SIMD-ONLY0-NEXT:    [[CONV244:%.*]] = sext i16 [[TMP113]] to i32
56627 // SIMD-ONLY0-NEXT:    br label [[COND_END245]]
56628 // SIMD-ONLY0:       cond.end245:
56629 // SIMD-ONLY0-NEXT:    [[COND246:%.*]] = phi i32 [ [[CONV242]], [[COND_TRUE241]] ], [ [[CONV244]], [[COND_FALSE243]] ]
56630 // SIMD-ONLY0-NEXT:    [[CONV247:%.*]] = trunc i32 [[COND246]] to i16
56631 // SIMD-ONLY0-NEXT:    store i16 [[CONV247]], ptr [[SX]], align 2
56632 // SIMD-ONLY0-NEXT:    [[TMP114:%.*]] = load i16, ptr [[SX]], align 2
56633 // SIMD-ONLY0-NEXT:    store i16 [[TMP114]], ptr [[SV]], align 2
56634 // SIMD-ONLY0-NEXT:    [[TMP115:%.*]] = load i16, ptr [[SX]], align 2
56635 // SIMD-ONLY0-NEXT:    [[CONV248:%.*]] = sext i16 [[TMP115]] to i32
56636 // SIMD-ONLY0-NEXT:    [[TMP116:%.*]] = load i16, ptr [[SE]], align 2
56637 // SIMD-ONLY0-NEXT:    [[CONV249:%.*]] = sext i16 [[TMP116]] to i32
56638 // SIMD-ONLY0-NEXT:    [[CMP250:%.*]] = icmp eq i32 [[CONV248]], [[CONV249]]
56639 // SIMD-ONLY0-NEXT:    br i1 [[CMP250]], label [[COND_TRUE252:%.*]], label [[COND_FALSE254:%.*]]
56640 // SIMD-ONLY0:       cond.true252:
56641 // SIMD-ONLY0-NEXT:    [[TMP117:%.*]] = load i16, ptr [[SD]], align 2
56642 // SIMD-ONLY0-NEXT:    [[CONV253:%.*]] = sext i16 [[TMP117]] to i32
56643 // SIMD-ONLY0-NEXT:    br label [[COND_END256:%.*]]
56644 // SIMD-ONLY0:       cond.false254:
56645 // SIMD-ONLY0-NEXT:    [[TMP118:%.*]] = load i16, ptr [[SX]], align 2
56646 // SIMD-ONLY0-NEXT:    [[CONV255:%.*]] = sext i16 [[TMP118]] to i32
56647 // SIMD-ONLY0-NEXT:    br label [[COND_END256]]
56648 // SIMD-ONLY0:       cond.end256:
56649 // SIMD-ONLY0-NEXT:    [[COND257:%.*]] = phi i32 [ [[CONV253]], [[COND_TRUE252]] ], [ [[CONV255]], [[COND_FALSE254]] ]
56650 // SIMD-ONLY0-NEXT:    [[CONV258:%.*]] = trunc i32 [[COND257]] to i16
56651 // SIMD-ONLY0-NEXT:    store i16 [[CONV258]], ptr [[SX]], align 2
56652 // SIMD-ONLY0-NEXT:    [[TMP119:%.*]] = load i16, ptr [[SX]], align 2
56653 // SIMD-ONLY0-NEXT:    store i16 [[TMP119]], ptr [[SV]], align 2
56654 // SIMD-ONLY0-NEXT:    [[TMP120:%.*]] = load i16, ptr [[SX]], align 2
56655 // SIMD-ONLY0-NEXT:    store i16 [[TMP120]], ptr [[SV]], align 2
56656 // SIMD-ONLY0-NEXT:    [[TMP121:%.*]] = load i16, ptr [[SX]], align 2
56657 // SIMD-ONLY0-NEXT:    [[CONV259:%.*]] = sext i16 [[TMP121]] to i32
56658 // SIMD-ONLY0-NEXT:    [[TMP122:%.*]] = load i16, ptr [[SE]], align 2
56659 // SIMD-ONLY0-NEXT:    [[CONV260:%.*]] = sext i16 [[TMP122]] to i32
56660 // SIMD-ONLY0-NEXT:    [[CMP261:%.*]] = icmp sgt i32 [[CONV259]], [[CONV260]]
56661 // SIMD-ONLY0-NEXT:    br i1 [[CMP261]], label [[COND_TRUE263:%.*]], label [[COND_FALSE265:%.*]]
56662 // SIMD-ONLY0:       cond.true263:
56663 // SIMD-ONLY0-NEXT:    [[TMP123:%.*]] = load i16, ptr [[SE]], align 2
56664 // SIMD-ONLY0-NEXT:    [[CONV264:%.*]] = sext i16 [[TMP123]] to i32
56665 // SIMD-ONLY0-NEXT:    br label [[COND_END267:%.*]]
56666 // SIMD-ONLY0:       cond.false265:
56667 // SIMD-ONLY0-NEXT:    [[TMP124:%.*]] = load i16, ptr [[SX]], align 2
56668 // SIMD-ONLY0-NEXT:    [[CONV266:%.*]] = sext i16 [[TMP124]] to i32
56669 // SIMD-ONLY0-NEXT:    br label [[COND_END267]]
56670 // SIMD-ONLY0:       cond.end267:
56671 // SIMD-ONLY0-NEXT:    [[COND268:%.*]] = phi i32 [ [[CONV264]], [[COND_TRUE263]] ], [ [[CONV266]], [[COND_FALSE265]] ]
56672 // SIMD-ONLY0-NEXT:    [[CONV269:%.*]] = trunc i32 [[COND268]] to i16
56673 // SIMD-ONLY0-NEXT:    store i16 [[CONV269]], ptr [[SX]], align 2
56674 // SIMD-ONLY0-NEXT:    [[TMP125:%.*]] = load i16, ptr [[SX]], align 2
56675 // SIMD-ONLY0-NEXT:    store i16 [[TMP125]], ptr [[SV]], align 2
56676 // SIMD-ONLY0-NEXT:    [[TMP126:%.*]] = load i16, ptr [[SX]], align 2
56677 // SIMD-ONLY0-NEXT:    [[CONV270:%.*]] = sext i16 [[TMP126]] to i32
56678 // SIMD-ONLY0-NEXT:    [[TMP127:%.*]] = load i16, ptr [[SE]], align 2
56679 // SIMD-ONLY0-NEXT:    [[CONV271:%.*]] = sext i16 [[TMP127]] to i32
56680 // SIMD-ONLY0-NEXT:    [[CMP272:%.*]] = icmp slt i32 [[CONV270]], [[CONV271]]
56681 // SIMD-ONLY0-NEXT:    br i1 [[CMP272]], label [[COND_TRUE274:%.*]], label [[COND_FALSE276:%.*]]
56682 // SIMD-ONLY0:       cond.true274:
56683 // SIMD-ONLY0-NEXT:    [[TMP128:%.*]] = load i16, ptr [[SE]], align 2
56684 // SIMD-ONLY0-NEXT:    [[CONV275:%.*]] = sext i16 [[TMP128]] to i32
56685 // SIMD-ONLY0-NEXT:    br label [[COND_END278:%.*]]
56686 // SIMD-ONLY0:       cond.false276:
56687 // SIMD-ONLY0-NEXT:    [[TMP129:%.*]] = load i16, ptr [[SX]], align 2
56688 // SIMD-ONLY0-NEXT:    [[CONV277:%.*]] = sext i16 [[TMP129]] to i32
56689 // SIMD-ONLY0-NEXT:    br label [[COND_END278]]
56690 // SIMD-ONLY0:       cond.end278:
56691 // SIMD-ONLY0-NEXT:    [[COND279:%.*]] = phi i32 [ [[CONV275]], [[COND_TRUE274]] ], [ [[CONV277]], [[COND_FALSE276]] ]
56692 // SIMD-ONLY0-NEXT:    [[CONV280:%.*]] = trunc i32 [[COND279]] to i16
56693 // SIMD-ONLY0-NEXT:    store i16 [[CONV280]], ptr [[SX]], align 2
56694 // SIMD-ONLY0-NEXT:    [[TMP130:%.*]] = load i16, ptr [[SX]], align 2
56695 // SIMD-ONLY0-NEXT:    store i16 [[TMP130]], ptr [[SV]], align 2
56696 // SIMD-ONLY0-NEXT:    [[TMP131:%.*]] = load i16, ptr [[SX]], align 2
56697 // SIMD-ONLY0-NEXT:    [[CONV281:%.*]] = sext i16 [[TMP131]] to i32
56698 // SIMD-ONLY0-NEXT:    [[TMP132:%.*]] = load i16, ptr [[SE]], align 2
56699 // SIMD-ONLY0-NEXT:    [[CONV282:%.*]] = sext i16 [[TMP132]] to i32
56700 // SIMD-ONLY0-NEXT:    [[CMP283:%.*]] = icmp eq i32 [[CONV281]], [[CONV282]]
56701 // SIMD-ONLY0-NEXT:    br i1 [[CMP283]], label [[COND_TRUE285:%.*]], label [[COND_FALSE287:%.*]]
56702 // SIMD-ONLY0:       cond.true285:
56703 // SIMD-ONLY0-NEXT:    [[TMP133:%.*]] = load i16, ptr [[SD]], align 2
56704 // SIMD-ONLY0-NEXT:    [[CONV286:%.*]] = sext i16 [[TMP133]] to i32
56705 // SIMD-ONLY0-NEXT:    br label [[COND_END289:%.*]]
56706 // SIMD-ONLY0:       cond.false287:
56707 // SIMD-ONLY0-NEXT:    [[TMP134:%.*]] = load i16, ptr [[SX]], align 2
56708 // SIMD-ONLY0-NEXT:    [[CONV288:%.*]] = sext i16 [[TMP134]] to i32
56709 // SIMD-ONLY0-NEXT:    br label [[COND_END289]]
56710 // SIMD-ONLY0:       cond.end289:
56711 // SIMD-ONLY0-NEXT:    [[COND290:%.*]] = phi i32 [ [[CONV286]], [[COND_TRUE285]] ], [ [[CONV288]], [[COND_FALSE287]] ]
56712 // SIMD-ONLY0-NEXT:    [[CONV291:%.*]] = trunc i32 [[COND290]] to i16
56713 // SIMD-ONLY0-NEXT:    store i16 [[CONV291]], ptr [[SX]], align 2
56714 // SIMD-ONLY0-NEXT:    [[TMP135:%.*]] = load i16, ptr [[SX]], align 2
56715 // SIMD-ONLY0-NEXT:    [[CONV292:%.*]] = sext i16 [[TMP135]] to i32
56716 // SIMD-ONLY0-NEXT:    [[TMP136:%.*]] = load i16, ptr [[SE]], align 2
56717 // SIMD-ONLY0-NEXT:    [[CONV293:%.*]] = sext i16 [[TMP136]] to i32
56718 // SIMD-ONLY0-NEXT:    [[CMP294:%.*]] = icmp sgt i32 [[CONV292]], [[CONV293]]
56719 // SIMD-ONLY0-NEXT:    br i1 [[CMP294]], label [[COND_TRUE296:%.*]], label [[COND_FALSE298:%.*]]
56720 // SIMD-ONLY0:       cond.true296:
56721 // SIMD-ONLY0-NEXT:    [[TMP137:%.*]] = load i16, ptr [[SE]], align 2
56722 // SIMD-ONLY0-NEXT:    [[CONV297:%.*]] = sext i16 [[TMP137]] to i32
56723 // SIMD-ONLY0-NEXT:    br label [[COND_END300:%.*]]
56724 // SIMD-ONLY0:       cond.false298:
56725 // SIMD-ONLY0-NEXT:    [[TMP138:%.*]] = load i16, ptr [[SX]], align 2
56726 // SIMD-ONLY0-NEXT:    [[CONV299:%.*]] = sext i16 [[TMP138]] to i32
56727 // SIMD-ONLY0-NEXT:    br label [[COND_END300]]
56728 // SIMD-ONLY0:       cond.end300:
56729 // SIMD-ONLY0-NEXT:    [[COND301:%.*]] = phi i32 [ [[CONV297]], [[COND_TRUE296]] ], [ [[CONV299]], [[COND_FALSE298]] ]
56730 // SIMD-ONLY0-NEXT:    [[CONV302:%.*]] = trunc i32 [[COND301]] to i16
56731 // SIMD-ONLY0-NEXT:    store i16 [[CONV302]], ptr [[SX]], align 2
56732 // SIMD-ONLY0-NEXT:    [[TMP139:%.*]] = load i16, ptr [[SX]], align 2
56733 // SIMD-ONLY0-NEXT:    store i16 [[TMP139]], ptr [[SV]], align 2
56734 // SIMD-ONLY0-NEXT:    [[TMP140:%.*]] = load i16, ptr [[SX]], align 2
56735 // SIMD-ONLY0-NEXT:    [[CONV303:%.*]] = sext i16 [[TMP140]] to i32
56736 // SIMD-ONLY0-NEXT:    [[TMP141:%.*]] = load i16, ptr [[SE]], align 2
56737 // SIMD-ONLY0-NEXT:    [[CONV304:%.*]] = sext i16 [[TMP141]] to i32
56738 // SIMD-ONLY0-NEXT:    [[CMP305:%.*]] = icmp slt i32 [[CONV303]], [[CONV304]]
56739 // SIMD-ONLY0-NEXT:    br i1 [[CMP305]], label [[COND_TRUE307:%.*]], label [[COND_FALSE309:%.*]]
56740 // SIMD-ONLY0:       cond.true307:
56741 // SIMD-ONLY0-NEXT:    [[TMP142:%.*]] = load i16, ptr [[SE]], align 2
56742 // SIMD-ONLY0-NEXT:    [[CONV308:%.*]] = sext i16 [[TMP142]] to i32
56743 // SIMD-ONLY0-NEXT:    br label [[COND_END311:%.*]]
56744 // SIMD-ONLY0:       cond.false309:
56745 // SIMD-ONLY0-NEXT:    [[TMP143:%.*]] = load i16, ptr [[SX]], align 2
56746 // SIMD-ONLY0-NEXT:    [[CONV310:%.*]] = sext i16 [[TMP143]] to i32
56747 // SIMD-ONLY0-NEXT:    br label [[COND_END311]]
56748 // SIMD-ONLY0:       cond.end311:
56749 // SIMD-ONLY0-NEXT:    [[COND312:%.*]] = phi i32 [ [[CONV308]], [[COND_TRUE307]] ], [ [[CONV310]], [[COND_FALSE309]] ]
56750 // SIMD-ONLY0-NEXT:    [[CONV313:%.*]] = trunc i32 [[COND312]] to i16
56751 // SIMD-ONLY0-NEXT:    store i16 [[CONV313]], ptr [[SX]], align 2
56752 // SIMD-ONLY0-NEXT:    [[TMP144:%.*]] = load i16, ptr [[SX]], align 2
56753 // SIMD-ONLY0-NEXT:    store i16 [[TMP144]], ptr [[SV]], align 2
56754 // SIMD-ONLY0-NEXT:    [[TMP145:%.*]] = load i16, ptr [[SX]], align 2
56755 // SIMD-ONLY0-NEXT:    [[CONV314:%.*]] = sext i16 [[TMP145]] to i32
56756 // SIMD-ONLY0-NEXT:    [[TMP146:%.*]] = load i16, ptr [[SE]], align 2
56757 // SIMD-ONLY0-NEXT:    [[CONV315:%.*]] = sext i16 [[TMP146]] to i32
56758 // SIMD-ONLY0-NEXT:    [[CMP316:%.*]] = icmp eq i32 [[CONV314]], [[CONV315]]
56759 // SIMD-ONLY0-NEXT:    br i1 [[CMP316]], label [[COND_TRUE318:%.*]], label [[COND_FALSE320:%.*]]
56760 // SIMD-ONLY0:       cond.true318:
56761 // SIMD-ONLY0-NEXT:    [[TMP147:%.*]] = load i16, ptr [[SD]], align 2
56762 // SIMD-ONLY0-NEXT:    [[CONV319:%.*]] = sext i16 [[TMP147]] to i32
56763 // SIMD-ONLY0-NEXT:    br label [[COND_END322:%.*]]
56764 // SIMD-ONLY0:       cond.false320:
56765 // SIMD-ONLY0-NEXT:    [[TMP148:%.*]] = load i16, ptr [[SX]], align 2
56766 // SIMD-ONLY0-NEXT:    [[CONV321:%.*]] = sext i16 [[TMP148]] to i32
56767 // SIMD-ONLY0-NEXT:    br label [[COND_END322]]
56768 // SIMD-ONLY0:       cond.end322:
56769 // SIMD-ONLY0-NEXT:    [[COND323:%.*]] = phi i32 [ [[CONV319]], [[COND_TRUE318]] ], [ [[CONV321]], [[COND_FALSE320]] ]
56770 // SIMD-ONLY0-NEXT:    [[CONV324:%.*]] = trunc i32 [[COND323]] to i16
56771 // SIMD-ONLY0-NEXT:    store i16 [[CONV324]], ptr [[SX]], align 2
56772 // SIMD-ONLY0-NEXT:    [[TMP149:%.*]] = load i16, ptr [[SX]], align 2
56773 // SIMD-ONLY0-NEXT:    store i16 [[TMP149]], ptr [[SV]], align 2
56774 // SIMD-ONLY0-NEXT:    [[TMP150:%.*]] = load i16, ptr [[SX]], align 2
56775 // SIMD-ONLY0-NEXT:    store i16 [[TMP150]], ptr [[SV]], align 2
56776 // SIMD-ONLY0-NEXT:    [[TMP151:%.*]] = load i16, ptr [[SX]], align 2
56777 // SIMD-ONLY0-NEXT:    [[CONV325:%.*]] = sext i16 [[TMP151]] to i32
56778 // SIMD-ONLY0-NEXT:    [[TMP152:%.*]] = load i16, ptr [[SE]], align 2
56779 // SIMD-ONLY0-NEXT:    [[CONV326:%.*]] = sext i16 [[TMP152]] to i32
56780 // SIMD-ONLY0-NEXT:    [[CMP327:%.*]] = icmp sgt i32 [[CONV325]], [[CONV326]]
56781 // SIMD-ONLY0-NEXT:    br i1 [[CMP327]], label [[COND_TRUE329:%.*]], label [[COND_FALSE331:%.*]]
56782 // SIMD-ONLY0:       cond.true329:
56783 // SIMD-ONLY0-NEXT:    [[TMP153:%.*]] = load i16, ptr [[SE]], align 2
56784 // SIMD-ONLY0-NEXT:    [[CONV330:%.*]] = sext i16 [[TMP153]] to i32
56785 // SIMD-ONLY0-NEXT:    br label [[COND_END333:%.*]]
56786 // SIMD-ONLY0:       cond.false331:
56787 // SIMD-ONLY0-NEXT:    [[TMP154:%.*]] = load i16, ptr [[SX]], align 2
56788 // SIMD-ONLY0-NEXT:    [[CONV332:%.*]] = sext i16 [[TMP154]] to i32
56789 // SIMD-ONLY0-NEXT:    br label [[COND_END333]]
56790 // SIMD-ONLY0:       cond.end333:
56791 // SIMD-ONLY0-NEXT:    [[COND334:%.*]] = phi i32 [ [[CONV330]], [[COND_TRUE329]] ], [ [[CONV332]], [[COND_FALSE331]] ]
56792 // SIMD-ONLY0-NEXT:    [[CONV335:%.*]] = trunc i32 [[COND334]] to i16
56793 // SIMD-ONLY0-NEXT:    store i16 [[CONV335]], ptr [[SX]], align 2
56794 // SIMD-ONLY0-NEXT:    [[TMP155:%.*]] = load i16, ptr [[SX]], align 2
56795 // SIMD-ONLY0-NEXT:    store i16 [[TMP155]], ptr [[SV]], align 2
56796 // SIMD-ONLY0-NEXT:    [[TMP156:%.*]] = load i16, ptr [[SX]], align 2
56797 // SIMD-ONLY0-NEXT:    [[CONV336:%.*]] = sext i16 [[TMP156]] to i32
56798 // SIMD-ONLY0-NEXT:    [[TMP157:%.*]] = load i16, ptr [[SE]], align 2
56799 // SIMD-ONLY0-NEXT:    [[CONV337:%.*]] = sext i16 [[TMP157]] to i32
56800 // SIMD-ONLY0-NEXT:    [[CMP338:%.*]] = icmp slt i32 [[CONV336]], [[CONV337]]
56801 // SIMD-ONLY0-NEXT:    br i1 [[CMP338]], label [[COND_TRUE340:%.*]], label [[COND_FALSE342:%.*]]
56802 // SIMD-ONLY0:       cond.true340:
56803 // SIMD-ONLY0-NEXT:    [[TMP158:%.*]] = load i16, ptr [[SE]], align 2
56804 // SIMD-ONLY0-NEXT:    [[CONV341:%.*]] = sext i16 [[TMP158]] to i32
56805 // SIMD-ONLY0-NEXT:    br label [[COND_END344:%.*]]
56806 // SIMD-ONLY0:       cond.false342:
56807 // SIMD-ONLY0-NEXT:    [[TMP159:%.*]] = load i16, ptr [[SX]], align 2
56808 // SIMD-ONLY0-NEXT:    [[CONV343:%.*]] = sext i16 [[TMP159]] to i32
56809 // SIMD-ONLY0-NEXT:    br label [[COND_END344]]
56810 // SIMD-ONLY0:       cond.end344:
56811 // SIMD-ONLY0-NEXT:    [[COND345:%.*]] = phi i32 [ [[CONV341]], [[COND_TRUE340]] ], [ [[CONV343]], [[COND_FALSE342]] ]
56812 // SIMD-ONLY0-NEXT:    [[CONV346:%.*]] = trunc i32 [[COND345]] to i16
56813 // SIMD-ONLY0-NEXT:    store i16 [[CONV346]], ptr [[SX]], align 2
56814 // SIMD-ONLY0-NEXT:    [[TMP160:%.*]] = load i16, ptr [[SX]], align 2
56815 // SIMD-ONLY0-NEXT:    store i16 [[TMP160]], ptr [[SV]], align 2
56816 // SIMD-ONLY0-NEXT:    [[TMP161:%.*]] = load i16, ptr [[SX]], align 2
56817 // SIMD-ONLY0-NEXT:    [[CONV347:%.*]] = sext i16 [[TMP161]] to i32
56818 // SIMD-ONLY0-NEXT:    [[TMP162:%.*]] = load i16, ptr [[SE]], align 2
56819 // SIMD-ONLY0-NEXT:    [[CONV348:%.*]] = sext i16 [[TMP162]] to i32
56820 // SIMD-ONLY0-NEXT:    [[CMP349:%.*]] = icmp eq i32 [[CONV347]], [[CONV348]]
56821 // SIMD-ONLY0-NEXT:    br i1 [[CMP349]], label [[COND_TRUE351:%.*]], label [[COND_FALSE353:%.*]]
56822 // SIMD-ONLY0:       cond.true351:
56823 // SIMD-ONLY0-NEXT:    [[TMP163:%.*]] = load i16, ptr [[SD]], align 2
56824 // SIMD-ONLY0-NEXT:    [[CONV352:%.*]] = sext i16 [[TMP163]] to i32
56825 // SIMD-ONLY0-NEXT:    br label [[COND_END355:%.*]]
56826 // SIMD-ONLY0:       cond.false353:
56827 // SIMD-ONLY0-NEXT:    [[TMP164:%.*]] = load i16, ptr [[SX]], align 2
56828 // SIMD-ONLY0-NEXT:    [[CONV354:%.*]] = sext i16 [[TMP164]] to i32
56829 // SIMD-ONLY0-NEXT:    br label [[COND_END355]]
56830 // SIMD-ONLY0:       cond.end355:
56831 // SIMD-ONLY0-NEXT:    [[COND356:%.*]] = phi i32 [ [[CONV352]], [[COND_TRUE351]] ], [ [[CONV354]], [[COND_FALSE353]] ]
56832 // SIMD-ONLY0-NEXT:    [[CONV357:%.*]] = trunc i32 [[COND356]] to i16
56833 // SIMD-ONLY0-NEXT:    store i16 [[CONV357]], ptr [[SX]], align 2
56834 // SIMD-ONLY0-NEXT:    [[TMP165:%.*]] = load i16, ptr [[SX]], align 2
56835 // SIMD-ONLY0-NEXT:    [[CONV358:%.*]] = sext i16 [[TMP165]] to i32
56836 // SIMD-ONLY0-NEXT:    [[TMP166:%.*]] = load i16, ptr [[SE]], align 2
56837 // SIMD-ONLY0-NEXT:    [[CONV359:%.*]] = sext i16 [[TMP166]] to i32
56838 // SIMD-ONLY0-NEXT:    [[CMP360:%.*]] = icmp sgt i32 [[CONV358]], [[CONV359]]
56839 // SIMD-ONLY0-NEXT:    br i1 [[CMP360]], label [[COND_TRUE362:%.*]], label [[COND_FALSE364:%.*]]
56840 // SIMD-ONLY0:       cond.true362:
56841 // SIMD-ONLY0-NEXT:    [[TMP167:%.*]] = load i16, ptr [[SE]], align 2
56842 // SIMD-ONLY0-NEXT:    [[CONV363:%.*]] = sext i16 [[TMP167]] to i32
56843 // SIMD-ONLY0-NEXT:    br label [[COND_END366:%.*]]
56844 // SIMD-ONLY0:       cond.false364:
56845 // SIMD-ONLY0-NEXT:    [[TMP168:%.*]] = load i16, ptr [[SX]], align 2
56846 // SIMD-ONLY0-NEXT:    [[CONV365:%.*]] = sext i16 [[TMP168]] to i32
56847 // SIMD-ONLY0-NEXT:    br label [[COND_END366]]
56848 // SIMD-ONLY0:       cond.end366:
56849 // SIMD-ONLY0-NEXT:    [[COND367:%.*]] = phi i32 [ [[CONV363]], [[COND_TRUE362]] ], [ [[CONV365]], [[COND_FALSE364]] ]
56850 // SIMD-ONLY0-NEXT:    [[CONV368:%.*]] = trunc i32 [[COND367]] to i16
56851 // SIMD-ONLY0-NEXT:    store i16 [[CONV368]], ptr [[SX]], align 2
56852 // SIMD-ONLY0-NEXT:    [[TMP169:%.*]] = load i16, ptr [[SX]], align 2
56853 // SIMD-ONLY0-NEXT:    store i16 [[TMP169]], ptr [[SV]], align 2
56854 // SIMD-ONLY0-NEXT:    [[TMP170:%.*]] = load i16, ptr [[SX]], align 2
56855 // SIMD-ONLY0-NEXT:    [[CONV369:%.*]] = sext i16 [[TMP170]] to i32
56856 // SIMD-ONLY0-NEXT:    [[TMP171:%.*]] = load i16, ptr [[SE]], align 2
56857 // SIMD-ONLY0-NEXT:    [[CONV370:%.*]] = sext i16 [[TMP171]] to i32
56858 // SIMD-ONLY0-NEXT:    [[CMP371:%.*]] = icmp slt i32 [[CONV369]], [[CONV370]]
56859 // SIMD-ONLY0-NEXT:    br i1 [[CMP371]], label [[COND_TRUE373:%.*]], label [[COND_FALSE375:%.*]]
56860 // SIMD-ONLY0:       cond.true373:
56861 // SIMD-ONLY0-NEXT:    [[TMP172:%.*]] = load i16, ptr [[SE]], align 2
56862 // SIMD-ONLY0-NEXT:    [[CONV374:%.*]] = sext i16 [[TMP172]] to i32
56863 // SIMD-ONLY0-NEXT:    br label [[COND_END377:%.*]]
56864 // SIMD-ONLY0:       cond.false375:
56865 // SIMD-ONLY0-NEXT:    [[TMP173:%.*]] = load i16, ptr [[SX]], align 2
56866 // SIMD-ONLY0-NEXT:    [[CONV376:%.*]] = sext i16 [[TMP173]] to i32
56867 // SIMD-ONLY0-NEXT:    br label [[COND_END377]]
56868 // SIMD-ONLY0:       cond.end377:
56869 // SIMD-ONLY0-NEXT:    [[COND378:%.*]] = phi i32 [ [[CONV374]], [[COND_TRUE373]] ], [ [[CONV376]], [[COND_FALSE375]] ]
56870 // SIMD-ONLY0-NEXT:    [[CONV379:%.*]] = trunc i32 [[COND378]] to i16
56871 // SIMD-ONLY0-NEXT:    store i16 [[CONV379]], ptr [[SX]], align 2
56872 // SIMD-ONLY0-NEXT:    [[TMP174:%.*]] = load i16, ptr [[SX]], align 2
56873 // SIMD-ONLY0-NEXT:    store i16 [[TMP174]], ptr [[SV]], align 2
56874 // SIMD-ONLY0-NEXT:    [[TMP175:%.*]] = load i16, ptr [[SX]], align 2
56875 // SIMD-ONLY0-NEXT:    [[CONV380:%.*]] = sext i16 [[TMP175]] to i32
56876 // SIMD-ONLY0-NEXT:    [[TMP176:%.*]] = load i16, ptr [[SE]], align 2
56877 // SIMD-ONLY0-NEXT:    [[CONV381:%.*]] = sext i16 [[TMP176]] to i32
56878 // SIMD-ONLY0-NEXT:    [[CMP382:%.*]] = icmp eq i32 [[CONV380]], [[CONV381]]
56879 // SIMD-ONLY0-NEXT:    br i1 [[CMP382]], label [[COND_TRUE384:%.*]], label [[COND_FALSE386:%.*]]
56880 // SIMD-ONLY0:       cond.true384:
56881 // SIMD-ONLY0-NEXT:    [[TMP177:%.*]] = load i16, ptr [[SD]], align 2
56882 // SIMD-ONLY0-NEXT:    [[CONV385:%.*]] = sext i16 [[TMP177]] to i32
56883 // SIMD-ONLY0-NEXT:    br label [[COND_END388:%.*]]
56884 // SIMD-ONLY0:       cond.false386:
56885 // SIMD-ONLY0-NEXT:    [[TMP178:%.*]] = load i16, ptr [[SX]], align 2
56886 // SIMD-ONLY0-NEXT:    [[CONV387:%.*]] = sext i16 [[TMP178]] to i32
56887 // SIMD-ONLY0-NEXT:    br label [[COND_END388]]
56888 // SIMD-ONLY0:       cond.end388:
56889 // SIMD-ONLY0-NEXT:    [[COND389:%.*]] = phi i32 [ [[CONV385]], [[COND_TRUE384]] ], [ [[CONV387]], [[COND_FALSE386]] ]
56890 // SIMD-ONLY0-NEXT:    [[CONV390:%.*]] = trunc i32 [[COND389]] to i16
56891 // SIMD-ONLY0-NEXT:    store i16 [[CONV390]], ptr [[SX]], align 2
56892 // SIMD-ONLY0-NEXT:    [[TMP179:%.*]] = load i16, ptr [[SX]], align 2
56893 // SIMD-ONLY0-NEXT:    store i16 [[TMP179]], ptr [[SV]], align 2
56894 // SIMD-ONLY0-NEXT:    [[TMP180:%.*]] = load i16, ptr [[SV]], align 2
56895 // SIMD-ONLY0-NEXT:    ret i16 [[TMP180]]
56896 //
56897 //
56898 // SIMD-ONLY0-LABEL: @usxevd(
56899 // SIMD-ONLY0-NEXT:  entry:
56900 // SIMD-ONLY0-NEXT:    [[USX:%.*]] = alloca i16, align 2
56901 // SIMD-ONLY0-NEXT:    [[USV:%.*]] = alloca i16, align 2
56902 // SIMD-ONLY0-NEXT:    [[USE:%.*]] = alloca i16, align 2
56903 // SIMD-ONLY0-NEXT:    [[USD:%.*]] = alloca i16, align 2
56904 // SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = load i16, ptr [[USX]], align 2
56905 // SIMD-ONLY0-NEXT:    store i16 [[TMP0]], ptr [[USV]], align 2
56906 // SIMD-ONLY0-NEXT:    [[TMP1:%.*]] = load i16, ptr [[USX]], align 2
56907 // SIMD-ONLY0-NEXT:    [[CONV:%.*]] = zext i16 [[TMP1]] to i32
56908 // SIMD-ONLY0-NEXT:    [[TMP2:%.*]] = load i16, ptr [[USE]], align 2
56909 // SIMD-ONLY0-NEXT:    [[CONV1:%.*]] = zext i16 [[TMP2]] to i32
56910 // SIMD-ONLY0-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[CONV]], [[CONV1]]
56911 // SIMD-ONLY0-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
56912 // SIMD-ONLY0:       cond.true:
56913 // SIMD-ONLY0-NEXT:    [[TMP3:%.*]] = load i16, ptr [[USE]], align 2
56914 // SIMD-ONLY0-NEXT:    [[CONV3:%.*]] = zext i16 [[TMP3]] to i32
56915 // SIMD-ONLY0-NEXT:    br label [[COND_END:%.*]]
56916 // SIMD-ONLY0:       cond.false:
56917 // SIMD-ONLY0-NEXT:    [[TMP4:%.*]] = load i16, ptr [[USX]], align 2
56918 // SIMD-ONLY0-NEXT:    [[CONV4:%.*]] = zext i16 [[TMP4]] to i32
56919 // SIMD-ONLY0-NEXT:    br label [[COND_END]]
56920 // SIMD-ONLY0:       cond.end:
56921 // SIMD-ONLY0-NEXT:    [[COND:%.*]] = phi i32 [ [[CONV3]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ]
56922 // SIMD-ONLY0-NEXT:    [[CONV5:%.*]] = trunc i32 [[COND]] to i16
56923 // SIMD-ONLY0-NEXT:    store i16 [[CONV5]], ptr [[USX]], align 2
56924 // SIMD-ONLY0-NEXT:    [[TMP5:%.*]] = load i16, ptr [[USX]], align 2
56925 // SIMD-ONLY0-NEXT:    store i16 [[TMP5]], ptr [[USV]], align 2
56926 // SIMD-ONLY0-NEXT:    [[TMP6:%.*]] = load i16, ptr [[USX]], align 2
56927 // SIMD-ONLY0-NEXT:    [[CONV6:%.*]] = zext i16 [[TMP6]] to i32
56928 // SIMD-ONLY0-NEXT:    [[TMP7:%.*]] = load i16, ptr [[USE]], align 2
56929 // SIMD-ONLY0-NEXT:    [[CONV7:%.*]] = zext i16 [[TMP7]] to i32
56930 // SIMD-ONLY0-NEXT:    [[CMP8:%.*]] = icmp slt i32 [[CONV6]], [[CONV7]]
56931 // SIMD-ONLY0-NEXT:    br i1 [[CMP8]], label [[COND_TRUE10:%.*]], label [[COND_FALSE12:%.*]]
56932 // SIMD-ONLY0:       cond.true10:
56933 // SIMD-ONLY0-NEXT:    [[TMP8:%.*]] = load i16, ptr [[USE]], align 2
56934 // SIMD-ONLY0-NEXT:    [[CONV11:%.*]] = zext i16 [[TMP8]] to i32
56935 // SIMD-ONLY0-NEXT:    br label [[COND_END14:%.*]]
56936 // SIMD-ONLY0:       cond.false12:
56937 // SIMD-ONLY0-NEXT:    [[TMP9:%.*]] = load i16, ptr [[USX]], align 2
56938 // SIMD-ONLY0-NEXT:    [[CONV13:%.*]] = zext i16 [[TMP9]] to i32
56939 // SIMD-ONLY0-NEXT:    br label [[COND_END14]]
56940 // SIMD-ONLY0:       cond.end14:
56941 // SIMD-ONLY0-NEXT:    [[COND15:%.*]] = phi i32 [ [[CONV11]], [[COND_TRUE10]] ], [ [[CONV13]], [[COND_FALSE12]] ]
56942 // SIMD-ONLY0-NEXT:    [[CONV16:%.*]] = trunc i32 [[COND15]] to i16
56943 // SIMD-ONLY0-NEXT:    store i16 [[CONV16]], ptr [[USX]], align 2
56944 // SIMD-ONLY0-NEXT:    [[TMP10:%.*]] = load i16, ptr [[USX]], align 2
56945 // SIMD-ONLY0-NEXT:    store i16 [[TMP10]], ptr [[USV]], align 2
56946 // SIMD-ONLY0-NEXT:    [[TMP11:%.*]] = load i16, ptr [[USX]], align 2
56947 // SIMD-ONLY0-NEXT:    [[CONV17:%.*]] = zext i16 [[TMP11]] to i32
56948 // SIMD-ONLY0-NEXT:    [[TMP12:%.*]] = load i16, ptr [[USE]], align 2
56949 // SIMD-ONLY0-NEXT:    [[CONV18:%.*]] = zext i16 [[TMP12]] to i32
56950 // SIMD-ONLY0-NEXT:    [[CMP19:%.*]] = icmp eq i32 [[CONV17]], [[CONV18]]
56951 // SIMD-ONLY0-NEXT:    br i1 [[CMP19]], label [[COND_TRUE21:%.*]], label [[COND_FALSE23:%.*]]
56952 // SIMD-ONLY0:       cond.true21:
56953 // SIMD-ONLY0-NEXT:    [[TMP13:%.*]] = load i16, ptr [[USD]], align 2
56954 // SIMD-ONLY0-NEXT:    [[CONV22:%.*]] = zext i16 [[TMP13]] to i32
56955 // SIMD-ONLY0-NEXT:    br label [[COND_END25:%.*]]
56956 // SIMD-ONLY0:       cond.false23:
56957 // SIMD-ONLY0-NEXT:    [[TMP14:%.*]] = load i16, ptr [[USX]], align 2
56958 // SIMD-ONLY0-NEXT:    [[CONV24:%.*]] = zext i16 [[TMP14]] to i32
56959 // SIMD-ONLY0-NEXT:    br label [[COND_END25]]
56960 // SIMD-ONLY0:       cond.end25:
56961 // SIMD-ONLY0-NEXT:    [[COND26:%.*]] = phi i32 [ [[CONV22]], [[COND_TRUE21]] ], [ [[CONV24]], [[COND_FALSE23]] ]
56962 // SIMD-ONLY0-NEXT:    [[CONV27:%.*]] = trunc i32 [[COND26]] to i16
56963 // SIMD-ONLY0-NEXT:    store i16 [[CONV27]], ptr [[USX]], align 2
56964 // SIMD-ONLY0-NEXT:    [[TMP15:%.*]] = load i16, ptr [[USX]], align 2
56965 // SIMD-ONLY0-NEXT:    [[CONV28:%.*]] = zext i16 [[TMP15]] to i32
56966 // SIMD-ONLY0-NEXT:    [[TMP16:%.*]] = load i16, ptr [[USE]], align 2
56967 // SIMD-ONLY0-NEXT:    [[CONV29:%.*]] = zext i16 [[TMP16]] to i32
56968 // SIMD-ONLY0-NEXT:    [[CMP30:%.*]] = icmp sgt i32 [[CONV28]], [[CONV29]]
56969 // SIMD-ONLY0-NEXT:    br i1 [[CMP30]], label [[COND_TRUE32:%.*]], label [[COND_FALSE34:%.*]]
56970 // SIMD-ONLY0:       cond.true32:
56971 // SIMD-ONLY0-NEXT:    [[TMP17:%.*]] = load i16, ptr [[USE]], align 2
56972 // SIMD-ONLY0-NEXT:    [[CONV33:%.*]] = zext i16 [[TMP17]] to i32
56973 // SIMD-ONLY0-NEXT:    br label [[COND_END36:%.*]]
56974 // SIMD-ONLY0:       cond.false34:
56975 // SIMD-ONLY0-NEXT:    [[TMP18:%.*]] = load i16, ptr [[USX]], align 2
56976 // SIMD-ONLY0-NEXT:    [[CONV35:%.*]] = zext i16 [[TMP18]] to i32
56977 // SIMD-ONLY0-NEXT:    br label [[COND_END36]]
56978 // SIMD-ONLY0:       cond.end36:
56979 // SIMD-ONLY0-NEXT:    [[COND37:%.*]] = phi i32 [ [[CONV33]], [[COND_TRUE32]] ], [ [[CONV35]], [[COND_FALSE34]] ]
56980 // SIMD-ONLY0-NEXT:    [[CONV38:%.*]] = trunc i32 [[COND37]] to i16
56981 // SIMD-ONLY0-NEXT:    store i16 [[CONV38]], ptr [[USX]], align 2
56982 // SIMD-ONLY0-NEXT:    [[TMP19:%.*]] = load i16, ptr [[USX]], align 2
56983 // SIMD-ONLY0-NEXT:    store i16 [[TMP19]], ptr [[USV]], align 2
56984 // SIMD-ONLY0-NEXT:    [[TMP20:%.*]] = load i16, ptr [[USX]], align 2
56985 // SIMD-ONLY0-NEXT:    [[CONV39:%.*]] = zext i16 [[TMP20]] to i32
56986 // SIMD-ONLY0-NEXT:    [[TMP21:%.*]] = load i16, ptr [[USE]], align 2
56987 // SIMD-ONLY0-NEXT:    [[CONV40:%.*]] = zext i16 [[TMP21]] to i32
56988 // SIMD-ONLY0-NEXT:    [[CMP41:%.*]] = icmp slt i32 [[CONV39]], [[CONV40]]
56989 // SIMD-ONLY0-NEXT:    br i1 [[CMP41]], label [[COND_TRUE43:%.*]], label [[COND_FALSE45:%.*]]
56990 // SIMD-ONLY0:       cond.true43:
56991 // SIMD-ONLY0-NEXT:    [[TMP22:%.*]] = load i16, ptr [[USE]], align 2
56992 // SIMD-ONLY0-NEXT:    [[CONV44:%.*]] = zext i16 [[TMP22]] to i32
56993 // SIMD-ONLY0-NEXT:    br label [[COND_END47:%.*]]
56994 // SIMD-ONLY0:       cond.false45:
56995 // SIMD-ONLY0-NEXT:    [[TMP23:%.*]] = load i16, ptr [[USX]], align 2
56996 // SIMD-ONLY0-NEXT:    [[CONV46:%.*]] = zext i16 [[TMP23]] to i32
56997 // SIMD-ONLY0-NEXT:    br label [[COND_END47]]
56998 // SIMD-ONLY0:       cond.end47:
56999 // SIMD-ONLY0-NEXT:    [[COND48:%.*]] = phi i32 [ [[CONV44]], [[COND_TRUE43]] ], [ [[CONV46]], [[COND_FALSE45]] ]
57000 // SIMD-ONLY0-NEXT:    [[CONV49:%.*]] = trunc i32 [[COND48]] to i16
57001 // SIMD-ONLY0-NEXT:    store i16 [[CONV49]], ptr [[USX]], align 2
57002 // SIMD-ONLY0-NEXT:    [[TMP24:%.*]] = load i16, ptr [[USX]], align 2
57003 // SIMD-ONLY0-NEXT:    store i16 [[TMP24]], ptr [[USV]], align 2
57004 // SIMD-ONLY0-NEXT:    [[TMP25:%.*]] = load i16, ptr [[USX]], align 2
57005 // SIMD-ONLY0-NEXT:    [[CONV50:%.*]] = zext i16 [[TMP25]] to i32
57006 // SIMD-ONLY0-NEXT:    [[TMP26:%.*]] = load i16, ptr [[USE]], align 2
57007 // SIMD-ONLY0-NEXT:    [[CONV51:%.*]] = zext i16 [[TMP26]] to i32
57008 // SIMD-ONLY0-NEXT:    [[CMP52:%.*]] = icmp eq i32 [[CONV50]], [[CONV51]]
57009 // SIMD-ONLY0-NEXT:    br i1 [[CMP52]], label [[COND_TRUE54:%.*]], label [[COND_FALSE56:%.*]]
57010 // SIMD-ONLY0:       cond.true54:
57011 // SIMD-ONLY0-NEXT:    [[TMP27:%.*]] = load i16, ptr [[USD]], align 2
57012 // SIMD-ONLY0-NEXT:    [[CONV55:%.*]] = zext i16 [[TMP27]] to i32
57013 // SIMD-ONLY0-NEXT:    br label [[COND_END58:%.*]]
57014 // SIMD-ONLY0:       cond.false56:
57015 // SIMD-ONLY0-NEXT:    [[TMP28:%.*]] = load i16, ptr [[USX]], align 2
57016 // SIMD-ONLY0-NEXT:    [[CONV57:%.*]] = zext i16 [[TMP28]] to i32
57017 // SIMD-ONLY0-NEXT:    br label [[COND_END58]]
57018 // SIMD-ONLY0:       cond.end58:
57019 // SIMD-ONLY0-NEXT:    [[COND59:%.*]] = phi i32 [ [[CONV55]], [[COND_TRUE54]] ], [ [[CONV57]], [[COND_FALSE56]] ]
57020 // SIMD-ONLY0-NEXT:    [[CONV60:%.*]] = trunc i32 [[COND59]] to i16
57021 // SIMD-ONLY0-NEXT:    store i16 [[CONV60]], ptr [[USX]], align 2
57022 // SIMD-ONLY0-NEXT:    [[TMP29:%.*]] = load i16, ptr [[USX]], align 2
57023 // SIMD-ONLY0-NEXT:    store i16 [[TMP29]], ptr [[USV]], align 2
57024 // SIMD-ONLY0-NEXT:    [[TMP30:%.*]] = load i16, ptr [[USX]], align 2
57025 // SIMD-ONLY0-NEXT:    store i16 [[TMP30]], ptr [[USV]], align 2
57026 // SIMD-ONLY0-NEXT:    [[TMP31:%.*]] = load i16, ptr [[USX]], align 2
57027 // SIMD-ONLY0-NEXT:    [[CONV61:%.*]] = zext i16 [[TMP31]] to i32
57028 // SIMD-ONLY0-NEXT:    [[TMP32:%.*]] = load i16, ptr [[USE]], align 2
57029 // SIMD-ONLY0-NEXT:    [[CONV62:%.*]] = zext i16 [[TMP32]] to i32
57030 // SIMD-ONLY0-NEXT:    [[CMP63:%.*]] = icmp sgt i32 [[CONV61]], [[CONV62]]
57031 // SIMD-ONLY0-NEXT:    br i1 [[CMP63]], label [[COND_TRUE65:%.*]], label [[COND_FALSE67:%.*]]
57032 // SIMD-ONLY0:       cond.true65:
57033 // SIMD-ONLY0-NEXT:    [[TMP33:%.*]] = load i16, ptr [[USE]], align 2
57034 // SIMD-ONLY0-NEXT:    [[CONV66:%.*]] = zext i16 [[TMP33]] to i32
57035 // SIMD-ONLY0-NEXT:    br label [[COND_END69:%.*]]
57036 // SIMD-ONLY0:       cond.false67:
57037 // SIMD-ONLY0-NEXT:    [[TMP34:%.*]] = load i16, ptr [[USX]], align 2
57038 // SIMD-ONLY0-NEXT:    [[CONV68:%.*]] = zext i16 [[TMP34]] to i32
57039 // SIMD-ONLY0-NEXT:    br label [[COND_END69]]
57040 // SIMD-ONLY0:       cond.end69:
57041 // SIMD-ONLY0-NEXT:    [[COND70:%.*]] = phi i32 [ [[CONV66]], [[COND_TRUE65]] ], [ [[CONV68]], [[COND_FALSE67]] ]
57042 // SIMD-ONLY0-NEXT:    [[CONV71:%.*]] = trunc i32 [[COND70]] to i16
57043 // SIMD-ONLY0-NEXT:    store i16 [[CONV71]], ptr [[USX]], align 2
57044 // SIMD-ONLY0-NEXT:    [[TMP35:%.*]] = load i16, ptr [[USX]], align 2
57045 // SIMD-ONLY0-NEXT:    store i16 [[TMP35]], ptr [[USV]], align 2
57046 // SIMD-ONLY0-NEXT:    [[TMP36:%.*]] = load i16, ptr [[USX]], align 2
57047 // SIMD-ONLY0-NEXT:    [[CONV72:%.*]] = zext i16 [[TMP36]] to i32
57048 // SIMD-ONLY0-NEXT:    [[TMP37:%.*]] = load i16, ptr [[USE]], align 2
57049 // SIMD-ONLY0-NEXT:    [[CONV73:%.*]] = zext i16 [[TMP37]] to i32
57050 // SIMD-ONLY0-NEXT:    [[CMP74:%.*]] = icmp slt i32 [[CONV72]], [[CONV73]]
57051 // SIMD-ONLY0-NEXT:    br i1 [[CMP74]], label [[COND_TRUE76:%.*]], label [[COND_FALSE78:%.*]]
57052 // SIMD-ONLY0:       cond.true76:
57053 // SIMD-ONLY0-NEXT:    [[TMP38:%.*]] = load i16, ptr [[USE]], align 2
57054 // SIMD-ONLY0-NEXT:    [[CONV77:%.*]] = zext i16 [[TMP38]] to i32
57055 // SIMD-ONLY0-NEXT:    br label [[COND_END80:%.*]]
57056 // SIMD-ONLY0:       cond.false78:
57057 // SIMD-ONLY0-NEXT:    [[TMP39:%.*]] = load i16, ptr [[USX]], align 2
57058 // SIMD-ONLY0-NEXT:    [[CONV79:%.*]] = zext i16 [[TMP39]] to i32
57059 // SIMD-ONLY0-NEXT:    br label [[COND_END80]]
57060 // SIMD-ONLY0:       cond.end80:
57061 // SIMD-ONLY0-NEXT:    [[COND81:%.*]] = phi i32 [ [[CONV77]], [[COND_TRUE76]] ], [ [[CONV79]], [[COND_FALSE78]] ]
57062 // SIMD-ONLY0-NEXT:    [[CONV82:%.*]] = trunc i32 [[COND81]] to i16
57063 // SIMD-ONLY0-NEXT:    store i16 [[CONV82]], ptr [[USX]], align 2
57064 // SIMD-ONLY0-NEXT:    [[TMP40:%.*]] = load i16, ptr [[USX]], align 2
57065 // SIMD-ONLY0-NEXT:    store i16 [[TMP40]], ptr [[USV]], align 2
57066 // SIMD-ONLY0-NEXT:    [[TMP41:%.*]] = load i16, ptr [[USX]], align 2
57067 // SIMD-ONLY0-NEXT:    [[CONV83:%.*]] = zext i16 [[TMP41]] to i32
57068 // SIMD-ONLY0-NEXT:    [[TMP42:%.*]] = load i16, ptr [[USE]], align 2
57069 // SIMD-ONLY0-NEXT:    [[CONV84:%.*]] = zext i16 [[TMP42]] to i32
57070 // SIMD-ONLY0-NEXT:    [[CMP85:%.*]] = icmp eq i32 [[CONV83]], [[CONV84]]
57071 // SIMD-ONLY0-NEXT:    br i1 [[CMP85]], label [[COND_TRUE87:%.*]], label [[COND_FALSE89:%.*]]
57072 // SIMD-ONLY0:       cond.true87:
57073 // SIMD-ONLY0-NEXT:    [[TMP43:%.*]] = load i16, ptr [[USD]], align 2
57074 // SIMD-ONLY0-NEXT:    [[CONV88:%.*]] = zext i16 [[TMP43]] to i32
57075 // SIMD-ONLY0-NEXT:    br label [[COND_END91:%.*]]
57076 // SIMD-ONLY0:       cond.false89:
57077 // SIMD-ONLY0-NEXT:    [[TMP44:%.*]] = load i16, ptr [[USX]], align 2
57078 // SIMD-ONLY0-NEXT:    [[CONV90:%.*]] = zext i16 [[TMP44]] to i32
57079 // SIMD-ONLY0-NEXT:    br label [[COND_END91]]
57080 // SIMD-ONLY0:       cond.end91:
57081 // SIMD-ONLY0-NEXT:    [[COND92:%.*]] = phi i32 [ [[CONV88]], [[COND_TRUE87]] ], [ [[CONV90]], [[COND_FALSE89]] ]
57082 // SIMD-ONLY0-NEXT:    [[CONV93:%.*]] = trunc i32 [[COND92]] to i16
57083 // SIMD-ONLY0-NEXT:    store i16 [[CONV93]], ptr [[USX]], align 2
57084 // SIMD-ONLY0-NEXT:    [[TMP45:%.*]] = load i16, ptr [[USX]], align 2
57085 // SIMD-ONLY0-NEXT:    [[CONV94:%.*]] = zext i16 [[TMP45]] to i32
57086 // SIMD-ONLY0-NEXT:    [[TMP46:%.*]] = load i16, ptr [[USE]], align 2
57087 // SIMD-ONLY0-NEXT:    [[CONV95:%.*]] = zext i16 [[TMP46]] to i32
57088 // SIMD-ONLY0-NEXT:    [[CMP96:%.*]] = icmp sgt i32 [[CONV94]], [[CONV95]]
57089 // SIMD-ONLY0-NEXT:    br i1 [[CMP96]], label [[COND_TRUE98:%.*]], label [[COND_FALSE100:%.*]]
57090 // SIMD-ONLY0:       cond.true98:
57091 // SIMD-ONLY0-NEXT:    [[TMP47:%.*]] = load i16, ptr [[USE]], align 2
57092 // SIMD-ONLY0-NEXT:    [[CONV99:%.*]] = zext i16 [[TMP47]] to i32
57093 // SIMD-ONLY0-NEXT:    br label [[COND_END102:%.*]]
57094 // SIMD-ONLY0:       cond.false100:
57095 // SIMD-ONLY0-NEXT:    [[TMP48:%.*]] = load i16, ptr [[USX]], align 2
57096 // SIMD-ONLY0-NEXT:    [[CONV101:%.*]] = zext i16 [[TMP48]] to i32
57097 // SIMD-ONLY0-NEXT:    br label [[COND_END102]]
57098 // SIMD-ONLY0:       cond.end102:
57099 // SIMD-ONLY0-NEXT:    [[COND103:%.*]] = phi i32 [ [[CONV99]], [[COND_TRUE98]] ], [ [[CONV101]], [[COND_FALSE100]] ]
57100 // SIMD-ONLY0-NEXT:    [[CONV104:%.*]] = trunc i32 [[COND103]] to i16
57101 // SIMD-ONLY0-NEXT:    store i16 [[CONV104]], ptr [[USX]], align 2
57102 // SIMD-ONLY0-NEXT:    [[TMP49:%.*]] = load i16, ptr [[USX]], align 2
57103 // SIMD-ONLY0-NEXT:    store i16 [[TMP49]], ptr [[USV]], align 2
57104 // SIMD-ONLY0-NEXT:    [[TMP50:%.*]] = load i16, ptr [[USX]], align 2
57105 // SIMD-ONLY0-NEXT:    [[CONV105:%.*]] = zext i16 [[TMP50]] to i32
57106 // SIMD-ONLY0-NEXT:    [[TMP51:%.*]] = load i16, ptr [[USE]], align 2
57107 // SIMD-ONLY0-NEXT:    [[CONV106:%.*]] = zext i16 [[TMP51]] to i32
57108 // SIMD-ONLY0-NEXT:    [[CMP107:%.*]] = icmp slt i32 [[CONV105]], [[CONV106]]
57109 // SIMD-ONLY0-NEXT:    br i1 [[CMP107]], label [[COND_TRUE109:%.*]], label [[COND_FALSE111:%.*]]
57110 // SIMD-ONLY0:       cond.true109:
57111 // SIMD-ONLY0-NEXT:    [[TMP52:%.*]] = load i16, ptr [[USE]], align 2
57112 // SIMD-ONLY0-NEXT:    [[CONV110:%.*]] = zext i16 [[TMP52]] to i32
57113 // SIMD-ONLY0-NEXT:    br label [[COND_END113:%.*]]
57114 // SIMD-ONLY0:       cond.false111:
57115 // SIMD-ONLY0-NEXT:    [[TMP53:%.*]] = load i16, ptr [[USX]], align 2
57116 // SIMD-ONLY0-NEXT:    [[CONV112:%.*]] = zext i16 [[TMP53]] to i32
57117 // SIMD-ONLY0-NEXT:    br label [[COND_END113]]
57118 // SIMD-ONLY0:       cond.end113:
57119 // SIMD-ONLY0-NEXT:    [[COND114:%.*]] = phi i32 [ [[CONV110]], [[COND_TRUE109]] ], [ [[CONV112]], [[COND_FALSE111]] ]
57120 // SIMD-ONLY0-NEXT:    [[CONV115:%.*]] = trunc i32 [[COND114]] to i16
57121 // SIMD-ONLY0-NEXT:    store i16 [[CONV115]], ptr [[USX]], align 2
57122 // SIMD-ONLY0-NEXT:    [[TMP54:%.*]] = load i16, ptr [[USX]], align 2
57123 // SIMD-ONLY0-NEXT:    store i16 [[TMP54]], ptr [[USV]], align 2
57124 // SIMD-ONLY0-NEXT:    [[TMP55:%.*]] = load i16, ptr [[USX]], align 2
57125 // SIMD-ONLY0-NEXT:    [[CONV116:%.*]] = zext i16 [[TMP55]] to i32
57126 // SIMD-ONLY0-NEXT:    [[TMP56:%.*]] = load i16, ptr [[USE]], align 2
57127 // SIMD-ONLY0-NEXT:    [[CONV117:%.*]] = zext i16 [[TMP56]] to i32
57128 // SIMD-ONLY0-NEXT:    [[CMP118:%.*]] = icmp eq i32 [[CONV116]], [[CONV117]]
57129 // SIMD-ONLY0-NEXT:    br i1 [[CMP118]], label [[COND_TRUE120:%.*]], label [[COND_FALSE122:%.*]]
57130 // SIMD-ONLY0:       cond.true120:
57131 // SIMD-ONLY0-NEXT:    [[TMP57:%.*]] = load i16, ptr [[USD]], align 2
57132 // SIMD-ONLY0-NEXT:    [[CONV121:%.*]] = zext i16 [[TMP57]] to i32
57133 // SIMD-ONLY0-NEXT:    br label [[COND_END124:%.*]]
57134 // SIMD-ONLY0:       cond.false122:
57135 // SIMD-ONLY0-NEXT:    [[TMP58:%.*]] = load i16, ptr [[USX]], align 2
57136 // SIMD-ONLY0-NEXT:    [[CONV123:%.*]] = zext i16 [[TMP58]] to i32
57137 // SIMD-ONLY0-NEXT:    br label [[COND_END124]]
57138 // SIMD-ONLY0:       cond.end124:
57139 // SIMD-ONLY0-NEXT:    [[COND125:%.*]] = phi i32 [ [[CONV121]], [[COND_TRUE120]] ], [ [[CONV123]], [[COND_FALSE122]] ]
57140 // SIMD-ONLY0-NEXT:    [[CONV126:%.*]] = trunc i32 [[COND125]] to i16
57141 // SIMD-ONLY0-NEXT:    store i16 [[CONV126]], ptr [[USX]], align 2
57142 // SIMD-ONLY0-NEXT:    [[TMP59:%.*]] = load i16, ptr [[USX]], align 2
57143 // SIMD-ONLY0-NEXT:    store i16 [[TMP59]], ptr [[USV]], align 2
57144 // SIMD-ONLY0-NEXT:    [[TMP60:%.*]] = load i16, ptr [[USX]], align 2
57145 // SIMD-ONLY0-NEXT:    store i16 [[TMP60]], ptr [[USV]], align 2
57146 // SIMD-ONLY0-NEXT:    [[TMP61:%.*]] = load i16, ptr [[USX]], align 2
57147 // SIMD-ONLY0-NEXT:    [[CONV127:%.*]] = zext i16 [[TMP61]] to i32
57148 // SIMD-ONLY0-NEXT:    [[TMP62:%.*]] = load i16, ptr [[USE]], align 2
57149 // SIMD-ONLY0-NEXT:    [[CONV128:%.*]] = zext i16 [[TMP62]] to i32
57150 // SIMD-ONLY0-NEXT:    [[CMP129:%.*]] = icmp sgt i32 [[CONV127]], [[CONV128]]
57151 // SIMD-ONLY0-NEXT:    br i1 [[CMP129]], label [[COND_TRUE131:%.*]], label [[COND_FALSE133:%.*]]
57152 // SIMD-ONLY0:       cond.true131:
57153 // SIMD-ONLY0-NEXT:    [[TMP63:%.*]] = load i16, ptr [[USE]], align 2
57154 // SIMD-ONLY0-NEXT:    [[CONV132:%.*]] = zext i16 [[TMP63]] to i32
57155 // SIMD-ONLY0-NEXT:    br label [[COND_END135:%.*]]
57156 // SIMD-ONLY0:       cond.false133:
57157 // SIMD-ONLY0-NEXT:    [[TMP64:%.*]] = load i16, ptr [[USX]], align 2
57158 // SIMD-ONLY0-NEXT:    [[CONV134:%.*]] = zext i16 [[TMP64]] to i32
57159 // SIMD-ONLY0-NEXT:    br label [[COND_END135]]
57160 // SIMD-ONLY0:       cond.end135:
57161 // SIMD-ONLY0-NEXT:    [[COND136:%.*]] = phi i32 [ [[CONV132]], [[COND_TRUE131]] ], [ [[CONV134]], [[COND_FALSE133]] ]
57162 // SIMD-ONLY0-NEXT:    [[CONV137:%.*]] = trunc i32 [[COND136]] to i16
57163 // SIMD-ONLY0-NEXT:    store i16 [[CONV137]], ptr [[USX]], align 2
57164 // SIMD-ONLY0-NEXT:    [[TMP65:%.*]] = load i16, ptr [[USX]], align 2
57165 // SIMD-ONLY0-NEXT:    store i16 [[TMP65]], ptr [[USV]], align 2
57166 // SIMD-ONLY0-NEXT:    [[TMP66:%.*]] = load i16, ptr [[USX]], align 2
57167 // SIMD-ONLY0-NEXT:    [[CONV138:%.*]] = zext i16 [[TMP66]] to i32
57168 // SIMD-ONLY0-NEXT:    [[TMP67:%.*]] = load i16, ptr [[USE]], align 2
57169 // SIMD-ONLY0-NEXT:    [[CONV139:%.*]] = zext i16 [[TMP67]] to i32
57170 // SIMD-ONLY0-NEXT:    [[CMP140:%.*]] = icmp slt i32 [[CONV138]], [[CONV139]]
57171 // SIMD-ONLY0-NEXT:    br i1 [[CMP140]], label [[COND_TRUE142:%.*]], label [[COND_FALSE144:%.*]]
57172 // SIMD-ONLY0:       cond.true142:
57173 // SIMD-ONLY0-NEXT:    [[TMP68:%.*]] = load i16, ptr [[USE]], align 2
57174 // SIMD-ONLY0-NEXT:    [[CONV143:%.*]] = zext i16 [[TMP68]] to i32
57175 // SIMD-ONLY0-NEXT:    br label [[COND_END146:%.*]]
57176 // SIMD-ONLY0:       cond.false144:
57177 // SIMD-ONLY0-NEXT:    [[TMP69:%.*]] = load i16, ptr [[USX]], align 2
57178 // SIMD-ONLY0-NEXT:    [[CONV145:%.*]] = zext i16 [[TMP69]] to i32
57179 // SIMD-ONLY0-NEXT:    br label [[COND_END146]]
57180 // SIMD-ONLY0:       cond.end146:
57181 // SIMD-ONLY0-NEXT:    [[COND147:%.*]] = phi i32 [ [[CONV143]], [[COND_TRUE142]] ], [ [[CONV145]], [[COND_FALSE144]] ]
57182 // SIMD-ONLY0-NEXT:    [[CONV148:%.*]] = trunc i32 [[COND147]] to i16
57183 // SIMD-ONLY0-NEXT:    store i16 [[CONV148]], ptr [[USX]], align 2
57184 // SIMD-ONLY0-NEXT:    [[TMP70:%.*]] = load i16, ptr [[USX]], align 2
57185 // SIMD-ONLY0-NEXT:    store i16 [[TMP70]], ptr [[USV]], align 2
57186 // SIMD-ONLY0-NEXT:    [[TMP71:%.*]] = load i16, ptr [[USX]], align 2
57187 // SIMD-ONLY0-NEXT:    [[CONV149:%.*]] = zext i16 [[TMP71]] to i32
57188 // SIMD-ONLY0-NEXT:    [[TMP72:%.*]] = load i16, ptr [[USE]], align 2
57189 // SIMD-ONLY0-NEXT:    [[CONV150:%.*]] = zext i16 [[TMP72]] to i32
57190 // SIMD-ONLY0-NEXT:    [[CMP151:%.*]] = icmp eq i32 [[CONV149]], [[CONV150]]
57191 // SIMD-ONLY0-NEXT:    br i1 [[CMP151]], label [[COND_TRUE153:%.*]], label [[COND_FALSE155:%.*]]
57192 // SIMD-ONLY0:       cond.true153:
57193 // SIMD-ONLY0-NEXT:    [[TMP73:%.*]] = load i16, ptr [[USD]], align 2
57194 // SIMD-ONLY0-NEXT:    [[CONV154:%.*]] = zext i16 [[TMP73]] to i32
57195 // SIMD-ONLY0-NEXT:    br label [[COND_END157:%.*]]
57196 // SIMD-ONLY0:       cond.false155:
57197 // SIMD-ONLY0-NEXT:    [[TMP74:%.*]] = load i16, ptr [[USX]], align 2
57198 // SIMD-ONLY0-NEXT:    [[CONV156:%.*]] = zext i16 [[TMP74]] to i32
57199 // SIMD-ONLY0-NEXT:    br label [[COND_END157]]
57200 // SIMD-ONLY0:       cond.end157:
57201 // SIMD-ONLY0-NEXT:    [[COND158:%.*]] = phi i32 [ [[CONV154]], [[COND_TRUE153]] ], [ [[CONV156]], [[COND_FALSE155]] ]
57202 // SIMD-ONLY0-NEXT:    [[CONV159:%.*]] = trunc i32 [[COND158]] to i16
57203 // SIMD-ONLY0-NEXT:    store i16 [[CONV159]], ptr [[USX]], align 2
57204 // SIMD-ONLY0-NEXT:    [[TMP75:%.*]] = load i16, ptr [[USX]], align 2
57205 // SIMD-ONLY0-NEXT:    [[CONV160:%.*]] = zext i16 [[TMP75]] to i32
57206 // SIMD-ONLY0-NEXT:    [[TMP76:%.*]] = load i16, ptr [[USE]], align 2
57207 // SIMD-ONLY0-NEXT:    [[CONV161:%.*]] = zext i16 [[TMP76]] to i32
57208 // SIMD-ONLY0-NEXT:    [[CMP162:%.*]] = icmp sgt i32 [[CONV160]], [[CONV161]]
57209 // SIMD-ONLY0-NEXT:    br i1 [[CMP162]], label [[COND_TRUE164:%.*]], label [[COND_FALSE166:%.*]]
57210 // SIMD-ONLY0:       cond.true164:
57211 // SIMD-ONLY0-NEXT:    [[TMP77:%.*]] = load i16, ptr [[USE]], align 2
57212 // SIMD-ONLY0-NEXT:    [[CONV165:%.*]] = zext i16 [[TMP77]] to i32
57213 // SIMD-ONLY0-NEXT:    br label [[COND_END168:%.*]]
57214 // SIMD-ONLY0:       cond.false166:
57215 // SIMD-ONLY0-NEXT:    [[TMP78:%.*]] = load i16, ptr [[USX]], align 2
57216 // SIMD-ONLY0-NEXT:    [[CONV167:%.*]] = zext i16 [[TMP78]] to i32
57217 // SIMD-ONLY0-NEXT:    br label [[COND_END168]]
57218 // SIMD-ONLY0:       cond.end168:
57219 // SIMD-ONLY0-NEXT:    [[COND169:%.*]] = phi i32 [ [[CONV165]], [[COND_TRUE164]] ], [ [[CONV167]], [[COND_FALSE166]] ]
57220 // SIMD-ONLY0-NEXT:    [[CONV170:%.*]] = trunc i32 [[COND169]] to i16
57221 // SIMD-ONLY0-NEXT:    store i16 [[CONV170]], ptr [[USX]], align 2
57222 // SIMD-ONLY0-NEXT:    [[TMP79:%.*]] = load i16, ptr [[USX]], align 2
57223 // SIMD-ONLY0-NEXT:    store i16 [[TMP79]], ptr [[USV]], align 2
57224 // SIMD-ONLY0-NEXT:    [[TMP80:%.*]] = load i16, ptr [[USX]], align 2
57225 // SIMD-ONLY0-NEXT:    [[CONV171:%.*]] = zext i16 [[TMP80]] to i32
57226 // SIMD-ONLY0-NEXT:    [[TMP81:%.*]] = load i16, ptr [[USE]], align 2
57227 // SIMD-ONLY0-NEXT:    [[CONV172:%.*]] = zext i16 [[TMP81]] to i32
57228 // SIMD-ONLY0-NEXT:    [[CMP173:%.*]] = icmp slt i32 [[CONV171]], [[CONV172]]
57229 // SIMD-ONLY0-NEXT:    br i1 [[CMP173]], label [[COND_TRUE175:%.*]], label [[COND_FALSE177:%.*]]
57230 // SIMD-ONLY0:       cond.true175:
57231 // SIMD-ONLY0-NEXT:    [[TMP82:%.*]] = load i16, ptr [[USE]], align 2
57232 // SIMD-ONLY0-NEXT:    [[CONV176:%.*]] = zext i16 [[TMP82]] to i32
57233 // SIMD-ONLY0-NEXT:    br label [[COND_END179:%.*]]
57234 // SIMD-ONLY0:       cond.false177:
57235 // SIMD-ONLY0-NEXT:    [[TMP83:%.*]] = load i16, ptr [[USX]], align 2
57236 // SIMD-ONLY0-NEXT:    [[CONV178:%.*]] = zext i16 [[TMP83]] to i32
57237 // SIMD-ONLY0-NEXT:    br label [[COND_END179]]
57238 // SIMD-ONLY0:       cond.end179:
57239 // SIMD-ONLY0-NEXT:    [[COND180:%.*]] = phi i32 [ [[CONV176]], [[COND_TRUE175]] ], [ [[CONV178]], [[COND_FALSE177]] ]
57240 // SIMD-ONLY0-NEXT:    [[CONV181:%.*]] = trunc i32 [[COND180]] to i16
57241 // SIMD-ONLY0-NEXT:    store i16 [[CONV181]], ptr [[USX]], align 2
57242 // SIMD-ONLY0-NEXT:    [[TMP84:%.*]] = load i16, ptr [[USX]], align 2
57243 // SIMD-ONLY0-NEXT:    store i16 [[TMP84]], ptr [[USV]], align 2
57244 // SIMD-ONLY0-NEXT:    [[TMP85:%.*]] = load i16, ptr [[USX]], align 2
57245 // SIMD-ONLY0-NEXT:    [[CONV182:%.*]] = zext i16 [[TMP85]] to i32
57246 // SIMD-ONLY0-NEXT:    [[TMP86:%.*]] = load i16, ptr [[USE]], align 2
57247 // SIMD-ONLY0-NEXT:    [[CONV183:%.*]] = zext i16 [[TMP86]] to i32
57248 // SIMD-ONLY0-NEXT:    [[CMP184:%.*]] = icmp eq i32 [[CONV182]], [[CONV183]]
57249 // SIMD-ONLY0-NEXT:    br i1 [[CMP184]], label [[COND_TRUE186:%.*]], label [[COND_FALSE188:%.*]]
57250 // SIMD-ONLY0:       cond.true186:
57251 // SIMD-ONLY0-NEXT:    [[TMP87:%.*]] = load i16, ptr [[USD]], align 2
57252 // SIMD-ONLY0-NEXT:    [[CONV187:%.*]] = zext i16 [[TMP87]] to i32
57253 // SIMD-ONLY0-NEXT:    br label [[COND_END190:%.*]]
57254 // SIMD-ONLY0:       cond.false188:
57255 // SIMD-ONLY0-NEXT:    [[TMP88:%.*]] = load i16, ptr [[USX]], align 2
57256 // SIMD-ONLY0-NEXT:    [[CONV189:%.*]] = zext i16 [[TMP88]] to i32
57257 // SIMD-ONLY0-NEXT:    br label [[COND_END190]]
57258 // SIMD-ONLY0:       cond.end190:
57259 // SIMD-ONLY0-NEXT:    [[COND191:%.*]] = phi i32 [ [[CONV187]], [[COND_TRUE186]] ], [ [[CONV189]], [[COND_FALSE188]] ]
57260 // SIMD-ONLY0-NEXT:    [[CONV192:%.*]] = trunc i32 [[COND191]] to i16
57261 // SIMD-ONLY0-NEXT:    store i16 [[CONV192]], ptr [[USX]], align 2
57262 // SIMD-ONLY0-NEXT:    [[TMP89:%.*]] = load i16, ptr [[USX]], align 2
57263 // SIMD-ONLY0-NEXT:    store i16 [[TMP89]], ptr [[USV]], align 2
57264 // SIMD-ONLY0-NEXT:    [[TMP90:%.*]] = load i16, ptr [[USX]], align 2
57265 // SIMD-ONLY0-NEXT:    store i16 [[TMP90]], ptr [[USV]], align 2
57266 // SIMD-ONLY0-NEXT:    [[TMP91:%.*]] = load i16, ptr [[USX]], align 2
57267 // SIMD-ONLY0-NEXT:    [[CONV193:%.*]] = zext i16 [[TMP91]] to i32
57268 // SIMD-ONLY0-NEXT:    [[TMP92:%.*]] = load i16, ptr [[USE]], align 2
57269 // SIMD-ONLY0-NEXT:    [[CONV194:%.*]] = zext i16 [[TMP92]] to i32
57270 // SIMD-ONLY0-NEXT:    [[CMP195:%.*]] = icmp sgt i32 [[CONV193]], [[CONV194]]
57271 // SIMD-ONLY0-NEXT:    br i1 [[CMP195]], label [[COND_TRUE197:%.*]], label [[COND_FALSE199:%.*]]
57272 // SIMD-ONLY0:       cond.true197:
57273 // SIMD-ONLY0-NEXT:    [[TMP93:%.*]] = load i16, ptr [[USE]], align 2
57274 // SIMD-ONLY0-NEXT:    [[CONV198:%.*]] = zext i16 [[TMP93]] to i32
57275 // SIMD-ONLY0-NEXT:    br label [[COND_END201:%.*]]
57276 // SIMD-ONLY0:       cond.false199:
57277 // SIMD-ONLY0-NEXT:    [[TMP94:%.*]] = load i16, ptr [[USX]], align 2
57278 // SIMD-ONLY0-NEXT:    [[CONV200:%.*]] = zext i16 [[TMP94]] to i32
57279 // SIMD-ONLY0-NEXT:    br label [[COND_END201]]
57280 // SIMD-ONLY0:       cond.end201:
57281 // SIMD-ONLY0-NEXT:    [[COND202:%.*]] = phi i32 [ [[CONV198]], [[COND_TRUE197]] ], [ [[CONV200]], [[COND_FALSE199]] ]
57282 // SIMD-ONLY0-NEXT:    [[CONV203:%.*]] = trunc i32 [[COND202]] to i16
57283 // SIMD-ONLY0-NEXT:    store i16 [[CONV203]], ptr [[USX]], align 2
57284 // SIMD-ONLY0-NEXT:    [[TMP95:%.*]] = load i16, ptr [[USX]], align 2
57285 // SIMD-ONLY0-NEXT:    store i16 [[TMP95]], ptr [[USV]], align 2
57286 // SIMD-ONLY0-NEXT:    [[TMP96:%.*]] = load i16, ptr [[USX]], align 2
57287 // SIMD-ONLY0-NEXT:    [[CONV204:%.*]] = zext i16 [[TMP96]] to i32
57288 // SIMD-ONLY0-NEXT:    [[TMP97:%.*]] = load i16, ptr [[USE]], align 2
57289 // SIMD-ONLY0-NEXT:    [[CONV205:%.*]] = zext i16 [[TMP97]] to i32
57290 // SIMD-ONLY0-NEXT:    [[CMP206:%.*]] = icmp slt i32 [[CONV204]], [[CONV205]]
57291 // SIMD-ONLY0-NEXT:    br i1 [[CMP206]], label [[COND_TRUE208:%.*]], label [[COND_FALSE210:%.*]]
57292 // SIMD-ONLY0:       cond.true208:
57293 // SIMD-ONLY0-NEXT:    [[TMP98:%.*]] = load i16, ptr [[USE]], align 2
57294 // SIMD-ONLY0-NEXT:    [[CONV209:%.*]] = zext i16 [[TMP98]] to i32
57295 // SIMD-ONLY0-NEXT:    br label [[COND_END212:%.*]]
57296 // SIMD-ONLY0:       cond.false210:
57297 // SIMD-ONLY0-NEXT:    [[TMP99:%.*]] = load i16, ptr [[USX]], align 2
57298 // SIMD-ONLY0-NEXT:    [[CONV211:%.*]] = zext i16 [[TMP99]] to i32
57299 // SIMD-ONLY0-NEXT:    br label [[COND_END212]]
57300 // SIMD-ONLY0:       cond.end212:
57301 // SIMD-ONLY0-NEXT:    [[COND213:%.*]] = phi i32 [ [[CONV209]], [[COND_TRUE208]] ], [ [[CONV211]], [[COND_FALSE210]] ]
57302 // SIMD-ONLY0-NEXT:    [[CONV214:%.*]] = trunc i32 [[COND213]] to i16
57303 // SIMD-ONLY0-NEXT:    store i16 [[CONV214]], ptr [[USX]], align 2
57304 // SIMD-ONLY0-NEXT:    [[TMP100:%.*]] = load i16, ptr [[USX]], align 2
57305 // SIMD-ONLY0-NEXT:    store i16 [[TMP100]], ptr [[USV]], align 2
57306 // SIMD-ONLY0-NEXT:    [[TMP101:%.*]] = load i16, ptr [[USX]], align 2
57307 // SIMD-ONLY0-NEXT:    [[CONV215:%.*]] = zext i16 [[TMP101]] to i32
57308 // SIMD-ONLY0-NEXT:    [[TMP102:%.*]] = load i16, ptr [[USE]], align 2
57309 // SIMD-ONLY0-NEXT:    [[CONV216:%.*]] = zext i16 [[TMP102]] to i32
57310 // SIMD-ONLY0-NEXT:    [[CMP217:%.*]] = icmp eq i32 [[CONV215]], [[CONV216]]
57311 // SIMD-ONLY0-NEXT:    br i1 [[CMP217]], label [[COND_TRUE219:%.*]], label [[COND_FALSE221:%.*]]
57312 // SIMD-ONLY0:       cond.true219:
57313 // SIMD-ONLY0-NEXT:    [[TMP103:%.*]] = load i16, ptr [[USD]], align 2
57314 // SIMD-ONLY0-NEXT:    [[CONV220:%.*]] = zext i16 [[TMP103]] to i32
57315 // SIMD-ONLY0-NEXT:    br label [[COND_END223:%.*]]
57316 // SIMD-ONLY0:       cond.false221:
57317 // SIMD-ONLY0-NEXT:    [[TMP104:%.*]] = load i16, ptr [[USX]], align 2
57318 // SIMD-ONLY0-NEXT:    [[CONV222:%.*]] = zext i16 [[TMP104]] to i32
57319 // SIMD-ONLY0-NEXT:    br label [[COND_END223]]
57320 // SIMD-ONLY0:       cond.end223:
57321 // SIMD-ONLY0-NEXT:    [[COND224:%.*]] = phi i32 [ [[CONV220]], [[COND_TRUE219]] ], [ [[CONV222]], [[COND_FALSE221]] ]
57322 // SIMD-ONLY0-NEXT:    [[CONV225:%.*]] = trunc i32 [[COND224]] to i16
57323 // SIMD-ONLY0-NEXT:    store i16 [[CONV225]], ptr [[USX]], align 2
57324 // SIMD-ONLY0-NEXT:    [[TMP105:%.*]] = load i16, ptr [[USX]], align 2
57325 // SIMD-ONLY0-NEXT:    [[CONV226:%.*]] = zext i16 [[TMP105]] to i32
57326 // SIMD-ONLY0-NEXT:    [[TMP106:%.*]] = load i16, ptr [[USE]], align 2
57327 // SIMD-ONLY0-NEXT:    [[CONV227:%.*]] = zext i16 [[TMP106]] to i32
57328 // SIMD-ONLY0-NEXT:    [[CMP228:%.*]] = icmp sgt i32 [[CONV226]], [[CONV227]]
57329 // SIMD-ONLY0-NEXT:    br i1 [[CMP228]], label [[COND_TRUE230:%.*]], label [[COND_FALSE232:%.*]]
57330 // SIMD-ONLY0:       cond.true230:
57331 // SIMD-ONLY0-NEXT:    [[TMP107:%.*]] = load i16, ptr [[USE]], align 2
57332 // SIMD-ONLY0-NEXT:    [[CONV231:%.*]] = zext i16 [[TMP107]] to i32
57333 // SIMD-ONLY0-NEXT:    br label [[COND_END234:%.*]]
57334 // SIMD-ONLY0:       cond.false232:
57335 // SIMD-ONLY0-NEXT:    [[TMP108:%.*]] = load i16, ptr [[USX]], align 2
57336 // SIMD-ONLY0-NEXT:    [[CONV233:%.*]] = zext i16 [[TMP108]] to i32
57337 // SIMD-ONLY0-NEXT:    br label [[COND_END234]]
57338 // SIMD-ONLY0:       cond.end234:
57339 // SIMD-ONLY0-NEXT:    [[COND235:%.*]] = phi i32 [ [[CONV231]], [[COND_TRUE230]] ], [ [[CONV233]], [[COND_FALSE232]] ]
57340 // SIMD-ONLY0-NEXT:    [[CONV236:%.*]] = trunc i32 [[COND235]] to i16
57341 // SIMD-ONLY0-NEXT:    store i16 [[CONV236]], ptr [[USX]], align 2
57342 // SIMD-ONLY0-NEXT:    [[TMP109:%.*]] = load i16, ptr [[USX]], align 2
57343 // SIMD-ONLY0-NEXT:    store i16 [[TMP109]], ptr [[USV]], align 2
57344 // SIMD-ONLY0-NEXT:    [[TMP110:%.*]] = load i16, ptr [[USX]], align 2
57345 // SIMD-ONLY0-NEXT:    [[CONV237:%.*]] = zext i16 [[TMP110]] to i32
57346 // SIMD-ONLY0-NEXT:    [[TMP111:%.*]] = load i16, ptr [[USE]], align 2
57347 // SIMD-ONLY0-NEXT:    [[CONV238:%.*]] = zext i16 [[TMP111]] to i32
57348 // SIMD-ONLY0-NEXT:    [[CMP239:%.*]] = icmp slt i32 [[CONV237]], [[CONV238]]
57349 // SIMD-ONLY0-NEXT:    br i1 [[CMP239]], label [[COND_TRUE241:%.*]], label [[COND_FALSE243:%.*]]
57350 // SIMD-ONLY0:       cond.true241:
57351 // SIMD-ONLY0-NEXT:    [[TMP112:%.*]] = load i16, ptr [[USE]], align 2
57352 // SIMD-ONLY0-NEXT:    [[CONV242:%.*]] = zext i16 [[TMP112]] to i32
57353 // SIMD-ONLY0-NEXT:    br label [[COND_END245:%.*]]
57354 // SIMD-ONLY0:       cond.false243:
57355 // SIMD-ONLY0-NEXT:    [[TMP113:%.*]] = load i16, ptr [[USX]], align 2
57356 // SIMD-ONLY0-NEXT:    [[CONV244:%.*]] = zext i16 [[TMP113]] to i32
57357 // SIMD-ONLY0-NEXT:    br label [[COND_END245]]
57358 // SIMD-ONLY0:       cond.end245:
57359 // SIMD-ONLY0-NEXT:    [[COND246:%.*]] = phi i32 [ [[CONV242]], [[COND_TRUE241]] ], [ [[CONV244]], [[COND_FALSE243]] ]
57360 // SIMD-ONLY0-NEXT:    [[CONV247:%.*]] = trunc i32 [[COND246]] to i16
57361 // SIMD-ONLY0-NEXT:    store i16 [[CONV247]], ptr [[USX]], align 2
57362 // SIMD-ONLY0-NEXT:    [[TMP114:%.*]] = load i16, ptr [[USX]], align 2
57363 // SIMD-ONLY0-NEXT:    store i16 [[TMP114]], ptr [[USV]], align 2
57364 // SIMD-ONLY0-NEXT:    [[TMP115:%.*]] = load i16, ptr [[USX]], align 2
57365 // SIMD-ONLY0-NEXT:    [[CONV248:%.*]] = zext i16 [[TMP115]] to i32
57366 // SIMD-ONLY0-NEXT:    [[TMP116:%.*]] = load i16, ptr [[USE]], align 2
57367 // SIMD-ONLY0-NEXT:    [[CONV249:%.*]] = zext i16 [[TMP116]] to i32
57368 // SIMD-ONLY0-NEXT:    [[CMP250:%.*]] = icmp eq i32 [[CONV248]], [[CONV249]]
57369 // SIMD-ONLY0-NEXT:    br i1 [[CMP250]], label [[COND_TRUE252:%.*]], label [[COND_FALSE254:%.*]]
57370 // SIMD-ONLY0:       cond.true252:
57371 // SIMD-ONLY0-NEXT:    [[TMP117:%.*]] = load i16, ptr [[USD]], align 2
57372 // SIMD-ONLY0-NEXT:    [[CONV253:%.*]] = zext i16 [[TMP117]] to i32
57373 // SIMD-ONLY0-NEXT:    br label [[COND_END256:%.*]]
57374 // SIMD-ONLY0:       cond.false254:
57375 // SIMD-ONLY0-NEXT:    [[TMP118:%.*]] = load i16, ptr [[USX]], align 2
57376 // SIMD-ONLY0-NEXT:    [[CONV255:%.*]] = zext i16 [[TMP118]] to i32
57377 // SIMD-ONLY0-NEXT:    br label [[COND_END256]]
57378 // SIMD-ONLY0:       cond.end256:
57379 // SIMD-ONLY0-NEXT:    [[COND257:%.*]] = phi i32 [ [[CONV253]], [[COND_TRUE252]] ], [ [[CONV255]], [[COND_FALSE254]] ]
57380 // SIMD-ONLY0-NEXT:    [[CONV258:%.*]] = trunc i32 [[COND257]] to i16
57381 // SIMD-ONLY0-NEXT:    store i16 [[CONV258]], ptr [[USX]], align 2
57382 // SIMD-ONLY0-NEXT:    [[TMP119:%.*]] = load i16, ptr [[USX]], align 2
57383 // SIMD-ONLY0-NEXT:    store i16 [[TMP119]], ptr [[USV]], align 2
57384 // SIMD-ONLY0-NEXT:    [[TMP120:%.*]] = load i16, ptr [[USX]], align 2
57385 // SIMD-ONLY0-NEXT:    store i16 [[TMP120]], ptr [[USV]], align 2
57386 // SIMD-ONLY0-NEXT:    [[TMP121:%.*]] = load i16, ptr [[USX]], align 2
57387 // SIMD-ONLY0-NEXT:    [[CONV259:%.*]] = zext i16 [[TMP121]] to i32
57388 // SIMD-ONLY0-NEXT:    [[TMP122:%.*]] = load i16, ptr [[USE]], align 2
57389 // SIMD-ONLY0-NEXT:    [[CONV260:%.*]] = zext i16 [[TMP122]] to i32
57390 // SIMD-ONLY0-NEXT:    [[CMP261:%.*]] = icmp sgt i32 [[CONV259]], [[CONV260]]
57391 // SIMD-ONLY0-NEXT:    br i1 [[CMP261]], label [[COND_TRUE263:%.*]], label [[COND_FALSE265:%.*]]
57392 // SIMD-ONLY0:       cond.true263:
57393 // SIMD-ONLY0-NEXT:    [[TMP123:%.*]] = load i16, ptr [[USE]], align 2
57394 // SIMD-ONLY0-NEXT:    [[CONV264:%.*]] = zext i16 [[TMP123]] to i32
57395 // SIMD-ONLY0-NEXT:    br label [[COND_END267:%.*]]
57396 // SIMD-ONLY0:       cond.false265:
57397 // SIMD-ONLY0-NEXT:    [[TMP124:%.*]] = load i16, ptr [[USX]], align 2
57398 // SIMD-ONLY0-NEXT:    [[CONV266:%.*]] = zext i16 [[TMP124]] to i32
57399 // SIMD-ONLY0-NEXT:    br label [[COND_END267]]
57400 // SIMD-ONLY0:       cond.end267:
57401 // SIMD-ONLY0-NEXT:    [[COND268:%.*]] = phi i32 [ [[CONV264]], [[COND_TRUE263]] ], [ [[CONV266]], [[COND_FALSE265]] ]
57402 // SIMD-ONLY0-NEXT:    [[CONV269:%.*]] = trunc i32 [[COND268]] to i16
57403 // SIMD-ONLY0-NEXT:    store i16 [[CONV269]], ptr [[USX]], align 2
57404 // SIMD-ONLY0-NEXT:    [[TMP125:%.*]] = load i16, ptr [[USX]], align 2
57405 // SIMD-ONLY0-NEXT:    store i16 [[TMP125]], ptr [[USV]], align 2
57406 // SIMD-ONLY0-NEXT:    [[TMP126:%.*]] = load i16, ptr [[USX]], align 2
57407 // SIMD-ONLY0-NEXT:    [[CONV270:%.*]] = zext i16 [[TMP126]] to i32
57408 // SIMD-ONLY0-NEXT:    [[TMP127:%.*]] = load i16, ptr [[USE]], align 2
57409 // SIMD-ONLY0-NEXT:    [[CONV271:%.*]] = zext i16 [[TMP127]] to i32
57410 // SIMD-ONLY0-NEXT:    [[CMP272:%.*]] = icmp slt i32 [[CONV270]], [[CONV271]]
57411 // SIMD-ONLY0-NEXT:    br i1 [[CMP272]], label [[COND_TRUE274:%.*]], label [[COND_FALSE276:%.*]]
57412 // SIMD-ONLY0:       cond.true274:
57413 // SIMD-ONLY0-NEXT:    [[TMP128:%.*]] = load i16, ptr [[USE]], align 2
57414 // SIMD-ONLY0-NEXT:    [[CONV275:%.*]] = zext i16 [[TMP128]] to i32
57415 // SIMD-ONLY0-NEXT:    br label [[COND_END278:%.*]]
57416 // SIMD-ONLY0:       cond.false276:
57417 // SIMD-ONLY0-NEXT:    [[TMP129:%.*]] = load i16, ptr [[USX]], align 2
57418 // SIMD-ONLY0-NEXT:    [[CONV277:%.*]] = zext i16 [[TMP129]] to i32
57419 // SIMD-ONLY0-NEXT:    br label [[COND_END278]]
57420 // SIMD-ONLY0:       cond.end278:
57421 // SIMD-ONLY0-NEXT:    [[COND279:%.*]] = phi i32 [ [[CONV275]], [[COND_TRUE274]] ], [ [[CONV277]], [[COND_FALSE276]] ]
57422 // SIMD-ONLY0-NEXT:    [[CONV280:%.*]] = trunc i32 [[COND279]] to i16
57423 // SIMD-ONLY0-NEXT:    store i16 [[CONV280]], ptr [[USX]], align 2
57424 // SIMD-ONLY0-NEXT:    [[TMP130:%.*]] = load i16, ptr [[USX]], align 2
57425 // SIMD-ONLY0-NEXT:    store i16 [[TMP130]], ptr [[USV]], align 2
57426 // SIMD-ONLY0-NEXT:    [[TMP131:%.*]] = load i16, ptr [[USX]], align 2
57427 // SIMD-ONLY0-NEXT:    [[CONV281:%.*]] = zext i16 [[TMP131]] to i32
57428 // SIMD-ONLY0-NEXT:    [[TMP132:%.*]] = load i16, ptr [[USE]], align 2
57429 // SIMD-ONLY0-NEXT:    [[CONV282:%.*]] = zext i16 [[TMP132]] to i32
57430 // SIMD-ONLY0-NEXT:    [[CMP283:%.*]] = icmp eq i32 [[CONV281]], [[CONV282]]
57431 // SIMD-ONLY0-NEXT:    br i1 [[CMP283]], label [[COND_TRUE285:%.*]], label [[COND_FALSE287:%.*]]
57432 // SIMD-ONLY0:       cond.true285:
57433 // SIMD-ONLY0-NEXT:    [[TMP133:%.*]] = load i16, ptr [[USD]], align 2
57434 // SIMD-ONLY0-NEXT:    [[CONV286:%.*]] = zext i16 [[TMP133]] to i32
57435 // SIMD-ONLY0-NEXT:    br label [[COND_END289:%.*]]
57436 // SIMD-ONLY0:       cond.false287:
57437 // SIMD-ONLY0-NEXT:    [[TMP134:%.*]] = load i16, ptr [[USX]], align 2
57438 // SIMD-ONLY0-NEXT:    [[CONV288:%.*]] = zext i16 [[TMP134]] to i32
57439 // SIMD-ONLY0-NEXT:    br label [[COND_END289]]
57440 // SIMD-ONLY0:       cond.end289:
57441 // SIMD-ONLY0-NEXT:    [[COND290:%.*]] = phi i32 [ [[CONV286]], [[COND_TRUE285]] ], [ [[CONV288]], [[COND_FALSE287]] ]
57442 // SIMD-ONLY0-NEXT:    [[CONV291:%.*]] = trunc i32 [[COND290]] to i16
57443 // SIMD-ONLY0-NEXT:    store i16 [[CONV291]], ptr [[USX]], align 2
57444 // SIMD-ONLY0-NEXT:    [[TMP135:%.*]] = load i16, ptr [[USX]], align 2
57445 // SIMD-ONLY0-NEXT:    [[CONV292:%.*]] = zext i16 [[TMP135]] to i32
57446 // SIMD-ONLY0-NEXT:    [[TMP136:%.*]] = load i16, ptr [[USE]], align 2
57447 // SIMD-ONLY0-NEXT:    [[CONV293:%.*]] = zext i16 [[TMP136]] to i32
57448 // SIMD-ONLY0-NEXT:    [[CMP294:%.*]] = icmp sgt i32 [[CONV292]], [[CONV293]]
57449 // SIMD-ONLY0-NEXT:    br i1 [[CMP294]], label [[COND_TRUE296:%.*]], label [[COND_FALSE298:%.*]]
57450 // SIMD-ONLY0:       cond.true296:
57451 // SIMD-ONLY0-NEXT:    [[TMP137:%.*]] = load i16, ptr [[USE]], align 2
57452 // SIMD-ONLY0-NEXT:    [[CONV297:%.*]] = zext i16 [[TMP137]] to i32
57453 // SIMD-ONLY0-NEXT:    br label [[COND_END300:%.*]]
57454 // SIMD-ONLY0:       cond.false298:
57455 // SIMD-ONLY0-NEXT:    [[TMP138:%.*]] = load i16, ptr [[USX]], align 2
57456 // SIMD-ONLY0-NEXT:    [[CONV299:%.*]] = zext i16 [[TMP138]] to i32
57457 // SIMD-ONLY0-NEXT:    br label [[COND_END300]]
57458 // SIMD-ONLY0:       cond.end300:
57459 // SIMD-ONLY0-NEXT:    [[COND301:%.*]] = phi i32 [ [[CONV297]], [[COND_TRUE296]] ], [ [[CONV299]], [[COND_FALSE298]] ]
57460 // SIMD-ONLY0-NEXT:    [[CONV302:%.*]] = trunc i32 [[COND301]] to i16
57461 // SIMD-ONLY0-NEXT:    store i16 [[CONV302]], ptr [[USX]], align 2
57462 // SIMD-ONLY0-NEXT:    [[TMP139:%.*]] = load i16, ptr [[USX]], align 2
57463 // SIMD-ONLY0-NEXT:    store i16 [[TMP139]], ptr [[USV]], align 2
57464 // SIMD-ONLY0-NEXT:    [[TMP140:%.*]] = load i16, ptr [[USX]], align 2
57465 // SIMD-ONLY0-NEXT:    [[CONV303:%.*]] = zext i16 [[TMP140]] to i32
57466 // SIMD-ONLY0-NEXT:    [[TMP141:%.*]] = load i16, ptr [[USE]], align 2
57467 // SIMD-ONLY0-NEXT:    [[CONV304:%.*]] = zext i16 [[TMP141]] to i32
57468 // SIMD-ONLY0-NEXT:    [[CMP305:%.*]] = icmp slt i32 [[CONV303]], [[CONV304]]
57469 // SIMD-ONLY0-NEXT:    br i1 [[CMP305]], label [[COND_TRUE307:%.*]], label [[COND_FALSE309:%.*]]
57470 // SIMD-ONLY0:       cond.true307:
57471 // SIMD-ONLY0-NEXT:    [[TMP142:%.*]] = load i16, ptr [[USE]], align 2
57472 // SIMD-ONLY0-NEXT:    [[CONV308:%.*]] = zext i16 [[TMP142]] to i32
57473 // SIMD-ONLY0-NEXT:    br label [[COND_END311:%.*]]
57474 // SIMD-ONLY0:       cond.false309:
57475 // SIMD-ONLY0-NEXT:    [[TMP143:%.*]] = load i16, ptr [[USX]], align 2
57476 // SIMD-ONLY0-NEXT:    [[CONV310:%.*]] = zext i16 [[TMP143]] to i32
57477 // SIMD-ONLY0-NEXT:    br label [[COND_END311]]
57478 // SIMD-ONLY0:       cond.end311:
57479 // SIMD-ONLY0-NEXT:    [[COND312:%.*]] = phi i32 [ [[CONV308]], [[COND_TRUE307]] ], [ [[CONV310]], [[COND_FALSE309]] ]
57480 // SIMD-ONLY0-NEXT:    [[CONV313:%.*]] = trunc i32 [[COND312]] to i16
57481 // SIMD-ONLY0-NEXT:    store i16 [[CONV313]], ptr [[USX]], align 2
57482 // SIMD-ONLY0-NEXT:    [[TMP144:%.*]] = load i16, ptr [[USX]], align 2
57483 // SIMD-ONLY0-NEXT:    store i16 [[TMP144]], ptr [[USV]], align 2
57484 // SIMD-ONLY0-NEXT:    [[TMP145:%.*]] = load i16, ptr [[USX]], align 2
57485 // SIMD-ONLY0-NEXT:    [[CONV314:%.*]] = zext i16 [[TMP145]] to i32
57486 // SIMD-ONLY0-NEXT:    [[TMP146:%.*]] = load i16, ptr [[USE]], align 2
57487 // SIMD-ONLY0-NEXT:    [[CONV315:%.*]] = zext i16 [[TMP146]] to i32
57488 // SIMD-ONLY0-NEXT:    [[CMP316:%.*]] = icmp eq i32 [[CONV314]], [[CONV315]]
57489 // SIMD-ONLY0-NEXT:    br i1 [[CMP316]], label [[COND_TRUE318:%.*]], label [[COND_FALSE320:%.*]]
57490 // SIMD-ONLY0:       cond.true318:
57491 // SIMD-ONLY0-NEXT:    [[TMP147:%.*]] = load i16, ptr [[USD]], align 2
57492 // SIMD-ONLY0-NEXT:    [[CONV319:%.*]] = zext i16 [[TMP147]] to i32
57493 // SIMD-ONLY0-NEXT:    br label [[COND_END322:%.*]]
57494 // SIMD-ONLY0:       cond.false320:
57495 // SIMD-ONLY0-NEXT:    [[TMP148:%.*]] = load i16, ptr [[USX]], align 2
57496 // SIMD-ONLY0-NEXT:    [[CONV321:%.*]] = zext i16 [[TMP148]] to i32
57497 // SIMD-ONLY0-NEXT:    br label [[COND_END322]]
57498 // SIMD-ONLY0:       cond.end322:
57499 // SIMD-ONLY0-NEXT:    [[COND323:%.*]] = phi i32 [ [[CONV319]], [[COND_TRUE318]] ], [ [[CONV321]], [[COND_FALSE320]] ]
57500 // SIMD-ONLY0-NEXT:    [[CONV324:%.*]] = trunc i32 [[COND323]] to i16
57501 // SIMD-ONLY0-NEXT:    store i16 [[CONV324]], ptr [[USX]], align 2
57502 // SIMD-ONLY0-NEXT:    [[TMP149:%.*]] = load i16, ptr [[USX]], align 2
57503 // SIMD-ONLY0-NEXT:    store i16 [[TMP149]], ptr [[USV]], align 2
57504 // SIMD-ONLY0-NEXT:    [[TMP150:%.*]] = load i16, ptr [[USX]], align 2
57505 // SIMD-ONLY0-NEXT:    store i16 [[TMP150]], ptr [[USV]], align 2
57506 // SIMD-ONLY0-NEXT:    [[TMP151:%.*]] = load i16, ptr [[USX]], align 2
57507 // SIMD-ONLY0-NEXT:    [[CONV325:%.*]] = zext i16 [[TMP151]] to i32
57508 // SIMD-ONLY0-NEXT:    [[TMP152:%.*]] = load i16, ptr [[USE]], align 2
57509 // SIMD-ONLY0-NEXT:    [[CONV326:%.*]] = zext i16 [[TMP152]] to i32
57510 // SIMD-ONLY0-NEXT:    [[CMP327:%.*]] = icmp sgt i32 [[CONV325]], [[CONV326]]
57511 // SIMD-ONLY0-NEXT:    br i1 [[CMP327]], label [[COND_TRUE329:%.*]], label [[COND_FALSE331:%.*]]
57512 // SIMD-ONLY0:       cond.true329:
57513 // SIMD-ONLY0-NEXT:    [[TMP153:%.*]] = load i16, ptr [[USE]], align 2
57514 // SIMD-ONLY0-NEXT:    [[CONV330:%.*]] = zext i16 [[TMP153]] to i32
57515 // SIMD-ONLY0-NEXT:    br label [[COND_END333:%.*]]
57516 // SIMD-ONLY0:       cond.false331:
57517 // SIMD-ONLY0-NEXT:    [[TMP154:%.*]] = load i16, ptr [[USX]], align 2
57518 // SIMD-ONLY0-NEXT:    [[CONV332:%.*]] = zext i16 [[TMP154]] to i32
57519 // SIMD-ONLY0-NEXT:    br label [[COND_END333]]
57520 // SIMD-ONLY0:       cond.end333:
57521 // SIMD-ONLY0-NEXT:    [[COND334:%.*]] = phi i32 [ [[CONV330]], [[COND_TRUE329]] ], [ [[CONV332]], [[COND_FALSE331]] ]
57522 // SIMD-ONLY0-NEXT:    [[CONV335:%.*]] = trunc i32 [[COND334]] to i16
57523 // SIMD-ONLY0-NEXT:    store i16 [[CONV335]], ptr [[USX]], align 2
57524 // SIMD-ONLY0-NEXT:    [[TMP155:%.*]] = load i16, ptr [[USX]], align 2
57525 // SIMD-ONLY0-NEXT:    store i16 [[TMP155]], ptr [[USV]], align 2
57526 // SIMD-ONLY0-NEXT:    [[TMP156:%.*]] = load i16, ptr [[USX]], align 2
57527 // SIMD-ONLY0-NEXT:    [[CONV336:%.*]] = zext i16 [[TMP156]] to i32
57528 // SIMD-ONLY0-NEXT:    [[TMP157:%.*]] = load i16, ptr [[USE]], align 2
57529 // SIMD-ONLY0-NEXT:    [[CONV337:%.*]] = zext i16 [[TMP157]] to i32
57530 // SIMD-ONLY0-NEXT:    [[CMP338:%.*]] = icmp slt i32 [[CONV336]], [[CONV337]]
57531 // SIMD-ONLY0-NEXT:    br i1 [[CMP338]], label [[COND_TRUE340:%.*]], label [[COND_FALSE342:%.*]]
57532 // SIMD-ONLY0:       cond.true340:
57533 // SIMD-ONLY0-NEXT:    [[TMP158:%.*]] = load i16, ptr [[USE]], align 2
57534 // SIMD-ONLY0-NEXT:    [[CONV341:%.*]] = zext i16 [[TMP158]] to i32
57535 // SIMD-ONLY0-NEXT:    br label [[COND_END344:%.*]]
57536 // SIMD-ONLY0:       cond.false342:
57537 // SIMD-ONLY0-NEXT:    [[TMP159:%.*]] = load i16, ptr [[USX]], align 2
57538 // SIMD-ONLY0-NEXT:    [[CONV343:%.*]] = zext i16 [[TMP159]] to i32
57539 // SIMD-ONLY0-NEXT:    br label [[COND_END344]]
57540 // SIMD-ONLY0:       cond.end344:
57541 // SIMD-ONLY0-NEXT:    [[COND345:%.*]] = phi i32 [ [[CONV341]], [[COND_TRUE340]] ], [ [[CONV343]], [[COND_FALSE342]] ]
57542 // SIMD-ONLY0-NEXT:    [[CONV346:%.*]] = trunc i32 [[COND345]] to i16
57543 // SIMD-ONLY0-NEXT:    store i16 [[CONV346]], ptr [[USX]], align 2
57544 // SIMD-ONLY0-NEXT:    [[TMP160:%.*]] = load i16, ptr [[USX]], align 2
57545 // SIMD-ONLY0-NEXT:    store i16 [[TMP160]], ptr [[USV]], align 2
57546 // SIMD-ONLY0-NEXT:    [[TMP161:%.*]] = load i16, ptr [[USX]], align 2
57547 // SIMD-ONLY0-NEXT:    [[CONV347:%.*]] = zext i16 [[TMP161]] to i32
57548 // SIMD-ONLY0-NEXT:    [[TMP162:%.*]] = load i16, ptr [[USE]], align 2
57549 // SIMD-ONLY0-NEXT:    [[CONV348:%.*]] = zext i16 [[TMP162]] to i32
57550 // SIMD-ONLY0-NEXT:    [[CMP349:%.*]] = icmp eq i32 [[CONV347]], [[CONV348]]
57551 // SIMD-ONLY0-NEXT:    br i1 [[CMP349]], label [[COND_TRUE351:%.*]], label [[COND_FALSE353:%.*]]
57552 // SIMD-ONLY0:       cond.true351:
57553 // SIMD-ONLY0-NEXT:    [[TMP163:%.*]] = load i16, ptr [[USD]], align 2
57554 // SIMD-ONLY0-NEXT:    [[CONV352:%.*]] = zext i16 [[TMP163]] to i32
57555 // SIMD-ONLY0-NEXT:    br label [[COND_END355:%.*]]
57556 // SIMD-ONLY0:       cond.false353:
57557 // SIMD-ONLY0-NEXT:    [[TMP164:%.*]] = load i16, ptr [[USX]], align 2
57558 // SIMD-ONLY0-NEXT:    [[CONV354:%.*]] = zext i16 [[TMP164]] to i32
57559 // SIMD-ONLY0-NEXT:    br label [[COND_END355]]
57560 // SIMD-ONLY0:       cond.end355:
57561 // SIMD-ONLY0-NEXT:    [[COND356:%.*]] = phi i32 [ [[CONV352]], [[COND_TRUE351]] ], [ [[CONV354]], [[COND_FALSE353]] ]
57562 // SIMD-ONLY0-NEXT:    [[CONV357:%.*]] = trunc i32 [[COND356]] to i16
57563 // SIMD-ONLY0-NEXT:    store i16 [[CONV357]], ptr [[USX]], align 2
57564 // SIMD-ONLY0-NEXT:    [[TMP165:%.*]] = load i16, ptr [[USX]], align 2
57565 // SIMD-ONLY0-NEXT:    [[CONV358:%.*]] = zext i16 [[TMP165]] to i32
57566 // SIMD-ONLY0-NEXT:    [[TMP166:%.*]] = load i16, ptr [[USE]], align 2
57567 // SIMD-ONLY0-NEXT:    [[CONV359:%.*]] = zext i16 [[TMP166]] to i32
57568 // SIMD-ONLY0-NEXT:    [[CMP360:%.*]] = icmp sgt i32 [[CONV358]], [[CONV359]]
57569 // SIMD-ONLY0-NEXT:    br i1 [[CMP360]], label [[COND_TRUE362:%.*]], label [[COND_FALSE364:%.*]]
57570 // SIMD-ONLY0:       cond.true362:
57571 // SIMD-ONLY0-NEXT:    [[TMP167:%.*]] = load i16, ptr [[USE]], align 2
57572 // SIMD-ONLY0-NEXT:    [[CONV363:%.*]] = zext i16 [[TMP167]] to i32
57573 // SIMD-ONLY0-NEXT:    br label [[COND_END366:%.*]]
57574 // SIMD-ONLY0:       cond.false364:
57575 // SIMD-ONLY0-NEXT:    [[TMP168:%.*]] = load i16, ptr [[USX]], align 2
57576 // SIMD-ONLY0-NEXT:    [[CONV365:%.*]] = zext i16 [[TMP168]] to i32
57577 // SIMD-ONLY0-NEXT:    br label [[COND_END366]]
57578 // SIMD-ONLY0:       cond.end366:
57579 // SIMD-ONLY0-NEXT:    [[COND367:%.*]] = phi i32 [ [[CONV363]], [[COND_TRUE362]] ], [ [[CONV365]], [[COND_FALSE364]] ]
57580 // SIMD-ONLY0-NEXT:    [[CONV368:%.*]] = trunc i32 [[COND367]] to i16
57581 // SIMD-ONLY0-NEXT:    store i16 [[CONV368]], ptr [[USX]], align 2
57582 // SIMD-ONLY0-NEXT:    [[TMP169:%.*]] = load i16, ptr [[USX]], align 2
57583 // SIMD-ONLY0-NEXT:    store i16 [[TMP169]], ptr [[USV]], align 2
57584 // SIMD-ONLY0-NEXT:    [[TMP170:%.*]] = load i16, ptr [[USX]], align 2
57585 // SIMD-ONLY0-NEXT:    [[CONV369:%.*]] = zext i16 [[TMP170]] to i32
57586 // SIMD-ONLY0-NEXT:    [[TMP171:%.*]] = load i16, ptr [[USE]], align 2
57587 // SIMD-ONLY0-NEXT:    [[CONV370:%.*]] = zext i16 [[TMP171]] to i32
57588 // SIMD-ONLY0-NEXT:    [[CMP371:%.*]] = icmp slt i32 [[CONV369]], [[CONV370]]
57589 // SIMD-ONLY0-NEXT:    br i1 [[CMP371]], label [[COND_TRUE373:%.*]], label [[COND_FALSE375:%.*]]
57590 // SIMD-ONLY0:       cond.true373:
57591 // SIMD-ONLY0-NEXT:    [[TMP172:%.*]] = load i16, ptr [[USE]], align 2
57592 // SIMD-ONLY0-NEXT:    [[CONV374:%.*]] = zext i16 [[TMP172]] to i32
57593 // SIMD-ONLY0-NEXT:    br label [[COND_END377:%.*]]
57594 // SIMD-ONLY0:       cond.false375:
57595 // SIMD-ONLY0-NEXT:    [[TMP173:%.*]] = load i16, ptr [[USX]], align 2
57596 // SIMD-ONLY0-NEXT:    [[CONV376:%.*]] = zext i16 [[TMP173]] to i32
57597 // SIMD-ONLY0-NEXT:    br label [[COND_END377]]
57598 // SIMD-ONLY0:       cond.end377:
57599 // SIMD-ONLY0-NEXT:    [[COND378:%.*]] = phi i32 [ [[CONV374]], [[COND_TRUE373]] ], [ [[CONV376]], [[COND_FALSE375]] ]
57600 // SIMD-ONLY0-NEXT:    [[CONV379:%.*]] = trunc i32 [[COND378]] to i16
57601 // SIMD-ONLY0-NEXT:    store i16 [[CONV379]], ptr [[USX]], align 2
57602 // SIMD-ONLY0-NEXT:    [[TMP174:%.*]] = load i16, ptr [[USX]], align 2
57603 // SIMD-ONLY0-NEXT:    store i16 [[TMP174]], ptr [[USV]], align 2
57604 // SIMD-ONLY0-NEXT:    [[TMP175:%.*]] = load i16, ptr [[USX]], align 2
57605 // SIMD-ONLY0-NEXT:    [[CONV380:%.*]] = zext i16 [[TMP175]] to i32
57606 // SIMD-ONLY0-NEXT:    [[TMP176:%.*]] = load i16, ptr [[USE]], align 2
57607 // SIMD-ONLY0-NEXT:    [[CONV381:%.*]] = zext i16 [[TMP176]] to i32
57608 // SIMD-ONLY0-NEXT:    [[CMP382:%.*]] = icmp eq i32 [[CONV380]], [[CONV381]]
57609 // SIMD-ONLY0-NEXT:    br i1 [[CMP382]], label [[COND_TRUE384:%.*]], label [[COND_FALSE386:%.*]]
57610 // SIMD-ONLY0:       cond.true384:
57611 // SIMD-ONLY0-NEXT:    [[TMP177:%.*]] = load i16, ptr [[USD]], align 2
57612 // SIMD-ONLY0-NEXT:    [[CONV385:%.*]] = zext i16 [[TMP177]] to i32
57613 // SIMD-ONLY0-NEXT:    br label [[COND_END388:%.*]]
57614 // SIMD-ONLY0:       cond.false386:
57615 // SIMD-ONLY0-NEXT:    [[TMP178:%.*]] = load i16, ptr [[USX]], align 2
57616 // SIMD-ONLY0-NEXT:    [[CONV387:%.*]] = zext i16 [[TMP178]] to i32
57617 // SIMD-ONLY0-NEXT:    br label [[COND_END388]]
57618 // SIMD-ONLY0:       cond.end388:
57619 // SIMD-ONLY0-NEXT:    [[COND389:%.*]] = phi i32 [ [[CONV385]], [[COND_TRUE384]] ], [ [[CONV387]], [[COND_FALSE386]] ]
57620 // SIMD-ONLY0-NEXT:    [[CONV390:%.*]] = trunc i32 [[COND389]] to i16
57621 // SIMD-ONLY0-NEXT:    store i16 [[CONV390]], ptr [[USX]], align 2
57622 // SIMD-ONLY0-NEXT:    [[TMP179:%.*]] = load i16, ptr [[USX]], align 2
57623 // SIMD-ONLY0-NEXT:    store i16 [[TMP179]], ptr [[USV]], align 2
57624 // SIMD-ONLY0-NEXT:    [[TMP180:%.*]] = load i16, ptr [[USV]], align 2
57625 // SIMD-ONLY0-NEXT:    ret i16 [[TMP180]]
57626 //
57627 //
57628 // SIMD-ONLY0-LABEL: @ixevd(
57629 // SIMD-ONLY0-NEXT:  entry:
57630 // SIMD-ONLY0-NEXT:    [[IX:%.*]] = alloca i32, align 4
57631 // SIMD-ONLY0-NEXT:    [[IV:%.*]] = alloca i32, align 4
57632 // SIMD-ONLY0-NEXT:    [[IE:%.*]] = alloca i32, align 4
57633 // SIMD-ONLY0-NEXT:    [[ID:%.*]] = alloca i32, align 4
57634 // SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = load i32, ptr [[IX]], align 4
57635 // SIMD-ONLY0-NEXT:    store i32 [[TMP0]], ptr [[IV]], align 4
57636 // SIMD-ONLY0-NEXT:    [[TMP1:%.*]] = load i32, ptr [[IX]], align 4
57637 // SIMD-ONLY0-NEXT:    [[TMP2:%.*]] = load i32, ptr [[IE]], align 4
57638 // SIMD-ONLY0-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP1]], [[TMP2]]
57639 // SIMD-ONLY0-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
57640 // SIMD-ONLY0:       cond.true:
57641 // SIMD-ONLY0-NEXT:    [[TMP3:%.*]] = load i32, ptr [[IE]], align 4
57642 // SIMD-ONLY0-NEXT:    br label [[COND_END:%.*]]
57643 // SIMD-ONLY0:       cond.false:
57644 // SIMD-ONLY0-NEXT:    [[TMP4:%.*]] = load i32, ptr [[IX]], align 4
57645 // SIMD-ONLY0-NEXT:    br label [[COND_END]]
57646 // SIMD-ONLY0:       cond.end:
57647 // SIMD-ONLY0-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP3]], [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
57648 // SIMD-ONLY0-NEXT:    store i32 [[COND]], ptr [[IX]], align 4
57649 // SIMD-ONLY0-NEXT:    [[TMP5:%.*]] = load i32, ptr [[IX]], align 4
57650 // SIMD-ONLY0-NEXT:    store i32 [[TMP5]], ptr [[IV]], align 4
57651 // SIMD-ONLY0-NEXT:    [[TMP6:%.*]] = load i32, ptr [[IX]], align 4
57652 // SIMD-ONLY0-NEXT:    [[TMP7:%.*]] = load i32, ptr [[IE]], align 4
57653 // SIMD-ONLY0-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
57654 // SIMD-ONLY0-NEXT:    br i1 [[CMP1]], label [[COND_TRUE2:%.*]], label [[COND_FALSE3:%.*]]
57655 // SIMD-ONLY0:       cond.true2:
57656 // SIMD-ONLY0-NEXT:    [[TMP8:%.*]] = load i32, ptr [[IE]], align 4
57657 // SIMD-ONLY0-NEXT:    br label [[COND_END4:%.*]]
57658 // SIMD-ONLY0:       cond.false3:
57659 // SIMD-ONLY0-NEXT:    [[TMP9:%.*]] = load i32, ptr [[IX]], align 4
57660 // SIMD-ONLY0-NEXT:    br label [[COND_END4]]
57661 // SIMD-ONLY0:       cond.end4:
57662 // SIMD-ONLY0-NEXT:    [[COND5:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE2]] ], [ [[TMP9]], [[COND_FALSE3]] ]
57663 // SIMD-ONLY0-NEXT:    store i32 [[COND5]], ptr [[IX]], align 4
57664 // SIMD-ONLY0-NEXT:    [[TMP10:%.*]] = load i32, ptr [[IX]], align 4
57665 // SIMD-ONLY0-NEXT:    store i32 [[TMP10]], ptr [[IV]], align 4
57666 // SIMD-ONLY0-NEXT:    [[TMP11:%.*]] = load i32, ptr [[IX]], align 4
57667 // SIMD-ONLY0-NEXT:    [[TMP12:%.*]] = load i32, ptr [[IE]], align 4
57668 // SIMD-ONLY0-NEXT:    [[CMP6:%.*]] = icmp eq i32 [[TMP11]], [[TMP12]]
57669 // SIMD-ONLY0-NEXT:    br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
57670 // SIMD-ONLY0:       cond.true7:
57671 // SIMD-ONLY0-NEXT:    [[TMP13:%.*]] = load i32, ptr [[ID]], align 4
57672 // SIMD-ONLY0-NEXT:    br label [[COND_END9:%.*]]
57673 // SIMD-ONLY0:       cond.false8:
57674 // SIMD-ONLY0-NEXT:    [[TMP14:%.*]] = load i32, ptr [[IX]], align 4
57675 // SIMD-ONLY0-NEXT:    br label [[COND_END9]]
57676 // SIMD-ONLY0:       cond.end9:
57677 // SIMD-ONLY0-NEXT:    [[COND10:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE7]] ], [ [[TMP14]], [[COND_FALSE8]] ]
57678 // SIMD-ONLY0-NEXT:    store i32 [[COND10]], ptr [[IX]], align 4
57679 // SIMD-ONLY0-NEXT:    [[TMP15:%.*]] = load i32, ptr [[IX]], align 4
57680 // SIMD-ONLY0-NEXT:    [[TMP16:%.*]] = load i32, ptr [[IE]], align 4
57681 // SIMD-ONLY0-NEXT:    [[CMP11:%.*]] = icmp sgt i32 [[TMP15]], [[TMP16]]
57682 // SIMD-ONLY0-NEXT:    br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
57683 // SIMD-ONLY0:       cond.true12:
57684 // SIMD-ONLY0-NEXT:    [[TMP17:%.*]] = load i32, ptr [[IE]], align 4
57685 // SIMD-ONLY0-NEXT:    br label [[COND_END14:%.*]]
57686 // SIMD-ONLY0:       cond.false13:
57687 // SIMD-ONLY0-NEXT:    [[TMP18:%.*]] = load i32, ptr [[IX]], align 4
57688 // SIMD-ONLY0-NEXT:    br label [[COND_END14]]
57689 // SIMD-ONLY0:       cond.end14:
57690 // SIMD-ONLY0-NEXT:    [[COND15:%.*]] = phi i32 [ [[TMP17]], [[COND_TRUE12]] ], [ [[TMP18]], [[COND_FALSE13]] ]
57691 // SIMD-ONLY0-NEXT:    store i32 [[COND15]], ptr [[IX]], align 4
57692 // SIMD-ONLY0-NEXT:    [[TMP19:%.*]] = load i32, ptr [[IX]], align 4
57693 // SIMD-ONLY0-NEXT:    store i32 [[TMP19]], ptr [[IV]], align 4
57694 // SIMD-ONLY0-NEXT:    [[TMP20:%.*]] = load i32, ptr [[IX]], align 4
57695 // SIMD-ONLY0-NEXT:    [[TMP21:%.*]] = load i32, ptr [[IE]], align 4
57696 // SIMD-ONLY0-NEXT:    [[CMP16:%.*]] = icmp slt i32 [[TMP20]], [[TMP21]]
57697 // SIMD-ONLY0-NEXT:    br i1 [[CMP16]], label [[COND_TRUE17:%.*]], label [[COND_FALSE18:%.*]]
57698 // SIMD-ONLY0:       cond.true17:
57699 // SIMD-ONLY0-NEXT:    [[TMP22:%.*]] = load i32, ptr [[IE]], align 4
57700 // SIMD-ONLY0-NEXT:    br label [[COND_END19:%.*]]
57701 // SIMD-ONLY0:       cond.false18:
57702 // SIMD-ONLY0-NEXT:    [[TMP23:%.*]] = load i32, ptr [[IX]], align 4
57703 // SIMD-ONLY0-NEXT:    br label [[COND_END19]]
57704 // SIMD-ONLY0:       cond.end19:
57705 // SIMD-ONLY0-NEXT:    [[COND20:%.*]] = phi i32 [ [[TMP22]], [[COND_TRUE17]] ], [ [[TMP23]], [[COND_FALSE18]] ]
57706 // SIMD-ONLY0-NEXT:    store i32 [[COND20]], ptr [[IX]], align 4
57707 // SIMD-ONLY0-NEXT:    [[TMP24:%.*]] = load i32, ptr [[IX]], align 4
57708 // SIMD-ONLY0-NEXT:    store i32 [[TMP24]], ptr [[IV]], align 4
57709 // SIMD-ONLY0-NEXT:    [[TMP25:%.*]] = load i32, ptr [[IX]], align 4
57710 // SIMD-ONLY0-NEXT:    [[TMP26:%.*]] = load i32, ptr [[IE]], align 4
57711 // SIMD-ONLY0-NEXT:    [[CMP21:%.*]] = icmp eq i32 [[TMP25]], [[TMP26]]
57712 // SIMD-ONLY0-NEXT:    br i1 [[CMP21]], label [[COND_TRUE22:%.*]], label [[COND_FALSE23:%.*]]
57713 // SIMD-ONLY0:       cond.true22:
57714 // SIMD-ONLY0-NEXT:    [[TMP27:%.*]] = load i32, ptr [[ID]], align 4
57715 // SIMD-ONLY0-NEXT:    br label [[COND_END24:%.*]]
57716 // SIMD-ONLY0:       cond.false23:
57717 // SIMD-ONLY0-NEXT:    [[TMP28:%.*]] = load i32, ptr [[IX]], align 4
57718 // SIMD-ONLY0-NEXT:    br label [[COND_END24]]
57719 // SIMD-ONLY0:       cond.end24:
57720 // SIMD-ONLY0-NEXT:    [[COND25:%.*]] = phi i32 [ [[TMP27]], [[COND_TRUE22]] ], [ [[TMP28]], [[COND_FALSE23]] ]
57721 // SIMD-ONLY0-NEXT:    store i32 [[COND25]], ptr [[IX]], align 4
57722 // SIMD-ONLY0-NEXT:    [[TMP29:%.*]] = load i32, ptr [[IX]], align 4
57723 // SIMD-ONLY0-NEXT:    store i32 [[TMP29]], ptr [[IV]], align 4
57724 // SIMD-ONLY0-NEXT:    [[TMP30:%.*]] = load i32, ptr [[IX]], align 4
57725 // SIMD-ONLY0-NEXT:    store i32 [[TMP30]], ptr [[IV]], align 4
57726 // SIMD-ONLY0-NEXT:    [[TMP31:%.*]] = load i32, ptr [[IX]], align 4
57727 // SIMD-ONLY0-NEXT:    [[TMP32:%.*]] = load i32, ptr [[IE]], align 4
57728 // SIMD-ONLY0-NEXT:    [[CMP26:%.*]] = icmp sgt i32 [[TMP31]], [[TMP32]]
57729 // SIMD-ONLY0-NEXT:    br i1 [[CMP26]], label [[COND_TRUE27:%.*]], label [[COND_FALSE28:%.*]]
57730 // SIMD-ONLY0:       cond.true27:
57731 // SIMD-ONLY0-NEXT:    [[TMP33:%.*]] = load i32, ptr [[IE]], align 4
57732 // SIMD-ONLY0-NEXT:    br label [[COND_END29:%.*]]
57733 // SIMD-ONLY0:       cond.false28:
57734 // SIMD-ONLY0-NEXT:    [[TMP34:%.*]] = load i32, ptr [[IX]], align 4
57735 // SIMD-ONLY0-NEXT:    br label [[COND_END29]]
57736 // SIMD-ONLY0:       cond.end29:
57737 // SIMD-ONLY0-NEXT:    [[COND30:%.*]] = phi i32 [ [[TMP33]], [[COND_TRUE27]] ], [ [[TMP34]], [[COND_FALSE28]] ]
57738 // SIMD-ONLY0-NEXT:    store i32 [[COND30]], ptr [[IX]], align 4
57739 // SIMD-ONLY0-NEXT:    [[TMP35:%.*]] = load i32, ptr [[IX]], align 4
57740 // SIMD-ONLY0-NEXT:    store i32 [[TMP35]], ptr [[IV]], align 4
57741 // SIMD-ONLY0-NEXT:    [[TMP36:%.*]] = load i32, ptr [[IX]], align 4
57742 // SIMD-ONLY0-NEXT:    [[TMP37:%.*]] = load i32, ptr [[IE]], align 4
57743 // SIMD-ONLY0-NEXT:    [[CMP31:%.*]] = icmp slt i32 [[TMP36]], [[TMP37]]
57744 // SIMD-ONLY0-NEXT:    br i1 [[CMP31]], label [[COND_TRUE32:%.*]], label [[COND_FALSE33:%.*]]
57745 // SIMD-ONLY0:       cond.true32:
57746 // SIMD-ONLY0-NEXT:    [[TMP38:%.*]] = load i32, ptr [[IE]], align 4
57747 // SIMD-ONLY0-NEXT:    br label [[COND_END34:%.*]]
57748 // SIMD-ONLY0:       cond.false33:
57749 // SIMD-ONLY0-NEXT:    [[TMP39:%.*]] = load i32, ptr [[IX]], align 4
57750 // SIMD-ONLY0-NEXT:    br label [[COND_END34]]
57751 // SIMD-ONLY0:       cond.end34:
57752 // SIMD-ONLY0-NEXT:    [[COND35:%.*]] = phi i32 [ [[TMP38]], [[COND_TRUE32]] ], [ [[TMP39]], [[COND_FALSE33]] ]
57753 // SIMD-ONLY0-NEXT:    store i32 [[COND35]], ptr [[IX]], align 4
57754 // SIMD-ONLY0-NEXT:    [[TMP40:%.*]] = load i32, ptr [[IX]], align 4
57755 // SIMD-ONLY0-NEXT:    store i32 [[TMP40]], ptr [[IV]], align 4
57756 // SIMD-ONLY0-NEXT:    [[TMP41:%.*]] = load i32, ptr [[IX]], align 4
57757 // SIMD-ONLY0-NEXT:    [[TMP42:%.*]] = load i32, ptr [[IE]], align 4
57758 // SIMD-ONLY0-NEXT:    [[CMP36:%.*]] = icmp eq i32 [[TMP41]], [[TMP42]]
57759 // SIMD-ONLY0-NEXT:    br i1 [[CMP36]], label [[COND_TRUE37:%.*]], label [[COND_FALSE38:%.*]]
57760 // SIMD-ONLY0:       cond.true37:
57761 // SIMD-ONLY0-NEXT:    [[TMP43:%.*]] = load i32, ptr [[ID]], align 4
57762 // SIMD-ONLY0-NEXT:    br label [[COND_END39:%.*]]
57763 // SIMD-ONLY0:       cond.false38:
57764 // SIMD-ONLY0-NEXT:    [[TMP44:%.*]] = load i32, ptr [[IX]], align 4
57765 // SIMD-ONLY0-NEXT:    br label [[COND_END39]]
57766 // SIMD-ONLY0:       cond.end39:
57767 // SIMD-ONLY0-NEXT:    [[COND40:%.*]] = phi i32 [ [[TMP43]], [[COND_TRUE37]] ], [ [[TMP44]], [[COND_FALSE38]] ]
57768 // SIMD-ONLY0-NEXT:    store i32 [[COND40]], ptr [[IX]], align 4
57769 // SIMD-ONLY0-NEXT:    [[TMP45:%.*]] = load i32, ptr [[IX]], align 4
57770 // SIMD-ONLY0-NEXT:    [[TMP46:%.*]] = load i32, ptr [[IE]], align 4
57771 // SIMD-ONLY0-NEXT:    [[CMP41:%.*]] = icmp sgt i32 [[TMP45]], [[TMP46]]
57772 // SIMD-ONLY0-NEXT:    br i1 [[CMP41]], label [[COND_TRUE42:%.*]], label [[COND_FALSE43:%.*]]
57773 // SIMD-ONLY0:       cond.true42:
57774 // SIMD-ONLY0-NEXT:    [[TMP47:%.*]] = load i32, ptr [[IE]], align 4
57775 // SIMD-ONLY0-NEXT:    br label [[COND_END44:%.*]]
57776 // SIMD-ONLY0:       cond.false43:
57777 // SIMD-ONLY0-NEXT:    [[TMP48:%.*]] = load i32, ptr [[IX]], align 4
57778 // SIMD-ONLY0-NEXT:    br label [[COND_END44]]
57779 // SIMD-ONLY0:       cond.end44:
57780 // SIMD-ONLY0-NEXT:    [[COND45:%.*]] = phi i32 [ [[TMP47]], [[COND_TRUE42]] ], [ [[TMP48]], [[COND_FALSE43]] ]
57781 // SIMD-ONLY0-NEXT:    store i32 [[COND45]], ptr [[IX]], align 4
57782 // SIMD-ONLY0-NEXT:    [[TMP49:%.*]] = load i32, ptr [[IX]], align 4
57783 // SIMD-ONLY0-NEXT:    store i32 [[TMP49]], ptr [[IV]], align 4
57784 // SIMD-ONLY0-NEXT:    [[TMP50:%.*]] = load i32, ptr [[IX]], align 4
57785 // SIMD-ONLY0-NEXT:    [[TMP51:%.*]] = load i32, ptr [[IE]], align 4
57786 // SIMD-ONLY0-NEXT:    [[CMP46:%.*]] = icmp slt i32 [[TMP50]], [[TMP51]]
57787 // SIMD-ONLY0-NEXT:    br i1 [[CMP46]], label [[COND_TRUE47:%.*]], label [[COND_FALSE48:%.*]]
57788 // SIMD-ONLY0:       cond.true47:
57789 // SIMD-ONLY0-NEXT:    [[TMP52:%.*]] = load i32, ptr [[IE]], align 4
57790 // SIMD-ONLY0-NEXT:    br label [[COND_END49:%.*]]
57791 // SIMD-ONLY0:       cond.false48:
57792 // SIMD-ONLY0-NEXT:    [[TMP53:%.*]] = load i32, ptr [[IX]], align 4
57793 // SIMD-ONLY0-NEXT:    br label [[COND_END49]]
57794 // SIMD-ONLY0:       cond.end49:
57795 // SIMD-ONLY0-NEXT:    [[COND50:%.*]] = phi i32 [ [[TMP52]], [[COND_TRUE47]] ], [ [[TMP53]], [[COND_FALSE48]] ]
57796 // SIMD-ONLY0-NEXT:    store i32 [[COND50]], ptr [[IX]], align 4
57797 // SIMD-ONLY0-NEXT:    [[TMP54:%.*]] = load i32, ptr [[IX]], align 4
57798 // SIMD-ONLY0-NEXT:    store i32 [[TMP54]], ptr [[IV]], align 4
57799 // SIMD-ONLY0-NEXT:    [[TMP55:%.*]] = load i32, ptr [[IX]], align 4
57800 // SIMD-ONLY0-NEXT:    [[TMP56:%.*]] = load i32, ptr [[IE]], align 4
57801 // SIMD-ONLY0-NEXT:    [[CMP51:%.*]] = icmp eq i32 [[TMP55]], [[TMP56]]
57802 // SIMD-ONLY0-NEXT:    br i1 [[CMP51]], label [[COND_TRUE52:%.*]], label [[COND_FALSE53:%.*]]
57803 // SIMD-ONLY0:       cond.true52:
57804 // SIMD-ONLY0-NEXT:    [[TMP57:%.*]] = load i32, ptr [[ID]], align 4
57805 // SIMD-ONLY0-NEXT:    br label [[COND_END54:%.*]]
57806 // SIMD-ONLY0:       cond.false53:
57807 // SIMD-ONLY0-NEXT:    [[TMP58:%.*]] = load i32, ptr [[IX]], align 4
57808 // SIMD-ONLY0-NEXT:    br label [[COND_END54]]
57809 // SIMD-ONLY0:       cond.end54:
57810 // SIMD-ONLY0-NEXT:    [[COND55:%.*]] = phi i32 [ [[TMP57]], [[COND_TRUE52]] ], [ [[TMP58]], [[COND_FALSE53]] ]
57811 // SIMD-ONLY0-NEXT:    store i32 [[COND55]], ptr [[IX]], align 4
57812 // SIMD-ONLY0-NEXT:    [[TMP59:%.*]] = load i32, ptr [[IX]], align 4
57813 // SIMD-ONLY0-NEXT:    store i32 [[TMP59]], ptr [[IV]], align 4
57814 // SIMD-ONLY0-NEXT:    [[TMP60:%.*]] = load i32, ptr [[IX]], align 4
57815 // SIMD-ONLY0-NEXT:    store i32 [[TMP60]], ptr [[IV]], align 4
57816 // SIMD-ONLY0-NEXT:    [[TMP61:%.*]] = load i32, ptr [[IX]], align 4
57817 // SIMD-ONLY0-NEXT:    [[TMP62:%.*]] = load i32, ptr [[IE]], align 4
57818 // SIMD-ONLY0-NEXT:    [[CMP56:%.*]] = icmp sgt i32 [[TMP61]], [[TMP62]]
57819 // SIMD-ONLY0-NEXT:    br i1 [[CMP56]], label [[COND_TRUE57:%.*]], label [[COND_FALSE58:%.*]]
57820 // SIMD-ONLY0:       cond.true57:
57821 // SIMD-ONLY0-NEXT:    [[TMP63:%.*]] = load i32, ptr [[IE]], align 4
57822 // SIMD-ONLY0-NEXT:    br label [[COND_END59:%.*]]
57823 // SIMD-ONLY0:       cond.false58:
57824 // SIMD-ONLY0-NEXT:    [[TMP64:%.*]] = load i32, ptr [[IX]], align 4
57825 // SIMD-ONLY0-NEXT:    br label [[COND_END59]]
57826 // SIMD-ONLY0:       cond.end59:
57827 // SIMD-ONLY0-NEXT:    [[COND60:%.*]] = phi i32 [ [[TMP63]], [[COND_TRUE57]] ], [ [[TMP64]], [[COND_FALSE58]] ]
57828 // SIMD-ONLY0-NEXT:    store i32 [[COND60]], ptr [[IX]], align 4
57829 // SIMD-ONLY0-NEXT:    [[TMP65:%.*]] = load i32, ptr [[IX]], align 4
57830 // SIMD-ONLY0-NEXT:    store i32 [[TMP65]], ptr [[IV]], align 4
57831 // SIMD-ONLY0-NEXT:    [[TMP66:%.*]] = load i32, ptr [[IX]], align 4
57832 // SIMD-ONLY0-NEXT:    [[TMP67:%.*]] = load i32, ptr [[IE]], align 4
57833 // SIMD-ONLY0-NEXT:    [[CMP61:%.*]] = icmp slt i32 [[TMP66]], [[TMP67]]
57834 // SIMD-ONLY0-NEXT:    br i1 [[CMP61]], label [[COND_TRUE62:%.*]], label [[COND_FALSE63:%.*]]
57835 // SIMD-ONLY0:       cond.true62:
57836 // SIMD-ONLY0-NEXT:    [[TMP68:%.*]] = load i32, ptr [[IE]], align 4
57837 // SIMD-ONLY0-NEXT:    br label [[COND_END64:%.*]]
57838 // SIMD-ONLY0:       cond.false63:
57839 // SIMD-ONLY0-NEXT:    [[TMP69:%.*]] = load i32, ptr [[IX]], align 4
57840 // SIMD-ONLY0-NEXT:    br label [[COND_END64]]
57841 // SIMD-ONLY0:       cond.end64:
57842 // SIMD-ONLY0-NEXT:    [[COND65:%.*]] = phi i32 [ [[TMP68]], [[COND_TRUE62]] ], [ [[TMP69]], [[COND_FALSE63]] ]
57843 // SIMD-ONLY0-NEXT:    store i32 [[COND65]], ptr [[IX]], align 4
57844 // SIMD-ONLY0-NEXT:    [[TMP70:%.*]] = load i32, ptr [[IX]], align 4
57845 // SIMD-ONLY0-NEXT:    store i32 [[TMP70]], ptr [[IV]], align 4
57846 // SIMD-ONLY0-NEXT:    [[TMP71:%.*]] = load i32, ptr [[IX]], align 4
57847 // SIMD-ONLY0-NEXT:    [[TMP72:%.*]] = load i32, ptr [[IE]], align 4
57848 // SIMD-ONLY0-NEXT:    [[CMP66:%.*]] = icmp eq i32 [[TMP71]], [[TMP72]]
57849 // SIMD-ONLY0-NEXT:    br i1 [[CMP66]], label [[COND_TRUE67:%.*]], label [[COND_FALSE68:%.*]]
57850 // SIMD-ONLY0:       cond.true67:
57851 // SIMD-ONLY0-NEXT:    [[TMP73:%.*]] = load i32, ptr [[ID]], align 4
57852 // SIMD-ONLY0-NEXT:    br label [[COND_END69:%.*]]
57853 // SIMD-ONLY0:       cond.false68:
57854 // SIMD-ONLY0-NEXT:    [[TMP74:%.*]] = load i32, ptr [[IX]], align 4
57855 // SIMD-ONLY0-NEXT:    br label [[COND_END69]]
57856 // SIMD-ONLY0:       cond.end69:
57857 // SIMD-ONLY0-NEXT:    [[COND70:%.*]] = phi i32 [ [[TMP73]], [[COND_TRUE67]] ], [ [[TMP74]], [[COND_FALSE68]] ]
57858 // SIMD-ONLY0-NEXT:    store i32 [[COND70]], ptr [[IX]], align 4
57859 // SIMD-ONLY0-NEXT:    [[TMP75:%.*]] = load i32, ptr [[IX]], align 4
57860 // SIMD-ONLY0-NEXT:    [[TMP76:%.*]] = load i32, ptr [[IE]], align 4
57861 // SIMD-ONLY0-NEXT:    [[CMP71:%.*]] = icmp sgt i32 [[TMP75]], [[TMP76]]
57862 // SIMD-ONLY0-NEXT:    br i1 [[CMP71]], label [[COND_TRUE72:%.*]], label [[COND_FALSE73:%.*]]
57863 // SIMD-ONLY0:       cond.true72:
57864 // SIMD-ONLY0-NEXT:    [[TMP77:%.*]] = load i32, ptr [[IE]], align 4
57865 // SIMD-ONLY0-NEXT:    br label [[COND_END74:%.*]]
57866 // SIMD-ONLY0:       cond.false73:
57867 // SIMD-ONLY0-NEXT:    [[TMP78:%.*]] = load i32, ptr [[IX]], align 4
57868 // SIMD-ONLY0-NEXT:    br label [[COND_END74]]
57869 // SIMD-ONLY0:       cond.end74:
57870 // SIMD-ONLY0-NEXT:    [[COND75:%.*]] = phi i32 [ [[TMP77]], [[COND_TRUE72]] ], [ [[TMP78]], [[COND_FALSE73]] ]
57871 // SIMD-ONLY0-NEXT:    store i32 [[COND75]], ptr [[IX]], align 4
57872 // SIMD-ONLY0-NEXT:    [[TMP79:%.*]] = load i32, ptr [[IX]], align 4
57873 // SIMD-ONLY0-NEXT:    store i32 [[TMP79]], ptr [[IV]], align 4
57874 // SIMD-ONLY0-NEXT:    [[TMP80:%.*]] = load i32, ptr [[IX]], align 4
57875 // SIMD-ONLY0-NEXT:    [[TMP81:%.*]] = load i32, ptr [[IE]], align 4
57876 // SIMD-ONLY0-NEXT:    [[CMP76:%.*]] = icmp slt i32 [[TMP80]], [[TMP81]]
57877 // SIMD-ONLY0-NEXT:    br i1 [[CMP76]], label [[COND_TRUE77:%.*]], label [[COND_FALSE78:%.*]]
57878 // SIMD-ONLY0:       cond.true77:
57879 // SIMD-ONLY0-NEXT:    [[TMP82:%.*]] = load i32, ptr [[IE]], align 4
57880 // SIMD-ONLY0-NEXT:    br label [[COND_END79:%.*]]
57881 // SIMD-ONLY0:       cond.false78:
57882 // SIMD-ONLY0-NEXT:    [[TMP83:%.*]] = load i32, ptr [[IX]], align 4
57883 // SIMD-ONLY0-NEXT:    br label [[COND_END79]]
57884 // SIMD-ONLY0:       cond.end79:
57885 // SIMD-ONLY0-NEXT:    [[COND80:%.*]] = phi i32 [ [[TMP82]], [[COND_TRUE77]] ], [ [[TMP83]], [[COND_FALSE78]] ]
57886 // SIMD-ONLY0-NEXT:    store i32 [[COND80]], ptr [[IX]], align 4
57887 // SIMD-ONLY0-NEXT:    [[TMP84:%.*]] = load i32, ptr [[IX]], align 4
57888 // SIMD-ONLY0-NEXT:    store i32 [[TMP84]], ptr [[IV]], align 4
57889 // SIMD-ONLY0-NEXT:    [[TMP85:%.*]] = load i32, ptr [[IX]], align 4
57890 // SIMD-ONLY0-NEXT:    [[TMP86:%.*]] = load i32, ptr [[IE]], align 4
57891 // SIMD-ONLY0-NEXT:    [[CMP81:%.*]] = icmp eq i32 [[TMP85]], [[TMP86]]
57892 // SIMD-ONLY0-NEXT:    br i1 [[CMP81]], label [[COND_TRUE82:%.*]], label [[COND_FALSE83:%.*]]
57893 // SIMD-ONLY0:       cond.true82:
57894 // SIMD-ONLY0-NEXT:    [[TMP87:%.*]] = load i32, ptr [[ID]], align 4
57895 // SIMD-ONLY0-NEXT:    br label [[COND_END84:%.*]]
57896 // SIMD-ONLY0:       cond.false83:
57897 // SIMD-ONLY0-NEXT:    [[TMP88:%.*]] = load i32, ptr [[IX]], align 4
57898 // SIMD-ONLY0-NEXT:    br label [[COND_END84]]
57899 // SIMD-ONLY0:       cond.end84:
57900 // SIMD-ONLY0-NEXT:    [[COND85:%.*]] = phi i32 [ [[TMP87]], [[COND_TRUE82]] ], [ [[TMP88]], [[COND_FALSE83]] ]
57901 // SIMD-ONLY0-NEXT:    store i32 [[COND85]], ptr [[IX]], align 4
57902 // SIMD-ONLY0-NEXT:    [[TMP89:%.*]] = load i32, ptr [[IX]], align 4
57903 // SIMD-ONLY0-NEXT:    store i32 [[TMP89]], ptr [[IV]], align 4
57904 // SIMD-ONLY0-NEXT:    [[TMP90:%.*]] = load i32, ptr [[IX]], align 4
57905 // SIMD-ONLY0-NEXT:    store i32 [[TMP90]], ptr [[IV]], align 4
57906 // SIMD-ONLY0-NEXT:    [[TMP91:%.*]] = load i32, ptr [[IX]], align 4
57907 // SIMD-ONLY0-NEXT:    [[TMP92:%.*]] = load i32, ptr [[IE]], align 4
57908 // SIMD-ONLY0-NEXT:    [[CMP86:%.*]] = icmp sgt i32 [[TMP91]], [[TMP92]]
57909 // SIMD-ONLY0-NEXT:    br i1 [[CMP86]], label [[COND_TRUE87:%.*]], label [[COND_FALSE88:%.*]]
57910 // SIMD-ONLY0:       cond.true87:
57911 // SIMD-ONLY0-NEXT:    [[TMP93:%.*]] = load i32, ptr [[IE]], align 4
57912 // SIMD-ONLY0-NEXT:    br label [[COND_END89:%.*]]
57913 // SIMD-ONLY0:       cond.false88:
57914 // SIMD-ONLY0-NEXT:    [[TMP94:%.*]] = load i32, ptr [[IX]], align 4
57915 // SIMD-ONLY0-NEXT:    br label [[COND_END89]]
57916 // SIMD-ONLY0:       cond.end89:
57917 // SIMD-ONLY0-NEXT:    [[COND90:%.*]] = phi i32 [ [[TMP93]], [[COND_TRUE87]] ], [ [[TMP94]], [[COND_FALSE88]] ]
57918 // SIMD-ONLY0-NEXT:    store i32 [[COND90]], ptr [[IX]], align 4
57919 // SIMD-ONLY0-NEXT:    [[TMP95:%.*]] = load i32, ptr [[IX]], align 4
57920 // SIMD-ONLY0-NEXT:    store i32 [[TMP95]], ptr [[IV]], align 4
57921 // SIMD-ONLY0-NEXT:    [[TMP96:%.*]] = load i32, ptr [[IX]], align 4
57922 // SIMD-ONLY0-NEXT:    [[TMP97:%.*]] = load i32, ptr [[IE]], align 4
57923 // SIMD-ONLY0-NEXT:    [[CMP91:%.*]] = icmp slt i32 [[TMP96]], [[TMP97]]
57924 // SIMD-ONLY0-NEXT:    br i1 [[CMP91]], label [[COND_TRUE92:%.*]], label [[COND_FALSE93:%.*]]
57925 // SIMD-ONLY0:       cond.true92:
57926 // SIMD-ONLY0-NEXT:    [[TMP98:%.*]] = load i32, ptr [[IE]], align 4
57927 // SIMD-ONLY0-NEXT:    br label [[COND_END94:%.*]]
57928 // SIMD-ONLY0:       cond.false93:
57929 // SIMD-ONLY0-NEXT:    [[TMP99:%.*]] = load i32, ptr [[IX]], align 4
57930 // SIMD-ONLY0-NEXT:    br label [[COND_END94]]
57931 // SIMD-ONLY0:       cond.end94:
57932 // SIMD-ONLY0-NEXT:    [[COND95:%.*]] = phi i32 [ [[TMP98]], [[COND_TRUE92]] ], [ [[TMP99]], [[COND_FALSE93]] ]
57933 // SIMD-ONLY0-NEXT:    store i32 [[COND95]], ptr [[IX]], align 4
57934 // SIMD-ONLY0-NEXT:    [[TMP100:%.*]] = load i32, ptr [[IX]], align 4
57935 // SIMD-ONLY0-NEXT:    store i32 [[TMP100]], ptr [[IV]], align 4
57936 // SIMD-ONLY0-NEXT:    [[TMP101:%.*]] = load i32, ptr [[IX]], align 4
57937 // SIMD-ONLY0-NEXT:    [[TMP102:%.*]] = load i32, ptr [[IE]], align 4
57938 // SIMD-ONLY0-NEXT:    [[CMP96:%.*]] = icmp eq i32 [[TMP101]], [[TMP102]]
57939 // SIMD-ONLY0-NEXT:    br i1 [[CMP96]], label [[COND_TRUE97:%.*]], label [[COND_FALSE98:%.*]]
57940 // SIMD-ONLY0:       cond.true97:
57941 // SIMD-ONLY0-NEXT:    [[TMP103:%.*]] = load i32, ptr [[ID]], align 4
57942 // SIMD-ONLY0-NEXT:    br label [[COND_END99:%.*]]
57943 // SIMD-ONLY0:       cond.false98:
57944 // SIMD-ONLY0-NEXT:    [[TMP104:%.*]] = load i32, ptr [[IX]], align 4
57945 // SIMD-ONLY0-NEXT:    br label [[COND_END99]]
57946 // SIMD-ONLY0:       cond.end99:
57947 // SIMD-ONLY0-NEXT:    [[COND100:%.*]] = phi i32 [ [[TMP103]], [[COND_TRUE97]] ], [ [[TMP104]], [[COND_FALSE98]] ]
57948 // SIMD-ONLY0-NEXT:    store i32 [[COND100]], ptr [[IX]], align 4
57949 // SIMD-ONLY0-NEXT:    [[TMP105:%.*]] = load i32, ptr [[IX]], align 4
57950 // SIMD-ONLY0-NEXT:    [[TMP106:%.*]] = load i32, ptr [[IE]], align 4
57951 // SIMD-ONLY0-NEXT:    [[CMP101:%.*]] = icmp sgt i32 [[TMP105]], [[TMP106]]
57952 // SIMD-ONLY0-NEXT:    br i1 [[CMP101]], label [[COND_TRUE102:%.*]], label [[COND_FALSE103:%.*]]
57953 // SIMD-ONLY0:       cond.true102:
57954 // SIMD-ONLY0-NEXT:    [[TMP107:%.*]] = load i32, ptr [[IE]], align 4
57955 // SIMD-ONLY0-NEXT:    br label [[COND_END104:%.*]]
57956 // SIMD-ONLY0:       cond.false103:
57957 // SIMD-ONLY0-NEXT:    [[TMP108:%.*]] = load i32, ptr [[IX]], align 4
57958 // SIMD-ONLY0-NEXT:    br label [[COND_END104]]
57959 // SIMD-ONLY0:       cond.end104:
57960 // SIMD-ONLY0-NEXT:    [[COND105:%.*]] = phi i32 [ [[TMP107]], [[COND_TRUE102]] ], [ [[TMP108]], [[COND_FALSE103]] ]
57961 // SIMD-ONLY0-NEXT:    store i32 [[COND105]], ptr [[IX]], align 4
57962 // SIMD-ONLY0-NEXT:    [[TMP109:%.*]] = load i32, ptr [[IX]], align 4
57963 // SIMD-ONLY0-NEXT:    store i32 [[TMP109]], ptr [[IV]], align 4
57964 // SIMD-ONLY0-NEXT:    [[TMP110:%.*]] = load i32, ptr [[IX]], align 4
57965 // SIMD-ONLY0-NEXT:    [[TMP111:%.*]] = load i32, ptr [[IE]], align 4
57966 // SIMD-ONLY0-NEXT:    [[CMP106:%.*]] = icmp slt i32 [[TMP110]], [[TMP111]]
57967 // SIMD-ONLY0-NEXT:    br i1 [[CMP106]], label [[COND_TRUE107:%.*]], label [[COND_FALSE108:%.*]]
57968 // SIMD-ONLY0:       cond.true107:
57969 // SIMD-ONLY0-NEXT:    [[TMP112:%.*]] = load i32, ptr [[IE]], align 4
57970 // SIMD-ONLY0-NEXT:    br label [[COND_END109:%.*]]
57971 // SIMD-ONLY0:       cond.false108:
57972 // SIMD-ONLY0-NEXT:    [[TMP113:%.*]] = load i32, ptr [[IX]], align 4
57973 // SIMD-ONLY0-NEXT:    br label [[COND_END109]]
57974 // SIMD-ONLY0:       cond.end109:
57975 // SIMD-ONLY0-NEXT:    [[COND110:%.*]] = phi i32 [ [[TMP112]], [[COND_TRUE107]] ], [ [[TMP113]], [[COND_FALSE108]] ]
57976 // SIMD-ONLY0-NEXT:    store i32 [[COND110]], ptr [[IX]], align 4
57977 // SIMD-ONLY0-NEXT:    [[TMP114:%.*]] = load i32, ptr [[IX]], align 4
57978 // SIMD-ONLY0-NEXT:    store i32 [[TMP114]], ptr [[IV]], align 4
57979 // SIMD-ONLY0-NEXT:    [[TMP115:%.*]] = load i32, ptr [[IX]], align 4
57980 // SIMD-ONLY0-NEXT:    [[TMP116:%.*]] = load i32, ptr [[IE]], align 4
57981 // SIMD-ONLY0-NEXT:    [[CMP111:%.*]] = icmp eq i32 [[TMP115]], [[TMP116]]
57982 // SIMD-ONLY0-NEXT:    br i1 [[CMP111]], label [[COND_TRUE112:%.*]], label [[COND_FALSE113:%.*]]
57983 // SIMD-ONLY0:       cond.true112:
57984 // SIMD-ONLY0-NEXT:    [[TMP117:%.*]] = load i32, ptr [[ID]], align 4
57985 // SIMD-ONLY0-NEXT:    br label [[COND_END114:%.*]]
57986 // SIMD-ONLY0:       cond.false113:
57987 // SIMD-ONLY0-NEXT:    [[TMP118:%.*]] = load i32, ptr [[IX]], align 4
57988 // SIMD-ONLY0-NEXT:    br label [[COND_END114]]
57989 // SIMD-ONLY0:       cond.end114:
57990 // SIMD-ONLY0-NEXT:    [[COND115:%.*]] = phi i32 [ [[TMP117]], [[COND_TRUE112]] ], [ [[TMP118]], [[COND_FALSE113]] ]
57991 // SIMD-ONLY0-NEXT:    store i32 [[COND115]], ptr [[IX]], align 4
57992 // SIMD-ONLY0-NEXT:    [[TMP119:%.*]] = load i32, ptr [[IX]], align 4
57993 // SIMD-ONLY0-NEXT:    store i32 [[TMP119]], ptr [[IV]], align 4
57994 // SIMD-ONLY0-NEXT:    [[TMP120:%.*]] = load i32, ptr [[IX]], align 4
57995 // SIMD-ONLY0-NEXT:    store i32 [[TMP120]], ptr [[IV]], align 4
57996 // SIMD-ONLY0-NEXT:    [[TMP121:%.*]] = load i32, ptr [[IX]], align 4
57997 // SIMD-ONLY0-NEXT:    [[TMP122:%.*]] = load i32, ptr [[IE]], align 4
57998 // SIMD-ONLY0-NEXT:    [[CMP116:%.*]] = icmp sgt i32 [[TMP121]], [[TMP122]]
57999 // SIMD-ONLY0-NEXT:    br i1 [[CMP116]], label [[COND_TRUE117:%.*]], label [[COND_FALSE118:%.*]]
58000 // SIMD-ONLY0:       cond.true117:
58001 // SIMD-ONLY0-NEXT:    [[TMP123:%.*]] = load i32, ptr [[IE]], align 4
58002 // SIMD-ONLY0-NEXT:    br label [[COND_END119:%.*]]
58003 // SIMD-ONLY0:       cond.false118:
58004 // SIMD-ONLY0-NEXT:    [[TMP124:%.*]] = load i32, ptr [[IX]], align 4
58005 // SIMD-ONLY0-NEXT:    br label [[COND_END119]]
58006 // SIMD-ONLY0:       cond.end119:
58007 // SIMD-ONLY0-NEXT:    [[COND120:%.*]] = phi i32 [ [[TMP123]], [[COND_TRUE117]] ], [ [[TMP124]], [[COND_FALSE118]] ]
58008 // SIMD-ONLY0-NEXT:    store i32 [[COND120]], ptr [[IX]], align 4
58009 // SIMD-ONLY0-NEXT:    [[TMP125:%.*]] = load i32, ptr [[IX]], align 4
58010 // SIMD-ONLY0-NEXT:    store i32 [[TMP125]], ptr [[IV]], align 4
58011 // SIMD-ONLY0-NEXT:    [[TMP126:%.*]] = load i32, ptr [[IX]], align 4
58012 // SIMD-ONLY0-NEXT:    [[TMP127:%.*]] = load i32, ptr [[IE]], align 4
58013 // SIMD-ONLY0-NEXT:    [[CMP121:%.*]] = icmp slt i32 [[TMP126]], [[TMP127]]
58014 // SIMD-ONLY0-NEXT:    br i1 [[CMP121]], label [[COND_TRUE122:%.*]], label [[COND_FALSE123:%.*]]
58015 // SIMD-ONLY0:       cond.true122:
58016 // SIMD-ONLY0-NEXT:    [[TMP128:%.*]] = load i32, ptr [[IE]], align 4
58017 // SIMD-ONLY0-NEXT:    br label [[COND_END124:%.*]]
58018 // SIMD-ONLY0:       cond.false123:
58019 // SIMD-ONLY0-NEXT:    [[TMP129:%.*]] = load i32, ptr [[IX]], align 4
58020 // SIMD-ONLY0-NEXT:    br label [[COND_END124]]
58021 // SIMD-ONLY0:       cond.end124:
58022 // SIMD-ONLY0-NEXT:    [[COND125:%.*]] = phi i32 [ [[TMP128]], [[COND_TRUE122]] ], [ [[TMP129]], [[COND_FALSE123]] ]
58023 // SIMD-ONLY0-NEXT:    store i32 [[COND125]], ptr [[IX]], align 4
58024 // SIMD-ONLY0-NEXT:    [[TMP130:%.*]] = load i32, ptr [[IX]], align 4
58025 // SIMD-ONLY0-NEXT:    store i32 [[TMP130]], ptr [[IV]], align 4
58026 // SIMD-ONLY0-NEXT:    [[TMP131:%.*]] = load i32, ptr [[IX]], align 4
58027 // SIMD-ONLY0-NEXT:    [[TMP132:%.*]] = load i32, ptr [[IE]], align 4
58028 // SIMD-ONLY0-NEXT:    [[CMP126:%.*]] = icmp eq i32 [[TMP131]], [[TMP132]]
58029 // SIMD-ONLY0-NEXT:    br i1 [[CMP126]], label [[COND_TRUE127:%.*]], label [[COND_FALSE128:%.*]]
58030 // SIMD-ONLY0:       cond.true127:
58031 // SIMD-ONLY0-NEXT:    [[TMP133:%.*]] = load i32, ptr [[ID]], align 4
58032 // SIMD-ONLY0-NEXT:    br label [[COND_END129:%.*]]
58033 // SIMD-ONLY0:       cond.false128:
58034 // SIMD-ONLY0-NEXT:    [[TMP134:%.*]] = load i32, ptr [[IX]], align 4
58035 // SIMD-ONLY0-NEXT:    br label [[COND_END129]]
58036 // SIMD-ONLY0:       cond.end129:
58037 // SIMD-ONLY0-NEXT:    [[COND130:%.*]] = phi i32 [ [[TMP133]], [[COND_TRUE127]] ], [ [[TMP134]], [[COND_FALSE128]] ]
58038 // SIMD-ONLY0-NEXT:    store i32 [[COND130]], ptr [[IX]], align 4
58039 // SIMD-ONLY0-NEXT:    [[TMP135:%.*]] = load i32, ptr [[IX]], align 4
58040 // SIMD-ONLY0-NEXT:    [[TMP136:%.*]] = load i32, ptr [[IE]], align 4
58041 // SIMD-ONLY0-NEXT:    [[CMP131:%.*]] = icmp sgt i32 [[TMP135]], [[TMP136]]
58042 // SIMD-ONLY0-NEXT:    br i1 [[CMP131]], label [[COND_TRUE132:%.*]], label [[COND_FALSE133:%.*]]
58043 // SIMD-ONLY0:       cond.true132:
58044 // SIMD-ONLY0-NEXT:    [[TMP137:%.*]] = load i32, ptr [[IE]], align 4
58045 // SIMD-ONLY0-NEXT:    br label [[COND_END134:%.*]]
58046 // SIMD-ONLY0:       cond.false133:
58047 // SIMD-ONLY0-NEXT:    [[TMP138:%.*]] = load i32, ptr [[IX]], align 4
58048 // SIMD-ONLY0-NEXT:    br label [[COND_END134]]
58049 // SIMD-ONLY0:       cond.end134:
58050 // SIMD-ONLY0-NEXT:    [[COND135:%.*]] = phi i32 [ [[TMP137]], [[COND_TRUE132]] ], [ [[TMP138]], [[COND_FALSE133]] ]
58051 // SIMD-ONLY0-NEXT:    store i32 [[COND135]], ptr [[IX]], align 4
58052 // SIMD-ONLY0-NEXT:    [[TMP139:%.*]] = load i32, ptr [[IX]], align 4
58053 // SIMD-ONLY0-NEXT:    store i32 [[TMP139]], ptr [[IV]], align 4
58054 // SIMD-ONLY0-NEXT:    [[TMP140:%.*]] = load i32, ptr [[IX]], align 4
58055 // SIMD-ONLY0-NEXT:    [[TMP141:%.*]] = load i32, ptr [[IE]], align 4
58056 // SIMD-ONLY0-NEXT:    [[CMP136:%.*]] = icmp slt i32 [[TMP140]], [[TMP141]]
58057 // SIMD-ONLY0-NEXT:    br i1 [[CMP136]], label [[COND_TRUE137:%.*]], label [[COND_FALSE138:%.*]]
58058 // SIMD-ONLY0:       cond.true137:
58059 // SIMD-ONLY0-NEXT:    [[TMP142:%.*]] = load i32, ptr [[IE]], align 4
58060 // SIMD-ONLY0-NEXT:    br label [[COND_END139:%.*]]
58061 // SIMD-ONLY0:       cond.false138:
58062 // SIMD-ONLY0-NEXT:    [[TMP143:%.*]] = load i32, ptr [[IX]], align 4
58063 // SIMD-ONLY0-NEXT:    br label [[COND_END139]]
58064 // SIMD-ONLY0:       cond.end139:
58065 // SIMD-ONLY0-NEXT:    [[COND140:%.*]] = phi i32 [ [[TMP142]], [[COND_TRUE137]] ], [ [[TMP143]], [[COND_FALSE138]] ]
58066 // SIMD-ONLY0-NEXT:    store i32 [[COND140]], ptr [[IX]], align 4
58067 // SIMD-ONLY0-NEXT:    [[TMP144:%.*]] = load i32, ptr [[IX]], align 4
58068 // SIMD-ONLY0-NEXT:    store i32 [[TMP144]], ptr [[IV]], align 4
58069 // SIMD-ONLY0-NEXT:    [[TMP145:%.*]] = load i32, ptr [[IX]], align 4
58070 // SIMD-ONLY0-NEXT:    [[TMP146:%.*]] = load i32, ptr [[IE]], align 4
58071 // SIMD-ONLY0-NEXT:    [[CMP141:%.*]] = icmp eq i32 [[TMP145]], [[TMP146]]
58072 // SIMD-ONLY0-NEXT:    br i1 [[CMP141]], label [[COND_TRUE142:%.*]], label [[COND_FALSE143:%.*]]
58073 // SIMD-ONLY0:       cond.true142:
58074 // SIMD-ONLY0-NEXT:    [[TMP147:%.*]] = load i32, ptr [[ID]], align 4
58075 // SIMD-ONLY0-NEXT:    br label [[COND_END144:%.*]]
58076 // SIMD-ONLY0:       cond.false143:
58077 // SIMD-ONLY0-NEXT:    [[TMP148:%.*]] = load i32, ptr [[IX]], align 4
58078 // SIMD-ONLY0-NEXT:    br label [[COND_END144]]
58079 // SIMD-ONLY0:       cond.end144:
58080 // SIMD-ONLY0-NEXT:    [[COND145:%.*]] = phi i32 [ [[TMP147]], [[COND_TRUE142]] ], [ [[TMP148]], [[COND_FALSE143]] ]
58081 // SIMD-ONLY0-NEXT:    store i32 [[COND145]], ptr [[IX]], align 4
58082 // SIMD-ONLY0-NEXT:    [[TMP149:%.*]] = load i32, ptr [[IX]], align 4
58083 // SIMD-ONLY0-NEXT:    store i32 [[TMP149]], ptr [[IV]], align 4
58084 // SIMD-ONLY0-NEXT:    [[TMP150:%.*]] = load i32, ptr [[IX]], align 4
58085 // SIMD-ONLY0-NEXT:    store i32 [[TMP150]], ptr [[IV]], align 4
58086 // SIMD-ONLY0-NEXT:    [[TMP151:%.*]] = load i32, ptr [[IX]], align 4
58087 // SIMD-ONLY0-NEXT:    [[TMP152:%.*]] = load i32, ptr [[IE]], align 4
58088 // SIMD-ONLY0-NEXT:    [[CMP146:%.*]] = icmp sgt i32 [[TMP151]], [[TMP152]]
58089 // SIMD-ONLY0-NEXT:    br i1 [[CMP146]], label [[COND_TRUE147:%.*]], label [[COND_FALSE148:%.*]]
58090 // SIMD-ONLY0:       cond.true147:
58091 // SIMD-ONLY0-NEXT:    [[TMP153:%.*]] = load i32, ptr [[IE]], align 4
58092 // SIMD-ONLY0-NEXT:    br label [[COND_END149:%.*]]
58093 // SIMD-ONLY0:       cond.false148:
58094 // SIMD-ONLY0-NEXT:    [[TMP154:%.*]] = load i32, ptr [[IX]], align 4
58095 // SIMD-ONLY0-NEXT:    br label [[COND_END149]]
58096 // SIMD-ONLY0:       cond.end149:
58097 // SIMD-ONLY0-NEXT:    [[COND150:%.*]] = phi i32 [ [[TMP153]], [[COND_TRUE147]] ], [ [[TMP154]], [[COND_FALSE148]] ]
58098 // SIMD-ONLY0-NEXT:    store i32 [[COND150]], ptr [[IX]], align 4
58099 // SIMD-ONLY0-NEXT:    [[TMP155:%.*]] = load i32, ptr [[IX]], align 4
58100 // SIMD-ONLY0-NEXT:    store i32 [[TMP155]], ptr [[IV]], align 4
58101 // SIMD-ONLY0-NEXT:    [[TMP156:%.*]] = load i32, ptr [[IX]], align 4
58102 // SIMD-ONLY0-NEXT:    [[TMP157:%.*]] = load i32, ptr [[IE]], align 4
58103 // SIMD-ONLY0-NEXT:    [[CMP151:%.*]] = icmp slt i32 [[TMP156]], [[TMP157]]
58104 // SIMD-ONLY0-NEXT:    br i1 [[CMP151]], label [[COND_TRUE152:%.*]], label [[COND_FALSE153:%.*]]
58105 // SIMD-ONLY0:       cond.true152:
58106 // SIMD-ONLY0-NEXT:    [[TMP158:%.*]] = load i32, ptr [[IE]], align 4
58107 // SIMD-ONLY0-NEXT:    br label [[COND_END154:%.*]]
58108 // SIMD-ONLY0:       cond.false153:
58109 // SIMD-ONLY0-NEXT:    [[TMP159:%.*]] = load i32, ptr [[IX]], align 4
58110 // SIMD-ONLY0-NEXT:    br label [[COND_END154]]
58111 // SIMD-ONLY0:       cond.end154:
58112 // SIMD-ONLY0-NEXT:    [[COND155:%.*]] = phi i32 [ [[TMP158]], [[COND_TRUE152]] ], [ [[TMP159]], [[COND_FALSE153]] ]
58113 // SIMD-ONLY0-NEXT:    store i32 [[COND155]], ptr [[IX]], align 4
58114 // SIMD-ONLY0-NEXT:    [[TMP160:%.*]] = load i32, ptr [[IX]], align 4
58115 // SIMD-ONLY0-NEXT:    store i32 [[TMP160]], ptr [[IV]], align 4
58116 // SIMD-ONLY0-NEXT:    [[TMP161:%.*]] = load i32, ptr [[IX]], align 4
58117 // SIMD-ONLY0-NEXT:    [[TMP162:%.*]] = load i32, ptr [[IE]], align 4
58118 // SIMD-ONLY0-NEXT:    [[CMP156:%.*]] = icmp eq i32 [[TMP161]], [[TMP162]]
58119 // SIMD-ONLY0-NEXT:    br i1 [[CMP156]], label [[COND_TRUE157:%.*]], label [[COND_FALSE158:%.*]]
58120 // SIMD-ONLY0:       cond.true157:
58121 // SIMD-ONLY0-NEXT:    [[TMP163:%.*]] = load i32, ptr [[ID]], align 4
58122 // SIMD-ONLY0-NEXT:    br label [[COND_END159:%.*]]
58123 // SIMD-ONLY0:       cond.false158:
58124 // SIMD-ONLY0-NEXT:    [[TMP164:%.*]] = load i32, ptr [[IX]], align 4
58125 // SIMD-ONLY0-NEXT:    br label [[COND_END159]]
58126 // SIMD-ONLY0:       cond.end159:
58127 // SIMD-ONLY0-NEXT:    [[COND160:%.*]] = phi i32 [ [[TMP163]], [[COND_TRUE157]] ], [ [[TMP164]], [[COND_FALSE158]] ]
58128 // SIMD-ONLY0-NEXT:    store i32 [[COND160]], ptr [[IX]], align 4
58129 // SIMD-ONLY0-NEXT:    [[TMP165:%.*]] = load i32, ptr [[IX]], align 4
58130 // SIMD-ONLY0-NEXT:    [[TMP166:%.*]] = load i32, ptr [[IE]], align 4
58131 // SIMD-ONLY0-NEXT:    [[CMP161:%.*]] = icmp sgt i32 [[TMP165]], [[TMP166]]
58132 // SIMD-ONLY0-NEXT:    br i1 [[CMP161]], label [[COND_TRUE162:%.*]], label [[COND_FALSE163:%.*]]
58133 // SIMD-ONLY0:       cond.true162:
58134 // SIMD-ONLY0-NEXT:    [[TMP167:%.*]] = load i32, ptr [[IE]], align 4
58135 // SIMD-ONLY0-NEXT:    br label [[COND_END164:%.*]]
58136 // SIMD-ONLY0:       cond.false163:
58137 // SIMD-ONLY0-NEXT:    [[TMP168:%.*]] = load i32, ptr [[IX]], align 4
58138 // SIMD-ONLY0-NEXT:    br label [[COND_END164]]
58139 // SIMD-ONLY0:       cond.end164:
58140 // SIMD-ONLY0-NEXT:    [[COND165:%.*]] = phi i32 [ [[TMP167]], [[COND_TRUE162]] ], [ [[TMP168]], [[COND_FALSE163]] ]
58141 // SIMD-ONLY0-NEXT:    store i32 [[COND165]], ptr [[IX]], align 4
58142 // SIMD-ONLY0-NEXT:    [[TMP169:%.*]] = load i32, ptr [[IX]], align 4
58143 // SIMD-ONLY0-NEXT:    store i32 [[TMP169]], ptr [[IV]], align 4
58144 // SIMD-ONLY0-NEXT:    [[TMP170:%.*]] = load i32, ptr [[IX]], align 4
58145 // SIMD-ONLY0-NEXT:    [[TMP171:%.*]] = load i32, ptr [[IE]], align 4
58146 // SIMD-ONLY0-NEXT:    [[CMP166:%.*]] = icmp slt i32 [[TMP170]], [[TMP171]]
58147 // SIMD-ONLY0-NEXT:    br i1 [[CMP166]], label [[COND_TRUE167:%.*]], label [[COND_FALSE168:%.*]]
58148 // SIMD-ONLY0:       cond.true167:
58149 // SIMD-ONLY0-NEXT:    [[TMP172:%.*]] = load i32, ptr [[IE]], align 4
58150 // SIMD-ONLY0-NEXT:    br label [[COND_END169:%.*]]
58151 // SIMD-ONLY0:       cond.false168:
58152 // SIMD-ONLY0-NEXT:    [[TMP173:%.*]] = load i32, ptr [[IX]], align 4
58153 // SIMD-ONLY0-NEXT:    br label [[COND_END169]]
58154 // SIMD-ONLY0:       cond.end169:
58155 // SIMD-ONLY0-NEXT:    [[COND170:%.*]] = phi i32 [ [[TMP172]], [[COND_TRUE167]] ], [ [[TMP173]], [[COND_FALSE168]] ]
58156 // SIMD-ONLY0-NEXT:    store i32 [[COND170]], ptr [[IX]], align 4
58157 // SIMD-ONLY0-NEXT:    [[TMP174:%.*]] = load i32, ptr [[IX]], align 4
58158 // SIMD-ONLY0-NEXT:    store i32 [[TMP174]], ptr [[IV]], align 4
58159 // SIMD-ONLY0-NEXT:    [[TMP175:%.*]] = load i32, ptr [[IX]], align 4
58160 // SIMD-ONLY0-NEXT:    [[TMP176:%.*]] = load i32, ptr [[IE]], align 4
58161 // SIMD-ONLY0-NEXT:    [[CMP171:%.*]] = icmp eq i32 [[TMP175]], [[TMP176]]
58162 // SIMD-ONLY0-NEXT:    br i1 [[CMP171]], label [[COND_TRUE172:%.*]], label [[COND_FALSE173:%.*]]
58163 // SIMD-ONLY0:       cond.true172:
58164 // SIMD-ONLY0-NEXT:    [[TMP177:%.*]] = load i32, ptr [[ID]], align 4
58165 // SIMD-ONLY0-NEXT:    br label [[COND_END174:%.*]]
58166 // SIMD-ONLY0:       cond.false173:
58167 // SIMD-ONLY0-NEXT:    [[TMP178:%.*]] = load i32, ptr [[IX]], align 4
58168 // SIMD-ONLY0-NEXT:    br label [[COND_END174]]
58169 // SIMD-ONLY0:       cond.end174:
58170 // SIMD-ONLY0-NEXT:    [[COND175:%.*]] = phi i32 [ [[TMP177]], [[COND_TRUE172]] ], [ [[TMP178]], [[COND_FALSE173]] ]
58171 // SIMD-ONLY0-NEXT:    store i32 [[COND175]], ptr [[IX]], align 4
58172 // SIMD-ONLY0-NEXT:    [[TMP179:%.*]] = load i32, ptr [[IX]], align 4
58173 // SIMD-ONLY0-NEXT:    store i32 [[TMP179]], ptr [[IV]], align 4
58174 // SIMD-ONLY0-NEXT:    [[TMP180:%.*]] = load i32, ptr [[IV]], align 4
58175 // SIMD-ONLY0-NEXT:    ret i32 [[TMP180]]
58176 //
58177 //
58178 // SIMD-ONLY0-LABEL: @uixevd(
58179 // SIMD-ONLY0-NEXT:  entry:
58180 // SIMD-ONLY0-NEXT:    [[UIX:%.*]] = alloca i32, align 4
58181 // SIMD-ONLY0-NEXT:    [[UIV:%.*]] = alloca i32, align 4
58182 // SIMD-ONLY0-NEXT:    [[UIE:%.*]] = alloca i32, align 4
58183 // SIMD-ONLY0-NEXT:    [[UID:%.*]] = alloca i32, align 4
58184 // SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = load i32, ptr [[UIX]], align 4
58185 // SIMD-ONLY0-NEXT:    store i32 [[TMP0]], ptr [[UIV]], align 4
58186 // SIMD-ONLY0-NEXT:    [[TMP1:%.*]] = load i32, ptr [[UIX]], align 4
58187 // SIMD-ONLY0-NEXT:    [[TMP2:%.*]] = load i32, ptr [[UIE]], align 4
58188 // SIMD-ONLY0-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP1]], [[TMP2]]
58189 // SIMD-ONLY0-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
58190 // SIMD-ONLY0:       cond.true:
58191 // SIMD-ONLY0-NEXT:    [[TMP3:%.*]] = load i32, ptr [[UIE]], align 4
58192 // SIMD-ONLY0-NEXT:    br label [[COND_END:%.*]]
58193 // SIMD-ONLY0:       cond.false:
58194 // SIMD-ONLY0-NEXT:    [[TMP4:%.*]] = load i32, ptr [[UIX]], align 4
58195 // SIMD-ONLY0-NEXT:    br label [[COND_END]]
58196 // SIMD-ONLY0:       cond.end:
58197 // SIMD-ONLY0-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP3]], [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
58198 // SIMD-ONLY0-NEXT:    store i32 [[COND]], ptr [[UIX]], align 4
58199 // SIMD-ONLY0-NEXT:    [[TMP5:%.*]] = load i32, ptr [[UIX]], align 4
58200 // SIMD-ONLY0-NEXT:    store i32 [[TMP5]], ptr [[UIV]], align 4
58201 // SIMD-ONLY0-NEXT:    [[TMP6:%.*]] = load i32, ptr [[UIX]], align 4
58202 // SIMD-ONLY0-NEXT:    [[TMP7:%.*]] = load i32, ptr [[UIE]], align 4
58203 // SIMD-ONLY0-NEXT:    [[CMP1:%.*]] = icmp ult i32 [[TMP6]], [[TMP7]]
58204 // SIMD-ONLY0-NEXT:    br i1 [[CMP1]], label [[COND_TRUE2:%.*]], label [[COND_FALSE3:%.*]]
58205 // SIMD-ONLY0:       cond.true2:
58206 // SIMD-ONLY0-NEXT:    [[TMP8:%.*]] = load i32, ptr [[UIE]], align 4
58207 // SIMD-ONLY0-NEXT:    br label [[COND_END4:%.*]]
58208 // SIMD-ONLY0:       cond.false3:
58209 // SIMD-ONLY0-NEXT:    [[TMP9:%.*]] = load i32, ptr [[UIX]], align 4
58210 // SIMD-ONLY0-NEXT:    br label [[COND_END4]]
58211 // SIMD-ONLY0:       cond.end4:
58212 // SIMD-ONLY0-NEXT:    [[COND5:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE2]] ], [ [[TMP9]], [[COND_FALSE3]] ]
58213 // SIMD-ONLY0-NEXT:    store i32 [[COND5]], ptr [[UIX]], align 4
58214 // SIMD-ONLY0-NEXT:    [[TMP10:%.*]] = load i32, ptr [[UIX]], align 4
58215 // SIMD-ONLY0-NEXT:    store i32 [[TMP10]], ptr [[UIV]], align 4
58216 // SIMD-ONLY0-NEXT:    [[TMP11:%.*]] = load i32, ptr [[UIX]], align 4
58217 // SIMD-ONLY0-NEXT:    [[TMP12:%.*]] = load i32, ptr [[UIE]], align 4
58218 // SIMD-ONLY0-NEXT:    [[CMP6:%.*]] = icmp eq i32 [[TMP11]], [[TMP12]]
58219 // SIMD-ONLY0-NEXT:    br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
58220 // SIMD-ONLY0:       cond.true7:
58221 // SIMD-ONLY0-NEXT:    [[TMP13:%.*]] = load i32, ptr [[UID]], align 4
58222 // SIMD-ONLY0-NEXT:    br label [[COND_END9:%.*]]
58223 // SIMD-ONLY0:       cond.false8:
58224 // SIMD-ONLY0-NEXT:    [[TMP14:%.*]] = load i32, ptr [[UIX]], align 4
58225 // SIMD-ONLY0-NEXT:    br label [[COND_END9]]
58226 // SIMD-ONLY0:       cond.end9:
58227 // SIMD-ONLY0-NEXT:    [[COND10:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE7]] ], [ [[TMP14]], [[COND_FALSE8]] ]
58228 // SIMD-ONLY0-NEXT:    store i32 [[COND10]], ptr [[UIX]], align 4
58229 // SIMD-ONLY0-NEXT:    [[TMP15:%.*]] = load i32, ptr [[UIX]], align 4
58230 // SIMD-ONLY0-NEXT:    [[TMP16:%.*]] = load i32, ptr [[UIE]], align 4
58231 // SIMD-ONLY0-NEXT:    [[CMP11:%.*]] = icmp ugt i32 [[TMP15]], [[TMP16]]
58232 // SIMD-ONLY0-NEXT:    br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
58233 // SIMD-ONLY0:       cond.true12:
58234 // SIMD-ONLY0-NEXT:    [[TMP17:%.*]] = load i32, ptr [[UIE]], align 4
58235 // SIMD-ONLY0-NEXT:    br label [[COND_END14:%.*]]
58236 // SIMD-ONLY0:       cond.false13:
58237 // SIMD-ONLY0-NEXT:    [[TMP18:%.*]] = load i32, ptr [[UIX]], align 4
58238 // SIMD-ONLY0-NEXT:    br label [[COND_END14]]
58239 // SIMD-ONLY0:       cond.end14:
58240 // SIMD-ONLY0-NEXT:    [[COND15:%.*]] = phi i32 [ [[TMP17]], [[COND_TRUE12]] ], [ [[TMP18]], [[COND_FALSE13]] ]
58241 // SIMD-ONLY0-NEXT:    store i32 [[COND15]], ptr [[UIX]], align 4
58242 // SIMD-ONLY0-NEXT:    [[TMP19:%.*]] = load i32, ptr [[UIX]], align 4
58243 // SIMD-ONLY0-NEXT:    store i32 [[TMP19]], ptr [[UIV]], align 4
58244 // SIMD-ONLY0-NEXT:    [[TMP20:%.*]] = load i32, ptr [[UIX]], align 4
58245 // SIMD-ONLY0-NEXT:    [[TMP21:%.*]] = load i32, ptr [[UIE]], align 4
58246 // SIMD-ONLY0-NEXT:    [[CMP16:%.*]] = icmp ult i32 [[TMP20]], [[TMP21]]
58247 // SIMD-ONLY0-NEXT:    br i1 [[CMP16]], label [[COND_TRUE17:%.*]], label [[COND_FALSE18:%.*]]
58248 // SIMD-ONLY0:       cond.true17:
58249 // SIMD-ONLY0-NEXT:    [[TMP22:%.*]] = load i32, ptr [[UIE]], align 4
58250 // SIMD-ONLY0-NEXT:    br label [[COND_END19:%.*]]
58251 // SIMD-ONLY0:       cond.false18:
58252 // SIMD-ONLY0-NEXT:    [[TMP23:%.*]] = load i32, ptr [[UIX]], align 4
58253 // SIMD-ONLY0-NEXT:    br label [[COND_END19]]
58254 // SIMD-ONLY0:       cond.end19:
58255 // SIMD-ONLY0-NEXT:    [[COND20:%.*]] = phi i32 [ [[TMP22]], [[COND_TRUE17]] ], [ [[TMP23]], [[COND_FALSE18]] ]
58256 // SIMD-ONLY0-NEXT:    store i32 [[COND20]], ptr [[UIX]], align 4
58257 // SIMD-ONLY0-NEXT:    [[TMP24:%.*]] = load i32, ptr [[UIX]], align 4
58258 // SIMD-ONLY0-NEXT:    store i32 [[TMP24]], ptr [[UIV]], align 4
58259 // SIMD-ONLY0-NEXT:    [[TMP25:%.*]] = load i32, ptr [[UIX]], align 4
58260 // SIMD-ONLY0-NEXT:    [[TMP26:%.*]] = load i32, ptr [[UIE]], align 4
58261 // SIMD-ONLY0-NEXT:    [[CMP21:%.*]] = icmp eq i32 [[TMP25]], [[TMP26]]
58262 // SIMD-ONLY0-NEXT:    br i1 [[CMP21]], label [[COND_TRUE22:%.*]], label [[COND_FALSE23:%.*]]
58263 // SIMD-ONLY0:       cond.true22:
58264 // SIMD-ONLY0-NEXT:    [[TMP27:%.*]] = load i32, ptr [[UID]], align 4
58265 // SIMD-ONLY0-NEXT:    br label [[COND_END24:%.*]]
58266 // SIMD-ONLY0:       cond.false23:
58267 // SIMD-ONLY0-NEXT:    [[TMP28:%.*]] = load i32, ptr [[UIX]], align 4
58268 // SIMD-ONLY0-NEXT:    br label [[COND_END24]]
58269 // SIMD-ONLY0:       cond.end24:
58270 // SIMD-ONLY0-NEXT:    [[COND25:%.*]] = phi i32 [ [[TMP27]], [[COND_TRUE22]] ], [ [[TMP28]], [[COND_FALSE23]] ]
58271 // SIMD-ONLY0-NEXT:    store i32 [[COND25]], ptr [[UIX]], align 4
58272 // SIMD-ONLY0-NEXT:    [[TMP29:%.*]] = load i32, ptr [[UIX]], align 4
58273 // SIMD-ONLY0-NEXT:    store i32 [[TMP29]], ptr [[UIV]], align 4
58274 // SIMD-ONLY0-NEXT:    [[TMP30:%.*]] = load i32, ptr [[UIX]], align 4
58275 // SIMD-ONLY0-NEXT:    store i32 [[TMP30]], ptr [[UIV]], align 4
58276 // SIMD-ONLY0-NEXT:    [[TMP31:%.*]] = load i32, ptr [[UIX]], align 4
58277 // SIMD-ONLY0-NEXT:    [[TMP32:%.*]] = load i32, ptr [[UIE]], align 4
58278 // SIMD-ONLY0-NEXT:    [[CMP26:%.*]] = icmp ugt i32 [[TMP31]], [[TMP32]]
58279 // SIMD-ONLY0-NEXT:    br i1 [[CMP26]], label [[COND_TRUE27:%.*]], label [[COND_FALSE28:%.*]]
58280 // SIMD-ONLY0:       cond.true27:
58281 // SIMD-ONLY0-NEXT:    [[TMP33:%.*]] = load i32, ptr [[UIE]], align 4
58282 // SIMD-ONLY0-NEXT:    br label [[COND_END29:%.*]]
58283 // SIMD-ONLY0:       cond.false28:
58284 // SIMD-ONLY0-NEXT:    [[TMP34:%.*]] = load i32, ptr [[UIX]], align 4
58285 // SIMD-ONLY0-NEXT:    br label [[COND_END29]]
58286 // SIMD-ONLY0:       cond.end29:
58287 // SIMD-ONLY0-NEXT:    [[COND30:%.*]] = phi i32 [ [[TMP33]], [[COND_TRUE27]] ], [ [[TMP34]], [[COND_FALSE28]] ]
58288 // SIMD-ONLY0-NEXT:    store i32 [[COND30]], ptr [[UIX]], align 4
58289 // SIMD-ONLY0-NEXT:    [[TMP35:%.*]] = load i32, ptr [[UIX]], align 4
58290 // SIMD-ONLY0-NEXT:    store i32 [[TMP35]], ptr [[UIV]], align 4
58291 // SIMD-ONLY0-NEXT:    [[TMP36:%.*]] = load i32, ptr [[UIX]], align 4
58292 // SIMD-ONLY0-NEXT:    [[TMP37:%.*]] = load i32, ptr [[UIE]], align 4
58293 // SIMD-ONLY0-NEXT:    [[CMP31:%.*]] = icmp ult i32 [[TMP36]], [[TMP37]]
58294 // SIMD-ONLY0-NEXT:    br i1 [[CMP31]], label [[COND_TRUE32:%.*]], label [[COND_FALSE33:%.*]]
58295 // SIMD-ONLY0:       cond.true32:
58296 // SIMD-ONLY0-NEXT:    [[TMP38:%.*]] = load i32, ptr [[UIE]], align 4
58297 // SIMD-ONLY0-NEXT:    br label [[COND_END34:%.*]]
58298 // SIMD-ONLY0:       cond.false33:
58299 // SIMD-ONLY0-NEXT:    [[TMP39:%.*]] = load i32, ptr [[UIX]], align 4
58300 // SIMD-ONLY0-NEXT:    br label [[COND_END34]]
58301 // SIMD-ONLY0:       cond.end34:
58302 // SIMD-ONLY0-NEXT:    [[COND35:%.*]] = phi i32 [ [[TMP38]], [[COND_TRUE32]] ], [ [[TMP39]], [[COND_FALSE33]] ]
58303 // SIMD-ONLY0-NEXT:    store i32 [[COND35]], ptr [[UIX]], align 4
58304 // SIMD-ONLY0-NEXT:    [[TMP40:%.*]] = load i32, ptr [[UIX]], align 4
58305 // SIMD-ONLY0-NEXT:    store i32 [[TMP40]], ptr [[UIV]], align 4
58306 // SIMD-ONLY0-NEXT:    [[TMP41:%.*]] = load i32, ptr [[UIX]], align 4
58307 // SIMD-ONLY0-NEXT:    [[TMP42:%.*]] = load i32, ptr [[UIE]], align 4
58308 // SIMD-ONLY0-NEXT:    [[CMP36:%.*]] = icmp eq i32 [[TMP41]], [[TMP42]]
58309 // SIMD-ONLY0-NEXT:    br i1 [[CMP36]], label [[COND_TRUE37:%.*]], label [[COND_FALSE38:%.*]]
58310 // SIMD-ONLY0:       cond.true37:
58311 // SIMD-ONLY0-NEXT:    [[TMP43:%.*]] = load i32, ptr [[UID]], align 4
58312 // SIMD-ONLY0-NEXT:    br label [[COND_END39:%.*]]
58313 // SIMD-ONLY0:       cond.false38:
58314 // SIMD-ONLY0-NEXT:    [[TMP44:%.*]] = load i32, ptr [[UIX]], align 4
58315 // SIMD-ONLY0-NEXT:    br label [[COND_END39]]
58316 // SIMD-ONLY0:       cond.end39:
58317 // SIMD-ONLY0-NEXT:    [[COND40:%.*]] = phi i32 [ [[TMP43]], [[COND_TRUE37]] ], [ [[TMP44]], [[COND_FALSE38]] ]
58318 // SIMD-ONLY0-NEXT:    store i32 [[COND40]], ptr [[UIX]], align 4
58319 // SIMD-ONLY0-NEXT:    [[TMP45:%.*]] = load i32, ptr [[UIX]], align 4
58320 // SIMD-ONLY0-NEXT:    [[TMP46:%.*]] = load i32, ptr [[UIE]], align 4
58321 // SIMD-ONLY0-NEXT:    [[CMP41:%.*]] = icmp ugt i32 [[TMP45]], [[TMP46]]
58322 // SIMD-ONLY0-NEXT:    br i1 [[CMP41]], label [[COND_TRUE42:%.*]], label [[COND_FALSE43:%.*]]
58323 // SIMD-ONLY0:       cond.true42:
58324 // SIMD-ONLY0-NEXT:    [[TMP47:%.*]] = load i32, ptr [[UIE]], align 4
58325 // SIMD-ONLY0-NEXT:    br label [[COND_END44:%.*]]
58326 // SIMD-ONLY0:       cond.false43:
58327 // SIMD-ONLY0-NEXT:    [[TMP48:%.*]] = load i32, ptr [[UIX]], align 4
58328 // SIMD-ONLY0-NEXT:    br label [[COND_END44]]
58329 // SIMD-ONLY0:       cond.end44:
58330 // SIMD-ONLY0-NEXT:    [[COND45:%.*]] = phi i32 [ [[TMP47]], [[COND_TRUE42]] ], [ [[TMP48]], [[COND_FALSE43]] ]
58331 // SIMD-ONLY0-NEXT:    store i32 [[COND45]], ptr [[UIX]], align 4
58332 // SIMD-ONLY0-NEXT:    [[TMP49:%.*]] = load i32, ptr [[UIX]], align 4
58333 // SIMD-ONLY0-NEXT:    store i32 [[TMP49]], ptr [[UIV]], align 4
58334 // SIMD-ONLY0-NEXT:    [[TMP50:%.*]] = load i32, ptr [[UIX]], align 4
58335 // SIMD-ONLY0-NEXT:    [[TMP51:%.*]] = load i32, ptr [[UIE]], align 4
58336 // SIMD-ONLY0-NEXT:    [[CMP46:%.*]] = icmp ult i32 [[TMP50]], [[TMP51]]
58337 // SIMD-ONLY0-NEXT:    br i1 [[CMP46]], label [[COND_TRUE47:%.*]], label [[COND_FALSE48:%.*]]
58338 // SIMD-ONLY0:       cond.true47:
58339 // SIMD-ONLY0-NEXT:    [[TMP52:%.*]] = load i32, ptr [[UIE]], align 4
58340 // SIMD-ONLY0-NEXT:    br label [[COND_END49:%.*]]
58341 // SIMD-ONLY0:       cond.false48:
58342 // SIMD-ONLY0-NEXT:    [[TMP53:%.*]] = load i32, ptr [[UIX]], align 4
58343 // SIMD-ONLY0-NEXT:    br label [[COND_END49]]
58344 // SIMD-ONLY0:       cond.end49:
58345 // SIMD-ONLY0-NEXT:    [[COND50:%.*]] = phi i32 [ [[TMP52]], [[COND_TRUE47]] ], [ [[TMP53]], [[COND_FALSE48]] ]
58346 // SIMD-ONLY0-NEXT:    store i32 [[COND50]], ptr [[UIX]], align 4
58347 // SIMD-ONLY0-NEXT:    [[TMP54:%.*]] = load i32, ptr [[UIX]], align 4
58348 // SIMD-ONLY0-NEXT:    store i32 [[TMP54]], ptr [[UIV]], align 4
58349 // SIMD-ONLY0-NEXT:    [[TMP55:%.*]] = load i32, ptr [[UIX]], align 4
58350 // SIMD-ONLY0-NEXT:    [[TMP56:%.*]] = load i32, ptr [[UIE]], align 4
58351 // SIMD-ONLY0-NEXT:    [[CMP51:%.*]] = icmp eq i32 [[TMP55]], [[TMP56]]
58352 // SIMD-ONLY0-NEXT:    br i1 [[CMP51]], label [[COND_TRUE52:%.*]], label [[COND_FALSE53:%.*]]
58353 // SIMD-ONLY0:       cond.true52:
58354 // SIMD-ONLY0-NEXT:    [[TMP57:%.*]] = load i32, ptr [[UID]], align 4
58355 // SIMD-ONLY0-NEXT:    br label [[COND_END54:%.*]]
58356 // SIMD-ONLY0:       cond.false53:
58357 // SIMD-ONLY0-NEXT:    [[TMP58:%.*]] = load i32, ptr [[UIX]], align 4
58358 // SIMD-ONLY0-NEXT:    br label [[COND_END54]]
58359 // SIMD-ONLY0:       cond.end54:
58360 // SIMD-ONLY0-NEXT:    [[COND55:%.*]] = phi i32 [ [[TMP57]], [[COND_TRUE52]] ], [ [[TMP58]], [[COND_FALSE53]] ]
58361 // SIMD-ONLY0-NEXT:    store i32 [[COND55]], ptr [[UIX]], align 4
58362 // SIMD-ONLY0-NEXT:    [[TMP59:%.*]] = load i32, ptr [[UIX]], align 4
58363 // SIMD-ONLY0-NEXT:    store i32 [[TMP59]], ptr [[UIV]], align 4
58364 // SIMD-ONLY0-NEXT:    [[TMP60:%.*]] = load i32, ptr [[UIX]], align 4
58365 // SIMD-ONLY0-NEXT:    store i32 [[TMP60]], ptr [[UIV]], align 4
58366 // SIMD-ONLY0-NEXT:    [[TMP61:%.*]] = load i32, ptr [[UIX]], align 4
58367 // SIMD-ONLY0-NEXT:    [[TMP62:%.*]] = load i32, ptr [[UIE]], align 4
58368 // SIMD-ONLY0-NEXT:    [[CMP56:%.*]] = icmp ugt i32 [[TMP61]], [[TMP62]]
58369 // SIMD-ONLY0-NEXT:    br i1 [[CMP56]], label [[COND_TRUE57:%.*]], label [[COND_FALSE58:%.*]]
58370 // SIMD-ONLY0:       cond.true57:
58371 // SIMD-ONLY0-NEXT:    [[TMP63:%.*]] = load i32, ptr [[UIE]], align 4
58372 // SIMD-ONLY0-NEXT:    br label [[COND_END59:%.*]]
58373 // SIMD-ONLY0:       cond.false58:
58374 // SIMD-ONLY0-NEXT:    [[TMP64:%.*]] = load i32, ptr [[UIX]], align 4
58375 // SIMD-ONLY0-NEXT:    br label [[COND_END59]]
58376 // SIMD-ONLY0:       cond.end59:
58377 // SIMD-ONLY0-NEXT:    [[COND60:%.*]] = phi i32 [ [[TMP63]], [[COND_TRUE57]] ], [ [[TMP64]], [[COND_FALSE58]] ]
58378 // SIMD-ONLY0-NEXT:    store i32 [[COND60]], ptr [[UIX]], align 4
58379 // SIMD-ONLY0-NEXT:    [[TMP65:%.*]] = load i32, ptr [[UIX]], align 4
58380 // SIMD-ONLY0-NEXT:    store i32 [[TMP65]], ptr [[UIV]], align 4
58381 // SIMD-ONLY0-NEXT:    [[TMP66:%.*]] = load i32, ptr [[UIX]], align 4
58382 // SIMD-ONLY0-NEXT:    [[TMP67:%.*]] = load i32, ptr [[UIE]], align 4
58383 // SIMD-ONLY0-NEXT:    [[CMP61:%.*]] = icmp ult i32 [[TMP66]], [[TMP67]]
58384 // SIMD-ONLY0-NEXT:    br i1 [[CMP61]], label [[COND_TRUE62:%.*]], label [[COND_FALSE63:%.*]]
58385 // SIMD-ONLY0:       cond.true62:
58386 // SIMD-ONLY0-NEXT:    [[TMP68:%.*]] = load i32, ptr [[UIE]], align 4
58387 // SIMD-ONLY0-NEXT:    br label [[COND_END64:%.*]]
58388 // SIMD-ONLY0:       cond.false63:
58389 // SIMD-ONLY0-NEXT:    [[TMP69:%.*]] = load i32, ptr [[UIX]], align 4
58390 // SIMD-ONLY0-NEXT:    br label [[COND_END64]]
58391 // SIMD-ONLY0:       cond.end64:
58392 // SIMD-ONLY0-NEXT:    [[COND65:%.*]] = phi i32 [ [[TMP68]], [[COND_TRUE62]] ], [ [[TMP69]], [[COND_FALSE63]] ]
58393 // SIMD-ONLY0-NEXT:    store i32 [[COND65]], ptr [[UIX]], align 4
58394 // SIMD-ONLY0-NEXT:    [[TMP70:%.*]] = load i32, ptr [[UIX]], align 4
58395 // SIMD-ONLY0-NEXT:    store i32 [[TMP70]], ptr [[UIV]], align 4
58396 // SIMD-ONLY0-NEXT:    [[TMP71:%.*]] = load i32, ptr [[UIX]], align 4
58397 // SIMD-ONLY0-NEXT:    [[TMP72:%.*]] = load i32, ptr [[UIE]], align 4
58398 // SIMD-ONLY0-NEXT:    [[CMP66:%.*]] = icmp eq i32 [[TMP71]], [[TMP72]]
58399 // SIMD-ONLY0-NEXT:    br i1 [[CMP66]], label [[COND_TRUE67:%.*]], label [[COND_FALSE68:%.*]]
58400 // SIMD-ONLY0:       cond.true67:
58401 // SIMD-ONLY0-NEXT:    [[TMP73:%.*]] = load i32, ptr [[UID]], align 4
58402 // SIMD-ONLY0-NEXT:    br label [[COND_END69:%.*]]
58403 // SIMD-ONLY0:       cond.false68:
58404 // SIMD-ONLY0-NEXT:    [[TMP74:%.*]] = load i32, ptr [[UIX]], align 4
58405 // SIMD-ONLY0-NEXT:    br label [[COND_END69]]
58406 // SIMD-ONLY0:       cond.end69:
58407 // SIMD-ONLY0-NEXT:    [[COND70:%.*]] = phi i32 [ [[TMP73]], [[COND_TRUE67]] ], [ [[TMP74]], [[COND_FALSE68]] ]
58408 // SIMD-ONLY0-NEXT:    store i32 [[COND70]], ptr [[UIX]], align 4
58409 // SIMD-ONLY0-NEXT:    [[TMP75:%.*]] = load i32, ptr [[UIX]], align 4
58410 // SIMD-ONLY0-NEXT:    [[TMP76:%.*]] = load i32, ptr [[UIE]], align 4
58411 // SIMD-ONLY0-NEXT:    [[CMP71:%.*]] = icmp ugt i32 [[TMP75]], [[TMP76]]
58412 // SIMD-ONLY0-NEXT:    br i1 [[CMP71]], label [[COND_TRUE72:%.*]], label [[COND_FALSE73:%.*]]
58413 // SIMD-ONLY0:       cond.true72:
58414 // SIMD-ONLY0-NEXT:    [[TMP77:%.*]] = load i32, ptr [[UIE]], align 4
58415 // SIMD-ONLY0-NEXT:    br label [[COND_END74:%.*]]
58416 // SIMD-ONLY0:       cond.false73:
58417 // SIMD-ONLY0-NEXT:    [[TMP78:%.*]] = load i32, ptr [[UIX]], align 4
58418 // SIMD-ONLY0-NEXT:    br label [[COND_END74]]
58419 // SIMD-ONLY0:       cond.end74:
58420 // SIMD-ONLY0-NEXT:    [[COND75:%.*]] = phi i32 [ [[TMP77]], [[COND_TRUE72]] ], [ [[TMP78]], [[COND_FALSE73]] ]
58421 // SIMD-ONLY0-NEXT:    store i32 [[COND75]], ptr [[UIX]], align 4
58422 // SIMD-ONLY0-NEXT:    [[TMP79:%.*]] = load i32, ptr [[UIX]], align 4
58423 // SIMD-ONLY0-NEXT:    store i32 [[TMP79]], ptr [[UIV]], align 4
58424 // SIMD-ONLY0-NEXT:    [[TMP80:%.*]] = load i32, ptr [[UIX]], align 4
58425 // SIMD-ONLY0-NEXT:    [[TMP81:%.*]] = load i32, ptr [[UIE]], align 4
58426 // SIMD-ONLY0-NEXT:    [[CMP76:%.*]] = icmp ult i32 [[TMP80]], [[TMP81]]
58427 // SIMD-ONLY0-NEXT:    br i1 [[CMP76]], label [[COND_TRUE77:%.*]], label [[COND_FALSE78:%.*]]
58428 // SIMD-ONLY0:       cond.true77:
58429 // SIMD-ONLY0-NEXT:    [[TMP82:%.*]] = load i32, ptr [[UIE]], align 4
58430 // SIMD-ONLY0-NEXT:    br label [[COND_END79:%.*]]
58431 // SIMD-ONLY0:       cond.false78:
58432 // SIMD-ONLY0-NEXT:    [[TMP83:%.*]] = load i32, ptr [[UIX]], align 4
58433 // SIMD-ONLY0-NEXT:    br label [[COND_END79]]
58434 // SIMD-ONLY0:       cond.end79:
58435 // SIMD-ONLY0-NEXT:    [[COND80:%.*]] = phi i32 [ [[TMP82]], [[COND_TRUE77]] ], [ [[TMP83]], [[COND_FALSE78]] ]
58436 // SIMD-ONLY0-NEXT:    store i32 [[COND80]], ptr [[UIX]], align 4
58437 // SIMD-ONLY0-NEXT:    [[TMP84:%.*]] = load i32, ptr [[UIX]], align 4
58438 // SIMD-ONLY0-NEXT:    store i32 [[TMP84]], ptr [[UIV]], align 4
58439 // SIMD-ONLY0-NEXT:    [[TMP85:%.*]] = load i32, ptr [[UIX]], align 4
58440 // SIMD-ONLY0-NEXT:    [[TMP86:%.*]] = load i32, ptr [[UIE]], align 4
58441 // SIMD-ONLY0-NEXT:    [[CMP81:%.*]] = icmp eq i32 [[TMP85]], [[TMP86]]
58442 // SIMD-ONLY0-NEXT:    br i1 [[CMP81]], label [[COND_TRUE82:%.*]], label [[COND_FALSE83:%.*]]
58443 // SIMD-ONLY0:       cond.true82:
58444 // SIMD-ONLY0-NEXT:    [[TMP87:%.*]] = load i32, ptr [[UID]], align 4
58445 // SIMD-ONLY0-NEXT:    br label [[COND_END84:%.*]]
58446 // SIMD-ONLY0:       cond.false83:
58447 // SIMD-ONLY0-NEXT:    [[TMP88:%.*]] = load i32, ptr [[UIX]], align 4
58448 // SIMD-ONLY0-NEXT:    br label [[COND_END84]]
58449 // SIMD-ONLY0:       cond.end84:
58450 // SIMD-ONLY0-NEXT:    [[COND85:%.*]] = phi i32 [ [[TMP87]], [[COND_TRUE82]] ], [ [[TMP88]], [[COND_FALSE83]] ]
58451 // SIMD-ONLY0-NEXT:    store i32 [[COND85]], ptr [[UIX]], align 4
58452 // SIMD-ONLY0-NEXT:    [[TMP89:%.*]] = load i32, ptr [[UIX]], align 4
58453 // SIMD-ONLY0-NEXT:    store i32 [[TMP89]], ptr [[UIV]], align 4
58454 // SIMD-ONLY0-NEXT:    [[TMP90:%.*]] = load i32, ptr [[UIX]], align 4
58455 // SIMD-ONLY0-NEXT:    store i32 [[TMP90]], ptr [[UIV]], align 4
58456 // SIMD-ONLY0-NEXT:    [[TMP91:%.*]] = load i32, ptr [[UIX]], align 4
58457 // SIMD-ONLY0-NEXT:    [[TMP92:%.*]] = load i32, ptr [[UIE]], align 4
58458 // SIMD-ONLY0-NEXT:    [[CMP86:%.*]] = icmp ugt i32 [[TMP91]], [[TMP92]]
58459 // SIMD-ONLY0-NEXT:    br i1 [[CMP86]], label [[COND_TRUE87:%.*]], label [[COND_FALSE88:%.*]]
58460 // SIMD-ONLY0:       cond.true87:
58461 // SIMD-ONLY0-NEXT:    [[TMP93:%.*]] = load i32, ptr [[UIE]], align 4
58462 // SIMD-ONLY0-NEXT:    br label [[COND_END89:%.*]]
58463 // SIMD-ONLY0:       cond.false88:
58464 // SIMD-ONLY0-NEXT:    [[TMP94:%.*]] = load i32, ptr [[UIX]], align 4
58465 // SIMD-ONLY0-NEXT:    br label [[COND_END89]]
58466 // SIMD-ONLY0:       cond.end89:
58467 // SIMD-ONLY0-NEXT:    [[COND90:%.*]] = phi i32 [ [[TMP93]], [[COND_TRUE87]] ], [ [[TMP94]], [[COND_FALSE88]] ]
58468 // SIMD-ONLY0-NEXT:    store i32 [[COND90]], ptr [[UIX]], align 4
58469 // SIMD-ONLY0-NEXT:    [[TMP95:%.*]] = load i32, ptr [[UIX]], align 4
58470 // SIMD-ONLY0-NEXT:    store i32 [[TMP95]], ptr [[UIV]], align 4
58471 // SIMD-ONLY0-NEXT:    [[TMP96:%.*]] = load i32, ptr [[UIX]], align 4
58472 // SIMD-ONLY0-NEXT:    [[TMP97:%.*]] = load i32, ptr [[UIE]], align 4
58473 // SIMD-ONLY0-NEXT:    [[CMP91:%.*]] = icmp ult i32 [[TMP96]], [[TMP97]]
58474 // SIMD-ONLY0-NEXT:    br i1 [[CMP91]], label [[COND_TRUE92:%.*]], label [[COND_FALSE93:%.*]]
58475 // SIMD-ONLY0:       cond.true92:
58476 // SIMD-ONLY0-NEXT:    [[TMP98:%.*]] = load i32, ptr [[UIE]], align 4
58477 // SIMD-ONLY0-NEXT:    br label [[COND_END94:%.*]]
58478 // SIMD-ONLY0:       cond.false93:
58479 // SIMD-ONLY0-NEXT:    [[TMP99:%.*]] = load i32, ptr [[UIX]], align 4
58480 // SIMD-ONLY0-NEXT:    br label [[COND_END94]]
58481 // SIMD-ONLY0:       cond.end94:
58482 // SIMD-ONLY0-NEXT:    [[COND95:%.*]] = phi i32 [ [[TMP98]], [[COND_TRUE92]] ], [ [[TMP99]], [[COND_FALSE93]] ]
58483 // SIMD-ONLY0-NEXT:    store i32 [[COND95]], ptr [[UIX]], align 4
58484 // SIMD-ONLY0-NEXT:    [[TMP100:%.*]] = load i32, ptr [[UIX]], align 4
58485 // SIMD-ONLY0-NEXT:    store i32 [[TMP100]], ptr [[UIV]], align 4
58486 // SIMD-ONLY0-NEXT:    [[TMP101:%.*]] = load i32, ptr [[UIX]], align 4
58487 // SIMD-ONLY0-NEXT:    [[TMP102:%.*]] = load i32, ptr [[UIE]], align 4
58488 // SIMD-ONLY0-NEXT:    [[CMP96:%.*]] = icmp eq i32 [[TMP101]], [[TMP102]]
58489 // SIMD-ONLY0-NEXT:    br i1 [[CMP96]], label [[COND_TRUE97:%.*]], label [[COND_FALSE98:%.*]]
58490 // SIMD-ONLY0:       cond.true97:
58491 // SIMD-ONLY0-NEXT:    [[TMP103:%.*]] = load i32, ptr [[UID]], align 4
58492 // SIMD-ONLY0-NEXT:    br label [[COND_END99:%.*]]
58493 // SIMD-ONLY0:       cond.false98:
58494 // SIMD-ONLY0-NEXT:    [[TMP104:%.*]] = load i32, ptr [[UIX]], align 4
58495 // SIMD-ONLY0-NEXT:    br label [[COND_END99]]
58496 // SIMD-ONLY0:       cond.end99:
58497 // SIMD-ONLY0-NEXT:    [[COND100:%.*]] = phi i32 [ [[TMP103]], [[COND_TRUE97]] ], [ [[TMP104]], [[COND_FALSE98]] ]
58498 // SIMD-ONLY0-NEXT:    store i32 [[COND100]], ptr [[UIX]], align 4
58499 // SIMD-ONLY0-NEXT:    [[TMP105:%.*]] = load i32, ptr [[UIX]], align 4
58500 // SIMD-ONLY0-NEXT:    [[TMP106:%.*]] = load i32, ptr [[UIE]], align 4
58501 // SIMD-ONLY0-NEXT:    [[CMP101:%.*]] = icmp ugt i32 [[TMP105]], [[TMP106]]
58502 // SIMD-ONLY0-NEXT:    br i1 [[CMP101]], label [[COND_TRUE102:%.*]], label [[COND_FALSE103:%.*]]
58503 // SIMD-ONLY0:       cond.true102:
58504 // SIMD-ONLY0-NEXT:    [[TMP107:%.*]] = load i32, ptr [[UIE]], align 4
58505 // SIMD-ONLY0-NEXT:    br label [[COND_END104:%.*]]
58506 // SIMD-ONLY0:       cond.false103:
58507 // SIMD-ONLY0-NEXT:    [[TMP108:%.*]] = load i32, ptr [[UIX]], align 4
58508 // SIMD-ONLY0-NEXT:    br label [[COND_END104]]
58509 // SIMD-ONLY0:       cond.end104:
58510 // SIMD-ONLY0-NEXT:    [[COND105:%.*]] = phi i32 [ [[TMP107]], [[COND_TRUE102]] ], [ [[TMP108]], [[COND_FALSE103]] ]
58511 // SIMD-ONLY0-NEXT:    store i32 [[COND105]], ptr [[UIX]], align 4
58512 // SIMD-ONLY0-NEXT:    [[TMP109:%.*]] = load i32, ptr [[UIX]], align 4
58513 // SIMD-ONLY0-NEXT:    store i32 [[TMP109]], ptr [[UIV]], align 4
58514 // SIMD-ONLY0-NEXT:    [[TMP110:%.*]] = load i32, ptr [[UIX]], align 4
58515 // SIMD-ONLY0-NEXT:    [[TMP111:%.*]] = load i32, ptr [[UIE]], align 4
58516 // SIMD-ONLY0-NEXT:    [[CMP106:%.*]] = icmp ult i32 [[TMP110]], [[TMP111]]
58517 // SIMD-ONLY0-NEXT:    br i1 [[CMP106]], label [[COND_TRUE107:%.*]], label [[COND_FALSE108:%.*]]
58518 // SIMD-ONLY0:       cond.true107:
58519 // SIMD-ONLY0-NEXT:    [[TMP112:%.*]] = load i32, ptr [[UIE]], align 4
58520 // SIMD-ONLY0-NEXT:    br label [[COND_END109:%.*]]
58521 // SIMD-ONLY0:       cond.false108:
58522 // SIMD-ONLY0-NEXT:    [[TMP113:%.*]] = load i32, ptr [[UIX]], align 4
58523 // SIMD-ONLY0-NEXT:    br label [[COND_END109]]
58524 // SIMD-ONLY0:       cond.end109:
58525 // SIMD-ONLY0-NEXT:    [[COND110:%.*]] = phi i32 [ [[TMP112]], [[COND_TRUE107]] ], [ [[TMP113]], [[COND_FALSE108]] ]
58526 // SIMD-ONLY0-NEXT:    store i32 [[COND110]], ptr [[UIX]], align 4
58527 // SIMD-ONLY0-NEXT:    [[TMP114:%.*]] = load i32, ptr [[UIX]], align 4
58528 // SIMD-ONLY0-NEXT:    store i32 [[TMP114]], ptr [[UIV]], align 4
58529 // SIMD-ONLY0-NEXT:    [[TMP115:%.*]] = load i32, ptr [[UIX]], align 4
58530 // SIMD-ONLY0-NEXT:    [[TMP116:%.*]] = load i32, ptr [[UIE]], align 4
58531 // SIMD-ONLY0-NEXT:    [[CMP111:%.*]] = icmp eq i32 [[TMP115]], [[TMP116]]
58532 // SIMD-ONLY0-NEXT:    br i1 [[CMP111]], label [[COND_TRUE112:%.*]], label [[COND_FALSE113:%.*]]
58533 // SIMD-ONLY0:       cond.true112:
58534 // SIMD-ONLY0-NEXT:    [[TMP117:%.*]] = load i32, ptr [[UID]], align 4
58535 // SIMD-ONLY0-NEXT:    br label [[COND_END114:%.*]]
58536 // SIMD-ONLY0:       cond.false113:
58537 // SIMD-ONLY0-NEXT:    [[TMP118:%.*]] = load i32, ptr [[UIX]], align 4
58538 // SIMD-ONLY0-NEXT:    br label [[COND_END114]]
58539 // SIMD-ONLY0:       cond.end114:
58540 // SIMD-ONLY0-NEXT:    [[COND115:%.*]] = phi i32 [ [[TMP117]], [[COND_TRUE112]] ], [ [[TMP118]], [[COND_FALSE113]] ]
58541 // SIMD-ONLY0-NEXT:    store i32 [[COND115]], ptr [[UIX]], align 4
58542 // SIMD-ONLY0-NEXT:    [[TMP119:%.*]] = load i32, ptr [[UIX]], align 4
58543 // SIMD-ONLY0-NEXT:    store i32 [[TMP119]], ptr [[UIV]], align 4
58544 // SIMD-ONLY0-NEXT:    [[TMP120:%.*]] = load i32, ptr [[UIX]], align 4
58545 // SIMD-ONLY0-NEXT:    store i32 [[TMP120]], ptr [[UIV]], align 4
58546 // SIMD-ONLY0-NEXT:    [[TMP121:%.*]] = load i32, ptr [[UIX]], align 4
58547 // SIMD-ONLY0-NEXT:    [[TMP122:%.*]] = load i32, ptr [[UIE]], align 4
58548 // SIMD-ONLY0-NEXT:    [[CMP116:%.*]] = icmp ugt i32 [[TMP121]], [[TMP122]]
58549 // SIMD-ONLY0-NEXT:    br i1 [[CMP116]], label [[COND_TRUE117:%.*]], label [[COND_FALSE118:%.*]]
58550 // SIMD-ONLY0:       cond.true117:
58551 // SIMD-ONLY0-NEXT:    [[TMP123:%.*]] = load i32, ptr [[UIE]], align 4
58552 // SIMD-ONLY0-NEXT:    br label [[COND_END119:%.*]]
58553 // SIMD-ONLY0:       cond.false118:
58554 // SIMD-ONLY0-NEXT:    [[TMP124:%.*]] = load i32, ptr [[UIX]], align 4
58555 // SIMD-ONLY0-NEXT:    br label [[COND_END119]]
58556 // SIMD-ONLY0:       cond.end119:
58557 // SIMD-ONLY0-NEXT:    [[COND120:%.*]] = phi i32 [ [[TMP123]], [[COND_TRUE117]] ], [ [[TMP124]], [[COND_FALSE118]] ]
58558 // SIMD-ONLY0-NEXT:    store i32 [[COND120]], ptr [[UIX]], align 4
58559 // SIMD-ONLY0-NEXT:    [[TMP125:%.*]] = load i32, ptr [[UIX]], align 4
58560 // SIMD-ONLY0-NEXT:    store i32 [[TMP125]], ptr [[UIV]], align 4
58561 // SIMD-ONLY0-NEXT:    [[TMP126:%.*]] = load i32, ptr [[UIX]], align 4
58562 // SIMD-ONLY0-NEXT:    [[TMP127:%.*]] = load i32, ptr [[UIE]], align 4
58563 // SIMD-ONLY0-NEXT:    [[CMP121:%.*]] = icmp ult i32 [[TMP126]], [[TMP127]]
58564 // SIMD-ONLY0-NEXT:    br i1 [[CMP121]], label [[COND_TRUE122:%.*]], label [[COND_FALSE123:%.*]]
58565 // SIMD-ONLY0:       cond.true122:
58566 // SIMD-ONLY0-NEXT:    [[TMP128:%.*]] = load i32, ptr [[UIE]], align 4
58567 // SIMD-ONLY0-NEXT:    br label [[COND_END124:%.*]]
58568 // SIMD-ONLY0:       cond.false123:
58569 // SIMD-ONLY0-NEXT:    [[TMP129:%.*]] = load i32, ptr [[UIX]], align 4
58570 // SIMD-ONLY0-NEXT:    br label [[COND_END124]]
58571 // SIMD-ONLY0:       cond.end124:
58572 // SIMD-ONLY0-NEXT:    [[COND125:%.*]] = phi i32 [ [[TMP128]], [[COND_TRUE122]] ], [ [[TMP129]], [[COND_FALSE123]] ]
58573 // SIMD-ONLY0-NEXT:    store i32 [[COND125]], ptr [[UIX]], align 4
58574 // SIMD-ONLY0-NEXT:    [[TMP130:%.*]] = load i32, ptr [[UIX]], align 4
58575 // SIMD-ONLY0-NEXT:    store i32 [[TMP130]], ptr [[UIV]], align 4
58576 // SIMD-ONLY0-NEXT:    [[TMP131:%.*]] = load i32, ptr [[UIX]], align 4
58577 // SIMD-ONLY0-NEXT:    [[TMP132:%.*]] = load i32, ptr [[UIE]], align 4
58578 // SIMD-ONLY0-NEXT:    [[CMP126:%.*]] = icmp eq i32 [[TMP131]], [[TMP132]]
58579 // SIMD-ONLY0-NEXT:    br i1 [[CMP126]], label [[COND_TRUE127:%.*]], label [[COND_FALSE128:%.*]]
58580 // SIMD-ONLY0:       cond.true127:
58581 // SIMD-ONLY0-NEXT:    [[TMP133:%.*]] = load i32, ptr [[UID]], align 4
58582 // SIMD-ONLY0-NEXT:    br label [[COND_END129:%.*]]
58583 // SIMD-ONLY0:       cond.false128:
58584 // SIMD-ONLY0-NEXT:    [[TMP134:%.*]] = load i32, ptr [[UIX]], align 4
58585 // SIMD-ONLY0-NEXT:    br label [[COND_END129]]
58586 // SIMD-ONLY0:       cond.end129:
58587 // SIMD-ONLY0-NEXT:    [[COND130:%.*]] = phi i32 [ [[TMP133]], [[COND_TRUE127]] ], [ [[TMP134]], [[COND_FALSE128]] ]
58588 // SIMD-ONLY0-NEXT:    store i32 [[COND130]], ptr [[UIX]], align 4
58589 // SIMD-ONLY0-NEXT:    [[TMP135:%.*]] = load i32, ptr [[UIX]], align 4
58590 // SIMD-ONLY0-NEXT:    [[TMP136:%.*]] = load i32, ptr [[UIE]], align 4
58591 // SIMD-ONLY0-NEXT:    [[CMP131:%.*]] = icmp ugt i32 [[TMP135]], [[TMP136]]
58592 // SIMD-ONLY0-NEXT:    br i1 [[CMP131]], label [[COND_TRUE132:%.*]], label [[COND_FALSE133:%.*]]
58593 // SIMD-ONLY0:       cond.true132:
58594 // SIMD-ONLY0-NEXT:    [[TMP137:%.*]] = load i32, ptr [[UIE]], align 4
58595 // SIMD-ONLY0-NEXT:    br label [[COND_END134:%.*]]
58596 // SIMD-ONLY0:       cond.false133:
58597 // SIMD-ONLY0-NEXT:    [[TMP138:%.*]] = load i32, ptr [[UIX]], align 4
58598 // SIMD-ONLY0-NEXT:    br label [[COND_END134]]
58599 // SIMD-ONLY0:       cond.end134:
58600 // SIMD-ONLY0-NEXT:    [[COND135:%.*]] = phi i32 [ [[TMP137]], [[COND_TRUE132]] ], [ [[TMP138]], [[COND_FALSE133]] ]
58601 // SIMD-ONLY0-NEXT:    store i32 [[COND135]], ptr [[UIX]], align 4
58602 // SIMD-ONLY0-NEXT:    [[TMP139:%.*]] = load i32, ptr [[UIX]], align 4
58603 // SIMD-ONLY0-NEXT:    store i32 [[TMP139]], ptr [[UIV]], align 4
58604 // SIMD-ONLY0-NEXT:    [[TMP140:%.*]] = load i32, ptr [[UIX]], align 4
58605 // SIMD-ONLY0-NEXT:    [[TMP141:%.*]] = load i32, ptr [[UIE]], align 4
58606 // SIMD-ONLY0-NEXT:    [[CMP136:%.*]] = icmp ult i32 [[TMP140]], [[TMP141]]
58607 // SIMD-ONLY0-NEXT:    br i1 [[CMP136]], label [[COND_TRUE137:%.*]], label [[COND_FALSE138:%.*]]
58608 // SIMD-ONLY0:       cond.true137:
58609 // SIMD-ONLY0-NEXT:    [[TMP142:%.*]] = load i32, ptr [[UIE]], align 4
58610 // SIMD-ONLY0-NEXT:    br label [[COND_END139:%.*]]
58611 // SIMD-ONLY0:       cond.false138:
58612 // SIMD-ONLY0-NEXT:    [[TMP143:%.*]] = load i32, ptr [[UIX]], align 4
58613 // SIMD-ONLY0-NEXT:    br label [[COND_END139]]
58614 // SIMD-ONLY0:       cond.end139:
58615 // SIMD-ONLY0-NEXT:    [[COND140:%.*]] = phi i32 [ [[TMP142]], [[COND_TRUE137]] ], [ [[TMP143]], [[COND_FALSE138]] ]
58616 // SIMD-ONLY0-NEXT:    store i32 [[COND140]], ptr [[UIX]], align 4
58617 // SIMD-ONLY0-NEXT:    [[TMP144:%.*]] = load i32, ptr [[UIX]], align 4
58618 // SIMD-ONLY0-NEXT:    store i32 [[TMP144]], ptr [[UIV]], align 4
58619 // SIMD-ONLY0-NEXT:    [[TMP145:%.*]] = load i32, ptr [[UIX]], align 4
58620 // SIMD-ONLY0-NEXT:    [[TMP146:%.*]] = load i32, ptr [[UIE]], align 4
58621 // SIMD-ONLY0-NEXT:    [[CMP141:%.*]] = icmp eq i32 [[TMP145]], [[TMP146]]
58622 // SIMD-ONLY0-NEXT:    br i1 [[CMP141]], label [[COND_TRUE142:%.*]], label [[COND_FALSE143:%.*]]
58623 // SIMD-ONLY0:       cond.true142:
58624 // SIMD-ONLY0-NEXT:    [[TMP147:%.*]] = load i32, ptr [[UID]], align 4
58625 // SIMD-ONLY0-NEXT:    br label [[COND_END144:%.*]]
58626 // SIMD-ONLY0:       cond.false143:
58627 // SIMD-ONLY0-NEXT:    [[TMP148:%.*]] = load i32, ptr [[UIX]], align 4
58628 // SIMD-ONLY0-NEXT:    br label [[COND_END144]]
58629 // SIMD-ONLY0:       cond.end144:
58630 // SIMD-ONLY0-NEXT:    [[COND145:%.*]] = phi i32 [ [[TMP147]], [[COND_TRUE142]] ], [ [[TMP148]], [[COND_FALSE143]] ]
58631 // SIMD-ONLY0-NEXT:    store i32 [[COND145]], ptr [[UIX]], align 4
58632 // SIMD-ONLY0-NEXT:    [[TMP149:%.*]] = load i32, ptr [[UIX]], align 4
58633 // SIMD-ONLY0-NEXT:    store i32 [[TMP149]], ptr [[UIV]], align 4
58634 // SIMD-ONLY0-NEXT:    [[TMP150:%.*]] = load i32, ptr [[UIX]], align 4
58635 // SIMD-ONLY0-NEXT:    store i32 [[TMP150]], ptr [[UIV]], align 4
58636 // SIMD-ONLY0-NEXT:    [[TMP151:%.*]] = load i32, ptr [[UIX]], align 4
58637 // SIMD-ONLY0-NEXT:    [[TMP152:%.*]] = load i32, ptr [[UIE]], align 4
58638 // SIMD-ONLY0-NEXT:    [[CMP146:%.*]] = icmp ugt i32 [[TMP151]], [[TMP152]]
58639 // SIMD-ONLY0-NEXT:    br i1 [[CMP146]], label [[COND_TRUE147:%.*]], label [[COND_FALSE148:%.*]]
58640 // SIMD-ONLY0:       cond.true147:
58641 // SIMD-ONLY0-NEXT:    [[TMP153:%.*]] = load i32, ptr [[UIE]], align 4
58642 // SIMD-ONLY0-NEXT:    br label [[COND_END149:%.*]]
58643 // SIMD-ONLY0:       cond.false148:
58644 // SIMD-ONLY0-NEXT:    [[TMP154:%.*]] = load i32, ptr [[UIX]], align 4
58645 // SIMD-ONLY0-NEXT:    br label [[COND_END149]]
58646 // SIMD-ONLY0:       cond.end149:
58647 // SIMD-ONLY0-NEXT:    [[COND150:%.*]] = phi i32 [ [[TMP153]], [[COND_TRUE147]] ], [ [[TMP154]], [[COND_FALSE148]] ]
58648 // SIMD-ONLY0-NEXT:    store i32 [[COND150]], ptr [[UIX]], align 4
58649 // SIMD-ONLY0-NEXT:    [[TMP155:%.*]] = load i32, ptr [[UIX]], align 4
58650 // SIMD-ONLY0-NEXT:    store i32 [[TMP155]], ptr [[UIV]], align 4
58651 // SIMD-ONLY0-NEXT:    [[TMP156:%.*]] = load i32, ptr [[UIX]], align 4
58652 // SIMD-ONLY0-NEXT:    [[TMP157:%.*]] = load i32, ptr [[UIE]], align 4
58653 // SIMD-ONLY0-NEXT:    [[CMP151:%.*]] = icmp ult i32 [[TMP156]], [[TMP157]]
58654 // SIMD-ONLY0-NEXT:    br i1 [[CMP151]], label [[COND_TRUE152:%.*]], label [[COND_FALSE153:%.*]]
58655 // SIMD-ONLY0:       cond.true152:
58656 // SIMD-ONLY0-NEXT:    [[TMP158:%.*]] = load i32, ptr [[UIE]], align 4
58657 // SIMD-ONLY0-NEXT:    br label [[COND_END154:%.*]]
58658 // SIMD-ONLY0:       cond.false153:
58659 // SIMD-ONLY0-NEXT:    [[TMP159:%.*]] = load i32, ptr [[UIX]], align 4
58660 // SIMD-ONLY0-NEXT:    br label [[COND_END154]]
58661 // SIMD-ONLY0:       cond.end154:
58662 // SIMD-ONLY0-NEXT:    [[COND155:%.*]] = phi i32 [ [[TMP158]], [[COND_TRUE152]] ], [ [[TMP159]], [[COND_FALSE153]] ]
58663 // SIMD-ONLY0-NEXT:    store i32 [[COND155]], ptr [[UIX]], align 4
58664 // SIMD-ONLY0-NEXT:    [[TMP160:%.*]] = load i32, ptr [[UIX]], align 4
58665 // SIMD-ONLY0-NEXT:    store i32 [[TMP160]], ptr [[UIV]], align 4
58666 // SIMD-ONLY0-NEXT:    [[TMP161:%.*]] = load i32, ptr [[UIX]], align 4
58667 // SIMD-ONLY0-NEXT:    [[TMP162:%.*]] = load i32, ptr [[UIE]], align 4
58668 // SIMD-ONLY0-NEXT:    [[CMP156:%.*]] = icmp eq i32 [[TMP161]], [[TMP162]]
58669 // SIMD-ONLY0-NEXT:    br i1 [[CMP156]], label [[COND_TRUE157:%.*]], label [[COND_FALSE158:%.*]]
58670 // SIMD-ONLY0:       cond.true157:
58671 // SIMD-ONLY0-NEXT:    [[TMP163:%.*]] = load i32, ptr [[UID]], align 4
58672 // SIMD-ONLY0-NEXT:    br label [[COND_END159:%.*]]
58673 // SIMD-ONLY0:       cond.false158:
58674 // SIMD-ONLY0-NEXT:    [[TMP164:%.*]] = load i32, ptr [[UIX]], align 4
58675 // SIMD-ONLY0-NEXT:    br label [[COND_END159]]
58676 // SIMD-ONLY0:       cond.end159:
58677 // SIMD-ONLY0-NEXT:    [[COND160:%.*]] = phi i32 [ [[TMP163]], [[COND_TRUE157]] ], [ [[TMP164]], [[COND_FALSE158]] ]
58678 // SIMD-ONLY0-NEXT:    store i32 [[COND160]], ptr [[UIX]], align 4
58679 // SIMD-ONLY0-NEXT:    [[TMP165:%.*]] = load i32, ptr [[UIX]], align 4
58680 // SIMD-ONLY0-NEXT:    [[TMP166:%.*]] = load i32, ptr [[UIE]], align 4
58681 // SIMD-ONLY0-NEXT:    [[CMP161:%.*]] = icmp ugt i32 [[TMP165]], [[TMP166]]
58682 // SIMD-ONLY0-NEXT:    br i1 [[CMP161]], label [[COND_TRUE162:%.*]], label [[COND_FALSE163:%.*]]
58683 // SIMD-ONLY0:       cond.true162:
58684 // SIMD-ONLY0-NEXT:    [[TMP167:%.*]] = load i32, ptr [[UIE]], align 4
58685 // SIMD-ONLY0-NEXT:    br label [[COND_END164:%.*]]
58686 // SIMD-ONLY0:       cond.false163:
58687 // SIMD-ONLY0-NEXT:    [[TMP168:%.*]] = load i32, ptr [[UIX]], align 4
58688 // SIMD-ONLY0-NEXT:    br label [[COND_END164]]
58689 // SIMD-ONLY0:       cond.end164:
58690 // SIMD-ONLY0-NEXT:    [[COND165:%.*]] = phi i32 [ [[TMP167]], [[COND_TRUE162]] ], [ [[TMP168]], [[COND_FALSE163]] ]
58691 // SIMD-ONLY0-NEXT:    store i32 [[COND165]], ptr [[UIX]], align 4
58692 // SIMD-ONLY0-NEXT:    [[TMP169:%.*]] = load i32, ptr [[UIX]], align 4
58693 // SIMD-ONLY0-NEXT:    store i32 [[TMP169]], ptr [[UIV]], align 4
58694 // SIMD-ONLY0-NEXT:    [[TMP170:%.*]] = load i32, ptr [[UIX]], align 4
58695 // SIMD-ONLY0-NEXT:    [[TMP171:%.*]] = load i32, ptr [[UIE]], align 4
58696 // SIMD-ONLY0-NEXT:    [[CMP166:%.*]] = icmp ult i32 [[TMP170]], [[TMP171]]
58697 // SIMD-ONLY0-NEXT:    br i1 [[CMP166]], label [[COND_TRUE167:%.*]], label [[COND_FALSE168:%.*]]
58698 // SIMD-ONLY0:       cond.true167:
58699 // SIMD-ONLY0-NEXT:    [[TMP172:%.*]] = load i32, ptr [[UIE]], align 4
58700 // SIMD-ONLY0-NEXT:    br label [[COND_END169:%.*]]
58701 // SIMD-ONLY0:       cond.false168:
58702 // SIMD-ONLY0-NEXT:    [[TMP173:%.*]] = load i32, ptr [[UIX]], align 4
58703 // SIMD-ONLY0-NEXT:    br label [[COND_END169]]
58704 // SIMD-ONLY0:       cond.end169:
58705 // SIMD-ONLY0-NEXT:    [[COND170:%.*]] = phi i32 [ [[TMP172]], [[COND_TRUE167]] ], [ [[TMP173]], [[COND_FALSE168]] ]
58706 // SIMD-ONLY0-NEXT:    store i32 [[COND170]], ptr [[UIX]], align 4
58707 // SIMD-ONLY0-NEXT:    [[TMP174:%.*]] = load i32, ptr [[UIX]], align 4
58708 // SIMD-ONLY0-NEXT:    store i32 [[TMP174]], ptr [[UIV]], align 4
58709 // SIMD-ONLY0-NEXT:    [[TMP175:%.*]] = load i32, ptr [[UIX]], align 4
58710 // SIMD-ONLY0-NEXT:    [[TMP176:%.*]] = load i32, ptr [[UIE]], align 4
58711 // SIMD-ONLY0-NEXT:    [[CMP171:%.*]] = icmp eq i32 [[TMP175]], [[TMP176]]
58712 // SIMD-ONLY0-NEXT:    br i1 [[CMP171]], label [[COND_TRUE172:%.*]], label [[COND_FALSE173:%.*]]
58713 // SIMD-ONLY0:       cond.true172:
58714 // SIMD-ONLY0-NEXT:    [[TMP177:%.*]] = load i32, ptr [[UID]], align 4
58715 // SIMD-ONLY0-NEXT:    br label [[COND_END174:%.*]]
58716 // SIMD-ONLY0:       cond.false173:
58717 // SIMD-ONLY0-NEXT:    [[TMP178:%.*]] = load i32, ptr [[UIX]], align 4
58718 // SIMD-ONLY0-NEXT:    br label [[COND_END174]]
58719 // SIMD-ONLY0:       cond.end174:
58720 // SIMD-ONLY0-NEXT:    [[COND175:%.*]] = phi i32 [ [[TMP177]], [[COND_TRUE172]] ], [ [[TMP178]], [[COND_FALSE173]] ]
58721 // SIMD-ONLY0-NEXT:    store i32 [[COND175]], ptr [[UIX]], align 4
58722 // SIMD-ONLY0-NEXT:    [[TMP179:%.*]] = load i32, ptr [[UIX]], align 4
58723 // SIMD-ONLY0-NEXT:    store i32 [[TMP179]], ptr [[UIV]], align 4
58724 // SIMD-ONLY0-NEXT:    [[TMP180:%.*]] = load i32, ptr [[UIV]], align 4
58725 // SIMD-ONLY0-NEXT:    ret i32 [[TMP180]]
58726 //
58727 //
58728 // SIMD-ONLY0-LABEL: @lxevd(
58729 // SIMD-ONLY0-NEXT:  entry:
58730 // SIMD-ONLY0-NEXT:    [[LX:%.*]] = alloca i64, align 8
58731 // SIMD-ONLY0-NEXT:    [[LV:%.*]] = alloca i64, align 8
58732 // SIMD-ONLY0-NEXT:    [[LE:%.*]] = alloca i64, align 8
58733 // SIMD-ONLY0-NEXT:    [[LD:%.*]] = alloca i64, align 8
58734 // SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = load i64, ptr [[LX]], align 8
58735 // SIMD-ONLY0-NEXT:    store i64 [[TMP0]], ptr [[LV]], align 8
58736 // SIMD-ONLY0-NEXT:    [[TMP1:%.*]] = load i64, ptr [[LX]], align 8
58737 // SIMD-ONLY0-NEXT:    [[TMP2:%.*]] = load i64, ptr [[LE]], align 8
58738 // SIMD-ONLY0-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP1]], [[TMP2]]
58739 // SIMD-ONLY0-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
58740 // SIMD-ONLY0:       cond.true:
58741 // SIMD-ONLY0-NEXT:    [[TMP3:%.*]] = load i64, ptr [[LE]], align 8
58742 // SIMD-ONLY0-NEXT:    br label [[COND_END:%.*]]
58743 // SIMD-ONLY0:       cond.false:
58744 // SIMD-ONLY0-NEXT:    [[TMP4:%.*]] = load i64, ptr [[LX]], align 8
58745 // SIMD-ONLY0-NEXT:    br label [[COND_END]]
58746 // SIMD-ONLY0:       cond.end:
58747 // SIMD-ONLY0-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP3]], [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
58748 // SIMD-ONLY0-NEXT:    store i64 [[COND]], ptr [[LX]], align 8
58749 // SIMD-ONLY0-NEXT:    [[TMP5:%.*]] = load i64, ptr [[LX]], align 8
58750 // SIMD-ONLY0-NEXT:    store i64 [[TMP5]], ptr [[LV]], align 8
58751 // SIMD-ONLY0-NEXT:    [[TMP6:%.*]] = load i64, ptr [[LX]], align 8
58752 // SIMD-ONLY0-NEXT:    [[TMP7:%.*]] = load i64, ptr [[LE]], align 8
58753 // SIMD-ONLY0-NEXT:    [[CMP1:%.*]] = icmp slt i64 [[TMP6]], [[TMP7]]
58754 // SIMD-ONLY0-NEXT:    br i1 [[CMP1]], label [[COND_TRUE2:%.*]], label [[COND_FALSE3:%.*]]
58755 // SIMD-ONLY0:       cond.true2:
58756 // SIMD-ONLY0-NEXT:    [[TMP8:%.*]] = load i64, ptr [[LE]], align 8
58757 // SIMD-ONLY0-NEXT:    br label [[COND_END4:%.*]]
58758 // SIMD-ONLY0:       cond.false3:
58759 // SIMD-ONLY0-NEXT:    [[TMP9:%.*]] = load i64, ptr [[LX]], align 8
58760 // SIMD-ONLY0-NEXT:    br label [[COND_END4]]
58761 // SIMD-ONLY0:       cond.end4:
58762 // SIMD-ONLY0-NEXT:    [[COND5:%.*]] = phi i64 [ [[TMP8]], [[COND_TRUE2]] ], [ [[TMP9]], [[COND_FALSE3]] ]
58763 // SIMD-ONLY0-NEXT:    store i64 [[COND5]], ptr [[LX]], align 8
58764 // SIMD-ONLY0-NEXT:    [[TMP10:%.*]] = load i64, ptr [[LX]], align 8
58765 // SIMD-ONLY0-NEXT:    store i64 [[TMP10]], ptr [[LV]], align 8
58766 // SIMD-ONLY0-NEXT:    [[TMP11:%.*]] = load i64, ptr [[LX]], align 8
58767 // SIMD-ONLY0-NEXT:    [[TMP12:%.*]] = load i64, ptr [[LE]], align 8
58768 // SIMD-ONLY0-NEXT:    [[CMP6:%.*]] = icmp eq i64 [[TMP11]], [[TMP12]]
58769 // SIMD-ONLY0-NEXT:    br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
58770 // SIMD-ONLY0:       cond.true7:
58771 // SIMD-ONLY0-NEXT:    [[TMP13:%.*]] = load i64, ptr [[LD]], align 8
58772 // SIMD-ONLY0-NEXT:    br label [[COND_END9:%.*]]
58773 // SIMD-ONLY0:       cond.false8:
58774 // SIMD-ONLY0-NEXT:    [[TMP14:%.*]] = load i64, ptr [[LX]], align 8
58775 // SIMD-ONLY0-NEXT:    br label [[COND_END9]]
58776 // SIMD-ONLY0:       cond.end9:
58777 // SIMD-ONLY0-NEXT:    [[COND10:%.*]] = phi i64 [ [[TMP13]], [[COND_TRUE7]] ], [ [[TMP14]], [[COND_FALSE8]] ]
58778 // SIMD-ONLY0-NEXT:    store i64 [[COND10]], ptr [[LX]], align 8
58779 // SIMD-ONLY0-NEXT:    [[TMP15:%.*]] = load i64, ptr [[LX]], align 8
58780 // SIMD-ONLY0-NEXT:    [[TMP16:%.*]] = load i64, ptr [[LE]], align 8
58781 // SIMD-ONLY0-NEXT:    [[CMP11:%.*]] = icmp sgt i64 [[TMP15]], [[TMP16]]
58782 // SIMD-ONLY0-NEXT:    br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
58783 // SIMD-ONLY0:       cond.true12:
58784 // SIMD-ONLY0-NEXT:    [[TMP17:%.*]] = load i64, ptr [[LE]], align 8
58785 // SIMD-ONLY0-NEXT:    br label [[COND_END14:%.*]]
58786 // SIMD-ONLY0:       cond.false13:
58787 // SIMD-ONLY0-NEXT:    [[TMP18:%.*]] = load i64, ptr [[LX]], align 8
58788 // SIMD-ONLY0-NEXT:    br label [[COND_END14]]
58789 // SIMD-ONLY0:       cond.end14:
58790 // SIMD-ONLY0-NEXT:    [[COND15:%.*]] = phi i64 [ [[TMP17]], [[COND_TRUE12]] ], [ [[TMP18]], [[COND_FALSE13]] ]
58791 // SIMD-ONLY0-NEXT:    store i64 [[COND15]], ptr [[LX]], align 8
58792 // SIMD-ONLY0-NEXT:    [[TMP19:%.*]] = load i64, ptr [[LX]], align 8
58793 // SIMD-ONLY0-NEXT:    store i64 [[TMP19]], ptr [[LV]], align 8
58794 // SIMD-ONLY0-NEXT:    [[TMP20:%.*]] = load i64, ptr [[LX]], align 8
58795 // SIMD-ONLY0-NEXT:    [[TMP21:%.*]] = load i64, ptr [[LE]], align 8
58796 // SIMD-ONLY0-NEXT:    [[CMP16:%.*]] = icmp slt i64 [[TMP20]], [[TMP21]]
58797 // SIMD-ONLY0-NEXT:    br i1 [[CMP16]], label [[COND_TRUE17:%.*]], label [[COND_FALSE18:%.*]]
58798 // SIMD-ONLY0:       cond.true17:
58799 // SIMD-ONLY0-NEXT:    [[TMP22:%.*]] = load i64, ptr [[LE]], align 8
58800 // SIMD-ONLY0-NEXT:    br label [[COND_END19:%.*]]
58801 // SIMD-ONLY0:       cond.false18:
58802 // SIMD-ONLY0-NEXT:    [[TMP23:%.*]] = load i64, ptr [[LX]], align 8
58803 // SIMD-ONLY0-NEXT:    br label [[COND_END19]]
58804 // SIMD-ONLY0:       cond.end19:
58805 // SIMD-ONLY0-NEXT:    [[COND20:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE17]] ], [ [[TMP23]], [[COND_FALSE18]] ]
58806 // SIMD-ONLY0-NEXT:    store i64 [[COND20]], ptr [[LX]], align 8
58807 // SIMD-ONLY0-NEXT:    [[TMP24:%.*]] = load i64, ptr [[LX]], align 8
58808 // SIMD-ONLY0-NEXT:    store i64 [[TMP24]], ptr [[LV]], align 8
58809 // SIMD-ONLY0-NEXT:    [[TMP25:%.*]] = load i64, ptr [[LX]], align 8
58810 // SIMD-ONLY0-NEXT:    [[TMP26:%.*]] = load i64, ptr [[LE]], align 8
58811 // SIMD-ONLY0-NEXT:    [[CMP21:%.*]] = icmp eq i64 [[TMP25]], [[TMP26]]
58812 // SIMD-ONLY0-NEXT:    br i1 [[CMP21]], label [[COND_TRUE22:%.*]], label [[COND_FALSE23:%.*]]
58813 // SIMD-ONLY0:       cond.true22:
58814 // SIMD-ONLY0-NEXT:    [[TMP27:%.*]] = load i64, ptr [[LD]], align 8
58815 // SIMD-ONLY0-NEXT:    br label [[COND_END24:%.*]]
58816 // SIMD-ONLY0:       cond.false23:
58817 // SIMD-ONLY0-NEXT:    [[TMP28:%.*]] = load i64, ptr [[LX]], align 8
58818 // SIMD-ONLY0-NEXT:    br label [[COND_END24]]
58819 // SIMD-ONLY0:       cond.end24:
58820 // SIMD-ONLY0-NEXT:    [[COND25:%.*]] = phi i64 [ [[TMP27]], [[COND_TRUE22]] ], [ [[TMP28]], [[COND_FALSE23]] ]
58821 // SIMD-ONLY0-NEXT:    store i64 [[COND25]], ptr [[LX]], align 8
58822 // SIMD-ONLY0-NEXT:    [[TMP29:%.*]] = load i64, ptr [[LX]], align 8
58823 // SIMD-ONLY0-NEXT:    store i64 [[TMP29]], ptr [[LV]], align 8
58824 // SIMD-ONLY0-NEXT:    [[TMP30:%.*]] = load i64, ptr [[LX]], align 8
58825 // SIMD-ONLY0-NEXT:    store i64 [[TMP30]], ptr [[LV]], align 8
58826 // SIMD-ONLY0-NEXT:    [[TMP31:%.*]] = load i64, ptr [[LX]], align 8
58827 // SIMD-ONLY0-NEXT:    [[TMP32:%.*]] = load i64, ptr [[LE]], align 8
58828 // SIMD-ONLY0-NEXT:    [[CMP26:%.*]] = icmp sgt i64 [[TMP31]], [[TMP32]]
58829 // SIMD-ONLY0-NEXT:    br i1 [[CMP26]], label [[COND_TRUE27:%.*]], label [[COND_FALSE28:%.*]]
58830 // SIMD-ONLY0:       cond.true27:
58831 // SIMD-ONLY0-NEXT:    [[TMP33:%.*]] = load i64, ptr [[LE]], align 8
58832 // SIMD-ONLY0-NEXT:    br label [[COND_END29:%.*]]
58833 // SIMD-ONLY0:       cond.false28:
58834 // SIMD-ONLY0-NEXT:    [[TMP34:%.*]] = load i64, ptr [[LX]], align 8
58835 // SIMD-ONLY0-NEXT:    br label [[COND_END29]]
58836 // SIMD-ONLY0:       cond.end29:
58837 // SIMD-ONLY0-NEXT:    [[COND30:%.*]] = phi i64 [ [[TMP33]], [[COND_TRUE27]] ], [ [[TMP34]], [[COND_FALSE28]] ]
58838 // SIMD-ONLY0-NEXT:    store i64 [[COND30]], ptr [[LX]], align 8
58839 // SIMD-ONLY0-NEXT:    [[TMP35:%.*]] = load i64, ptr [[LX]], align 8
58840 // SIMD-ONLY0-NEXT:    store i64 [[TMP35]], ptr [[LV]], align 8
58841 // SIMD-ONLY0-NEXT:    [[TMP36:%.*]] = load i64, ptr [[LX]], align 8
58842 // SIMD-ONLY0-NEXT:    [[TMP37:%.*]] = load i64, ptr [[LE]], align 8
58843 // SIMD-ONLY0-NEXT:    [[CMP31:%.*]] = icmp slt i64 [[TMP36]], [[TMP37]]
58844 // SIMD-ONLY0-NEXT:    br i1 [[CMP31]], label [[COND_TRUE32:%.*]], label [[COND_FALSE33:%.*]]
58845 // SIMD-ONLY0:       cond.true32:
58846 // SIMD-ONLY0-NEXT:    [[TMP38:%.*]] = load i64, ptr [[LE]], align 8
58847 // SIMD-ONLY0-NEXT:    br label [[COND_END34:%.*]]
58848 // SIMD-ONLY0:       cond.false33:
58849 // SIMD-ONLY0-NEXT:    [[TMP39:%.*]] = load i64, ptr [[LX]], align 8
58850 // SIMD-ONLY0-NEXT:    br label [[COND_END34]]
58851 // SIMD-ONLY0:       cond.end34:
58852 // SIMD-ONLY0-NEXT:    [[COND35:%.*]] = phi i64 [ [[TMP38]], [[COND_TRUE32]] ], [ [[TMP39]], [[COND_FALSE33]] ]
58853 // SIMD-ONLY0-NEXT:    store i64 [[COND35]], ptr [[LX]], align 8
58854 // SIMD-ONLY0-NEXT:    [[TMP40:%.*]] = load i64, ptr [[LX]], align 8
58855 // SIMD-ONLY0-NEXT:    store i64 [[TMP40]], ptr [[LV]], align 8
58856 // SIMD-ONLY0-NEXT:    [[TMP41:%.*]] = load i64, ptr [[LX]], align 8
58857 // SIMD-ONLY0-NEXT:    [[TMP42:%.*]] = load i64, ptr [[LE]], align 8
58858 // SIMD-ONLY0-NEXT:    [[CMP36:%.*]] = icmp eq i64 [[TMP41]], [[TMP42]]
58859 // SIMD-ONLY0-NEXT:    br i1 [[CMP36]], label [[COND_TRUE37:%.*]], label [[COND_FALSE38:%.*]]
58860 // SIMD-ONLY0:       cond.true37:
58861 // SIMD-ONLY0-NEXT:    [[TMP43:%.*]] = load i64, ptr [[LD]], align 8
58862 // SIMD-ONLY0-NEXT:    br label [[COND_END39:%.*]]
58863 // SIMD-ONLY0:       cond.false38:
58864 // SIMD-ONLY0-NEXT:    [[TMP44:%.*]] = load i64, ptr [[LX]], align 8
58865 // SIMD-ONLY0-NEXT:    br label [[COND_END39]]
58866 // SIMD-ONLY0:       cond.end39:
58867 // SIMD-ONLY0-NEXT:    [[COND40:%.*]] = phi i64 [ [[TMP43]], [[COND_TRUE37]] ], [ [[TMP44]], [[COND_FALSE38]] ]
58868 // SIMD-ONLY0-NEXT:    store i64 [[COND40]], ptr [[LX]], align 8
58869 // SIMD-ONLY0-NEXT:    [[TMP45:%.*]] = load i64, ptr [[LX]], align 8
58870 // SIMD-ONLY0-NEXT:    [[TMP46:%.*]] = load i64, ptr [[LE]], align 8
58871 // SIMD-ONLY0-NEXT:    [[CMP41:%.*]] = icmp sgt i64 [[TMP45]], [[TMP46]]
58872 // SIMD-ONLY0-NEXT:    br i1 [[CMP41]], label [[COND_TRUE42:%.*]], label [[COND_FALSE43:%.*]]
58873 // SIMD-ONLY0:       cond.true42:
58874 // SIMD-ONLY0-NEXT:    [[TMP47:%.*]] = load i64, ptr [[LE]], align 8
58875 // SIMD-ONLY0-NEXT:    br label [[COND_END44:%.*]]
58876 // SIMD-ONLY0:       cond.false43:
58877 // SIMD-ONLY0-NEXT:    [[TMP48:%.*]] = load i64, ptr [[LX]], align 8
58878 // SIMD-ONLY0-NEXT:    br label [[COND_END44]]
58879 // SIMD-ONLY0:       cond.end44:
58880 // SIMD-ONLY0-NEXT:    [[COND45:%.*]] = phi i64 [ [[TMP47]], [[COND_TRUE42]] ], [ [[TMP48]], [[COND_FALSE43]] ]
58881 // SIMD-ONLY0-NEXT:    store i64 [[COND45]], ptr [[LX]], align 8
58882 // SIMD-ONLY0-NEXT:    [[TMP49:%.*]] = load i64, ptr [[LX]], align 8
58883 // SIMD-ONLY0-NEXT:    store i64 [[TMP49]], ptr [[LV]], align 8
58884 // SIMD-ONLY0-NEXT:    [[TMP50:%.*]] = load i64, ptr [[LX]], align 8
58885 // SIMD-ONLY0-NEXT:    [[TMP51:%.*]] = load i64, ptr [[LE]], align 8
58886 // SIMD-ONLY0-NEXT:    [[CMP46:%.*]] = icmp slt i64 [[TMP50]], [[TMP51]]
58887 // SIMD-ONLY0-NEXT:    br i1 [[CMP46]], label [[COND_TRUE47:%.*]], label [[COND_FALSE48:%.*]]
58888 // SIMD-ONLY0:       cond.true47:
58889 // SIMD-ONLY0-NEXT:    [[TMP52:%.*]] = load i64, ptr [[LE]], align 8
58890 // SIMD-ONLY0-NEXT:    br label [[COND_END49:%.*]]
58891 // SIMD-ONLY0:       cond.false48:
58892 // SIMD-ONLY0-NEXT:    [[TMP53:%.*]] = load i64, ptr [[LX]], align 8
58893 // SIMD-ONLY0-NEXT:    br label [[COND_END49]]
58894 // SIMD-ONLY0:       cond.end49:
58895 // SIMD-ONLY0-NEXT:    [[COND50:%.*]] = phi i64 [ [[TMP52]], [[COND_TRUE47]] ], [ [[TMP53]], [[COND_FALSE48]] ]
58896 // SIMD-ONLY0-NEXT:    store i64 [[COND50]], ptr [[LX]], align 8
58897 // SIMD-ONLY0-NEXT:    [[TMP54:%.*]] = load i64, ptr [[LX]], align 8
58898 // SIMD-ONLY0-NEXT:    store i64 [[TMP54]], ptr [[LV]], align 8
58899 // SIMD-ONLY0-NEXT:    [[TMP55:%.*]] = load i64, ptr [[LX]], align 8
58900 // SIMD-ONLY0-NEXT:    [[TMP56:%.*]] = load i64, ptr [[LE]], align 8
58901 // SIMD-ONLY0-NEXT:    [[CMP51:%.*]] = icmp eq i64 [[TMP55]], [[TMP56]]
58902 // SIMD-ONLY0-NEXT:    br i1 [[CMP51]], label [[COND_TRUE52:%.*]], label [[COND_FALSE53:%.*]]
58903 // SIMD-ONLY0:       cond.true52:
58904 // SIMD-ONLY0-NEXT:    [[TMP57:%.*]] = load i64, ptr [[LD]], align 8
58905 // SIMD-ONLY0-NEXT:    br label [[COND_END54:%.*]]
58906 // SIMD-ONLY0:       cond.false53:
58907 // SIMD-ONLY0-NEXT:    [[TMP58:%.*]] = load i64, ptr [[LX]], align 8
58908 // SIMD-ONLY0-NEXT:    br label [[COND_END54]]
58909 // SIMD-ONLY0:       cond.end54:
58910 // SIMD-ONLY0-NEXT:    [[COND55:%.*]] = phi i64 [ [[TMP57]], [[COND_TRUE52]] ], [ [[TMP58]], [[COND_FALSE53]] ]
58911 // SIMD-ONLY0-NEXT:    store i64 [[COND55]], ptr [[LX]], align 8
58912 // SIMD-ONLY0-NEXT:    [[TMP59:%.*]] = load i64, ptr [[LX]], align 8
58913 // SIMD-ONLY0-NEXT:    store i64 [[TMP59]], ptr [[LV]], align 8
58914 // SIMD-ONLY0-NEXT:    [[TMP60:%.*]] = load i64, ptr [[LX]], align 8
58915 // SIMD-ONLY0-NEXT:    store i64 [[TMP60]], ptr [[LV]], align 8
58916 // SIMD-ONLY0-NEXT:    [[TMP61:%.*]] = load i64, ptr [[LX]], align 8
58917 // SIMD-ONLY0-NEXT:    [[TMP62:%.*]] = load i64, ptr [[LE]], align 8
58918 // SIMD-ONLY0-NEXT:    [[CMP56:%.*]] = icmp sgt i64 [[TMP61]], [[TMP62]]
58919 // SIMD-ONLY0-NEXT:    br i1 [[CMP56]], label [[COND_TRUE57:%.*]], label [[COND_FALSE58:%.*]]
58920 // SIMD-ONLY0:       cond.true57:
58921 // SIMD-ONLY0-NEXT:    [[TMP63:%.*]] = load i64, ptr [[LE]], align 8
58922 // SIMD-ONLY0-NEXT:    br label [[COND_END59:%.*]]
58923 // SIMD-ONLY0:       cond.false58:
58924 // SIMD-ONLY0-NEXT:    [[TMP64:%.*]] = load i64, ptr [[LX]], align 8
58925 // SIMD-ONLY0-NEXT:    br label [[COND_END59]]
58926 // SIMD-ONLY0:       cond.end59:
58927 // SIMD-ONLY0-NEXT:    [[COND60:%.*]] = phi i64 [ [[TMP63]], [[COND_TRUE57]] ], [ [[TMP64]], [[COND_FALSE58]] ]
58928 // SIMD-ONLY0-NEXT:    store i64 [[COND60]], ptr [[LX]], align 8
58929 // SIMD-ONLY0-NEXT:    [[TMP65:%.*]] = load i64, ptr [[LX]], align 8
58930 // SIMD-ONLY0-NEXT:    store i64 [[TMP65]], ptr [[LV]], align 8
58931 // SIMD-ONLY0-NEXT:    [[TMP66:%.*]] = load i64, ptr [[LX]], align 8
58932 // SIMD-ONLY0-NEXT:    [[TMP67:%.*]] = load i64, ptr [[LE]], align 8
58933 // SIMD-ONLY0-NEXT:    [[CMP61:%.*]] = icmp slt i64 [[TMP66]], [[TMP67]]
58934 // SIMD-ONLY0-NEXT:    br i1 [[CMP61]], label [[COND_TRUE62:%.*]], label [[COND_FALSE63:%.*]]
58935 // SIMD-ONLY0:       cond.true62:
58936 // SIMD-ONLY0-NEXT:    [[TMP68:%.*]] = load i64, ptr [[LE]], align 8
58937 // SIMD-ONLY0-NEXT:    br label [[COND_END64:%.*]]
58938 // SIMD-ONLY0:       cond.false63:
58939 // SIMD-ONLY0-NEXT:    [[TMP69:%.*]] = load i64, ptr [[LX]], align 8
58940 // SIMD-ONLY0-NEXT:    br label [[COND_END64]]
58941 // SIMD-ONLY0:       cond.end64:
58942 // SIMD-ONLY0-NEXT:    [[COND65:%.*]] = phi i64 [ [[TMP68]], [[COND_TRUE62]] ], [ [[TMP69]], [[COND_FALSE63]] ]
58943 // SIMD-ONLY0-NEXT:    store i64 [[COND65]], ptr [[LX]], align 8
58944 // SIMD-ONLY0-NEXT:    [[TMP70:%.*]] = load i64, ptr [[LX]], align 8
58945 // SIMD-ONLY0-NEXT:    store i64 [[TMP70]], ptr [[LV]], align 8
58946 // SIMD-ONLY0-NEXT:    [[TMP71:%.*]] = load i64, ptr [[LX]], align 8
58947 // SIMD-ONLY0-NEXT:    [[TMP72:%.*]] = load i64, ptr [[LE]], align 8
58948 // SIMD-ONLY0-NEXT:    [[CMP66:%.*]] = icmp eq i64 [[TMP71]], [[TMP72]]
58949 // SIMD-ONLY0-NEXT:    br i1 [[CMP66]], label [[COND_TRUE67:%.*]], label [[COND_FALSE68:%.*]]
58950 // SIMD-ONLY0:       cond.true67:
58951 // SIMD-ONLY0-NEXT:    [[TMP73:%.*]] = load i64, ptr [[LD]], align 8
58952 // SIMD-ONLY0-NEXT:    br label [[COND_END69:%.*]]
58953 // SIMD-ONLY0:       cond.false68:
58954 // SIMD-ONLY0-NEXT:    [[TMP74:%.*]] = load i64, ptr [[LX]], align 8
58955 // SIMD-ONLY0-NEXT:    br label [[COND_END69]]
58956 // SIMD-ONLY0:       cond.end69:
58957 // SIMD-ONLY0-NEXT:    [[COND70:%.*]] = phi i64 [ [[TMP73]], [[COND_TRUE67]] ], [ [[TMP74]], [[COND_FALSE68]] ]
58958 // SIMD-ONLY0-NEXT:    store i64 [[COND70]], ptr [[LX]], align 8
58959 // SIMD-ONLY0-NEXT:    [[TMP75:%.*]] = load i64, ptr [[LX]], align 8
58960 // SIMD-ONLY0-NEXT:    [[TMP76:%.*]] = load i64, ptr [[LE]], align 8
58961 // SIMD-ONLY0-NEXT:    [[CMP71:%.*]] = icmp sgt i64 [[TMP75]], [[TMP76]]
58962 // SIMD-ONLY0-NEXT:    br i1 [[CMP71]], label [[COND_TRUE72:%.*]], label [[COND_FALSE73:%.*]]
58963 // SIMD-ONLY0:       cond.true72:
58964 // SIMD-ONLY0-NEXT:    [[TMP77:%.*]] = load i64, ptr [[LE]], align 8
58965 // SIMD-ONLY0-NEXT:    br label [[COND_END74:%.*]]
58966 // SIMD-ONLY0:       cond.false73:
58967 // SIMD-ONLY0-NEXT:    [[TMP78:%.*]] = load i64, ptr [[LX]], align 8
58968 // SIMD-ONLY0-NEXT:    br label [[COND_END74]]
58969 // SIMD-ONLY0:       cond.end74:
58970 // SIMD-ONLY0-NEXT:    [[COND75:%.*]] = phi i64 [ [[TMP77]], [[COND_TRUE72]] ], [ [[TMP78]], [[COND_FALSE73]] ]
58971 // SIMD-ONLY0-NEXT:    store i64 [[COND75]], ptr [[LX]], align 8
58972 // SIMD-ONLY0-NEXT:    [[TMP79:%.*]] = load i64, ptr [[LX]], align 8
58973 // SIMD-ONLY0-NEXT:    store i64 [[TMP79]], ptr [[LV]], align 8
58974 // SIMD-ONLY0-NEXT:    [[TMP80:%.*]] = load i64, ptr [[LX]], align 8
58975 // SIMD-ONLY0-NEXT:    [[TMP81:%.*]] = load i64, ptr [[LE]], align 8
58976 // SIMD-ONLY0-NEXT:    [[CMP76:%.*]] = icmp slt i64 [[TMP80]], [[TMP81]]
58977 // SIMD-ONLY0-NEXT:    br i1 [[CMP76]], label [[COND_TRUE77:%.*]], label [[COND_FALSE78:%.*]]
58978 // SIMD-ONLY0:       cond.true77:
58979 // SIMD-ONLY0-NEXT:    [[TMP82:%.*]] = load i64, ptr [[LE]], align 8
58980 // SIMD-ONLY0-NEXT:    br label [[COND_END79:%.*]]
58981 // SIMD-ONLY0:       cond.false78:
58982 // SIMD-ONLY0-NEXT:    [[TMP83:%.*]] = load i64, ptr [[LX]], align 8
58983 // SIMD-ONLY0-NEXT:    br label [[COND_END79]]
58984 // SIMD-ONLY0:       cond.end79:
58985 // SIMD-ONLY0-NEXT:    [[COND80:%.*]] = phi i64 [ [[TMP82]], [[COND_TRUE77]] ], [ [[TMP83]], [[COND_FALSE78]] ]
58986 // SIMD-ONLY0-NEXT:    store i64 [[COND80]], ptr [[LX]], align 8
58987 // SIMD-ONLY0-NEXT:    [[TMP84:%.*]] = load i64, ptr [[LX]], align 8
58988 // SIMD-ONLY0-NEXT:    store i64 [[TMP84]], ptr [[LV]], align 8
58989 // SIMD-ONLY0-NEXT:    [[TMP85:%.*]] = load i64, ptr [[LX]], align 8
58990 // SIMD-ONLY0-NEXT:    [[TMP86:%.*]] = load i64, ptr [[LE]], align 8
58991 // SIMD-ONLY0-NEXT:    [[CMP81:%.*]] = icmp eq i64 [[TMP85]], [[TMP86]]
58992 // SIMD-ONLY0-NEXT:    br i1 [[CMP81]], label [[COND_TRUE82:%.*]], label [[COND_FALSE83:%.*]]
58993 // SIMD-ONLY0:       cond.true82:
58994 // SIMD-ONLY0-NEXT:    [[TMP87:%.*]] = load i64, ptr [[LD]], align 8
58995 // SIMD-ONLY0-NEXT:    br label [[COND_END84:%.*]]
58996 // SIMD-ONLY0:       cond.false83:
58997 // SIMD-ONLY0-NEXT:    [[TMP88:%.*]] = load i64, ptr [[LX]], align 8
58998 // SIMD-ONLY0-NEXT:    br label [[COND_END84]]
58999 // SIMD-ONLY0:       cond.end84:
59000 // SIMD-ONLY0-NEXT:    [[COND85:%.*]] = phi i64 [ [[TMP87]], [[COND_TRUE82]] ], [ [[TMP88]], [[COND_FALSE83]] ]
59001 // SIMD-ONLY0-NEXT:    store i64 [[COND85]], ptr [[LX]], align 8
59002 // SIMD-ONLY0-NEXT:    [[TMP89:%.*]] = load i64, ptr [[LX]], align 8
59003 // SIMD-ONLY0-NEXT:    store i64 [[TMP89]], ptr [[LV]], align 8
59004 // SIMD-ONLY0-NEXT:    [[TMP90:%.*]] = load i64, ptr [[LX]], align 8
59005 // SIMD-ONLY0-NEXT:    store i64 [[TMP90]], ptr [[LV]], align 8
59006 // SIMD-ONLY0-NEXT:    [[TMP91:%.*]] = load i64, ptr [[LX]], align 8
59007 // SIMD-ONLY0-NEXT:    [[TMP92:%.*]] = load i64, ptr [[LE]], align 8
59008 // SIMD-ONLY0-NEXT:    [[CMP86:%.*]] = icmp sgt i64 [[TMP91]], [[TMP92]]
59009 // SIMD-ONLY0-NEXT:    br i1 [[CMP86]], label [[COND_TRUE87:%.*]], label [[COND_FALSE88:%.*]]
59010 // SIMD-ONLY0:       cond.true87:
59011 // SIMD-ONLY0-NEXT:    [[TMP93:%.*]] = load i64, ptr [[LE]], align 8
59012 // SIMD-ONLY0-NEXT:    br label [[COND_END89:%.*]]
59013 // SIMD-ONLY0:       cond.false88:
59014 // SIMD-ONLY0-NEXT:    [[TMP94:%.*]] = load i64, ptr [[LX]], align 8
59015 // SIMD-ONLY0-NEXT:    br label [[COND_END89]]
59016 // SIMD-ONLY0:       cond.end89:
59017 // SIMD-ONLY0-NEXT:    [[COND90:%.*]] = phi i64 [ [[TMP93]], [[COND_TRUE87]] ], [ [[TMP94]], [[COND_FALSE88]] ]
59018 // SIMD-ONLY0-NEXT:    store i64 [[COND90]], ptr [[LX]], align 8
59019 // SIMD-ONLY0-NEXT:    [[TMP95:%.*]] = load i64, ptr [[LX]], align 8
59020 // SIMD-ONLY0-NEXT:    store i64 [[TMP95]], ptr [[LV]], align 8
59021 // SIMD-ONLY0-NEXT:    [[TMP96:%.*]] = load i64, ptr [[LX]], align 8
59022 // SIMD-ONLY0-NEXT:    [[TMP97:%.*]] = load i64, ptr [[LE]], align 8
59023 // SIMD-ONLY0-NEXT:    [[CMP91:%.*]] = icmp slt i64 [[TMP96]], [[TMP97]]
59024 // SIMD-ONLY0-NEXT:    br i1 [[CMP91]], label [[COND_TRUE92:%.*]], label [[COND_FALSE93:%.*]]
59025 // SIMD-ONLY0:       cond.true92:
59026 // SIMD-ONLY0-NEXT:    [[TMP98:%.*]] = load i64, ptr [[LE]], align 8
59027 // SIMD-ONLY0-NEXT:    br label [[COND_END94:%.*]]
59028 // SIMD-ONLY0:       cond.false93:
59029 // SIMD-ONLY0-NEXT:    [[TMP99:%.*]] = load i64, ptr [[LX]], align 8
59030 // SIMD-ONLY0-NEXT:    br label [[COND_END94]]
59031 // SIMD-ONLY0:       cond.end94:
59032 // SIMD-ONLY0-NEXT:    [[COND95:%.*]] = phi i64 [ [[TMP98]], [[COND_TRUE92]] ], [ [[TMP99]], [[COND_FALSE93]] ]
59033 // SIMD-ONLY0-NEXT:    store i64 [[COND95]], ptr [[LX]], align 8
59034 // SIMD-ONLY0-NEXT:    [[TMP100:%.*]] = load i64, ptr [[LX]], align 8
59035 // SIMD-ONLY0-NEXT:    store i64 [[TMP100]], ptr [[LV]], align 8
59036 // SIMD-ONLY0-NEXT:    [[TMP101:%.*]] = load i64, ptr [[LX]], align 8
59037 // SIMD-ONLY0-NEXT:    [[TMP102:%.*]] = load i64, ptr [[LE]], align 8
59038 // SIMD-ONLY0-NEXT:    [[CMP96:%.*]] = icmp eq i64 [[TMP101]], [[TMP102]]
59039 // SIMD-ONLY0-NEXT:    br i1 [[CMP96]], label [[COND_TRUE97:%.*]], label [[COND_FALSE98:%.*]]
59040 // SIMD-ONLY0:       cond.true97:
59041 // SIMD-ONLY0-NEXT:    [[TMP103:%.*]] = load i64, ptr [[LD]], align 8
59042 // SIMD-ONLY0-NEXT:    br label [[COND_END99:%.*]]
59043 // SIMD-ONLY0:       cond.false98:
59044 // SIMD-ONLY0-NEXT:    [[TMP104:%.*]] = load i64, ptr [[LX]], align 8
59045 // SIMD-ONLY0-NEXT:    br label [[COND_END99]]
59046 // SIMD-ONLY0:       cond.end99:
59047 // SIMD-ONLY0-NEXT:    [[COND100:%.*]] = phi i64 [ [[TMP103]], [[COND_TRUE97]] ], [ [[TMP104]], [[COND_FALSE98]] ]
59048 // SIMD-ONLY0-NEXT:    store i64 [[COND100]], ptr [[LX]], align 8
59049 // SIMD-ONLY0-NEXT:    [[TMP105:%.*]] = load i64, ptr [[LX]], align 8
59050 // SIMD-ONLY0-NEXT:    [[TMP106:%.*]] = load i64, ptr [[LE]], align 8
59051 // SIMD-ONLY0-NEXT:    [[CMP101:%.*]] = icmp sgt i64 [[TMP105]], [[TMP106]]
59052 // SIMD-ONLY0-NEXT:    br i1 [[CMP101]], label [[COND_TRUE102:%.*]], label [[COND_FALSE103:%.*]]
59053 // SIMD-ONLY0:       cond.true102:
59054 // SIMD-ONLY0-NEXT:    [[TMP107:%.*]] = load i64, ptr [[LE]], align 8
59055 // SIMD-ONLY0-NEXT:    br label [[COND_END104:%.*]]
59056 // SIMD-ONLY0:       cond.false103:
59057 // SIMD-ONLY0-NEXT:    [[TMP108:%.*]] = load i64, ptr [[LX]], align 8
59058 // SIMD-ONLY0-NEXT:    br label [[COND_END104]]
59059 // SIMD-ONLY0:       cond.end104:
59060 // SIMD-ONLY0-NEXT:    [[COND105:%.*]] = phi i64 [ [[TMP107]], [[COND_TRUE102]] ], [ [[TMP108]], [[COND_FALSE103]] ]
59061 // SIMD-ONLY0-NEXT:    store i64 [[COND105]], ptr [[LX]], align 8
59062 // SIMD-ONLY0-NEXT:    [[TMP109:%.*]] = load i64, ptr [[LX]], align 8
59063 // SIMD-ONLY0-NEXT:    store i64 [[TMP109]], ptr [[LV]], align 8
59064 // SIMD-ONLY0-NEXT:    [[TMP110:%.*]] = load i64, ptr [[LX]], align 8
59065 // SIMD-ONLY0-NEXT:    [[TMP111:%.*]] = load i64, ptr [[LE]], align 8
59066 // SIMD-ONLY0-NEXT:    [[CMP106:%.*]] = icmp slt i64 [[TMP110]], [[TMP111]]
59067 // SIMD-ONLY0-NEXT:    br i1 [[CMP106]], label [[COND_TRUE107:%.*]], label [[COND_FALSE108:%.*]]
59068 // SIMD-ONLY0:       cond.true107:
59069 // SIMD-ONLY0-NEXT:    [[TMP112:%.*]] = load i64, ptr [[LE]], align 8
59070 // SIMD-ONLY0-NEXT:    br label [[COND_END109:%.*]]
59071 // SIMD-ONLY0:       cond.false108:
59072 // SIMD-ONLY0-NEXT:    [[TMP113:%.*]] = load i64, ptr [[LX]], align 8
59073 // SIMD-ONLY0-NEXT:    br label [[COND_END109]]
59074 // SIMD-ONLY0:       cond.end109:
59075 // SIMD-ONLY0-NEXT:    [[COND110:%.*]] = phi i64 [ [[TMP112]], [[COND_TRUE107]] ], [ [[TMP113]], [[COND_FALSE108]] ]
59076 // SIMD-ONLY0-NEXT:    store i64 [[COND110]], ptr [[LX]], align 8
59077 // SIMD-ONLY0-NEXT:    [[TMP114:%.*]] = load i64, ptr [[LX]], align 8
59078 // SIMD-ONLY0-NEXT:    store i64 [[TMP114]], ptr [[LV]], align 8
59079 // SIMD-ONLY0-NEXT:    [[TMP115:%.*]] = load i64, ptr [[LX]], align 8
59080 // SIMD-ONLY0-NEXT:    [[TMP116:%.*]] = load i64, ptr [[LE]], align 8
59081 // SIMD-ONLY0-NEXT:    [[CMP111:%.*]] = icmp eq i64 [[TMP115]], [[TMP116]]
59082 // SIMD-ONLY0-NEXT:    br i1 [[CMP111]], label [[COND_TRUE112:%.*]], label [[COND_FALSE113:%.*]]
59083 // SIMD-ONLY0:       cond.true112:
59084 // SIMD-ONLY0-NEXT:    [[TMP117:%.*]] = load i64, ptr [[LD]], align 8
59085 // SIMD-ONLY0-NEXT:    br label [[COND_END114:%.*]]
59086 // SIMD-ONLY0:       cond.false113:
59087 // SIMD-ONLY0-NEXT:    [[TMP118:%.*]] = load i64, ptr [[LX]], align 8
59088 // SIMD-ONLY0-NEXT:    br label [[COND_END114]]
59089 // SIMD-ONLY0:       cond.end114:
59090 // SIMD-ONLY0-NEXT:    [[COND115:%.*]] = phi i64 [ [[TMP117]], [[COND_TRUE112]] ], [ [[TMP118]], [[COND_FALSE113]] ]
59091 // SIMD-ONLY0-NEXT:    store i64 [[COND115]], ptr [[LX]], align 8
59092 // SIMD-ONLY0-NEXT:    [[TMP119:%.*]] = load i64, ptr [[LX]], align 8
59093 // SIMD-ONLY0-NEXT:    store i64 [[TMP119]], ptr [[LV]], align 8
59094 // SIMD-ONLY0-NEXT:    [[TMP120:%.*]] = load i64, ptr [[LX]], align 8
59095 // SIMD-ONLY0-NEXT:    store i64 [[TMP120]], ptr [[LV]], align 8
59096 // SIMD-ONLY0-NEXT:    [[TMP121:%.*]] = load i64, ptr [[LX]], align 8
59097 // SIMD-ONLY0-NEXT:    [[TMP122:%.*]] = load i64, ptr [[LE]], align 8
59098 // SIMD-ONLY0-NEXT:    [[CMP116:%.*]] = icmp sgt i64 [[TMP121]], [[TMP122]]
59099 // SIMD-ONLY0-NEXT:    br i1 [[CMP116]], label [[COND_TRUE117:%.*]], label [[COND_FALSE118:%.*]]
59100 // SIMD-ONLY0:       cond.true117:
59101 // SIMD-ONLY0-NEXT:    [[TMP123:%.*]] = load i64, ptr [[LE]], align 8
59102 // SIMD-ONLY0-NEXT:    br label [[COND_END119:%.*]]
59103 // SIMD-ONLY0:       cond.false118:
59104 // SIMD-ONLY0-NEXT:    [[TMP124:%.*]] = load i64, ptr [[LX]], align 8
59105 // SIMD-ONLY0-NEXT:    br label [[COND_END119]]
59106 // SIMD-ONLY0:       cond.end119:
59107 // SIMD-ONLY0-NEXT:    [[COND120:%.*]] = phi i64 [ [[TMP123]], [[COND_TRUE117]] ], [ [[TMP124]], [[COND_FALSE118]] ]
59108 // SIMD-ONLY0-NEXT:    store i64 [[COND120]], ptr [[LX]], align 8
59109 // SIMD-ONLY0-NEXT:    [[TMP125:%.*]] = load i64, ptr [[LX]], align 8
59110 // SIMD-ONLY0-NEXT:    store i64 [[TMP125]], ptr [[LV]], align 8
59111 // SIMD-ONLY0-NEXT:    [[TMP126:%.*]] = load i64, ptr [[LX]], align 8
59112 // SIMD-ONLY0-NEXT:    [[TMP127:%.*]] = load i64, ptr [[LE]], align 8
59113 // SIMD-ONLY0-NEXT:    [[CMP121:%.*]] = icmp slt i64 [[TMP126]], [[TMP127]]
59114 // SIMD-ONLY0-NEXT:    br i1 [[CMP121]], label [[COND_TRUE122:%.*]], label [[COND_FALSE123:%.*]]
59115 // SIMD-ONLY0:       cond.true122:
59116 // SIMD-ONLY0-NEXT:    [[TMP128:%.*]] = load i64, ptr [[LE]], align 8
59117 // SIMD-ONLY0-NEXT:    br label [[COND_END124:%.*]]
59118 // SIMD-ONLY0:       cond.false123:
59119 // SIMD-ONLY0-NEXT:    [[TMP129:%.*]] = load i64, ptr [[LX]], align 8
59120 // SIMD-ONLY0-NEXT:    br label [[COND_END124]]
59121 // SIMD-ONLY0:       cond.end124:
59122 // SIMD-ONLY0-NEXT:    [[COND125:%.*]] = phi i64 [ [[TMP128]], [[COND_TRUE122]] ], [ [[TMP129]], [[COND_FALSE123]] ]
59123 // SIMD-ONLY0-NEXT:    store i64 [[COND125]], ptr [[LX]], align 8
59124 // SIMD-ONLY0-NEXT:    [[TMP130:%.*]] = load i64, ptr [[LX]], align 8
59125 // SIMD-ONLY0-NEXT:    store i64 [[TMP130]], ptr [[LV]], align 8
59126 // SIMD-ONLY0-NEXT:    [[TMP131:%.*]] = load i64, ptr [[LX]], align 8
59127 // SIMD-ONLY0-NEXT:    [[TMP132:%.*]] = load i64, ptr [[LE]], align 8
59128 // SIMD-ONLY0-NEXT:    [[CMP126:%.*]] = icmp eq i64 [[TMP131]], [[TMP132]]
59129 // SIMD-ONLY0-NEXT:    br i1 [[CMP126]], label [[COND_TRUE127:%.*]], label [[COND_FALSE128:%.*]]
59130 // SIMD-ONLY0:       cond.true127:
59131 // SIMD-ONLY0-NEXT:    [[TMP133:%.*]] = load i64, ptr [[LD]], align 8
59132 // SIMD-ONLY0-NEXT:    br label [[COND_END129:%.*]]
59133 // SIMD-ONLY0:       cond.false128:
59134 // SIMD-ONLY0-NEXT:    [[TMP134:%.*]] = load i64, ptr [[LX]], align 8
59135 // SIMD-ONLY0-NEXT:    br label [[COND_END129]]
59136 // SIMD-ONLY0:       cond.end129:
59137 // SIMD-ONLY0-NEXT:    [[COND130:%.*]] = phi i64 [ [[TMP133]], [[COND_TRUE127]] ], [ [[TMP134]], [[COND_FALSE128]] ]
59138 // SIMD-ONLY0-NEXT:    store i64 [[COND130]], ptr [[LX]], align 8
59139 // SIMD-ONLY0-NEXT:    [[TMP135:%.*]] = load i64, ptr [[LX]], align 8
59140 // SIMD-ONLY0-NEXT:    [[TMP136:%.*]] = load i64, ptr [[LE]], align 8
59141 // SIMD-ONLY0-NEXT:    [[CMP131:%.*]] = icmp sgt i64 [[TMP135]], [[TMP136]]
59142 // SIMD-ONLY0-NEXT:    br i1 [[CMP131]], label [[COND_TRUE132:%.*]], label [[COND_FALSE133:%.*]]
59143 // SIMD-ONLY0:       cond.true132:
59144 // SIMD-ONLY0-NEXT:    [[TMP137:%.*]] = load i64, ptr [[LE]], align 8
59145 // SIMD-ONLY0-NEXT:    br label [[COND_END134:%.*]]
59146 // SIMD-ONLY0:       cond.false133:
59147 // SIMD-ONLY0-NEXT:    [[TMP138:%.*]] = load i64, ptr [[LX]], align 8
59148 // SIMD-ONLY0-NEXT:    br label [[COND_END134]]
59149 // SIMD-ONLY0:       cond.end134:
59150 // SIMD-ONLY0-NEXT:    [[COND135:%.*]] = phi i64 [ [[TMP137]], [[COND_TRUE132]] ], [ [[TMP138]], [[COND_FALSE133]] ]
59151 // SIMD-ONLY0-NEXT:    store i64 [[COND135]], ptr [[LX]], align 8
59152 // SIMD-ONLY0-NEXT:    [[TMP139:%.*]] = load i64, ptr [[LX]], align 8
59153 // SIMD-ONLY0-NEXT:    store i64 [[TMP139]], ptr [[LV]], align 8
59154 // SIMD-ONLY0-NEXT:    [[TMP140:%.*]] = load i64, ptr [[LX]], align 8
59155 // SIMD-ONLY0-NEXT:    [[TMP141:%.*]] = load i64, ptr [[LE]], align 8
59156 // SIMD-ONLY0-NEXT:    [[CMP136:%.*]] = icmp slt i64 [[TMP140]], [[TMP141]]
59157 // SIMD-ONLY0-NEXT:    br i1 [[CMP136]], label [[COND_TRUE137:%.*]], label [[COND_FALSE138:%.*]]
59158 // SIMD-ONLY0:       cond.true137:
59159 // SIMD-ONLY0-NEXT:    [[TMP142:%.*]] = load i64, ptr [[LE]], align 8
59160 // SIMD-ONLY0-NEXT:    br label [[COND_END139:%.*]]
59161 // SIMD-ONLY0:       cond.false138:
59162 // SIMD-ONLY0-NEXT:    [[TMP143:%.*]] = load i64, ptr [[LX]], align 8
59163 // SIMD-ONLY0-NEXT:    br label [[COND_END139]]
59164 // SIMD-ONLY0:       cond.end139:
59165 // SIMD-ONLY0-NEXT:    [[COND140:%.*]] = phi i64 [ [[TMP142]], [[COND_TRUE137]] ], [ [[TMP143]], [[COND_FALSE138]] ]
59166 // SIMD-ONLY0-NEXT:    store i64 [[COND140]], ptr [[LX]], align 8
59167 // SIMD-ONLY0-NEXT:    [[TMP144:%.*]] = load i64, ptr [[LX]], align 8
59168 // SIMD-ONLY0-NEXT:    store i64 [[TMP144]], ptr [[LV]], align 8
59169 // SIMD-ONLY0-NEXT:    [[TMP145:%.*]] = load i64, ptr [[LX]], align 8
59170 // SIMD-ONLY0-NEXT:    [[TMP146:%.*]] = load i64, ptr [[LE]], align 8
59171 // SIMD-ONLY0-NEXT:    [[CMP141:%.*]] = icmp eq i64 [[TMP145]], [[TMP146]]
59172 // SIMD-ONLY0-NEXT:    br i1 [[CMP141]], label [[COND_TRUE142:%.*]], label [[COND_FALSE143:%.*]]
59173 // SIMD-ONLY0:       cond.true142:
59174 // SIMD-ONLY0-NEXT:    [[TMP147:%.*]] = load i64, ptr [[LD]], align 8
59175 // SIMD-ONLY0-NEXT:    br label [[COND_END144:%.*]]
59176 // SIMD-ONLY0:       cond.false143:
59177 // SIMD-ONLY0-NEXT:    [[TMP148:%.*]] = load i64, ptr [[LX]], align 8
59178 // SIMD-ONLY0-NEXT:    br label [[COND_END144]]
59179 // SIMD-ONLY0:       cond.end144:
59180 // SIMD-ONLY0-NEXT:    [[COND145:%.*]] = phi i64 [ [[TMP147]], [[COND_TRUE142]] ], [ [[TMP148]], [[COND_FALSE143]] ]
59181 // SIMD-ONLY0-NEXT:    store i64 [[COND145]], ptr [[LX]], align 8
59182 // SIMD-ONLY0-NEXT:    [[TMP149:%.*]] = load i64, ptr [[LX]], align 8
59183 // SIMD-ONLY0-NEXT:    store i64 [[TMP149]], ptr [[LV]], align 8
59184 // SIMD-ONLY0-NEXT:    [[TMP150:%.*]] = load i64, ptr [[LX]], align 8
59185 // SIMD-ONLY0-NEXT:    store i64 [[TMP150]], ptr [[LV]], align 8
59186 // SIMD-ONLY0-NEXT:    [[TMP151:%.*]] = load i64, ptr [[LX]], align 8
59187 // SIMD-ONLY0-NEXT:    [[TMP152:%.*]] = load i64, ptr [[LE]], align 8
59188 // SIMD-ONLY0-NEXT:    [[CMP146:%.*]] = icmp sgt i64 [[TMP151]], [[TMP152]]
59189 // SIMD-ONLY0-NEXT:    br i1 [[CMP146]], label [[COND_TRUE147:%.*]], label [[COND_FALSE148:%.*]]
59190 // SIMD-ONLY0:       cond.true147:
59191 // SIMD-ONLY0-NEXT:    [[TMP153:%.*]] = load i64, ptr [[LE]], align 8
59192 // SIMD-ONLY0-NEXT:    br label [[COND_END149:%.*]]
59193 // SIMD-ONLY0:       cond.false148:
59194 // SIMD-ONLY0-NEXT:    [[TMP154:%.*]] = load i64, ptr [[LX]], align 8
59195 // SIMD-ONLY0-NEXT:    br label [[COND_END149]]
59196 // SIMD-ONLY0:       cond.end149:
59197 // SIMD-ONLY0-NEXT:    [[COND150:%.*]] = phi i64 [ [[TMP153]], [[COND_TRUE147]] ], [ [[TMP154]], [[COND_FALSE148]] ]
59198 // SIMD-ONLY0-NEXT:    store i64 [[COND150]], ptr [[LX]], align 8
59199 // SIMD-ONLY0-NEXT:    [[TMP155:%.*]] = load i64, ptr [[LX]], align 8
59200 // SIMD-ONLY0-NEXT:    store i64 [[TMP155]], ptr [[LV]], align 8
59201 // SIMD-ONLY0-NEXT:    [[TMP156:%.*]] = load i64, ptr [[LX]], align 8
59202 // SIMD-ONLY0-NEXT:    [[TMP157:%.*]] = load i64, ptr [[LE]], align 8
59203 // SIMD-ONLY0-NEXT:    [[CMP151:%.*]] = icmp slt i64 [[TMP156]], [[TMP157]]
59204 // SIMD-ONLY0-NEXT:    br i1 [[CMP151]], label [[COND_TRUE152:%.*]], label [[COND_FALSE153:%.*]]
59205 // SIMD-ONLY0:       cond.true152:
59206 // SIMD-ONLY0-NEXT:    [[TMP158:%.*]] = load i64, ptr [[LE]], align 8
59207 // SIMD-ONLY0-NEXT:    br label [[COND_END154:%.*]]
59208 // SIMD-ONLY0:       cond.false153:
59209 // SIMD-ONLY0-NEXT:    [[TMP159:%.*]] = load i64, ptr [[LX]], align 8
59210 // SIMD-ONLY0-NEXT:    br label [[COND_END154]]
59211 // SIMD-ONLY0:       cond.end154:
59212 // SIMD-ONLY0-NEXT:    [[COND155:%.*]] = phi i64 [ [[TMP158]], [[COND_TRUE152]] ], [ [[TMP159]], [[COND_FALSE153]] ]
59213 // SIMD-ONLY0-NEXT:    store i64 [[COND155]], ptr [[LX]], align 8
59214 // SIMD-ONLY0-NEXT:    [[TMP160:%.*]] = load i64, ptr [[LX]], align 8
59215 // SIMD-ONLY0-NEXT:    store i64 [[TMP160]], ptr [[LV]], align 8
59216 // SIMD-ONLY0-NEXT:    [[TMP161:%.*]] = load i64, ptr [[LX]], align 8
59217 // SIMD-ONLY0-NEXT:    [[TMP162:%.*]] = load i64, ptr [[LE]], align 8
59218 // SIMD-ONLY0-NEXT:    [[CMP156:%.*]] = icmp eq i64 [[TMP161]], [[TMP162]]
59219 // SIMD-ONLY0-NEXT:    br i1 [[CMP156]], label [[COND_TRUE157:%.*]], label [[COND_FALSE158:%.*]]
59220 // SIMD-ONLY0:       cond.true157:
59221 // SIMD-ONLY0-NEXT:    [[TMP163:%.*]] = load i64, ptr [[LD]], align 8
59222 // SIMD-ONLY0-NEXT:    br label [[COND_END159:%.*]]
59223 // SIMD-ONLY0:       cond.false158:
59224 // SIMD-ONLY0-NEXT:    [[TMP164:%.*]] = load i64, ptr [[LX]], align 8
59225 // SIMD-ONLY0-NEXT:    br label [[COND_END159]]
59226 // SIMD-ONLY0:       cond.end159:
59227 // SIMD-ONLY0-NEXT:    [[COND160:%.*]] = phi i64 [ [[TMP163]], [[COND_TRUE157]] ], [ [[TMP164]], [[COND_FALSE158]] ]
59228 // SIMD-ONLY0-NEXT:    store i64 [[COND160]], ptr [[LX]], align 8
59229 // SIMD-ONLY0-NEXT:    [[TMP165:%.*]] = load i64, ptr [[LX]], align 8
59230 // SIMD-ONLY0-NEXT:    [[TMP166:%.*]] = load i64, ptr [[LE]], align 8
59231 // SIMD-ONLY0-NEXT:    [[CMP161:%.*]] = icmp sgt i64 [[TMP165]], [[TMP166]]
59232 // SIMD-ONLY0-NEXT:    br i1 [[CMP161]], label [[COND_TRUE162:%.*]], label [[COND_FALSE163:%.*]]
59233 // SIMD-ONLY0:       cond.true162:
59234 // SIMD-ONLY0-NEXT:    [[TMP167:%.*]] = load i64, ptr [[LE]], align 8
59235 // SIMD-ONLY0-NEXT:    br label [[COND_END164:%.*]]
59236 // SIMD-ONLY0:       cond.false163:
59237 // SIMD-ONLY0-NEXT:    [[TMP168:%.*]] = load i64, ptr [[LX]], align 8
59238 // SIMD-ONLY0-NEXT:    br label [[COND_END164]]
59239 // SIMD-ONLY0:       cond.end164:
59240 // SIMD-ONLY0-NEXT:    [[COND165:%.*]] = phi i64 [ [[TMP167]], [[COND_TRUE162]] ], [ [[TMP168]], [[COND_FALSE163]] ]
59241 // SIMD-ONLY0-NEXT:    store i64 [[COND165]], ptr [[LX]], align 8
59242 // SIMD-ONLY0-NEXT:    [[TMP169:%.*]] = load i64, ptr [[LX]], align 8
59243 // SIMD-ONLY0-NEXT:    store i64 [[TMP169]], ptr [[LV]], align 8
59244 // SIMD-ONLY0-NEXT:    [[TMP170:%.*]] = load i64, ptr [[LX]], align 8
59245 // SIMD-ONLY0-NEXT:    [[TMP171:%.*]] = load i64, ptr [[LE]], align 8
59246 // SIMD-ONLY0-NEXT:    [[CMP166:%.*]] = icmp slt i64 [[TMP170]], [[TMP171]]
59247 // SIMD-ONLY0-NEXT:    br i1 [[CMP166]], label [[COND_TRUE167:%.*]], label [[COND_FALSE168:%.*]]
59248 // SIMD-ONLY0:       cond.true167:
59249 // SIMD-ONLY0-NEXT:    [[TMP172:%.*]] = load i64, ptr [[LE]], align 8
59250 // SIMD-ONLY0-NEXT:    br label [[COND_END169:%.*]]
59251 // SIMD-ONLY0:       cond.false168:
59252 // SIMD-ONLY0-NEXT:    [[TMP173:%.*]] = load i64, ptr [[LX]], align 8
59253 // SIMD-ONLY0-NEXT:    br label [[COND_END169]]
59254 // SIMD-ONLY0:       cond.end169:
59255 // SIMD-ONLY0-NEXT:    [[COND170:%.*]] = phi i64 [ [[TMP172]], [[COND_TRUE167]] ], [ [[TMP173]], [[COND_FALSE168]] ]
59256 // SIMD-ONLY0-NEXT:    store i64 [[COND170]], ptr [[LX]], align 8
59257 // SIMD-ONLY0-NEXT:    [[TMP174:%.*]] = load i64, ptr [[LX]], align 8
59258 // SIMD-ONLY0-NEXT:    store i64 [[TMP174]], ptr [[LV]], align 8
59259 // SIMD-ONLY0-NEXT:    [[TMP175:%.*]] = load i64, ptr [[LX]], align 8
59260 // SIMD-ONLY0-NEXT:    [[TMP176:%.*]] = load i64, ptr [[LE]], align 8
59261 // SIMD-ONLY0-NEXT:    [[CMP171:%.*]] = icmp eq i64 [[TMP175]], [[TMP176]]
59262 // SIMD-ONLY0-NEXT:    br i1 [[CMP171]], label [[COND_TRUE172:%.*]], label [[COND_FALSE173:%.*]]
59263 // SIMD-ONLY0:       cond.true172:
59264 // SIMD-ONLY0-NEXT:    [[TMP177:%.*]] = load i64, ptr [[LD]], align 8
59265 // SIMD-ONLY0-NEXT:    br label [[COND_END174:%.*]]
59266 // SIMD-ONLY0:       cond.false173:
59267 // SIMD-ONLY0-NEXT:    [[TMP178:%.*]] = load i64, ptr [[LX]], align 8
59268 // SIMD-ONLY0-NEXT:    br label [[COND_END174]]
59269 // SIMD-ONLY0:       cond.end174:
59270 // SIMD-ONLY0-NEXT:    [[COND175:%.*]] = phi i64 [ [[TMP177]], [[COND_TRUE172]] ], [ [[TMP178]], [[COND_FALSE173]] ]
59271 // SIMD-ONLY0-NEXT:    store i64 [[COND175]], ptr [[LX]], align 8
59272 // SIMD-ONLY0-NEXT:    [[TMP179:%.*]] = load i64, ptr [[LX]], align 8
59273 // SIMD-ONLY0-NEXT:    store i64 [[TMP179]], ptr [[LV]], align 8
59274 // SIMD-ONLY0-NEXT:    [[TMP180:%.*]] = load i64, ptr [[LV]], align 8
59275 // SIMD-ONLY0-NEXT:    ret i64 [[TMP180]]
59276 //
59277 //
59278 // SIMD-ONLY0-LABEL: @ulxevd(
59279 // SIMD-ONLY0-NEXT:  entry:
59280 // SIMD-ONLY0-NEXT:    [[ULX:%.*]] = alloca i64, align 8
59281 // SIMD-ONLY0-NEXT:    [[ULV:%.*]] = alloca i64, align 8
59282 // SIMD-ONLY0-NEXT:    [[ULE:%.*]] = alloca i64, align 8
59283 // SIMD-ONLY0-NEXT:    [[ULD:%.*]] = alloca i64, align 8
59284 // SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = load i64, ptr [[ULX]], align 8
59285 // SIMD-ONLY0-NEXT:    store i64 [[TMP0]], ptr [[ULV]], align 8
59286 // SIMD-ONLY0-NEXT:    [[TMP1:%.*]] = load i64, ptr [[ULX]], align 8
59287 // SIMD-ONLY0-NEXT:    [[TMP2:%.*]] = load i64, ptr [[ULE]], align 8
59288 // SIMD-ONLY0-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP1]], [[TMP2]]
59289 // SIMD-ONLY0-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
59290 // SIMD-ONLY0:       cond.true:
59291 // SIMD-ONLY0-NEXT:    [[TMP3:%.*]] = load i64, ptr [[ULE]], align 8
59292 // SIMD-ONLY0-NEXT:    br label [[COND_END:%.*]]
59293 // SIMD-ONLY0:       cond.false:
59294 // SIMD-ONLY0-NEXT:    [[TMP4:%.*]] = load i64, ptr [[ULX]], align 8
59295 // SIMD-ONLY0-NEXT:    br label [[COND_END]]
59296 // SIMD-ONLY0:       cond.end:
59297 // SIMD-ONLY0-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP3]], [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
59298 // SIMD-ONLY0-NEXT:    store i64 [[COND]], ptr [[ULX]], align 8
59299 // SIMD-ONLY0-NEXT:    [[TMP5:%.*]] = load i64, ptr [[ULX]], align 8
59300 // SIMD-ONLY0-NEXT:    store i64 [[TMP5]], ptr [[ULV]], align 8
59301 // SIMD-ONLY0-NEXT:    [[TMP6:%.*]] = load i64, ptr [[ULX]], align 8
59302 // SIMD-ONLY0-NEXT:    [[TMP7:%.*]] = load i64, ptr [[ULE]], align 8
59303 // SIMD-ONLY0-NEXT:    [[CMP1:%.*]] = icmp ult i64 [[TMP6]], [[TMP7]]
59304 // SIMD-ONLY0-NEXT:    br i1 [[CMP1]], label [[COND_TRUE2:%.*]], label [[COND_FALSE3:%.*]]
59305 // SIMD-ONLY0:       cond.true2:
59306 // SIMD-ONLY0-NEXT:    [[TMP8:%.*]] = load i64, ptr [[ULE]], align 8
59307 // SIMD-ONLY0-NEXT:    br label [[COND_END4:%.*]]
59308 // SIMD-ONLY0:       cond.false3:
59309 // SIMD-ONLY0-NEXT:    [[TMP9:%.*]] = load i64, ptr [[ULX]], align 8
59310 // SIMD-ONLY0-NEXT:    br label [[COND_END4]]
59311 // SIMD-ONLY0:       cond.end4:
59312 // SIMD-ONLY0-NEXT:    [[COND5:%.*]] = phi i64 [ [[TMP8]], [[COND_TRUE2]] ], [ [[TMP9]], [[COND_FALSE3]] ]
59313 // SIMD-ONLY0-NEXT:    store i64 [[COND5]], ptr [[ULX]], align 8
59314 // SIMD-ONLY0-NEXT:    [[TMP10:%.*]] = load i64, ptr [[ULX]], align 8
59315 // SIMD-ONLY0-NEXT:    store i64 [[TMP10]], ptr [[ULV]], align 8
59316 // SIMD-ONLY0-NEXT:    [[TMP11:%.*]] = load i64, ptr [[ULX]], align 8
59317 // SIMD-ONLY0-NEXT:    [[TMP12:%.*]] = load i64, ptr [[ULE]], align 8
59318 // SIMD-ONLY0-NEXT:    [[CMP6:%.*]] = icmp eq i64 [[TMP11]], [[TMP12]]
59319 // SIMD-ONLY0-NEXT:    br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
59320 // SIMD-ONLY0:       cond.true7:
59321 // SIMD-ONLY0-NEXT:    [[TMP13:%.*]] = load i64, ptr [[ULD]], align 8
59322 // SIMD-ONLY0-NEXT:    br label [[COND_END9:%.*]]
59323 // SIMD-ONLY0:       cond.false8:
59324 // SIMD-ONLY0-NEXT:    [[TMP14:%.*]] = load i64, ptr [[ULX]], align 8
59325 // SIMD-ONLY0-NEXT:    br label [[COND_END9]]
59326 // SIMD-ONLY0:       cond.end9:
59327 // SIMD-ONLY0-NEXT:    [[COND10:%.*]] = phi i64 [ [[TMP13]], [[COND_TRUE7]] ], [ [[TMP14]], [[COND_FALSE8]] ]
59328 // SIMD-ONLY0-NEXT:    store i64 [[COND10]], ptr [[ULX]], align 8
59329 // SIMD-ONLY0-NEXT:    [[TMP15:%.*]] = load i64, ptr [[ULX]], align 8
59330 // SIMD-ONLY0-NEXT:    [[TMP16:%.*]] = load i64, ptr [[ULE]], align 8
59331 // SIMD-ONLY0-NEXT:    [[CMP11:%.*]] = icmp ugt i64 [[TMP15]], [[TMP16]]
59332 // SIMD-ONLY0-NEXT:    br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
59333 // SIMD-ONLY0:       cond.true12:
59334 // SIMD-ONLY0-NEXT:    [[TMP17:%.*]] = load i64, ptr [[ULE]], align 8
59335 // SIMD-ONLY0-NEXT:    br label [[COND_END14:%.*]]
59336 // SIMD-ONLY0:       cond.false13:
59337 // SIMD-ONLY0-NEXT:    [[TMP18:%.*]] = load i64, ptr [[ULX]], align 8
59338 // SIMD-ONLY0-NEXT:    br label [[COND_END14]]
59339 // SIMD-ONLY0:       cond.end14:
59340 // SIMD-ONLY0-NEXT:    [[COND15:%.*]] = phi i64 [ [[TMP17]], [[COND_TRUE12]] ], [ [[TMP18]], [[COND_FALSE13]] ]
59341 // SIMD-ONLY0-NEXT:    store i64 [[COND15]], ptr [[ULX]], align 8
59342 // SIMD-ONLY0-NEXT:    [[TMP19:%.*]] = load i64, ptr [[ULX]], align 8
59343 // SIMD-ONLY0-NEXT:    store i64 [[TMP19]], ptr [[ULV]], align 8
59344 // SIMD-ONLY0-NEXT:    [[TMP20:%.*]] = load i64, ptr [[ULX]], align 8
59345 // SIMD-ONLY0-NEXT:    [[TMP21:%.*]] = load i64, ptr [[ULE]], align 8
59346 // SIMD-ONLY0-NEXT:    [[CMP16:%.*]] = icmp ult i64 [[TMP20]], [[TMP21]]
59347 // SIMD-ONLY0-NEXT:    br i1 [[CMP16]], label [[COND_TRUE17:%.*]], label [[COND_FALSE18:%.*]]
59348 // SIMD-ONLY0:       cond.true17:
59349 // SIMD-ONLY0-NEXT:    [[TMP22:%.*]] = load i64, ptr [[ULE]], align 8
59350 // SIMD-ONLY0-NEXT:    br label [[COND_END19:%.*]]
59351 // SIMD-ONLY0:       cond.false18:
59352 // SIMD-ONLY0-NEXT:    [[TMP23:%.*]] = load i64, ptr [[ULX]], align 8
59353 // SIMD-ONLY0-NEXT:    br label [[COND_END19]]
59354 // SIMD-ONLY0:       cond.end19:
59355 // SIMD-ONLY0-NEXT:    [[COND20:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE17]] ], [ [[TMP23]], [[COND_FALSE18]] ]
59356 // SIMD-ONLY0-NEXT:    store i64 [[COND20]], ptr [[ULX]], align 8
59357 // SIMD-ONLY0-NEXT:    [[TMP24:%.*]] = load i64, ptr [[ULX]], align 8
59358 // SIMD-ONLY0-NEXT:    store i64 [[TMP24]], ptr [[ULV]], align 8
59359 // SIMD-ONLY0-NEXT:    [[TMP25:%.*]] = load i64, ptr [[ULX]], align 8
59360 // SIMD-ONLY0-NEXT:    [[TMP26:%.*]] = load i64, ptr [[ULE]], align 8
59361 // SIMD-ONLY0-NEXT:    [[CMP21:%.*]] = icmp eq i64 [[TMP25]], [[TMP26]]
59362 // SIMD-ONLY0-NEXT:    br i1 [[CMP21]], label [[COND_TRUE22:%.*]], label [[COND_FALSE23:%.*]]
59363 // SIMD-ONLY0:       cond.true22:
59364 // SIMD-ONLY0-NEXT:    [[TMP27:%.*]] = load i64, ptr [[ULD]], align 8
59365 // SIMD-ONLY0-NEXT:    br label [[COND_END24:%.*]]
59366 // SIMD-ONLY0:       cond.false23:
59367 // SIMD-ONLY0-NEXT:    [[TMP28:%.*]] = load i64, ptr [[ULX]], align 8
59368 // SIMD-ONLY0-NEXT:    br label [[COND_END24]]
59369 // SIMD-ONLY0:       cond.end24:
59370 // SIMD-ONLY0-NEXT:    [[COND25:%.*]] = phi i64 [ [[TMP27]], [[COND_TRUE22]] ], [ [[TMP28]], [[COND_FALSE23]] ]
59371 // SIMD-ONLY0-NEXT:    store i64 [[COND25]], ptr [[ULX]], align 8
59372 // SIMD-ONLY0-NEXT:    [[TMP29:%.*]] = load i64, ptr [[ULX]], align 8
59373 // SIMD-ONLY0-NEXT:    store i64 [[TMP29]], ptr [[ULV]], align 8
59374 // SIMD-ONLY0-NEXT:    [[TMP30:%.*]] = load i64, ptr [[ULX]], align 8
59375 // SIMD-ONLY0-NEXT:    store i64 [[TMP30]], ptr [[ULV]], align 8
59376 // SIMD-ONLY0-NEXT:    [[TMP31:%.*]] = load i64, ptr [[ULX]], align 8
59377 // SIMD-ONLY0-NEXT:    [[TMP32:%.*]] = load i64, ptr [[ULE]], align 8
59378 // SIMD-ONLY0-NEXT:    [[CMP26:%.*]] = icmp ugt i64 [[TMP31]], [[TMP32]]
59379 // SIMD-ONLY0-NEXT:    br i1 [[CMP26]], label [[COND_TRUE27:%.*]], label [[COND_FALSE28:%.*]]
59380 // SIMD-ONLY0:       cond.true27:
59381 // SIMD-ONLY0-NEXT:    [[TMP33:%.*]] = load i64, ptr [[ULE]], align 8
59382 // SIMD-ONLY0-NEXT:    br label [[COND_END29:%.*]]
59383 // SIMD-ONLY0:       cond.false28:
59384 // SIMD-ONLY0-NEXT:    [[TMP34:%.*]] = load i64, ptr [[ULX]], align 8
59385 // SIMD-ONLY0-NEXT:    br label [[COND_END29]]
59386 // SIMD-ONLY0:       cond.end29:
59387 // SIMD-ONLY0-NEXT:    [[COND30:%.*]] = phi i64 [ [[TMP33]], [[COND_TRUE27]] ], [ [[TMP34]], [[COND_FALSE28]] ]
59388 // SIMD-ONLY0-NEXT:    store i64 [[COND30]], ptr [[ULX]], align 8
59389 // SIMD-ONLY0-NEXT:    [[TMP35:%.*]] = load i64, ptr [[ULX]], align 8
59390 // SIMD-ONLY0-NEXT:    store i64 [[TMP35]], ptr [[ULV]], align 8
59391 // SIMD-ONLY0-NEXT:    [[TMP36:%.*]] = load i64, ptr [[ULX]], align 8
59392 // SIMD-ONLY0-NEXT:    [[TMP37:%.*]] = load i64, ptr [[ULE]], align 8
59393 // SIMD-ONLY0-NEXT:    [[CMP31:%.*]] = icmp ult i64 [[TMP36]], [[TMP37]]
59394 // SIMD-ONLY0-NEXT:    br i1 [[CMP31]], label [[COND_TRUE32:%.*]], label [[COND_FALSE33:%.*]]
59395 // SIMD-ONLY0:       cond.true32:
59396 // SIMD-ONLY0-NEXT:    [[TMP38:%.*]] = load i64, ptr [[ULE]], align 8
59397 // SIMD-ONLY0-NEXT:    br label [[COND_END34:%.*]]
59398 // SIMD-ONLY0:       cond.false33:
59399 // SIMD-ONLY0-NEXT:    [[TMP39:%.*]] = load i64, ptr [[ULX]], align 8
59400 // SIMD-ONLY0-NEXT:    br label [[COND_END34]]
59401 // SIMD-ONLY0:       cond.end34:
59402 // SIMD-ONLY0-NEXT:    [[COND35:%.*]] = phi i64 [ [[TMP38]], [[COND_TRUE32]] ], [ [[TMP39]], [[COND_FALSE33]] ]
59403 // SIMD-ONLY0-NEXT:    store i64 [[COND35]], ptr [[ULX]], align 8
59404 // SIMD-ONLY0-NEXT:    [[TMP40:%.*]] = load i64, ptr [[ULX]], align 8
59405 // SIMD-ONLY0-NEXT:    store i64 [[TMP40]], ptr [[ULV]], align 8
59406 // SIMD-ONLY0-NEXT:    [[TMP41:%.*]] = load i64, ptr [[ULX]], align 8
59407 // SIMD-ONLY0-NEXT:    [[TMP42:%.*]] = load i64, ptr [[ULE]], align 8
59408 // SIMD-ONLY0-NEXT:    [[CMP36:%.*]] = icmp eq i64 [[TMP41]], [[TMP42]]
59409 // SIMD-ONLY0-NEXT:    br i1 [[CMP36]], label [[COND_TRUE37:%.*]], label [[COND_FALSE38:%.*]]
59410 // SIMD-ONLY0:       cond.true37:
59411 // SIMD-ONLY0-NEXT:    [[TMP43:%.*]] = load i64, ptr [[ULD]], align 8
59412 // SIMD-ONLY0-NEXT:    br label [[COND_END39:%.*]]
59413 // SIMD-ONLY0:       cond.false38:
59414 // SIMD-ONLY0-NEXT:    [[TMP44:%.*]] = load i64, ptr [[ULX]], align 8
59415 // SIMD-ONLY0-NEXT:    br label [[COND_END39]]
59416 // SIMD-ONLY0:       cond.end39:
59417 // SIMD-ONLY0-NEXT:    [[COND40:%.*]] = phi i64 [ [[TMP43]], [[COND_TRUE37]] ], [ [[TMP44]], [[COND_FALSE38]] ]
59418 // SIMD-ONLY0-NEXT:    store i64 [[COND40]], ptr [[ULX]], align 8
59419 // SIMD-ONLY0-NEXT:    [[TMP45:%.*]] = load i64, ptr [[ULX]], align 8
59420 // SIMD-ONLY0-NEXT:    [[TMP46:%.*]] = load i64, ptr [[ULE]], align 8
59421 // SIMD-ONLY0-NEXT:    [[CMP41:%.*]] = icmp ugt i64 [[TMP45]], [[TMP46]]
59422 // SIMD-ONLY0-NEXT:    br i1 [[CMP41]], label [[COND_TRUE42:%.*]], label [[COND_FALSE43:%.*]]
59423 // SIMD-ONLY0:       cond.true42:
59424 // SIMD-ONLY0-NEXT:    [[TMP47:%.*]] = load i64, ptr [[ULE]], align 8
59425 // SIMD-ONLY0-NEXT:    br label [[COND_END44:%.*]]
59426 // SIMD-ONLY0:       cond.false43:
59427 // SIMD-ONLY0-NEXT:    [[TMP48:%.*]] = load i64, ptr [[ULX]], align 8
59428 // SIMD-ONLY0-NEXT:    br label [[COND_END44]]
59429 // SIMD-ONLY0:       cond.end44:
59430 // SIMD-ONLY0-NEXT:    [[COND45:%.*]] = phi i64 [ [[TMP47]], [[COND_TRUE42]] ], [ [[TMP48]], [[COND_FALSE43]] ]
59431 // SIMD-ONLY0-NEXT:    store i64 [[COND45]], ptr [[ULX]], align 8
59432 // SIMD-ONLY0-NEXT:    [[TMP49:%.*]] = load i64, ptr [[ULX]], align 8
59433 // SIMD-ONLY0-NEXT:    store i64 [[TMP49]], ptr [[ULV]], align 8
59434 // SIMD-ONLY0-NEXT:    [[TMP50:%.*]] = load i64, ptr [[ULX]], align 8
59435 // SIMD-ONLY0-NEXT:    [[TMP51:%.*]] = load i64, ptr [[ULE]], align 8
59436 // SIMD-ONLY0-NEXT:    [[CMP46:%.*]] = icmp ult i64 [[TMP50]], [[TMP51]]
59437 // SIMD-ONLY0-NEXT:    br i1 [[CMP46]], label [[COND_TRUE47:%.*]], label [[COND_FALSE48:%.*]]
59438 // SIMD-ONLY0:       cond.true47:
59439 // SIMD-ONLY0-NEXT:    [[TMP52:%.*]] = load i64, ptr [[ULE]], align 8
59440 // SIMD-ONLY0-NEXT:    br label [[COND_END49:%.*]]
59441 // SIMD-ONLY0:       cond.false48:
59442 // SIMD-ONLY0-NEXT:    [[TMP53:%.*]] = load i64, ptr [[ULX]], align 8
59443 // SIMD-ONLY0-NEXT:    br label [[COND_END49]]
59444 // SIMD-ONLY0:       cond.end49:
59445 // SIMD-ONLY0-NEXT:    [[COND50:%.*]] = phi i64 [ [[TMP52]], [[COND_TRUE47]] ], [ [[TMP53]], [[COND_FALSE48]] ]
59446 // SIMD-ONLY0-NEXT:    store i64 [[COND50]], ptr [[ULX]], align 8
59447 // SIMD-ONLY0-NEXT:    [[TMP54:%.*]] = load i64, ptr [[ULX]], align 8
59448 // SIMD-ONLY0-NEXT:    store i64 [[TMP54]], ptr [[ULV]], align 8
59449 // SIMD-ONLY0-NEXT:    [[TMP55:%.*]] = load i64, ptr [[ULX]], align 8
59450 // SIMD-ONLY0-NEXT:    [[TMP56:%.*]] = load i64, ptr [[ULE]], align 8
59451 // SIMD-ONLY0-NEXT:    [[CMP51:%.*]] = icmp eq i64 [[TMP55]], [[TMP56]]
59452 // SIMD-ONLY0-NEXT:    br i1 [[CMP51]], label [[COND_TRUE52:%.*]], label [[COND_FALSE53:%.*]]
59453 // SIMD-ONLY0:       cond.true52:
59454 // SIMD-ONLY0-NEXT:    [[TMP57:%.*]] = load i64, ptr [[ULD]], align 8
59455 // SIMD-ONLY0-NEXT:    br label [[COND_END54:%.*]]
59456 // SIMD-ONLY0:       cond.false53:
59457 // SIMD-ONLY0-NEXT:    [[TMP58:%.*]] = load i64, ptr [[ULX]], align 8
59458 // SIMD-ONLY0-NEXT:    br label [[COND_END54]]
59459 // SIMD-ONLY0:       cond.end54:
59460 // SIMD-ONLY0-NEXT:    [[COND55:%.*]] = phi i64 [ [[TMP57]], [[COND_TRUE52]] ], [ [[TMP58]], [[COND_FALSE53]] ]
59461 // SIMD-ONLY0-NEXT:    store i64 [[COND55]], ptr [[ULX]], align 8
59462 // SIMD-ONLY0-NEXT:    [[TMP59:%.*]] = load i64, ptr [[ULX]], align 8
59463 // SIMD-ONLY0-NEXT:    store i64 [[TMP59]], ptr [[ULV]], align 8
59464 // SIMD-ONLY0-NEXT:    [[TMP60:%.*]] = load i64, ptr [[ULX]], align 8
59465 // SIMD-ONLY0-NEXT:    store i64 [[TMP60]], ptr [[ULV]], align 8
59466 // SIMD-ONLY0-NEXT:    [[TMP61:%.*]] = load i64, ptr [[ULX]], align 8
59467 // SIMD-ONLY0-NEXT:    [[TMP62:%.*]] = load i64, ptr [[ULE]], align 8
59468 // SIMD-ONLY0-NEXT:    [[CMP56:%.*]] = icmp ugt i64 [[TMP61]], [[TMP62]]
59469 // SIMD-ONLY0-NEXT:    br i1 [[CMP56]], label [[COND_TRUE57:%.*]], label [[COND_FALSE58:%.*]]
59470 // SIMD-ONLY0:       cond.true57:
59471 // SIMD-ONLY0-NEXT:    [[TMP63:%.*]] = load i64, ptr [[ULE]], align 8
59472 // SIMD-ONLY0-NEXT:    br label [[COND_END59:%.*]]
59473 // SIMD-ONLY0:       cond.false58:
59474 // SIMD-ONLY0-NEXT:    [[TMP64:%.*]] = load i64, ptr [[ULX]], align 8
59475 // SIMD-ONLY0-NEXT:    br label [[COND_END59]]
59476 // SIMD-ONLY0:       cond.end59:
59477 // SIMD-ONLY0-NEXT:    [[COND60:%.*]] = phi i64 [ [[TMP63]], [[COND_TRUE57]] ], [ [[TMP64]], [[COND_FALSE58]] ]
59478 // SIMD-ONLY0-NEXT:    store i64 [[COND60]], ptr [[ULX]], align 8
59479 // SIMD-ONLY0-NEXT:    [[TMP65:%.*]] = load i64, ptr [[ULX]], align 8
59480 // SIMD-ONLY0-NEXT:    store i64 [[TMP65]], ptr [[ULV]], align 8
59481 // SIMD-ONLY0-NEXT:    [[TMP66:%.*]] = load i64, ptr [[ULX]], align 8
59482 // SIMD-ONLY0-NEXT:    [[TMP67:%.*]] = load i64, ptr [[ULE]], align 8
59483 // SIMD-ONLY0-NEXT:    [[CMP61:%.*]] = icmp ult i64 [[TMP66]], [[TMP67]]
59484 // SIMD-ONLY0-NEXT:    br i1 [[CMP61]], label [[COND_TRUE62:%.*]], label [[COND_FALSE63:%.*]]
59485 // SIMD-ONLY0:       cond.true62:
59486 // SIMD-ONLY0-NEXT:    [[TMP68:%.*]] = load i64, ptr [[ULE]], align 8
59487 // SIMD-ONLY0-NEXT:    br label [[COND_END64:%.*]]
59488 // SIMD-ONLY0:       cond.false63:
59489 // SIMD-ONLY0-NEXT:    [[TMP69:%.*]] = load i64, ptr [[ULX]], align 8
59490 // SIMD-ONLY0-NEXT:    br label [[COND_END64]]
59491 // SIMD-ONLY0:       cond.end64:
59492 // SIMD-ONLY0-NEXT:    [[COND65:%.*]] = phi i64 [ [[TMP68]], [[COND_TRUE62]] ], [ [[TMP69]], [[COND_FALSE63]] ]
59493 // SIMD-ONLY0-NEXT:    store i64 [[COND65]], ptr [[ULX]], align 8
59494 // SIMD-ONLY0-NEXT:    [[TMP70:%.*]] = load i64, ptr [[ULX]], align 8
59495 // SIMD-ONLY0-NEXT:    store i64 [[TMP70]], ptr [[ULV]], align 8
59496 // SIMD-ONLY0-NEXT:    [[TMP71:%.*]] = load i64, ptr [[ULX]], align 8
59497 // SIMD-ONLY0-NEXT:    [[TMP72:%.*]] = load i64, ptr [[ULE]], align 8
59498 // SIMD-ONLY0-NEXT:    [[CMP66:%.*]] = icmp eq i64 [[TMP71]], [[TMP72]]
59499 // SIMD-ONLY0-NEXT:    br i1 [[CMP66]], label [[COND_TRUE67:%.*]], label [[COND_FALSE68:%.*]]
59500 // SIMD-ONLY0:       cond.true67:
59501 // SIMD-ONLY0-NEXT:    [[TMP73:%.*]] = load i64, ptr [[ULD]], align 8
59502 // SIMD-ONLY0-NEXT:    br label [[COND_END69:%.*]]
59503 // SIMD-ONLY0:       cond.false68:
59504 // SIMD-ONLY0-NEXT:    [[TMP74:%.*]] = load i64, ptr [[ULX]], align 8
59505 // SIMD-ONLY0-NEXT:    br label [[COND_END69]]
59506 // SIMD-ONLY0:       cond.end69:
59507 // SIMD-ONLY0-NEXT:    [[COND70:%.*]] = phi i64 [ [[TMP73]], [[COND_TRUE67]] ], [ [[TMP74]], [[COND_FALSE68]] ]
59508 // SIMD-ONLY0-NEXT:    store i64 [[COND70]], ptr [[ULX]], align 8
59509 // SIMD-ONLY0-NEXT:    [[TMP75:%.*]] = load i64, ptr [[ULX]], align 8
59510 // SIMD-ONLY0-NEXT:    [[TMP76:%.*]] = load i64, ptr [[ULE]], align 8
59511 // SIMD-ONLY0-NEXT:    [[CMP71:%.*]] = icmp ugt i64 [[TMP75]], [[TMP76]]
59512 // SIMD-ONLY0-NEXT:    br i1 [[CMP71]], label [[COND_TRUE72:%.*]], label [[COND_FALSE73:%.*]]
59513 // SIMD-ONLY0:       cond.true72:
59514 // SIMD-ONLY0-NEXT:    [[TMP77:%.*]] = load i64, ptr [[ULE]], align 8
59515 // SIMD-ONLY0-NEXT:    br label [[COND_END74:%.*]]
59516 // SIMD-ONLY0:       cond.false73:
59517 // SIMD-ONLY0-NEXT:    [[TMP78:%.*]] = load i64, ptr [[ULX]], align 8
59518 // SIMD-ONLY0-NEXT:    br label [[COND_END74]]
59519 // SIMD-ONLY0:       cond.end74:
59520 // SIMD-ONLY0-NEXT:    [[COND75:%.*]] = phi i64 [ [[TMP77]], [[COND_TRUE72]] ], [ [[TMP78]], [[COND_FALSE73]] ]
59521 // SIMD-ONLY0-NEXT:    store i64 [[COND75]], ptr [[ULX]], align 8
59522 // SIMD-ONLY0-NEXT:    [[TMP79:%.*]] = load i64, ptr [[ULX]], align 8
59523 // SIMD-ONLY0-NEXT:    store i64 [[TMP79]], ptr [[ULV]], align 8
59524 // SIMD-ONLY0-NEXT:    [[TMP80:%.*]] = load i64, ptr [[ULX]], align 8
59525 // SIMD-ONLY0-NEXT:    [[TMP81:%.*]] = load i64, ptr [[ULE]], align 8
59526 // SIMD-ONLY0-NEXT:    [[CMP76:%.*]] = icmp ult i64 [[TMP80]], [[TMP81]]
59527 // SIMD-ONLY0-NEXT:    br i1 [[CMP76]], label [[COND_TRUE77:%.*]], label [[COND_FALSE78:%.*]]
59528 // SIMD-ONLY0:       cond.true77:
59529 // SIMD-ONLY0-NEXT:    [[TMP82:%.*]] = load i64, ptr [[ULE]], align 8
59530 // SIMD-ONLY0-NEXT:    br label [[COND_END79:%.*]]
59531 // SIMD-ONLY0:       cond.false78:
59532 // SIMD-ONLY0-NEXT:    [[TMP83:%.*]] = load i64, ptr [[ULX]], align 8
59533 // SIMD-ONLY0-NEXT:    br label [[COND_END79]]
59534 // SIMD-ONLY0:       cond.end79:
59535 // SIMD-ONLY0-NEXT:    [[COND80:%.*]] = phi i64 [ [[TMP82]], [[COND_TRUE77]] ], [ [[TMP83]], [[COND_FALSE78]] ]
59536 // SIMD-ONLY0-NEXT:    store i64 [[COND80]], ptr [[ULX]], align 8
59537 // SIMD-ONLY0-NEXT:    [[TMP84:%.*]] = load i64, ptr [[ULX]], align 8
59538 // SIMD-ONLY0-NEXT:    store i64 [[TMP84]], ptr [[ULV]], align 8
59539 // SIMD-ONLY0-NEXT:    [[TMP85:%.*]] = load i64, ptr [[ULX]], align 8
59540 // SIMD-ONLY0-NEXT:    [[TMP86:%.*]] = load i64, ptr [[ULE]], align 8
59541 // SIMD-ONLY0-NEXT:    [[CMP81:%.*]] = icmp eq i64 [[TMP85]], [[TMP86]]
59542 // SIMD-ONLY0-NEXT:    br i1 [[CMP81]], label [[COND_TRUE82:%.*]], label [[COND_FALSE83:%.*]]
59543 // SIMD-ONLY0:       cond.true82:
59544 // SIMD-ONLY0-NEXT:    [[TMP87:%.*]] = load i64, ptr [[ULD]], align 8
59545 // SIMD-ONLY0-NEXT:    br label [[COND_END84:%.*]]
59546 // SIMD-ONLY0:       cond.false83:
59547 // SIMD-ONLY0-NEXT:    [[TMP88:%.*]] = load i64, ptr [[ULX]], align 8
59548 // SIMD-ONLY0-NEXT:    br label [[COND_END84]]
59549 // SIMD-ONLY0:       cond.end84:
59550 // SIMD-ONLY0-NEXT:    [[COND85:%.*]] = phi i64 [ [[TMP87]], [[COND_TRUE82]] ], [ [[TMP88]], [[COND_FALSE83]] ]
59551 // SIMD-ONLY0-NEXT:    store i64 [[COND85]], ptr [[ULX]], align 8
59552 // SIMD-ONLY0-NEXT:    [[TMP89:%.*]] = load i64, ptr [[ULX]], align 8
59553 // SIMD-ONLY0-NEXT:    store i64 [[TMP89]], ptr [[ULV]], align 8
59554 // SIMD-ONLY0-NEXT:    [[TMP90:%.*]] = load i64, ptr [[ULX]], align 8
59555 // SIMD-ONLY0-NEXT:    store i64 [[TMP90]], ptr [[ULV]], align 8
59556 // SIMD-ONLY0-NEXT:    [[TMP91:%.*]] = load i64, ptr [[ULX]], align 8
59557 // SIMD-ONLY0-NEXT:    [[TMP92:%.*]] = load i64, ptr [[ULE]], align 8
59558 // SIMD-ONLY0-NEXT:    [[CMP86:%.*]] = icmp ugt i64 [[TMP91]], [[TMP92]]
59559 // SIMD-ONLY0-NEXT:    br i1 [[CMP86]], label [[COND_TRUE87:%.*]], label [[COND_FALSE88:%.*]]
59560 // SIMD-ONLY0:       cond.true87:
59561 // SIMD-ONLY0-NEXT:    [[TMP93:%.*]] = load i64, ptr [[ULE]], align 8
59562 // SIMD-ONLY0-NEXT:    br label [[COND_END89:%.*]]
59563 // SIMD-ONLY0:       cond.false88:
59564 // SIMD-ONLY0-NEXT:    [[TMP94:%.*]] = load i64, ptr [[ULX]], align 8
59565 // SIMD-ONLY0-NEXT:    br label [[COND_END89]]
59566 // SIMD-ONLY0:       cond.end89:
59567 // SIMD-ONLY0-NEXT:    [[COND90:%.*]] = phi i64 [ [[TMP93]], [[COND_TRUE87]] ], [ [[TMP94]], [[COND_FALSE88]] ]
59568 // SIMD-ONLY0-NEXT:    store i64 [[COND90]], ptr [[ULX]], align 8
59569 // SIMD-ONLY0-NEXT:    [[TMP95:%.*]] = load i64, ptr [[ULX]], align 8
59570 // SIMD-ONLY0-NEXT:    store i64 [[TMP95]], ptr [[ULV]], align 8
59571 // SIMD-ONLY0-NEXT:    [[TMP96:%.*]] = load i64, ptr [[ULX]], align 8
59572 // SIMD-ONLY0-NEXT:    [[TMP97:%.*]] = load i64, ptr [[ULE]], align 8
59573 // SIMD-ONLY0-NEXT:    [[CMP91:%.*]] = icmp ult i64 [[TMP96]], [[TMP97]]
59574 // SIMD-ONLY0-NEXT:    br i1 [[CMP91]], label [[COND_TRUE92:%.*]], label [[COND_FALSE93:%.*]]
59575 // SIMD-ONLY0:       cond.true92:
59576 // SIMD-ONLY0-NEXT:    [[TMP98:%.*]] = load i64, ptr [[ULE]], align 8
59577 // SIMD-ONLY0-NEXT:    br label [[COND_END94:%.*]]
59578 // SIMD-ONLY0:       cond.false93:
59579 // SIMD-ONLY0-NEXT:    [[TMP99:%.*]] = load i64, ptr [[ULX]], align 8
59580 // SIMD-ONLY0-NEXT:    br label [[COND_END94]]
59581 // SIMD-ONLY0:       cond.end94:
59582 // SIMD-ONLY0-NEXT:    [[COND95:%.*]] = phi i64 [ [[TMP98]], [[COND_TRUE92]] ], [ [[TMP99]], [[COND_FALSE93]] ]
59583 // SIMD-ONLY0-NEXT:    store i64 [[COND95]], ptr [[ULX]], align 8
59584 // SIMD-ONLY0-NEXT:    [[TMP100:%.*]] = load i64, ptr [[ULX]], align 8
59585 // SIMD-ONLY0-NEXT:    store i64 [[TMP100]], ptr [[ULV]], align 8
59586 // SIMD-ONLY0-NEXT:    [[TMP101:%.*]] = load i64, ptr [[ULX]], align 8
59587 // SIMD-ONLY0-NEXT:    [[TMP102:%.*]] = load i64, ptr [[ULE]], align 8
59588 // SIMD-ONLY0-NEXT:    [[CMP96:%.*]] = icmp eq i64 [[TMP101]], [[TMP102]]
59589 // SIMD-ONLY0-NEXT:    br i1 [[CMP96]], label [[COND_TRUE97:%.*]], label [[COND_FALSE98:%.*]]
59590 // SIMD-ONLY0:       cond.true97:
59591 // SIMD-ONLY0-NEXT:    [[TMP103:%.*]] = load i64, ptr [[ULD]], align 8
59592 // SIMD-ONLY0-NEXT:    br label [[COND_END99:%.*]]
59593 // SIMD-ONLY0:       cond.false98:
59594 // SIMD-ONLY0-NEXT:    [[TMP104:%.*]] = load i64, ptr [[ULX]], align 8
59595 // SIMD-ONLY0-NEXT:    br label [[COND_END99]]
59596 // SIMD-ONLY0:       cond.end99:
59597 // SIMD-ONLY0-NEXT:    [[COND100:%.*]] = phi i64 [ [[TMP103]], [[COND_TRUE97]] ], [ [[TMP104]], [[COND_FALSE98]] ]
59598 // SIMD-ONLY0-NEXT:    store i64 [[COND100]], ptr [[ULX]], align 8
59599 // SIMD-ONLY0-NEXT:    [[TMP105:%.*]] = load i64, ptr [[ULX]], align 8
59600 // SIMD-ONLY0-NEXT:    [[TMP106:%.*]] = load i64, ptr [[ULE]], align 8
59601 // SIMD-ONLY0-NEXT:    [[CMP101:%.*]] = icmp ugt i64 [[TMP105]], [[TMP106]]
59602 // SIMD-ONLY0-NEXT:    br i1 [[CMP101]], label [[COND_TRUE102:%.*]], label [[COND_FALSE103:%.*]]
59603 // SIMD-ONLY0:       cond.true102:
59604 // SIMD-ONLY0-NEXT:    [[TMP107:%.*]] = load i64, ptr [[ULE]], align 8
59605 // SIMD-ONLY0-NEXT:    br label [[COND_END104:%.*]]
59606 // SIMD-ONLY0:       cond.false103:
59607 // SIMD-ONLY0-NEXT:    [[TMP108:%.*]] = load i64, ptr [[ULX]], align 8
59608 // SIMD-ONLY0-NEXT:    br label [[COND_END104]]
59609 // SIMD-ONLY0:       cond.end104:
59610 // SIMD-ONLY0-NEXT:    [[COND105:%.*]] = phi i64 [ [[TMP107]], [[COND_TRUE102]] ], [ [[TMP108]], [[COND_FALSE103]] ]
59611 // SIMD-ONLY0-NEXT:    store i64 [[COND105]], ptr [[ULX]], align 8
59612 // SIMD-ONLY0-NEXT:    [[TMP109:%.*]] = load i64, ptr [[ULX]], align 8
59613 // SIMD-ONLY0-NEXT:    store i64 [[TMP109]], ptr [[ULV]], align 8
59614 // SIMD-ONLY0-NEXT:    [[TMP110:%.*]] = load i64, ptr [[ULX]], align 8
59615 // SIMD-ONLY0-NEXT:    [[TMP111:%.*]] = load i64, ptr [[ULE]], align 8
59616 // SIMD-ONLY0-NEXT:    [[CMP106:%.*]] = icmp ult i64 [[TMP110]], [[TMP111]]
59617 // SIMD-ONLY0-NEXT:    br i1 [[CMP106]], label [[COND_TRUE107:%.*]], label [[COND_FALSE108:%.*]]
59618 // SIMD-ONLY0:       cond.true107:
59619 // SIMD-ONLY0-NEXT:    [[TMP112:%.*]] = load i64, ptr [[ULE]], align 8
59620 // SIMD-ONLY0-NEXT:    br label [[COND_END109:%.*]]
59621 // SIMD-ONLY0:       cond.false108:
59622 // SIMD-ONLY0-NEXT:    [[TMP113:%.*]] = load i64, ptr [[ULX]], align 8
59623 // SIMD-ONLY0-NEXT:    br label [[COND_END109]]
59624 // SIMD-ONLY0:       cond.end109:
59625 // SIMD-ONLY0-NEXT:    [[COND110:%.*]] = phi i64 [ [[TMP112]], [[COND_TRUE107]] ], [ [[TMP113]], [[COND_FALSE108]] ]
59626 // SIMD-ONLY0-NEXT:    store i64 [[COND110]], ptr [[ULX]], align 8
59627 // SIMD-ONLY0-NEXT:    [[TMP114:%.*]] = load i64, ptr [[ULX]], align 8
59628 // SIMD-ONLY0-NEXT:    store i64 [[TMP114]], ptr [[ULV]], align 8
59629 // SIMD-ONLY0-NEXT:    [[TMP115:%.*]] = load i64, ptr [[ULX]], align 8
59630 // SIMD-ONLY0-NEXT:    [[TMP116:%.*]] = load i64, ptr [[ULE]], align 8
59631 // SIMD-ONLY0-NEXT:    [[CMP111:%.*]] = icmp eq i64 [[TMP115]], [[TMP116]]
59632 // SIMD-ONLY0-NEXT:    br i1 [[CMP111]], label [[COND_TRUE112:%.*]], label [[COND_FALSE113:%.*]]
59633 // SIMD-ONLY0:       cond.true112:
59634 // SIMD-ONLY0-NEXT:    [[TMP117:%.*]] = load i64, ptr [[ULD]], align 8
59635 // SIMD-ONLY0-NEXT:    br label [[COND_END114:%.*]]
59636 // SIMD-ONLY0:       cond.false113:
59637 // SIMD-ONLY0-NEXT:    [[TMP118:%.*]] = load i64, ptr [[ULX]], align 8
59638 // SIMD-ONLY0-NEXT:    br label [[COND_END114]]
59639 // SIMD-ONLY0:       cond.end114:
59640 // SIMD-ONLY0-NEXT:    [[COND115:%.*]] = phi i64 [ [[TMP117]], [[COND_TRUE112]] ], [ [[TMP118]], [[COND_FALSE113]] ]
59641 // SIMD-ONLY0-NEXT:    store i64 [[COND115]], ptr [[ULX]], align 8
59642 // SIMD-ONLY0-NEXT:    [[TMP119:%.*]] = load i64, ptr [[ULX]], align 8
59643 // SIMD-ONLY0-NEXT:    store i64 [[TMP119]], ptr [[ULV]], align 8
59644 // SIMD-ONLY0-NEXT:    [[TMP120:%.*]] = load i64, ptr [[ULX]], align 8
59645 // SIMD-ONLY0-NEXT:    store i64 [[TMP120]], ptr [[ULV]], align 8
59646 // SIMD-ONLY0-NEXT:    [[TMP121:%.*]] = load i64, ptr [[ULX]], align 8
59647 // SIMD-ONLY0-NEXT:    [[TMP122:%.*]] = load i64, ptr [[ULE]], align 8
59648 // SIMD-ONLY0-NEXT:    [[CMP116:%.*]] = icmp ugt i64 [[TMP121]], [[TMP122]]
59649 // SIMD-ONLY0-NEXT:    br i1 [[CMP116]], label [[COND_TRUE117:%.*]], label [[COND_FALSE118:%.*]]
59650 // SIMD-ONLY0:       cond.true117:
59651 // SIMD-ONLY0-NEXT:    [[TMP123:%.*]] = load i64, ptr [[ULE]], align 8
59652 // SIMD-ONLY0-NEXT:    br label [[COND_END119:%.*]]
59653 // SIMD-ONLY0:       cond.false118:
59654 // SIMD-ONLY0-NEXT:    [[TMP124:%.*]] = load i64, ptr [[ULX]], align 8
59655 // SIMD-ONLY0-NEXT:    br label [[COND_END119]]
59656 // SIMD-ONLY0:       cond.end119:
59657 // SIMD-ONLY0-NEXT:    [[COND120:%.*]] = phi i64 [ [[TMP123]], [[COND_TRUE117]] ], [ [[TMP124]], [[COND_FALSE118]] ]
59658 // SIMD-ONLY0-NEXT:    store i64 [[COND120]], ptr [[ULX]], align 8
59659 // SIMD-ONLY0-NEXT:    [[TMP125:%.*]] = load i64, ptr [[ULX]], align 8
59660 // SIMD-ONLY0-NEXT:    store i64 [[TMP125]], ptr [[ULV]], align 8
59661 // SIMD-ONLY0-NEXT:    [[TMP126:%.*]] = load i64, ptr [[ULX]], align 8
59662 // SIMD-ONLY0-NEXT:    [[TMP127:%.*]] = load i64, ptr [[ULE]], align 8
59663 // SIMD-ONLY0-NEXT:    [[CMP121:%.*]] = icmp ult i64 [[TMP126]], [[TMP127]]
59664 // SIMD-ONLY0-NEXT:    br i1 [[CMP121]], label [[COND_TRUE122:%.*]], label [[COND_FALSE123:%.*]]
59665 // SIMD-ONLY0:       cond.true122:
59666 // SIMD-ONLY0-NEXT:    [[TMP128:%.*]] = load i64, ptr [[ULE]], align 8
59667 // SIMD-ONLY0-NEXT:    br label [[COND_END124:%.*]]
59668 // SIMD-ONLY0:       cond.false123:
59669 // SIMD-ONLY0-NEXT:    [[TMP129:%.*]] = load i64, ptr [[ULX]], align 8
59670 // SIMD-ONLY0-NEXT:    br label [[COND_END124]]
59671 // SIMD-ONLY0:       cond.end124:
59672 // SIMD-ONLY0-NEXT:    [[COND125:%.*]] = phi i64 [ [[TMP128]], [[COND_TRUE122]] ], [ [[TMP129]], [[COND_FALSE123]] ]
59673 // SIMD-ONLY0-NEXT:    store i64 [[COND125]], ptr [[ULX]], align 8
59674 // SIMD-ONLY0-NEXT:    [[TMP130:%.*]] = load i64, ptr [[ULX]], align 8
59675 // SIMD-ONLY0-NEXT:    store i64 [[TMP130]], ptr [[ULV]], align 8
59676 // SIMD-ONLY0-NEXT:    [[TMP131:%.*]] = load i64, ptr [[ULX]], align 8
59677 // SIMD-ONLY0-NEXT:    [[TMP132:%.*]] = load i64, ptr [[ULE]], align 8
59678 // SIMD-ONLY0-NEXT:    [[CMP126:%.*]] = icmp eq i64 [[TMP131]], [[TMP132]]
59679 // SIMD-ONLY0-NEXT:    br i1 [[CMP126]], label [[COND_TRUE127:%.*]], label [[COND_FALSE128:%.*]]
59680 // SIMD-ONLY0:       cond.true127:
59681 // SIMD-ONLY0-NEXT:    [[TMP133:%.*]] = load i64, ptr [[ULD]], align 8
59682 // SIMD-ONLY0-NEXT:    br label [[COND_END129:%.*]]
59683 // SIMD-ONLY0:       cond.false128:
59684 // SIMD-ONLY0-NEXT:    [[TMP134:%.*]] = load i64, ptr [[ULX]], align 8
59685 // SIMD-ONLY0-NEXT:    br label [[COND_END129]]
59686 // SIMD-ONLY0:       cond.end129:
59687 // SIMD-ONLY0-NEXT:    [[COND130:%.*]] = phi i64 [ [[TMP133]], [[COND_TRUE127]] ], [ [[TMP134]], [[COND_FALSE128]] ]
59688 // SIMD-ONLY0-NEXT:    store i64 [[COND130]], ptr [[ULX]], align 8
59689 // SIMD-ONLY0-NEXT:    [[TMP135:%.*]] = load i64, ptr [[ULX]], align 8
59690 // SIMD-ONLY0-NEXT:    [[TMP136:%.*]] = load i64, ptr [[ULE]], align 8
59691 // SIMD-ONLY0-NEXT:    [[CMP131:%.*]] = icmp ugt i64 [[TMP135]], [[TMP136]]
59692 // SIMD-ONLY0-NEXT:    br i1 [[CMP131]], label [[COND_TRUE132:%.*]], label [[COND_FALSE133:%.*]]
59693 // SIMD-ONLY0:       cond.true132:
59694 // SIMD-ONLY0-NEXT:    [[TMP137:%.*]] = load i64, ptr [[ULE]], align 8
59695 // SIMD-ONLY0-NEXT:    br label [[COND_END134:%.*]]
59696 // SIMD-ONLY0:       cond.false133:
59697 // SIMD-ONLY0-NEXT:    [[TMP138:%.*]] = load i64, ptr [[ULX]], align 8
59698 // SIMD-ONLY0-NEXT:    br label [[COND_END134]]
59699 // SIMD-ONLY0:       cond.end134:
59700 // SIMD-ONLY0-NEXT:    [[COND135:%.*]] = phi i64 [ [[TMP137]], [[COND_TRUE132]] ], [ [[TMP138]], [[COND_FALSE133]] ]
59701 // SIMD-ONLY0-NEXT:    store i64 [[COND135]], ptr [[ULX]], align 8
59702 // SIMD-ONLY0-NEXT:    [[TMP139:%.*]] = load i64, ptr [[ULX]], align 8
59703 // SIMD-ONLY0-NEXT:    store i64 [[TMP139]], ptr [[ULV]], align 8
59704 // SIMD-ONLY0-NEXT:    [[TMP140:%.*]] = load i64, ptr [[ULX]], align 8
59705 // SIMD-ONLY0-NEXT:    [[TMP141:%.*]] = load i64, ptr [[ULE]], align 8
59706 // SIMD-ONLY0-NEXT:    [[CMP136:%.*]] = icmp ult i64 [[TMP140]], [[TMP141]]
59707 // SIMD-ONLY0-NEXT:    br i1 [[CMP136]], label [[COND_TRUE137:%.*]], label [[COND_FALSE138:%.*]]
59708 // SIMD-ONLY0:       cond.true137:
59709 // SIMD-ONLY0-NEXT:    [[TMP142:%.*]] = load i64, ptr [[ULE]], align 8
59710 // SIMD-ONLY0-NEXT:    br label [[COND_END139:%.*]]
59711 // SIMD-ONLY0:       cond.false138:
59712 // SIMD-ONLY0-NEXT:    [[TMP143:%.*]] = load i64, ptr [[ULX]], align 8
59713 // SIMD-ONLY0-NEXT:    br label [[COND_END139]]
59714 // SIMD-ONLY0:       cond.end139:
59715 // SIMD-ONLY0-NEXT:    [[COND140:%.*]] = phi i64 [ [[TMP142]], [[COND_TRUE137]] ], [ [[TMP143]], [[COND_FALSE138]] ]
59716 // SIMD-ONLY0-NEXT:    store i64 [[COND140]], ptr [[ULX]], align 8
59717 // SIMD-ONLY0-NEXT:    [[TMP144:%.*]] = load i64, ptr [[ULX]], align 8
59718 // SIMD-ONLY0-NEXT:    store i64 [[TMP144]], ptr [[ULV]], align 8
59719 // SIMD-ONLY0-NEXT:    [[TMP145:%.*]] = load i64, ptr [[ULX]], align 8
59720 // SIMD-ONLY0-NEXT:    [[TMP146:%.*]] = load i64, ptr [[ULE]], align 8
59721 // SIMD-ONLY0-NEXT:    [[CMP141:%.*]] = icmp eq i64 [[TMP145]], [[TMP146]]
59722 // SIMD-ONLY0-NEXT:    br i1 [[CMP141]], label [[COND_TRUE142:%.*]], label [[COND_FALSE143:%.*]]
59723 // SIMD-ONLY0:       cond.true142:
59724 // SIMD-ONLY0-NEXT:    [[TMP147:%.*]] = load i64, ptr [[ULD]], align 8
59725 // SIMD-ONLY0-NEXT:    br label [[COND_END144:%.*]]
59726 // SIMD-ONLY0:       cond.false143:
59727 // SIMD-ONLY0-NEXT:    [[TMP148:%.*]] = load i64, ptr [[ULX]], align 8
59728 // SIMD-ONLY0-NEXT:    br label [[COND_END144]]
59729 // SIMD-ONLY0:       cond.end144:
59730 // SIMD-ONLY0-NEXT:    [[COND145:%.*]] = phi i64 [ [[TMP147]], [[COND_TRUE142]] ], [ [[TMP148]], [[COND_FALSE143]] ]
59731 // SIMD-ONLY0-NEXT:    store i64 [[COND145]], ptr [[ULX]], align 8
59732 // SIMD-ONLY0-NEXT:    [[TMP149:%.*]] = load i64, ptr [[ULX]], align 8
59733 // SIMD-ONLY0-NEXT:    store i64 [[TMP149]], ptr [[ULV]], align 8
59734 // SIMD-ONLY0-NEXT:    [[TMP150:%.*]] = load i64, ptr [[ULX]], align 8
59735 // SIMD-ONLY0-NEXT:    store i64 [[TMP150]], ptr [[ULV]], align 8
59736 // SIMD-ONLY0-NEXT:    [[TMP151:%.*]] = load i64, ptr [[ULX]], align 8
59737 // SIMD-ONLY0-NEXT:    [[TMP152:%.*]] = load i64, ptr [[ULE]], align 8
59738 // SIMD-ONLY0-NEXT:    [[CMP146:%.*]] = icmp ugt i64 [[TMP151]], [[TMP152]]
59739 // SIMD-ONLY0-NEXT:    br i1 [[CMP146]], label [[COND_TRUE147:%.*]], label [[COND_FALSE148:%.*]]
59740 // SIMD-ONLY0:       cond.true147:
59741 // SIMD-ONLY0-NEXT:    [[TMP153:%.*]] = load i64, ptr [[ULE]], align 8
59742 // SIMD-ONLY0-NEXT:    br label [[COND_END149:%.*]]
59743 // SIMD-ONLY0:       cond.false148:
59744 // SIMD-ONLY0-NEXT:    [[TMP154:%.*]] = load i64, ptr [[ULX]], align 8
59745 // SIMD-ONLY0-NEXT:    br label [[COND_END149]]
59746 // SIMD-ONLY0:       cond.end149:
59747 // SIMD-ONLY0-NEXT:    [[COND150:%.*]] = phi i64 [ [[TMP153]], [[COND_TRUE147]] ], [ [[TMP154]], [[COND_FALSE148]] ]
59748 // SIMD-ONLY0-NEXT:    store i64 [[COND150]], ptr [[ULX]], align 8
59749 // SIMD-ONLY0-NEXT:    [[TMP155:%.*]] = load i64, ptr [[ULX]], align 8
59750 // SIMD-ONLY0-NEXT:    store i64 [[TMP155]], ptr [[ULV]], align 8
59751 // SIMD-ONLY0-NEXT:    [[TMP156:%.*]] = load i64, ptr [[ULX]], align 8
59752 // SIMD-ONLY0-NEXT:    [[TMP157:%.*]] = load i64, ptr [[ULE]], align 8
59753 // SIMD-ONLY0-NEXT:    [[CMP151:%.*]] = icmp ult i64 [[TMP156]], [[TMP157]]
59754 // SIMD-ONLY0-NEXT:    br i1 [[CMP151]], label [[COND_TRUE152:%.*]], label [[COND_FALSE153:%.*]]
59755 // SIMD-ONLY0:       cond.true152:
59756 // SIMD-ONLY0-NEXT:    [[TMP158:%.*]] = load i64, ptr [[ULE]], align 8
59757 // SIMD-ONLY0-NEXT:    br label [[COND_END154:%.*]]
59758 // SIMD-ONLY0:       cond.false153:
59759 // SIMD-ONLY0-NEXT:    [[TMP159:%.*]] = load i64, ptr [[ULX]], align 8
59760 // SIMD-ONLY0-NEXT:    br label [[COND_END154]]
59761 // SIMD-ONLY0:       cond.end154:
59762 // SIMD-ONLY0-NEXT:    [[COND155:%.*]] = phi i64 [ [[TMP158]], [[COND_TRUE152]] ], [ [[TMP159]], [[COND_FALSE153]] ]
59763 // SIMD-ONLY0-NEXT:    store i64 [[COND155]], ptr [[ULX]], align 8
59764 // SIMD-ONLY0-NEXT:    [[TMP160:%.*]] = load i64, ptr [[ULX]], align 8
59765 // SIMD-ONLY0-NEXT:    store i64 [[TMP160]], ptr [[ULV]], align 8
59766 // SIMD-ONLY0-NEXT:    [[TMP161:%.*]] = load i64, ptr [[ULX]], align 8
59767 // SIMD-ONLY0-NEXT:    [[TMP162:%.*]] = load i64, ptr [[ULE]], align 8
59768 // SIMD-ONLY0-NEXT:    [[CMP156:%.*]] = icmp eq i64 [[TMP161]], [[TMP162]]
59769 // SIMD-ONLY0-NEXT:    br i1 [[CMP156]], label [[COND_TRUE157:%.*]], label [[COND_FALSE158:%.*]]
59770 // SIMD-ONLY0:       cond.true157:
59771 // SIMD-ONLY0-NEXT:    [[TMP163:%.*]] = load i64, ptr [[ULD]], align 8
59772 // SIMD-ONLY0-NEXT:    br label [[COND_END159:%.*]]
59773 // SIMD-ONLY0:       cond.false158:
59774 // SIMD-ONLY0-NEXT:    [[TMP164:%.*]] = load i64, ptr [[ULX]], align 8
59775 // SIMD-ONLY0-NEXT:    br label [[COND_END159]]
59776 // SIMD-ONLY0:       cond.end159:
59777 // SIMD-ONLY0-NEXT:    [[COND160:%.*]] = phi i64 [ [[TMP163]], [[COND_TRUE157]] ], [ [[TMP164]], [[COND_FALSE158]] ]
59778 // SIMD-ONLY0-NEXT:    store i64 [[COND160]], ptr [[ULX]], align 8
59779 // SIMD-ONLY0-NEXT:    [[TMP165:%.*]] = load i64, ptr [[ULX]], align 8
59780 // SIMD-ONLY0-NEXT:    [[TMP166:%.*]] = load i64, ptr [[ULE]], align 8
59781 // SIMD-ONLY0-NEXT:    [[CMP161:%.*]] = icmp ugt i64 [[TMP165]], [[TMP166]]
59782 // SIMD-ONLY0-NEXT:    br i1 [[CMP161]], label [[COND_TRUE162:%.*]], label [[COND_FALSE163:%.*]]
59783 // SIMD-ONLY0:       cond.true162:
59784 // SIMD-ONLY0-NEXT:    [[TMP167:%.*]] = load i64, ptr [[ULE]], align 8
59785 // SIMD-ONLY0-NEXT:    br label [[COND_END164:%.*]]
59786 // SIMD-ONLY0:       cond.false163:
59787 // SIMD-ONLY0-NEXT:    [[TMP168:%.*]] = load i64, ptr [[ULX]], align 8
59788 // SIMD-ONLY0-NEXT:    br label [[COND_END164]]
59789 // SIMD-ONLY0:       cond.end164:
59790 // SIMD-ONLY0-NEXT:    [[COND165:%.*]] = phi i64 [ [[TMP167]], [[COND_TRUE162]] ], [ [[TMP168]], [[COND_FALSE163]] ]
59791 // SIMD-ONLY0-NEXT:    store i64 [[COND165]], ptr [[ULX]], align 8
59792 // SIMD-ONLY0-NEXT:    [[TMP169:%.*]] = load i64, ptr [[ULX]], align 8
59793 // SIMD-ONLY0-NEXT:    store i64 [[TMP169]], ptr [[ULV]], align 8
59794 // SIMD-ONLY0-NEXT:    [[TMP170:%.*]] = load i64, ptr [[ULX]], align 8
59795 // SIMD-ONLY0-NEXT:    [[TMP171:%.*]] = load i64, ptr [[ULE]], align 8
59796 // SIMD-ONLY0-NEXT:    [[CMP166:%.*]] = icmp ult i64 [[TMP170]], [[TMP171]]
59797 // SIMD-ONLY0-NEXT:    br i1 [[CMP166]], label [[COND_TRUE167:%.*]], label [[COND_FALSE168:%.*]]
59798 // SIMD-ONLY0:       cond.true167:
59799 // SIMD-ONLY0-NEXT:    [[TMP172:%.*]] = load i64, ptr [[ULE]], align 8
59800 // SIMD-ONLY0-NEXT:    br label [[COND_END169:%.*]]
59801 // SIMD-ONLY0:       cond.false168:
59802 // SIMD-ONLY0-NEXT:    [[TMP173:%.*]] = load i64, ptr [[ULX]], align 8
59803 // SIMD-ONLY0-NEXT:    br label [[COND_END169]]
59804 // SIMD-ONLY0:       cond.end169:
59805 // SIMD-ONLY0-NEXT:    [[COND170:%.*]] = phi i64 [ [[TMP172]], [[COND_TRUE167]] ], [ [[TMP173]], [[COND_FALSE168]] ]
59806 // SIMD-ONLY0-NEXT:    store i64 [[COND170]], ptr [[ULX]], align 8
59807 // SIMD-ONLY0-NEXT:    [[TMP174:%.*]] = load i64, ptr [[ULX]], align 8
59808 // SIMD-ONLY0-NEXT:    store i64 [[TMP174]], ptr [[ULV]], align 8
59809 // SIMD-ONLY0-NEXT:    [[TMP175:%.*]] = load i64, ptr [[ULX]], align 8
59810 // SIMD-ONLY0-NEXT:    [[TMP176:%.*]] = load i64, ptr [[ULE]], align 8
59811 // SIMD-ONLY0-NEXT:    [[CMP171:%.*]] = icmp eq i64 [[TMP175]], [[TMP176]]
59812 // SIMD-ONLY0-NEXT:    br i1 [[CMP171]], label [[COND_TRUE172:%.*]], label [[COND_FALSE173:%.*]]
59813 // SIMD-ONLY0:       cond.true172:
59814 // SIMD-ONLY0-NEXT:    [[TMP177:%.*]] = load i64, ptr [[ULD]], align 8
59815 // SIMD-ONLY0-NEXT:    br label [[COND_END174:%.*]]
59816 // SIMD-ONLY0:       cond.false173:
59817 // SIMD-ONLY0-NEXT:    [[TMP178:%.*]] = load i64, ptr [[ULX]], align 8
59818 // SIMD-ONLY0-NEXT:    br label [[COND_END174]]
59819 // SIMD-ONLY0:       cond.end174:
59820 // SIMD-ONLY0-NEXT:    [[COND175:%.*]] = phi i64 [ [[TMP177]], [[COND_TRUE172]] ], [ [[TMP178]], [[COND_FALSE173]] ]
59821 // SIMD-ONLY0-NEXT:    store i64 [[COND175]], ptr [[ULX]], align 8
59822 // SIMD-ONLY0-NEXT:    [[TMP179:%.*]] = load i64, ptr [[ULX]], align 8
59823 // SIMD-ONLY0-NEXT:    store i64 [[TMP179]], ptr [[ULV]], align 8
59824 // SIMD-ONLY0-NEXT:    [[TMP180:%.*]] = load i64, ptr [[ULV]], align 8
59825 // SIMD-ONLY0-NEXT:    ret i64 [[TMP180]]
59826 //
59827 //
59828 // SIMD-ONLY0-LABEL: @llxevd(
59829 // SIMD-ONLY0-NEXT:  entry:
59830 // SIMD-ONLY0-NEXT:    [[LLX:%.*]] = alloca i64, align 8
59831 // SIMD-ONLY0-NEXT:    [[LLV:%.*]] = alloca i64, align 8
59832 // SIMD-ONLY0-NEXT:    [[LLE:%.*]] = alloca i64, align 8
59833 // SIMD-ONLY0-NEXT:    [[LLD:%.*]] = alloca i64, align 8
59834 // SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = load i64, ptr [[LLX]], align 8
59835 // SIMD-ONLY0-NEXT:    store i64 [[TMP0]], ptr [[LLV]], align 8
59836 // SIMD-ONLY0-NEXT:    [[TMP1:%.*]] = load i64, ptr [[LLX]], align 8
59837 // SIMD-ONLY0-NEXT:    [[TMP2:%.*]] = load i64, ptr [[LLE]], align 8
59838 // SIMD-ONLY0-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP1]], [[TMP2]]
59839 // SIMD-ONLY0-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
59840 // SIMD-ONLY0:       cond.true:
59841 // SIMD-ONLY0-NEXT:    [[TMP3:%.*]] = load i64, ptr [[LLE]], align 8
59842 // SIMD-ONLY0-NEXT:    br label [[COND_END:%.*]]
59843 // SIMD-ONLY0:       cond.false:
59844 // SIMD-ONLY0-NEXT:    [[TMP4:%.*]] = load i64, ptr [[LLX]], align 8
59845 // SIMD-ONLY0-NEXT:    br label [[COND_END]]
59846 // SIMD-ONLY0:       cond.end:
59847 // SIMD-ONLY0-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP3]], [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
59848 // SIMD-ONLY0-NEXT:    store i64 [[COND]], ptr [[LLX]], align 8
59849 // SIMD-ONLY0-NEXT:    [[TMP5:%.*]] = load i64, ptr [[LLX]], align 8
59850 // SIMD-ONLY0-NEXT:    store i64 [[TMP5]], ptr [[LLV]], align 8
59851 // SIMD-ONLY0-NEXT:    [[TMP6:%.*]] = load i64, ptr [[LLX]], align 8
59852 // SIMD-ONLY0-NEXT:    [[TMP7:%.*]] = load i64, ptr [[LLE]], align 8
59853 // SIMD-ONLY0-NEXT:    [[CMP1:%.*]] = icmp slt i64 [[TMP6]], [[TMP7]]
59854 // SIMD-ONLY0-NEXT:    br i1 [[CMP1]], label [[COND_TRUE2:%.*]], label [[COND_FALSE3:%.*]]
59855 // SIMD-ONLY0:       cond.true2:
59856 // SIMD-ONLY0-NEXT:    [[TMP8:%.*]] = load i64, ptr [[LLE]], align 8
59857 // SIMD-ONLY0-NEXT:    br label [[COND_END4:%.*]]
59858 // SIMD-ONLY0:       cond.false3:
59859 // SIMD-ONLY0-NEXT:    [[TMP9:%.*]] = load i64, ptr [[LLX]], align 8
59860 // SIMD-ONLY0-NEXT:    br label [[COND_END4]]
59861 // SIMD-ONLY0:       cond.end4:
59862 // SIMD-ONLY0-NEXT:    [[COND5:%.*]] = phi i64 [ [[TMP8]], [[COND_TRUE2]] ], [ [[TMP9]], [[COND_FALSE3]] ]
59863 // SIMD-ONLY0-NEXT:    store i64 [[COND5]], ptr [[LLX]], align 8
59864 // SIMD-ONLY0-NEXT:    [[TMP10:%.*]] = load i64, ptr [[LLX]], align 8
59865 // SIMD-ONLY0-NEXT:    store i64 [[TMP10]], ptr [[LLV]], align 8
59866 // SIMD-ONLY0-NEXT:    [[TMP11:%.*]] = load i64, ptr [[LLX]], align 8
59867 // SIMD-ONLY0-NEXT:    [[TMP12:%.*]] = load i64, ptr [[LLE]], align 8
59868 // SIMD-ONLY0-NEXT:    [[CMP6:%.*]] = icmp eq i64 [[TMP11]], [[TMP12]]
59869 // SIMD-ONLY0-NEXT:    br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
59870 // SIMD-ONLY0:       cond.true7:
59871 // SIMD-ONLY0-NEXT:    [[TMP13:%.*]] = load i64, ptr [[LLD]], align 8
59872 // SIMD-ONLY0-NEXT:    br label [[COND_END9:%.*]]
59873 // SIMD-ONLY0:       cond.false8:
59874 // SIMD-ONLY0-NEXT:    [[TMP14:%.*]] = load i64, ptr [[LLX]], align 8
59875 // SIMD-ONLY0-NEXT:    br label [[COND_END9]]
59876 // SIMD-ONLY0:       cond.end9:
59877 // SIMD-ONLY0-NEXT:    [[COND10:%.*]] = phi i64 [ [[TMP13]], [[COND_TRUE7]] ], [ [[TMP14]], [[COND_FALSE8]] ]
59878 // SIMD-ONLY0-NEXT:    store i64 [[COND10]], ptr [[LLX]], align 8
59879 // SIMD-ONLY0-NEXT:    [[TMP15:%.*]] = load i64, ptr [[LLX]], align 8
59880 // SIMD-ONLY0-NEXT:    [[TMP16:%.*]] = load i64, ptr [[LLE]], align 8
59881 // SIMD-ONLY0-NEXT:    [[CMP11:%.*]] = icmp sgt i64 [[TMP15]], [[TMP16]]
59882 // SIMD-ONLY0-NEXT:    br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
59883 // SIMD-ONLY0:       cond.true12:
59884 // SIMD-ONLY0-NEXT:    [[TMP17:%.*]] = load i64, ptr [[LLE]], align 8
59885 // SIMD-ONLY0-NEXT:    br label [[COND_END14:%.*]]
59886 // SIMD-ONLY0:       cond.false13:
59887 // SIMD-ONLY0-NEXT:    [[TMP18:%.*]] = load i64, ptr [[LLX]], align 8
59888 // SIMD-ONLY0-NEXT:    br label [[COND_END14]]
59889 // SIMD-ONLY0:       cond.end14:
59890 // SIMD-ONLY0-NEXT:    [[COND15:%.*]] = phi i64 [ [[TMP17]], [[COND_TRUE12]] ], [ [[TMP18]], [[COND_FALSE13]] ]
59891 // SIMD-ONLY0-NEXT:    store i64 [[COND15]], ptr [[LLX]], align 8
59892 // SIMD-ONLY0-NEXT:    [[TMP19:%.*]] = load i64, ptr [[LLX]], align 8
59893 // SIMD-ONLY0-NEXT:    store i64 [[TMP19]], ptr [[LLV]], align 8
59894 // SIMD-ONLY0-NEXT:    [[TMP20:%.*]] = load i64, ptr [[LLX]], align 8
59895 // SIMD-ONLY0-NEXT:    [[TMP21:%.*]] = load i64, ptr [[LLE]], align 8
59896 // SIMD-ONLY0-NEXT:    [[CMP16:%.*]] = icmp slt i64 [[TMP20]], [[TMP21]]
59897 // SIMD-ONLY0-NEXT:    br i1 [[CMP16]], label [[COND_TRUE17:%.*]], label [[COND_FALSE18:%.*]]
59898 // SIMD-ONLY0:       cond.true17:
59899 // SIMD-ONLY0-NEXT:    [[TMP22:%.*]] = load i64, ptr [[LLE]], align 8
59900 // SIMD-ONLY0-NEXT:    br label [[COND_END19:%.*]]
59901 // SIMD-ONLY0:       cond.false18:
59902 // SIMD-ONLY0-NEXT:    [[TMP23:%.*]] = load i64, ptr [[LLX]], align 8
59903 // SIMD-ONLY0-NEXT:    br label [[COND_END19]]
59904 // SIMD-ONLY0:       cond.end19:
59905 // SIMD-ONLY0-NEXT:    [[COND20:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE17]] ], [ [[TMP23]], [[COND_FALSE18]] ]
59906 // SIMD-ONLY0-NEXT:    store i64 [[COND20]], ptr [[LLX]], align 8
59907 // SIMD-ONLY0-NEXT:    [[TMP24:%.*]] = load i64, ptr [[LLX]], align 8
59908 // SIMD-ONLY0-NEXT:    store i64 [[TMP24]], ptr [[LLV]], align 8
59909 // SIMD-ONLY0-NEXT:    [[TMP25:%.*]] = load i64, ptr [[LLX]], align 8
59910 // SIMD-ONLY0-NEXT:    [[TMP26:%.*]] = load i64, ptr [[LLE]], align 8
59911 // SIMD-ONLY0-NEXT:    [[CMP21:%.*]] = icmp eq i64 [[TMP25]], [[TMP26]]
59912 // SIMD-ONLY0-NEXT:    br i1 [[CMP21]], label [[COND_TRUE22:%.*]], label [[COND_FALSE23:%.*]]
59913 // SIMD-ONLY0:       cond.true22:
59914 // SIMD-ONLY0-NEXT:    [[TMP27:%.*]] = load i64, ptr [[LLD]], align 8
59915 // SIMD-ONLY0-NEXT:    br label [[COND_END24:%.*]]
59916 // SIMD-ONLY0:       cond.false23:
59917 // SIMD-ONLY0-NEXT:    [[TMP28:%.*]] = load i64, ptr [[LLX]], align 8
59918 // SIMD-ONLY0-NEXT:    br label [[COND_END24]]
59919 // SIMD-ONLY0:       cond.end24:
59920 // SIMD-ONLY0-NEXT:    [[COND25:%.*]] = phi i64 [ [[TMP27]], [[COND_TRUE22]] ], [ [[TMP28]], [[COND_FALSE23]] ]
59921 // SIMD-ONLY0-NEXT:    store i64 [[COND25]], ptr [[LLX]], align 8
59922 // SIMD-ONLY0-NEXT:    [[TMP29:%.*]] = load i64, ptr [[LLX]], align 8
59923 // SIMD-ONLY0-NEXT:    store i64 [[TMP29]], ptr [[LLV]], align 8
59924 // SIMD-ONLY0-NEXT:    [[TMP30:%.*]] = load i64, ptr [[LLX]], align 8
59925 // SIMD-ONLY0-NEXT:    store i64 [[TMP30]], ptr [[LLV]], align 8
59926 // SIMD-ONLY0-NEXT:    [[TMP31:%.*]] = load i64, ptr [[LLX]], align 8
59927 // SIMD-ONLY0-NEXT:    [[TMP32:%.*]] = load i64, ptr [[LLE]], align 8
59928 // SIMD-ONLY0-NEXT:    [[CMP26:%.*]] = icmp sgt i64 [[TMP31]], [[TMP32]]
59929 // SIMD-ONLY0-NEXT:    br i1 [[CMP26]], label [[COND_TRUE27:%.*]], label [[COND_FALSE28:%.*]]
59930 // SIMD-ONLY0:       cond.true27:
59931 // SIMD-ONLY0-NEXT:    [[TMP33:%.*]] = load i64, ptr [[LLE]], align 8
59932 // SIMD-ONLY0-NEXT:    br label [[COND_END29:%.*]]
59933 // SIMD-ONLY0:       cond.false28:
59934 // SIMD-ONLY0-NEXT:    [[TMP34:%.*]] = load i64, ptr [[LLX]], align 8
59935 // SIMD-ONLY0-NEXT:    br label [[COND_END29]]
59936 // SIMD-ONLY0:       cond.end29:
59937 // SIMD-ONLY0-NEXT:    [[COND30:%.*]] = phi i64 [ [[TMP33]], [[COND_TRUE27]] ], [ [[TMP34]], [[COND_FALSE28]] ]
59938 // SIMD-ONLY0-NEXT:    store i64 [[COND30]], ptr [[LLX]], align 8
59939 // SIMD-ONLY0-NEXT:    [[TMP35:%.*]] = load i64, ptr [[LLX]], align 8
59940 // SIMD-ONLY0-NEXT:    store i64 [[TMP35]], ptr [[LLV]], align 8
59941 // SIMD-ONLY0-NEXT:    [[TMP36:%.*]] = load i64, ptr [[LLX]], align 8
59942 // SIMD-ONLY0-NEXT:    [[TMP37:%.*]] = load i64, ptr [[LLE]], align 8
59943 // SIMD-ONLY0-NEXT:    [[CMP31:%.*]] = icmp slt i64 [[TMP36]], [[TMP37]]
59944 // SIMD-ONLY0-NEXT:    br i1 [[CMP31]], label [[COND_TRUE32:%.*]], label [[COND_FALSE33:%.*]]
59945 // SIMD-ONLY0:       cond.true32:
59946 // SIMD-ONLY0-NEXT:    [[TMP38:%.*]] = load i64, ptr [[LLE]], align 8
59947 // SIMD-ONLY0-NEXT:    br label [[COND_END34:%.*]]
59948 // SIMD-ONLY0:       cond.false33:
59949 // SIMD-ONLY0-NEXT:    [[TMP39:%.*]] = load i64, ptr [[LLX]], align 8
59950 // SIMD-ONLY0-NEXT:    br label [[COND_END34]]
59951 // SIMD-ONLY0:       cond.end34:
59952 // SIMD-ONLY0-NEXT:    [[COND35:%.*]] = phi i64 [ [[TMP38]], [[COND_TRUE32]] ], [ [[TMP39]], [[COND_FALSE33]] ]
59953 // SIMD-ONLY0-NEXT:    store i64 [[COND35]], ptr [[LLX]], align 8
59954 // SIMD-ONLY0-NEXT:    [[TMP40:%.*]] = load i64, ptr [[LLX]], align 8
59955 // SIMD-ONLY0-NEXT:    store i64 [[TMP40]], ptr [[LLV]], align 8
59956 // SIMD-ONLY0-NEXT:    [[TMP41:%.*]] = load i64, ptr [[LLX]], align 8
59957 // SIMD-ONLY0-NEXT:    [[TMP42:%.*]] = load i64, ptr [[LLE]], align 8
59958 // SIMD-ONLY0-NEXT:    [[CMP36:%.*]] = icmp eq i64 [[TMP41]], [[TMP42]]
59959 // SIMD-ONLY0-NEXT:    br i1 [[CMP36]], label [[COND_TRUE37:%.*]], label [[COND_FALSE38:%.*]]
59960 // SIMD-ONLY0:       cond.true37:
59961 // SIMD-ONLY0-NEXT:    [[TMP43:%.*]] = load i64, ptr [[LLD]], align 8
59962 // SIMD-ONLY0-NEXT:    br label [[COND_END39:%.*]]
59963 // SIMD-ONLY0:       cond.false38:
59964 // SIMD-ONLY0-NEXT:    [[TMP44:%.*]] = load i64, ptr [[LLX]], align 8
59965 // SIMD-ONLY0-NEXT:    br label [[COND_END39]]
59966 // SIMD-ONLY0:       cond.end39:
59967 // SIMD-ONLY0-NEXT:    [[COND40:%.*]] = phi i64 [ [[TMP43]], [[COND_TRUE37]] ], [ [[TMP44]], [[COND_FALSE38]] ]
59968 // SIMD-ONLY0-NEXT:    store i64 [[COND40]], ptr [[LLX]], align 8
59969 // SIMD-ONLY0-NEXT:    [[TMP45:%.*]] = load i64, ptr [[LLX]], align 8
59970 // SIMD-ONLY0-NEXT:    [[TMP46:%.*]] = load i64, ptr [[LLE]], align 8
59971 // SIMD-ONLY0-NEXT:    [[CMP41:%.*]] = icmp sgt i64 [[TMP45]], [[TMP46]]
59972 // SIMD-ONLY0-NEXT:    br i1 [[CMP41]], label [[COND_TRUE42:%.*]], label [[COND_FALSE43:%.*]]
59973 // SIMD-ONLY0:       cond.true42:
59974 // SIMD-ONLY0-NEXT:    [[TMP47:%.*]] = load i64, ptr [[LLE]], align 8
59975 // SIMD-ONLY0-NEXT:    br label [[COND_END44:%.*]]
59976 // SIMD-ONLY0:       cond.false43:
59977 // SIMD-ONLY0-NEXT:    [[TMP48:%.*]] = load i64, ptr [[LLX]], align 8
59978 // SIMD-ONLY0-NEXT:    br label [[COND_END44]]
59979 // SIMD-ONLY0:       cond.end44:
59980 // SIMD-ONLY0-NEXT:    [[COND45:%.*]] = phi i64 [ [[TMP47]], [[COND_TRUE42]] ], [ [[TMP48]], [[COND_FALSE43]] ]
59981 // SIMD-ONLY0-NEXT:    store i64 [[COND45]], ptr [[LLX]], align 8
59982 // SIMD-ONLY0-NEXT:    [[TMP49:%.*]] = load i64, ptr [[LLX]], align 8
59983 // SIMD-ONLY0-NEXT:    store i64 [[TMP49]], ptr [[LLV]], align 8
59984 // SIMD-ONLY0-NEXT:    [[TMP50:%.*]] = load i64, ptr [[LLX]], align 8
59985 // SIMD-ONLY0-NEXT:    [[TMP51:%.*]] = load i64, ptr [[LLE]], align 8
59986 // SIMD-ONLY0-NEXT:    [[CMP46:%.*]] = icmp slt i64 [[TMP50]], [[TMP51]]
59987 // SIMD-ONLY0-NEXT:    br i1 [[CMP46]], label [[COND_TRUE47:%.*]], label [[COND_FALSE48:%.*]]
59988 // SIMD-ONLY0:       cond.true47:
59989 // SIMD-ONLY0-NEXT:    [[TMP52:%.*]] = load i64, ptr [[LLE]], align 8
59990 // SIMD-ONLY0-NEXT:    br label [[COND_END49:%.*]]
59991 // SIMD-ONLY0:       cond.false48:
59992 // SIMD-ONLY0-NEXT:    [[TMP53:%.*]] = load i64, ptr [[LLX]], align 8
59993 // SIMD-ONLY0-NEXT:    br label [[COND_END49]]
59994 // SIMD-ONLY0:       cond.end49:
59995 // SIMD-ONLY0-NEXT:    [[COND50:%.*]] = phi i64 [ [[TMP52]], [[COND_TRUE47]] ], [ [[TMP53]], [[COND_FALSE48]] ]
59996 // SIMD-ONLY0-NEXT:    store i64 [[COND50]], ptr [[LLX]], align 8
59997 // SIMD-ONLY0-NEXT:    [[TMP54:%.*]] = load i64, ptr [[LLX]], align 8
59998 // SIMD-ONLY0-NEXT:    store i64 [[TMP54]], ptr [[LLV]], align 8
59999 // SIMD-ONLY0-NEXT:    [[TMP55:%.*]] = load i64, ptr [[LLX]], align 8
60000 // SIMD-ONLY0-NEXT:    [[TMP56:%.*]] = load i64, ptr [[LLE]], align 8
60001 // SIMD-ONLY0-NEXT:    [[CMP51:%.*]] = icmp eq i64 [[TMP55]], [[TMP56]]
60002 // SIMD-ONLY0-NEXT:    br i1 [[CMP51]], label [[COND_TRUE52:%.*]], label [[COND_FALSE53:%.*]]
60003 // SIMD-ONLY0:       cond.true52:
60004 // SIMD-ONLY0-NEXT:    [[TMP57:%.*]] = load i64, ptr [[LLD]], align 8
60005 // SIMD-ONLY0-NEXT:    br label [[COND_END54:%.*]]
60006 // SIMD-ONLY0:       cond.false53:
60007 // SIMD-ONLY0-NEXT:    [[TMP58:%.*]] = load i64, ptr [[LLX]], align 8
60008 // SIMD-ONLY0-NEXT:    br label [[COND_END54]]
60009 // SIMD-ONLY0:       cond.end54:
60010 // SIMD-ONLY0-NEXT:    [[COND55:%.*]] = phi i64 [ [[TMP57]], [[COND_TRUE52]] ], [ [[TMP58]], [[COND_FALSE53]] ]
60011 // SIMD-ONLY0-NEXT:    store i64 [[COND55]], ptr [[LLX]], align 8
60012 // SIMD-ONLY0-NEXT:    [[TMP59:%.*]] = load i64, ptr [[LLX]], align 8
60013 // SIMD-ONLY0-NEXT:    store i64 [[TMP59]], ptr [[LLV]], align 8
60014 // SIMD-ONLY0-NEXT:    [[TMP60:%.*]] = load i64, ptr [[LLX]], align 8
60015 // SIMD-ONLY0-NEXT:    store i64 [[TMP60]], ptr [[LLV]], align 8
60016 // SIMD-ONLY0-NEXT:    [[TMP61:%.*]] = load i64, ptr [[LLX]], align 8
60017 // SIMD-ONLY0-NEXT:    [[TMP62:%.*]] = load i64, ptr [[LLE]], align 8
60018 // SIMD-ONLY0-NEXT:    [[CMP56:%.*]] = icmp sgt i64 [[TMP61]], [[TMP62]]
60019 // SIMD-ONLY0-NEXT:    br i1 [[CMP56]], label [[COND_TRUE57:%.*]], label [[COND_FALSE58:%.*]]
60020 // SIMD-ONLY0:       cond.true57:
60021 // SIMD-ONLY0-NEXT:    [[TMP63:%.*]] = load i64, ptr [[LLE]], align 8
60022 // SIMD-ONLY0-NEXT:    br label [[COND_END59:%.*]]
60023 // SIMD-ONLY0:       cond.false58:
60024 // SIMD-ONLY0-NEXT:    [[TMP64:%.*]] = load i64, ptr [[LLX]], align 8
60025 // SIMD-ONLY0-NEXT:    br label [[COND_END59]]
60026 // SIMD-ONLY0:       cond.end59:
60027 // SIMD-ONLY0-NEXT:    [[COND60:%.*]] = phi i64 [ [[TMP63]], [[COND_TRUE57]] ], [ [[TMP64]], [[COND_FALSE58]] ]
60028 // SIMD-ONLY0-NEXT:    store i64 [[COND60]], ptr [[LLX]], align 8
60029 // SIMD-ONLY0-NEXT:    [[TMP65:%.*]] = load i64, ptr [[LLX]], align 8
60030 // SIMD-ONLY0-NEXT:    store i64 [[TMP65]], ptr [[LLV]], align 8
60031 // SIMD-ONLY0-NEXT:    [[TMP66:%.*]] = load i64, ptr [[LLX]], align 8
60032 // SIMD-ONLY0-NEXT:    [[TMP67:%.*]] = load i64, ptr [[LLE]], align 8
60033 // SIMD-ONLY0-NEXT:    [[CMP61:%.*]] = icmp slt i64 [[TMP66]], [[TMP67]]
60034 // SIMD-ONLY0-NEXT:    br i1 [[CMP61]], label [[COND_TRUE62:%.*]], label [[COND_FALSE63:%.*]]
60035 // SIMD-ONLY0:       cond.true62:
60036 // SIMD-ONLY0-NEXT:    [[TMP68:%.*]] = load i64, ptr [[LLE]], align 8
60037 // SIMD-ONLY0-NEXT:    br label [[COND_END64:%.*]]
60038 // SIMD-ONLY0:       cond.false63:
60039 // SIMD-ONLY0-NEXT:    [[TMP69:%.*]] = load i64, ptr [[LLX]], align 8
60040 // SIMD-ONLY0-NEXT:    br label [[COND_END64]]
60041 // SIMD-ONLY0:       cond.end64:
60042 // SIMD-ONLY0-NEXT:    [[COND65:%.*]] = phi i64 [ [[TMP68]], [[COND_TRUE62]] ], [ [[TMP69]], [[COND_FALSE63]] ]
60043 // SIMD-ONLY0-NEXT:    store i64 [[COND65]], ptr [[LLX]], align 8
60044 // SIMD-ONLY0-NEXT:    [[TMP70:%.*]] = load i64, ptr [[LLX]], align 8
60045 // SIMD-ONLY0-NEXT:    store i64 [[TMP70]], ptr [[LLV]], align 8
60046 // SIMD-ONLY0-NEXT:    [[TMP71:%.*]] = load i64, ptr [[LLX]], align 8
60047 // SIMD-ONLY0-NEXT:    [[TMP72:%.*]] = load i64, ptr [[LLE]], align 8
60048 // SIMD-ONLY0-NEXT:    [[CMP66:%.*]] = icmp eq i64 [[TMP71]], [[TMP72]]
60049 // SIMD-ONLY0-NEXT:    br i1 [[CMP66]], label [[COND_TRUE67:%.*]], label [[COND_FALSE68:%.*]]
60050 // SIMD-ONLY0:       cond.true67:
60051 // SIMD-ONLY0-NEXT:    [[TMP73:%.*]] = load i64, ptr [[LLD]], align 8
60052 // SIMD-ONLY0-NEXT:    br label [[COND_END69:%.*]]
60053 // SIMD-ONLY0:       cond.false68:
60054 // SIMD-ONLY0-NEXT:    [[TMP74:%.*]] = load i64, ptr [[LLX]], align 8
60055 // SIMD-ONLY0-NEXT:    br label [[COND_END69]]
60056 // SIMD-ONLY0:       cond.end69:
60057 // SIMD-ONLY0-NEXT:    [[COND70:%.*]] = phi i64 [ [[TMP73]], [[COND_TRUE67]] ], [ [[TMP74]], [[COND_FALSE68]] ]
60058 // SIMD-ONLY0-NEXT:    store i64 [[COND70]], ptr [[LLX]], align 8
60059 // SIMD-ONLY0-NEXT:    [[TMP75:%.*]] = load i64, ptr [[LLX]], align 8
60060 // SIMD-ONLY0-NEXT:    [[TMP76:%.*]] = load i64, ptr [[LLE]], align 8
60061 // SIMD-ONLY0-NEXT:    [[CMP71:%.*]] = icmp sgt i64 [[TMP75]], [[TMP76]]
60062 // SIMD-ONLY0-NEXT:    br i1 [[CMP71]], label [[COND_TRUE72:%.*]], label [[COND_FALSE73:%.*]]
60063 // SIMD-ONLY0:       cond.true72:
60064 // SIMD-ONLY0-NEXT:    [[TMP77:%.*]] = load i64, ptr [[LLE]], align 8
60065 // SIMD-ONLY0-NEXT:    br label [[COND_END74:%.*]]
60066 // SIMD-ONLY0:       cond.false73:
60067 // SIMD-ONLY0-NEXT:    [[TMP78:%.*]] = load i64, ptr [[LLX]], align 8
60068 // SIMD-ONLY0-NEXT:    br label [[COND_END74]]
60069 // SIMD-ONLY0:       cond.end74:
60070 // SIMD-ONLY0-NEXT:    [[COND75:%.*]] = phi i64 [ [[TMP77]], [[COND_TRUE72]] ], [ [[TMP78]], [[COND_FALSE73]] ]
60071 // SIMD-ONLY0-NEXT:    store i64 [[COND75]], ptr [[LLX]], align 8
60072 // SIMD-ONLY0-NEXT:    [[TMP79:%.*]] = load i64, ptr [[LLX]], align 8
60073 // SIMD-ONLY0-NEXT:    store i64 [[TMP79]], ptr [[LLV]], align 8
60074 // SIMD-ONLY0-NEXT:    [[TMP80:%.*]] = load i64, ptr [[LLX]], align 8
60075 // SIMD-ONLY0-NEXT:    [[TMP81:%.*]] = load i64, ptr [[LLE]], align 8
60076 // SIMD-ONLY0-NEXT:    [[CMP76:%.*]] = icmp slt i64 [[TMP80]], [[TMP81]]
60077 // SIMD-ONLY0-NEXT:    br i1 [[CMP76]], label [[COND_TRUE77:%.*]], label [[COND_FALSE78:%.*]]
60078 // SIMD-ONLY0:       cond.true77:
60079 // SIMD-ONLY0-NEXT:    [[TMP82:%.*]] = load i64, ptr [[LLE]], align 8
60080 // SIMD-ONLY0-NEXT:    br label [[COND_END79:%.*]]
60081 // SIMD-ONLY0:       cond.false78:
60082 // SIMD-ONLY0-NEXT:    [[TMP83:%.*]] = load i64, ptr [[LLX]], align 8
60083 // SIMD-ONLY0-NEXT:    br label [[COND_END79]]
60084 // SIMD-ONLY0:       cond.end79:
60085 // SIMD-ONLY0-NEXT:    [[COND80:%.*]] = phi i64 [ [[TMP82]], [[COND_TRUE77]] ], [ [[TMP83]], [[COND_FALSE78]] ]
60086 // SIMD-ONLY0-NEXT:    store i64 [[COND80]], ptr [[LLX]], align 8
60087 // SIMD-ONLY0-NEXT:    [[TMP84:%.*]] = load i64, ptr [[LLX]], align 8
60088 // SIMD-ONLY0-NEXT:    store i64 [[TMP84]], ptr [[LLV]], align 8
60089 // SIMD-ONLY0-NEXT:    [[TMP85:%.*]] = load i64, ptr [[LLX]], align 8
60090 // SIMD-ONLY0-NEXT:    [[TMP86:%.*]] = load i64, ptr [[LLE]], align 8
60091 // SIMD-ONLY0-NEXT:    [[CMP81:%.*]] = icmp eq i64 [[TMP85]], [[TMP86]]
60092 // SIMD-ONLY0-NEXT:    br i1 [[CMP81]], label [[COND_TRUE82:%.*]], label [[COND_FALSE83:%.*]]
60093 // SIMD-ONLY0:       cond.true82:
60094 // SIMD-ONLY0-NEXT:    [[TMP87:%.*]] = load i64, ptr [[LLD]], align 8
60095 // SIMD-ONLY0-NEXT:    br label [[COND_END84:%.*]]
60096 // SIMD-ONLY0:       cond.false83:
60097 // SIMD-ONLY0-NEXT:    [[TMP88:%.*]] = load i64, ptr [[LLX]], align 8
60098 // SIMD-ONLY0-NEXT:    br label [[COND_END84]]
60099 // SIMD-ONLY0:       cond.end84:
60100 // SIMD-ONLY0-NEXT:    [[COND85:%.*]] = phi i64 [ [[TMP87]], [[COND_TRUE82]] ], [ [[TMP88]], [[COND_FALSE83]] ]
60101 // SIMD-ONLY0-NEXT:    store i64 [[COND85]], ptr [[LLX]], align 8
60102 // SIMD-ONLY0-NEXT:    [[TMP89:%.*]] = load i64, ptr [[LLX]], align 8
60103 // SIMD-ONLY0-NEXT:    store i64 [[TMP89]], ptr [[LLV]], align 8
60104 // SIMD-ONLY0-NEXT:    [[TMP90:%.*]] = load i64, ptr [[LLX]], align 8
60105 // SIMD-ONLY0-NEXT:    store i64 [[TMP90]], ptr [[LLV]], align 8
60106 // SIMD-ONLY0-NEXT:    [[TMP91:%.*]] = load i64, ptr [[LLX]], align 8
60107 // SIMD-ONLY0-NEXT:    [[TMP92:%.*]] = load i64, ptr [[LLE]], align 8
60108 // SIMD-ONLY0-NEXT:    [[CMP86:%.*]] = icmp sgt i64 [[TMP91]], [[TMP92]]
60109 // SIMD-ONLY0-NEXT:    br i1 [[CMP86]], label [[COND_TRUE87:%.*]], label [[COND_FALSE88:%.*]]
60110 // SIMD-ONLY0:       cond.true87:
60111 // SIMD-ONLY0-NEXT:    [[TMP93:%.*]] = load i64, ptr [[LLE]], align 8
60112 // SIMD-ONLY0-NEXT:    br label [[COND_END89:%.*]]
60113 // SIMD-ONLY0:       cond.false88:
60114 // SIMD-ONLY0-NEXT:    [[TMP94:%.*]] = load i64, ptr [[LLX]], align 8
60115 // SIMD-ONLY0-NEXT:    br label [[COND_END89]]
60116 // SIMD-ONLY0:       cond.end89:
60117 // SIMD-ONLY0-NEXT:    [[COND90:%.*]] = phi i64 [ [[TMP93]], [[COND_TRUE87]] ], [ [[TMP94]], [[COND_FALSE88]] ]
60118 // SIMD-ONLY0-NEXT:    store i64 [[COND90]], ptr [[LLX]], align 8
60119 // SIMD-ONLY0-NEXT:    [[TMP95:%.*]] = load i64, ptr [[LLX]], align 8
60120 // SIMD-ONLY0-NEXT:    store i64 [[TMP95]], ptr [[LLV]], align 8
60121 // SIMD-ONLY0-NEXT:    [[TMP96:%.*]] = load i64, ptr [[LLX]], align 8
60122 // SIMD-ONLY0-NEXT:    [[TMP97:%.*]] = load i64, ptr [[LLE]], align 8
60123 // SIMD-ONLY0-NEXT:    [[CMP91:%.*]] = icmp slt i64 [[TMP96]], [[TMP97]]
60124 // SIMD-ONLY0-NEXT:    br i1 [[CMP91]], label [[COND_TRUE92:%.*]], label [[COND_FALSE93:%.*]]
60125 // SIMD-ONLY0:       cond.true92:
60126 // SIMD-ONLY0-NEXT:    [[TMP98:%.*]] = load i64, ptr [[LLE]], align 8
60127 // SIMD-ONLY0-NEXT:    br label [[COND_END94:%.*]]
60128 // SIMD-ONLY0:       cond.false93:
60129 // SIMD-ONLY0-NEXT:    [[TMP99:%.*]] = load i64, ptr [[LLX]], align 8
60130 // SIMD-ONLY0-NEXT:    br label [[COND_END94]]
60131 // SIMD-ONLY0:       cond.end94:
60132 // SIMD-ONLY0-NEXT:    [[COND95:%.*]] = phi i64 [ [[TMP98]], [[COND_TRUE92]] ], [ [[TMP99]], [[COND_FALSE93]] ]
60133 // SIMD-ONLY0-NEXT:    store i64 [[COND95]], ptr [[LLX]], align 8
60134 // SIMD-ONLY0-NEXT:    [[TMP100:%.*]] = load i64, ptr [[LLX]], align 8
60135 // SIMD-ONLY0-NEXT:    store i64 [[TMP100]], ptr [[LLV]], align 8
60136 // SIMD-ONLY0-NEXT:    [[TMP101:%.*]] = load i64, ptr [[LLX]], align 8
60137 // SIMD-ONLY0-NEXT:    [[TMP102:%.*]] = load i64, ptr [[LLE]], align 8
60138 // SIMD-ONLY0-NEXT:    [[CMP96:%.*]] = icmp eq i64 [[TMP101]], [[TMP102]]
60139 // SIMD-ONLY0-NEXT:    br i1 [[CMP96]], label [[COND_TRUE97:%.*]], label [[COND_FALSE98:%.*]]
60140 // SIMD-ONLY0:       cond.true97:
60141 // SIMD-ONLY0-NEXT:    [[TMP103:%.*]] = load i64, ptr [[LLD]], align 8
60142 // SIMD-ONLY0-NEXT:    br label [[COND_END99:%.*]]
60143 // SIMD-ONLY0:       cond.false98:
60144 // SIMD-ONLY0-NEXT:    [[TMP104:%.*]] = load i64, ptr [[LLX]], align 8
60145 // SIMD-ONLY0-NEXT:    br label [[COND_END99]]
60146 // SIMD-ONLY0:       cond.end99:
60147 // SIMD-ONLY0-NEXT:    [[COND100:%.*]] = phi i64 [ [[TMP103]], [[COND_TRUE97]] ], [ [[TMP104]], [[COND_FALSE98]] ]
60148 // SIMD-ONLY0-NEXT:    store i64 [[COND100]], ptr [[LLX]], align 8
60149 // SIMD-ONLY0-NEXT:    [[TMP105:%.*]] = load i64, ptr [[LLX]], align 8
60150 // SIMD-ONLY0-NEXT:    [[TMP106:%.*]] = load i64, ptr [[LLE]], align 8
60151 // SIMD-ONLY0-NEXT:    [[CMP101:%.*]] = icmp sgt i64 [[TMP105]], [[TMP106]]
60152 // SIMD-ONLY0-NEXT:    br i1 [[CMP101]], label [[COND_TRUE102:%.*]], label [[COND_FALSE103:%.*]]
60153 // SIMD-ONLY0:       cond.true102:
60154 // SIMD-ONLY0-NEXT:    [[TMP107:%.*]] = load i64, ptr [[LLE]], align 8
60155 // SIMD-ONLY0-NEXT:    br label [[COND_END104:%.*]]
60156 // SIMD-ONLY0:       cond.false103:
60157 // SIMD-ONLY0-NEXT:    [[TMP108:%.*]] = load i64, ptr [[LLX]], align 8
60158 // SIMD-ONLY0-NEXT:    br label [[COND_END104]]
60159 // SIMD-ONLY0:       cond.end104:
60160 // SIMD-ONLY0-NEXT:    [[COND105:%.*]] = phi i64 [ [[TMP107]], [[COND_TRUE102]] ], [ [[TMP108]], [[COND_FALSE103]] ]
60161 // SIMD-ONLY0-NEXT:    store i64 [[COND105]], ptr [[LLX]], align 8
60162 // SIMD-ONLY0-NEXT:    [[TMP109:%.*]] = load i64, ptr [[LLX]], align 8
60163 // SIMD-ONLY0-NEXT:    store i64 [[TMP109]], ptr [[LLV]], align 8
60164 // SIMD-ONLY0-NEXT:    [[TMP110:%.*]] = load i64, ptr [[LLX]], align 8
60165 // SIMD-ONLY0-NEXT:    [[TMP111:%.*]] = load i64, ptr [[LLE]], align 8
60166 // SIMD-ONLY0-NEXT:    [[CMP106:%.*]] = icmp slt i64 [[TMP110]], [[TMP111]]
60167 // SIMD-ONLY0-NEXT:    br i1 [[CMP106]], label [[COND_TRUE107:%.*]], label [[COND_FALSE108:%.*]]
60168 // SIMD-ONLY0:       cond.true107:
60169 // SIMD-ONLY0-NEXT:    [[TMP112:%.*]] = load i64, ptr [[LLE]], align 8
60170 // SIMD-ONLY0-NEXT:    br label [[COND_END109:%.*]]
60171 // SIMD-ONLY0:       cond.false108:
60172 // SIMD-ONLY0-NEXT:    [[TMP113:%.*]] = load i64, ptr [[LLX]], align 8
60173 // SIMD-ONLY0-NEXT:    br label [[COND_END109]]
60174 // SIMD-ONLY0:       cond.end109:
60175 // SIMD-ONLY0-NEXT:    [[COND110:%.*]] = phi i64 [ [[TMP112]], [[COND_TRUE107]] ], [ [[TMP113]], [[COND_FALSE108]] ]
60176 // SIMD-ONLY0-NEXT:    store i64 [[COND110]], ptr [[LLX]], align 8
60177 // SIMD-ONLY0-NEXT:    [[TMP114:%.*]] = load i64, ptr [[LLX]], align 8
60178 // SIMD-ONLY0-NEXT:    store i64 [[TMP114]], ptr [[LLV]], align 8
60179 // SIMD-ONLY0-NEXT:    [[TMP115:%.*]] = load i64, ptr [[LLX]], align 8
60180 // SIMD-ONLY0-NEXT:    [[TMP116:%.*]] = load i64, ptr [[LLE]], align 8
60181 // SIMD-ONLY0-NEXT:    [[CMP111:%.*]] = icmp eq i64 [[TMP115]], [[TMP116]]
60182 // SIMD-ONLY0-NEXT:    br i1 [[CMP111]], label [[COND_TRUE112:%.*]], label [[COND_FALSE113:%.*]]
60183 // SIMD-ONLY0:       cond.true112:
60184 // SIMD-ONLY0-NEXT:    [[TMP117:%.*]] = load i64, ptr [[LLD]], align 8
60185 // SIMD-ONLY0-NEXT:    br label [[COND_END114:%.*]]
60186 // SIMD-ONLY0:       cond.false113:
60187 // SIMD-ONLY0-NEXT:    [[TMP118:%.*]] = load i64, ptr [[LLX]], align 8
60188 // SIMD-ONLY0-NEXT:    br label [[COND_END114]]
60189 // SIMD-ONLY0:       cond.end114:
60190 // SIMD-ONLY0-NEXT:    [[COND115:%.*]] = phi i64 [ [[TMP117]], [[COND_TRUE112]] ], [ [[TMP118]], [[COND_FALSE113]] ]
60191 // SIMD-ONLY0-NEXT:    store i64 [[COND115]], ptr [[LLX]], align 8
60192 // SIMD-ONLY0-NEXT:    [[TMP119:%.*]] = load i64, ptr [[LLX]], align 8
60193 // SIMD-ONLY0-NEXT:    store i64 [[TMP119]], ptr [[LLV]], align 8
60194 // SIMD-ONLY0-NEXT:    [[TMP120:%.*]] = load i64, ptr [[LLX]], align 8
60195 // SIMD-ONLY0-NEXT:    store i64 [[TMP120]], ptr [[LLV]], align 8
60196 // SIMD-ONLY0-NEXT:    [[TMP121:%.*]] = load i64, ptr [[LLX]], align 8
60197 // SIMD-ONLY0-NEXT:    [[TMP122:%.*]] = load i64, ptr [[LLE]], align 8
60198 // SIMD-ONLY0-NEXT:    [[CMP116:%.*]] = icmp sgt i64 [[TMP121]], [[TMP122]]
60199 // SIMD-ONLY0-NEXT:    br i1 [[CMP116]], label [[COND_TRUE117:%.*]], label [[COND_FALSE118:%.*]]
60200 // SIMD-ONLY0:       cond.true117:
60201 // SIMD-ONLY0-NEXT:    [[TMP123:%.*]] = load i64, ptr [[LLE]], align 8
60202 // SIMD-ONLY0-NEXT:    br label [[COND_END119:%.*]]
60203 // SIMD-ONLY0:       cond.false118:
60204 // SIMD-ONLY0-NEXT:    [[TMP124:%.*]] = load i64, ptr [[LLX]], align 8
60205 // SIMD-ONLY0-NEXT:    br label [[COND_END119]]
60206 // SIMD-ONLY0:       cond.end119:
60207 // SIMD-ONLY0-NEXT:    [[COND120:%.*]] = phi i64 [ [[TMP123]], [[COND_TRUE117]] ], [ [[TMP124]], [[COND_FALSE118]] ]
60208 // SIMD-ONLY0-NEXT:    store i64 [[COND120]], ptr [[LLX]], align 8
60209 // SIMD-ONLY0-NEXT:    [[TMP125:%.*]] = load i64, ptr [[LLX]], align 8
60210 // SIMD-ONLY0-NEXT:    store i64 [[TMP125]], ptr [[LLV]], align 8
60211 // SIMD-ONLY0-NEXT:    [[TMP126:%.*]] = load i64, ptr [[LLX]], align 8
60212 // SIMD-ONLY0-NEXT:    [[TMP127:%.*]] = load i64, ptr [[LLE]], align 8
60213 // SIMD-ONLY0-NEXT:    [[CMP121:%.*]] = icmp slt i64 [[TMP126]], [[TMP127]]
60214 // SIMD-ONLY0-NEXT:    br i1 [[CMP121]], label [[COND_TRUE122:%.*]], label [[COND_FALSE123:%.*]]
60215 // SIMD-ONLY0:       cond.true122:
60216 // SIMD-ONLY0-NEXT:    [[TMP128:%.*]] = load i64, ptr [[LLE]], align 8
60217 // SIMD-ONLY0-NEXT:    br label [[COND_END124:%.*]]
60218 // SIMD-ONLY0:       cond.false123:
60219 // SIMD-ONLY0-NEXT:    [[TMP129:%.*]] = load i64, ptr [[LLX]], align 8
60220 // SIMD-ONLY0-NEXT:    br label [[COND_END124]]
60221 // SIMD-ONLY0:       cond.end124:
60222 // SIMD-ONLY0-NEXT:    [[COND125:%.*]] = phi i64 [ [[TMP128]], [[COND_TRUE122]] ], [ [[TMP129]], [[COND_FALSE123]] ]
60223 // SIMD-ONLY0-NEXT:    store i64 [[COND125]], ptr [[LLX]], align 8
60224 // SIMD-ONLY0-NEXT:    [[TMP130:%.*]] = load i64, ptr [[LLX]], align 8
60225 // SIMD-ONLY0-NEXT:    store i64 [[TMP130]], ptr [[LLV]], align 8
60226 // SIMD-ONLY0-NEXT:    [[TMP131:%.*]] = load i64, ptr [[LLX]], align 8
60227 // SIMD-ONLY0-NEXT:    [[TMP132:%.*]] = load i64, ptr [[LLE]], align 8
60228 // SIMD-ONLY0-NEXT:    [[CMP126:%.*]] = icmp eq i64 [[TMP131]], [[TMP132]]
60229 // SIMD-ONLY0-NEXT:    br i1 [[CMP126]], label [[COND_TRUE127:%.*]], label [[COND_FALSE128:%.*]]
60230 // SIMD-ONLY0:       cond.true127:
60231 // SIMD-ONLY0-NEXT:    [[TMP133:%.*]] = load i64, ptr [[LLD]], align 8
60232 // SIMD-ONLY0-NEXT:    br label [[COND_END129:%.*]]
60233 // SIMD-ONLY0:       cond.false128:
60234 // SIMD-ONLY0-NEXT:    [[TMP134:%.*]] = load i64, ptr [[LLX]], align 8
60235 // SIMD-ONLY0-NEXT:    br label [[COND_END129]]
60236 // SIMD-ONLY0:       cond.end129:
60237 // SIMD-ONLY0-NEXT:    [[COND130:%.*]] = phi i64 [ [[TMP133]], [[COND_TRUE127]] ], [ [[TMP134]], [[COND_FALSE128]] ]
60238 // SIMD-ONLY0-NEXT:    store i64 [[COND130]], ptr [[LLX]], align 8
60239 // SIMD-ONLY0-NEXT:    [[TMP135:%.*]] = load i64, ptr [[LLX]], align 8
60240 // SIMD-ONLY0-NEXT:    [[TMP136:%.*]] = load i64, ptr [[LLE]], align 8
60241 // SIMD-ONLY0-NEXT:    [[CMP131:%.*]] = icmp sgt i64 [[TMP135]], [[TMP136]]
60242 // SIMD-ONLY0-NEXT:    br i1 [[CMP131]], label [[COND_TRUE132:%.*]], label [[COND_FALSE133:%.*]]
60243 // SIMD-ONLY0:       cond.true132:
60244 // SIMD-ONLY0-NEXT:    [[TMP137:%.*]] = load i64, ptr [[LLE]], align 8
60245 // SIMD-ONLY0-NEXT:    br label [[COND_END134:%.*]]
60246 // SIMD-ONLY0:       cond.false133:
60247 // SIMD-ONLY0-NEXT:    [[TMP138:%.*]] = load i64, ptr [[LLX]], align 8
60248 // SIMD-ONLY0-NEXT:    br label [[COND_END134]]
60249 // SIMD-ONLY0:       cond.end134:
60250 // SIMD-ONLY0-NEXT:    [[COND135:%.*]] = phi i64 [ [[TMP137]], [[COND_TRUE132]] ], [ [[TMP138]], [[COND_FALSE133]] ]
60251 // SIMD-ONLY0-NEXT:    store i64 [[COND135]], ptr [[LLX]], align 8
60252 // SIMD-ONLY0-NEXT:    [[TMP139:%.*]] = load i64, ptr [[LLX]], align 8
60253 // SIMD-ONLY0-NEXT:    store i64 [[TMP139]], ptr [[LLV]], align 8
60254 // SIMD-ONLY0-NEXT:    [[TMP140:%.*]] = load i64, ptr [[LLX]], align 8
60255 // SIMD-ONLY0-NEXT:    [[TMP141:%.*]] = load i64, ptr [[LLE]], align 8
60256 // SIMD-ONLY0-NEXT:    [[CMP136:%.*]] = icmp slt i64 [[TMP140]], [[TMP141]]
60257 // SIMD-ONLY0-NEXT:    br i1 [[CMP136]], label [[COND_TRUE137:%.*]], label [[COND_FALSE138:%.*]]
60258 // SIMD-ONLY0:       cond.true137:
60259 // SIMD-ONLY0-NEXT:    [[TMP142:%.*]] = load i64, ptr [[LLE]], align 8
60260 // SIMD-ONLY0-NEXT:    br label [[COND_END139:%.*]]
60261 // SIMD-ONLY0:       cond.false138:
60262 // SIMD-ONLY0-NEXT:    [[TMP143:%.*]] = load i64, ptr [[LLX]], align 8
60263 // SIMD-ONLY0-NEXT:    br label [[COND_END139]]
60264 // SIMD-ONLY0:       cond.end139:
60265 // SIMD-ONLY0-NEXT:    [[COND140:%.*]] = phi i64 [ [[TMP142]], [[COND_TRUE137]] ], [ [[TMP143]], [[COND_FALSE138]] ]
60266 // SIMD-ONLY0-NEXT:    store i64 [[COND140]], ptr [[LLX]], align 8
60267 // SIMD-ONLY0-NEXT:    [[TMP144:%.*]] = load i64, ptr [[LLX]], align 8
60268 // SIMD-ONLY0-NEXT:    store i64 [[TMP144]], ptr [[LLV]], align 8
60269 // SIMD-ONLY0-NEXT:    [[TMP145:%.*]] = load i64, ptr [[LLX]], align 8
60270 // SIMD-ONLY0-NEXT:    [[TMP146:%.*]] = load i64, ptr [[LLE]], align 8
60271 // SIMD-ONLY0-NEXT:    [[CMP141:%.*]] = icmp eq i64 [[TMP145]], [[TMP146]]
60272 // SIMD-ONLY0-NEXT:    br i1 [[CMP141]], label [[COND_TRUE142:%.*]], label [[COND_FALSE143:%.*]]
60273 // SIMD-ONLY0:       cond.true142:
60274 // SIMD-ONLY0-NEXT:    [[TMP147:%.*]] = load i64, ptr [[LLD]], align 8
60275 // SIMD-ONLY0-NEXT:    br label [[COND_END144:%.*]]
60276 // SIMD-ONLY0:       cond.false143:
60277 // SIMD-ONLY0-NEXT:    [[TMP148:%.*]] = load i64, ptr [[LLX]], align 8
60278 // SIMD-ONLY0-NEXT:    br label [[COND_END144]]
60279 // SIMD-ONLY0:       cond.end144:
60280 // SIMD-ONLY0-NEXT:    [[COND145:%.*]] = phi i64 [ [[TMP147]], [[COND_TRUE142]] ], [ [[TMP148]], [[COND_FALSE143]] ]
60281 // SIMD-ONLY0-NEXT:    store i64 [[COND145]], ptr [[LLX]], align 8
60282 // SIMD-ONLY0-NEXT:    [[TMP149:%.*]] = load i64, ptr [[LLX]], align 8
60283 // SIMD-ONLY0-NEXT:    store i64 [[TMP149]], ptr [[LLV]], align 8
60284 // SIMD-ONLY0-NEXT:    [[TMP150:%.*]] = load i64, ptr [[LLX]], align 8
60285 // SIMD-ONLY0-NEXT:    store i64 [[TMP150]], ptr [[LLV]], align 8
60286 // SIMD-ONLY0-NEXT:    [[TMP151:%.*]] = load i64, ptr [[LLX]], align 8
60287 // SIMD-ONLY0-NEXT:    [[TMP152:%.*]] = load i64, ptr [[LLE]], align 8
60288 // SIMD-ONLY0-NEXT:    [[CMP146:%.*]] = icmp sgt i64 [[TMP151]], [[TMP152]]
60289 // SIMD-ONLY0-NEXT:    br i1 [[CMP146]], label [[COND_TRUE147:%.*]], label [[COND_FALSE148:%.*]]
60290 // SIMD-ONLY0:       cond.true147:
60291 // SIMD-ONLY0-NEXT:    [[TMP153:%.*]] = load i64, ptr [[LLE]], align 8
60292 // SIMD-ONLY0-NEXT:    br label [[COND_END149:%.*]]
60293 // SIMD-ONLY0:       cond.false148:
60294 // SIMD-ONLY0-NEXT:    [[TMP154:%.*]] = load i64, ptr [[LLX]], align 8
60295 // SIMD-ONLY0-NEXT:    br label [[COND_END149]]
60296 // SIMD-ONLY0:       cond.end149:
60297 // SIMD-ONLY0-NEXT:    [[COND150:%.*]] = phi i64 [ [[TMP153]], [[COND_TRUE147]] ], [ [[TMP154]], [[COND_FALSE148]] ]
60298 // SIMD-ONLY0-NEXT:    store i64 [[COND150]], ptr [[LLX]], align 8
60299 // SIMD-ONLY0-NEXT:    [[TMP155:%.*]] = load i64, ptr [[LLX]], align 8
60300 // SIMD-ONLY0-NEXT:    store i64 [[TMP155]], ptr [[LLV]], align 8
60301 // SIMD-ONLY0-NEXT:    [[TMP156:%.*]] = load i64, ptr [[LLX]], align 8
60302 // SIMD-ONLY0-NEXT:    [[TMP157:%.*]] = load i64, ptr [[LLE]], align 8
60303 // SIMD-ONLY0-NEXT:    [[CMP151:%.*]] = icmp slt i64 [[TMP156]], [[TMP157]]
60304 // SIMD-ONLY0-NEXT:    br i1 [[CMP151]], label [[COND_TRUE152:%.*]], label [[COND_FALSE153:%.*]]
60305 // SIMD-ONLY0:       cond.true152:
60306 // SIMD-ONLY0-NEXT:    [[TMP158:%.*]] = load i64, ptr [[LLE]], align 8
60307 // SIMD-ONLY0-NEXT:    br label [[COND_END154:%.*]]
60308 // SIMD-ONLY0:       cond.false153:
60309 // SIMD-ONLY0-NEXT:    [[TMP159:%.*]] = load i64, ptr [[LLX]], align 8
60310 // SIMD-ONLY0-NEXT:    br label [[COND_END154]]
60311 // SIMD-ONLY0:       cond.end154:
60312 // SIMD-ONLY0-NEXT:    [[COND155:%.*]] = phi i64 [ [[TMP158]], [[COND_TRUE152]] ], [ [[TMP159]], [[COND_FALSE153]] ]
60313 // SIMD-ONLY0-NEXT:    store i64 [[COND155]], ptr [[LLX]], align 8
60314 // SIMD-ONLY0-NEXT:    [[TMP160:%.*]] = load i64, ptr [[LLX]], align 8
60315 // SIMD-ONLY0-NEXT:    store i64 [[TMP160]], ptr [[LLV]], align 8
60316 // SIMD-ONLY0-NEXT:    [[TMP161:%.*]] = load i64, ptr [[LLX]], align 8
60317 // SIMD-ONLY0-NEXT:    [[TMP162:%.*]] = load i64, ptr [[LLE]], align 8
60318 // SIMD-ONLY0-NEXT:    [[CMP156:%.*]] = icmp eq i64 [[TMP161]], [[TMP162]]
60319 // SIMD-ONLY0-NEXT:    br i1 [[CMP156]], label [[COND_TRUE157:%.*]], label [[COND_FALSE158:%.*]]
60320 // SIMD-ONLY0:       cond.true157:
60321 // SIMD-ONLY0-NEXT:    [[TMP163:%.*]] = load i64, ptr [[LLD]], align 8
60322 // SIMD-ONLY0-NEXT:    br label [[COND_END159:%.*]]
60323 // SIMD-ONLY0:       cond.false158:
60324 // SIMD-ONLY0-NEXT:    [[TMP164:%.*]] = load i64, ptr [[LLX]], align 8
60325 // SIMD-ONLY0-NEXT:    br label [[COND_END159]]
60326 // SIMD-ONLY0:       cond.end159:
60327 // SIMD-ONLY0-NEXT:    [[COND160:%.*]] = phi i64 [ [[TMP163]], [[COND_TRUE157]] ], [ [[TMP164]], [[COND_FALSE158]] ]
60328 // SIMD-ONLY0-NEXT:    store i64 [[COND160]], ptr [[LLX]], align 8
60329 // SIMD-ONLY0-NEXT:    [[TMP165:%.*]] = load i64, ptr [[LLX]], align 8
60330 // SIMD-ONLY0-NEXT:    [[TMP166:%.*]] = load i64, ptr [[LLE]], align 8
60331 // SIMD-ONLY0-NEXT:    [[CMP161:%.*]] = icmp sgt i64 [[TMP165]], [[TMP166]]
60332 // SIMD-ONLY0-NEXT:    br i1 [[CMP161]], label [[COND_TRUE162:%.*]], label [[COND_FALSE163:%.*]]
60333 // SIMD-ONLY0:       cond.true162:
60334 // SIMD-ONLY0-NEXT:    [[TMP167:%.*]] = load i64, ptr [[LLE]], align 8
60335 // SIMD-ONLY0-NEXT:    br label [[COND_END164:%.*]]
60336 // SIMD-ONLY0:       cond.false163:
60337 // SIMD-ONLY0-NEXT:    [[TMP168:%.*]] = load i64, ptr [[LLX]], align 8
60338 // SIMD-ONLY0-NEXT:    br label [[COND_END164]]
60339 // SIMD-ONLY0:       cond.end164:
60340 // SIMD-ONLY0-NEXT:    [[COND165:%.*]] = phi i64 [ [[TMP167]], [[COND_TRUE162]] ], [ [[TMP168]], [[COND_FALSE163]] ]
60341 // SIMD-ONLY0-NEXT:    store i64 [[COND165]], ptr [[LLX]], align 8
60342 // SIMD-ONLY0-NEXT:    [[TMP169:%.*]] = load i64, ptr [[LLX]], align 8
60343 // SIMD-ONLY0-NEXT:    store i64 [[TMP169]], ptr [[LLV]], align 8
60344 // SIMD-ONLY0-NEXT:    [[TMP170:%.*]] = load i64, ptr [[LLX]], align 8
60345 // SIMD-ONLY0-NEXT:    [[TMP171:%.*]] = load i64, ptr [[LLE]], align 8
60346 // SIMD-ONLY0-NEXT:    [[CMP166:%.*]] = icmp slt i64 [[TMP170]], [[TMP171]]
60347 // SIMD-ONLY0-NEXT:    br i1 [[CMP166]], label [[COND_TRUE167:%.*]], label [[COND_FALSE168:%.*]]
60348 // SIMD-ONLY0:       cond.true167:
60349 // SIMD-ONLY0-NEXT:    [[TMP172:%.*]] = load i64, ptr [[LLE]], align 8
60350 // SIMD-ONLY0-NEXT:    br label [[COND_END169:%.*]]
60351 // SIMD-ONLY0:       cond.false168:
60352 // SIMD-ONLY0-NEXT:    [[TMP173:%.*]] = load i64, ptr [[LLX]], align 8
60353 // SIMD-ONLY0-NEXT:    br label [[COND_END169]]
60354 // SIMD-ONLY0:       cond.end169:
60355 // SIMD-ONLY0-NEXT:    [[COND170:%.*]] = phi i64 [ [[TMP172]], [[COND_TRUE167]] ], [ [[TMP173]], [[COND_FALSE168]] ]
60356 // SIMD-ONLY0-NEXT:    store i64 [[COND170]], ptr [[LLX]], align 8
60357 // SIMD-ONLY0-NEXT:    [[TMP174:%.*]] = load i64, ptr [[LLX]], align 8
60358 // SIMD-ONLY0-NEXT:    store i64 [[TMP174]], ptr [[LLV]], align 8
60359 // SIMD-ONLY0-NEXT:    [[TMP175:%.*]] = load i64, ptr [[LLX]], align 8
60360 // SIMD-ONLY0-NEXT:    [[TMP176:%.*]] = load i64, ptr [[LLE]], align 8
60361 // SIMD-ONLY0-NEXT:    [[CMP171:%.*]] = icmp eq i64 [[TMP175]], [[TMP176]]
60362 // SIMD-ONLY0-NEXT:    br i1 [[CMP171]], label [[COND_TRUE172:%.*]], label [[COND_FALSE173:%.*]]
60363 // SIMD-ONLY0:       cond.true172:
60364 // SIMD-ONLY0-NEXT:    [[TMP177:%.*]] = load i64, ptr [[LLD]], align 8
60365 // SIMD-ONLY0-NEXT:    br label [[COND_END174:%.*]]
60366 // SIMD-ONLY0:       cond.false173:
60367 // SIMD-ONLY0-NEXT:    [[TMP178:%.*]] = load i64, ptr [[LLX]], align 8
60368 // SIMD-ONLY0-NEXT:    br label [[COND_END174]]
60369 // SIMD-ONLY0:       cond.end174:
60370 // SIMD-ONLY0-NEXT:    [[COND175:%.*]] = phi i64 [ [[TMP177]], [[COND_TRUE172]] ], [ [[TMP178]], [[COND_FALSE173]] ]
60371 // SIMD-ONLY0-NEXT:    store i64 [[COND175]], ptr [[LLX]], align 8
60372 // SIMD-ONLY0-NEXT:    [[TMP179:%.*]] = load i64, ptr [[LLX]], align 8
60373 // SIMD-ONLY0-NEXT:    store i64 [[TMP179]], ptr [[LLV]], align 8
60374 // SIMD-ONLY0-NEXT:    [[TMP180:%.*]] = load i64, ptr [[LLV]], align 8
60375 // SIMD-ONLY0-NEXT:    ret i64 [[TMP180]]
60376 //
60377 //
60378 // SIMD-ONLY0-LABEL: @ullxevd(
60379 // SIMD-ONLY0-NEXT:  entry:
60380 // SIMD-ONLY0-NEXT:    [[ULLX:%.*]] = alloca i64, align 8
60381 // SIMD-ONLY0-NEXT:    [[ULLV:%.*]] = alloca i64, align 8
60382 // SIMD-ONLY0-NEXT:    [[ULLE:%.*]] = alloca i64, align 8
60383 // SIMD-ONLY0-NEXT:    [[ULLD:%.*]] = alloca i64, align 8
60384 // SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = load i64, ptr [[ULLX]], align 8
60385 // SIMD-ONLY0-NEXT:    store i64 [[TMP0]], ptr [[ULLV]], align 8
60386 // SIMD-ONLY0-NEXT:    [[TMP1:%.*]] = load i64, ptr [[ULLX]], align 8
60387 // SIMD-ONLY0-NEXT:    [[TMP2:%.*]] = load i64, ptr [[ULLE]], align 8
60388 // SIMD-ONLY0-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP1]], [[TMP2]]
60389 // SIMD-ONLY0-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
60390 // SIMD-ONLY0:       cond.true:
60391 // SIMD-ONLY0-NEXT:    [[TMP3:%.*]] = load i64, ptr [[ULLE]], align 8
60392 // SIMD-ONLY0-NEXT:    br label [[COND_END:%.*]]
60393 // SIMD-ONLY0:       cond.false:
60394 // SIMD-ONLY0-NEXT:    [[TMP4:%.*]] = load i64, ptr [[ULLX]], align 8
60395 // SIMD-ONLY0-NEXT:    br label [[COND_END]]
60396 // SIMD-ONLY0:       cond.end:
60397 // SIMD-ONLY0-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP3]], [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
60398 // SIMD-ONLY0-NEXT:    store i64 [[COND]], ptr [[ULLX]], align 8
60399 // SIMD-ONLY0-NEXT:    [[TMP5:%.*]] = load i64, ptr [[ULLX]], align 8
60400 // SIMD-ONLY0-NEXT:    store i64 [[TMP5]], ptr [[ULLV]], align 8
60401 // SIMD-ONLY0-NEXT:    [[TMP6:%.*]] = load i64, ptr [[ULLX]], align 8
60402 // SIMD-ONLY0-NEXT:    [[TMP7:%.*]] = load i64, ptr [[ULLE]], align 8
60403 // SIMD-ONLY0-NEXT:    [[CMP1:%.*]] = icmp ult i64 [[TMP6]], [[TMP7]]
60404 // SIMD-ONLY0-NEXT:    br i1 [[CMP1]], label [[COND_TRUE2:%.*]], label [[COND_FALSE3:%.*]]
60405 // SIMD-ONLY0:       cond.true2:
60406 // SIMD-ONLY0-NEXT:    [[TMP8:%.*]] = load i64, ptr [[ULLE]], align 8
60407 // SIMD-ONLY0-NEXT:    br label [[COND_END4:%.*]]
60408 // SIMD-ONLY0:       cond.false3:
60409 // SIMD-ONLY0-NEXT:    [[TMP9:%.*]] = load i64, ptr [[ULLX]], align 8
60410 // SIMD-ONLY0-NEXT:    br label [[COND_END4]]
60411 // SIMD-ONLY0:       cond.end4:
60412 // SIMD-ONLY0-NEXT:    [[COND5:%.*]] = phi i64 [ [[TMP8]], [[COND_TRUE2]] ], [ [[TMP9]], [[COND_FALSE3]] ]
60413 // SIMD-ONLY0-NEXT:    store i64 [[COND5]], ptr [[ULLX]], align 8
60414 // SIMD-ONLY0-NEXT:    [[TMP10:%.*]] = load i64, ptr [[ULLX]], align 8
60415 // SIMD-ONLY0-NEXT:    store i64 [[TMP10]], ptr [[ULLV]], align 8
60416 // SIMD-ONLY0-NEXT:    [[TMP11:%.*]] = load i64, ptr [[ULLX]], align 8
60417 // SIMD-ONLY0-NEXT:    [[TMP12:%.*]] = load i64, ptr [[ULLE]], align 8
60418 // SIMD-ONLY0-NEXT:    [[CMP6:%.*]] = icmp eq i64 [[TMP11]], [[TMP12]]
60419 // SIMD-ONLY0-NEXT:    br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
60420 // SIMD-ONLY0:       cond.true7:
60421 // SIMD-ONLY0-NEXT:    [[TMP13:%.*]] = load i64, ptr [[ULLD]], align 8
60422 // SIMD-ONLY0-NEXT:    br label [[COND_END9:%.*]]
60423 // SIMD-ONLY0:       cond.false8:
60424 // SIMD-ONLY0-NEXT:    [[TMP14:%.*]] = load i64, ptr [[ULLX]], align 8
60425 // SIMD-ONLY0-NEXT:    br label [[COND_END9]]
60426 // SIMD-ONLY0:       cond.end9:
60427 // SIMD-ONLY0-NEXT:    [[COND10:%.*]] = phi i64 [ [[TMP13]], [[COND_TRUE7]] ], [ [[TMP14]], [[COND_FALSE8]] ]
60428 // SIMD-ONLY0-NEXT:    store i64 [[COND10]], ptr [[ULLX]], align 8
60429 // SIMD-ONLY0-NEXT:    [[TMP15:%.*]] = load i64, ptr [[ULLX]], align 8
60430 // SIMD-ONLY0-NEXT:    [[TMP16:%.*]] = load i64, ptr [[ULLE]], align 8
60431 // SIMD-ONLY0-NEXT:    [[CMP11:%.*]] = icmp ugt i64 [[TMP15]], [[TMP16]]
60432 // SIMD-ONLY0-NEXT:    br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
60433 // SIMD-ONLY0:       cond.true12:
60434 // SIMD-ONLY0-NEXT:    [[TMP17:%.*]] = load i64, ptr [[ULLE]], align 8
60435 // SIMD-ONLY0-NEXT:    br label [[COND_END14:%.*]]
60436 // SIMD-ONLY0:       cond.false13:
60437 // SIMD-ONLY0-NEXT:    [[TMP18:%.*]] = load i64, ptr [[ULLX]], align 8
60438 // SIMD-ONLY0-NEXT:    br label [[COND_END14]]
60439 // SIMD-ONLY0:       cond.end14:
60440 // SIMD-ONLY0-NEXT:    [[COND15:%.*]] = phi i64 [ [[TMP17]], [[COND_TRUE12]] ], [ [[TMP18]], [[COND_FALSE13]] ]
60441 // SIMD-ONLY0-NEXT:    store i64 [[COND15]], ptr [[ULLX]], align 8
60442 // SIMD-ONLY0-NEXT:    [[TMP19:%.*]] = load i64, ptr [[ULLX]], align 8
60443 // SIMD-ONLY0-NEXT:    store i64 [[TMP19]], ptr [[ULLV]], align 8
60444 // SIMD-ONLY0-NEXT:    [[TMP20:%.*]] = load i64, ptr [[ULLX]], align 8
60445 // SIMD-ONLY0-NEXT:    [[TMP21:%.*]] = load i64, ptr [[ULLE]], align 8
60446 // SIMD-ONLY0-NEXT:    [[CMP16:%.*]] = icmp ult i64 [[TMP20]], [[TMP21]]
60447 // SIMD-ONLY0-NEXT:    br i1 [[CMP16]], label [[COND_TRUE17:%.*]], label [[COND_FALSE18:%.*]]
60448 // SIMD-ONLY0:       cond.true17:
60449 // SIMD-ONLY0-NEXT:    [[TMP22:%.*]] = load i64, ptr [[ULLE]], align 8
60450 // SIMD-ONLY0-NEXT:    br label [[COND_END19:%.*]]
60451 // SIMD-ONLY0:       cond.false18:
60452 // SIMD-ONLY0-NEXT:    [[TMP23:%.*]] = load i64, ptr [[ULLX]], align 8
60453 // SIMD-ONLY0-NEXT:    br label [[COND_END19]]
60454 // SIMD-ONLY0:       cond.end19:
60455 // SIMD-ONLY0-NEXT:    [[COND20:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE17]] ], [ [[TMP23]], [[COND_FALSE18]] ]
60456 // SIMD-ONLY0-NEXT:    store i64 [[COND20]], ptr [[ULLX]], align 8
60457 // SIMD-ONLY0-NEXT:    [[TMP24:%.*]] = load i64, ptr [[ULLX]], align 8
60458 // SIMD-ONLY0-NEXT:    store i64 [[TMP24]], ptr [[ULLV]], align 8
60459 // SIMD-ONLY0-NEXT:    [[TMP25:%.*]] = load i64, ptr [[ULLX]], align 8
60460 // SIMD-ONLY0-NEXT:    [[TMP26:%.*]] = load i64, ptr [[ULLE]], align 8
60461 // SIMD-ONLY0-NEXT:    [[CMP21:%.*]] = icmp eq i64 [[TMP25]], [[TMP26]]
60462 // SIMD-ONLY0-NEXT:    br i1 [[CMP21]], label [[COND_TRUE22:%.*]], label [[COND_FALSE23:%.*]]
60463 // SIMD-ONLY0:       cond.true22:
60464 // SIMD-ONLY0-NEXT:    [[TMP27:%.*]] = load i64, ptr [[ULLD]], align 8
60465 // SIMD-ONLY0-NEXT:    br label [[COND_END24:%.*]]
60466 // SIMD-ONLY0:       cond.false23:
60467 // SIMD-ONLY0-NEXT:    [[TMP28:%.*]] = load i64, ptr [[ULLX]], align 8
60468 // SIMD-ONLY0-NEXT:    br label [[COND_END24]]
60469 // SIMD-ONLY0:       cond.end24:
60470 // SIMD-ONLY0-NEXT:    [[COND25:%.*]] = phi i64 [ [[TMP27]], [[COND_TRUE22]] ], [ [[TMP28]], [[COND_FALSE23]] ]
60471 // SIMD-ONLY0-NEXT:    store i64 [[COND25]], ptr [[ULLX]], align 8
60472 // SIMD-ONLY0-NEXT:    [[TMP29:%.*]] = load i64, ptr [[ULLX]], align 8
60473 // SIMD-ONLY0-NEXT:    store i64 [[TMP29]], ptr [[ULLV]], align 8
60474 // SIMD-ONLY0-NEXT:    [[TMP30:%.*]] = load i64, ptr [[ULLX]], align 8
60475 // SIMD-ONLY0-NEXT:    store i64 [[TMP30]], ptr [[ULLV]], align 8
60476 // SIMD-ONLY0-NEXT:    [[TMP31:%.*]] = load i64, ptr [[ULLX]], align 8
60477 // SIMD-ONLY0-NEXT:    [[TMP32:%.*]] = load i64, ptr [[ULLE]], align 8
60478 // SIMD-ONLY0-NEXT:    [[CMP26:%.*]] = icmp ugt i64 [[TMP31]], [[TMP32]]
60479 // SIMD-ONLY0-NEXT:    br i1 [[CMP26]], label [[COND_TRUE27:%.*]], label [[COND_FALSE28:%.*]]
60480 // SIMD-ONLY0:       cond.true27:
60481 // SIMD-ONLY0-NEXT:    [[TMP33:%.*]] = load i64, ptr [[ULLE]], align 8
60482 // SIMD-ONLY0-NEXT:    br label [[COND_END29:%.*]]
60483 // SIMD-ONLY0:       cond.false28:
60484 // SIMD-ONLY0-NEXT:    [[TMP34:%.*]] = load i64, ptr [[ULLX]], align 8
60485 // SIMD-ONLY0-NEXT:    br label [[COND_END29]]
60486 // SIMD-ONLY0:       cond.end29:
60487 // SIMD-ONLY0-NEXT:    [[COND30:%.*]] = phi i64 [ [[TMP33]], [[COND_TRUE27]] ], [ [[TMP34]], [[COND_FALSE28]] ]
60488 // SIMD-ONLY0-NEXT:    store i64 [[COND30]], ptr [[ULLX]], align 8
60489 // SIMD-ONLY0-NEXT:    [[TMP35:%.*]] = load i64, ptr [[ULLX]], align 8
60490 // SIMD-ONLY0-NEXT:    store i64 [[TMP35]], ptr [[ULLV]], align 8
60491 // SIMD-ONLY0-NEXT:    [[TMP36:%.*]] = load i64, ptr [[ULLX]], align 8
60492 // SIMD-ONLY0-NEXT:    [[TMP37:%.*]] = load i64, ptr [[ULLE]], align 8
60493 // SIMD-ONLY0-NEXT:    [[CMP31:%.*]] = icmp ult i64 [[TMP36]], [[TMP37]]
60494 // SIMD-ONLY0-NEXT:    br i1 [[CMP31]], label [[COND_TRUE32:%.*]], label [[COND_FALSE33:%.*]]
60495 // SIMD-ONLY0:       cond.true32:
60496 // SIMD-ONLY0-NEXT:    [[TMP38:%.*]] = load i64, ptr [[ULLE]], align 8
60497 // SIMD-ONLY0-NEXT:    br label [[COND_END34:%.*]]
60498 // SIMD-ONLY0:       cond.false33:
60499 // SIMD-ONLY0-NEXT:    [[TMP39:%.*]] = load i64, ptr [[ULLX]], align 8
60500 // SIMD-ONLY0-NEXT:    br label [[COND_END34]]
60501 // SIMD-ONLY0:       cond.end34:
60502 // SIMD-ONLY0-NEXT:    [[COND35:%.*]] = phi i64 [ [[TMP38]], [[COND_TRUE32]] ], [ [[TMP39]], [[COND_FALSE33]] ]
60503 // SIMD-ONLY0-NEXT:    store i64 [[COND35]], ptr [[ULLX]], align 8
60504 // SIMD-ONLY0-NEXT:    [[TMP40:%.*]] = load i64, ptr [[ULLX]], align 8
60505 // SIMD-ONLY0-NEXT:    store i64 [[TMP40]], ptr [[ULLV]], align 8
60506 // SIMD-ONLY0-NEXT:    [[TMP41:%.*]] = load i64, ptr [[ULLX]], align 8
60507 // SIMD-ONLY0-NEXT:    [[TMP42:%.*]] = load i64, ptr [[ULLE]], align 8
60508 // SIMD-ONLY0-NEXT:    [[CMP36:%.*]] = icmp eq i64 [[TMP41]], [[TMP42]]
60509 // SIMD-ONLY0-NEXT:    br i1 [[CMP36]], label [[COND_TRUE37:%.*]], label [[COND_FALSE38:%.*]]
60510 // SIMD-ONLY0:       cond.true37:
60511 // SIMD-ONLY0-NEXT:    [[TMP43:%.*]] = load i64, ptr [[ULLD]], align 8
60512 // SIMD-ONLY0-NEXT:    br label [[COND_END39:%.*]]
60513 // SIMD-ONLY0:       cond.false38:
60514 // SIMD-ONLY0-NEXT:    [[TMP44:%.*]] = load i64, ptr [[ULLX]], align 8
60515 // SIMD-ONLY0-NEXT:    br label [[COND_END39]]
60516 // SIMD-ONLY0:       cond.end39:
60517 // SIMD-ONLY0-NEXT:    [[COND40:%.*]] = phi i64 [ [[TMP43]], [[COND_TRUE37]] ], [ [[TMP44]], [[COND_FALSE38]] ]
60518 // SIMD-ONLY0-NEXT:    store i64 [[COND40]], ptr [[ULLX]], align 8
60519 // SIMD-ONLY0-NEXT:    [[TMP45:%.*]] = load i64, ptr [[ULLX]], align 8
60520 // SIMD-ONLY0-NEXT:    [[TMP46:%.*]] = load i64, ptr [[ULLE]], align 8
60521 // SIMD-ONLY0-NEXT:    [[CMP41:%.*]] = icmp ugt i64 [[TMP45]], [[TMP46]]
60522 // SIMD-ONLY0-NEXT:    br i1 [[CMP41]], label [[COND_TRUE42:%.*]], label [[COND_FALSE43:%.*]]
60523 // SIMD-ONLY0:       cond.true42:
60524 // SIMD-ONLY0-NEXT:    [[TMP47:%.*]] = load i64, ptr [[ULLE]], align 8
60525 // SIMD-ONLY0-NEXT:    br label [[COND_END44:%.*]]
60526 // SIMD-ONLY0:       cond.false43:
60527 // SIMD-ONLY0-NEXT:    [[TMP48:%.*]] = load i64, ptr [[ULLX]], align 8
60528 // SIMD-ONLY0-NEXT:    br label [[COND_END44]]
60529 // SIMD-ONLY0:       cond.end44:
60530 // SIMD-ONLY0-NEXT:    [[COND45:%.*]] = phi i64 [ [[TMP47]], [[COND_TRUE42]] ], [ [[TMP48]], [[COND_FALSE43]] ]
60531 // SIMD-ONLY0-NEXT:    store i64 [[COND45]], ptr [[ULLX]], align 8
60532 // SIMD-ONLY0-NEXT:    [[TMP49:%.*]] = load i64, ptr [[ULLX]], align 8
60533 // SIMD-ONLY0-NEXT:    store i64 [[TMP49]], ptr [[ULLV]], align 8
60534 // SIMD-ONLY0-NEXT:    [[TMP50:%.*]] = load i64, ptr [[ULLX]], align 8
60535 // SIMD-ONLY0-NEXT:    [[TMP51:%.*]] = load i64, ptr [[ULLE]], align 8
60536 // SIMD-ONLY0-NEXT:    [[CMP46:%.*]] = icmp ult i64 [[TMP50]], [[TMP51]]
60537 // SIMD-ONLY0-NEXT:    br i1 [[CMP46]], label [[COND_TRUE47:%.*]], label [[COND_FALSE48:%.*]]
60538 // SIMD-ONLY0:       cond.true47:
60539 // SIMD-ONLY0-NEXT:    [[TMP52:%.*]] = load i64, ptr [[ULLE]], align 8
60540 // SIMD-ONLY0-NEXT:    br label [[COND_END49:%.*]]
60541 // SIMD-ONLY0:       cond.false48:
60542 // SIMD-ONLY0-NEXT:    [[TMP53:%.*]] = load i64, ptr [[ULLX]], align 8
60543 // SIMD-ONLY0-NEXT:    br label [[COND_END49]]
60544 // SIMD-ONLY0:       cond.end49:
60545 // SIMD-ONLY0-NEXT:    [[COND50:%.*]] = phi i64 [ [[TMP52]], [[COND_TRUE47]] ], [ [[TMP53]], [[COND_FALSE48]] ]
60546 // SIMD-ONLY0-NEXT:    store i64 [[COND50]], ptr [[ULLX]], align 8
60547 // SIMD-ONLY0-NEXT:    [[TMP54:%.*]] = load i64, ptr [[ULLX]], align 8
60548 // SIMD-ONLY0-NEXT:    store i64 [[TMP54]], ptr [[ULLV]], align 8
60549 // SIMD-ONLY0-NEXT:    [[TMP55:%.*]] = load i64, ptr [[ULLX]], align 8
60550 // SIMD-ONLY0-NEXT:    [[TMP56:%.*]] = load i64, ptr [[ULLE]], align 8
60551 // SIMD-ONLY0-NEXT:    [[CMP51:%.*]] = icmp eq i64 [[TMP55]], [[TMP56]]
60552 // SIMD-ONLY0-NEXT:    br i1 [[CMP51]], label [[COND_TRUE52:%.*]], label [[COND_FALSE53:%.*]]
60553 // SIMD-ONLY0:       cond.true52:
60554 // SIMD-ONLY0-NEXT:    [[TMP57:%.*]] = load i64, ptr [[ULLD]], align 8
60555 // SIMD-ONLY0-NEXT:    br label [[COND_END54:%.*]]
60556 // SIMD-ONLY0:       cond.false53:
60557 // SIMD-ONLY0-NEXT:    [[TMP58:%.*]] = load i64, ptr [[ULLX]], align 8
60558 // SIMD-ONLY0-NEXT:    br label [[COND_END54]]
60559 // SIMD-ONLY0:       cond.end54:
60560 // SIMD-ONLY0-NEXT:    [[COND55:%.*]] = phi i64 [ [[TMP57]], [[COND_TRUE52]] ], [ [[TMP58]], [[COND_FALSE53]] ]
60561 // SIMD-ONLY0-NEXT:    store i64 [[COND55]], ptr [[ULLX]], align 8
60562 // SIMD-ONLY0-NEXT:    [[TMP59:%.*]] = load i64, ptr [[ULLX]], align 8
60563 // SIMD-ONLY0-NEXT:    store i64 [[TMP59]], ptr [[ULLV]], align 8
60564 // SIMD-ONLY0-NEXT:    [[TMP60:%.*]] = load i64, ptr [[ULLX]], align 8
60565 // SIMD-ONLY0-NEXT:    store i64 [[TMP60]], ptr [[ULLV]], align 8
60566 // SIMD-ONLY0-NEXT:    [[TMP61:%.*]] = load i64, ptr [[ULLX]], align 8
60567 // SIMD-ONLY0-NEXT:    [[TMP62:%.*]] = load i64, ptr [[ULLE]], align 8
60568 // SIMD-ONLY0-NEXT:    [[CMP56:%.*]] = icmp ugt i64 [[TMP61]], [[TMP62]]
60569 // SIMD-ONLY0-NEXT:    br i1 [[CMP56]], label [[COND_TRUE57:%.*]], label [[COND_FALSE58:%.*]]
60570 // SIMD-ONLY0:       cond.true57:
60571 // SIMD-ONLY0-NEXT:    [[TMP63:%.*]] = load i64, ptr [[ULLE]], align 8
60572 // SIMD-ONLY0-NEXT:    br label [[COND_END59:%.*]]
60573 // SIMD-ONLY0:       cond.false58:
60574 // SIMD-ONLY0-NEXT:    [[TMP64:%.*]] = load i64, ptr [[ULLX]], align 8
60575 // SIMD-ONLY0-NEXT:    br label [[COND_END59]]
60576 // SIMD-ONLY0:       cond.end59:
60577 // SIMD-ONLY0-NEXT:    [[COND60:%.*]] = phi i64 [ [[TMP63]], [[COND_TRUE57]] ], [ [[TMP64]], [[COND_FALSE58]] ]
60578 // SIMD-ONLY0-NEXT:    store i64 [[COND60]], ptr [[ULLX]], align 8
60579 // SIMD-ONLY0-NEXT:    [[TMP65:%.*]] = load i64, ptr [[ULLX]], align 8
60580 // SIMD-ONLY0-NEXT:    store i64 [[TMP65]], ptr [[ULLV]], align 8
60581 // SIMD-ONLY0-NEXT:    [[TMP66:%.*]] = load i64, ptr [[ULLX]], align 8
60582 // SIMD-ONLY0-NEXT:    [[TMP67:%.*]] = load i64, ptr [[ULLE]], align 8
60583 // SIMD-ONLY0-NEXT:    [[CMP61:%.*]] = icmp ult i64 [[TMP66]], [[TMP67]]
60584 // SIMD-ONLY0-NEXT:    br i1 [[CMP61]], label [[COND_TRUE62:%.*]], label [[COND_FALSE63:%.*]]
60585 // SIMD-ONLY0:       cond.true62:
60586 // SIMD-ONLY0-NEXT:    [[TMP68:%.*]] = load i64, ptr [[ULLE]], align 8
60587 // SIMD-ONLY0-NEXT:    br label [[COND_END64:%.*]]
60588 // SIMD-ONLY0:       cond.false63:
60589 // SIMD-ONLY0-NEXT:    [[TMP69:%.*]] = load i64, ptr [[ULLX]], align 8
60590 // SIMD-ONLY0-NEXT:    br label [[COND_END64]]
60591 // SIMD-ONLY0:       cond.end64:
60592 // SIMD-ONLY0-NEXT:    [[COND65:%.*]] = phi i64 [ [[TMP68]], [[COND_TRUE62]] ], [ [[TMP69]], [[COND_FALSE63]] ]
60593 // SIMD-ONLY0-NEXT:    store i64 [[COND65]], ptr [[ULLX]], align 8
60594 // SIMD-ONLY0-NEXT:    [[TMP70:%.*]] = load i64, ptr [[ULLX]], align 8
60595 // SIMD-ONLY0-NEXT:    store i64 [[TMP70]], ptr [[ULLV]], align 8
60596 // SIMD-ONLY0-NEXT:    [[TMP71:%.*]] = load i64, ptr [[ULLX]], align 8
60597 // SIMD-ONLY0-NEXT:    [[TMP72:%.*]] = load i64, ptr [[ULLE]], align 8
60598 // SIMD-ONLY0-NEXT:    [[CMP66:%.*]] = icmp eq i64 [[TMP71]], [[TMP72]]
60599 // SIMD-ONLY0-NEXT:    br i1 [[CMP66]], label [[COND_TRUE67:%.*]], label [[COND_FALSE68:%.*]]
60600 // SIMD-ONLY0:       cond.true67:
60601 // SIMD-ONLY0-NEXT:    [[TMP73:%.*]] = load i64, ptr [[ULLD]], align 8
60602 // SIMD-ONLY0-NEXT:    br label [[COND_END69:%.*]]
60603 // SIMD-ONLY0:       cond.false68:
60604 // SIMD-ONLY0-NEXT:    [[TMP74:%.*]] = load i64, ptr [[ULLX]], align 8
60605 // SIMD-ONLY0-NEXT:    br label [[COND_END69]]
60606 // SIMD-ONLY0:       cond.end69:
60607 // SIMD-ONLY0-NEXT:    [[COND70:%.*]] = phi i64 [ [[TMP73]], [[COND_TRUE67]] ], [ [[TMP74]], [[COND_FALSE68]] ]
60608 // SIMD-ONLY0-NEXT:    store i64 [[COND70]], ptr [[ULLX]], align 8
60609 // SIMD-ONLY0-NEXT:    [[TMP75:%.*]] = load i64, ptr [[ULLX]], align 8
60610 // SIMD-ONLY0-NEXT:    [[TMP76:%.*]] = load i64, ptr [[ULLE]], align 8
60611 // SIMD-ONLY0-NEXT:    [[CMP71:%.*]] = icmp ugt i64 [[TMP75]], [[TMP76]]
60612 // SIMD-ONLY0-NEXT:    br i1 [[CMP71]], label [[COND_TRUE72:%.*]], label [[COND_FALSE73:%.*]]
60613 // SIMD-ONLY0:       cond.true72:
60614 // SIMD-ONLY0-NEXT:    [[TMP77:%.*]] = load i64, ptr [[ULLE]], align 8
60615 // SIMD-ONLY0-NEXT:    br label [[COND_END74:%.*]]
60616 // SIMD-ONLY0:       cond.false73:
60617 // SIMD-ONLY0-NEXT:    [[TMP78:%.*]] = load i64, ptr [[ULLX]], align 8
60618 // SIMD-ONLY0-NEXT:    br label [[COND_END74]]
60619 // SIMD-ONLY0:       cond.end74:
60620 // SIMD-ONLY0-NEXT:    [[COND75:%.*]] = phi i64 [ [[TMP77]], [[COND_TRUE72]] ], [ [[TMP78]], [[COND_FALSE73]] ]
60621 // SIMD-ONLY0-NEXT:    store i64 [[COND75]], ptr [[ULLX]], align 8
60622 // SIMD-ONLY0-NEXT:    [[TMP79:%.*]] = load i64, ptr [[ULLX]], align 8
60623 // SIMD-ONLY0-NEXT:    store i64 [[TMP79]], ptr [[ULLV]], align 8
60624 // SIMD-ONLY0-NEXT:    [[TMP80:%.*]] = load i64, ptr [[ULLX]], align 8
60625 // SIMD-ONLY0-NEXT:    [[TMP81:%.*]] = load i64, ptr [[ULLE]], align 8
60626 // SIMD-ONLY0-NEXT:    [[CMP76:%.*]] = icmp ult i64 [[TMP80]], [[TMP81]]
60627 // SIMD-ONLY0-NEXT:    br i1 [[CMP76]], label [[COND_TRUE77:%.*]], label [[COND_FALSE78:%.*]]
60628 // SIMD-ONLY0:       cond.true77:
60629 // SIMD-ONLY0-NEXT:    [[TMP82:%.*]] = load i64, ptr [[ULLE]], align 8
60630 // SIMD-ONLY0-NEXT:    br label [[COND_END79:%.*]]
60631 // SIMD-ONLY0:       cond.false78:
60632 // SIMD-ONLY0-NEXT:    [[TMP83:%.*]] = load i64, ptr [[ULLX]], align 8
60633 // SIMD-ONLY0-NEXT:    br label [[COND_END79]]
60634 // SIMD-ONLY0:       cond.end79:
60635 // SIMD-ONLY0-NEXT:    [[COND80:%.*]] = phi i64 [ [[TMP82]], [[COND_TRUE77]] ], [ [[TMP83]], [[COND_FALSE78]] ]
60636 // SIMD-ONLY0-NEXT:    store i64 [[COND80]], ptr [[ULLX]], align 8
60637 // SIMD-ONLY0-NEXT:    [[TMP84:%.*]] = load i64, ptr [[ULLX]], align 8
60638 // SIMD-ONLY0-NEXT:    store i64 [[TMP84]], ptr [[ULLV]], align 8
60639 // SIMD-ONLY0-NEXT:    [[TMP85:%.*]] = load i64, ptr [[ULLX]], align 8
60640 // SIMD-ONLY0-NEXT:    [[TMP86:%.*]] = load i64, ptr [[ULLE]], align 8
60641 // SIMD-ONLY0-NEXT:    [[CMP81:%.*]] = icmp eq i64 [[TMP85]], [[TMP86]]
60642 // SIMD-ONLY0-NEXT:    br i1 [[CMP81]], label [[COND_TRUE82:%.*]], label [[COND_FALSE83:%.*]]
60643 // SIMD-ONLY0:       cond.true82:
60644 // SIMD-ONLY0-NEXT:    [[TMP87:%.*]] = load i64, ptr [[ULLD]], align 8
60645 // SIMD-ONLY0-NEXT:    br label [[COND_END84:%.*]]
60646 // SIMD-ONLY0:       cond.false83:
60647 // SIMD-ONLY0-NEXT:    [[TMP88:%.*]] = load i64, ptr [[ULLX]], align 8
60648 // SIMD-ONLY0-NEXT:    br label [[COND_END84]]
60649 // SIMD-ONLY0:       cond.end84:
60650 // SIMD-ONLY0-NEXT:    [[COND85:%.*]] = phi i64 [ [[TMP87]], [[COND_TRUE82]] ], [ [[TMP88]], [[COND_FALSE83]] ]
60651 // SIMD-ONLY0-NEXT:    store i64 [[COND85]], ptr [[ULLX]], align 8
60652 // SIMD-ONLY0-NEXT:    [[TMP89:%.*]] = load i64, ptr [[ULLX]], align 8
60653 // SIMD-ONLY0-NEXT:    store i64 [[TMP89]], ptr [[ULLV]], align 8
60654 // SIMD-ONLY0-NEXT:    [[TMP90:%.*]] = load i64, ptr [[ULLX]], align 8
60655 // SIMD-ONLY0-NEXT:    store i64 [[TMP90]], ptr [[ULLV]], align 8
60656 // SIMD-ONLY0-NEXT:    [[TMP91:%.*]] = load i64, ptr [[ULLX]], align 8
60657 // SIMD-ONLY0-NEXT:    [[TMP92:%.*]] = load i64, ptr [[ULLE]], align 8
60658 // SIMD-ONLY0-NEXT:    [[CMP86:%.*]] = icmp ugt i64 [[TMP91]], [[TMP92]]
60659 // SIMD-ONLY0-NEXT:    br i1 [[CMP86]], label [[COND_TRUE87:%.*]], label [[COND_FALSE88:%.*]]
60660 // SIMD-ONLY0:       cond.true87:
60661 // SIMD-ONLY0-NEXT:    [[TMP93:%.*]] = load i64, ptr [[ULLE]], align 8
60662 // SIMD-ONLY0-NEXT:    br label [[COND_END89:%.*]]
60663 // SIMD-ONLY0:       cond.false88:
60664 // SIMD-ONLY0-NEXT:    [[TMP94:%.*]] = load i64, ptr [[ULLX]], align 8
60665 // SIMD-ONLY0-NEXT:    br label [[COND_END89]]
60666 // SIMD-ONLY0:       cond.end89:
60667 // SIMD-ONLY0-NEXT:    [[COND90:%.*]] = phi i64 [ [[TMP93]], [[COND_TRUE87]] ], [ [[TMP94]], [[COND_FALSE88]] ]
60668 // SIMD-ONLY0-NEXT:    store i64 [[COND90]], ptr [[ULLX]], align 8
60669 // SIMD-ONLY0-NEXT:    [[TMP95:%.*]] = load i64, ptr [[ULLX]], align 8
60670 // SIMD-ONLY0-NEXT:    store i64 [[TMP95]], ptr [[ULLV]], align 8
60671 // SIMD-ONLY0-NEXT:    [[TMP96:%.*]] = load i64, ptr [[ULLX]], align 8
60672 // SIMD-ONLY0-NEXT:    [[TMP97:%.*]] = load i64, ptr [[ULLE]], align 8
60673 // SIMD-ONLY0-NEXT:    [[CMP91:%.*]] = icmp ult i64 [[TMP96]], [[TMP97]]
60674 // SIMD-ONLY0-NEXT:    br i1 [[CMP91]], label [[COND_TRUE92:%.*]], label [[COND_FALSE93:%.*]]
60675 // SIMD-ONLY0:       cond.true92:
60676 // SIMD-ONLY0-NEXT:    [[TMP98:%.*]] = load i64, ptr [[ULLE]], align 8
60677 // SIMD-ONLY0-NEXT:    br label [[COND_END94:%.*]]
60678 // SIMD-ONLY0:       cond.false93:
60679 // SIMD-ONLY0-NEXT:    [[TMP99:%.*]] = load i64, ptr [[ULLX]], align 8
60680 // SIMD-ONLY0-NEXT:    br label [[COND_END94]]
60681 // SIMD-ONLY0:       cond.end94:
60682 // SIMD-ONLY0-NEXT:    [[COND95:%.*]] = phi i64 [ [[TMP98]], [[COND_TRUE92]] ], [ [[TMP99]], [[COND_FALSE93]] ]
60683 // SIMD-ONLY0-NEXT:    store i64 [[COND95]], ptr [[ULLX]], align 8
60684 // SIMD-ONLY0-NEXT:    [[TMP100:%.*]] = load i64, ptr [[ULLX]], align 8
60685 // SIMD-ONLY0-NEXT:    store i64 [[TMP100]], ptr [[ULLV]], align 8
60686 // SIMD-ONLY0-NEXT:    [[TMP101:%.*]] = load i64, ptr [[ULLX]], align 8
60687 // SIMD-ONLY0-NEXT:    [[TMP102:%.*]] = load i64, ptr [[ULLE]], align 8
60688 // SIMD-ONLY0-NEXT:    [[CMP96:%.*]] = icmp eq i64 [[TMP101]], [[TMP102]]
60689 // SIMD-ONLY0-NEXT:    br i1 [[CMP96]], label [[COND_TRUE97:%.*]], label [[COND_FALSE98:%.*]]
60690 // SIMD-ONLY0:       cond.true97:
60691 // SIMD-ONLY0-NEXT:    [[TMP103:%.*]] = load i64, ptr [[ULLD]], align 8
60692 // SIMD-ONLY0-NEXT:    br label [[COND_END99:%.*]]
60693 // SIMD-ONLY0:       cond.false98:
60694 // SIMD-ONLY0-NEXT:    [[TMP104:%.*]] = load i64, ptr [[ULLX]], align 8
60695 // SIMD-ONLY0-NEXT:    br label [[COND_END99]]
60696 // SIMD-ONLY0:       cond.end99:
60697 // SIMD-ONLY0-NEXT:    [[COND100:%.*]] = phi i64 [ [[TMP103]], [[COND_TRUE97]] ], [ [[TMP104]], [[COND_FALSE98]] ]
60698 // SIMD-ONLY0-NEXT:    store i64 [[COND100]], ptr [[ULLX]], align 8
60699 // SIMD-ONLY0-NEXT:    [[TMP105:%.*]] = load i64, ptr [[ULLX]], align 8
60700 // SIMD-ONLY0-NEXT:    [[TMP106:%.*]] = load i64, ptr [[ULLE]], align 8
60701 // SIMD-ONLY0-NEXT:    [[CMP101:%.*]] = icmp ugt i64 [[TMP105]], [[TMP106]]
60702 // SIMD-ONLY0-NEXT:    br i1 [[CMP101]], label [[COND_TRUE102:%.*]], label [[COND_FALSE103:%.*]]
60703 // SIMD-ONLY0:       cond.true102:
60704 // SIMD-ONLY0-NEXT:    [[TMP107:%.*]] = load i64, ptr [[ULLE]], align 8
60705 // SIMD-ONLY0-NEXT:    br label [[COND_END104:%.*]]
60706 // SIMD-ONLY0:       cond.false103:
60707 // SIMD-ONLY0-NEXT:    [[TMP108:%.*]] = load i64, ptr [[ULLX]], align 8
60708 // SIMD-ONLY0-NEXT:    br label [[COND_END104]]
60709 // SIMD-ONLY0:       cond.end104:
60710 // SIMD-ONLY0-NEXT:    [[COND105:%.*]] = phi i64 [ [[TMP107]], [[COND_TRUE102]] ], [ [[TMP108]], [[COND_FALSE103]] ]
60711 // SIMD-ONLY0-NEXT:    store i64 [[COND105]], ptr [[ULLX]], align 8
60712 // SIMD-ONLY0-NEXT:    [[TMP109:%.*]] = load i64, ptr [[ULLX]], align 8
60713 // SIMD-ONLY0-NEXT:    store i64 [[TMP109]], ptr [[ULLV]], align 8
60714 // SIMD-ONLY0-NEXT:    [[TMP110:%.*]] = load i64, ptr [[ULLX]], align 8
60715 // SIMD-ONLY0-NEXT:    [[TMP111:%.*]] = load i64, ptr [[ULLE]], align 8
60716 // SIMD-ONLY0-NEXT:    [[CMP106:%.*]] = icmp ult i64 [[TMP110]], [[TMP111]]
60717 // SIMD-ONLY0-NEXT:    br i1 [[CMP106]], label [[COND_TRUE107:%.*]], label [[COND_FALSE108:%.*]]
60718 // SIMD-ONLY0:       cond.true107:
60719 // SIMD-ONLY0-NEXT:    [[TMP112:%.*]] = load i64, ptr [[ULLE]], align 8
60720 // SIMD-ONLY0-NEXT:    br label [[COND_END109:%.*]]
60721 // SIMD-ONLY0:       cond.false108:
60722 // SIMD-ONLY0-NEXT:    [[TMP113:%.*]] = load i64, ptr [[ULLX]], align 8
60723 // SIMD-ONLY0-NEXT:    br label [[COND_END109]]
60724 // SIMD-ONLY0:       cond.end109:
60725 // SIMD-ONLY0-NEXT:    [[COND110:%.*]] = phi i64 [ [[TMP112]], [[COND_TRUE107]] ], [ [[TMP113]], [[COND_FALSE108]] ]
60726 // SIMD-ONLY0-NEXT:    store i64 [[COND110]], ptr [[ULLX]], align 8
60727 // SIMD-ONLY0-NEXT:    [[TMP114:%.*]] = load i64, ptr [[ULLX]], align 8
60728 // SIMD-ONLY0-NEXT:    store i64 [[TMP114]], ptr [[ULLV]], align 8
60729 // SIMD-ONLY0-NEXT:    [[TMP115:%.*]] = load i64, ptr [[ULLX]], align 8
60730 // SIMD-ONLY0-NEXT:    [[TMP116:%.*]] = load i64, ptr [[ULLE]], align 8
60731 // SIMD-ONLY0-NEXT:    [[CMP111:%.*]] = icmp eq i64 [[TMP115]], [[TMP116]]
60732 // SIMD-ONLY0-NEXT:    br i1 [[CMP111]], label [[COND_TRUE112:%.*]], label [[COND_FALSE113:%.*]]
60733 // SIMD-ONLY0:       cond.true112:
60734 // SIMD-ONLY0-NEXT:    [[TMP117:%.*]] = load i64, ptr [[ULLD]], align 8
60735 // SIMD-ONLY0-NEXT:    br label [[COND_END114:%.*]]
60736 // SIMD-ONLY0:       cond.false113:
60737 // SIMD-ONLY0-NEXT:    [[TMP118:%.*]] = load i64, ptr [[ULLX]], align 8
60738 // SIMD-ONLY0-NEXT:    br label [[COND_END114]]
60739 // SIMD-ONLY0:       cond.end114:
60740 // SIMD-ONLY0-NEXT:    [[COND115:%.*]] = phi i64 [ [[TMP117]], [[COND_TRUE112]] ], [ [[TMP118]], [[COND_FALSE113]] ]
60741 // SIMD-ONLY0-NEXT:    store i64 [[COND115]], ptr [[ULLX]], align 8
60742 // SIMD-ONLY0-NEXT:    [[TMP119:%.*]] = load i64, ptr [[ULLX]], align 8
60743 // SIMD-ONLY0-NEXT:    store i64 [[TMP119]], ptr [[ULLV]], align 8
60744 // SIMD-ONLY0-NEXT:    [[TMP120:%.*]] = load i64, ptr [[ULLX]], align 8
60745 // SIMD-ONLY0-NEXT:    store i64 [[TMP120]], ptr [[ULLV]], align 8
60746 // SIMD-ONLY0-NEXT:    [[TMP121:%.*]] = load i64, ptr [[ULLX]], align 8
60747 // SIMD-ONLY0-NEXT:    [[TMP122:%.*]] = load i64, ptr [[ULLE]], align 8
60748 // SIMD-ONLY0-NEXT:    [[CMP116:%.*]] = icmp ugt i64 [[TMP121]], [[TMP122]]
60749 // SIMD-ONLY0-NEXT:    br i1 [[CMP116]], label [[COND_TRUE117:%.*]], label [[COND_FALSE118:%.*]]
60750 // SIMD-ONLY0:       cond.true117:
60751 // SIMD-ONLY0-NEXT:    [[TMP123:%.*]] = load i64, ptr [[ULLE]], align 8
60752 // SIMD-ONLY0-NEXT:    br label [[COND_END119:%.*]]
60753 // SIMD-ONLY0:       cond.false118:
60754 // SIMD-ONLY0-NEXT:    [[TMP124:%.*]] = load i64, ptr [[ULLX]], align 8
60755 // SIMD-ONLY0-NEXT:    br label [[COND_END119]]
60756 // SIMD-ONLY0:       cond.end119:
60757 // SIMD-ONLY0-NEXT:    [[COND120:%.*]] = phi i64 [ [[TMP123]], [[COND_TRUE117]] ], [ [[TMP124]], [[COND_FALSE118]] ]
60758 // SIMD-ONLY0-NEXT:    store i64 [[COND120]], ptr [[ULLX]], align 8
60759 // SIMD-ONLY0-NEXT:    [[TMP125:%.*]] = load i64, ptr [[ULLX]], align 8
60760 // SIMD-ONLY0-NEXT:    store i64 [[TMP125]], ptr [[ULLV]], align 8
60761 // SIMD-ONLY0-NEXT:    [[TMP126:%.*]] = load i64, ptr [[ULLX]], align 8
60762 // SIMD-ONLY0-NEXT:    [[TMP127:%.*]] = load i64, ptr [[ULLE]], align 8
60763 // SIMD-ONLY0-NEXT:    [[CMP121:%.*]] = icmp ult i64 [[TMP126]], [[TMP127]]
60764 // SIMD-ONLY0-NEXT:    br i1 [[CMP121]], label [[COND_TRUE122:%.*]], label [[COND_FALSE123:%.*]]
60765 // SIMD-ONLY0:       cond.true122:
60766 // SIMD-ONLY0-NEXT:    [[TMP128:%.*]] = load i64, ptr [[ULLE]], align 8
60767 // SIMD-ONLY0-NEXT:    br label [[COND_END124:%.*]]
60768 // SIMD-ONLY0:       cond.false123:
60769 // SIMD-ONLY0-NEXT:    [[TMP129:%.*]] = load i64, ptr [[ULLX]], align 8
60770 // SIMD-ONLY0-NEXT:    br label [[COND_END124]]
60771 // SIMD-ONLY0:       cond.end124:
60772 // SIMD-ONLY0-NEXT:    [[COND125:%.*]] = phi i64 [ [[TMP128]], [[COND_TRUE122]] ], [ [[TMP129]], [[COND_FALSE123]] ]
60773 // SIMD-ONLY0-NEXT:    store i64 [[COND125]], ptr [[ULLX]], align 8
60774 // SIMD-ONLY0-NEXT:    [[TMP130:%.*]] = load i64, ptr [[ULLX]], align 8
60775 // SIMD-ONLY0-NEXT:    store i64 [[TMP130]], ptr [[ULLV]], align 8
60776 // SIMD-ONLY0-NEXT:    [[TMP131:%.*]] = load i64, ptr [[ULLX]], align 8
60777 // SIMD-ONLY0-NEXT:    [[TMP132:%.*]] = load i64, ptr [[ULLE]], align 8
60778 // SIMD-ONLY0-NEXT:    [[CMP126:%.*]] = icmp eq i64 [[TMP131]], [[TMP132]]
60779 // SIMD-ONLY0-NEXT:    br i1 [[CMP126]], label [[COND_TRUE127:%.*]], label [[COND_FALSE128:%.*]]
60780 // SIMD-ONLY0:       cond.true127:
60781 // SIMD-ONLY0-NEXT:    [[TMP133:%.*]] = load i64, ptr [[ULLD]], align 8
60782 // SIMD-ONLY0-NEXT:    br label [[COND_END129:%.*]]
60783 // SIMD-ONLY0:       cond.false128:
60784 // SIMD-ONLY0-NEXT:    [[TMP134:%.*]] = load i64, ptr [[ULLX]], align 8
60785 // SIMD-ONLY0-NEXT:    br label [[COND_END129]]
60786 // SIMD-ONLY0:       cond.end129:
60787 // SIMD-ONLY0-NEXT:    [[COND130:%.*]] = phi i64 [ [[TMP133]], [[COND_TRUE127]] ], [ [[TMP134]], [[COND_FALSE128]] ]
60788 // SIMD-ONLY0-NEXT:    store i64 [[COND130]], ptr [[ULLX]], align 8
60789 // SIMD-ONLY0-NEXT:    [[TMP135:%.*]] = load i64, ptr [[ULLX]], align 8
60790 // SIMD-ONLY0-NEXT:    [[TMP136:%.*]] = load i64, ptr [[ULLE]], align 8
60791 // SIMD-ONLY0-NEXT:    [[CMP131:%.*]] = icmp ugt i64 [[TMP135]], [[TMP136]]
60792 // SIMD-ONLY0-NEXT:    br i1 [[CMP131]], label [[COND_TRUE132:%.*]], label [[COND_FALSE133:%.*]]
60793 // SIMD-ONLY0:       cond.true132:
60794 // SIMD-ONLY0-NEXT:    [[TMP137:%.*]] = load i64, ptr [[ULLE]], align 8
60795 // SIMD-ONLY0-NEXT:    br label [[COND_END134:%.*]]
60796 // SIMD-ONLY0:       cond.false133:
60797 // SIMD-ONLY0-NEXT:    [[TMP138:%.*]] = load i64, ptr [[ULLX]], align 8
60798 // SIMD-ONLY0-NEXT:    br label [[COND_END134]]
60799 // SIMD-ONLY0:       cond.end134:
60800 // SIMD-ONLY0-NEXT:    [[COND135:%.*]] = phi i64 [ [[TMP137]], [[COND_TRUE132]] ], [ [[TMP138]], [[COND_FALSE133]] ]
60801 // SIMD-ONLY0-NEXT:    store i64 [[COND135]], ptr [[ULLX]], align 8
60802 // SIMD-ONLY0-NEXT:    [[TMP139:%.*]] = load i64, ptr [[ULLX]], align 8
60803 // SIMD-ONLY0-NEXT:    store i64 [[TMP139]], ptr [[ULLV]], align 8
60804 // SIMD-ONLY0-NEXT:    [[TMP140:%.*]] = load i64, ptr [[ULLX]], align 8
60805 // SIMD-ONLY0-NEXT:    [[TMP141:%.*]] = load i64, ptr [[ULLE]], align 8
60806 // SIMD-ONLY0-NEXT:    [[CMP136:%.*]] = icmp ult i64 [[TMP140]], [[TMP141]]
60807 // SIMD-ONLY0-NEXT:    br i1 [[CMP136]], label [[COND_TRUE137:%.*]], label [[COND_FALSE138:%.*]]
60808 // SIMD-ONLY0:       cond.true137:
60809 // SIMD-ONLY0-NEXT:    [[TMP142:%.*]] = load i64, ptr [[ULLE]], align 8
60810 // SIMD-ONLY0-NEXT:    br label [[COND_END139:%.*]]
60811 // SIMD-ONLY0:       cond.false138:
60812 // SIMD-ONLY0-NEXT:    [[TMP143:%.*]] = load i64, ptr [[ULLX]], align 8
60813 // SIMD-ONLY0-NEXT:    br label [[COND_END139]]
60814 // SIMD-ONLY0:       cond.end139:
60815 // SIMD-ONLY0-NEXT:    [[COND140:%.*]] = phi i64 [ [[TMP142]], [[COND_TRUE137]] ], [ [[TMP143]], [[COND_FALSE138]] ]
60816 // SIMD-ONLY0-NEXT:    store i64 [[COND140]], ptr [[ULLX]], align 8
60817 // SIMD-ONLY0-NEXT:    [[TMP144:%.*]] = load i64, ptr [[ULLX]], align 8
60818 // SIMD-ONLY0-NEXT:    store i64 [[TMP144]], ptr [[ULLV]], align 8
60819 // SIMD-ONLY0-NEXT:    [[TMP145:%.*]] = load i64, ptr [[ULLX]], align 8
60820 // SIMD-ONLY0-NEXT:    [[TMP146:%.*]] = load i64, ptr [[ULLE]], align 8
60821 // SIMD-ONLY0-NEXT:    [[CMP141:%.*]] = icmp eq i64 [[TMP145]], [[TMP146]]
60822 // SIMD-ONLY0-NEXT:    br i1 [[CMP141]], label [[COND_TRUE142:%.*]], label [[COND_FALSE143:%.*]]
60823 // SIMD-ONLY0:       cond.true142:
60824 // SIMD-ONLY0-NEXT:    [[TMP147:%.*]] = load i64, ptr [[ULLD]], align 8
60825 // SIMD-ONLY0-NEXT:    br label [[COND_END144:%.*]]
60826 // SIMD-ONLY0:       cond.false143:
60827 // SIMD-ONLY0-NEXT:    [[TMP148:%.*]] = load i64, ptr [[ULLX]], align 8
60828 // SIMD-ONLY0-NEXT:    br label [[COND_END144]]
60829 // SIMD-ONLY0:       cond.end144:
60830 // SIMD-ONLY0-NEXT:    [[COND145:%.*]] = phi i64 [ [[TMP147]], [[COND_TRUE142]] ], [ [[TMP148]], [[COND_FALSE143]] ]
60831 // SIMD-ONLY0-NEXT:    store i64 [[COND145]], ptr [[ULLX]], align 8
60832 // SIMD-ONLY0-NEXT:    [[TMP149:%.*]] = load i64, ptr [[ULLX]], align 8
60833 // SIMD-ONLY0-NEXT:    store i64 [[TMP149]], ptr [[ULLV]], align 8
60834 // SIMD-ONLY0-NEXT:    [[TMP150:%.*]] = load i64, ptr [[ULLX]], align 8
60835 // SIMD-ONLY0-NEXT:    store i64 [[TMP150]], ptr [[ULLV]], align 8
60836 // SIMD-ONLY0-NEXT:    [[TMP151:%.*]] = load i64, ptr [[ULLX]], align 8
60837 // SIMD-ONLY0-NEXT:    [[TMP152:%.*]] = load i64, ptr [[ULLE]], align 8
60838 // SIMD-ONLY0-NEXT:    [[CMP146:%.*]] = icmp ugt i64 [[TMP151]], [[TMP152]]
60839 // SIMD-ONLY0-NEXT:    br i1 [[CMP146]], label [[COND_TRUE147:%.*]], label [[COND_FALSE148:%.*]]
60840 // SIMD-ONLY0:       cond.true147:
60841 // SIMD-ONLY0-NEXT:    [[TMP153:%.*]] = load i64, ptr [[ULLE]], align 8
60842 // SIMD-ONLY0-NEXT:    br label [[COND_END149:%.*]]
60843 // SIMD-ONLY0:       cond.false148:
60844 // SIMD-ONLY0-NEXT:    [[TMP154:%.*]] = load i64, ptr [[ULLX]], align 8
60845 // SIMD-ONLY0-NEXT:    br label [[COND_END149]]
60846 // SIMD-ONLY0:       cond.end149:
60847 // SIMD-ONLY0-NEXT:    [[COND150:%.*]] = phi i64 [ [[TMP153]], [[COND_TRUE147]] ], [ [[TMP154]], [[COND_FALSE148]] ]
60848 // SIMD-ONLY0-NEXT:    store i64 [[COND150]], ptr [[ULLX]], align 8
60849 // SIMD-ONLY0-NEXT:    [[TMP155:%.*]] = load i64, ptr [[ULLX]], align 8
60850 // SIMD-ONLY0-NEXT:    store i64 [[TMP155]], ptr [[ULLV]], align 8
60851 // SIMD-ONLY0-NEXT:    [[TMP156:%.*]] = load i64, ptr [[ULLX]], align 8
60852 // SIMD-ONLY0-NEXT:    [[TMP157:%.*]] = load i64, ptr [[ULLE]], align 8
60853 // SIMD-ONLY0-NEXT:    [[CMP151:%.*]] = icmp ult i64 [[TMP156]], [[TMP157]]
60854 // SIMD-ONLY0-NEXT:    br i1 [[CMP151]], label [[COND_TRUE152:%.*]], label [[COND_FALSE153:%.*]]
60855 // SIMD-ONLY0:       cond.true152:
60856 // SIMD-ONLY0-NEXT:    [[TMP158:%.*]] = load i64, ptr [[ULLE]], align 8
60857 // SIMD-ONLY0-NEXT:    br label [[COND_END154:%.*]]
60858 // SIMD-ONLY0:       cond.false153:
60859 // SIMD-ONLY0-NEXT:    [[TMP159:%.*]] = load i64, ptr [[ULLX]], align 8
60860 // SIMD-ONLY0-NEXT:    br label [[COND_END154]]
60861 // SIMD-ONLY0:       cond.end154:
60862 // SIMD-ONLY0-NEXT:    [[COND155:%.*]] = phi i64 [ [[TMP158]], [[COND_TRUE152]] ], [ [[TMP159]], [[COND_FALSE153]] ]
60863 // SIMD-ONLY0-NEXT:    store i64 [[COND155]], ptr [[ULLX]], align 8
60864 // SIMD-ONLY0-NEXT:    [[TMP160:%.*]] = load i64, ptr [[ULLX]], align 8
60865 // SIMD-ONLY0-NEXT:    store i64 [[TMP160]], ptr [[ULLV]], align 8
60866 // SIMD-ONLY0-NEXT:    [[TMP161:%.*]] = load i64, ptr [[ULLX]], align 8
60867 // SIMD-ONLY0-NEXT:    [[TMP162:%.*]] = load i64, ptr [[ULLE]], align 8
60868 // SIMD-ONLY0-NEXT:    [[CMP156:%.*]] = icmp eq i64 [[TMP161]], [[TMP162]]
60869 // SIMD-ONLY0-NEXT:    br i1 [[CMP156]], label [[COND_TRUE157:%.*]], label [[COND_FALSE158:%.*]]
60870 // SIMD-ONLY0:       cond.true157:
60871 // SIMD-ONLY0-NEXT:    [[TMP163:%.*]] = load i64, ptr [[ULLD]], align 8
60872 // SIMD-ONLY0-NEXT:    br label [[COND_END159:%.*]]
60873 // SIMD-ONLY0:       cond.false158:
60874 // SIMD-ONLY0-NEXT:    [[TMP164:%.*]] = load i64, ptr [[ULLX]], align 8
60875 // SIMD-ONLY0-NEXT:    br label [[COND_END159]]
60876 // SIMD-ONLY0:       cond.end159:
60877 // SIMD-ONLY0-NEXT:    [[COND160:%.*]] = phi i64 [ [[TMP163]], [[COND_TRUE157]] ], [ [[TMP164]], [[COND_FALSE158]] ]
60878 // SIMD-ONLY0-NEXT:    store i64 [[COND160]], ptr [[ULLX]], align 8
60879 // SIMD-ONLY0-NEXT:    [[TMP165:%.*]] = load i64, ptr [[ULLX]], align 8
60880 // SIMD-ONLY0-NEXT:    [[TMP166:%.*]] = load i64, ptr [[ULLE]], align 8
60881 // SIMD-ONLY0-NEXT:    [[CMP161:%.*]] = icmp ugt i64 [[TMP165]], [[TMP166]]
60882 // SIMD-ONLY0-NEXT:    br i1 [[CMP161]], label [[COND_TRUE162:%.*]], label [[COND_FALSE163:%.*]]
60883 // SIMD-ONLY0:       cond.true162:
60884 // SIMD-ONLY0-NEXT:    [[TMP167:%.*]] = load i64, ptr [[ULLE]], align 8
60885 // SIMD-ONLY0-NEXT:    br label [[COND_END164:%.*]]
60886 // SIMD-ONLY0:       cond.false163:
60887 // SIMD-ONLY0-NEXT:    [[TMP168:%.*]] = load i64, ptr [[ULLX]], align 8
60888 // SIMD-ONLY0-NEXT:    br label [[COND_END164]]
60889 // SIMD-ONLY0:       cond.end164:
60890 // SIMD-ONLY0-NEXT:    [[COND165:%.*]] = phi i64 [ [[TMP167]], [[COND_TRUE162]] ], [ [[TMP168]], [[COND_FALSE163]] ]
60891 // SIMD-ONLY0-NEXT:    store i64 [[COND165]], ptr [[ULLX]], align 8
60892 // SIMD-ONLY0-NEXT:    [[TMP169:%.*]] = load i64, ptr [[ULLX]], align 8
60893 // SIMD-ONLY0-NEXT:    store i64 [[TMP169]], ptr [[ULLV]], align 8
60894 // SIMD-ONLY0-NEXT:    [[TMP170:%.*]] = load i64, ptr [[ULLX]], align 8
60895 // SIMD-ONLY0-NEXT:    [[TMP171:%.*]] = load i64, ptr [[ULLE]], align 8
60896 // SIMD-ONLY0-NEXT:    [[CMP166:%.*]] = icmp ult i64 [[TMP170]], [[TMP171]]
60897 // SIMD-ONLY0-NEXT:    br i1 [[CMP166]], label [[COND_TRUE167:%.*]], label [[COND_FALSE168:%.*]]
60898 // SIMD-ONLY0:       cond.true167:
60899 // SIMD-ONLY0-NEXT:    [[TMP172:%.*]] = load i64, ptr [[ULLE]], align 8
60900 // SIMD-ONLY0-NEXT:    br label [[COND_END169:%.*]]
60901 // SIMD-ONLY0:       cond.false168:
60902 // SIMD-ONLY0-NEXT:    [[TMP173:%.*]] = load i64, ptr [[ULLX]], align 8
60903 // SIMD-ONLY0-NEXT:    br label [[COND_END169]]
60904 // SIMD-ONLY0:       cond.end169:
60905 // SIMD-ONLY0-NEXT:    [[COND170:%.*]] = phi i64 [ [[TMP172]], [[COND_TRUE167]] ], [ [[TMP173]], [[COND_FALSE168]] ]
60906 // SIMD-ONLY0-NEXT:    store i64 [[COND170]], ptr [[ULLX]], align 8
60907 // SIMD-ONLY0-NEXT:    [[TMP174:%.*]] = load i64, ptr [[ULLX]], align 8
60908 // SIMD-ONLY0-NEXT:    store i64 [[TMP174]], ptr [[ULLV]], align 8
60909 // SIMD-ONLY0-NEXT:    [[TMP175:%.*]] = load i64, ptr [[ULLX]], align 8
60910 // SIMD-ONLY0-NEXT:    [[TMP176:%.*]] = load i64, ptr [[ULLE]], align 8
60911 // SIMD-ONLY0-NEXT:    [[CMP171:%.*]] = icmp eq i64 [[TMP175]], [[TMP176]]
60912 // SIMD-ONLY0-NEXT:    br i1 [[CMP171]], label [[COND_TRUE172:%.*]], label [[COND_FALSE173:%.*]]
60913 // SIMD-ONLY0:       cond.true172:
60914 // SIMD-ONLY0-NEXT:    [[TMP177:%.*]] = load i64, ptr [[ULLD]], align 8
60915 // SIMD-ONLY0-NEXT:    br label [[COND_END174:%.*]]
60916 // SIMD-ONLY0:       cond.false173:
60917 // SIMD-ONLY0-NEXT:    [[TMP178:%.*]] = load i64, ptr [[ULLX]], align 8
60918 // SIMD-ONLY0-NEXT:    br label [[COND_END174]]
60919 // SIMD-ONLY0:       cond.end174:
60920 // SIMD-ONLY0-NEXT:    [[COND175:%.*]] = phi i64 [ [[TMP177]], [[COND_TRUE172]] ], [ [[TMP178]], [[COND_FALSE173]] ]
60921 // SIMD-ONLY0-NEXT:    store i64 [[COND175]], ptr [[ULLX]], align 8
60922 // SIMD-ONLY0-NEXT:    [[TMP179:%.*]] = load i64, ptr [[ULLX]], align 8
60923 // SIMD-ONLY0-NEXT:    store i64 [[TMP179]], ptr [[ULLV]], align 8
60924 // SIMD-ONLY0-NEXT:    [[TMP180:%.*]] = load i64, ptr [[ULLV]], align 8
60925 // SIMD-ONLY0-NEXT:    ret i64 [[TMP180]]
60926 //
60927 //
60928 // SIMD-ONLY0-LABEL: @fxevd(
60929 // SIMD-ONLY0-NEXT:  entry:
60930 // SIMD-ONLY0-NEXT:    [[FX:%.*]] = alloca float, align 4
60931 // SIMD-ONLY0-NEXT:    [[FV:%.*]] = alloca float, align 4
60932 // SIMD-ONLY0-NEXT:    [[FE:%.*]] = alloca float, align 4
60933 // SIMD-ONLY0-NEXT:    [[FD:%.*]] = alloca float, align 4
60934 // SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = load float, ptr [[FX]], align 4
60935 // SIMD-ONLY0-NEXT:    store float [[TMP0]], ptr [[FV]], align 4
60936 // SIMD-ONLY0-NEXT:    [[TMP1:%.*]] = load float, ptr [[FX]], align 4
60937 // SIMD-ONLY0-NEXT:    [[TMP2:%.*]] = load float, ptr [[FE]], align 4
60938 // SIMD-ONLY0-NEXT:    [[CMP:%.*]] = fcmp ogt float [[TMP1]], [[TMP2]]
60939 // SIMD-ONLY0-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
60940 // SIMD-ONLY0:       cond.true:
60941 // SIMD-ONLY0-NEXT:    [[TMP3:%.*]] = load float, ptr [[FE]], align 4
60942 // SIMD-ONLY0-NEXT:    br label [[COND_END:%.*]]
60943 // SIMD-ONLY0:       cond.false:
60944 // SIMD-ONLY0-NEXT:    [[TMP4:%.*]] = load float, ptr [[FX]], align 4
60945 // SIMD-ONLY0-NEXT:    br label [[COND_END]]
60946 // SIMD-ONLY0:       cond.end:
60947 // SIMD-ONLY0-NEXT:    [[COND:%.*]] = phi float [ [[TMP3]], [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
60948 // SIMD-ONLY0-NEXT:    store float [[COND]], ptr [[FX]], align 4
60949 // SIMD-ONLY0-NEXT:    [[TMP5:%.*]] = load float, ptr [[FX]], align 4
60950 // SIMD-ONLY0-NEXT:    store float [[TMP5]], ptr [[FV]], align 4
60951 // SIMD-ONLY0-NEXT:    [[TMP6:%.*]] = load float, ptr [[FX]], align 4
60952 // SIMD-ONLY0-NEXT:    [[TMP7:%.*]] = load float, ptr [[FE]], align 4
60953 // SIMD-ONLY0-NEXT:    [[CMP1:%.*]] = fcmp olt float [[TMP6]], [[TMP7]]
60954 // SIMD-ONLY0-NEXT:    br i1 [[CMP1]], label [[COND_TRUE2:%.*]], label [[COND_FALSE3:%.*]]
60955 // SIMD-ONLY0:       cond.true2:
60956 // SIMD-ONLY0-NEXT:    [[TMP8:%.*]] = load float, ptr [[FE]], align 4
60957 // SIMD-ONLY0-NEXT:    br label [[COND_END4:%.*]]
60958 // SIMD-ONLY0:       cond.false3:
60959 // SIMD-ONLY0-NEXT:    [[TMP9:%.*]] = load float, ptr [[FX]], align 4
60960 // SIMD-ONLY0-NEXT:    br label [[COND_END4]]
60961 // SIMD-ONLY0:       cond.end4:
60962 // SIMD-ONLY0-NEXT:    [[COND5:%.*]] = phi float [ [[TMP8]], [[COND_TRUE2]] ], [ [[TMP9]], [[COND_FALSE3]] ]
60963 // SIMD-ONLY0-NEXT:    store float [[COND5]], ptr [[FX]], align 4
60964 // SIMD-ONLY0-NEXT:    [[TMP10:%.*]] = load float, ptr [[FX]], align 4
60965 // SIMD-ONLY0-NEXT:    store float [[TMP10]], ptr [[FV]], align 4
60966 // SIMD-ONLY0-NEXT:    [[TMP11:%.*]] = load float, ptr [[FX]], align 4
60967 // SIMD-ONLY0-NEXT:    [[TMP12:%.*]] = load float, ptr [[FE]], align 4
60968 // SIMD-ONLY0-NEXT:    [[CMP6:%.*]] = fcmp oeq float [[TMP11]], [[TMP12]]
60969 // SIMD-ONLY0-NEXT:    br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
60970 // SIMD-ONLY0:       cond.true7:
60971 // SIMD-ONLY0-NEXT:    [[TMP13:%.*]] = load float, ptr [[FD]], align 4
60972 // SIMD-ONLY0-NEXT:    br label [[COND_END9:%.*]]
60973 // SIMD-ONLY0:       cond.false8:
60974 // SIMD-ONLY0-NEXT:    [[TMP14:%.*]] = load float, ptr [[FX]], align 4
60975 // SIMD-ONLY0-NEXT:    br label [[COND_END9]]
60976 // SIMD-ONLY0:       cond.end9:
60977 // SIMD-ONLY0-NEXT:    [[COND10:%.*]] = phi float [ [[TMP13]], [[COND_TRUE7]] ], [ [[TMP14]], [[COND_FALSE8]] ]
60978 // SIMD-ONLY0-NEXT:    store float [[COND10]], ptr [[FX]], align 4
60979 // SIMD-ONLY0-NEXT:    [[TMP15:%.*]] = load float, ptr [[FX]], align 4
60980 // SIMD-ONLY0-NEXT:    [[TMP16:%.*]] = load float, ptr [[FE]], align 4
60981 // SIMD-ONLY0-NEXT:    [[CMP11:%.*]] = fcmp ogt float [[TMP15]], [[TMP16]]
60982 // SIMD-ONLY0-NEXT:    br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
60983 // SIMD-ONLY0:       cond.true12:
60984 // SIMD-ONLY0-NEXT:    [[TMP17:%.*]] = load float, ptr [[FE]], align 4
60985 // SIMD-ONLY0-NEXT:    br label [[COND_END14:%.*]]
60986 // SIMD-ONLY0:       cond.false13:
60987 // SIMD-ONLY0-NEXT:    [[TMP18:%.*]] = load float, ptr [[FX]], align 4
60988 // SIMD-ONLY0-NEXT:    br label [[COND_END14]]
60989 // SIMD-ONLY0:       cond.end14:
60990 // SIMD-ONLY0-NEXT:    [[COND15:%.*]] = phi float [ [[TMP17]], [[COND_TRUE12]] ], [ [[TMP18]], [[COND_FALSE13]] ]
60991 // SIMD-ONLY0-NEXT:    store float [[COND15]], ptr [[FX]], align 4
60992 // SIMD-ONLY0-NEXT:    [[TMP19:%.*]] = load float, ptr [[FX]], align 4
60993 // SIMD-ONLY0-NEXT:    store float [[TMP19]], ptr [[FV]], align 4
60994 // SIMD-ONLY0-NEXT:    [[TMP20:%.*]] = load float, ptr [[FX]], align 4
60995 // SIMD-ONLY0-NEXT:    [[TMP21:%.*]] = load float, ptr [[FE]], align 4
60996 // SIMD-ONLY0-NEXT:    [[CMP16:%.*]] = fcmp olt float [[TMP20]], [[TMP21]]
60997 // SIMD-ONLY0-NEXT:    br i1 [[CMP16]], label [[COND_TRUE17:%.*]], label [[COND_FALSE18:%.*]]
60998 // SIMD-ONLY0:       cond.true17:
60999 // SIMD-ONLY0-NEXT:    [[TMP22:%.*]] = load float, ptr [[FE]], align 4
61000 // SIMD-ONLY0-NEXT:    br label [[COND_END19:%.*]]
61001 // SIMD-ONLY0:       cond.false18:
61002 // SIMD-ONLY0-NEXT:    [[TMP23:%.*]] = load float, ptr [[FX]], align 4
61003 // SIMD-ONLY0-NEXT:    br label [[COND_END19]]
61004 // SIMD-ONLY0:       cond.end19:
61005 // SIMD-ONLY0-NEXT:    [[COND20:%.*]] = phi float [ [[TMP22]], [[COND_TRUE17]] ], [ [[TMP23]], [[COND_FALSE18]] ]
61006 // SIMD-ONLY0-NEXT:    store float [[COND20]], ptr [[FX]], align 4
61007 // SIMD-ONLY0-NEXT:    [[TMP24:%.*]] = load float, ptr [[FX]], align 4
61008 // SIMD-ONLY0-NEXT:    store float [[TMP24]], ptr [[FV]], align 4
61009 // SIMD-ONLY0-NEXT:    [[TMP25:%.*]] = load float, ptr [[FX]], align 4
61010 // SIMD-ONLY0-NEXT:    [[TMP26:%.*]] = load float, ptr [[FE]], align 4
61011 // SIMD-ONLY0-NEXT:    [[CMP21:%.*]] = fcmp oeq float [[TMP25]], [[TMP26]]
61012 // SIMD-ONLY0-NEXT:    br i1 [[CMP21]], label [[COND_TRUE22:%.*]], label [[COND_FALSE23:%.*]]
61013 // SIMD-ONLY0:       cond.true22:
61014 // SIMD-ONLY0-NEXT:    [[TMP27:%.*]] = load float, ptr [[FD]], align 4
61015 // SIMD-ONLY0-NEXT:    br label [[COND_END24:%.*]]
61016 // SIMD-ONLY0:       cond.false23:
61017 // SIMD-ONLY0-NEXT:    [[TMP28:%.*]] = load float, ptr [[FX]], align 4
61018 // SIMD-ONLY0-NEXT:    br label [[COND_END24]]
61019 // SIMD-ONLY0:       cond.end24:
61020 // SIMD-ONLY0-NEXT:    [[COND25:%.*]] = phi float [ [[TMP27]], [[COND_TRUE22]] ], [ [[TMP28]], [[COND_FALSE23]] ]
61021 // SIMD-ONLY0-NEXT:    store float [[COND25]], ptr [[FX]], align 4
61022 // SIMD-ONLY0-NEXT:    [[TMP29:%.*]] = load float, ptr [[FX]], align 4
61023 // SIMD-ONLY0-NEXT:    store float [[TMP29]], ptr [[FV]], align 4
61024 // SIMD-ONLY0-NEXT:    [[TMP30:%.*]] = load float, ptr [[FX]], align 4
61025 // SIMD-ONLY0-NEXT:    store float [[TMP30]], ptr [[FV]], align 4
61026 // SIMD-ONLY0-NEXT:    [[TMP31:%.*]] = load float, ptr [[FX]], align 4
61027 // SIMD-ONLY0-NEXT:    [[TMP32:%.*]] = load float, ptr [[FE]], align 4
61028 // SIMD-ONLY0-NEXT:    [[CMP26:%.*]] = fcmp ogt float [[TMP31]], [[TMP32]]
61029 // SIMD-ONLY0-NEXT:    br i1 [[CMP26]], label [[COND_TRUE27:%.*]], label [[COND_FALSE28:%.*]]
61030 // SIMD-ONLY0:       cond.true27:
61031 // SIMD-ONLY0-NEXT:    [[TMP33:%.*]] = load float, ptr [[FE]], align 4
61032 // SIMD-ONLY0-NEXT:    br label [[COND_END29:%.*]]
61033 // SIMD-ONLY0:       cond.false28:
61034 // SIMD-ONLY0-NEXT:    [[TMP34:%.*]] = load float, ptr [[FX]], align 4
61035 // SIMD-ONLY0-NEXT:    br label [[COND_END29]]
61036 // SIMD-ONLY0:       cond.end29:
61037 // SIMD-ONLY0-NEXT:    [[COND30:%.*]] = phi float [ [[TMP33]], [[COND_TRUE27]] ], [ [[TMP34]], [[COND_FALSE28]] ]
61038 // SIMD-ONLY0-NEXT:    store float [[COND30]], ptr [[FX]], align 4
61039 // SIMD-ONLY0-NEXT:    [[TMP35:%.*]] = load float, ptr [[FX]], align 4
61040 // SIMD-ONLY0-NEXT:    store float [[TMP35]], ptr [[FV]], align 4
61041 // SIMD-ONLY0-NEXT:    [[TMP36:%.*]] = load float, ptr [[FX]], align 4
61042 // SIMD-ONLY0-NEXT:    [[TMP37:%.*]] = load float, ptr [[FE]], align 4
61043 // SIMD-ONLY0-NEXT:    [[CMP31:%.*]] = fcmp olt float [[TMP36]], [[TMP37]]
61044 // SIMD-ONLY0-NEXT:    br i1 [[CMP31]], label [[COND_TRUE32:%.*]], label [[COND_FALSE33:%.*]]
61045 // SIMD-ONLY0:       cond.true32:
61046 // SIMD-ONLY0-NEXT:    [[TMP38:%.*]] = load float, ptr [[FE]], align 4
61047 // SIMD-ONLY0-NEXT:    br label [[COND_END34:%.*]]
61048 // SIMD-ONLY0:       cond.false33:
61049 // SIMD-ONLY0-NEXT:    [[TMP39:%.*]] = load float, ptr [[FX]], align 4
61050 // SIMD-ONLY0-NEXT:    br label [[COND_END34]]
61051 // SIMD-ONLY0:       cond.end34:
61052 // SIMD-ONLY0-NEXT:    [[COND35:%.*]] = phi float [ [[TMP38]], [[COND_TRUE32]] ], [ [[TMP39]], [[COND_FALSE33]] ]
61053 // SIMD-ONLY0-NEXT:    store float [[COND35]], ptr [[FX]], align 4
61054 // SIMD-ONLY0-NEXT:    [[TMP40:%.*]] = load float, ptr [[FX]], align 4
61055 // SIMD-ONLY0-NEXT:    store float [[TMP40]], ptr [[FV]], align 4
61056 // SIMD-ONLY0-NEXT:    [[TMP41:%.*]] = load float, ptr [[FX]], align 4
61057 // SIMD-ONLY0-NEXT:    [[TMP42:%.*]] = load float, ptr [[FE]], align 4
61058 // SIMD-ONLY0-NEXT:    [[CMP36:%.*]] = fcmp oeq float [[TMP41]], [[TMP42]]
61059 // SIMD-ONLY0-NEXT:    br i1 [[CMP36]], label [[COND_TRUE37:%.*]], label [[COND_FALSE38:%.*]]
61060 // SIMD-ONLY0:       cond.true37:
61061 // SIMD-ONLY0-NEXT:    [[TMP43:%.*]] = load float, ptr [[FD]], align 4
61062 // SIMD-ONLY0-NEXT:    br label [[COND_END39:%.*]]
61063 // SIMD-ONLY0:       cond.false38:
61064 // SIMD-ONLY0-NEXT:    [[TMP44:%.*]] = load float, ptr [[FX]], align 4
61065 // SIMD-ONLY0-NEXT:    br label [[COND_END39]]
61066 // SIMD-ONLY0:       cond.end39:
61067 // SIMD-ONLY0-NEXT:    [[COND40:%.*]] = phi float [ [[TMP43]], [[COND_TRUE37]] ], [ [[TMP44]], [[COND_FALSE38]] ]
61068 // SIMD-ONLY0-NEXT:    store float [[COND40]], ptr [[FX]], align 4
61069 // SIMD-ONLY0-NEXT:    [[TMP45:%.*]] = load float, ptr [[FX]], align 4
61070 // SIMD-ONLY0-NEXT:    [[TMP46:%.*]] = load float, ptr [[FE]], align 4
61071 // SIMD-ONLY0-NEXT:    [[CMP41:%.*]] = fcmp ogt float [[TMP45]], [[TMP46]]
61072 // SIMD-ONLY0-NEXT:    br i1 [[CMP41]], label [[COND_TRUE42:%.*]], label [[COND_FALSE43:%.*]]
61073 // SIMD-ONLY0:       cond.true42:
61074 // SIMD-ONLY0-NEXT:    [[TMP47:%.*]] = load float, ptr [[FE]], align 4
61075 // SIMD-ONLY0-NEXT:    br label [[COND_END44:%.*]]
61076 // SIMD-ONLY0:       cond.false43:
61077 // SIMD-ONLY0-NEXT:    [[TMP48:%.*]] = load float, ptr [[FX]], align 4
61078 // SIMD-ONLY0-NEXT:    br label [[COND_END44]]
61079 // SIMD-ONLY0:       cond.end44:
61080 // SIMD-ONLY0-NEXT:    [[COND45:%.*]] = phi float [ [[TMP47]], [[COND_TRUE42]] ], [ [[TMP48]], [[COND_FALSE43]] ]
61081 // SIMD-ONLY0-NEXT:    store float [[COND45]], ptr [[FX]], align 4
61082 // SIMD-ONLY0-NEXT:    [[TMP49:%.*]] = load float, ptr [[FX]], align 4
61083 // SIMD-ONLY0-NEXT:    store float [[TMP49]], ptr [[FV]], align 4
61084 // SIMD-ONLY0-NEXT:    [[TMP50:%.*]] = load float, ptr [[FX]], align 4
61085 // SIMD-ONLY0-NEXT:    [[TMP51:%.*]] = load float, ptr [[FE]], align 4
61086 // SIMD-ONLY0-NEXT:    [[CMP46:%.*]] = fcmp olt float [[TMP50]], [[TMP51]]
61087 // SIMD-ONLY0-NEXT:    br i1 [[CMP46]], label [[COND_TRUE47:%.*]], label [[COND_FALSE48:%.*]]
61088 // SIMD-ONLY0:       cond.true47:
61089 // SIMD-ONLY0-NEXT:    [[TMP52:%.*]] = load float, ptr [[FE]], align 4
61090 // SIMD-ONLY0-NEXT:    br label [[COND_END49:%.*]]
61091 // SIMD-ONLY0:       cond.false48:
61092 // SIMD-ONLY0-NEXT:    [[TMP53:%.*]] = load float, ptr [[FX]], align 4
61093 // SIMD-ONLY0-NEXT:    br label [[COND_END49]]
61094 // SIMD-ONLY0:       cond.end49:
61095 // SIMD-ONLY0-NEXT:    [[COND50:%.*]] = phi float [ [[TMP52]], [[COND_TRUE47]] ], [ [[TMP53]], [[COND_FALSE48]] ]
61096 // SIMD-ONLY0-NEXT:    store float [[COND50]], ptr [[FX]], align 4
61097 // SIMD-ONLY0-NEXT:    [[TMP54:%.*]] = load float, ptr [[FX]], align 4
61098 // SIMD-ONLY0-NEXT:    store float [[TMP54]], ptr [[FV]], align 4
61099 // SIMD-ONLY0-NEXT:    [[TMP55:%.*]] = load float, ptr [[FX]], align 4
61100 // SIMD-ONLY0-NEXT:    [[TMP56:%.*]] = load float, ptr [[FE]], align 4
61101 // SIMD-ONLY0-NEXT:    [[CMP51:%.*]] = fcmp oeq float [[TMP55]], [[TMP56]]
61102 // SIMD-ONLY0-NEXT:    br i1 [[CMP51]], label [[COND_TRUE52:%.*]], label [[COND_FALSE53:%.*]]
61103 // SIMD-ONLY0:       cond.true52:
61104 // SIMD-ONLY0-NEXT:    [[TMP57:%.*]] = load float, ptr [[FD]], align 4
61105 // SIMD-ONLY0-NEXT:    br label [[COND_END54:%.*]]
61106 // SIMD-ONLY0:       cond.false53:
61107 // SIMD-ONLY0-NEXT:    [[TMP58:%.*]] = load float, ptr [[FX]], align 4
61108 // SIMD-ONLY0-NEXT:    br label [[COND_END54]]
61109 // SIMD-ONLY0:       cond.end54:
61110 // SIMD-ONLY0-NEXT:    [[COND55:%.*]] = phi float [ [[TMP57]], [[COND_TRUE52]] ], [ [[TMP58]], [[COND_FALSE53]] ]
61111 // SIMD-ONLY0-NEXT:    store float [[COND55]], ptr [[FX]], align 4
61112 // SIMD-ONLY0-NEXT:    [[TMP59:%.*]] = load float, ptr [[FX]], align 4
61113 // SIMD-ONLY0-NEXT:    store float [[TMP59]], ptr [[FV]], align 4
61114 // SIMD-ONLY0-NEXT:    [[TMP60:%.*]] = load float, ptr [[FX]], align 4
61115 // SIMD-ONLY0-NEXT:    store float [[TMP60]], ptr [[FV]], align 4
61116 // SIMD-ONLY0-NEXT:    [[TMP61:%.*]] = load float, ptr [[FX]], align 4
61117 // SIMD-ONLY0-NEXT:    [[TMP62:%.*]] = load float, ptr [[FE]], align 4
61118 // SIMD-ONLY0-NEXT:    [[CMP56:%.*]] = fcmp ogt float [[TMP61]], [[TMP62]]
61119 // SIMD-ONLY0-NEXT:    br i1 [[CMP56]], label [[COND_TRUE57:%.*]], label [[COND_FALSE58:%.*]]
61120 // SIMD-ONLY0:       cond.true57:
61121 // SIMD-ONLY0-NEXT:    [[TMP63:%.*]] = load float, ptr [[FE]], align 4
61122 // SIMD-ONLY0-NEXT:    br label [[COND_END59:%.*]]
61123 // SIMD-ONLY0:       cond.false58:
61124 // SIMD-ONLY0-NEXT:    [[TMP64:%.*]] = load float, ptr [[FX]], align 4
61125 // SIMD-ONLY0-NEXT:    br label [[COND_END59]]
61126 // SIMD-ONLY0:       cond.end59:
61127 // SIMD-ONLY0-NEXT:    [[COND60:%.*]] = phi float [ [[TMP63]], [[COND_TRUE57]] ], [ [[TMP64]], [[COND_FALSE58]] ]
61128 // SIMD-ONLY0-NEXT:    store float [[COND60]], ptr [[FX]], align 4
61129 // SIMD-ONLY0-NEXT:    [[TMP65:%.*]] = load float, ptr [[FX]], align 4
61130 // SIMD-ONLY0-NEXT:    store float [[TMP65]], ptr [[FV]], align 4
61131 // SIMD-ONLY0-NEXT:    [[TMP66:%.*]] = load float, ptr [[FX]], align 4
61132 // SIMD-ONLY0-NEXT:    [[TMP67:%.*]] = load float, ptr [[FE]], align 4
61133 // SIMD-ONLY0-NEXT:    [[CMP61:%.*]] = fcmp olt float [[TMP66]], [[TMP67]]
61134 // SIMD-ONLY0-NEXT:    br i1 [[CMP61]], label [[COND_TRUE62:%.*]], label [[COND_FALSE63:%.*]]
61135 // SIMD-ONLY0:       cond.true62:
61136 // SIMD-ONLY0-NEXT:    [[TMP68:%.*]] = load float, ptr [[FE]], align 4
61137 // SIMD-ONLY0-NEXT:    br label [[COND_END64:%.*]]
61138 // SIMD-ONLY0:       cond.false63:
61139 // SIMD-ONLY0-NEXT:    [[TMP69:%.*]] = load float, ptr [[FX]], align 4
61140 // SIMD-ONLY0-NEXT:    br label [[COND_END64]]
61141 // SIMD-ONLY0:       cond.end64:
61142 // SIMD-ONLY0-NEXT:    [[COND65:%.*]] = phi float [ [[TMP68]], [[COND_TRUE62]] ], [ [[TMP69]], [[COND_FALSE63]] ]
61143 // SIMD-ONLY0-NEXT:    store float [[COND65]], ptr [[FX]], align 4
61144 // SIMD-ONLY0-NEXT:    [[TMP70:%.*]] = load float, ptr [[FX]], align 4
61145 // SIMD-ONLY0-NEXT:    store float [[TMP70]], ptr [[FV]], align 4
61146 // SIMD-ONLY0-NEXT:    [[TMP71:%.*]] = load float, ptr [[FX]], align 4
61147 // SIMD-ONLY0-NEXT:    [[TMP72:%.*]] = load float, ptr [[FE]], align 4
61148 // SIMD-ONLY0-NEXT:    [[CMP66:%.*]] = fcmp oeq float [[TMP71]], [[TMP72]]
61149 // SIMD-ONLY0-NEXT:    br i1 [[CMP66]], label [[COND_TRUE67:%.*]], label [[COND_FALSE68:%.*]]
61150 // SIMD-ONLY0:       cond.true67:
61151 // SIMD-ONLY0-NEXT:    [[TMP73:%.*]] = load float, ptr [[FD]], align 4
61152 // SIMD-ONLY0-NEXT:    br label [[COND_END69:%.*]]
61153 // SIMD-ONLY0:       cond.false68:
61154 // SIMD-ONLY0-NEXT:    [[TMP74:%.*]] = load float, ptr [[FX]], align 4
61155 // SIMD-ONLY0-NEXT:    br label [[COND_END69]]
61156 // SIMD-ONLY0:       cond.end69:
61157 // SIMD-ONLY0-NEXT:    [[COND70:%.*]] = phi float [ [[TMP73]], [[COND_TRUE67]] ], [ [[TMP74]], [[COND_FALSE68]] ]
61158 // SIMD-ONLY0-NEXT:    store float [[COND70]], ptr [[FX]], align 4
61159 // SIMD-ONLY0-NEXT:    [[TMP75:%.*]] = load float, ptr [[FX]], align 4
61160 // SIMD-ONLY0-NEXT:    [[TMP76:%.*]] = load float, ptr [[FE]], align 4
61161 // SIMD-ONLY0-NEXT:    [[CMP71:%.*]] = fcmp ogt float [[TMP75]], [[TMP76]]
61162 // SIMD-ONLY0-NEXT:    br i1 [[CMP71]], label [[COND_TRUE72:%.*]], label [[COND_FALSE73:%.*]]
61163 // SIMD-ONLY0:       cond.true72:
61164 // SIMD-ONLY0-NEXT:    [[TMP77:%.*]] = load float, ptr [[FE]], align 4
61165 // SIMD-ONLY0-NEXT:    br label [[COND_END74:%.*]]
61166 // SIMD-ONLY0:       cond.false73:
61167 // SIMD-ONLY0-NEXT:    [[TMP78:%.*]] = load float, ptr [[FX]], align 4
61168 // SIMD-ONLY0-NEXT:    br label [[COND_END74]]
61169 // SIMD-ONLY0:       cond.end74:
61170 // SIMD-ONLY0-NEXT:    [[COND75:%.*]] = phi float [ [[TMP77]], [[COND_TRUE72]] ], [ [[TMP78]], [[COND_FALSE73]] ]
61171 // SIMD-ONLY0-NEXT:    store float [[COND75]], ptr [[FX]], align 4
61172 // SIMD-ONLY0-NEXT:    [[TMP79:%.*]] = load float, ptr [[FX]], align 4
61173 // SIMD-ONLY0-NEXT:    store float [[TMP79]], ptr [[FV]], align 4
61174 // SIMD-ONLY0-NEXT:    [[TMP80:%.*]] = load float, ptr [[FX]], align 4
61175 // SIMD-ONLY0-NEXT:    [[TMP81:%.*]] = load float, ptr [[FE]], align 4
61176 // SIMD-ONLY0-NEXT:    [[CMP76:%.*]] = fcmp olt float [[TMP80]], [[TMP81]]
61177 // SIMD-ONLY0-NEXT:    br i1 [[CMP76]], label [[COND_TRUE77:%.*]], label [[COND_FALSE78:%.*]]
61178 // SIMD-ONLY0:       cond.true77:
61179 // SIMD-ONLY0-NEXT:    [[TMP82:%.*]] = load float, ptr [[FE]], align 4
61180 // SIMD-ONLY0-NEXT:    br label [[COND_END79:%.*]]
61181 // SIMD-ONLY0:       cond.false78:
61182 // SIMD-ONLY0-NEXT:    [[TMP83:%.*]] = load float, ptr [[FX]], align 4
61183 // SIMD-ONLY0-NEXT:    br label [[COND_END79]]
61184 // SIMD-ONLY0:       cond.end79:
61185 // SIMD-ONLY0-NEXT:    [[COND80:%.*]] = phi float [ [[TMP82]], [[COND_TRUE77]] ], [ [[TMP83]], [[COND_FALSE78]] ]
61186 // SIMD-ONLY0-NEXT:    store float [[COND80]], ptr [[FX]], align 4
61187 // SIMD-ONLY0-NEXT:    [[TMP84:%.*]] = load float, ptr [[FX]], align 4
61188 // SIMD-ONLY0-NEXT:    store float [[TMP84]], ptr [[FV]], align 4
61189 // SIMD-ONLY0-NEXT:    [[TMP85:%.*]] = load float, ptr [[FX]], align 4
61190 // SIMD-ONLY0-NEXT:    [[TMP86:%.*]] = load float, ptr [[FE]], align 4
61191 // SIMD-ONLY0-NEXT:    [[CMP81:%.*]] = fcmp oeq float [[TMP85]], [[TMP86]]
61192 // SIMD-ONLY0-NEXT:    br i1 [[CMP81]], label [[COND_TRUE82:%.*]], label [[COND_FALSE83:%.*]]
61193 // SIMD-ONLY0:       cond.true82:
61194 // SIMD-ONLY0-NEXT:    [[TMP87:%.*]] = load float, ptr [[FD]], align 4
61195 // SIMD-ONLY0-NEXT:    br label [[COND_END84:%.*]]
61196 // SIMD-ONLY0:       cond.false83:
61197 // SIMD-ONLY0-NEXT:    [[TMP88:%.*]] = load float, ptr [[FX]], align 4
61198 // SIMD-ONLY0-NEXT:    br label [[COND_END84]]
61199 // SIMD-ONLY0:       cond.end84:
61200 // SIMD-ONLY0-NEXT:    [[COND85:%.*]] = phi float [ [[TMP87]], [[COND_TRUE82]] ], [ [[TMP88]], [[COND_FALSE83]] ]
61201 // SIMD-ONLY0-NEXT:    store float [[COND85]], ptr [[FX]], align 4
61202 // SIMD-ONLY0-NEXT:    [[TMP89:%.*]] = load float, ptr [[FX]], align 4
61203 // SIMD-ONLY0-NEXT:    store float [[TMP89]], ptr [[FV]], align 4
61204 // SIMD-ONLY0-NEXT:    [[TMP90:%.*]] = load float, ptr [[FX]], align 4
61205 // SIMD-ONLY0-NEXT:    store float [[TMP90]], ptr [[FV]], align 4
61206 // SIMD-ONLY0-NEXT:    [[TMP91:%.*]] = load float, ptr [[FX]], align 4
61207 // SIMD-ONLY0-NEXT:    [[TMP92:%.*]] = load float, ptr [[FE]], align 4
61208 // SIMD-ONLY0-NEXT:    [[CMP86:%.*]] = fcmp ogt float [[TMP91]], [[TMP92]]
61209 // SIMD-ONLY0-NEXT:    br i1 [[CMP86]], label [[COND_TRUE87:%.*]], label [[COND_FALSE88:%.*]]
61210 // SIMD-ONLY0:       cond.true87:
61211 // SIMD-ONLY0-NEXT:    [[TMP93:%.*]] = load float, ptr [[FE]], align 4
61212 // SIMD-ONLY0-NEXT:    br label [[COND_END89:%.*]]
61213 // SIMD-ONLY0:       cond.false88:
61214 // SIMD-ONLY0-NEXT:    [[TMP94:%.*]] = load float, ptr [[FX]], align 4
61215 // SIMD-ONLY0-NEXT:    br label [[COND_END89]]
61216 // SIMD-ONLY0:       cond.end89:
61217 // SIMD-ONLY0-NEXT:    [[COND90:%.*]] = phi float [ [[TMP93]], [[COND_TRUE87]] ], [ [[TMP94]], [[COND_FALSE88]] ]
61218 // SIMD-ONLY0-NEXT:    store float [[COND90]], ptr [[FX]], align 4
61219 // SIMD-ONLY0-NEXT:    [[TMP95:%.*]] = load float, ptr [[FX]], align 4
61220 // SIMD-ONLY0-NEXT:    store float [[TMP95]], ptr [[FV]], align 4
61221 // SIMD-ONLY0-NEXT:    [[TMP96:%.*]] = load float, ptr [[FX]], align 4
61222 // SIMD-ONLY0-NEXT:    [[TMP97:%.*]] = load float, ptr [[FE]], align 4
61223 // SIMD-ONLY0-NEXT:    [[CMP91:%.*]] = fcmp olt float [[TMP96]], [[TMP97]]
61224 // SIMD-ONLY0-NEXT:    br i1 [[CMP91]], label [[COND_TRUE92:%.*]], label [[COND_FALSE93:%.*]]
61225 // SIMD-ONLY0:       cond.true92:
61226 // SIMD-ONLY0-NEXT:    [[TMP98:%.*]] = load float, ptr [[FE]], align 4
61227 // SIMD-ONLY0-NEXT:    br label [[COND_END94:%.*]]
61228 // SIMD-ONLY0:       cond.false93:
61229 // SIMD-ONLY0-NEXT:    [[TMP99:%.*]] = load float, ptr [[FX]], align 4
61230 // SIMD-ONLY0-NEXT:    br label [[COND_END94]]
61231 // SIMD-ONLY0:       cond.end94:
61232 // SIMD-ONLY0-NEXT:    [[COND95:%.*]] = phi float [ [[TMP98]], [[COND_TRUE92]] ], [ [[TMP99]], [[COND_FALSE93]] ]
61233 // SIMD-ONLY0-NEXT:    store float [[COND95]], ptr [[FX]], align 4
61234 // SIMD-ONLY0-NEXT:    [[TMP100:%.*]] = load float, ptr [[FX]], align 4
61235 // SIMD-ONLY0-NEXT:    store float [[TMP100]], ptr [[FV]], align 4
61236 // SIMD-ONLY0-NEXT:    [[TMP101:%.*]] = load float, ptr [[FX]], align 4
61237 // SIMD-ONLY0-NEXT:    [[TMP102:%.*]] = load float, ptr [[FE]], align 4
61238 // SIMD-ONLY0-NEXT:    [[CMP96:%.*]] = fcmp oeq float [[TMP101]], [[TMP102]]
61239 // SIMD-ONLY0-NEXT:    br i1 [[CMP96]], label [[COND_TRUE97:%.*]], label [[COND_FALSE98:%.*]]
61240 // SIMD-ONLY0:       cond.true97:
61241 // SIMD-ONLY0-NEXT:    [[TMP103:%.*]] = load float, ptr [[FD]], align 4
61242 // SIMD-ONLY0-NEXT:    br label [[COND_END99:%.*]]
61243 // SIMD-ONLY0:       cond.false98:
61244 // SIMD-ONLY0-NEXT:    [[TMP104:%.*]] = load float, ptr [[FX]], align 4
61245 // SIMD-ONLY0-NEXT:    br label [[COND_END99]]
61246 // SIMD-ONLY0:       cond.end99:
61247 // SIMD-ONLY0-NEXT:    [[COND100:%.*]] = phi float [ [[TMP103]], [[COND_TRUE97]] ], [ [[TMP104]], [[COND_FALSE98]] ]
61248 // SIMD-ONLY0-NEXT:    store float [[COND100]], ptr [[FX]], align 4
61249 // SIMD-ONLY0-NEXT:    [[TMP105:%.*]] = load float, ptr [[FX]], align 4
61250 // SIMD-ONLY0-NEXT:    [[TMP106:%.*]] = load float, ptr [[FE]], align 4
61251 // SIMD-ONLY0-NEXT:    [[CMP101:%.*]] = fcmp ogt float [[TMP105]], [[TMP106]]
61252 // SIMD-ONLY0-NEXT:    br i1 [[CMP101]], label [[COND_TRUE102:%.*]], label [[COND_FALSE103:%.*]]
61253 // SIMD-ONLY0:       cond.true102:
61254 // SIMD-ONLY0-NEXT:    [[TMP107:%.*]] = load float, ptr [[FE]], align 4
61255 // SIMD-ONLY0-NEXT:    br label [[COND_END104:%.*]]
61256 // SIMD-ONLY0:       cond.false103:
61257 // SIMD-ONLY0-NEXT:    [[TMP108:%.*]] = load float, ptr [[FX]], align 4
61258 // SIMD-ONLY0-NEXT:    br label [[COND_END104]]
61259 // SIMD-ONLY0:       cond.end104:
61260 // SIMD-ONLY0-NEXT:    [[COND105:%.*]] = phi float [ [[TMP107]], [[COND_TRUE102]] ], [ [[TMP108]], [[COND_FALSE103]] ]
61261 // SIMD-ONLY0-NEXT:    store float [[COND105]], ptr [[FX]], align 4
61262 // SIMD-ONLY0-NEXT:    [[TMP109:%.*]] = load float, ptr [[FX]], align 4
61263 // SIMD-ONLY0-NEXT:    store float [[TMP109]], ptr [[FV]], align 4
61264 // SIMD-ONLY0-NEXT:    [[TMP110:%.*]] = load float, ptr [[FX]], align 4
61265 // SIMD-ONLY0-NEXT:    [[TMP111:%.*]] = load float, ptr [[FE]], align 4
61266 // SIMD-ONLY0-NEXT:    [[CMP106:%.*]] = fcmp olt float [[TMP110]], [[TMP111]]
61267 // SIMD-ONLY0-NEXT:    br i1 [[CMP106]], label [[COND_TRUE107:%.*]], label [[COND_FALSE108:%.*]]
61268 // SIMD-ONLY0:       cond.true107:
61269 // SIMD-ONLY0-NEXT:    [[TMP112:%.*]] = load float, ptr [[FE]], align 4
61270 // SIMD-ONLY0-NEXT:    br label [[COND_END109:%.*]]
61271 // SIMD-ONLY0:       cond.false108:
61272 // SIMD-ONLY0-NEXT:    [[TMP113:%.*]] = load float, ptr [[FX]], align 4
61273 // SIMD-ONLY0-NEXT:    br label [[COND_END109]]
61274 // SIMD-ONLY0:       cond.end109:
61275 // SIMD-ONLY0-NEXT:    [[COND110:%.*]] = phi float [ [[TMP112]], [[COND_TRUE107]] ], [ [[TMP113]], [[COND_FALSE108]] ]
61276 // SIMD-ONLY0-NEXT:    store float [[COND110]], ptr [[FX]], align 4
61277 // SIMD-ONLY0-NEXT:    [[TMP114:%.*]] = load float, ptr [[FX]], align 4
61278 // SIMD-ONLY0-NEXT:    store float [[TMP114]], ptr [[FV]], align 4
61279 // SIMD-ONLY0-NEXT:    [[TMP115:%.*]] = load float, ptr [[FX]], align 4
61280 // SIMD-ONLY0-NEXT:    [[TMP116:%.*]] = load float, ptr [[FE]], align 4
61281 // SIMD-ONLY0-NEXT:    [[CMP111:%.*]] = fcmp oeq float [[TMP115]], [[TMP116]]
61282 // SIMD-ONLY0-NEXT:    br i1 [[CMP111]], label [[COND_TRUE112:%.*]], label [[COND_FALSE113:%.*]]
61283 // SIMD-ONLY0:       cond.true112:
61284 // SIMD-ONLY0-NEXT:    [[TMP117:%.*]] = load float, ptr [[FD]], align 4
61285 // SIMD-ONLY0-NEXT:    br label [[COND_END114:%.*]]
61286 // SIMD-ONLY0:       cond.false113:
61287 // SIMD-ONLY0-NEXT:    [[TMP118:%.*]] = load float, ptr [[FX]], align 4
61288 // SIMD-ONLY0-NEXT:    br label [[COND_END114]]
61289 // SIMD-ONLY0:       cond.end114:
61290 // SIMD-ONLY0-NEXT:    [[COND115:%.*]] = phi float [ [[TMP117]], [[COND_TRUE112]] ], [ [[TMP118]], [[COND_FALSE113]] ]
61291 // SIMD-ONLY0-NEXT:    store float [[COND115]], ptr [[FX]], align 4
61292 // SIMD-ONLY0-NEXT:    [[TMP119:%.*]] = load float, ptr [[FX]], align 4
61293 // SIMD-ONLY0-NEXT:    store float [[TMP119]], ptr [[FV]], align 4
61294 // SIMD-ONLY0-NEXT:    [[TMP120:%.*]] = load float, ptr [[FX]], align 4
61295 // SIMD-ONLY0-NEXT:    store float [[TMP120]], ptr [[FV]], align 4
61296 // SIMD-ONLY0-NEXT:    [[TMP121:%.*]] = load float, ptr [[FX]], align 4
61297 // SIMD-ONLY0-NEXT:    [[TMP122:%.*]] = load float, ptr [[FE]], align 4
61298 // SIMD-ONLY0-NEXT:    [[CMP116:%.*]] = fcmp ogt float [[TMP121]], [[TMP122]]
61299 // SIMD-ONLY0-NEXT:    br i1 [[CMP116]], label [[COND_TRUE117:%.*]], label [[COND_FALSE118:%.*]]
61300 // SIMD-ONLY0:       cond.true117:
61301 // SIMD-ONLY0-NEXT:    [[TMP123:%.*]] = load float, ptr [[FE]], align 4
61302 // SIMD-ONLY0-NEXT:    br label [[COND_END119:%.*]]
61303 // SIMD-ONLY0:       cond.false118:
61304 // SIMD-ONLY0-NEXT:    [[TMP124:%.*]] = load float, ptr [[FX]], align 4
61305 // SIMD-ONLY0-NEXT:    br label [[COND_END119]]
61306 // SIMD-ONLY0:       cond.end119:
61307 // SIMD-ONLY0-NEXT:    [[COND120:%.*]] = phi float [ [[TMP123]], [[COND_TRUE117]] ], [ [[TMP124]], [[COND_FALSE118]] ]
61308 // SIMD-ONLY0-NEXT:    store float [[COND120]], ptr [[FX]], align 4
61309 // SIMD-ONLY0-NEXT:    [[TMP125:%.*]] = load float, ptr [[FX]], align 4
61310 // SIMD-ONLY0-NEXT:    store float [[TMP125]], ptr [[FV]], align 4
61311 // SIMD-ONLY0-NEXT:    [[TMP126:%.*]] = load float, ptr [[FX]], align 4
61312 // SIMD-ONLY0-NEXT:    [[TMP127:%.*]] = load float, ptr [[FE]], align 4
61313 // SIMD-ONLY0-NEXT:    [[CMP121:%.*]] = fcmp olt float [[TMP126]], [[TMP127]]
61314 // SIMD-ONLY0-NEXT:    br i1 [[CMP121]], label [[COND_TRUE122:%.*]], label [[COND_FALSE123:%.*]]
61315 // SIMD-ONLY0:       cond.true122:
61316 // SIMD-ONLY0-NEXT:    [[TMP128:%.*]] = load float, ptr [[FE]], align 4
61317 // SIMD-ONLY0-NEXT:    br label [[COND_END124:%.*]]
61318 // SIMD-ONLY0:       cond.false123:
61319 // SIMD-ONLY0-NEXT:    [[TMP129:%.*]] = load float, ptr [[FX]], align 4
61320 // SIMD-ONLY0-NEXT:    br label [[COND_END124]]
61321 // SIMD-ONLY0:       cond.end124:
61322 // SIMD-ONLY0-NEXT:    [[COND125:%.*]] = phi float [ [[TMP128]], [[COND_TRUE122]] ], [ [[TMP129]], [[COND_FALSE123]] ]
61323 // SIMD-ONLY0-NEXT:    store float [[COND125]], ptr [[FX]], align 4
61324 // SIMD-ONLY0-NEXT:    [[TMP130:%.*]] = load float, ptr [[FX]], align 4
61325 // SIMD-ONLY0-NEXT:    store float [[TMP130]], ptr [[FV]], align 4
61326 // SIMD-ONLY0-NEXT:    [[TMP131:%.*]] = load float, ptr [[FX]], align 4
61327 // SIMD-ONLY0-NEXT:    [[TMP132:%.*]] = load float, ptr [[FE]], align 4
61328 // SIMD-ONLY0-NEXT:    [[CMP126:%.*]] = fcmp oeq float [[TMP131]], [[TMP132]]
61329 // SIMD-ONLY0-NEXT:    br i1 [[CMP126]], label [[COND_TRUE127:%.*]], label [[COND_FALSE128:%.*]]
61330 // SIMD-ONLY0:       cond.true127:
61331 // SIMD-ONLY0-NEXT:    [[TMP133:%.*]] = load float, ptr [[FD]], align 4
61332 // SIMD-ONLY0-NEXT:    br label [[COND_END129:%.*]]
61333 // SIMD-ONLY0:       cond.false128:
61334 // SIMD-ONLY0-NEXT:    [[TMP134:%.*]] = load float, ptr [[FX]], align 4
61335 // SIMD-ONLY0-NEXT:    br label [[COND_END129]]
61336 // SIMD-ONLY0:       cond.end129:
61337 // SIMD-ONLY0-NEXT:    [[COND130:%.*]] = phi float [ [[TMP133]], [[COND_TRUE127]] ], [ [[TMP134]], [[COND_FALSE128]] ]
61338 // SIMD-ONLY0-NEXT:    store float [[COND130]], ptr [[FX]], align 4
61339 // SIMD-ONLY0-NEXT:    [[TMP135:%.*]] = load float, ptr [[FX]], align 4
61340 // SIMD-ONLY0-NEXT:    [[TMP136:%.*]] = load float, ptr [[FE]], align 4
61341 // SIMD-ONLY0-NEXT:    [[CMP131:%.*]] = fcmp ogt float [[TMP135]], [[TMP136]]
61342 // SIMD-ONLY0-NEXT:    br i1 [[CMP131]], label [[COND_TRUE132:%.*]], label [[COND_FALSE133:%.*]]
61343 // SIMD-ONLY0:       cond.true132:
61344 // SIMD-ONLY0-NEXT:    [[TMP137:%.*]] = load float, ptr [[FE]], align 4
61345 // SIMD-ONLY0-NEXT:    br label [[COND_END134:%.*]]
61346 // SIMD-ONLY0:       cond.false133:
61347 // SIMD-ONLY0-NEXT:    [[TMP138:%.*]] = load float, ptr [[FX]], align 4
61348 // SIMD-ONLY0-NEXT:    br label [[COND_END134]]
61349 // SIMD-ONLY0:       cond.end134:
61350 // SIMD-ONLY0-NEXT:    [[COND135:%.*]] = phi float [ [[TMP137]], [[COND_TRUE132]] ], [ [[TMP138]], [[COND_FALSE133]] ]
61351 // SIMD-ONLY0-NEXT:    store float [[COND135]], ptr [[FX]], align 4
61352 // SIMD-ONLY0-NEXT:    [[TMP139:%.*]] = load float, ptr [[FX]], align 4
61353 // SIMD-ONLY0-NEXT:    store float [[TMP139]], ptr [[FV]], align 4
61354 // SIMD-ONLY0-NEXT:    [[TMP140:%.*]] = load float, ptr [[FX]], align 4
61355 // SIMD-ONLY0-NEXT:    [[TMP141:%.*]] = load float, ptr [[FE]], align 4
61356 // SIMD-ONLY0-NEXT:    [[CMP136:%.*]] = fcmp olt float [[TMP140]], [[TMP141]]
61357 // SIMD-ONLY0-NEXT:    br i1 [[CMP136]], label [[COND_TRUE137:%.*]], label [[COND_FALSE138:%.*]]
61358 // SIMD-ONLY0:       cond.true137:
61359 // SIMD-ONLY0-NEXT:    [[TMP142:%.*]] = load float, ptr [[FE]], align 4
61360 // SIMD-ONLY0-NEXT:    br label [[COND_END139:%.*]]
61361 // SIMD-ONLY0:       cond.false138:
61362 // SIMD-ONLY0-NEXT:    [[TMP143:%.*]] = load float, ptr [[FX]], align 4
61363 // SIMD-ONLY0-NEXT:    br label [[COND_END139]]
61364 // SIMD-ONLY0:       cond.end139:
61365 // SIMD-ONLY0-NEXT:    [[COND140:%.*]] = phi float [ [[TMP142]], [[COND_TRUE137]] ], [ [[TMP143]], [[COND_FALSE138]] ]
61366 // SIMD-ONLY0-NEXT:    store float [[COND140]], ptr [[FX]], align 4
61367 // SIMD-ONLY0-NEXT:    [[TMP144:%.*]] = load float, ptr [[FX]], align 4
61368 // SIMD-ONLY0-NEXT:    store float [[TMP144]], ptr [[FV]], align 4
61369 // SIMD-ONLY0-NEXT:    [[TMP145:%.*]] = load float, ptr [[FX]], align 4
61370 // SIMD-ONLY0-NEXT:    [[TMP146:%.*]] = load float, ptr [[FE]], align 4
61371 // SIMD-ONLY0-NEXT:    [[CMP141:%.*]] = fcmp oeq float [[TMP145]], [[TMP146]]
61372 // SIMD-ONLY0-NEXT:    br i1 [[CMP141]], label [[COND_TRUE142:%.*]], label [[COND_FALSE143:%.*]]
61373 // SIMD-ONLY0:       cond.true142:
61374 // SIMD-ONLY0-NEXT:    [[TMP147:%.*]] = load float, ptr [[FD]], align 4
61375 // SIMD-ONLY0-NEXT:    br label [[COND_END144:%.*]]
61376 // SIMD-ONLY0:       cond.false143:
61377 // SIMD-ONLY0-NEXT:    [[TMP148:%.*]] = load float, ptr [[FX]], align 4
61378 // SIMD-ONLY0-NEXT:    br label [[COND_END144]]
61379 // SIMD-ONLY0:       cond.end144:
61380 // SIMD-ONLY0-NEXT:    [[COND145:%.*]] = phi float [ [[TMP147]], [[COND_TRUE142]] ], [ [[TMP148]], [[COND_FALSE143]] ]
61381 // SIMD-ONLY0-NEXT:    store float [[COND145]], ptr [[FX]], align 4
61382 // SIMD-ONLY0-NEXT:    [[TMP149:%.*]] = load float, ptr [[FX]], align 4
61383 // SIMD-ONLY0-NEXT:    store float [[TMP149]], ptr [[FV]], align 4
61384 // SIMD-ONLY0-NEXT:    [[TMP150:%.*]] = load float, ptr [[FX]], align 4
61385 // SIMD-ONLY0-NEXT:    store float [[TMP150]], ptr [[FV]], align 4
61386 // SIMD-ONLY0-NEXT:    [[TMP151:%.*]] = load float, ptr [[FX]], align 4
61387 // SIMD-ONLY0-NEXT:    [[TMP152:%.*]] = load float, ptr [[FE]], align 4
61388 // SIMD-ONLY0-NEXT:    [[CMP146:%.*]] = fcmp ogt float [[TMP151]], [[TMP152]]
61389 // SIMD-ONLY0-NEXT:    br i1 [[CMP146]], label [[COND_TRUE147:%.*]], label [[COND_FALSE148:%.*]]
61390 // SIMD-ONLY0:       cond.true147:
61391 // SIMD-ONLY0-NEXT:    [[TMP153:%.*]] = load float, ptr [[FE]], align 4
61392 // SIMD-ONLY0-NEXT:    br label [[COND_END149:%.*]]
61393 // SIMD-ONLY0:       cond.false148:
61394 // SIMD-ONLY0-NEXT:    [[TMP154:%.*]] = load float, ptr [[FX]], align 4
61395 // SIMD-ONLY0-NEXT:    br label [[COND_END149]]
61396 // SIMD-ONLY0:       cond.end149:
61397 // SIMD-ONLY0-NEXT:    [[COND150:%.*]] = phi float [ [[TMP153]], [[COND_TRUE147]] ], [ [[TMP154]], [[COND_FALSE148]] ]
61398 // SIMD-ONLY0-NEXT:    store float [[COND150]], ptr [[FX]], align 4
61399 // SIMD-ONLY0-NEXT:    [[TMP155:%.*]] = load float, ptr [[FX]], align 4
61400 // SIMD-ONLY0-NEXT:    store float [[TMP155]], ptr [[FV]], align 4
61401 // SIMD-ONLY0-NEXT:    [[TMP156:%.*]] = load float, ptr [[FX]], align 4
61402 // SIMD-ONLY0-NEXT:    [[TMP157:%.*]] = load float, ptr [[FE]], align 4
61403 // SIMD-ONLY0-NEXT:    [[CMP151:%.*]] = fcmp olt float [[TMP156]], [[TMP157]]
61404 // SIMD-ONLY0-NEXT:    br i1 [[CMP151]], label [[COND_TRUE152:%.*]], label [[COND_FALSE153:%.*]]
61405 // SIMD-ONLY0:       cond.true152:
61406 // SIMD-ONLY0-NEXT:    [[TMP158:%.*]] = load float, ptr [[FE]], align 4
61407 // SIMD-ONLY0-NEXT:    br label [[COND_END154:%.*]]
61408 // SIMD-ONLY0:       cond.false153:
61409 // SIMD-ONLY0-NEXT:    [[TMP159:%.*]] = load float, ptr [[FX]], align 4
61410 // SIMD-ONLY0-NEXT:    br label [[COND_END154]]
61411 // SIMD-ONLY0:       cond.end154:
61412 // SIMD-ONLY0-NEXT:    [[COND155:%.*]] = phi float [ [[TMP158]], [[COND_TRUE152]] ], [ [[TMP159]], [[COND_FALSE153]] ]
61413 // SIMD-ONLY0-NEXT:    store float [[COND155]], ptr [[FX]], align 4
61414 // SIMD-ONLY0-NEXT:    [[TMP160:%.*]] = load float, ptr [[FX]], align 4
61415 // SIMD-ONLY0-NEXT:    store float [[TMP160]], ptr [[FV]], align 4
61416 // SIMD-ONLY0-NEXT:    [[TMP161:%.*]] = load float, ptr [[FX]], align 4
61417 // SIMD-ONLY0-NEXT:    [[TMP162:%.*]] = load float, ptr [[FE]], align 4
61418 // SIMD-ONLY0-NEXT:    [[CMP156:%.*]] = fcmp oeq float [[TMP161]], [[TMP162]]
61419 // SIMD-ONLY0-NEXT:    br i1 [[CMP156]], label [[COND_TRUE157:%.*]], label [[COND_FALSE158:%.*]]
61420 // SIMD-ONLY0:       cond.true157:
61421 // SIMD-ONLY0-NEXT:    [[TMP163:%.*]] = load float, ptr [[FD]], align 4
61422 // SIMD-ONLY0-NEXT:    br label [[COND_END159:%.*]]
61423 // SIMD-ONLY0:       cond.false158:
61424 // SIMD-ONLY0-NEXT:    [[TMP164:%.*]] = load float, ptr [[FX]], align 4
61425 // SIMD-ONLY0-NEXT:    br label [[COND_END159]]
61426 // SIMD-ONLY0:       cond.end159:
61427 // SIMD-ONLY0-NEXT:    [[COND160:%.*]] = phi float [ [[TMP163]], [[COND_TRUE157]] ], [ [[TMP164]], [[COND_FALSE158]] ]
61428 // SIMD-ONLY0-NEXT:    store float [[COND160]], ptr [[FX]], align 4
61429 // SIMD-ONLY0-NEXT:    [[TMP165:%.*]] = load float, ptr [[FX]], align 4
61430 // SIMD-ONLY0-NEXT:    [[TMP166:%.*]] = load float, ptr [[FE]], align 4
61431 // SIMD-ONLY0-NEXT:    [[CMP161:%.*]] = fcmp ogt float [[TMP165]], [[TMP166]]
61432 // SIMD-ONLY0-NEXT:    br i1 [[CMP161]], label [[COND_TRUE162:%.*]], label [[COND_FALSE163:%.*]]
61433 // SIMD-ONLY0:       cond.true162:
61434 // SIMD-ONLY0-NEXT:    [[TMP167:%.*]] = load float, ptr [[FE]], align 4
61435 // SIMD-ONLY0-NEXT:    br label [[COND_END164:%.*]]
61436 // SIMD-ONLY0:       cond.false163:
61437 // SIMD-ONLY0-NEXT:    [[TMP168:%.*]] = load float, ptr [[FX]], align 4
61438 // SIMD-ONLY0-NEXT:    br label [[COND_END164]]
61439 // SIMD-ONLY0:       cond.end164:
61440 // SIMD-ONLY0-NEXT:    [[COND165:%.*]] = phi float [ [[TMP167]], [[COND_TRUE162]] ], [ [[TMP168]], [[COND_FALSE163]] ]
61441 // SIMD-ONLY0-NEXT:    store float [[COND165]], ptr [[FX]], align 4
61442 // SIMD-ONLY0-NEXT:    [[TMP169:%.*]] = load float, ptr [[FX]], align 4
61443 // SIMD-ONLY0-NEXT:    store float [[TMP169]], ptr [[FV]], align 4
61444 // SIMD-ONLY0-NEXT:    [[TMP170:%.*]] = load float, ptr [[FX]], align 4
61445 // SIMD-ONLY0-NEXT:    [[TMP171:%.*]] = load float, ptr [[FE]], align 4
61446 // SIMD-ONLY0-NEXT:    [[CMP166:%.*]] = fcmp olt float [[TMP170]], [[TMP171]]
61447 // SIMD-ONLY0-NEXT:    br i1 [[CMP166]], label [[COND_TRUE167:%.*]], label [[COND_FALSE168:%.*]]
61448 // SIMD-ONLY0:       cond.true167:
61449 // SIMD-ONLY0-NEXT:    [[TMP172:%.*]] = load float, ptr [[FE]], align 4
61450 // SIMD-ONLY0-NEXT:    br label [[COND_END169:%.*]]
61451 // SIMD-ONLY0:       cond.false168:
61452 // SIMD-ONLY0-NEXT:    [[TMP173:%.*]] = load float, ptr [[FX]], align 4
61453 // SIMD-ONLY0-NEXT:    br label [[COND_END169]]
61454 // SIMD-ONLY0:       cond.end169:
61455 // SIMD-ONLY0-NEXT:    [[COND170:%.*]] = phi float [ [[TMP172]], [[COND_TRUE167]] ], [ [[TMP173]], [[COND_FALSE168]] ]
61456 // SIMD-ONLY0-NEXT:    store float [[COND170]], ptr [[FX]], align 4
61457 // SIMD-ONLY0-NEXT:    [[TMP174:%.*]] = load float, ptr [[FX]], align 4
61458 // SIMD-ONLY0-NEXT:    store float [[TMP174]], ptr [[FV]], align 4
61459 // SIMD-ONLY0-NEXT:    [[TMP175:%.*]] = load float, ptr [[FX]], align 4
61460 // SIMD-ONLY0-NEXT:    [[TMP176:%.*]] = load float, ptr [[FE]], align 4
61461 // SIMD-ONLY0-NEXT:    [[CMP171:%.*]] = fcmp oeq float [[TMP175]], [[TMP176]]
61462 // SIMD-ONLY0-NEXT:    br i1 [[CMP171]], label [[COND_TRUE172:%.*]], label [[COND_FALSE173:%.*]]
61463 // SIMD-ONLY0:       cond.true172:
61464 // SIMD-ONLY0-NEXT:    [[TMP177:%.*]] = load float, ptr [[FD]], align 4
61465 // SIMD-ONLY0-NEXT:    br label [[COND_END174:%.*]]
61466 // SIMD-ONLY0:       cond.false173:
61467 // SIMD-ONLY0-NEXT:    [[TMP178:%.*]] = load float, ptr [[FX]], align 4
61468 // SIMD-ONLY0-NEXT:    br label [[COND_END174]]
61469 // SIMD-ONLY0:       cond.end174:
61470 // SIMD-ONLY0-NEXT:    [[COND175:%.*]] = phi float [ [[TMP177]], [[COND_TRUE172]] ], [ [[TMP178]], [[COND_FALSE173]] ]
61471 // SIMD-ONLY0-NEXT:    store float [[COND175]], ptr [[FX]], align 4
61472 // SIMD-ONLY0-NEXT:    [[TMP179:%.*]] = load float, ptr [[FX]], align 4
61473 // SIMD-ONLY0-NEXT:    store float [[TMP179]], ptr [[FV]], align 4
61474 // SIMD-ONLY0-NEXT:    [[TMP180:%.*]] = load float, ptr [[FV]], align 4
61475 // SIMD-ONLY0-NEXT:    ret float [[TMP180]]
61476 //
61477 //
61478 // SIMD-ONLY0-LABEL: @dxevd(
61479 // SIMD-ONLY0-NEXT:  entry:
61480 // SIMD-ONLY0-NEXT:    [[DX:%.*]] = alloca double, align 8
61481 // SIMD-ONLY0-NEXT:    [[DV:%.*]] = alloca double, align 8
61482 // SIMD-ONLY0-NEXT:    [[DE:%.*]] = alloca double, align 8
61483 // SIMD-ONLY0-NEXT:    [[DD:%.*]] = alloca double, align 8
61484 // SIMD-ONLY0-NEXT:    [[TMP0:%.*]] = load double, ptr [[DX]], align 8
61485 // SIMD-ONLY0-NEXT:    store double [[TMP0]], ptr [[DV]], align 8
61486 // SIMD-ONLY0-NEXT:    [[TMP1:%.*]] = load double, ptr [[DX]], align 8
61487 // SIMD-ONLY0-NEXT:    [[TMP2:%.*]] = load double, ptr [[DE]], align 8
61488 // SIMD-ONLY0-NEXT:    [[CMP:%.*]] = fcmp ogt double [[TMP1]], [[TMP2]]
61489 // SIMD-ONLY0-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
61490 // SIMD-ONLY0:       cond.true:
61491 // SIMD-ONLY0-NEXT:    [[TMP3:%.*]] = load double, ptr [[DE]], align 8
61492 // SIMD-ONLY0-NEXT:    br label [[COND_END:%.*]]
61493 // SIMD-ONLY0:       cond.false:
61494 // SIMD-ONLY0-NEXT:    [[TMP4:%.*]] = load double, ptr [[DX]], align 8
61495 // SIMD-ONLY0-NEXT:    br label [[COND_END]]
61496 // SIMD-ONLY0:       cond.end:
61497 // SIMD-ONLY0-NEXT:    [[COND:%.*]] = phi double [ [[TMP3]], [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
61498 // SIMD-ONLY0-NEXT:    store double [[COND]], ptr [[DX]], align 8
61499 // SIMD-ONLY0-NEXT:    [[TMP5:%.*]] = load double, ptr [[DX]], align 8
61500 // SIMD-ONLY0-NEXT:    store double [[TMP5]], ptr [[DV]], align 8
61501 // SIMD-ONLY0-NEXT:    [[TMP6:%.*]] = load double, ptr [[DX]], align 8
61502 // SIMD-ONLY0-NEXT:    [[TMP7:%.*]] = load double, ptr [[DE]], align 8
61503 // SIMD-ONLY0-NEXT:    [[CMP1:%.*]] = fcmp olt double [[TMP6]], [[TMP7]]
61504 // SIMD-ONLY0-NEXT:    br i1 [[CMP1]], label [[COND_TRUE2:%.*]], label [[COND_FALSE3:%.*]]
61505 // SIMD-ONLY0:       cond.true2:
61506 // SIMD-ONLY0-NEXT:    [[TMP8:%.*]] = load double, ptr [[DE]], align 8
61507 // SIMD-ONLY0-NEXT:    br label [[COND_END4:%.*]]
61508 // SIMD-ONLY0:       cond.false3:
61509 // SIMD-ONLY0-NEXT:    [[TMP9:%.*]] = load double, ptr [[DX]], align 8
61510 // SIMD-ONLY0-NEXT:    br label [[COND_END4]]
61511 // SIMD-ONLY0:       cond.end4:
61512 // SIMD-ONLY0-NEXT:    [[COND5:%.*]] = phi double [ [[TMP8]], [[COND_TRUE2]] ], [ [[TMP9]], [[COND_FALSE3]] ]
61513 // SIMD-ONLY0-NEXT:    store double [[COND5]], ptr [[DX]], align 8
61514 // SIMD-ONLY0-NEXT:    [[TMP10:%.*]] = load double, ptr [[DX]], align 8
61515 // SIMD-ONLY0-NEXT:    store double [[TMP10]], ptr [[DV]], align 8
61516 // SIMD-ONLY0-NEXT:    [[TMP11:%.*]] = load double, ptr [[DX]], align 8
61517 // SIMD-ONLY0-NEXT:    [[TMP12:%.*]] = load double, ptr [[DE]], align 8
61518 // SIMD-ONLY0-NEXT:    [[CMP6:%.*]] = fcmp oeq double [[TMP11]], [[TMP12]]
61519 // SIMD-ONLY0-NEXT:    br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
61520 // SIMD-ONLY0:       cond.true7:
61521 // SIMD-ONLY0-NEXT:    [[TMP13:%.*]] = load double, ptr [[DD]], align 8
61522 // SIMD-ONLY0-NEXT:    br label [[COND_END9:%.*]]
61523 // SIMD-ONLY0:       cond.false8:
61524 // SIMD-ONLY0-NEXT:    [[TMP14:%.*]] = load double, ptr [[DX]], align 8
61525 // SIMD-ONLY0-NEXT:    br label [[COND_END9]]
61526 // SIMD-ONLY0:       cond.end9:
61527 // SIMD-ONLY0-NEXT:    [[COND10:%.*]] = phi double [ [[TMP13]], [[COND_TRUE7]] ], [ [[TMP14]], [[COND_FALSE8]] ]
61528 // SIMD-ONLY0-NEXT:    store double [[COND10]], ptr [[DX]], align 8
61529 // SIMD-ONLY0-NEXT:    [[TMP15:%.*]] = load double, ptr [[DX]], align 8
61530 // SIMD-ONLY0-NEXT:    [[TMP16:%.*]] = load double, ptr [[DE]], align 8
61531 // SIMD-ONLY0-NEXT:    [[CMP11:%.*]] = fcmp ogt double [[TMP15]], [[TMP16]]
61532 // SIMD-ONLY0-NEXT:    br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
61533 // SIMD-ONLY0:       cond.true12:
61534 // SIMD-ONLY0-NEXT:    [[TMP17:%.*]] = load double, ptr [[DE]], align 8
61535 // SIMD-ONLY0-NEXT:    br label [[COND_END14:%.*]]
61536 // SIMD-ONLY0:       cond.false13:
61537 // SIMD-ONLY0-NEXT:    [[TMP18:%.*]] = load double, ptr [[DX]], align 8
61538 // SIMD-ONLY0-NEXT:    br label [[COND_END14]]
61539 // SIMD-ONLY0:       cond.end14:
61540 // SIMD-ONLY0-NEXT:    [[COND15:%.*]] = phi double [ [[TMP17]], [[COND_TRUE12]] ], [ [[TMP18]], [[COND_FALSE13]] ]
61541 // SIMD-ONLY0-NEXT:    store double [[COND15]], ptr [[DX]], align 8
61542 // SIMD-ONLY0-NEXT:    [[TMP19:%.*]] = load double, ptr [[DX]], align 8
61543 // SIMD-ONLY0-NEXT:    store double [[TMP19]], ptr [[DV]], align 8
61544 // SIMD-ONLY0-NEXT:    [[TMP20:%.*]] = load double, ptr [[DX]], align 8
61545 // SIMD-ONLY0-NEXT:    [[TMP21:%.*]] = load double, ptr [[DE]], align 8
61546 // SIMD-ONLY0-NEXT:    [[CMP16:%.*]] = fcmp olt double [[TMP20]], [[TMP21]]
61547 // SIMD-ONLY0-NEXT:    br i1 [[CMP16]], label [[COND_TRUE17:%.*]], label [[COND_FALSE18:%.*]]
61548 // SIMD-ONLY0:       cond.true17:
61549 // SIMD-ONLY0-NEXT:    [[TMP22:%.*]] = load double, ptr [[DE]], align 8
61550 // SIMD-ONLY0-NEXT:    br label [[COND_END19:%.*]]
61551 // SIMD-ONLY0:       cond.false18:
61552 // SIMD-ONLY0-NEXT:    [[TMP23:%.*]] = load double, ptr [[DX]], align 8
61553 // SIMD-ONLY0-NEXT:    br label [[COND_END19]]
61554 // SIMD-ONLY0:       cond.end19:
61555 // SIMD-ONLY0-NEXT:    [[COND20:%.*]] = phi double [ [[TMP22]], [[COND_TRUE17]] ], [ [[TMP23]], [[COND_FALSE18]] ]
61556 // SIMD-ONLY0-NEXT:    store double [[COND20]], ptr [[DX]], align 8
61557 // SIMD-ONLY0-NEXT:    [[TMP24:%.*]] = load double, ptr [[DX]], align 8
61558 // SIMD-ONLY0-NEXT:    store double [[TMP24]], ptr [[DV]], align 8
61559 // SIMD-ONLY0-NEXT:    [[TMP25:%.*]] = load double, ptr [[DX]], align 8
61560 // SIMD-ONLY0-NEXT:    [[TMP26:%.*]] = load double, ptr [[DE]], align 8
61561 // SIMD-ONLY0-NEXT:    [[CMP21:%.*]] = fcmp oeq double [[TMP25]], [[TMP26]]
61562 // SIMD-ONLY0-NEXT:    br i1 [[CMP21]], label [[COND_TRUE22:%.*]], label [[COND_FALSE23:%.*]]
61563 // SIMD-ONLY0:       cond.true22:
61564 // SIMD-ONLY0-NEXT:    [[TMP27:%.*]] = load double, ptr [[DD]], align 8
61565 // SIMD-ONLY0-NEXT:    br label [[COND_END24:%.*]]
61566 // SIMD-ONLY0:       cond.false23:
61567 // SIMD-ONLY0-NEXT:    [[TMP28:%.*]] = load double, ptr [[DX]], align 8
61568 // SIMD-ONLY0-NEXT:    br label [[COND_END24]]
61569 // SIMD-ONLY0:       cond.end24:
61570 // SIMD-ONLY0-NEXT:    [[COND25:%.*]] = phi double [ [[TMP27]], [[COND_TRUE22]] ], [ [[TMP28]], [[COND_FALSE23]] ]
61571 // SIMD-ONLY0-NEXT:    store double [[COND25]], ptr [[DX]], align 8
61572 // SIMD-ONLY0-NEXT:    [[TMP29:%.*]] = load double, ptr [[DX]], align 8
61573 // SIMD-ONLY0-NEXT:    store double [[TMP29]], ptr [[DV]], align 8
61574 // SIMD-ONLY0-NEXT:    [[TMP30:%.*]] = load double, ptr [[DX]], align 8
61575 // SIMD-ONLY0-NEXT:    store double [[TMP30]], ptr [[DV]], align 8
61576 // SIMD-ONLY0-NEXT:    [[TMP31:%.*]] = load double, ptr [[DX]], align 8
61577 // SIMD-ONLY0-NEXT:    [[TMP32:%.*]] = load double, ptr [[DE]], align 8
61578 // SIMD-ONLY0-NEXT:    [[CMP26:%.*]] = fcmp ogt double [[TMP31]], [[TMP32]]
61579 // SIMD-ONLY0-NEXT:    br i1 [[CMP26]], label [[COND_TRUE27:%.*]], label [[COND_FALSE28:%.*]]
61580 // SIMD-ONLY0:       cond.true27:
61581 // SIMD-ONLY0-NEXT:    [[TMP33:%.*]] = load double, ptr [[DE]], align 8
61582 // SIMD-ONLY0-NEXT:    br label [[COND_END29:%.*]]
61583 // SIMD-ONLY0:       cond.false28:
61584 // SIMD-ONLY0-NEXT:    [[TMP34:%.*]] = load double, ptr [[DX]], align 8
61585 // SIMD-ONLY0-NEXT:    br label [[COND_END29]]
61586 // SIMD-ONLY0:       cond.end29:
61587 // SIMD-ONLY0-NEXT:    [[COND30:%.*]] = phi double [ [[TMP33]], [[COND_TRUE27]] ], [ [[TMP34]], [[COND_FALSE28]] ]
61588 // SIMD-ONLY0-NEXT:    store double [[COND30]], ptr [[DX]], align 8
61589 // SIMD-ONLY0-NEXT:    [[TMP35:%.*]] = load double, ptr [[DX]], align 8
61590 // SIMD-ONLY0-NEXT:    store double [[TMP35]], ptr [[DV]], align 8
61591 // SIMD-ONLY0-NEXT:    [[TMP36:%.*]] = load double, ptr [[DX]], align 8
61592 // SIMD-ONLY0-NEXT:    [[TMP37:%.*]] = load double, ptr [[DE]], align 8
61593 // SIMD-ONLY0-NEXT:    [[CMP31:%.*]] = fcmp olt double [[TMP36]], [[TMP37]]
61594 // SIMD-ONLY0-NEXT:    br i1 [[CMP31]], label [[COND_TRUE32:%.*]], label [[COND_FALSE33:%.*]]
61595 // SIMD-ONLY0:       cond.true32:
61596 // SIMD-ONLY0-NEXT:    [[TMP38:%.*]] = load double, ptr [[DE]], align 8
61597 // SIMD-ONLY0-NEXT:    br label [[COND_END34:%.*]]
61598 // SIMD-ONLY0:       cond.false33:
61599 // SIMD-ONLY0-NEXT:    [[TMP39:%.*]] = load double, ptr [[DX]], align 8
61600 // SIMD-ONLY0-NEXT:    br label [[COND_END34]]
61601 // SIMD-ONLY0:       cond.end34:
61602 // SIMD-ONLY0-NEXT:    [[COND35:%.*]] = phi double [ [[TMP38]], [[COND_TRUE32]] ], [ [[TMP39]], [[COND_FALSE33]] ]
61603 // SIMD-ONLY0-NEXT:    store double [[COND35]], ptr [[DX]], align 8
61604 // SIMD-ONLY0-NEXT:    [[TMP40:%.*]] = load double, ptr [[DX]], align 8
61605 // SIMD-ONLY0-NEXT:    store double [[TMP40]], ptr [[DV]], align 8
61606 // SIMD-ONLY0-NEXT:    [[TMP41:%.*]] = load double, ptr [[DX]], align 8
61607 // SIMD-ONLY0-NEXT:    [[TMP42:%.*]] = load double, ptr [[DE]], align 8
61608 // SIMD-ONLY0-NEXT:    [[CMP36:%.*]] = fcmp oeq double [[TMP41]], [[TMP42]]
61609 // SIMD-ONLY0-NEXT:    br i1 [[CMP36]], label [[COND_TRUE37:%.*]], label [[COND_FALSE38:%.*]]
61610 // SIMD-ONLY0:       cond.true37:
61611 // SIMD-ONLY0-NEXT:    [[TMP43:%.*]] = load double, ptr [[DD]], align 8
61612 // SIMD-ONLY0-NEXT:    br label [[COND_END39:%.*]]
61613 // SIMD-ONLY0:       cond.false38:
61614 // SIMD-ONLY0-NEXT:    [[TMP44:%.*]] = load double, ptr [[DX]], align 8
61615 // SIMD-ONLY0-NEXT:    br label [[COND_END39]]
61616 // SIMD-ONLY0:       cond.end39:
61617 // SIMD-ONLY0-NEXT:    [[COND40:%.*]] = phi double [ [[TMP43]], [[COND_TRUE37]] ], [ [[TMP44]], [[COND_FALSE38]] ]
61618 // SIMD-ONLY0-NEXT:    store double [[COND40]], ptr [[DX]], align 8
61619 // SIMD-ONLY0-NEXT:    [[TMP45:%.*]] = load double, ptr [[DX]], align 8
61620 // SIMD-ONLY0-NEXT:    [[TMP46:%.*]] = load double, ptr [[DE]], align 8
61621 // SIMD-ONLY0-NEXT:    [[CMP41:%.*]] = fcmp ogt double [[TMP45]], [[TMP46]]
61622 // SIMD-ONLY0-NEXT:    br i1 [[CMP41]], label [[COND_TRUE42:%.*]], label [[COND_FALSE43:%.*]]
61623 // SIMD-ONLY0:       cond.true42:
61624 // SIMD-ONLY0-NEXT:    [[TMP47:%.*]] = load double, ptr [[DE]], align 8
61625 // SIMD-ONLY0-NEXT:    br label [[COND_END44:%.*]]
61626 // SIMD-ONLY0:       cond.false43:
61627 // SIMD-ONLY0-NEXT:    [[TMP48:%.*]] = load double, ptr [[DX]], align 8
61628 // SIMD-ONLY0-NEXT:    br label [[COND_END44]]
61629 // SIMD-ONLY0:       cond.end44:
61630 // SIMD-ONLY0-NEXT:    [[COND45:%.*]] = phi double [ [[TMP47]], [[COND_TRUE42]] ], [ [[TMP48]], [[COND_FALSE43]] ]
61631 // SIMD-ONLY0-NEXT:    store double [[COND45]], ptr [[DX]], align 8
61632 // SIMD-ONLY0-NEXT:    [[TMP49:%.*]] = load double, ptr [[DX]], align 8
61633 // SIMD-ONLY0-NEXT:    store double [[TMP49]], ptr [[DV]], align 8
61634 // SIMD-ONLY0-NEXT:    [[TMP50:%.*]] = load double, ptr [[DX]], align 8
61635 // SIMD-ONLY0-NEXT:    [[TMP51:%.*]] = load double, ptr [[DE]], align 8
61636 // SIMD-ONLY0-NEXT:    [[CMP46:%.*]] = fcmp olt double [[TMP50]], [[TMP51]]
61637 // SIMD-ONLY0-NEXT:    br i1 [[CMP46]], label [[COND_TRUE47:%.*]], label [[COND_FALSE48:%.*]]
61638 // SIMD-ONLY0:       cond.true47:
61639 // SIMD-ONLY0-NEXT:    [[TMP52:%.*]] = load double, ptr [[DE]], align 8
61640 // SIMD-ONLY0-NEXT:    br label [[COND_END49:%.*]]
61641 // SIMD-ONLY0:       cond.false48:
61642 // SIMD-ONLY0-NEXT:    [[TMP53:%.*]] = load double, ptr [[DX]], align 8
61643 // SIMD-ONLY0-NEXT:    br label [[COND_END49]]
61644 // SIMD-ONLY0:       cond.end49:
61645 // SIMD-ONLY0-NEXT:    [[COND50:%.*]] = phi double [ [[TMP52]], [[COND_TRUE47]] ], [ [[TMP53]], [[COND_FALSE48]] ]
61646 // SIMD-ONLY0-NEXT:    store double [[COND50]], ptr [[DX]], align 8
61647 // SIMD-ONLY0-NEXT:    [[TMP54:%.*]] = load double, ptr [[DX]], align 8
61648 // SIMD-ONLY0-NEXT:    store double [[TMP54]], ptr [[DV]], align 8
61649 // SIMD-ONLY0-NEXT:    [[TMP55:%.*]] = load double, ptr [[DX]], align 8
61650 // SIMD-ONLY0-NEXT:    [[TMP56:%.*]] = load double, ptr [[DE]], align 8
61651 // SIMD-ONLY0-NEXT:    [[CMP51:%.*]] = fcmp oeq double [[TMP55]], [[TMP56]]
61652 // SIMD-ONLY0-NEXT:    br i1 [[CMP51]], label [[COND_TRUE52:%.*]], label [[COND_FALSE53:%.*]]
61653 // SIMD-ONLY0:       cond.true52:
61654 // SIMD-ONLY0-NEXT:    [[TMP57:%.*]] = load double, ptr [[DD]], align 8
61655 // SIMD-ONLY0-NEXT:    br label [[COND_END54:%.*]]
61656 // SIMD-ONLY0:       cond.false53:
61657 // SIMD-ONLY0-NEXT:    [[TMP58:%.*]] = load double, ptr [[DX]], align 8
61658 // SIMD-ONLY0-NEXT:    br label [[COND_END54]]
61659 // SIMD-ONLY0:       cond.end54:
61660 // SIMD-ONLY0-NEXT:    [[COND55:%.*]] = phi double [ [[TMP57]], [[COND_TRUE52]] ], [ [[TMP58]], [[COND_FALSE53]] ]
61661 // SIMD-ONLY0-NEXT:    store double [[COND55]], ptr [[DX]], align 8
61662 // SIMD-ONLY0-NEXT:    [[TMP59:%.*]] = load double, ptr [[DX]], align 8
61663 // SIMD-ONLY0-NEXT:    store double [[TMP59]], ptr [[DV]], align 8
61664 // SIMD-ONLY0-NEXT:    [[TMP60:%.*]] = load double, ptr [[DX]], align 8
61665 // SIMD-ONLY0-NEXT:    store double [[TMP60]], ptr [[DV]], align 8
61666 // SIMD-ONLY0-NEXT:    [[TMP61:%.*]] = load double, ptr [[DX]], align 8
61667 // SIMD-ONLY0-NEXT:    [[TMP62:%.*]] = load double, ptr [[DE]], align 8
61668 // SIMD-ONLY0-NEXT:    [[CMP56:%.*]] = fcmp ogt double [[TMP61]], [[TMP62]]
61669 // SIMD-ONLY0-NEXT:    br i1 [[CMP56]], label [[COND_TRUE57:%.*]], label [[COND_FALSE58:%.*]]
61670 // SIMD-ONLY0:       cond.true57:
61671 // SIMD-ONLY0-NEXT:    [[TMP63:%.*]] = load double, ptr [[DE]], align 8
61672 // SIMD-ONLY0-NEXT:    br label [[COND_END59:%.*]]
61673 // SIMD-ONLY0:       cond.false58:
61674 // SIMD-ONLY0-NEXT:    [[TMP64:%.*]] = load double, ptr [[DX]], align 8
61675 // SIMD-ONLY0-NEXT:    br label [[COND_END59]]
61676 // SIMD-ONLY0:       cond.end59:
61677 // SIMD-ONLY0-NEXT:    [[COND60:%.*]] = phi double [ [[TMP63]], [[COND_TRUE57]] ], [ [[TMP64]], [[COND_FALSE58]] ]
61678 // SIMD-ONLY0-NEXT:    store double [[COND60]], ptr [[DX]], align 8
61679 // SIMD-ONLY0-NEXT:    [[TMP65:%.*]] = load double, ptr [[DX]], align 8
61680 // SIMD-ONLY0-NEXT:    store double [[TMP65]], ptr [[DV]], align 8
61681 // SIMD-ONLY0-NEXT:    [[TMP66:%.*]] = load double, ptr [[DX]], align 8
61682 // SIMD-ONLY0-NEXT:    [[TMP67:%.*]] = load double, ptr [[DE]], align 8
61683 // SIMD-ONLY0-NEXT:    [[CMP61:%.*]] = fcmp olt double [[TMP66]], [[TMP67]]
61684 // SIMD-ONLY0-NEXT:    br i1 [[CMP61]], label [[COND_TRUE62:%.*]], label [[COND_FALSE63:%.*]]
61685 // SIMD-ONLY0:       cond.true62:
61686 // SIMD-ONLY0-NEXT:    [[TMP68:%.*]] = load double, ptr [[DE]], align 8
61687 // SIMD-ONLY0-NEXT:    br label [[COND_END64:%.*]]
61688 // SIMD-ONLY0:       cond.false63:
61689 // SIMD-ONLY0-NEXT:    [[TMP69:%.*]] = load double, ptr [[DX]], align 8
61690 // SIMD-ONLY0-NEXT:    br label [[COND_END64]]
61691 // SIMD-ONLY0:       cond.end64:
61692 // SIMD-ONLY0-NEXT:    [[COND65:%.*]] = phi double [ [[TMP68]], [[COND_TRUE62]] ], [ [[TMP69]], [[COND_FALSE63]] ]
61693 // SIMD-ONLY0-NEXT:    store double [[COND65]], ptr [[DX]], align 8
61694 // SIMD-ONLY0-NEXT:    [[TMP70:%.*]] = load double, ptr [[DX]], align 8
61695 // SIMD-ONLY0-NEXT:    store double [[TMP70]], ptr [[DV]], align 8
61696 // SIMD-ONLY0-NEXT:    [[TMP71:%.*]] = load double, ptr [[DX]], align 8
61697 // SIMD-ONLY0-NEXT:    [[TMP72:%.*]] = load double, ptr [[DE]], align 8
61698 // SIMD-ONLY0-NEXT:    [[CMP66:%.*]] = fcmp oeq double [[TMP71]], [[TMP72]]
61699 // SIMD-ONLY0-NEXT:    br i1 [[CMP66]], label [[COND_TRUE67:%.*]], label [[COND_FALSE68:%.*]]
61700 // SIMD-ONLY0:       cond.true67:
61701 // SIMD-ONLY0-NEXT:    [[TMP73:%.*]] = load double, ptr [[DD]], align 8
61702 // SIMD-ONLY0-NEXT:    br label [[COND_END69:%.*]]
61703 // SIMD-ONLY0:       cond.false68:
61704 // SIMD-ONLY0-NEXT:    [[TMP74:%.*]] = load double, ptr [[DX]], align 8
61705 // SIMD-ONLY0-NEXT:    br label [[COND_END69]]
61706 // SIMD-ONLY0:       cond.end69:
61707 // SIMD-ONLY0-NEXT:    [[COND70:%.*]] = phi double [ [[TMP73]], [[COND_TRUE67]] ], [ [[TMP74]], [[COND_FALSE68]] ]
61708 // SIMD-ONLY0-NEXT:    store double [[COND70]], ptr [[DX]], align 8
61709 // SIMD-ONLY0-NEXT:    [[TMP75:%.*]] = load double, ptr [[DX]], align 8
61710 // SIMD-ONLY0-NEXT:    [[TMP76:%.*]] = load double, ptr [[DE]], align 8
61711 // SIMD-ONLY0-NEXT:    [[CMP71:%.*]] = fcmp ogt double [[TMP75]], [[TMP76]]
61712 // SIMD-ONLY0-NEXT:    br i1 [[CMP71]], label [[COND_TRUE72:%.*]], label [[COND_FALSE73:%.*]]
61713 // SIMD-ONLY0:       cond.true72:
61714 // SIMD-ONLY0-NEXT:    [[TMP77:%.*]] = load double, ptr [[DE]], align 8
61715 // SIMD-ONLY0-NEXT:    br label [[COND_END74:%.*]]
61716 // SIMD-ONLY0:       cond.false73:
61717 // SIMD-ONLY0-NEXT:    [[TMP78:%.*]] = load double, ptr [[DX]], align 8
61718 // SIMD-ONLY0-NEXT:    br label [[COND_END74]]
61719 // SIMD-ONLY0:       cond.end74:
61720 // SIMD-ONLY0-NEXT:    [[COND75:%.*]] = phi double [ [[TMP77]], [[COND_TRUE72]] ], [ [[TMP78]], [[COND_FALSE73]] ]
61721 // SIMD-ONLY0-NEXT:    store double [[COND75]], ptr [[DX]], align 8
61722 // SIMD-ONLY0-NEXT:    [[TMP79:%.*]] = load double, ptr [[DX]], align 8
61723 // SIMD-ONLY0-NEXT:    store double [[TMP79]], ptr [[DV]], align 8
61724 // SIMD-ONLY0-NEXT:    [[TMP80:%.*]] = load double, ptr [[DX]], align 8
61725 // SIMD-ONLY0-NEXT:    [[TMP81:%.*]] = load double, ptr [[DE]], align 8
61726 // SIMD-ONLY0-NEXT:    [[CMP76:%.*]] = fcmp olt double [[TMP80]], [[TMP81]]
61727 // SIMD-ONLY0-NEXT:    br i1 [[CMP76]], label [[COND_TRUE77:%.*]], label [[COND_FALSE78:%.*]]
61728 // SIMD-ONLY0:       cond.true77:
61729 // SIMD-ONLY0-NEXT:    [[TMP82:%.*]] = load double, ptr [[DE]], align 8
61730 // SIMD-ONLY0-NEXT:    br label [[COND_END79:%.*]]
61731 // SIMD-ONLY0:       cond.false78:
61732 // SIMD-ONLY0-NEXT:    [[TMP83:%.*]] = load double, ptr [[DX]], align 8
61733 // SIMD-ONLY0-NEXT:    br label [[COND_END79]]
61734 // SIMD-ONLY0:       cond.end79:
61735 // SIMD-ONLY0-NEXT:    [[COND80:%.*]] = phi double [ [[TMP82]], [[COND_TRUE77]] ], [ [[TMP83]], [[COND_FALSE78]] ]
61736 // SIMD-ONLY0-NEXT:    store double [[COND80]], ptr [[DX]], align 8
61737 // SIMD-ONLY0-NEXT:    [[TMP84:%.*]] = load double, ptr [[DX]], align 8
61738 // SIMD-ONLY0-NEXT:    store double [[TMP84]], ptr [[DV]], align 8
61739 // SIMD-ONLY0-NEXT:    [[TMP85:%.*]] = load double, ptr [[DX]], align 8
61740 // SIMD-ONLY0-NEXT:    [[TMP86:%.*]] = load double, ptr [[DE]], align 8
61741 // SIMD-ONLY0-NEXT:    [[CMP81:%.*]] = fcmp oeq double [[TMP85]], [[TMP86]]
61742 // SIMD-ONLY0-NEXT:    br i1 [[CMP81]], label [[COND_TRUE82:%.*]], label [[COND_FALSE83:%.*]]
61743 // SIMD-ONLY0:       cond.true82:
61744 // SIMD-ONLY0-NEXT:    [[TMP87:%.*]] = load double, ptr [[DD]], align 8
61745 // SIMD-ONLY0-NEXT:    br label [[COND_END84:%.*]]
61746 // SIMD-ONLY0:       cond.false83:
61747 // SIMD-ONLY0-NEXT:    [[TMP88:%.*]] = load double, ptr [[DX]], align 8
61748 // SIMD-ONLY0-NEXT:    br label [[COND_END84]]
61749 // SIMD-ONLY0:       cond.end84:
61750 // SIMD-ONLY0-NEXT:    [[COND85:%.*]] = phi double [ [[TMP87]], [[COND_TRUE82]] ], [ [[TMP88]], [[COND_FALSE83]] ]
61751 // SIMD-ONLY0-NEXT:    store double [[COND85]], ptr [[DX]], align 8
61752 // SIMD-ONLY0-NEXT:    [[TMP89:%.*]] = load double, ptr [[DX]], align 8
61753 // SIMD-ONLY0-NEXT:    store double [[TMP89]], ptr [[DV]], align 8
61754 // SIMD-ONLY0-NEXT:    [[TMP90:%.*]] = load double, ptr [[DX]], align 8
61755 // SIMD-ONLY0-NEXT:    store double [[TMP90]], ptr [[DV]], align 8
61756 // SIMD-ONLY0-NEXT:    [[TMP91:%.*]] = load double, ptr [[DX]], align 8
61757 // SIMD-ONLY0-NEXT:    [[TMP92:%.*]] = load double, ptr [[DE]], align 8
61758 // SIMD-ONLY0-NEXT:    [[CMP86:%.*]] = fcmp ogt double [[TMP91]], [[TMP92]]
61759 // SIMD-ONLY0-NEXT:    br i1 [[CMP86]], label [[COND_TRUE87:%.*]], label [[COND_FALSE88:%.*]]
61760 // SIMD-ONLY0:       cond.true87:
61761 // SIMD-ONLY0-NEXT:    [[TMP93:%.*]] = load double, ptr [[DE]], align 8
61762 // SIMD-ONLY0-NEXT:    br label [[COND_END89:%.*]]
61763 // SIMD-ONLY0:       cond.false88:
61764 // SIMD-ONLY0-NEXT:    [[TMP94:%.*]] = load double, ptr [[DX]], align 8
61765 // SIMD-ONLY0-NEXT:    br label [[COND_END89]]
61766 // SIMD-ONLY0:       cond.end89:
61767 // SIMD-ONLY0-NEXT:    [[COND90:%.*]] = phi double [ [[TMP93]], [[COND_TRUE87]] ], [ [[TMP94]], [[COND_FALSE88]] ]
61768 // SIMD-ONLY0-NEXT:    store double [[COND90]], ptr [[DX]], align 8
61769 // SIMD-ONLY0-NEXT:    [[TMP95:%.*]] = load double, ptr [[DX]], align 8
61770 // SIMD-ONLY0-NEXT:    store double [[TMP95]], ptr [[DV]], align 8
61771 // SIMD-ONLY0-NEXT:    [[TMP96:%.*]] = load double, ptr [[DX]], align 8
61772 // SIMD-ONLY0-NEXT:    [[TMP97:%.*]] = load double, ptr [[DE]], align 8
61773 // SIMD-ONLY0-NEXT:    [[CMP91:%.*]] = fcmp olt double [[TMP96]], [[TMP97]]
61774 // SIMD-ONLY0-NEXT:    br i1 [[CMP91]], label [[COND_TRUE92:%.*]], label [[COND_FALSE93:%.*]]
61775 // SIMD-ONLY0:       cond.true92:
61776 // SIMD-ONLY0-NEXT:    [[TMP98:%.*]] = load double, ptr [[DE]], align 8
61777 // SIMD-ONLY0-NEXT:    br label [[COND_END94:%.*]]
61778 // SIMD-ONLY0:       cond.false93:
61779 // SIMD-ONLY0-NEXT:    [[TMP99:%.*]] = load double, ptr [[DX]], align 8
61780 // SIMD-ONLY0-NEXT:    br label [[COND_END94]]
61781 // SIMD-ONLY0:       cond.end94:
61782 // SIMD-ONLY0-NEXT:    [[COND95:%.*]] = phi double [ [[TMP98]], [[COND_TRUE92]] ], [ [[TMP99]], [[COND_FALSE93]] ]
61783 // SIMD-ONLY0-NEXT:    store double [[COND95]], ptr [[DX]], align 8
61784 // SIMD-ONLY0-NEXT:    [[TMP100:%.*]] = load double, ptr [[DX]], align 8
61785 // SIMD-ONLY0-NEXT:    store double [[TMP100]], ptr [[DV]], align 8
61786 // SIMD-ONLY0-NEXT:    [[TMP101:%.*]] = load double, ptr [[DX]], align 8
61787 // SIMD-ONLY0-NEXT:    [[TMP102:%.*]] = load double, ptr [[DE]], align 8
61788 // SIMD-ONLY0-NEXT:    [[CMP96:%.*]] = fcmp oeq double [[TMP101]], [[TMP102]]
61789 // SIMD-ONLY0-NEXT:    br i1 [[CMP96]], label [[COND_TRUE97:%.*]], label [[COND_FALSE98:%.*]]
61790 // SIMD-ONLY0:       cond.true97:
61791 // SIMD-ONLY0-NEXT:    [[TMP103:%.*]] = load double, ptr [[DD]], align 8
61792 // SIMD-ONLY0-NEXT:    br label [[COND_END99:%.*]]
61793 // SIMD-ONLY0:       cond.false98:
61794 // SIMD-ONLY0-NEXT:    [[TMP104:%.*]] = load double, ptr [[DX]], align 8
61795 // SIMD-ONLY0-NEXT:    br label [[COND_END99]]
61796 // SIMD-ONLY0:       cond.end99:
61797 // SIMD-ONLY0-NEXT:    [[COND100:%.*]] = phi double [ [[TMP103]], [[COND_TRUE97]] ], [ [[TMP104]], [[COND_FALSE98]] ]
61798 // SIMD-ONLY0-NEXT:    store double [[COND100]], ptr [[DX]], align 8
61799 // SIMD-ONLY0-NEXT:    [[TMP105:%.*]] = load double, ptr [[DX]], align 8
61800 // SIMD-ONLY0-NEXT:    [[TMP106:%.*]] = load double, ptr [[DE]], align 8
61801 // SIMD-ONLY0-NEXT:    [[CMP101:%.*]] = fcmp ogt double [[TMP105]], [[TMP106]]
61802 // SIMD-ONLY0-NEXT:    br i1 [[CMP101]], label [[COND_TRUE102:%.*]], label [[COND_FALSE103:%.*]]
61803 // SIMD-ONLY0:       cond.true102:
61804 // SIMD-ONLY0-NEXT:    [[TMP107:%.*]] = load double, ptr [[DE]], align 8
61805 // SIMD-ONLY0-NEXT:    br label [[COND_END104:%.*]]
61806 // SIMD-ONLY0:       cond.false103:
61807 // SIMD-ONLY0-NEXT:    [[TMP108:%.*]] = load double, ptr [[DX]], align 8
61808 // SIMD-ONLY0-NEXT:    br label [[COND_END104]]
61809 // SIMD-ONLY0:       cond.end104:
61810 // SIMD-ONLY0-NEXT:    [[COND105:%.*]] = phi double [ [[TMP107]], [[COND_TRUE102]] ], [ [[TMP108]], [[COND_FALSE103]] ]
61811 // SIMD-ONLY0-NEXT:    store double [[COND105]], ptr [[DX]], align 8
61812 // SIMD-ONLY0-NEXT:    [[TMP109:%.*]] = load double, ptr [[DX]], align 8
61813 // SIMD-ONLY0-NEXT:    store double [[TMP109]], ptr [[DV]], align 8
61814 // SIMD-ONLY0-NEXT:    [[TMP110:%.*]] = load double, ptr [[DX]], align 8
61815 // SIMD-ONLY0-NEXT:    [[TMP111:%.*]] = load double, ptr [[DE]], align 8
61816 // SIMD-ONLY0-NEXT:    [[CMP106:%.*]] = fcmp olt double [[TMP110]], [[TMP111]]
61817 // SIMD-ONLY0-NEXT:    br i1 [[CMP106]], label [[COND_TRUE107:%.*]], label [[COND_FALSE108:%.*]]
61818 // SIMD-ONLY0:       cond.true107:
61819 // SIMD-ONLY0-NEXT:    [[TMP112:%.*]] = load double, ptr [[DE]], align 8
61820 // SIMD-ONLY0-NEXT:    br label [[COND_END109:%.*]]
61821 // SIMD-ONLY0:       cond.false108:
61822 // SIMD-ONLY0-NEXT:    [[TMP113:%.*]] = load double, ptr [[DX]], align 8
61823 // SIMD-ONLY0-NEXT:    br label [[COND_END109]]
61824 // SIMD-ONLY0:       cond.end109:
61825 // SIMD-ONLY0-NEXT:    [[COND110:%.*]] = phi double [ [[TMP112]], [[COND_TRUE107]] ], [ [[TMP113]], [[COND_FALSE108]] ]
61826 // SIMD-ONLY0-NEXT:    store double [[COND110]], ptr [[DX]], align 8
61827 // SIMD-ONLY0-NEXT:    [[TMP114:%.*]] = load double, ptr [[DX]], align 8
61828 // SIMD-ONLY0-NEXT:    store double [[TMP114]], ptr [[DV]], align 8
61829 // SIMD-ONLY0-NEXT:    [[TMP115:%.*]] = load double, ptr [[DX]], align 8
61830 // SIMD-ONLY0-NEXT:    [[TMP116:%.*]] = load double, ptr [[DE]], align 8
61831 // SIMD-ONLY0-NEXT:    [[CMP111:%.*]] = fcmp oeq double [[TMP115]], [[TMP116]]
61832 // SIMD-ONLY0-NEXT:    br i1 [[CMP111]], label [[COND_TRUE112:%.*]], label [[COND_FALSE113:%.*]]
61833 // SIMD-ONLY0:       cond.true112:
61834 // SIMD-ONLY0-NEXT:    [[TMP117:%.*]] = load double, ptr [[DD]], align 8
61835 // SIMD-ONLY0-NEXT:    br label [[COND_END114:%.*]]
61836 // SIMD-ONLY0:       cond.false113:
61837 // SIMD-ONLY0-NEXT:    [[TMP118:%.*]] = load double, ptr [[DX]], align 8
61838 // SIMD-ONLY0-NEXT:    br label [[COND_END114]]
61839 // SIMD-ONLY0:       cond.end114:
61840 // SIMD-ONLY0-NEXT:    [[COND115:%.*]] = phi double [ [[TMP117]], [[COND_TRUE112]] ], [ [[TMP118]], [[COND_FALSE113]] ]
61841 // SIMD-ONLY0-NEXT:    store double [[COND115]], ptr [[DX]], align 8
61842 // SIMD-ONLY0-NEXT:    [[TMP119:%.*]] = load double, ptr [[DX]], align 8
61843 // SIMD-ONLY0-NEXT:    store double [[TMP119]], ptr [[DV]], align 8
61844 // SIMD-ONLY0-NEXT:    [[TMP120:%.*]] = load double, ptr [[DX]], align 8
61845 // SIMD-ONLY0-NEXT:    store double [[TMP120]], ptr [[DV]], align 8
61846 // SIMD-ONLY0-NEXT:    [[TMP121:%.*]] = load double, ptr [[DX]], align 8
61847 // SIMD-ONLY0-NEXT:    [[TMP122:%.*]] = load double, ptr [[DE]], align 8
61848 // SIMD-ONLY0-NEXT:    [[CMP116:%.*]] = fcmp ogt double [[TMP121]], [[TMP122]]
61849 // SIMD-ONLY0-NEXT:    br i1 [[CMP116]], label [[COND_TRUE117:%.*]], label [[COND_FALSE118:%.*]]
61850 // SIMD-ONLY0:       cond.true117:
61851 // SIMD-ONLY0-NEXT:    [[TMP123:%.*]] = load double, ptr [[DE]], align 8
61852 // SIMD-ONLY0-NEXT:    br label [[COND_END119:%.*]]
61853 // SIMD-ONLY0:       cond.false118:
61854 // SIMD-ONLY0-NEXT:    [[TMP124:%.*]] = load double, ptr [[DX]], align 8
61855 // SIMD-ONLY0-NEXT:    br label [[COND_END119]]
61856 // SIMD-ONLY0:       cond.end119:
61857 // SIMD-ONLY0-NEXT:    [[COND120:%.*]] = phi double [ [[TMP123]], [[COND_TRUE117]] ], [ [[TMP124]], [[COND_FALSE118]] ]
61858 // SIMD-ONLY0-NEXT:    store double [[COND120]], ptr [[DX]], align 8
61859 // SIMD-ONLY0-NEXT:    [[TMP125:%.*]] = load double, ptr [[DX]], align 8
61860 // SIMD-ONLY0-NEXT:    store double [[TMP125]], ptr [[DV]], align 8
61861 // SIMD-ONLY0-NEXT:    [[TMP126:%.*]] = load double, ptr [[DX]], align 8
61862 // SIMD-ONLY0-NEXT:    [[TMP127:%.*]] = load double, ptr [[DE]], align 8
61863 // SIMD-ONLY0-NEXT:    [[CMP121:%.*]] = fcmp olt double [[TMP126]], [[TMP127]]
61864 // SIMD-ONLY0-NEXT:    br i1 [[CMP121]], label [[COND_TRUE122:%.*]], label [[COND_FALSE123:%.*]]
61865 // SIMD-ONLY0:       cond.true122:
61866 // SIMD-ONLY0-NEXT:    [[TMP128:%.*]] = load double, ptr [[DE]], align 8
61867 // SIMD-ONLY0-NEXT:    br label [[COND_END124:%.*]]
61868 // SIMD-ONLY0:       cond.false123:
61869 // SIMD-ONLY0-NEXT:    [[TMP129:%.*]] = load double, ptr [[DX]], align 8
61870 // SIMD-ONLY0-NEXT:    br label [[COND_END124]]
61871 // SIMD-ONLY0:       cond.end124:
61872 // SIMD-ONLY0-NEXT:    [[COND125:%.*]] = phi double [ [[TMP128]], [[COND_TRUE122]] ], [ [[TMP129]], [[COND_FALSE123]] ]
61873 // SIMD-ONLY0-NEXT:    store double [[COND125]], ptr [[DX]], align 8
61874 // SIMD-ONLY0-NEXT:    [[TMP130:%.*]] = load double, ptr [[DX]], align 8
61875 // SIMD-ONLY0-NEXT:    store double [[TMP130]], ptr [[DV]], align 8
61876 // SIMD-ONLY0-NEXT:    [[TMP131:%.*]] = load double, ptr [[DX]], align 8
61877 // SIMD-ONLY0-NEXT:    [[TMP132:%.*]] = load double, ptr [[DE]], align 8
61878 // SIMD-ONLY0-NEXT:    [[CMP126:%.*]] = fcmp oeq double [[TMP131]], [[TMP132]]
61879 // SIMD-ONLY0-NEXT:    br i1 [[CMP126]], label [[COND_TRUE127:%.*]], label [[COND_FALSE128:%.*]]
61880 // SIMD-ONLY0:       cond.true127:
61881 // SIMD-ONLY0-NEXT:    [[TMP133:%.*]] = load double, ptr [[DD]], align 8
61882 // SIMD-ONLY0-NEXT:    br label [[COND_END129:%.*]]
61883 // SIMD-ONLY0:       cond.false128:
61884 // SIMD-ONLY0-NEXT:    [[TMP134:%.*]] = load double, ptr [[DX]], align 8
61885 // SIMD-ONLY0-NEXT:    br label [[COND_END129]]
61886 // SIMD-ONLY0:       cond.end129:
61887 // SIMD-ONLY0-NEXT:    [[COND130:%.*]] = phi double [ [[TMP133]], [[COND_TRUE127]] ], [ [[TMP134]], [[COND_FALSE128]] ]
61888 // SIMD-ONLY0-NEXT:    store double [[COND130]], ptr [[DX]], align 8
61889 // SIMD-ONLY0-NEXT:    [[TMP135:%.*]] = load double, ptr [[DX]], align 8
61890 // SIMD-ONLY0-NEXT:    [[TMP136:%.*]] = load double, ptr [[DE]], align 8
61891 // SIMD-ONLY0-NEXT:    [[CMP131:%.*]] = fcmp ogt double [[TMP135]], [[TMP136]]
61892 // SIMD-ONLY0-NEXT:    br i1 [[CMP131]], label [[COND_TRUE132:%.*]], label [[COND_FALSE133:%.*]]
61893 // SIMD-ONLY0:       cond.true132:
61894 // SIMD-ONLY0-NEXT:    [[TMP137:%.*]] = load double, ptr [[DE]], align 8
61895 // SIMD-ONLY0-NEXT:    br label [[COND_END134:%.*]]
61896 // SIMD-ONLY0:       cond.false133:
61897 // SIMD-ONLY0-NEXT:    [[TMP138:%.*]] = load double, ptr [[DX]], align 8
61898 // SIMD-ONLY0-NEXT:    br label [[COND_END134]]
61899 // SIMD-ONLY0:       cond.end134:
61900 // SIMD-ONLY0-NEXT:    [[COND135:%.*]] = phi double [ [[TMP137]], [[COND_TRUE132]] ], [ [[TMP138]], [[COND_FALSE133]] ]
61901 // SIMD-ONLY0-NEXT:    store double [[COND135]], ptr [[DX]], align 8
61902 // SIMD-ONLY0-NEXT:    [[TMP139:%.*]] = load double, ptr [[DX]], align 8
61903 // SIMD-ONLY0-NEXT:    store double [[TMP139]], ptr [[DV]], align 8
61904 // SIMD-ONLY0-NEXT:    [[TMP140:%.*]] = load double, ptr [[DX]], align 8
61905 // SIMD-ONLY0-NEXT:    [[TMP141:%.*]] = load double, ptr [[DE]], align 8
61906 // SIMD-ONLY0-NEXT:    [[CMP136:%.*]] = fcmp olt double [[TMP140]], [[TMP141]]
61907 // SIMD-ONLY0-NEXT:    br i1 [[CMP136]], label [[COND_TRUE137:%.*]], label [[COND_FALSE138:%.*]]
61908 // SIMD-ONLY0:       cond.true137:
61909 // SIMD-ONLY0-NEXT:    [[TMP142:%.*]] = load double, ptr [[DE]], align 8
61910 // SIMD-ONLY0-NEXT:    br label [[COND_END139:%.*]]
61911 // SIMD-ONLY0:       cond.false138:
61912 // SIMD-ONLY0-NEXT:    [[TMP143:%.*]] = load double, ptr [[DX]], align 8
61913 // SIMD-ONLY0-NEXT:    br label [[COND_END139]]
61914 // SIMD-ONLY0:       cond.end139:
61915 // SIMD-ONLY0-NEXT:    [[COND140:%.*]] = phi double [ [[TMP142]], [[COND_TRUE137]] ], [ [[TMP143]], [[COND_FALSE138]] ]
61916 // SIMD-ONLY0-NEXT:    store double [[COND140]], ptr [[DX]], align 8
61917 // SIMD-ONLY0-NEXT:    [[TMP144:%.*]] = load double, ptr [[DX]], align 8
61918 // SIMD-ONLY0-NEXT:    store double [[TMP144]], ptr [[DV]], align 8
61919 // SIMD-ONLY0-NEXT:    [[TMP145:%.*]] = load double, ptr [[DX]], align 8
61920 // SIMD-ONLY0-NEXT:    [[TMP146:%.*]] = load double, ptr [[DE]], align 8
61921 // SIMD-ONLY0-NEXT:    [[CMP141:%.*]] = fcmp oeq double [[TMP145]], [[TMP146]]
61922 // SIMD-ONLY0-NEXT:    br i1 [[CMP141]], label [[COND_TRUE142:%.*]], label [[COND_FALSE143:%.*]]
61923 // SIMD-ONLY0:       cond.true142:
61924 // SIMD-ONLY0-NEXT:    [[TMP147:%.*]] = load double, ptr [[DD]], align 8
61925 // SIMD-ONLY0-NEXT:    br label [[COND_END144:%.*]]
61926 // SIMD-ONLY0:       cond.false143:
61927 // SIMD-ONLY0-NEXT:    [[TMP148:%.*]] = load double, ptr [[DX]], align 8
61928 // SIMD-ONLY0-NEXT:    br label [[COND_END144]]
61929 // SIMD-ONLY0:       cond.end144:
61930 // SIMD-ONLY0-NEXT:    [[COND145:%.*]] = phi double [ [[TMP147]], [[COND_TRUE142]] ], [ [[TMP148]], [[COND_FALSE143]] ]
61931 // SIMD-ONLY0-NEXT:    store double [[COND145]], ptr [[DX]], align 8
61932 // SIMD-ONLY0-NEXT:    [[TMP149:%.*]] = load double, ptr [[DX]], align 8
61933 // SIMD-ONLY0-NEXT:    store double [[TMP149]], ptr [[DV]], align 8
61934 // SIMD-ONLY0-NEXT:    [[TMP150:%.*]] = load double, ptr [[DX]], align 8
61935 // SIMD-ONLY0-NEXT:    store double [[TMP150]], ptr [[DV]], align 8
61936 // SIMD-ONLY0-NEXT:    [[TMP151:%.*]] = load double, ptr [[DX]], align 8
61937 // SIMD-ONLY0-NEXT:    [[TMP152:%.*]] = load double, ptr [[DE]], align 8
61938 // SIMD-ONLY0-NEXT:    [[CMP146:%.*]] = fcmp ogt double [[TMP151]], [[TMP152]]
61939 // SIMD-ONLY0-NEXT:    br i1 [[CMP146]], label [[COND_TRUE147:%.*]], label [[COND_FALSE148:%.*]]
61940 // SIMD-ONLY0:       cond.true147:
61941 // SIMD-ONLY0-NEXT:    [[TMP153:%.*]] = load double, ptr [[DE]], align 8
61942 // SIMD-ONLY0-NEXT:    br label [[COND_END149:%.*]]
61943 // SIMD-ONLY0:       cond.false148:
61944 // SIMD-ONLY0-NEXT:    [[TMP154:%.*]] = load double, ptr [[DX]], align 8
61945 // SIMD-ONLY0-NEXT:    br label [[COND_END149]]
61946 // SIMD-ONLY0:       cond.end149:
61947 // SIMD-ONLY0-NEXT:    [[COND150:%.*]] = phi double [ [[TMP153]], [[COND_TRUE147]] ], [ [[TMP154]], [[COND_FALSE148]] ]
61948 // SIMD-ONLY0-NEXT:    store double [[COND150]], ptr [[DX]], align 8
61949 // SIMD-ONLY0-NEXT:    [[TMP155:%.*]] = load double, ptr [[DX]], align 8
61950 // SIMD-ONLY0-NEXT:    store double [[TMP155]], ptr [[DV]], align 8
61951 // SIMD-ONLY0-NEXT:    [[TMP156:%.*]] = load double, ptr [[DX]], align 8
61952 // SIMD-ONLY0-NEXT:    [[TMP157:%.*]] = load double, ptr [[DE]], align 8
61953 // SIMD-ONLY0-NEXT:    [[CMP151:%.*]] = fcmp olt double [[TMP156]], [[TMP157]]
61954 // SIMD-ONLY0-NEXT:    br i1 [[CMP151]], label [[COND_TRUE152:%.*]], label [[COND_FALSE153:%.*]]
61955 // SIMD-ONLY0:       cond.true152:
61956 // SIMD-ONLY0-NEXT:    [[TMP158:%.*]] = load double, ptr [[DE]], align 8
61957 // SIMD-ONLY0-NEXT:    br label [[COND_END154:%.*]]
61958 // SIMD-ONLY0:       cond.false153:
61959 // SIMD-ONLY0-NEXT:    [[TMP159:%.*]] = load double, ptr [[DX]], align 8
61960 // SIMD-ONLY0-NEXT:    br label [[COND_END154]]
61961 // SIMD-ONLY0:       cond.end154:
61962 // SIMD-ONLY0-NEXT:    [[COND155:%.*]] = phi double [ [[TMP158]], [[COND_TRUE152]] ], [ [[TMP159]], [[COND_FALSE153]] ]
61963 // SIMD-ONLY0-NEXT:    store double [[COND155]], ptr [[DX]], align 8
61964 // SIMD-ONLY0-NEXT:    [[TMP160:%.*]] = load double, ptr [[DX]], align 8
61965 // SIMD-ONLY0-NEXT:    store double [[TMP160]], ptr [[DV]], align 8
61966 // SIMD-ONLY0-NEXT:    [[TMP161:%.*]] = load double, ptr [[DX]], align 8
61967 // SIMD-ONLY0-NEXT:    [[TMP162:%.*]] = load double, ptr [[DE]], align 8
61968 // SIMD-ONLY0-NEXT:    [[CMP156:%.*]] = fcmp oeq double [[TMP161]], [[TMP162]]
61969 // SIMD-ONLY0-NEXT:    br i1 [[CMP156]], label [[COND_TRUE157:%.*]], label [[COND_FALSE158:%.*]]
61970 // SIMD-ONLY0:       cond.true157:
61971 // SIMD-ONLY0-NEXT:    [[TMP163:%.*]] = load double, ptr [[DD]], align 8
61972 // SIMD-ONLY0-NEXT:    br label [[COND_END159:%.*]]
61973 // SIMD-ONLY0:       cond.false158:
61974 // SIMD-ONLY0-NEXT:    [[TMP164:%.*]] = load double, ptr [[DX]], align 8
61975 // SIMD-ONLY0-NEXT:    br label [[COND_END159]]
61976 // SIMD-ONLY0:       cond.end159:
61977 // SIMD-ONLY0-NEXT:    [[COND160:%.*]] = phi double [ [[TMP163]], [[COND_TRUE157]] ], [ [[TMP164]], [[COND_FALSE158]] ]
61978 // SIMD-ONLY0-NEXT:    store double [[COND160]], ptr [[DX]], align 8
61979 // SIMD-ONLY0-NEXT:    [[TMP165:%.*]] = load double, ptr [[DX]], align 8
61980 // SIMD-ONLY0-NEXT:    [[TMP166:%.*]] = load double, ptr [[DE]], align 8
61981 // SIMD-ONLY0-NEXT:    [[CMP161:%.*]] = fcmp ogt double [[TMP165]], [[TMP166]]
61982 // SIMD-ONLY0-NEXT:    br i1 [[CMP161]], label [[COND_TRUE162:%.*]], label [[COND_FALSE163:%.*]]
61983 // SIMD-ONLY0:       cond.true162:
61984 // SIMD-ONLY0-NEXT:    [[TMP167:%.*]] = load double, ptr [[DE]], align 8
61985 // SIMD-ONLY0-NEXT:    br label [[COND_END164:%.*]]
61986 // SIMD-ONLY0:       cond.false163:
61987 // SIMD-ONLY0-NEXT:    [[TMP168:%.*]] = load double, ptr [[DX]], align 8
61988 // SIMD-ONLY0-NEXT:    br label [[COND_END164]]
61989 // SIMD-ONLY0:       cond.end164:
61990 // SIMD-ONLY0-NEXT:    [[COND165:%.*]] = phi double [ [[TMP167]], [[COND_TRUE162]] ], [ [[TMP168]], [[COND_FALSE163]] ]
61991 // SIMD-ONLY0-NEXT:    store double [[COND165]], ptr [[DX]], align 8
61992 // SIMD-ONLY0-NEXT:    [[TMP169:%.*]] = load double, ptr [[DX]], align 8
61993 // SIMD-ONLY0-NEXT:    store double [[TMP169]], ptr [[DV]], align 8
61994 // SIMD-ONLY0-NEXT:    [[TMP170:%.*]] = load double, ptr [[DX]], align 8
61995 // SIMD-ONLY0-NEXT:    [[TMP171:%.*]] = load double, ptr [[DE]], align 8
61996 // SIMD-ONLY0-NEXT:    [[CMP166:%.*]] = fcmp olt double [[TMP170]], [[TMP171]]
61997 // SIMD-ONLY0-NEXT:    br i1 [[CMP166]], label [[COND_TRUE167:%.*]], label [[COND_FALSE168:%.*]]
61998 // SIMD-ONLY0:       cond.true167:
61999 // SIMD-ONLY0-NEXT:    [[TMP172:%.*]] = load double, ptr [[DE]], align 8
62000 // SIMD-ONLY0-NEXT:    br label [[COND_END169:%.*]]
62001 // SIMD-ONLY0:       cond.false168:
62002 // SIMD-ONLY0-NEXT:    [[TMP173:%.*]] = load double, ptr [[DX]], align 8
62003 // SIMD-ONLY0-NEXT:    br label [[COND_END169]]
62004 // SIMD-ONLY0:       cond.end169:
62005 // SIMD-ONLY0-NEXT:    [[COND170:%.*]] = phi double [ [[TMP172]], [[COND_TRUE167]] ], [ [[TMP173]], [[COND_FALSE168]] ]
62006 // SIMD-ONLY0-NEXT:    store double [[COND170]], ptr [[DX]], align 8
62007 // SIMD-ONLY0-NEXT:    [[TMP174:%.*]] = load double, ptr [[DX]], align 8
62008 // SIMD-ONLY0-NEXT:    store double [[TMP174]], ptr [[DV]], align 8
62009 // SIMD-ONLY0-NEXT:    [[TMP175:%.*]] = load double, ptr [[DX]], align 8
62010 // SIMD-ONLY0-NEXT:    [[TMP176:%.*]] = load double, ptr [[DE]], align 8
62011 // SIMD-ONLY0-NEXT:    [[CMP171:%.*]] = fcmp oeq double [[TMP175]], [[TMP176]]
62012 // SIMD-ONLY0-NEXT:    br i1 [[CMP171]], label [[COND_TRUE172:%.*]], label [[COND_FALSE173:%.*]]
62013 // SIMD-ONLY0:       cond.true172:
62014 // SIMD-ONLY0-NEXT:    [[TMP177:%.*]] = load double, ptr [[DD]], align 8
62015 // SIMD-ONLY0-NEXT:    br label [[COND_END174:%.*]]
62016 // SIMD-ONLY0:       cond.false173:
62017 // SIMD-ONLY0-NEXT:    [[TMP178:%.*]] = load double, ptr [[DX]], align 8
62018 // SIMD-ONLY0-NEXT:    br label [[COND_END174]]
62019 // SIMD-ONLY0:       cond.end174:
62020 // SIMD-ONLY0-NEXT:    [[COND175:%.*]] = phi double [ [[TMP177]], [[COND_TRUE172]] ], [ [[TMP178]], [[COND_FALSE173]] ]
62021 // SIMD-ONLY0-NEXT:    store double [[COND175]], ptr [[DX]], align 8
62022 // SIMD-ONLY0-NEXT:    [[TMP179:%.*]] = load double, ptr [[DX]], align 8
62023 // SIMD-ONLY0-NEXT:    store double [[TMP179]], ptr [[DV]], align 8
62024 // SIMD-ONLY0-NEXT:    [[TMP180:%.*]] = load double, ptr [[DV]], align 8
62025 // SIMD-ONLY0-NEXT:    ret double [[TMP180]]
62026 //
62027 // CHECK-LABEL: {{.+}}fail_dxevd{{.+}}
62028 // CHECK-NEXT:  entry:
62029 // CHECK:       {{.+}} load double,{{.+}}
62030 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62031 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62032 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62033 // CHECK-NEXT:    {{.+}}cmpxchg ptr {{.+}} monotonic monotonic{{.+}}
62034 // CHECK:       {{.+}} load double,{{.+}}
62035 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62036 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62037 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62038 // CHECK:    {{.+}}cmpxchg ptr {{.+}} acquire monotonic{{.+}}
62039 // CHECK:       {{.+}} load double,{{.+}}
62040 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62041 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62042 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62043 // CHECK:    {{.+}}cmpxchg ptr {{.+}} release monotonic{{.+}}
62044 // CHECK:       {{.+}} load double,{{.+}}
62045 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62046 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62047 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62048 // CHECK:    {{.+}}cmpxchg ptr {{.+}} acq_rel monotonic{{.+}}
62049 // CHECK:       {{.+}} load double,{{.+}}
62050 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62051 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62052 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62053 // CHECK-NEXT:  {{.+}}cmpxchg ptr {{.+}} seq_cst monotonic{{.+}}
62054 // CHECK:    {{.+}}__kmpc_flush{{.+}}
62055 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62056 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62057 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62058 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62059 // CHECK:    {{.+}}cmpxchg ptr {{.+}} monotonic acquire{{.+}}
62060 // CHECK:       {{.+}} load double,{{.+}}
62061 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62062 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62063 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62064 // CHECK:    {{.+}}cmpxchg ptr {{.+}} acquire acquire{{.+}}
62065 // CHECK:       {{.+}} load double,{{.+}}
62066 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62067 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62068 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62069 // CHECK:    {{.+}}cmpxchg ptr {{.+}} release acquire{{.+}}
62070 // CHECK:       {{.+}} load double,{{.+}}
62071 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62072 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62073 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62074 // CHECK:    {{.+}}cmpxchg ptr {{.+}} acq_rel acquire{{.+}}
62075 // CHECK:       {{.+}} load double,{{.+}}
62076 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62077 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62078 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62079 // CHECK:    {{.+}}cmpxchg ptr {{.+}} seq_cst acquire{{.+}}
62080 // CHECK:    {{.+}}__kmpc_flush{{.+}}
62081 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62082 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62083 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62084 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62085 // CHECK:    {{.+}}cmpxchg ptr {{.+}} monotonic seq_cst{{.+}}
62086 // CHECK:       {{.+}} load double,{{.+}}
62087 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62088 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62089 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62090 // CHECK:    {{.+}}cmpxchg ptr {{.+}} acquire seq_cst{{.+}}
62091 // CHECK:       {{.+}} load double,{{.+}}
62092 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62093 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62094 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62095 // CHECK:    {{.+}}cmpxchg ptr {{.+}} release seq_cst{{.+}}
62096 // CHECK:       {{.+}} load double,{{.+}}
62097 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62098 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62099 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62100 // CHECK:    {{.+}}cmpxchg ptr {{.+}} acq_rel seq_cst{{.+}}
62101 // CHECK:       {{.+}} load double,{{.+}}
62102 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62103 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62104 // CHECK-NEXT:  {{.+}} bitcast double{{.+}}
62105 // CHECK:    {{.+}}cmpxchg ptr {{.+}} seq_cst seq_cst{{.+}}
62106 // CHECK:    call void {{.+}}__kmpc_flush{{.+}}
62107 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62108 // CHECK-NEXT:  {{.+}} atomicrmw fmax {{.+}} seq_cst{{.+}}
62109 // CHECK-NEXT:  call void {{.+}}__kmpc_flush{{.+}}
62110 // CHECK-NEXT:  {{.+}} load double,{{.+}}
62111 // CHECK-NEXT:  {{.+}} atomicrmw fmin {{.+}} monotonic{{.+}}
62112 // CHECK:    ret double {{.+}}
62113