1 // Check target CPUs are correctly passed. 2 3 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=rocket-rv32 | FileCheck -check-prefix=MCPU-ROCKET32 %s 4 // MCPU-ROCKET32: "-nostdsysteminc" "-target-cpu" "rocket-rv32" 5 // MCPU-ROCKET32: "-target-feature" "+zicsr" "-target-feature" "+zifencei" 6 7 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=rocket-rv64 | FileCheck -check-prefix=MCPU-ROCKET64 %s 8 // MCPU-ROCKET64: "-nostdsysteminc" "-target-cpu" "rocket-rv64" 9 // MCPU-ROCKET64: "-target-feature" "+zicsr" "-target-feature" "+zifencei" 10 11 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-base | FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-BASE %s 12 // MCPU-SYNTACORE-SCR1-BASE: "-target-cpu" "syntacore-scr1-base" 13 // MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+c" 14 // MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+zicsr" "-target-feature" "+zifencei" 15 // MCPU-SYNTACORE-SCR1-BASE: "-target-abi" "ilp32" 16 17 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-max | FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-MAX %s 18 // MCPU-SYNTACORE-SCR1-MAX: "-target-cpu" "syntacore-scr1-max" 19 // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+m" "-target-feature" "+c" 20 // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" "+zifencei" 21 // MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32" 22 23 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu | FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s 24 // MCPU-XIANGSHAN-NANHU: "-nostdsysteminc" "-target-cpu" "xiangshan-nanhu" 25 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 26 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+c" 27 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zicbom" "-target-feature" "+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei" 28 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbc" 29 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zbkb" "-target-feature" "+zbkc" "-target-feature" "+zbkx" "-target-feature" "+zbs" 30 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zkn" "-target-feature" "+zknd" "-target-feature" "+zkne" "-target-feature" "+zknh" 31 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval" 32 // MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d" 33 34 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x60 | FileCheck -check-prefix=MCPU-SPACEMIT-X60 %s 35 // MCPU-SPACEMIT-X60: "-nostdsysteminc" "-target-cpu" "spacemit-x60" 36 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m" 37 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+a" 38 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+f" 39 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+d" 40 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+c" 41 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+v" 42 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zic64b" 43 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicbom" 44 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicbop" 45 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicboz" 46 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccamoa" 47 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccif" 48 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicclsm" 49 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccrse" 50 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicntr" 51 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicond" 52 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicsr" 53 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zifencei" 54 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zihintpause" 55 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zihpm" 56 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+za64rs" 57 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zfh" 58 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zfhmin" 59 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zba" 60 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbb" 61 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbc" 62 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbkc" 63 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbs" 64 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zkt" 65 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve32f" 66 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve32x" 67 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64d" 68 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64f" 69 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64x" 70 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvfh" 71 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvfhmin" 72 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvkt" 73 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl128b" 74 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl256b" 75 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl32b" 76 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl64b" 77 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ssccptr" 78 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sscofpmf" 79 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sscounterenw" 80 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstc" 81 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstvala" 82 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstvecd" 83 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svade" 84 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svbare" 85 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svinval" 86 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svnapot" 87 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svpbmt" 88 // MCPU-SPACEMIT-X60-SAME: "-target-abi" "lp64d" 89 90 // We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string. 91 // RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true 92 // RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s 93 // MCPU-NATIVE-NOT: "-target-cpu" "native" 94 95 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=rocket-rv32 | FileCheck -check-prefix=MTUNE-ROCKET32 %s 96 // MTUNE-ROCKET32: "-tune-cpu" "rocket-rv32" 97 98 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket-rv64 | FileCheck -check-prefix=MTUNE-ROCKET64 %s 99 // MTUNE-ROCKET64: "-tune-cpu" "rocket-rv64" 100 101 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=mips-p8700 | FileCheck -check-prefix=MTUNE-MIPS-P8700 %s 102 // MTUNE-MIPS-P8700: "-tune-cpu" "mips-p8700" 103 104 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=mips-p8700 | FileCheck -check-prefix=MCPU-MIPS-P8700 %s 105 // MCPU-MIPS-P8700: "-target-cpu" "mips-p8700" 106 // MCPU-MIPS-P8700-SAME: "-target-feature" "+m" 107 // MCPU-MIPS-P8700-SAME: "-target-feature" "+a" 108 // MCPU-MIPS-P8700-SAME: "-target-feature" "+f" 109 // MCPU-MIPS-P8700-SAME: "-target-feature" "+d" 110 // MCPU-MIPS-P8700-SAME: "-target-feature" "+c" 111 // MCPU-MIPS-P8700-SAME: "-target-feature" "+zicsr" 112 // MCPU-MIPS-P8700-SAME: "-target-feature" "+zifencei" 113 // MCPU-MIPS-P8700-SAME: "-target-feature" "+zaamo" 114 // MCPU-MIPS-P8700-SAME: "-target-feature" "+zalrsc" 115 // MCPU-MIPS-P8700-SAME: "-target-feature" "+zba" 116 // MCPU-MIPS-P8700-SAME: "-target-feature" "+zbb" 117 118 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-base | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-BASE %s 119 // MTUNE-SYNTACORE-SCR1-BASE: "-tune-cpu" "syntacore-scr1-base" 120 121 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s 122 // MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max" 123 124 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=tt-ascalon-d8 | FileCheck -check-prefix=MTUNE-TT-ASCALON-D8 %s 125 // MTUNE-TT-ASCALON-D8: "-tune-cpu" "tt-ascalon-d8" 126 127 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=tt-ascalon-d8 | FileCheck -check-prefix=MCPU-TT-ASCALON-D8 %s 128 // MCPU-TT-ASCALON-D8: "-target-cpu" "tt-ascalon-d8" 129 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+m" 130 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+a" 131 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+f" 132 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+d" 133 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+c" 134 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+v" 135 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+h" 136 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicbom" 137 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicbop" 138 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicboz" 139 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicntr" 140 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicond" 141 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicsr" 142 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zifencei" 143 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintntl" 144 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintpause" 145 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihpm" 146 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zimop" 147 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zmmul" 148 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zawrs" 149 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfa" 150 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfbfmin" 151 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfh" 152 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfhmin" 153 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zca" 154 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zcb" 155 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zba" 156 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zbb" 157 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zbs" 158 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zkt" 159 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbb" 160 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbc" 161 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve32f" 162 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve32x" 163 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64d" 164 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64f" 165 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64x" 166 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfbfmin" 167 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfbfwma" 168 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfh" 169 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfhmin" 170 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkb" 171 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkg" 172 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkn" 173 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvknc" 174 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkned" 175 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkng" 176 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvknhb" 177 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkt" 178 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl128b" 179 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl256b" 180 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl32b" 181 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl64b" 182 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svinval" 183 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svnapot" 184 // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svpbmt" 185 186 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=veyron-v1 | FileCheck -check-prefix=MCPU-VEYRON-V1 %s 187 // MCPU-VEYRON-V1: "-target-cpu" "veyron-v1" 188 // MCPU-VEYRON-V1: "-target-feature" "+m" 189 // MCPU-VEYRON-V1: "-target-feature" "+a" 190 // MCPU-VEYRON-V1: "-target-feature" "+f" 191 // MCPU-VEYRON-V1: "-target-feature" "+d" 192 // MCPU-VEYRON-V1: "-target-feature" "+c" 193 // MCPU-VEYRON-V1: "-target-feature" "+zicbom" 194 // MCPU-VEYRON-V1: "-target-feature" "+zicbop" 195 // MCPU-VEYRON-V1: "-target-feature" "+zicboz" 196 // MCPU-VEYRON-V1: "-target-feature" "+zicntr" 197 // MCPU-VEYRON-V1: "-target-feature" "+zicsr" 198 // MCPU-VEYRON-V1: "-target-feature" "+zifencei" 199 // MCPU-VEYRON-V1: "-target-feature" "+zihintpause" 200 // MCPU-VEYRON-V1: "-target-feature" "+zihpm" 201 // MCPU-VEYRON-V1: "-target-feature" "+zba" 202 // MCPU-VEYRON-V1: "-target-feature" "+zbb" 203 // MCPU-VEYRON-V1: "-target-feature" "+zbc" 204 // MCPU-VEYRON-V1: "-target-feature" "+zbs" 205 // MCPU-VEYRON-V1: "-target-feature" "+xventanacondops" 206 // MCPU-VEYRON-V1: "-target-abi" "lp64d" 207 208 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck -check-prefix=MTUNE-VEYRON-V1 %s 209 // MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1" 210 211 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu | FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s 212 // MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu" 213 214 // Check mtune alias CPU has resolved to the right CPU according XLEN. 215 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-32 %s 216 // MTUNE-GENERIC-32: "-tune-cpu" "generic" 217 218 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-64 %s 219 // MTUNE-GENERIC-64: "-tune-cpu" "generic" 220 221 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=rocket | FileCheck -check-prefix=MTUNE-ROCKET-32 %s 222 // MTUNE-ROCKET-32: "-tune-cpu" "rocket" 223 224 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket | FileCheck -check-prefix=MTUNE-ROCKET-64 %s 225 // MTUNE-ROCKET-64: "-tune-cpu" "rocket" 226 227 // We cannot check much for -mtune=native, but it should be replaced by a valid CPU string. 228 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=native | FileCheck -check-prefix=MTUNE-NATIVE %s 229 // MTUNE-NATIVE-NOT: "-tune-cpu" "native" 230 231 // mcpu with default march 232 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e20 | FileCheck -check-prefix=MCPU-SIFIVE-E20 %s 233 // MCPU-SIFIVE-E20: "-nostdsysteminc" "-target-cpu" "sifive-e20" 234 // MCPU-SIFIVE-E20: "-target-feature" "+m" "-target-feature" "+c" 235 // MCPU-SIFIVE-E20: "-target-feature" "+zicsr" "-target-feature" "+zifencei" 236 // MCPU-SIFIVE-E20: "-target-abi" "ilp32" 237 238 // mcpu with default march 239 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e21 | FileCheck -check-prefix=MCPU-SIFIVE-E21 %s 240 // MCPU-SIFIVE-E21: "-nostdsysteminc" "-target-cpu" "sifive-e21" 241 // MCPU-SIFIVE-E21: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+c" 242 // MCPU-SIFIVE-E21: "-target-feature" "+zicsr" "-target-feature" "+zifencei" 243 // MCPU-SIFIVE-E21: "-target-abi" "ilp32" 244 245 // mcpu with default march 246 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e24 | FileCheck -check-prefix=MCPU-SIFIVE-E24 %s 247 // MCPU-SIFIVE-E24: "-nostdsysteminc" "-target-cpu" "sifive-e24" 248 // MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" 249 // MCPU-SIFIVE-E24: "-target-feature" "+c" 250 // MCPU-SIFIVE-E24: "-target-feature" "+zicsr" "-target-feature" "+zifencei" 251 // MCPU-SIFIVE-E24: "-target-abi" "ilp32f" 252 253 // mcpu with default march 254 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck -check-prefix=MCPU-SIFIVE-E34 %s 255 // MCPU-SIFIVE-E34: "-nostdsysteminc" "-target-cpu" "sifive-e34" 256 // MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" 257 // MCPU-SIFIVE-E34: "-target-feature" "+c" 258 // MCPU-SIFIVE-E34: "-target-feature" "+zicsr" "-target-feature" "+zifencei" 259 // MCPU-SIFIVE-E34: "-target-abi" "ilp32f" 260 261 // mcpu with mabi option 262 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s 263 // MCPU-ABI-SIFIVE-S21: "-nostdsysteminc" "-target-cpu" "sifive-s21" 264 // MCPU-ABI-SIFIVE-S21: "-target-feature" "+m" "-target-feature" "+a" 265 // MCPU-ABI-SIFIVE-S21: "-target-feature" "+c" 266 // MCPU-ABI-SIFIVE-S21: "-target-feature" "+zicsr" "-target-feature" "+zifencei" 267 // MCPU-ABI-SIFIVE-S21: "-target-abi" "lp64" 268 269 // mcpu with mabi option 270 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s 271 // MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51" 272 // MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a" 273 // MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" 274 // MCPU-ABI-SIFIVE-S51: "-target-feature" "+zicsr" "-target-feature" "+zifencei" 275 // MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64" 276 277 // mcpu with default march 278 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s54 | FileCheck -check-prefix=MCPU-SIFIVE-S54 %s 279 // MCPU-SIFIVE-S54: "-nostdsysteminc" "-target-cpu" "sifive-s54" 280 // MCPU-SIFIVE-S54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 281 // MCPU-SIFIVE-S54: "-target-feature" "+c" 282 // MCPU-SIFIVE-S54: "-target-feature" "+zicsr" "-target-feature" "+zifencei" 283 // MCPU-SIFIVE-S54: "-target-abi" "lp64d" 284 285 // mcpu with mabi option 286 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s76 | FileCheck -check-prefix=MCPU-SIFIVE-S76 %s 287 // MCPU-SIFIVE-S76: "-nostdsysteminc" "-target-cpu" "sifive-s76" 288 // MCPU-SIFIVE-S76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 289 // MCPU-SIFIVE-S76: "-target-feature" "+c" 290 // MCPU-SIFIVE-S76: "-target-feature" "+zicsr" "-target-feature" "+zifencei" "-target-feature" "+zihintpause" 291 // MCPU-SIFIVE-S76: "-target-abi" "lp64d" 292 293 // mcpu with default march 294 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck -check-prefix=MCPU-SIFIVE-U54 %s 295 // MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54" 296 // MCPU-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 297 // MCPU-SIFIVE-U54: "-target-feature" "+c" 298 // MCPU-SIFIVE-U54: "-target-feature" "+zicsr" "-target-feature" "+zifencei" 299 // MCPU-SIFIVE-U54: "-target-abi" "lp64d" 300 301 // mcpu with mabi option 302 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U54 %s 303 // MCPU-ABI-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54" 304 // MCPU-ABI-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 305 // MCPU-ABI-SIFIVE-U54: "-target-feature" "+c" 306 // MCPU-ABI-SIFIVE-U54: "-target-feature" "+zicsr" "-target-feature" "+zifencei" 307 // MCPU-ABI-SIFIVE-U54: "-target-abi" "lp64" 308 309 // mcpu with default march 310 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e76 | FileCheck -check-prefix=MCPU-SIFIVE-E76 %s 311 // MCPU-SIFIVE-E76: "-nostdsysteminc" "-target-cpu" "sifive-e76" 312 // MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" 313 // MCPU-SIFIVE-E76: "-target-feature" "+c" 314 // MCPU-SIFIVE-E76: "-target-feature" "+zicsr" "-target-feature" "+zifencei" 315 // MCPU-SIFIVE-E76: "-target-abi" "ilp32f" 316 317 // mcpu with mabi option 318 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s 319 // MCPU-ABI-SIFIVE-U74: "-nostdsysteminc" "-target-cpu" "sifive-u74" 320 // MCPU-ABI-SIFIVE-U74: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 321 // MCPU-ABI-SIFIVE-U74: "-target-feature" "+c" 322 // MCPU-ABI-SIFIVE-U74: "-target-feature" "+zicsr" "-target-feature" "+zifencei" 323 // MCPU-ABI-SIFIVE-U74: "-target-abi" "lp64" 324 325 // march overwrite mcpu's default march 326 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 -march=rv32imc | FileCheck -check-prefix=MCPU-MARCH %s 327 // MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature" "+m" "-target-feature" "+c" 328 // MCPU-MARCH: "-target-abi" "ilp32" 329 330 // Check interaction between mcpu and mtune, mtune won't affect arch related 331 // target feature, but mcpu will. 332 // 333 // In this case, sifive-e31 is rv32imac, sifive-e76 is rv32imafc, so F-extension 334 // should not enabled. 335 // 336 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 -mtune=sifive-e76 | FileCheck -check-prefix=MTUNE-E31-MCPU-E76 %s 337 // MTUNE-E31-MCPU-E76: "-target-cpu" "sifive-e31" 338 // MTUNE-E31-MCPU-E76-NOT: "-target-feature" "+f" 339 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+m" 340 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+a" 341 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+c" 342 // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei" 343 // MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76" 344 345 // mcpu with default march include experimental extensions 346 // RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-x280 | FileCheck -check-prefix=MCPU-SIFIVE-X280 %s 347 // MCPU-SIFIVE-X280: "-nostdsysteminc" "-target-cpu" "sifive-x280" 348 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 349 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v" 350 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei" 351 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh" 352 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" 353 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvfh" 354 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b" 355 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl256b" "-target-feature" "+zvl32b" 356 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b" 357 // MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d" 358 359 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p450 | FileCheck -check-prefix=MCPU-SIFIVE-P450 %s 360 // MCPU-SIFIVE-P450: "-nostdsysteminc" "-target-cpu" "sifive-p450" 361 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+m" 362 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+a" 363 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+f" 364 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+d" 365 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+c" 366 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zic64b" 367 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicbom" 368 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicbop" 369 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicboz" 370 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccamoa" 371 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccif" 372 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicclsm" 373 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccrse" 374 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicntr" 375 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicsr" 376 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zifencei" 377 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihintntl" 378 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihintpause" 379 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihpm" 380 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+za64rs" 381 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zfhmin" 382 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zba" 383 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb" 384 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs" 385 // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d" 386 387 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p470 | FileCheck -check-prefix=MCPU-SIFIVE-P470 %s 388 // MCPU-SIFIVE-P470: "-target-cpu" "sifive-p470" 389 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+m" 390 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+a" 391 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+f" 392 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+d" 393 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+c" 394 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+v" 395 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zic64b" 396 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicbom" 397 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicbop" 398 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicboz" 399 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccamoa" 400 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccif" 401 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicclsm" 402 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccrse" 403 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicntr" 404 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicsr" 405 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zifencei" 406 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihintntl" 407 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihintpause" 408 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihpm" 409 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zmmul" 410 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+za64rs" 411 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zfhmin" 412 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zba" 413 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zbb" 414 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zbs" 415 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvbb" 416 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvbc" 417 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve32f" 418 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve32x" 419 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64d" 420 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64f" 421 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64x" 422 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkg" 423 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkn" 424 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvknc" 425 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkned" 426 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkng" 427 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvknhb" 428 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvks" 429 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksc" 430 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksed" 431 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksg" 432 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksh" 433 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkt" 434 // MCPU-SIFIVE-P470-SAME: "-target-abi" "lp64d" 435 436 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p550 | FileCheck -check-prefix=MCPU-SIFIVE-P550 %s 437 // MCPU-SIFIVE-P550: "-nostdsysteminc" "-target-cpu" "sifive-p550" 438 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+m" 439 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+a" 440 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+f" 441 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+d" 442 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+c" 443 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+zicsr" 444 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+zifencei" 445 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+zba" 446 // MCPU-SIFIVE-P550-SAME: "-target-feature" "+zbb" 447 // MCPU-SIFIVE-P550-SAME: "-target-abi" "lp64d" 448 449 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck -check-prefix=MCPU-SIFIVE-P670 %s 450 // MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670" 451 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+m" 452 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+a" 453 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+f" 454 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+d" 455 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+c" 456 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+v" 457 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zic64b" 458 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicbom" 459 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicbop" 460 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicboz" 461 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccamoa" 462 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccif" 463 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicclsm" 464 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccrse" 465 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicntr" 466 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicsr" 467 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zifencei" 468 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zihintntl" 469 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zihintpause" 470 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zihpm" 471 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+za64rs" 472 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zfhmin" 473 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zba" 474 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zbb" 475 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zbs" 476 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvbb" 477 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvbc" 478 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve32f" 479 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve32x" 480 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve64d" 481 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve64f" 482 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve64x" 483 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkg" 484 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkn" 485 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvknc" 486 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkned" 487 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkng" 488 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvknhb" 489 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvks" 490 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvksc" 491 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvksed" 492 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvksg" 493 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvksh" 494 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt" 495 // MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d" 496 497 // RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rp2350-hazard3 | FileCheck -check-prefix=MCPU-HAZARD3 %s 498 // MCPU-HAZARD3: "-target-cpu" "rp2350-hazard3" 499 // MCPU-HAZARD3-SAME: "-target-feature" "+m" 500 // MCPU-HAZARD3-SAME: "-target-feature" "+a" 501 // MCPU-HAZARD3-SAME: "-target-feature" "+c" 502 // MCPU-HAZARD3-SAME: "-target-feature" "+zicsr" 503 // MCPU-HAZARD3-SAME: "-target-feature" "+zifencei" 504 // MCPU-HAZARD3-SAME: "-target-feature" "+zcb" 505 // MCPU-HAZARD3-SAME: "-target-feature" "+zcmp" 506 // MCPU-HAZARD3-SAME: "-target-feature" "+zba" 507 // MCPU-HAZARD3-SAME: "-target-feature" "+zbb" 508 // MCPU-HAZARD3-SAME: "-target-feature" "+zbkb" 509 // MCPU-HAZARD3-SAME: "-target-feature" "+zbs" 510 // MCPU-HAZARD3-SAME: "-target-abi" "ilp32" 511 512 // Check failed cases 513 514 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s 515 // FAIL-MCPU-NAME: error: unsupported argument 'generic-rv321' to option '-mcpu=' 516 517 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s 518 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64 519 520 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv32 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV32 %s 521 // MCPU-SYNTACORE-SCR3-RV32: "-target-cpu" "syntacore-scr3-rv32" 522 // MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+m" 523 // MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+c" 524 // MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+zicsr" 525 // MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+zifencei" 526 // MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-abi" "ilp32" 527 528 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr3-rv32 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR3-RV32 %s 529 // MTUNE-SYNTACORE-SCR3-RV32: "-tune-cpu" "syntacore-scr3-rv32" 530 531 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv64 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV64 %s 532 // MCPU-SYNTACORE-SCR3-RV64: "-target-cpu" "syntacore-scr3-rv64" 533 // MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+m" 534 // MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+a" 535 // MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+c" 536 // MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+zicsr" 537 // MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+zifencei" 538 // MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-abi" "lp64" 539 540 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr3-rv64 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR3-RV64 %s 541 // MTUNE-SYNTACORE-SCR3-RV64: "-tune-cpu" "syntacore-scr3-rv64" 542 543 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr4-rv32 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR4-RV32 %s 544 // MCPU-SYNTACORE-SCR4-RV32: "-target-cpu" "syntacore-scr4-rv32" 545 // MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+m" 546 // MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+f" 547 // MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+d" 548 // MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+c" 549 // MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+zicsr" 550 // MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+zifencei" 551 // MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-abi" "ilp32d" 552 553 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr4-rv32 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR4-RV32 %s 554 // MTUNE-SYNTACORE-SCR4-RV32: "-tune-cpu" "syntacore-scr4-rv32" 555 556 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr4-rv64 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR4-RV64 %s 557 // MCPU-SYNTACORE-SCR4-RV64: "-target-cpu" "syntacore-scr4-rv64" 558 // MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+m" 559 // MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+a" 560 // MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+f" 561 // MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+d" 562 // MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+c" 563 // MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+zicsr" 564 // MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+zifencei" 565 // MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-abi" "lp64d" 566 567 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr4-rv64 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR4-RV64 %s 568 // MTUNE-SYNTACORE-SCR4-RV64: "-tune-cpu" "syntacore-scr4-rv64" 569 570 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr5-rv32 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR5-RV32 %s 571 // MCPU-SYNTACORE-SCR5-RV32: "-target-cpu" "syntacore-scr5-rv32" 572 // MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+m" 573 // MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+a" 574 // MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+f" 575 // MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+d" 576 // MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+c" 577 // MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+zicsr" 578 // MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+zifencei" 579 // MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-abi" "ilp32d" 580 581 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr5-rv32 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR5-RV32 %s 582 // MTUNE-SYNTACORE-SCR5-RV32: "-tune-cpu" "syntacore-scr5-rv32" 583 584 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr5-rv64 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR5-RV64 %s 585 // MCPU-SYNTACORE-SCR5-RV64: "-target-cpu" "syntacore-scr5-rv64" 586 // MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+m" 587 // MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+a" 588 // MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+f" 589 // MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+d" 590 // MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+c" 591 // MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+zicsr" 592 // MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+zifencei" 593 // MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-abi" "lp64d" 594 595 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr5-rv64 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR5-RV64 %s 596 // MTUNE-SYNTACORE-SCR5-RV64: "-tune-cpu" "syntacore-scr5-rv64" 597 598 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr7 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR7 %s 599 // MCPU-SYNTACORE-SCR7: "-target-cpu" "syntacore-scr7" 600 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+m" 601 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+a" 602 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+f" 603 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+d" 604 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+c" 605 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+v" 606 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zicsr" 607 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zifencei" 608 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zba" 609 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbb" 610 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbc" 611 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkb" 612 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkc" 613 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkx" 614 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbs" 615 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zkn" 616 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zknd" 617 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zkne" 618 // MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zknh" 619 // MCPU-SYNTACORE-SCR7-SAME: "-target-abi" "lp64d" 620 621 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s 622 // MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7" 623