xref: /llvm-project/clang/test/CodeGenCUDA/unnamed-types.cu (revision 1b1c8d83d3567a60280291c0adb95d1d60335509)
1 // RUN: %clang_cc1 -std=c++11 -x hip -triple x86_64-linux-gnu -aux-triple amdgcn-amd-amdhsa -emit-llvm %s -o - | FileCheck %s --check-prefix=HOST
2 // RUN: %clang_cc1 -std=c++11 -x hip -triple x86_64-pc-windows-msvc -aux-triple amdgcn-amd-amdhsa -emit-llvm %s -o - | FileCheck %s --check-prefix=MSVC
3 // RUN: %clang_cc1 -std=c++11 -x hip -triple amdgcn-amd-amdhsa -fcuda-is-device -emit-llvm %s -o - | FileCheck %s --check-prefix=DEVICE
4 
5 #include "Inputs/cuda.h"
6 
7 // HOST: @0 = private unnamed_addr constant [43 x i8] c"_Z2k0IZZ2f1PfENKUlS0_E_clES0_EUlfE_EvS0_T_\00", align 1
8 // HOST: @1 = private unnamed_addr constant [60 x i8] c"_Z2k1IZ2f1PfEUlfE_Z2f1S0_EUlffE_Z2f1S0_EUlfE0_EvS0_T_T0_T1_\00", align 1
9 // Check that, on MSVC, the same device kernel mangling name is generated.
10 // MSVC: @0 = private unnamed_addr constant [43 x i8] c"_Z2k0IZZ2f1PfENKUlS0_E_clES0_EUlfE_EvS0_T_\00", align 1
11 // MSVC: @1 = private unnamed_addr constant [60 x i8] c"_Z2k1IZ2f1PfEUlfE_Z2f1S0_EUlffE_Z2f1S0_EUlfE0_EvS0_T_T0_T1_\00", align 1
12 
d0(float x)13 __device__ float d0(float x) {
14   return [](float x) { return x + 1.f; }(x);
15 }
16 
d1(float x)17 __device__ float d1(float x) {
18   return [](float x) { return x * 2.f; }(x);
19 }
20 
21 // DEVICE: amdgpu_kernel void @_Z2k0IZZ2f1PfENKUlS0_E_clES0_EUlfE_EvS0_T_(
22 // DEVICE: define internal noundef float @_ZZZ2f1PfENKUlS_E_clES_ENKUlfE_clEf(
23 template <typename F>
k0(float * p,F f)24 __global__ void k0(float *p, F f) {
25   p[0] = f(p[0]) + d0(p[1]) + d1(p[2]);
26 }
27 
28 // DEVICE: amdgpu_kernel void @_Z2k1IZ2f1PfEUlfE_Z2f1S0_EUlffE_Z2f1S0_EUlfE0_EvS0_T_T0_T1_(
29 // DEVICE: define internal noundef float @_ZZ2f1PfENKUlfE_clEf(
30 // DEVICE: define internal noundef float @_ZZ2f1PfENKUlffE_clEff(
31 // DEVICE: define internal noundef float @_ZZ2f1PfENKUlfE0_clEf(
32 template <typename F0, typename F1, typename F2>
k1(float * p,F0 f0,F1 f1,F2 f2)33 __global__ void k1(float *p, F0 f0, F1 f1, F2 f2) {
34   p[0] = f0(p[0]) + f1(p[1], p[2]) + f2(p[3]);
35 }
36 
f0(float * p)37 void f0(float *p) {
38   [](float *p) {
39     *p = 1.f;
40   }(p);
41 }
42 
43 // The inner/outer lambdas are required to be mangled following ODR but their
44 // linkages are still required to keep the original `internal` linkage.
45 
46 // HOST: define internal void @_ZZ2f1PfENKUlS_E_clES_(
f1(float * p)47 void f1(float *p) {
48   [](float *p) {
49     k0<<<1,1>>>(p, [] __device__ (float x) { return x + 3.f; });
50   }(p);
51   k1<<<1,1>>>(p,
52               [] __device__ (float x) { return x + 4.f; },
53               [] __device__ (float x, float y) { return x * y; },
54               [] __device__ (float x) { return x + 5.f; });
55 }
56 // HOST: @__hip_register_globals
57 // HOST: __hipRegisterFunction{{.*}}@_Z2k0IZZ2f1PfENKUlS0_E_clES0_EUlfE_EvS0_T_{{.*}}@0
58 // HOST: __hipRegisterFunction{{.*}}@_Z2k1IZ2f1PfEUlfE_Z2f1S0_EUlffE_Z2f1S0_EUlfE0_EvS0_T_T0_T1_{{.*}}@1
59 // MSVC: __hipRegisterFunction{{.*}}@"??$k0@V<lambda_1>@?0???R1?0??f1@@YAXPEAM@Z@QEBA@0@Z@@@YAXPEAMV<lambda_1>@?0???R0?0??f1@@YAX0@Z@QEBA@0@Z@@Z{{.*}}@0
60 // MSVC: __hipRegisterFunction{{.*}}@"??$k1@V<lambda_2>@?0??f1@@YAXPEAM@Z@V<lambda_3>@?0??2@YAX0@Z@V<lambda_4>@?0??2@YAX0@Z@@@YAXPEAMV<lambda_2>@?0??f1@@YAX0@Z@V<lambda_3>@?0??1@YAX0@Z@V<lambda_4>@?0??1@YAX0@Z@@Z{{.*}}@1
61