1 // RUN: %clang_cc1 -triple hexagon -target-cpu hexagonv68 -target-feature +hvxv68 -target-feature +hvx-length128b -emit-llvm -o - %s | FileCheck %s
2 // REQUIRES: hexagon-registered-target
3
4 typedef long HEXAGON_Vect1024 __attribute__((__vector_size__(128)))
5 __attribute__((aligned(128)));
6 typedef long HEXAGON_Vect2048 __attribute__((__vector_size__(256)))
7 __attribute__((aligned(128)));
8
9 // CHECK-LABEL: test0
10 // CHECK: call <64 x i32> @llvm.hexagon.V6.v6mpyhubs10.128B(<64 x i32> %{{.*}}, <64 x i32> %{{.*}}, i32 0)
test0(HEXAGON_Vect2048 Vuu,HEXAGON_Vect2048 Vvv)11 HEXAGON_Vect2048 test0(HEXAGON_Vect2048 Vuu, HEXAGON_Vect2048 Vvv) {
12 return __builtin_HEXAGON_V6_v6mpyhubs10_128B(Vuu, Vvv, 0);
13 }
14
15 // CHECK-LABEL: test1
16 // CHECK: call <64 x i32> @llvm.hexagon.V6.v6mpyhubs10.vxx.128B(<64 x i32> %{{.*}}, <64 x i32> %{{.*}}, <64 x i32> %{{.*}}, i32 1)
test1(HEXAGON_Vect2048 Vxx,HEXAGON_Vect2048 Vuu,HEXAGON_Vect2048 Vvv)17 HEXAGON_Vect2048 test1(HEXAGON_Vect2048 Vxx, HEXAGON_Vect2048 Vuu,
18 HEXAGON_Vect2048 Vvv) {
19 return __builtin_HEXAGON_V6_v6mpyhubs10_vxx_128B(Vxx, Vuu, Vvv, 1);
20 }
21
22 // CHECK-LABEL: test2
23 // CHECK: call <64 x i32> @llvm.hexagon.V6.v6mpyvubs10.128B(<64 x i32> %{{.*}}, <64 x i32> %{{.*}}, i32 2)
test2(HEXAGON_Vect2048 Vuu,HEXAGON_Vect2048 Vvv)24 HEXAGON_Vect2048 test2(HEXAGON_Vect2048 Vuu, HEXAGON_Vect2048 Vvv) {
25 return __builtin_HEXAGON_V6_v6mpyvubs10_128B(Vuu, Vvv, 2);
26 }
27
28 // CHECK-LABEL: test3
29 // CHECK: call <64 x i32> @llvm.hexagon.V6.v6mpyvubs10.vxx.128B(<64 x i32> %{{.*}}, <64 x i32> %{{.*}}, <64 x i32> %{{.*}}, i32 3)
test3(HEXAGON_Vect2048 Vxx,HEXAGON_Vect2048 Vuu,HEXAGON_Vect2048 Vvv)30 HEXAGON_Vect2048 test3(HEXAGON_Vect2048 Vxx, HEXAGON_Vect2048 Vuu,
31 HEXAGON_Vect2048 Vvv) {
32 return __builtin_HEXAGON_V6_v6mpyvubs10_vxx_128B(Vxx, Vuu, Vvv, 3);
33 }
34
35