1 // RUN: %clang_cc1 -O1 -triple x86_64 %s -emit-llvm -disable-llvm-passes -o - | FileCheck --check-prefixes=CHECK %s
2
3 // REQUIRES: aarch64-registered-target
4 // RUN: %clang_cc1 -O1 -triple aarch64 -target-feature +neon %s -emit-llvm -disable-llvm-passes -o - | FileCheck --check-prefixes=CHECK,NEON %s
5
6 // REQUIRES: aarch64-registered-target
7 // RUN: %clang_cc1 -O1 -triple aarch64 -target-feature +sve %s -emit-llvm -disable-llvm-passes -o - | FileCheck --check-prefixes=CHECK,SVE %s
8
9 // REQUIRES: riscv-registered-target
10 // RUN: %clang_cc1 -O1 -triple riscv64 -target-feature +v %s -emit-llvm -disable-llvm-passes -o - | FileCheck --check-prefixes=CHECK,RISCV %s
11
12 /// Note that this does not make sense to check for x86 SIMD types, because
13 /// __m128i, __m256i, and __m512i do not specify the element type. There are no
14 /// "logical" number of elements in them.
15
16 typedef int int1 __attribute__((vector_size(4)));
17 typedef int int4 __attribute__((vector_size(16)));
18 typedef int int8 __attribute__((vector_size(32)));
19 typedef int int16 __attribute__((vector_size(64)));
20 typedef float float2 __attribute__((vector_size(8)));
21 typedef long extLong4 __attribute__((ext_vector_type(4)));
22
23
test_builtin_vectorelements_int1()24 int test_builtin_vectorelements_int1() {
25 // CHECK-LABEL: i32 @test_builtin_vectorelements_int1(
26 // CHECK: ret i32 1
27 return __builtin_vectorelements(int1);
28 }
29
test_builtin_vectorelements_int4()30 int test_builtin_vectorelements_int4() {
31 // CHECK-LABEL: i32 @test_builtin_vectorelements_int4(
32 // CHECK: ret i32 4
33 return __builtin_vectorelements(int4);
34 }
35
test_builtin_vectorelements_int8()36 int test_builtin_vectorelements_int8() {
37 // CHECK-LABEL: i32 @test_builtin_vectorelements_int8(
38 // CHECK: ret i32 8
39 return __builtin_vectorelements(int8);
40 }
41
test_builtin_vectorelements_int16()42 int test_builtin_vectorelements_int16() {
43 // CHECK-LABEL: i32 @test_builtin_vectorelements_int16(
44 // CHECK: ret i32 16
45 return __builtin_vectorelements(int16);
46 }
47
test_builtin_vectorelements_float2()48 int test_builtin_vectorelements_float2() {
49 // CHECK-LABEL: i32 @test_builtin_vectorelements_float2(
50 // CHECK: ret i32 2
51 return __builtin_vectorelements(float2);
52 }
53
test_builtin_vectorelements_extLong4()54 int test_builtin_vectorelements_extLong4() {
55 // CHECK-LABEL: i32 @test_builtin_vectorelements_extLong4(
56 // CHECK: ret i32 4
57 return __builtin_vectorelements(extLong4);
58 }
59
test_builtin_vectorelements_multiply_constant()60 int test_builtin_vectorelements_multiply_constant() {
61 // CHECK-LABEL: i32 @test_builtin_vectorelements_multiply_constant(
62 // CHECK: ret i32 32
63 return __builtin_vectorelements(int16) * 2;
64 }
65
66 #if defined(__ARM_NEON)
67 #include <arm_neon.h>
68
test_builtin_vectorelements_neon32x4()69 int test_builtin_vectorelements_neon32x4() {
70 // NEON: i32 @test_builtin_vectorelements_neon32x4(
71 // NEON: ret i32 4
72 return __builtin_vectorelements(uint32x4_t);
73 }
74
test_builtin_vectorelements_neon64x1()75 int test_builtin_vectorelements_neon64x1() {
76 // NEON: i32 @test_builtin_vectorelements_neon64x1(
77 // NEON: ret i32 1
78 return __builtin_vectorelements(uint64x1_t);
79 }
80 #endif
81
82 #if defined(__ARM_FEATURE_SVE)
83 #include <arm_sve.h>
84
test_builtin_vectorelements_sve32()85 long test_builtin_vectorelements_sve32() {
86 // SVE: i64 @test_builtin_vectorelements_sve32(
87 // SVE: [[VSCALE:%.+]] = call i64 @llvm.vscale.i64()
88 // SVE: [[RES:%.+]] = mul i64 [[VSCALE]], 4
89 // SVE: ret i64 [[RES]]
90 return __builtin_vectorelements(svuint32_t);
91 }
92
test_builtin_vectorelements_sve8()93 long test_builtin_vectorelements_sve8() {
94 // SVE: i64 @test_builtin_vectorelements_sve8(
95 // SVE: [[VSCALE:%.+]] = call i64 @llvm.vscale.i64()
96 // SVE: [[RES:%.+]] = mul i64 [[VSCALE]], 16
97 // SVE: ret i64 [[RES]]
98 return __builtin_vectorelements(svuint8_t);
99 }
100 #endif
101
102 #if defined(__riscv)
103 #include <riscv_vector.h>
104
test_builtin_vectorelements_riscv8()105 long test_builtin_vectorelements_riscv8() {
106 // RISCV: i64 @test_builtin_vectorelements_riscv8(
107 // RISCV: [[VSCALE:%.+]] = call i64 @llvm.vscale.i64()
108 // RISCV: [[RES:%.+]] = mul i64 [[VSCALE]], 8
109 // RISCV: ret i64 [[RES]]
110 return __builtin_vectorelements(vuint8m1_t);
111 }
112
test_builtin_vectorelements_riscv64()113 long test_builtin_vectorelements_riscv64() {
114 // RISCV: i64 @test_builtin_vectorelements_riscv64(
115 // RISCV: [[VSCALE:%.+]] = call i64 @llvm.vscale.i64()
116 // RISCV: ret i64 [[VSCALE]]
117 return __builtin_vectorelements(vuint64m1_t);
118 }
119
test_builtin_vectorelements_riscv32m2()120 long test_builtin_vectorelements_riscv32m2() {
121 // RISCV: i64 @test_builtin_vectorelements_riscv32m2(
122 // RISCV: [[VSCALE:%.+]] = call i64 @llvm.vscale.i64()
123 // RISCV: [[RES:%.+]] = mul i64 [[VSCALE]], 4
124 // RISCV: ret i64 [[RES]]
125 return __builtin_vectorelements(vuint32m2_t);
126 }
127 #endif
128