1 // RUN: %clang_cc1 %s -emit-llvm -o - -triple=arm64-apple-ios7 | FileCheck %s
2
3 // Memory ordering values.
4 enum {
5 memory_order_relaxed = 0,
6 memory_order_consume = 1,
7 memory_order_acquire = 2,
8 memory_order_release = 3,
9 memory_order_acq_rel = 4,
10 memory_order_seq_cst = 5
11 };
12
13 typedef struct { void *a, *b; } pointer_pair_t;
14 typedef struct { void *a, *b, *c, *d; } pointer_quad_t;
15
16 extern _Atomic(_Bool) a_bool;
17 extern _Atomic(float) a_float;
18 extern _Atomic(void*) a_pointer;
19 extern _Atomic(pointer_pair_t) a_pointer_pair;
20 extern _Atomic(pointer_quad_t) a_pointer_quad;
21
22 // CHECK-LABEL:define{{.*}} void @test0()
23 // CHECK: [[TEMP:%.*]] = alloca i8, align 1
24 // CHECK-NEXT: store i8 1, ptr [[TEMP]]
25 // CHECK-NEXT: [[T0:%.*]] = load i8, ptr [[TEMP]], align 1
26 // CHECK-NEXT: store atomic i8 [[T0]], ptr @a_bool seq_cst, align 1
test0(void)27 void test0(void) {
28 __c11_atomic_store(&a_bool, 1, memory_order_seq_cst);
29 }
30
31 // CHECK-LABEL:define{{.*}} void @test1()
32 // CHECK: [[TEMP:%.*]] = alloca float, align 4
33 // CHECK-NEXT: store float 3.000000e+00, ptr [[TEMP]]
34 // CHECK-NEXT: [[T1:%.*]] = load i32, ptr [[TEMP]], align 4
35 // CHECK-NEXT: store atomic i32 [[T1]], ptr @a_float seq_cst, align 4
test1(void)36 void test1(void) {
37 __c11_atomic_store(&a_float, 3, memory_order_seq_cst);
38 }
39
40 // CHECK-LABEL:define{{.*}} void @test2()
41 // CHECK: [[TEMP:%.*]] = alloca ptr, align 8
42 // CHECK-NEXT: store ptr @a_bool, ptr [[TEMP]]
43 // CHECK-NEXT: [[T1:%.*]] = load i64, ptr [[TEMP]], align 8
44 // CHECK-NEXT: store atomic i64 [[T1]], ptr @a_pointer seq_cst, align 8
test2(void)45 void test2(void) {
46 __c11_atomic_store(&a_pointer, &a_bool, memory_order_seq_cst);
47 }
48
49 // CHECK-LABEL:define{{.*}} void @test3(
50 // CHECK: [[PAIR:%.*]] = alloca [[PAIR_T:%.*]], align 8
51 // CHECK-NEXT: [[TEMP:%.*]] = alloca [[PAIR_T]], align 8
52 // CHECK: llvm.memcpy
53 // CHECK-NEXT: [[T1:%.*]] = load i128, ptr [[TEMP]], align 8
54 // CHECK-NEXT: store atomic i128 [[T1]], ptr @a_pointer_pair seq_cst, align 16
test3(pointer_pair_t pair)55 void test3(pointer_pair_t pair) {
56 __c11_atomic_store(&a_pointer_pair, pair, memory_order_seq_cst);
57 }
58
59 // CHECK-LABEL:define{{.*}} void @test4(
60 // CHECK-SAME: ptr noundef [[QUAD:%.*]])
61 // CHECK: [[QUAD_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
62 // CHECK-NEXT: [[TEMP:%.*]] = alloca [[QUAD_T:%.*]], align 8
63 // CHECK-NEXT: store ptr [[QUAD]], ptr [[QUAD_INDIRECT_ADDR]]
64 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TEMP]], ptr align 8 {{%.*}}, i64 32, i1 false)
65 // CHECK-NEXT: call void @__atomic_store(i64 noundef 32, ptr noundef @a_pointer_quad, ptr noundef [[TEMP]], i32 noundef 5)
test4(pointer_quad_t quad)66 void test4(pointer_quad_t quad) {
67 __c11_atomic_store(&a_pointer_quad, quad, memory_order_seq_cst);
68 }
69