1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi \
3 // RUN: -target-feature +cdecp0 -target-feature +cdecp1 \
4 // RUN: -mfloat-abi hard -O0 -disable-O0-optnone \
5 // RUN: -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s
6
7 // REQUIRES: aarch64-registered-target || arm-registered-target
8
9 #include <arm_cde.h>
10
11 // CHECK-LABEL: @test_cx1(
12 // CHECK-NEXT: entry:
13 // CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.cde.cx1(i32 0, i32 123)
14 // CHECK-NEXT: ret i32 [[TMP0]]
15 //
test_cx1(void)16 uint32_t test_cx1(void) {
17 return __arm_cx1(0, 123);
18 }
19
20 // CHECK-LABEL: @test_cx1a(
21 // CHECK-NEXT: entry:
22 // CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.cde.cx1a(i32 0, i32 [[ACC:%.*]], i32 345)
23 // CHECK-NEXT: ret i32 [[TMP0]]
24 //
test_cx1a(uint32_t acc)25 uint32_t test_cx1a(uint32_t acc) {
26 return __arm_cx1a(0, acc, 345);
27 }
28
29 // CHECK-LABEL: @test_cx1d(
30 // CHECK-NEXT: entry:
31 // CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.cde.cx1d(i32 1, i32 567)
32 // CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1
33 // CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
34 // CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32
35 // CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0
36 // CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
37 // CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]
38 // CHECK-NEXT: ret i64 [[TMP6]]
39 //
test_cx1d(void)40 uint64_t test_cx1d(void) {
41 return __arm_cx1d(1, 567);
42 }
43
44 // CHECK-LABEL: @test_cx1da(
45 // CHECK-NEXT: entry:
46 // CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[ACC:%.*]], 32
47 // CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
48 // CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[ACC]] to i32
49 // CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.cde.cx1da(i32 0, i32 [[TMP2]], i32 [[TMP1]], i32 789)
50 // CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 1
51 // CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
52 // CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 32
53 // CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 0
54 // CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
55 // CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]
56 // CHECK-NEXT: ret i64 [[TMP9]]
57 //
test_cx1da(uint64_t acc)58 uint64_t test_cx1da(uint64_t acc) {
59 return __arm_cx1da(0, acc, 789);
60 }
61
62 // CHECK-LABEL: @test_cx2(
63 // CHECK-NEXT: entry:
64 // CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.cde.cx2(i32 0, i32 [[N:%.*]], i32 11)
65 // CHECK-NEXT: ret i32 [[TMP0]]
66 //
test_cx2(uint32_t n)67 uint32_t test_cx2(uint32_t n) {
68 return __arm_cx2(0, n, 11);
69 }
70
71 // CHECK-LABEL: @test_cx2a(
72 // CHECK-NEXT: entry:
73 // CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.cde.cx2a(i32 1, i32 [[ACC:%.*]], i32 [[N:%.*]], i32 22)
74 // CHECK-NEXT: ret i32 [[TMP0]]
75 //
test_cx2a(uint32_t acc,uint32_t n)76 uint32_t test_cx2a(uint32_t acc, uint32_t n) {
77 return __arm_cx2a(1, acc, n, 22);
78 }
79
80 // CHECK-LABEL: @test_cx2d(
81 // CHECK-NEXT: entry:
82 // CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.cde.cx2d(i32 1, i32 [[N:%.*]], i32 33)
83 // CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1
84 // CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
85 // CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32
86 // CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0
87 // CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
88 // CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]
89 // CHECK-NEXT: ret i64 [[TMP6]]
90 //
test_cx2d(uint32_t n)91 uint64_t test_cx2d(uint32_t n) {
92 return __arm_cx2d(1, n, 33);
93 }
94
95 // CHECK-LABEL: @test_cx2da(
96 // CHECK-NEXT: entry:
97 // CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[ACC:%.*]], 32
98 // CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
99 // CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[ACC]] to i32
100 // CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.cde.cx2da(i32 0, i32 [[TMP2]], i32 [[TMP1]], i32 [[N:%.*]], i32 44)
101 // CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 1
102 // CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
103 // CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 32
104 // CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 0
105 // CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
106 // CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]
107 // CHECK-NEXT: ret i64 [[TMP9]]
108 //
test_cx2da(uint64_t acc,uint32_t n)109 uint64_t test_cx2da(uint64_t acc, uint32_t n) {
110 return __arm_cx2da(0, acc, n, 44);
111 }
112
113 // CHECK-LABEL: @test_cx3(
114 // CHECK-NEXT: entry:
115 // CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.cde.cx3(i32 0, i32 [[N:%.*]], i32 [[M:%.*]], i32 1)
116 // CHECK-NEXT: ret i32 [[TMP0]]
117 //
test_cx3(uint32_t n,uint32_t m)118 uint32_t test_cx3(uint32_t n, uint32_t m) {
119 return __arm_cx3(0, n, m, 1);
120 }
121
122 // CHECK-LABEL: @test_cx3a(
123 // CHECK-NEXT: entry:
124 // CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.cde.cx3a(i32 1, i32 [[ACC:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 2)
125 // CHECK-NEXT: ret i32 [[TMP0]]
126 //
test_cx3a(uint32_t acc,uint32_t n,uint32_t m)127 uint32_t test_cx3a(uint32_t acc, uint32_t n, uint32_t m) {
128 return __arm_cx3a(1, acc, n, m, 2);
129 }
130
131 // CHECK-LABEL: @test_cx3d(
132 // CHECK-NEXT: entry:
133 // CHECK-NEXT: [[TMP0:%.*]] = call { i32, i32 } @llvm.arm.cde.cx3d(i32 1, i32 [[N:%.*]], i32 [[M:%.*]], i32 3)
134 // CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1
135 // CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
136 // CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 32
137 // CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0
138 // CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
139 // CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]
140 // CHECK-NEXT: ret i64 [[TMP6]]
141 //
test_cx3d(uint32_t n,uint32_t m)142 uint64_t test_cx3d(uint32_t n, uint32_t m) {
143 return __arm_cx3d(1, n, m, 3);
144 }
145
146 // CHECK-LABEL: @test_cx3da(
147 // CHECK-NEXT: entry:
148 // CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[ACC:%.*]], 32
149 // CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
150 // CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[ACC]] to i32
151 // CHECK-NEXT: [[TMP3:%.*]] = call { i32, i32 } @llvm.arm.cde.cx3da(i32 0, i32 [[TMP2]], i32 [[TMP1]], i32 [[N:%.*]], i32 [[M:%.*]], i32 4)
152 // CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 1
153 // CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
154 // CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 32
155 // CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 0
156 // CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
157 // CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP6]], [[TMP8]]
158 // CHECK-NEXT: ret i64 [[TMP9]]
159 //
test_cx3da(uint64_t acc,uint32_t n,uint32_t m)160 uint64_t test_cx3da(uint64_t acc, uint32_t n, uint32_t m) {
161 return __arm_cx3da(0, acc, n, m, 4);
162 }
163