1 // REQUIRES: riscv-registered-target 2 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ 3 // RUN: -target-feature +v \ 4 // RUN: -target-feature +xsfvcp \ 5 // RUN: -fsyntax-only -verify %s 6 // expected-no-diagnostics 7 8 #include <sifive_vector.h> 9 10 #define p27_26 (0b11) 11 #define p11_7 (0b11111) 12 test_sf_vc_xv_se_u64m1(vuint64m1_t vs2,uint64_t rs1,size_t vl)13void test_sf_vc_xv_se_u64m1(vuint64m1_t vs2, uint64_t rs1, size_t vl) { 14 __riscv_sf_vc_xv_se_u64m1(p27_26, p11_7, vs2, rs1, vl); 15 } 16