xref: /llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfnmacc-out-of-range.c (revision 3055c5815ac08aa0d8597bff63569b9ed8ec0822)
1 // REQUIRES: riscv-registered-target
2 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
3 // RUN:   -target-feature +v -target-feature +zfh -target-feature +zvfh \
4 // RUN:   -fsyntax-only -verify %s
5 
6 #include <riscv_vector.h>
7 
8 
test_vfnmacc_vv_f32m1_rm(vfloat32m1_t vd,vfloat32m1_t vs1,vfloat32m1_t vs2,size_t vl)9 vfloat32m1_t test_vfnmacc_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
10   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
11   return __riscv_vfnmacc_vv_f32m1_rm(vd, vs1, vs2, 5, vl);
12 }
13 
test_vfnmacc_vf_f32m1_rm(vfloat32m1_t vd,float rs1,vfloat32m1_t vs2,size_t vl)14 vfloat32m1_t test_vfnmacc_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
15   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
16   return __riscv_vfnmacc_vf_f32m1_rm(vd, rs1, vs2, 5, vl);
17 }
18 
test_vfnmacc_vv_f32m1_rm_m(vbool32_t mask,vfloat32m1_t vd,vfloat32m1_t vs1,vfloat32m1_t vs2,size_t vl)19 vfloat32m1_t test_vfnmacc_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
20   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
21   return __riscv_vfnmacc_vv_f32m1_rm_m(mask, vd, vs1, vs2, 5, vl);
22 }
23 
test_vfnmacc_vf_f32m1_rm_m(vbool32_t mask,vfloat32m1_t vd,float rs1,vfloat32m1_t vs2,size_t vl)24 vfloat32m1_t test_vfnmacc_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
25   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
26   return __riscv_vfnmacc_vf_f32m1_rm_m(mask, vd, rs1, vs2, 5, vl);
27 }
28 
test_vfnmacc_vv_f32m1_rm_tu(vfloat32m1_t vd,vfloat32m1_t vs1,vfloat32m1_t vs2,size_t vl)29 vfloat32m1_t test_vfnmacc_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
30   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
31   return __riscv_vfnmacc_vv_f32m1_rm_tu(vd, vs1, vs2, 5, vl);
32 }
33 
test_vfnmacc_vf_f32m1_rm_tu(vfloat32m1_t vd,float rs1,vfloat32m1_t vs2,size_t vl)34 vfloat32m1_t test_vfnmacc_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
35   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
36   return __riscv_vfnmacc_vf_f32m1_rm_tu(vd, rs1, vs2, 5, vl);
37 }
38 
test_vfnmacc_vv_f32m1_rm_tum(vbool32_t mask,vfloat32m1_t vd,vfloat32m1_t vs1,vfloat32m1_t vs2,size_t vl)39 vfloat32m1_t test_vfnmacc_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
40   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
41   return __riscv_vfnmacc_vv_f32m1_rm_tum(mask, vd, vs1, vs2, 5, vl);
42 }
43 
test_vfnmacc_vf_f32m1_rm_tum(vbool32_t mask,vfloat32m1_t vd,float rs1,vfloat32m1_t vs2,size_t vl)44 vfloat32m1_t test_vfnmacc_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
45   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
46   return __riscv_vfnmacc_vf_f32m1_rm_tum(mask, vd, rs1, vs2, 5, vl);
47 }
48 
test_vfnmacc_vv_f32m1_rm_tumu(vbool32_t mask,vfloat32m1_t vd,vfloat32m1_t vs1,vfloat32m1_t vs2,size_t vl)49 vfloat32m1_t test_vfnmacc_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
50   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
51   return __riscv_vfnmacc_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, 5, vl);
52 }
53 
test_vfnmacc_vf_f32m1_rm_tumu(vbool32_t mask,vfloat32m1_t vd,float rs1,vfloat32m1_t vs2,size_t vl)54 vfloat32m1_t test_vfnmacc_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
55   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
56   return __riscv_vfnmacc_vf_f32m1_rm_tumu(mask, vd, rs1, vs2, 5, vl);
57 }
58 
test_vfnmacc_vv_f32m1_rm_mu(vbool32_t mask,vfloat32m1_t vd,vfloat32m1_t vs1,vfloat32m1_t vs2,size_t vl)59 vfloat32m1_t test_vfnmacc_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
60   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
61   return __riscv_vfnmacc_vv_f32m1_rm_mu(mask, vd, vs1, vs2, 5, vl);
62 }
63 
test_vfnmacc_vf_f32m1_rm_mu(vbool32_t mask,vfloat32m1_t vd,float rs1,vfloat32m1_t vs2,size_t vl)64 vfloat32m1_t test_vfnmacc_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
65   // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
66   return __riscv_vfnmacc_vf_f32m1_rm_mu(mask, vd, rs1, vs2, 5, vl);
67 }
68