1 // REQUIRES: riscv-registered-target
2 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
3 // RUN: -target-feature +v -target-feature +zfh -target-feature +zvfh \
4 // RUN: -fsyntax-only -verify %s
5
6 #include <riscv_vector.h>
7
test_vfcvt_x_f_v_i32m1_rm(vfloat32m1_t src,size_t vl)8 vint32m1_t test_vfcvt_x_f_v_i32m1_rm(vfloat32m1_t src, size_t vl) {
9 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
10 return __riscv_vfcvt_x_f_v_i32m1_rm(src, 5, vl);
11 }
12
test_vfcvt_xu_f_v_u32m1_rm(vfloat32m1_t src,size_t vl)13 vuint32m1_t test_vfcvt_xu_f_v_u32m1_rm(vfloat32m1_t src, size_t vl) {
14 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
15 return __riscv_vfcvt_xu_f_v_u32m1_rm(src, 5, vl);
16 }
17
test_vfcvt_f_x_v_f32m1_rm(vint32m1_t src,size_t vl)18 vfloat32m1_t test_vfcvt_f_x_v_f32m1_rm(vint32m1_t src, size_t vl) {
19 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
20 return __riscv_vfcvt_f_x_v_f32m1_rm(src, 5, vl);
21 }
22
test_vfcvt_f_xu_v_f32m1_rm(vuint32m1_t src,size_t vl)23 vfloat32m1_t test_vfcvt_f_xu_v_f32m1_rm(vuint32m1_t src, size_t vl) {
24 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
25 return __riscv_vfcvt_f_xu_v_f32m1_rm(src, 5, vl);
26 }
27
test_vfcvt_x_f_v_i32m1_rm_m(vbool32_t mask,vfloat32m1_t src,size_t vl)28 vint32m1_t test_vfcvt_x_f_v_i32m1_rm_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {
29 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
30 return __riscv_vfcvt_x_f_v_i32m1_rm_m(mask, src, 5, vl);
31 }
32
test_vfcvt_xu_f_v_u32m1_rm_m(vbool32_t mask,vfloat32m1_t src,size_t vl)33 vuint32m1_t test_vfcvt_xu_f_v_u32m1_rm_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {
34 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
35 return __riscv_vfcvt_xu_f_v_u32m1_rm_m(mask, src, 5, vl);
36 }
37
test_vfcvt_f_x_v_f32m1_rm_m(vbool32_t mask,vint32m1_t src,size_t vl)38 vfloat32m1_t test_vfcvt_f_x_v_f32m1_rm_m(vbool32_t mask, vint32m1_t src, size_t vl) {
39 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
40 return __riscv_vfcvt_f_x_v_f32m1_rm_m(mask, src, 5, vl);
41 }
42
test_vfcvt_f_xu_v_f32m1_rm_m(vbool32_t mask,vuint32m1_t src,size_t vl)43 vfloat32m1_t test_vfcvt_f_xu_v_f32m1_rm_m(vbool32_t mask, vuint32m1_t src, size_t vl) {
44 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
45 return __riscv_vfcvt_f_xu_v_f32m1_rm_m(mask, src, 5, vl);
46 }
47
test_vfcvt_x_f_v_i32m1_rm_tu(vint32m1_t maskedoff,vfloat32m1_t src,size_t vl)48 vint32m1_t test_vfcvt_x_f_v_i32m1_rm_tu(vint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
49 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
50 return __riscv_vfcvt_x_f_v_i32m1_rm_tu(maskedoff, src, 5, vl);
51 }
52
test_vfcvt_xu_f_v_u32m1_rm_tu(vuint32m1_t maskedoff,vfloat32m1_t src,size_t vl)53 vuint32m1_t test_vfcvt_xu_f_v_u32m1_rm_tu(vuint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
54 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
55 return __riscv_vfcvt_xu_f_v_u32m1_rm_tu(maskedoff, src, 5, vl);
56 }
57
test_vfcvt_f_x_v_f32m1_rm_tu(vfloat32m1_t maskedoff,vint32m1_t src,size_t vl)58 vfloat32m1_t test_vfcvt_f_x_v_f32m1_rm_tu(vfloat32m1_t maskedoff, vint32m1_t src, size_t vl) {
59 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
60 return __riscv_vfcvt_f_x_v_f32m1_rm_tu(maskedoff, src, 5, vl);
61 }
62
test_vfcvt_f_xu_v_f32m1_rm_tu(vfloat32m1_t maskedoff,vuint32m1_t src,size_t vl)63 vfloat32m1_t test_vfcvt_f_xu_v_f32m1_rm_tu(vfloat32m1_t maskedoff, vuint32m1_t src, size_t vl) {
64 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
65 return __riscv_vfcvt_f_xu_v_f32m1_rm_tu(maskedoff, src, 5, vl);
66 }
67
test_vfcvt_x_f_v_i32m1_rm_tum(vbool32_t mask,vint32m1_t maskedoff,vfloat32m1_t src,size_t vl)68 vint32m1_t test_vfcvt_x_f_v_i32m1_rm_tum(vbool32_t mask, vint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
69 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
70 return __riscv_vfcvt_x_f_v_i32m1_rm_tum(mask, maskedoff, src, 5, vl);
71 }
72
test_vfcvt_xu_f_v_u32m1_rm_tum(vbool32_t mask,vuint32m1_t maskedoff,vfloat32m1_t src,size_t vl)73 vuint32m1_t test_vfcvt_xu_f_v_u32m1_rm_tum(vbool32_t mask, vuint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
74 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
75 return __riscv_vfcvt_xu_f_v_u32m1_rm_tum(mask, maskedoff, src, 5, vl);
76 }
77
test_vfcvt_f_x_v_f32m1_rm_tum(vbool32_t mask,vfloat32m1_t maskedoff,vint32m1_t src,size_t vl)78 vfloat32m1_t test_vfcvt_f_x_v_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vint32m1_t src, size_t vl) {
79 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
80 return __riscv_vfcvt_f_x_v_f32m1_rm_tum(mask, maskedoff, src, 5, vl);
81 }
82
test_vfcvt_f_xu_v_f32m1_rm_tum(vbool32_t mask,vfloat32m1_t maskedoff,vuint32m1_t src,size_t vl)83 vfloat32m1_t test_vfcvt_f_xu_v_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vuint32m1_t src, size_t vl) {
84 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
85 return __riscv_vfcvt_f_xu_v_f32m1_rm_tum(mask, maskedoff, src, 5, vl);
86 }
87
test_vfcvt_x_f_v_i32m1_rm_tumu(vbool32_t mask,vint32m1_t maskedoff,vfloat32m1_t src,size_t vl)88 vint32m1_t test_vfcvt_x_f_v_i32m1_rm_tumu(vbool32_t mask, vint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
89 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
90 return __riscv_vfcvt_x_f_v_i32m1_rm_tumu(mask, maskedoff, src, 5, vl);
91 }
92
test_vfcvt_xu_f_v_u32m1_rm_tumu(vbool32_t mask,vuint32m1_t maskedoff,vfloat32m1_t src,size_t vl)93 vuint32m1_t test_vfcvt_xu_f_v_u32m1_rm_tumu(vbool32_t mask, vuint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
94 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
95 return __riscv_vfcvt_xu_f_v_u32m1_rm_tumu(mask, maskedoff, src, 5, vl);
96 }
97
test_vfcvt_f_x_v_f32m1_rm_tumu(vbool32_t mask,vfloat32m1_t maskedoff,vint32m1_t src,size_t vl)98 vfloat32m1_t test_vfcvt_f_x_v_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vint32m1_t src, size_t vl) {
99 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
100 return __riscv_vfcvt_f_x_v_f32m1_rm_tumu(mask, maskedoff, src, 5, vl);
101 }
102
test_vfcvt_f_xu_v_f32m1_rm_tumu(vbool32_t mask,vfloat32m1_t maskedoff,vuint32m1_t src,size_t vl)103 vfloat32m1_t test_vfcvt_f_xu_v_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vuint32m1_t src, size_t vl) {
104 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
105 return __riscv_vfcvt_f_xu_v_f32m1_rm_tumu(mask, maskedoff, src, 5, vl);
106 }
107
test_vfcvt_x_f_v_i32m1_rm_mu(vbool32_t mask,vint32m1_t maskedoff,vfloat32m1_t src,size_t vl)108 vint32m1_t test_vfcvt_x_f_v_i32m1_rm_mu(vbool32_t mask, vint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
109 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
110 return __riscv_vfcvt_x_f_v_i32m1_rm_mu(mask, maskedoff, src, 5, vl);
111 }
112
test_vfcvt_xu_f_v_u32m1_rm_mu(vbool32_t mask,vuint32m1_t maskedoff,vfloat32m1_t src,size_t vl)113 vuint32m1_t test_vfcvt_xu_f_v_u32m1_rm_mu(vbool32_t mask, vuint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
114 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
115 return __riscv_vfcvt_xu_f_v_u32m1_rm_mu(mask, maskedoff, src, 5, vl);
116 }
117
test_vfcvt_f_x_v_f32m1_rm_mu(vbool32_t mask,vfloat32m1_t maskedoff,vint32m1_t src,size_t vl)118 vfloat32m1_t test_vfcvt_f_x_v_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vint32m1_t src, size_t vl) {
119 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
120 return __riscv_vfcvt_f_x_v_f32m1_rm_mu(mask, maskedoff, src, 5, vl);
121 }
122
test_vfcvt_f_xu_v_f32m1_rm_mu(vbool32_t mask,vfloat32m1_t maskedoff,vuint32m1_t src,size_t vl)123 vfloat32m1_t test_vfcvt_f_xu_v_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vuint32m1_t src, size_t vl) {
124 // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
125 return __riscv_vfcvt_f_xu_v_f32m1_rm_mu(mask, maskedoff, src, 5, vl);
126 }
127