1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
4 // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
5 // RUN: FileCheck --check-prefix=CHECK-RV64 %s
6
7 #include <riscv_vector.h>
8
9 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8_tu
10 // CHECK-RV64-SAME: (<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
11 // CHECK-RV64-NEXT: entry:
12 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], i64 [[VL]])
13 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
14 //
test_vmulhsu_vv_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)15 vint8mf8_t test_vmulhsu_vv_i8mf8_tu(vint8mf8_t maskedoff, vint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
16 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
17 }
18
19 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8_tu
20 // CHECK-RV64-SAME: (<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
21 // CHECK-RV64-NEXT: entry:
22 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
23 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
24 //
test_vmulhsu_vx_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,uint8_t op2,size_t vl)25 vint8mf8_t test_vmulhsu_vx_i8mf8_tu(vint8mf8_t maskedoff, vint8mf8_t op1, uint8_t op2, size_t vl) {
26 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
27 }
28
29 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4_tu
30 // CHECK-RV64-SAME: (<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
31 // CHECK-RV64-NEXT: entry:
32 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], i64 [[VL]])
33 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
34 //
test_vmulhsu_vv_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)35 vint8mf4_t test_vmulhsu_vv_i8mf4_tu(vint8mf4_t maskedoff, vint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
36 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
37 }
38
39 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4_tu
40 // CHECK-RV64-SAME: (<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
41 // CHECK-RV64-NEXT: entry:
42 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
43 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
44 //
test_vmulhsu_vx_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,uint8_t op2,size_t vl)45 vint8mf4_t test_vmulhsu_vx_i8mf4_tu(vint8mf4_t maskedoff, vint8mf4_t op1, uint8_t op2, size_t vl) {
46 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
47 }
48
49 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2_tu
50 // CHECK-RV64-SAME: (<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
51 // CHECK-RV64-NEXT: entry:
52 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], i64 [[VL]])
53 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
54 //
test_vmulhsu_vv_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)55 vint8mf2_t test_vmulhsu_vv_i8mf2_tu(vint8mf2_t maskedoff, vint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
56 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
57 }
58
59 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2_tu
60 // CHECK-RV64-SAME: (<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
61 // CHECK-RV64-NEXT: entry:
62 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
63 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
64 //
test_vmulhsu_vx_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,uint8_t op2,size_t vl)65 vint8mf2_t test_vmulhsu_vx_i8mf2_tu(vint8mf2_t maskedoff, vint8mf2_t op1, uint8_t op2, size_t vl) {
66 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
67 }
68
69 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1_tu
70 // CHECK-RV64-SAME: (<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
71 // CHECK-RV64-NEXT: entry:
72 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], i64 [[VL]])
73 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
74 //
test_vmulhsu_vv_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,vuint8m1_t op2,size_t vl)75 vint8m1_t test_vmulhsu_vv_i8m1_tu(vint8m1_t maskedoff, vint8m1_t op1, vuint8m1_t op2, size_t vl) {
76 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
77 }
78
79 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1_tu
80 // CHECK-RV64-SAME: (<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
81 // CHECK-RV64-NEXT: entry:
82 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
83 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
84 //
test_vmulhsu_vx_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,uint8_t op2,size_t vl)85 vint8m1_t test_vmulhsu_vx_i8m1_tu(vint8m1_t maskedoff, vint8m1_t op1, uint8_t op2, size_t vl) {
86 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
87 }
88
89 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2_tu
90 // CHECK-RV64-SAME: (<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
91 // CHECK-RV64-NEXT: entry:
92 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], i64 [[VL]])
93 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
94 //
test_vmulhsu_vv_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,vuint8m2_t op2,size_t vl)95 vint8m2_t test_vmulhsu_vv_i8m2_tu(vint8m2_t maskedoff, vint8m2_t op1, vuint8m2_t op2, size_t vl) {
96 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
97 }
98
99 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2_tu
100 // CHECK-RV64-SAME: (<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
101 // CHECK-RV64-NEXT: entry:
102 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
103 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
104 //
test_vmulhsu_vx_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,uint8_t op2,size_t vl)105 vint8m2_t test_vmulhsu_vx_i8m2_tu(vint8m2_t maskedoff, vint8m2_t op1, uint8_t op2, size_t vl) {
106 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
107 }
108
109 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4_tu
110 // CHECK-RV64-SAME: (<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
111 // CHECK-RV64-NEXT: entry:
112 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], i64 [[VL]])
113 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
114 //
test_vmulhsu_vv_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,vuint8m4_t op2,size_t vl)115 vint8m4_t test_vmulhsu_vv_i8m4_tu(vint8m4_t maskedoff, vint8m4_t op1, vuint8m4_t op2, size_t vl) {
116 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
117 }
118
119 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmulhsu_vx_i8m4_tu
120 // CHECK-RV64-SAME: (<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
121 // CHECK-RV64-NEXT: entry:
122 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
123 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
124 //
test_vmulhsu_vx_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,uint8_t op2,size_t vl)125 vint8m4_t test_vmulhsu_vx_i8m4_tu(vint8m4_t maskedoff, vint8m4_t op1, uint8_t op2, size_t vl) {
126 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
127 }
128
129 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmulhsu_vv_i8m8_tu
130 // CHECK-RV64-SAME: (<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
131 // CHECK-RV64-NEXT: entry:
132 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], i64 [[VL]])
133 // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
134 //
test_vmulhsu_vv_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,vuint8m8_t op2,size_t vl)135 vint8m8_t test_vmulhsu_vv_i8m8_tu(vint8m8_t maskedoff, vint8m8_t op1, vuint8m8_t op2, size_t vl) {
136 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
137 }
138
139 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmulhsu_vx_i8m8_tu
140 // CHECK-RV64-SAME: (<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
141 // CHECK-RV64-NEXT: entry:
142 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
143 // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
144 //
test_vmulhsu_vx_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,uint8_t op2,size_t vl)145 vint8m8_t test_vmulhsu_vx_i8m8_tu(vint8m8_t maskedoff, vint8m8_t op1, uint8_t op2, size_t vl) {
146 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
147 }
148
149 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmulhsu_vv_i16mf4_tu
150 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
151 // CHECK-RV64-NEXT: entry:
152 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], i64 [[VL]])
153 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
154 //
test_vmulhsu_vv_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)155 vint16mf4_t test_vmulhsu_vv_i16mf4_tu(vint16mf4_t maskedoff, vint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
156 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
157 }
158
159 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmulhsu_vx_i16mf4_tu
160 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
161 // CHECK-RV64-NEXT: entry:
162 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
163 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
164 //
test_vmulhsu_vx_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,uint16_t op2,size_t vl)165 vint16mf4_t test_vmulhsu_vx_i16mf4_tu(vint16mf4_t maskedoff, vint16mf4_t op1, uint16_t op2, size_t vl) {
166 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
167 }
168
169 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmulhsu_vv_i16mf2_tu
170 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
171 // CHECK-RV64-NEXT: entry:
172 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], i64 [[VL]])
173 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
174 //
test_vmulhsu_vv_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)175 vint16mf2_t test_vmulhsu_vv_i16mf2_tu(vint16mf2_t maskedoff, vint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
176 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
177 }
178
179 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmulhsu_vx_i16mf2_tu
180 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
181 // CHECK-RV64-NEXT: entry:
182 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
183 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
184 //
test_vmulhsu_vx_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,uint16_t op2,size_t vl)185 vint16mf2_t test_vmulhsu_vx_i16mf2_tu(vint16mf2_t maskedoff, vint16mf2_t op1, uint16_t op2, size_t vl) {
186 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
187 }
188
189 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmulhsu_vv_i16m1_tu
190 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
191 // CHECK-RV64-NEXT: entry:
192 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmulhsu.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], i64 [[VL]])
193 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
194 //
test_vmulhsu_vv_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,vuint16m1_t op2,size_t vl)195 vint16m1_t test_vmulhsu_vv_i16m1_tu(vint16m1_t maskedoff, vint16m1_t op1, vuint16m1_t op2, size_t vl) {
196 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
197 }
198
199 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmulhsu_vx_i16m1_tu
200 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
201 // CHECK-RV64-NEXT: entry:
202 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmulhsu.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
203 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
204 //
test_vmulhsu_vx_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,uint16_t op2,size_t vl)205 vint16m1_t test_vmulhsu_vx_i16m1_tu(vint16m1_t maskedoff, vint16m1_t op1, uint16_t op2, size_t vl) {
206 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
207 }
208
209 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmulhsu_vv_i16m2_tu
210 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
211 // CHECK-RV64-NEXT: entry:
212 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmulhsu.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], i64 [[VL]])
213 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
214 //
test_vmulhsu_vv_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,vuint16m2_t op2,size_t vl)215 vint16m2_t test_vmulhsu_vv_i16m2_tu(vint16m2_t maskedoff, vint16m2_t op1, vuint16m2_t op2, size_t vl) {
216 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
217 }
218
219 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmulhsu_vx_i16m2_tu
220 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
221 // CHECK-RV64-NEXT: entry:
222 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmulhsu.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
223 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
224 //
test_vmulhsu_vx_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,uint16_t op2,size_t vl)225 vint16m2_t test_vmulhsu_vx_i16m2_tu(vint16m2_t maskedoff, vint16m2_t op1, uint16_t op2, size_t vl) {
226 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
227 }
228
229 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmulhsu_vv_i16m4_tu
230 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
231 // CHECK-RV64-NEXT: entry:
232 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmulhsu.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], i64 [[VL]])
233 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
234 //
test_vmulhsu_vv_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,vuint16m4_t op2,size_t vl)235 vint16m4_t test_vmulhsu_vv_i16m4_tu(vint16m4_t maskedoff, vint16m4_t op1, vuint16m4_t op2, size_t vl) {
236 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
237 }
238
239 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmulhsu_vx_i16m4_tu
240 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
241 // CHECK-RV64-NEXT: entry:
242 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmulhsu.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
243 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
244 //
test_vmulhsu_vx_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,uint16_t op2,size_t vl)245 vint16m4_t test_vmulhsu_vx_i16m4_tu(vint16m4_t maskedoff, vint16m4_t op1, uint16_t op2, size_t vl) {
246 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
247 }
248
249 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmulhsu_vv_i16m8_tu
250 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
251 // CHECK-RV64-NEXT: entry:
252 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], i64 [[VL]])
253 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
254 //
test_vmulhsu_vv_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,vuint16m8_t op2,size_t vl)255 vint16m8_t test_vmulhsu_vv_i16m8_tu(vint16m8_t maskedoff, vint16m8_t op1, vuint16m8_t op2, size_t vl) {
256 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
257 }
258
259 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmulhsu_vx_i16m8_tu
260 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
261 // CHECK-RV64-NEXT: entry:
262 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
263 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
264 //
test_vmulhsu_vx_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,uint16_t op2,size_t vl)265 vint16m8_t test_vmulhsu_vx_i16m8_tu(vint16m8_t maskedoff, vint16m8_t op1, uint16_t op2, size_t vl) {
266 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
267 }
268
269 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmulhsu_vv_i32mf2_tu
270 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
271 // CHECK-RV64-NEXT: entry:
272 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], i64 [[VL]])
273 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
274 //
test_vmulhsu_vv_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)275 vint32mf2_t test_vmulhsu_vv_i32mf2_tu(vint32mf2_t maskedoff, vint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
276 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
277 }
278
279 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmulhsu_vx_i32mf2_tu
280 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
281 // CHECK-RV64-NEXT: entry:
282 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
283 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
284 //
test_vmulhsu_vx_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,uint32_t op2,size_t vl)285 vint32mf2_t test_vmulhsu_vx_i32mf2_tu(vint32mf2_t maskedoff, vint32mf2_t op1, uint32_t op2, size_t vl) {
286 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
287 }
288
289 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmulhsu_vv_i32m1_tu
290 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
291 // CHECK-RV64-NEXT: entry:
292 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], i64 [[VL]])
293 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
294 //
test_vmulhsu_vv_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,vuint32m1_t op2,size_t vl)295 vint32m1_t test_vmulhsu_vv_i32m1_tu(vint32m1_t maskedoff, vint32m1_t op1, vuint32m1_t op2, size_t vl) {
296 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
297 }
298
299 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmulhsu_vx_i32m1_tu
300 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
301 // CHECK-RV64-NEXT: entry:
302 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
303 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
304 //
test_vmulhsu_vx_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,uint32_t op2,size_t vl)305 vint32m1_t test_vmulhsu_vx_i32m1_tu(vint32m1_t maskedoff, vint32m1_t op1, uint32_t op2, size_t vl) {
306 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
307 }
308
309 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmulhsu_vv_i32m2_tu
310 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
311 // CHECK-RV64-NEXT: entry:
312 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmulhsu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], i64 [[VL]])
313 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
314 //
test_vmulhsu_vv_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,vuint32m2_t op2,size_t vl)315 vint32m2_t test_vmulhsu_vv_i32m2_tu(vint32m2_t maskedoff, vint32m2_t op1, vuint32m2_t op2, size_t vl) {
316 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
317 }
318
319 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmulhsu_vx_i32m2_tu
320 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
321 // CHECK-RV64-NEXT: entry:
322 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmulhsu.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
323 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
324 //
test_vmulhsu_vx_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,uint32_t op2,size_t vl)325 vint32m2_t test_vmulhsu_vx_i32m2_tu(vint32m2_t maskedoff, vint32m2_t op1, uint32_t op2, size_t vl) {
326 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
327 }
328
329 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmulhsu_vv_i32m4_tu
330 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
331 // CHECK-RV64-NEXT: entry:
332 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmulhsu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], i64 [[VL]])
333 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
334 //
test_vmulhsu_vv_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,vuint32m4_t op2,size_t vl)335 vint32m4_t test_vmulhsu_vv_i32m4_tu(vint32m4_t maskedoff, vint32m4_t op1, vuint32m4_t op2, size_t vl) {
336 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
337 }
338
339 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmulhsu_vx_i32m4_tu
340 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
341 // CHECK-RV64-NEXT: entry:
342 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmulhsu.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
343 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
344 //
test_vmulhsu_vx_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,uint32_t op2,size_t vl)345 vint32m4_t test_vmulhsu_vx_i32m4_tu(vint32m4_t maskedoff, vint32m4_t op1, uint32_t op2, size_t vl) {
346 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
347 }
348
349 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmulhsu_vv_i32m8_tu
350 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
351 // CHECK-RV64-NEXT: entry:
352 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], i64 [[VL]])
353 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
354 //
test_vmulhsu_vv_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,vuint32m8_t op2,size_t vl)355 vint32m8_t test_vmulhsu_vv_i32m8_tu(vint32m8_t maskedoff, vint32m8_t op1, vuint32m8_t op2, size_t vl) {
356 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
357 }
358
359 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmulhsu_vx_i32m8_tu
360 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
361 // CHECK-RV64-NEXT: entry:
362 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
363 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
364 //
test_vmulhsu_vx_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,uint32_t op2,size_t vl)365 vint32m8_t test_vmulhsu_vx_i32m8_tu(vint32m8_t maskedoff, vint32m8_t op1, uint32_t op2, size_t vl) {
366 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
367 }
368
369 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1_tu
370 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
371 // CHECK-RV64-NEXT: entry:
372 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], i64 [[VL]])
373 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
374 //
test_vmulhsu_vv_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,vuint64m1_t op2,size_t vl)375 vint64m1_t test_vmulhsu_vv_i64m1_tu(vint64m1_t maskedoff, vint64m1_t op1, vuint64m1_t op2, size_t vl) {
376 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
377 }
378
379 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1_tu
380 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
381 // CHECK-RV64-NEXT: entry:
382 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
383 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
384 //
test_vmulhsu_vx_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,uint64_t op2,size_t vl)385 vint64m1_t test_vmulhsu_vx_i64m1_tu(vint64m1_t maskedoff, vint64m1_t op1, uint64_t op2, size_t vl) {
386 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
387 }
388
389 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmulhsu_vv_i64m2_tu
390 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
391 // CHECK-RV64-NEXT: entry:
392 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], i64 [[VL]])
393 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
394 //
test_vmulhsu_vv_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,vuint64m2_t op2,size_t vl)395 vint64m2_t test_vmulhsu_vv_i64m2_tu(vint64m2_t maskedoff, vint64m2_t op1, vuint64m2_t op2, size_t vl) {
396 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
397 }
398
399 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmulhsu_vx_i64m2_tu
400 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
401 // CHECK-RV64-NEXT: entry:
402 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
403 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
404 //
test_vmulhsu_vx_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,uint64_t op2,size_t vl)405 vint64m2_t test_vmulhsu_vx_i64m2_tu(vint64m2_t maskedoff, vint64m2_t op1, uint64_t op2, size_t vl) {
406 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
407 }
408
409 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmulhsu_vv_i64m4_tu
410 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
411 // CHECK-RV64-NEXT: entry:
412 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], i64 [[VL]])
413 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
414 //
test_vmulhsu_vv_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,vuint64m4_t op2,size_t vl)415 vint64m4_t test_vmulhsu_vv_i64m4_tu(vint64m4_t maskedoff, vint64m4_t op1, vuint64m4_t op2, size_t vl) {
416 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
417 }
418
419 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmulhsu_vx_i64m4_tu
420 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
421 // CHECK-RV64-NEXT: entry:
422 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
423 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
424 //
test_vmulhsu_vx_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,uint64_t op2,size_t vl)425 vint64m4_t test_vmulhsu_vx_i64m4_tu(vint64m4_t maskedoff, vint64m4_t op1, uint64_t op2, size_t vl) {
426 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
427 }
428
429 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmulhsu_vv_i64m8_tu
430 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
431 // CHECK-RV64-NEXT: entry:
432 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], i64 [[VL]])
433 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
434 //
test_vmulhsu_vv_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,vuint64m8_t op2,size_t vl)435 vint64m8_t test_vmulhsu_vv_i64m8_tu(vint64m8_t maskedoff, vint64m8_t op1, vuint64m8_t op2, size_t vl) {
436 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
437 }
438
439 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmulhsu_vx_i64m8_tu
440 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
441 // CHECK-RV64-NEXT: entry:
442 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
443 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
444 //
test_vmulhsu_vx_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,uint64_t op2,size_t vl)445 vint64m8_t test_vmulhsu_vx_i64m8_tu(vint64m8_t maskedoff, vint64m8_t op1, uint64_t op2, size_t vl) {
446 return __riscv_vmulhsu_tu(maskedoff, op1, op2, vl);
447 }
448
449 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8_tum
450 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
451 // CHECK-RV64-NEXT: entry:
452 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
453 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
454 //
test_vmulhsu_vv_i8mf8_tum(vbool64_t mask,vint8mf8_t maskedoff,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)455 vint8mf8_t test_vmulhsu_vv_i8mf8_tum(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
456 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
457 }
458
459 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8_tum
460 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
461 // CHECK-RV64-NEXT: entry:
462 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
463 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
464 //
test_vmulhsu_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t maskedoff,vint8mf8_t op1,uint8_t op2,size_t vl)465 vint8mf8_t test_vmulhsu_vx_i8mf8_tum(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, uint8_t op2, size_t vl) {
466 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
467 }
468
469 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4_tum
470 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
471 // CHECK-RV64-NEXT: entry:
472 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
473 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
474 //
test_vmulhsu_vv_i8mf4_tum(vbool32_t mask,vint8mf4_t maskedoff,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)475 vint8mf4_t test_vmulhsu_vv_i8mf4_tum(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
476 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
477 }
478
479 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4_tum
480 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
481 // CHECK-RV64-NEXT: entry:
482 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
483 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
484 //
test_vmulhsu_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t maskedoff,vint8mf4_t op1,uint8_t op2,size_t vl)485 vint8mf4_t test_vmulhsu_vx_i8mf4_tum(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, uint8_t op2, size_t vl) {
486 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
487 }
488
489 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2_tum
490 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
491 // CHECK-RV64-NEXT: entry:
492 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
493 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
494 //
test_vmulhsu_vv_i8mf2_tum(vbool16_t mask,vint8mf2_t maskedoff,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)495 vint8mf2_t test_vmulhsu_vv_i8mf2_tum(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
496 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
497 }
498
499 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2_tum
500 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
501 // CHECK-RV64-NEXT: entry:
502 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
503 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
504 //
test_vmulhsu_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t maskedoff,vint8mf2_t op1,uint8_t op2,size_t vl)505 vint8mf2_t test_vmulhsu_vx_i8mf2_tum(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, uint8_t op2, size_t vl) {
506 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
507 }
508
509 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1_tum
510 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
511 // CHECK-RV64-NEXT: entry:
512 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
513 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
514 //
test_vmulhsu_vv_i8m1_tum(vbool8_t mask,vint8m1_t maskedoff,vint8m1_t op1,vuint8m1_t op2,size_t vl)515 vint8m1_t test_vmulhsu_vv_i8m1_tum(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, vuint8m1_t op2, size_t vl) {
516 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
517 }
518
519 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1_tum
520 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
521 // CHECK-RV64-NEXT: entry:
522 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
523 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
524 //
test_vmulhsu_vx_i8m1_tum(vbool8_t mask,vint8m1_t maskedoff,vint8m1_t op1,uint8_t op2,size_t vl)525 vint8m1_t test_vmulhsu_vx_i8m1_tum(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, uint8_t op2, size_t vl) {
526 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
527 }
528
529 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2_tum
530 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
531 // CHECK-RV64-NEXT: entry:
532 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
533 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
534 //
test_vmulhsu_vv_i8m2_tum(vbool4_t mask,vint8m2_t maskedoff,vint8m2_t op1,vuint8m2_t op2,size_t vl)535 vint8m2_t test_vmulhsu_vv_i8m2_tum(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, vuint8m2_t op2, size_t vl) {
536 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
537 }
538
539 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2_tum
540 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
541 // CHECK-RV64-NEXT: entry:
542 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
543 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
544 //
test_vmulhsu_vx_i8m2_tum(vbool4_t mask,vint8m2_t maskedoff,vint8m2_t op1,uint8_t op2,size_t vl)545 vint8m2_t test_vmulhsu_vx_i8m2_tum(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, uint8_t op2, size_t vl) {
546 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
547 }
548
549 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4_tum
550 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
551 // CHECK-RV64-NEXT: entry:
552 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)
553 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
554 //
test_vmulhsu_vv_i8m4_tum(vbool2_t mask,vint8m4_t maskedoff,vint8m4_t op1,vuint8m4_t op2,size_t vl)555 vint8m4_t test_vmulhsu_vv_i8m4_tum(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, vuint8m4_t op2, size_t vl) {
556 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
557 }
558
559 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmulhsu_vx_i8m4_tum
560 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
561 // CHECK-RV64-NEXT: entry:
562 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)
563 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
564 //
test_vmulhsu_vx_i8m4_tum(vbool2_t mask,vint8m4_t maskedoff,vint8m4_t op1,uint8_t op2,size_t vl)565 vint8m4_t test_vmulhsu_vx_i8m4_tum(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, uint8_t op2, size_t vl) {
566 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
567 }
568
569 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmulhsu_vv_i8m8_tum
570 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
571 // CHECK-RV64-NEXT: entry:
572 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 2)
573 // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
574 //
test_vmulhsu_vv_i8m8_tum(vbool1_t mask,vint8m8_t maskedoff,vint8m8_t op1,vuint8m8_t op2,size_t vl)575 vint8m8_t test_vmulhsu_vv_i8m8_tum(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, vuint8m8_t op2, size_t vl) {
576 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
577 }
578
579 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmulhsu_vx_i8m8_tum
580 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
581 // CHECK-RV64-NEXT: entry:
582 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], i8 [[OP2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 2)
583 // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
584 //
test_vmulhsu_vx_i8m8_tum(vbool1_t mask,vint8m8_t maskedoff,vint8m8_t op1,uint8_t op2,size_t vl)585 vint8m8_t test_vmulhsu_vx_i8m8_tum(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, uint8_t op2, size_t vl) {
586 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
587 }
588
589 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmulhsu_vv_i16mf4_tum
590 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
591 // CHECK-RV64-NEXT: entry:
592 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
593 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
594 //
test_vmulhsu_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t maskedoff,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)595 vint16mf4_t test_vmulhsu_vv_i16mf4_tum(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
596 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
597 }
598
599 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmulhsu_vx_i16mf4_tum
600 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
601 // CHECK-RV64-NEXT: entry:
602 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
603 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
604 //
test_vmulhsu_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t maskedoff,vint16mf4_t op1,uint16_t op2,size_t vl)605 vint16mf4_t test_vmulhsu_vx_i16mf4_tum(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, uint16_t op2, size_t vl) {
606 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
607 }
608
609 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmulhsu_vv_i16mf2_tum
610 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
611 // CHECK-RV64-NEXT: entry:
612 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
613 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
614 //
test_vmulhsu_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t maskedoff,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)615 vint16mf2_t test_vmulhsu_vv_i16mf2_tum(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
616 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
617 }
618
619 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmulhsu_vx_i16mf2_tum
620 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
621 // CHECK-RV64-NEXT: entry:
622 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
623 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
624 //
test_vmulhsu_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t maskedoff,vint16mf2_t op1,uint16_t op2,size_t vl)625 vint16mf2_t test_vmulhsu_vx_i16mf2_tum(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, uint16_t op2, size_t vl) {
626 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
627 }
628
629 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmulhsu_vv_i16m1_tum
630 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
631 // CHECK-RV64-NEXT: entry:
632 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmulhsu.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
633 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
634 //
test_vmulhsu_vv_i16m1_tum(vbool16_t mask,vint16m1_t maskedoff,vint16m1_t op1,vuint16m1_t op2,size_t vl)635 vint16m1_t test_vmulhsu_vv_i16m1_tum(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, vuint16m1_t op2, size_t vl) {
636 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
637 }
638
639 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmulhsu_vx_i16m1_tum
640 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
641 // CHECK-RV64-NEXT: entry:
642 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmulhsu.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
643 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
644 //
test_vmulhsu_vx_i16m1_tum(vbool16_t mask,vint16m1_t maskedoff,vint16m1_t op1,uint16_t op2,size_t vl)645 vint16m1_t test_vmulhsu_vx_i16m1_tum(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, uint16_t op2, size_t vl) {
646 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
647 }
648
649 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmulhsu_vv_i16m2_tum
650 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
651 // CHECK-RV64-NEXT: entry:
652 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmulhsu.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
653 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
654 //
test_vmulhsu_vv_i16m2_tum(vbool8_t mask,vint16m2_t maskedoff,vint16m2_t op1,vuint16m2_t op2,size_t vl)655 vint16m2_t test_vmulhsu_vv_i16m2_tum(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, vuint16m2_t op2, size_t vl) {
656 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
657 }
658
659 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmulhsu_vx_i16m2_tum
660 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
661 // CHECK-RV64-NEXT: entry:
662 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmulhsu.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
663 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
664 //
test_vmulhsu_vx_i16m2_tum(vbool8_t mask,vint16m2_t maskedoff,vint16m2_t op1,uint16_t op2,size_t vl)665 vint16m2_t test_vmulhsu_vx_i16m2_tum(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, uint16_t op2, size_t vl) {
666 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
667 }
668
669 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmulhsu_vv_i16m4_tum
670 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
671 // CHECK-RV64-NEXT: entry:
672 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmulhsu.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
673 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
674 //
test_vmulhsu_vv_i16m4_tum(vbool4_t mask,vint16m4_t maskedoff,vint16m4_t op1,vuint16m4_t op2,size_t vl)675 vint16m4_t test_vmulhsu_vv_i16m4_tum(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, vuint16m4_t op2, size_t vl) {
676 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
677 }
678
679 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmulhsu_vx_i16m4_tum
680 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
681 // CHECK-RV64-NEXT: entry:
682 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmulhsu.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
683 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
684 //
test_vmulhsu_vx_i16m4_tum(vbool4_t mask,vint16m4_t maskedoff,vint16m4_t op1,uint16_t op2,size_t vl)685 vint16m4_t test_vmulhsu_vx_i16m4_tum(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, uint16_t op2, size_t vl) {
686 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
687 }
688
689 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmulhsu_vv_i16m8_tum
690 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
691 // CHECK-RV64-NEXT: entry:
692 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)
693 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
694 //
test_vmulhsu_vv_i16m8_tum(vbool2_t mask,vint16m8_t maskedoff,vint16m8_t op1,vuint16m8_t op2,size_t vl)695 vint16m8_t test_vmulhsu_vv_i16m8_tum(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, vuint16m8_t op2, size_t vl) {
696 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
697 }
698
699 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmulhsu_vx_i16m8_tum
700 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
701 // CHECK-RV64-NEXT: entry:
702 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], i16 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)
703 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
704 //
test_vmulhsu_vx_i16m8_tum(vbool2_t mask,vint16m8_t maskedoff,vint16m8_t op1,uint16_t op2,size_t vl)705 vint16m8_t test_vmulhsu_vx_i16m8_tum(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, uint16_t op2, size_t vl) {
706 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
707 }
708
709 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmulhsu_vv_i32mf2_tum
710 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
711 // CHECK-RV64-NEXT: entry:
712 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
713 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
714 //
test_vmulhsu_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t maskedoff,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)715 vint32mf2_t test_vmulhsu_vv_i32mf2_tum(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
716 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
717 }
718
719 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmulhsu_vx_i32mf2_tum
720 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
721 // CHECK-RV64-NEXT: entry:
722 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
723 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
724 //
test_vmulhsu_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t maskedoff,vint32mf2_t op1,uint32_t op2,size_t vl)725 vint32mf2_t test_vmulhsu_vx_i32mf2_tum(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, uint32_t op2, size_t vl) {
726 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
727 }
728
729 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmulhsu_vv_i32m1_tum
730 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
731 // CHECK-RV64-NEXT: entry:
732 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
733 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
734 //
test_vmulhsu_vv_i32m1_tum(vbool32_t mask,vint32m1_t maskedoff,vint32m1_t op1,vuint32m1_t op2,size_t vl)735 vint32m1_t test_vmulhsu_vv_i32m1_tum(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, vuint32m1_t op2, size_t vl) {
736 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
737 }
738
739 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmulhsu_vx_i32m1_tum
740 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
741 // CHECK-RV64-NEXT: entry:
742 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
743 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
744 //
test_vmulhsu_vx_i32m1_tum(vbool32_t mask,vint32m1_t maskedoff,vint32m1_t op1,uint32_t op2,size_t vl)745 vint32m1_t test_vmulhsu_vx_i32m1_tum(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, uint32_t op2, size_t vl) {
746 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
747 }
748
749 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmulhsu_vv_i32m2_tum
750 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
751 // CHECK-RV64-NEXT: entry:
752 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmulhsu.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
753 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
754 //
test_vmulhsu_vv_i32m2_tum(vbool16_t mask,vint32m2_t maskedoff,vint32m2_t op1,vuint32m2_t op2,size_t vl)755 vint32m2_t test_vmulhsu_vv_i32m2_tum(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, vuint32m2_t op2, size_t vl) {
756 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
757 }
758
759 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmulhsu_vx_i32m2_tum
760 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
761 // CHECK-RV64-NEXT: entry:
762 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmulhsu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
763 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
764 //
test_vmulhsu_vx_i32m2_tum(vbool16_t mask,vint32m2_t maskedoff,vint32m2_t op1,uint32_t op2,size_t vl)765 vint32m2_t test_vmulhsu_vx_i32m2_tum(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, uint32_t op2, size_t vl) {
766 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
767 }
768
769 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmulhsu_vv_i32m4_tum
770 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
771 // CHECK-RV64-NEXT: entry:
772 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmulhsu.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
773 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
774 //
test_vmulhsu_vv_i32m4_tum(vbool8_t mask,vint32m4_t maskedoff,vint32m4_t op1,vuint32m4_t op2,size_t vl)775 vint32m4_t test_vmulhsu_vv_i32m4_tum(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, vuint32m4_t op2, size_t vl) {
776 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
777 }
778
779 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmulhsu_vx_i32m4_tum
780 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
781 // CHECK-RV64-NEXT: entry:
782 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmulhsu.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
783 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
784 //
test_vmulhsu_vx_i32m4_tum(vbool8_t mask,vint32m4_t maskedoff,vint32m4_t op1,uint32_t op2,size_t vl)785 vint32m4_t test_vmulhsu_vx_i32m4_tum(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, uint32_t op2, size_t vl) {
786 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
787 }
788
789 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmulhsu_vv_i32m8_tum
790 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
791 // CHECK-RV64-NEXT: entry:
792 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
793 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
794 //
test_vmulhsu_vv_i32m8_tum(vbool4_t mask,vint32m8_t maskedoff,vint32m8_t op1,vuint32m8_t op2,size_t vl)795 vint32m8_t test_vmulhsu_vv_i32m8_tum(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, vuint32m8_t op2, size_t vl) {
796 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
797 }
798
799 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmulhsu_vx_i32m8_tum
800 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
801 // CHECK-RV64-NEXT: entry:
802 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], i32 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
803 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
804 //
test_vmulhsu_vx_i32m8_tum(vbool4_t mask,vint32m8_t maskedoff,vint32m8_t op1,uint32_t op2,size_t vl)805 vint32m8_t test_vmulhsu_vx_i32m8_tum(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, uint32_t op2, size_t vl) {
806 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
807 }
808
809 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1_tum
810 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
811 // CHECK-RV64-NEXT: entry:
812 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
813 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
814 //
test_vmulhsu_vv_i64m1_tum(vbool64_t mask,vint64m1_t maskedoff,vint64m1_t op1,vuint64m1_t op2,size_t vl)815 vint64m1_t test_vmulhsu_vv_i64m1_tum(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, vuint64m1_t op2, size_t vl) {
816 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
817 }
818
819 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1_tum
820 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
821 // CHECK-RV64-NEXT: entry:
822 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], i64 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
823 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
824 //
test_vmulhsu_vx_i64m1_tum(vbool64_t mask,vint64m1_t maskedoff,vint64m1_t op1,uint64_t op2,size_t vl)825 vint64m1_t test_vmulhsu_vx_i64m1_tum(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, uint64_t op2, size_t vl) {
826 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
827 }
828
829 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmulhsu_vv_i64m2_tum
830 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
831 // CHECK-RV64-NEXT: entry:
832 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
833 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
834 //
test_vmulhsu_vv_i64m2_tum(vbool32_t mask,vint64m2_t maskedoff,vint64m2_t op1,vuint64m2_t op2,size_t vl)835 vint64m2_t test_vmulhsu_vv_i64m2_tum(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, vuint64m2_t op2, size_t vl) {
836 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
837 }
838
839 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmulhsu_vx_i64m2_tum
840 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
841 // CHECK-RV64-NEXT: entry:
842 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], i64 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
843 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
844 //
test_vmulhsu_vx_i64m2_tum(vbool32_t mask,vint64m2_t maskedoff,vint64m2_t op1,uint64_t op2,size_t vl)845 vint64m2_t test_vmulhsu_vx_i64m2_tum(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, uint64_t op2, size_t vl) {
846 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
847 }
848
849 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmulhsu_vv_i64m4_tum
850 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
851 // CHECK-RV64-NEXT: entry:
852 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
853 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
854 //
test_vmulhsu_vv_i64m4_tum(vbool16_t mask,vint64m4_t maskedoff,vint64m4_t op1,vuint64m4_t op2,size_t vl)855 vint64m4_t test_vmulhsu_vv_i64m4_tum(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, vuint64m4_t op2, size_t vl) {
856 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
857 }
858
859 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmulhsu_vx_i64m4_tum
860 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
861 // CHECK-RV64-NEXT: entry:
862 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], i64 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
863 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
864 //
test_vmulhsu_vx_i64m4_tum(vbool16_t mask,vint64m4_t maskedoff,vint64m4_t op1,uint64_t op2,size_t vl)865 vint64m4_t test_vmulhsu_vx_i64m4_tum(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, uint64_t op2, size_t vl) {
866 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
867 }
868
869 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmulhsu_vv_i64m8_tum
870 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
871 // CHECK-RV64-NEXT: entry:
872 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
873 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
874 //
test_vmulhsu_vv_i64m8_tum(vbool8_t mask,vint64m8_t maskedoff,vint64m8_t op1,vuint64m8_t op2,size_t vl)875 vint64m8_t test_vmulhsu_vv_i64m8_tum(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, vuint64m8_t op2, size_t vl) {
876 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
877 }
878
879 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmulhsu_vx_i64m8_tum
880 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
881 // CHECK-RV64-NEXT: entry:
882 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], i64 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
883 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
884 //
test_vmulhsu_vx_i64m8_tum(vbool8_t mask,vint64m8_t maskedoff,vint64m8_t op1,uint64_t op2,size_t vl)885 vint64m8_t test_vmulhsu_vx_i64m8_tum(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, uint64_t op2, size_t vl) {
886 return __riscv_vmulhsu_tum(mask, maskedoff, op1, op2, vl);
887 }
888
889 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8_tumu
890 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
891 // CHECK-RV64-NEXT: entry:
892 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
893 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
894 //
test_vmulhsu_vv_i8mf8_tumu(vbool64_t mask,vint8mf8_t maskedoff,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)895 vint8mf8_t test_vmulhsu_vv_i8mf8_tumu(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
896 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
897 }
898
899 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8_tumu
900 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
901 // CHECK-RV64-NEXT: entry:
902 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
903 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
904 //
test_vmulhsu_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t maskedoff,vint8mf8_t op1,uint8_t op2,size_t vl)905 vint8mf8_t test_vmulhsu_vx_i8mf8_tumu(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, uint8_t op2, size_t vl) {
906 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
907 }
908
909 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4_tumu
910 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
911 // CHECK-RV64-NEXT: entry:
912 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
913 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
914 //
test_vmulhsu_vv_i8mf4_tumu(vbool32_t mask,vint8mf4_t maskedoff,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)915 vint8mf4_t test_vmulhsu_vv_i8mf4_tumu(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
916 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
917 }
918
919 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4_tumu
920 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
921 // CHECK-RV64-NEXT: entry:
922 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
923 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
924 //
test_vmulhsu_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t maskedoff,vint8mf4_t op1,uint8_t op2,size_t vl)925 vint8mf4_t test_vmulhsu_vx_i8mf4_tumu(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, uint8_t op2, size_t vl) {
926 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
927 }
928
929 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2_tumu
930 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
931 // CHECK-RV64-NEXT: entry:
932 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
933 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
934 //
test_vmulhsu_vv_i8mf2_tumu(vbool16_t mask,vint8mf2_t maskedoff,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)935 vint8mf2_t test_vmulhsu_vv_i8mf2_tumu(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
936 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
937 }
938
939 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2_tumu
940 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
941 // CHECK-RV64-NEXT: entry:
942 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
943 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
944 //
test_vmulhsu_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t maskedoff,vint8mf2_t op1,uint8_t op2,size_t vl)945 vint8mf2_t test_vmulhsu_vx_i8mf2_tumu(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, uint8_t op2, size_t vl) {
946 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
947 }
948
949 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1_tumu
950 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
951 // CHECK-RV64-NEXT: entry:
952 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
953 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
954 //
test_vmulhsu_vv_i8m1_tumu(vbool8_t mask,vint8m1_t maskedoff,vint8m1_t op1,vuint8m1_t op2,size_t vl)955 vint8m1_t test_vmulhsu_vv_i8m1_tumu(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, vuint8m1_t op2, size_t vl) {
956 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
957 }
958
959 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1_tumu
960 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
961 // CHECK-RV64-NEXT: entry:
962 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
963 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
964 //
test_vmulhsu_vx_i8m1_tumu(vbool8_t mask,vint8m1_t maskedoff,vint8m1_t op1,uint8_t op2,size_t vl)965 vint8m1_t test_vmulhsu_vx_i8m1_tumu(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, uint8_t op2, size_t vl) {
966 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
967 }
968
969 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2_tumu
970 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
971 // CHECK-RV64-NEXT: entry:
972 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
973 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
974 //
test_vmulhsu_vv_i8m2_tumu(vbool4_t mask,vint8m2_t maskedoff,vint8m2_t op1,vuint8m2_t op2,size_t vl)975 vint8m2_t test_vmulhsu_vv_i8m2_tumu(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, vuint8m2_t op2, size_t vl) {
976 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
977 }
978
979 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2_tumu
980 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
981 // CHECK-RV64-NEXT: entry:
982 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
983 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
984 //
test_vmulhsu_vx_i8m2_tumu(vbool4_t mask,vint8m2_t maskedoff,vint8m2_t op1,uint8_t op2,size_t vl)985 vint8m2_t test_vmulhsu_vx_i8m2_tumu(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, uint8_t op2, size_t vl) {
986 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
987 }
988
989 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4_tumu
990 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
991 // CHECK-RV64-NEXT: entry:
992 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)
993 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
994 //
test_vmulhsu_vv_i8m4_tumu(vbool2_t mask,vint8m4_t maskedoff,vint8m4_t op1,vuint8m4_t op2,size_t vl)995 vint8m4_t test_vmulhsu_vv_i8m4_tumu(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, vuint8m4_t op2, size_t vl) {
996 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
997 }
998
999 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmulhsu_vx_i8m4_tumu
1000 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1001 // CHECK-RV64-NEXT: entry:
1002 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)
1003 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
1004 //
test_vmulhsu_vx_i8m4_tumu(vbool2_t mask,vint8m4_t maskedoff,vint8m4_t op1,uint8_t op2,size_t vl)1005 vint8m4_t test_vmulhsu_vx_i8m4_tumu(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, uint8_t op2, size_t vl) {
1006 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1007 }
1008
1009 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmulhsu_vv_i8m8_tumu
1010 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1011 // CHECK-RV64-NEXT: entry:
1012 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 0)
1013 // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
1014 //
test_vmulhsu_vv_i8m8_tumu(vbool1_t mask,vint8m8_t maskedoff,vint8m8_t op1,vuint8m8_t op2,size_t vl)1015 vint8m8_t test_vmulhsu_vv_i8m8_tumu(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, vuint8m8_t op2, size_t vl) {
1016 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1017 }
1018
1019 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmulhsu_vx_i8m8_tumu
1020 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1021 // CHECK-RV64-NEXT: entry:
1022 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], i8 [[OP2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 0)
1023 // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
1024 //
test_vmulhsu_vx_i8m8_tumu(vbool1_t mask,vint8m8_t maskedoff,vint8m8_t op1,uint8_t op2,size_t vl)1025 vint8m8_t test_vmulhsu_vx_i8m8_tumu(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, uint8_t op2, size_t vl) {
1026 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1027 }
1028
1029 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmulhsu_vv_i16mf4_tumu
1030 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1031 // CHECK-RV64-NEXT: entry:
1032 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1033 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
1034 //
test_vmulhsu_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t maskedoff,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)1035 vint16mf4_t test_vmulhsu_vv_i16mf4_tumu(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
1036 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1037 }
1038
1039 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmulhsu_vx_i16mf4_tumu
1040 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1041 // CHECK-RV64-NEXT: entry:
1042 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1043 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
1044 //
test_vmulhsu_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t maskedoff,vint16mf4_t op1,uint16_t op2,size_t vl)1045 vint16mf4_t test_vmulhsu_vx_i16mf4_tumu(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, uint16_t op2, size_t vl) {
1046 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1047 }
1048
1049 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmulhsu_vv_i16mf2_tumu
1050 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1051 // CHECK-RV64-NEXT: entry:
1052 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1053 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
1054 //
test_vmulhsu_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t maskedoff,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)1055 vint16mf2_t test_vmulhsu_vv_i16mf2_tumu(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
1056 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1057 }
1058
1059 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmulhsu_vx_i16mf2_tumu
1060 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1061 // CHECK-RV64-NEXT: entry:
1062 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1063 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
1064 //
test_vmulhsu_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t maskedoff,vint16mf2_t op1,uint16_t op2,size_t vl)1065 vint16mf2_t test_vmulhsu_vx_i16mf2_tumu(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, uint16_t op2, size_t vl) {
1066 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1067 }
1068
1069 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmulhsu_vv_i16m1_tumu
1070 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1071 // CHECK-RV64-NEXT: entry:
1072 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmulhsu.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1073 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
1074 //
test_vmulhsu_vv_i16m1_tumu(vbool16_t mask,vint16m1_t maskedoff,vint16m1_t op1,vuint16m1_t op2,size_t vl)1075 vint16m1_t test_vmulhsu_vv_i16m1_tumu(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, vuint16m1_t op2, size_t vl) {
1076 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1077 }
1078
1079 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmulhsu_vx_i16m1_tumu
1080 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1081 // CHECK-RV64-NEXT: entry:
1082 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmulhsu.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1083 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
1084 //
test_vmulhsu_vx_i16m1_tumu(vbool16_t mask,vint16m1_t maskedoff,vint16m1_t op1,uint16_t op2,size_t vl)1085 vint16m1_t test_vmulhsu_vx_i16m1_tumu(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, uint16_t op2, size_t vl) {
1086 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1087 }
1088
1089 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmulhsu_vv_i16m2_tumu
1090 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1091 // CHECK-RV64-NEXT: entry:
1092 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmulhsu.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1093 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
1094 //
test_vmulhsu_vv_i16m2_tumu(vbool8_t mask,vint16m2_t maskedoff,vint16m2_t op1,vuint16m2_t op2,size_t vl)1095 vint16m2_t test_vmulhsu_vv_i16m2_tumu(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, vuint16m2_t op2, size_t vl) {
1096 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1097 }
1098
1099 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmulhsu_vx_i16m2_tumu
1100 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1101 // CHECK-RV64-NEXT: entry:
1102 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmulhsu.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1103 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
1104 //
test_vmulhsu_vx_i16m2_tumu(vbool8_t mask,vint16m2_t maskedoff,vint16m2_t op1,uint16_t op2,size_t vl)1105 vint16m2_t test_vmulhsu_vx_i16m2_tumu(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, uint16_t op2, size_t vl) {
1106 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1107 }
1108
1109 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmulhsu_vv_i16m4_tumu
1110 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1111 // CHECK-RV64-NEXT: entry:
1112 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmulhsu.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
1113 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
1114 //
test_vmulhsu_vv_i16m4_tumu(vbool4_t mask,vint16m4_t maskedoff,vint16m4_t op1,vuint16m4_t op2,size_t vl)1115 vint16m4_t test_vmulhsu_vv_i16m4_tumu(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, vuint16m4_t op2, size_t vl) {
1116 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1117 }
1118
1119 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmulhsu_vx_i16m4_tumu
1120 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1121 // CHECK-RV64-NEXT: entry:
1122 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmulhsu.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
1123 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
1124 //
test_vmulhsu_vx_i16m4_tumu(vbool4_t mask,vint16m4_t maskedoff,vint16m4_t op1,uint16_t op2,size_t vl)1125 vint16m4_t test_vmulhsu_vx_i16m4_tumu(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, uint16_t op2, size_t vl) {
1126 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1127 }
1128
1129 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmulhsu_vv_i16m8_tumu
1130 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1131 // CHECK-RV64-NEXT: entry:
1132 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)
1133 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
1134 //
test_vmulhsu_vv_i16m8_tumu(vbool2_t mask,vint16m8_t maskedoff,vint16m8_t op1,vuint16m8_t op2,size_t vl)1135 vint16m8_t test_vmulhsu_vv_i16m8_tumu(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, vuint16m8_t op2, size_t vl) {
1136 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1137 }
1138
1139 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmulhsu_vx_i16m8_tumu
1140 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1141 // CHECK-RV64-NEXT: entry:
1142 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], i16 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)
1143 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
1144 //
test_vmulhsu_vx_i16m8_tumu(vbool2_t mask,vint16m8_t maskedoff,vint16m8_t op1,uint16_t op2,size_t vl)1145 vint16m8_t test_vmulhsu_vx_i16m8_tumu(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, uint16_t op2, size_t vl) {
1146 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1147 }
1148
1149 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmulhsu_vv_i32mf2_tumu
1150 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1151 // CHECK-RV64-NEXT: entry:
1152 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1153 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
1154 //
test_vmulhsu_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t maskedoff,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)1155 vint32mf2_t test_vmulhsu_vv_i32mf2_tumu(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
1156 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1157 }
1158
1159 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmulhsu_vx_i32mf2_tumu
1160 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1161 // CHECK-RV64-NEXT: entry:
1162 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1163 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
1164 //
test_vmulhsu_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t maskedoff,vint32mf2_t op1,uint32_t op2,size_t vl)1165 vint32mf2_t test_vmulhsu_vx_i32mf2_tumu(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, uint32_t op2, size_t vl) {
1166 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1167 }
1168
1169 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmulhsu_vv_i32m1_tumu
1170 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1171 // CHECK-RV64-NEXT: entry:
1172 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1173 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
1174 //
test_vmulhsu_vv_i32m1_tumu(vbool32_t mask,vint32m1_t maskedoff,vint32m1_t op1,vuint32m1_t op2,size_t vl)1175 vint32m1_t test_vmulhsu_vv_i32m1_tumu(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, vuint32m1_t op2, size_t vl) {
1176 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1177 }
1178
1179 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmulhsu_vx_i32m1_tumu
1180 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1181 // CHECK-RV64-NEXT: entry:
1182 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1183 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
1184 //
test_vmulhsu_vx_i32m1_tumu(vbool32_t mask,vint32m1_t maskedoff,vint32m1_t op1,uint32_t op2,size_t vl)1185 vint32m1_t test_vmulhsu_vx_i32m1_tumu(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, uint32_t op2, size_t vl) {
1186 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1187 }
1188
1189 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmulhsu_vv_i32m2_tumu
1190 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1191 // CHECK-RV64-NEXT: entry:
1192 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmulhsu.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1193 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
1194 //
test_vmulhsu_vv_i32m2_tumu(vbool16_t mask,vint32m2_t maskedoff,vint32m2_t op1,vuint32m2_t op2,size_t vl)1195 vint32m2_t test_vmulhsu_vv_i32m2_tumu(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, vuint32m2_t op2, size_t vl) {
1196 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1197 }
1198
1199 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmulhsu_vx_i32m2_tumu
1200 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1201 // CHECK-RV64-NEXT: entry:
1202 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmulhsu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1203 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
1204 //
test_vmulhsu_vx_i32m2_tumu(vbool16_t mask,vint32m2_t maskedoff,vint32m2_t op1,uint32_t op2,size_t vl)1205 vint32m2_t test_vmulhsu_vx_i32m2_tumu(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, uint32_t op2, size_t vl) {
1206 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1207 }
1208
1209 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmulhsu_vv_i32m4_tumu
1210 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1211 // CHECK-RV64-NEXT: entry:
1212 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmulhsu.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1213 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
1214 //
test_vmulhsu_vv_i32m4_tumu(vbool8_t mask,vint32m4_t maskedoff,vint32m4_t op1,vuint32m4_t op2,size_t vl)1215 vint32m4_t test_vmulhsu_vv_i32m4_tumu(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, vuint32m4_t op2, size_t vl) {
1216 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1217 }
1218
1219 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmulhsu_vx_i32m4_tumu
1220 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1221 // CHECK-RV64-NEXT: entry:
1222 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmulhsu.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1223 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
1224 //
test_vmulhsu_vx_i32m4_tumu(vbool8_t mask,vint32m4_t maskedoff,vint32m4_t op1,uint32_t op2,size_t vl)1225 vint32m4_t test_vmulhsu_vx_i32m4_tumu(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, uint32_t op2, size_t vl) {
1226 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1227 }
1228
1229 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmulhsu_vv_i32m8_tumu
1230 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1231 // CHECK-RV64-NEXT: entry:
1232 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
1233 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
1234 //
test_vmulhsu_vv_i32m8_tumu(vbool4_t mask,vint32m8_t maskedoff,vint32m8_t op1,vuint32m8_t op2,size_t vl)1235 vint32m8_t test_vmulhsu_vv_i32m8_tumu(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, vuint32m8_t op2, size_t vl) {
1236 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1237 }
1238
1239 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmulhsu_vx_i32m8_tumu
1240 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1241 // CHECK-RV64-NEXT: entry:
1242 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], i32 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
1243 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
1244 //
test_vmulhsu_vx_i32m8_tumu(vbool4_t mask,vint32m8_t maskedoff,vint32m8_t op1,uint32_t op2,size_t vl)1245 vint32m8_t test_vmulhsu_vx_i32m8_tumu(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, uint32_t op2, size_t vl) {
1246 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1247 }
1248
1249 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1_tumu
1250 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1251 // CHECK-RV64-NEXT: entry:
1252 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1253 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
1254 //
test_vmulhsu_vv_i64m1_tumu(vbool64_t mask,vint64m1_t maskedoff,vint64m1_t op1,vuint64m1_t op2,size_t vl)1255 vint64m1_t test_vmulhsu_vv_i64m1_tumu(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, vuint64m1_t op2, size_t vl) {
1256 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1257 }
1258
1259 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1_tumu
1260 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1261 // CHECK-RV64-NEXT: entry:
1262 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], i64 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
1263 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
1264 //
test_vmulhsu_vx_i64m1_tumu(vbool64_t mask,vint64m1_t maskedoff,vint64m1_t op1,uint64_t op2,size_t vl)1265 vint64m1_t test_vmulhsu_vx_i64m1_tumu(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, uint64_t op2, size_t vl) {
1266 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1267 }
1268
1269 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmulhsu_vv_i64m2_tumu
1270 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1271 // CHECK-RV64-NEXT: entry:
1272 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1273 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
1274 //
test_vmulhsu_vv_i64m2_tumu(vbool32_t mask,vint64m2_t maskedoff,vint64m2_t op1,vuint64m2_t op2,size_t vl)1275 vint64m2_t test_vmulhsu_vv_i64m2_tumu(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, vuint64m2_t op2, size_t vl) {
1276 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1277 }
1278
1279 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmulhsu_vx_i64m2_tumu
1280 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1281 // CHECK-RV64-NEXT: entry:
1282 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], i64 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
1283 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
1284 //
test_vmulhsu_vx_i64m2_tumu(vbool32_t mask,vint64m2_t maskedoff,vint64m2_t op1,uint64_t op2,size_t vl)1285 vint64m2_t test_vmulhsu_vx_i64m2_tumu(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, uint64_t op2, size_t vl) {
1286 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1287 }
1288
1289 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmulhsu_vv_i64m4_tumu
1290 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1291 // CHECK-RV64-NEXT: entry:
1292 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1293 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
1294 //
test_vmulhsu_vv_i64m4_tumu(vbool16_t mask,vint64m4_t maskedoff,vint64m4_t op1,vuint64m4_t op2,size_t vl)1295 vint64m4_t test_vmulhsu_vv_i64m4_tumu(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, vuint64m4_t op2, size_t vl) {
1296 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1297 }
1298
1299 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmulhsu_vx_i64m4_tumu
1300 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1301 // CHECK-RV64-NEXT: entry:
1302 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], i64 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
1303 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
1304 //
test_vmulhsu_vx_i64m4_tumu(vbool16_t mask,vint64m4_t maskedoff,vint64m4_t op1,uint64_t op2,size_t vl)1305 vint64m4_t test_vmulhsu_vx_i64m4_tumu(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, uint64_t op2, size_t vl) {
1306 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1307 }
1308
1309 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmulhsu_vv_i64m8_tumu
1310 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1311 // CHECK-RV64-NEXT: entry:
1312 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1313 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
1314 //
test_vmulhsu_vv_i64m8_tumu(vbool8_t mask,vint64m8_t maskedoff,vint64m8_t op1,vuint64m8_t op2,size_t vl)1315 vint64m8_t test_vmulhsu_vv_i64m8_tumu(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, vuint64m8_t op2, size_t vl) {
1316 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1317 }
1318
1319 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmulhsu_vx_i64m8_tumu
1320 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1321 // CHECK-RV64-NEXT: entry:
1322 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], i64 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
1323 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
1324 //
test_vmulhsu_vx_i64m8_tumu(vbool8_t mask,vint64m8_t maskedoff,vint64m8_t op1,uint64_t op2,size_t vl)1325 vint64m8_t test_vmulhsu_vx_i64m8_tumu(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, uint64_t op2, size_t vl) {
1326 return __riscv_vmulhsu_tumu(mask, maskedoff, op1, op2, vl);
1327 }
1328
1329 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8_mu
1330 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1331 // CHECK-RV64-NEXT: entry:
1332 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
1333 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
1334 //
test_vmulhsu_vv_i8mf8_mu(vbool64_t mask,vint8mf8_t maskedoff,vint8mf8_t op1,vuint8mf8_t op2,size_t vl)1335 vint8mf8_t test_vmulhsu_vv_i8mf8_mu(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
1336 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1337 }
1338
1339 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8_mu
1340 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1341 // CHECK-RV64-NEXT: entry:
1342 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
1343 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
1344 //
test_vmulhsu_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t maskedoff,vint8mf8_t op1,uint8_t op2,size_t vl)1345 vint8mf8_t test_vmulhsu_vx_i8mf8_mu(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, uint8_t op2, size_t vl) {
1346 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1347 }
1348
1349 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4_mu
1350 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1351 // CHECK-RV64-NEXT: entry:
1352 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
1353 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
1354 //
test_vmulhsu_vv_i8mf4_mu(vbool32_t mask,vint8mf4_t maskedoff,vint8mf4_t op1,vuint8mf4_t op2,size_t vl)1355 vint8mf4_t test_vmulhsu_vv_i8mf4_mu(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
1356 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1357 }
1358
1359 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4_mu
1360 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1361 // CHECK-RV64-NEXT: entry:
1362 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
1363 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
1364 //
test_vmulhsu_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t maskedoff,vint8mf4_t op1,uint8_t op2,size_t vl)1365 vint8mf4_t test_vmulhsu_vx_i8mf4_mu(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, uint8_t op2, size_t vl) {
1366 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1367 }
1368
1369 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2_mu
1370 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1371 // CHECK-RV64-NEXT: entry:
1372 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
1373 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
1374 //
test_vmulhsu_vv_i8mf2_mu(vbool16_t mask,vint8mf2_t maskedoff,vint8mf2_t op1,vuint8mf2_t op2,size_t vl)1375 vint8mf2_t test_vmulhsu_vv_i8mf2_mu(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
1376 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1377 }
1378
1379 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2_mu
1380 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1381 // CHECK-RV64-NEXT: entry:
1382 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
1383 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
1384 //
test_vmulhsu_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t maskedoff,vint8mf2_t op1,uint8_t op2,size_t vl)1385 vint8mf2_t test_vmulhsu_vx_i8mf2_mu(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, uint8_t op2, size_t vl) {
1386 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1387 }
1388
1389 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1_mu
1390 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1391 // CHECK-RV64-NEXT: entry:
1392 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
1393 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
1394 //
test_vmulhsu_vv_i8m1_mu(vbool8_t mask,vint8m1_t maskedoff,vint8m1_t op1,vuint8m1_t op2,size_t vl)1395 vint8m1_t test_vmulhsu_vv_i8m1_mu(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, vuint8m1_t op2, size_t vl) {
1396 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1397 }
1398
1399 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1_mu
1400 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1401 // CHECK-RV64-NEXT: entry:
1402 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
1403 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
1404 //
test_vmulhsu_vx_i8m1_mu(vbool8_t mask,vint8m1_t maskedoff,vint8m1_t op1,uint8_t op2,size_t vl)1405 vint8m1_t test_vmulhsu_vx_i8m1_mu(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, uint8_t op2, size_t vl) {
1406 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1407 }
1408
1409 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2_mu
1410 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1411 // CHECK-RV64-NEXT: entry:
1412 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
1413 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
1414 //
test_vmulhsu_vv_i8m2_mu(vbool4_t mask,vint8m2_t maskedoff,vint8m2_t op1,vuint8m2_t op2,size_t vl)1415 vint8m2_t test_vmulhsu_vv_i8m2_mu(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, vuint8m2_t op2, size_t vl) {
1416 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1417 }
1418
1419 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2_mu
1420 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1421 // CHECK-RV64-NEXT: entry:
1422 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
1423 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
1424 //
test_vmulhsu_vx_i8m2_mu(vbool4_t mask,vint8m2_t maskedoff,vint8m2_t op1,uint8_t op2,size_t vl)1425 vint8m2_t test_vmulhsu_vx_i8m2_mu(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, uint8_t op2, size_t vl) {
1426 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1427 }
1428
1429 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4_mu
1430 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1431 // CHECK-RV64-NEXT: entry:
1432 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)
1433 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
1434 //
test_vmulhsu_vv_i8m4_mu(vbool2_t mask,vint8m4_t maskedoff,vint8m4_t op1,vuint8m4_t op2,size_t vl)1435 vint8m4_t test_vmulhsu_vv_i8m4_mu(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, vuint8m4_t op2, size_t vl) {
1436 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1437 }
1438
1439 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vmulhsu_vx_i8m4_mu
1440 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1441 // CHECK-RV64-NEXT: entry:
1442 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)
1443 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
1444 //
test_vmulhsu_vx_i8m4_mu(vbool2_t mask,vint8m4_t maskedoff,vint8m4_t op1,uint8_t op2,size_t vl)1445 vint8m4_t test_vmulhsu_vx_i8m4_mu(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, uint8_t op2, size_t vl) {
1446 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1447 }
1448
1449 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmulhsu_vv_i8m8_mu
1450 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1451 // CHECK-RV64-NEXT: entry:
1452 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 1)
1453 // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
1454 //
test_vmulhsu_vv_i8m8_mu(vbool1_t mask,vint8m8_t maskedoff,vint8m8_t op1,vuint8m8_t op2,size_t vl)1455 vint8m8_t test_vmulhsu_vv_i8m8_mu(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, vuint8m8_t op2, size_t vl) {
1456 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1457 }
1458
1459 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vmulhsu_vx_i8m8_mu
1460 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1461 // CHECK-RV64-NEXT: entry:
1462 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], i8 [[OP2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 1)
1463 // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
1464 //
test_vmulhsu_vx_i8m8_mu(vbool1_t mask,vint8m8_t maskedoff,vint8m8_t op1,uint8_t op2,size_t vl)1465 vint8m8_t test_vmulhsu_vx_i8m8_mu(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, uint8_t op2, size_t vl) {
1466 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1467 }
1468
1469 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmulhsu_vv_i16mf4_mu
1470 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1471 // CHECK-RV64-NEXT: entry:
1472 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
1473 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
1474 //
test_vmulhsu_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t maskedoff,vint16mf4_t op1,vuint16mf4_t op2,size_t vl)1475 vint16mf4_t test_vmulhsu_vv_i16mf4_mu(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
1476 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1477 }
1478
1479 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vmulhsu_vx_i16mf4_mu
1480 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1481 // CHECK-RV64-NEXT: entry:
1482 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
1483 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
1484 //
test_vmulhsu_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t maskedoff,vint16mf4_t op1,uint16_t op2,size_t vl)1485 vint16mf4_t test_vmulhsu_vx_i16mf4_mu(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, uint16_t op2, size_t vl) {
1486 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1487 }
1488
1489 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmulhsu_vv_i16mf2_mu
1490 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1491 // CHECK-RV64-NEXT: entry:
1492 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
1493 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
1494 //
test_vmulhsu_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t maskedoff,vint16mf2_t op1,vuint16mf2_t op2,size_t vl)1495 vint16mf2_t test_vmulhsu_vv_i16mf2_mu(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
1496 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1497 }
1498
1499 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vmulhsu_vx_i16mf2_mu
1500 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1501 // CHECK-RV64-NEXT: entry:
1502 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
1503 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
1504 //
test_vmulhsu_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t maskedoff,vint16mf2_t op1,uint16_t op2,size_t vl)1505 vint16mf2_t test_vmulhsu_vx_i16mf2_mu(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, uint16_t op2, size_t vl) {
1506 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1507 }
1508
1509 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmulhsu_vv_i16m1_mu
1510 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1511 // CHECK-RV64-NEXT: entry:
1512 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmulhsu.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
1513 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
1514 //
test_vmulhsu_vv_i16m1_mu(vbool16_t mask,vint16m1_t maskedoff,vint16m1_t op1,vuint16m1_t op2,size_t vl)1515 vint16m1_t test_vmulhsu_vv_i16m1_mu(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, vuint16m1_t op2, size_t vl) {
1516 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1517 }
1518
1519 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vmulhsu_vx_i16m1_mu
1520 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1521 // CHECK-RV64-NEXT: entry:
1522 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vmulhsu.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
1523 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
1524 //
test_vmulhsu_vx_i16m1_mu(vbool16_t mask,vint16m1_t maskedoff,vint16m1_t op1,uint16_t op2,size_t vl)1525 vint16m1_t test_vmulhsu_vx_i16m1_mu(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, uint16_t op2, size_t vl) {
1526 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1527 }
1528
1529 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmulhsu_vv_i16m2_mu
1530 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1531 // CHECK-RV64-NEXT: entry:
1532 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmulhsu.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
1533 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
1534 //
test_vmulhsu_vv_i16m2_mu(vbool8_t mask,vint16m2_t maskedoff,vint16m2_t op1,vuint16m2_t op2,size_t vl)1535 vint16m2_t test_vmulhsu_vv_i16m2_mu(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, vuint16m2_t op2, size_t vl) {
1536 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1537 }
1538
1539 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vmulhsu_vx_i16m2_mu
1540 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1541 // CHECK-RV64-NEXT: entry:
1542 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vmulhsu.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
1543 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
1544 //
test_vmulhsu_vx_i16m2_mu(vbool8_t mask,vint16m2_t maskedoff,vint16m2_t op1,uint16_t op2,size_t vl)1545 vint16m2_t test_vmulhsu_vx_i16m2_mu(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, uint16_t op2, size_t vl) {
1546 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1547 }
1548
1549 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmulhsu_vv_i16m4_mu
1550 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1551 // CHECK-RV64-NEXT: entry:
1552 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmulhsu.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
1553 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
1554 //
test_vmulhsu_vv_i16m4_mu(vbool4_t mask,vint16m4_t maskedoff,vint16m4_t op1,vuint16m4_t op2,size_t vl)1555 vint16m4_t test_vmulhsu_vv_i16m4_mu(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, vuint16m4_t op2, size_t vl) {
1556 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1557 }
1558
1559 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vmulhsu_vx_i16m4_mu
1560 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1561 // CHECK-RV64-NEXT: entry:
1562 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vmulhsu.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
1563 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
1564 //
test_vmulhsu_vx_i16m4_mu(vbool4_t mask,vint16m4_t maskedoff,vint16m4_t op1,uint16_t op2,size_t vl)1565 vint16m4_t test_vmulhsu_vx_i16m4_mu(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, uint16_t op2, size_t vl) {
1566 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1567 }
1568
1569 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmulhsu_vv_i16m8_mu
1570 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1571 // CHECK-RV64-NEXT: entry:
1572 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)
1573 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
1574 //
test_vmulhsu_vv_i16m8_mu(vbool2_t mask,vint16m8_t maskedoff,vint16m8_t op1,vuint16m8_t op2,size_t vl)1575 vint16m8_t test_vmulhsu_vv_i16m8_mu(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, vuint16m8_t op2, size_t vl) {
1576 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1577 }
1578
1579 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vmulhsu_vx_i16m8_mu
1580 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1581 // CHECK-RV64-NEXT: entry:
1582 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], i16 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)
1583 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
1584 //
test_vmulhsu_vx_i16m8_mu(vbool2_t mask,vint16m8_t maskedoff,vint16m8_t op1,uint16_t op2,size_t vl)1585 vint16m8_t test_vmulhsu_vx_i16m8_mu(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, uint16_t op2, size_t vl) {
1586 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1587 }
1588
1589 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmulhsu_vv_i32mf2_mu
1590 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1591 // CHECK-RV64-NEXT: entry:
1592 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
1593 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
1594 //
test_vmulhsu_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t maskedoff,vint32mf2_t op1,vuint32mf2_t op2,size_t vl)1595 vint32mf2_t test_vmulhsu_vv_i32mf2_mu(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
1596 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1597 }
1598
1599 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vmulhsu_vx_i32mf2_mu
1600 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1601 // CHECK-RV64-NEXT: entry:
1602 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
1603 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
1604 //
test_vmulhsu_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t maskedoff,vint32mf2_t op1,uint32_t op2,size_t vl)1605 vint32mf2_t test_vmulhsu_vx_i32mf2_mu(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, uint32_t op2, size_t vl) {
1606 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1607 }
1608
1609 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmulhsu_vv_i32m1_mu
1610 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1611 // CHECK-RV64-NEXT: entry:
1612 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
1613 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
1614 //
test_vmulhsu_vv_i32m1_mu(vbool32_t mask,vint32m1_t maskedoff,vint32m1_t op1,vuint32m1_t op2,size_t vl)1615 vint32m1_t test_vmulhsu_vv_i32m1_mu(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, vuint32m1_t op2, size_t vl) {
1616 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1617 }
1618
1619 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vmulhsu_vx_i32m1_mu
1620 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1621 // CHECK-RV64-NEXT: entry:
1622 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
1623 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
1624 //
test_vmulhsu_vx_i32m1_mu(vbool32_t mask,vint32m1_t maskedoff,vint32m1_t op1,uint32_t op2,size_t vl)1625 vint32m1_t test_vmulhsu_vx_i32m1_mu(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, uint32_t op2, size_t vl) {
1626 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1627 }
1628
1629 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmulhsu_vv_i32m2_mu
1630 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1631 // CHECK-RV64-NEXT: entry:
1632 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmulhsu.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
1633 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
1634 //
test_vmulhsu_vv_i32m2_mu(vbool16_t mask,vint32m2_t maskedoff,vint32m2_t op1,vuint32m2_t op2,size_t vl)1635 vint32m2_t test_vmulhsu_vv_i32m2_mu(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, vuint32m2_t op2, size_t vl) {
1636 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1637 }
1638
1639 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vmulhsu_vx_i32m2_mu
1640 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1641 // CHECK-RV64-NEXT: entry:
1642 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vmulhsu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
1643 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
1644 //
test_vmulhsu_vx_i32m2_mu(vbool16_t mask,vint32m2_t maskedoff,vint32m2_t op1,uint32_t op2,size_t vl)1645 vint32m2_t test_vmulhsu_vx_i32m2_mu(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, uint32_t op2, size_t vl) {
1646 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1647 }
1648
1649 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmulhsu_vv_i32m4_mu
1650 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1651 // CHECK-RV64-NEXT: entry:
1652 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmulhsu.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
1653 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
1654 //
test_vmulhsu_vv_i32m4_mu(vbool8_t mask,vint32m4_t maskedoff,vint32m4_t op1,vuint32m4_t op2,size_t vl)1655 vint32m4_t test_vmulhsu_vv_i32m4_mu(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, vuint32m4_t op2, size_t vl) {
1656 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1657 }
1658
1659 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vmulhsu_vx_i32m4_mu
1660 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1661 // CHECK-RV64-NEXT: entry:
1662 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vmulhsu.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
1663 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
1664 //
test_vmulhsu_vx_i32m4_mu(vbool8_t mask,vint32m4_t maskedoff,vint32m4_t op1,uint32_t op2,size_t vl)1665 vint32m4_t test_vmulhsu_vx_i32m4_mu(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, uint32_t op2, size_t vl) {
1666 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1667 }
1668
1669 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmulhsu_vv_i32m8_mu
1670 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1671 // CHECK-RV64-NEXT: entry:
1672 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
1673 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
1674 //
test_vmulhsu_vv_i32m8_mu(vbool4_t mask,vint32m8_t maskedoff,vint32m8_t op1,vuint32m8_t op2,size_t vl)1675 vint32m8_t test_vmulhsu_vv_i32m8_mu(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, vuint32m8_t op2, size_t vl) {
1676 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1677 }
1678
1679 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vmulhsu_vx_i32m8_mu
1680 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1681 // CHECK-RV64-NEXT: entry:
1682 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], i32 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
1683 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
1684 //
test_vmulhsu_vx_i32m8_mu(vbool4_t mask,vint32m8_t maskedoff,vint32m8_t op1,uint32_t op2,size_t vl)1685 vint32m8_t test_vmulhsu_vx_i32m8_mu(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, uint32_t op2, size_t vl) {
1686 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1687 }
1688
1689 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1_mu
1690 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1691 // CHECK-RV64-NEXT: entry:
1692 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
1693 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
1694 //
test_vmulhsu_vv_i64m1_mu(vbool64_t mask,vint64m1_t maskedoff,vint64m1_t op1,vuint64m1_t op2,size_t vl)1695 vint64m1_t test_vmulhsu_vv_i64m1_mu(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, vuint64m1_t op2, size_t vl) {
1696 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1697 }
1698
1699 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1_mu
1700 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1701 // CHECK-RV64-NEXT: entry:
1702 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], i64 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
1703 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
1704 //
test_vmulhsu_vx_i64m1_mu(vbool64_t mask,vint64m1_t maskedoff,vint64m1_t op1,uint64_t op2,size_t vl)1705 vint64m1_t test_vmulhsu_vx_i64m1_mu(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, uint64_t op2, size_t vl) {
1706 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1707 }
1708
1709 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmulhsu_vv_i64m2_mu
1710 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1711 // CHECK-RV64-NEXT: entry:
1712 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
1713 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
1714 //
test_vmulhsu_vv_i64m2_mu(vbool32_t mask,vint64m2_t maskedoff,vint64m2_t op1,vuint64m2_t op2,size_t vl)1715 vint64m2_t test_vmulhsu_vv_i64m2_mu(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, vuint64m2_t op2, size_t vl) {
1716 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1717 }
1718
1719 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vmulhsu_vx_i64m2_mu
1720 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1721 // CHECK-RV64-NEXT: entry:
1722 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], i64 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
1723 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
1724 //
test_vmulhsu_vx_i64m2_mu(vbool32_t mask,vint64m2_t maskedoff,vint64m2_t op1,uint64_t op2,size_t vl)1725 vint64m2_t test_vmulhsu_vx_i64m2_mu(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, uint64_t op2, size_t vl) {
1726 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1727 }
1728
1729 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmulhsu_vv_i64m4_mu
1730 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1731 // CHECK-RV64-NEXT: entry:
1732 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
1733 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
1734 //
test_vmulhsu_vv_i64m4_mu(vbool16_t mask,vint64m4_t maskedoff,vint64m4_t op1,vuint64m4_t op2,size_t vl)1735 vint64m4_t test_vmulhsu_vv_i64m4_mu(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, vuint64m4_t op2, size_t vl) {
1736 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1737 }
1738
1739 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vmulhsu_vx_i64m4_mu
1740 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1741 // CHECK-RV64-NEXT: entry:
1742 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], i64 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
1743 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
1744 //
test_vmulhsu_vx_i64m4_mu(vbool16_t mask,vint64m4_t maskedoff,vint64m4_t op1,uint64_t op2,size_t vl)1745 vint64m4_t test_vmulhsu_vx_i64m4_mu(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, uint64_t op2, size_t vl) {
1746 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1747 }
1748
1749 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmulhsu_vv_i64m8_mu
1750 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1751 // CHECK-RV64-NEXT: entry:
1752 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
1753 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
1754 //
test_vmulhsu_vv_i64m8_mu(vbool8_t mask,vint64m8_t maskedoff,vint64m8_t op1,vuint64m8_t op2,size_t vl)1755 vint64m8_t test_vmulhsu_vv_i64m8_mu(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, vuint64m8_t op2, size_t vl) {
1756 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1757 }
1758
1759 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vmulhsu_vx_i64m8_mu
1760 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1761 // CHECK-RV64-NEXT: entry:
1762 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], i64 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
1763 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
1764 //
test_vmulhsu_vx_i64m8_mu(vbool8_t mask,vint64m8_t maskedoff,vint64m8_t op1,uint64_t op2,size_t vl)1765 vint64m8_t test_vmulhsu_vx_i64m8_mu(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, uint64_t op2, size_t vl) {
1766 return __riscv_vmulhsu_mu(mask, maskedoff, op1, op2, vl);
1767 }
1768
1769