1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4 // RUN: -target-feature +zvfh -disable-O0-optnone \
5 // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
6 // RUN: FileCheck --check-prefix=CHECK-RV64 %s
7
8 #include <riscv_vector.h>
9
10 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_tu
11 // CHECK-RV64-SAME: (<vscale x 1 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
12 // CHECK-RV64-NEXT: entry:
13 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])
14 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP0]], 0
15 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP0]], 1
16 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 1
17 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
18 //
test_vle8ff_v_i8mf8_tu(vint8mf8_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)19 vint8mf8_t test_vle8ff_v_i8mf8_tu(vint8mf8_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
20 return __riscv_vle8ff_tu(maskedoff, base, new_vl, vl);
21 }
22
23 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_tu
24 // CHECK-RV64-SAME: (<vscale x 2 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
25 // CHECK-RV64-NEXT: entry:
26 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])
27 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP0]], 0
28 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP0]], 1
29 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 1
30 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
31 //
test_vle8ff_v_i8mf4_tu(vint8mf4_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)32 vint8mf4_t test_vle8ff_v_i8mf4_tu(vint8mf4_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
33 return __riscv_vle8ff_tu(maskedoff, base, new_vl, vl);
34 }
35
36 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_tu
37 // CHECK-RV64-SAME: (<vscale x 4 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
38 // CHECK-RV64-NEXT: entry:
39 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])
40 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP0]], 0
41 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP0]], 1
42 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 1
43 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
44 //
test_vle8ff_v_i8mf2_tu(vint8mf2_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)45 vint8mf2_t test_vle8ff_v_i8mf2_tu(vint8mf2_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
46 return __riscv_vle8ff_tu(maskedoff, base, new_vl, vl);
47 }
48
49 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_tu
50 // CHECK-RV64-SAME: (<vscale x 8 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
51 // CHECK-RV64-NEXT: entry:
52 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])
53 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP0]], 0
54 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP0]], 1
55 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 1
56 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
57 //
test_vle8ff_v_i8m1_tu(vint8m1_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)58 vint8m1_t test_vle8ff_v_i8m1_tu(vint8m1_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
59 return __riscv_vle8ff_tu(maskedoff, base, new_vl, vl);
60 }
61
62 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_tu
63 // CHECK-RV64-SAME: (<vscale x 16 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
64 // CHECK-RV64-NEXT: entry:
65 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])
66 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP0]], 0
67 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP0]], 1
68 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 1
69 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
70 //
test_vle8ff_v_i8m2_tu(vint8m2_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)71 vint8m2_t test_vle8ff_v_i8m2_tu(vint8m2_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
72 return __riscv_vle8ff_tu(maskedoff, base, new_vl, vl);
73 }
74
75 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_tu
76 // CHECK-RV64-SAME: (<vscale x 32 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
77 // CHECK-RV64-NEXT: entry:
78 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])
79 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP0]], 0
80 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP0]], 1
81 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 1
82 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
83 //
test_vle8ff_v_i8m4_tu(vint8m4_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)84 vint8m4_t test_vle8ff_v_i8m4_tu(vint8m4_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
85 return __riscv_vle8ff_tu(maskedoff, base, new_vl, vl);
86 }
87
88 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_tu
89 // CHECK-RV64-SAME: (<vscale x 64 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
90 // CHECK-RV64-NEXT: entry:
91 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])
92 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP0]], 0
93 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP0]], 1
94 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 1
95 // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
96 //
test_vle8ff_v_i8m8_tu(vint8m8_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)97 vint8m8_t test_vle8ff_v_i8m8_tu(vint8m8_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
98 return __riscv_vle8ff_tu(maskedoff, base, new_vl, vl);
99 }
100
101 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_tu
102 // CHECK-RV64-SAME: (<vscale x 1 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
103 // CHECK-RV64-NEXT: entry:
104 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])
105 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP0]], 0
106 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP0]], 1
107 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 1
108 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
109 //
test_vle8ff_v_u8mf8_tu(vuint8mf8_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)110 vuint8mf8_t test_vle8ff_v_u8mf8_tu(vuint8mf8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
111 return __riscv_vle8ff_tu(maskedoff, base, new_vl, vl);
112 }
113
114 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4_tu
115 // CHECK-RV64-SAME: (<vscale x 2 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
116 // CHECK-RV64-NEXT: entry:
117 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])
118 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP0]], 0
119 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP0]], 1
120 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 1
121 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
122 //
test_vle8ff_v_u8mf4_tu(vuint8mf4_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)123 vuint8mf4_t test_vle8ff_v_u8mf4_tu(vuint8mf4_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
124 return __riscv_vle8ff_tu(maskedoff, base, new_vl, vl);
125 }
126
127 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vle8ff_v_u8mf2_tu
128 // CHECK-RV64-SAME: (<vscale x 4 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
129 // CHECK-RV64-NEXT: entry:
130 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])
131 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP0]], 0
132 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP0]], 1
133 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 1
134 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
135 //
test_vle8ff_v_u8mf2_tu(vuint8mf2_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)136 vuint8mf2_t test_vle8ff_v_u8mf2_tu(vuint8mf2_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
137 return __riscv_vle8ff_tu(maskedoff, base, new_vl, vl);
138 }
139
140 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vle8ff_v_u8m1_tu
141 // CHECK-RV64-SAME: (<vscale x 8 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
142 // CHECK-RV64-NEXT: entry:
143 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])
144 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP0]], 0
145 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP0]], 1
146 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 1
147 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
148 //
test_vle8ff_v_u8m1_tu(vuint8m1_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)149 vuint8m1_t test_vle8ff_v_u8m1_tu(vuint8m1_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
150 return __riscv_vle8ff_tu(maskedoff, base, new_vl, vl);
151 }
152
153 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vle8ff_v_u8m2_tu
154 // CHECK-RV64-SAME: (<vscale x 16 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
155 // CHECK-RV64-NEXT: entry:
156 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])
157 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP0]], 0
158 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP0]], 1
159 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 1
160 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
161 //
test_vle8ff_v_u8m2_tu(vuint8m2_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)162 vuint8m2_t test_vle8ff_v_u8m2_tu(vuint8m2_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
163 return __riscv_vle8ff_tu(maskedoff, base, new_vl, vl);
164 }
165
166 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vle8ff_v_u8m4_tu
167 // CHECK-RV64-SAME: (<vscale x 32 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
168 // CHECK-RV64-NEXT: entry:
169 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])
170 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP0]], 0
171 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP0]], 1
172 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 1
173 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
174 //
test_vle8ff_v_u8m4_tu(vuint8m4_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)175 vuint8m4_t test_vle8ff_v_u8m4_tu(vuint8m4_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
176 return __riscv_vle8ff_tu(maskedoff, base, new_vl, vl);
177 }
178
179 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vle8ff_v_u8m8_tu
180 // CHECK-RV64-SAME: (<vscale x 64 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
181 // CHECK-RV64-NEXT: entry:
182 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], ptr [[BASE]], i64 [[VL]])
183 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP0]], 0
184 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP0]], 1
185 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 1
186 // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
187 //
test_vle8ff_v_u8m8_tu(vuint8m8_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)188 vuint8m8_t test_vle8ff_v_u8m8_tu(vuint8m8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
189 return __riscv_vle8ff_tu(maskedoff, base, new_vl, vl);
190 }
191
192 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_tum
193 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
194 // CHECK-RV64-NEXT: entry:
195 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
196 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP0]], 0
197 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP0]], 1
198 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
199 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
200 //
test_vle8ff_v_i8mf8_tum(vbool64_t mask,vint8mf8_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)201 vint8mf8_t test_vle8ff_v_i8mf8_tum(vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
202 return __riscv_vle8ff_tum(mask, maskedoff, base, new_vl, vl);
203 }
204
205 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_tum
206 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
207 // CHECK-RV64-NEXT: entry:
208 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
209 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP0]], 0
210 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP0]], 1
211 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
212 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
213 //
test_vle8ff_v_i8mf4_tum(vbool32_t mask,vint8mf4_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)214 vint8mf4_t test_vle8ff_v_i8mf4_tum(vbool32_t mask, vint8mf4_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
215 return __riscv_vle8ff_tum(mask, maskedoff, base, new_vl, vl);
216 }
217
218 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_tum
219 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
220 // CHECK-RV64-NEXT: entry:
221 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
222 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP0]], 0
223 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP0]], 1
224 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
225 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
226 //
test_vle8ff_v_i8mf2_tum(vbool16_t mask,vint8mf2_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)227 vint8mf2_t test_vle8ff_v_i8mf2_tum(vbool16_t mask, vint8mf2_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
228 return __riscv_vle8ff_tum(mask, maskedoff, base, new_vl, vl);
229 }
230
231 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_tum
232 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
233 // CHECK-RV64-NEXT: entry:
234 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
235 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP0]], 0
236 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP0]], 1
237 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
238 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
239 //
test_vle8ff_v_i8m1_tum(vbool8_t mask,vint8m1_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)240 vint8m1_t test_vle8ff_v_i8m1_tum(vbool8_t mask, vint8m1_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
241 return __riscv_vle8ff_tum(mask, maskedoff, base, new_vl, vl);
242 }
243
244 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_tum
245 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
246 // CHECK-RV64-NEXT: entry:
247 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
248 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP0]], 0
249 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP0]], 1
250 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
251 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
252 //
test_vle8ff_v_i8m2_tum(vbool4_t mask,vint8m2_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)253 vint8m2_t test_vle8ff_v_i8m2_tum(vbool4_t mask, vint8m2_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
254 return __riscv_vle8ff_tum(mask, maskedoff, base, new_vl, vl);
255 }
256
257 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_tum
258 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
259 // CHECK-RV64-NEXT: entry:
260 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)
261 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP0]], 0
262 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP0]], 1
263 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
264 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
265 //
test_vle8ff_v_i8m4_tum(vbool2_t mask,vint8m4_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)266 vint8m4_t test_vle8ff_v_i8m4_tum(vbool2_t mask, vint8m4_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
267 return __riscv_vle8ff_tum(mask, maskedoff, base, new_vl, vl);
268 }
269
270 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_tum
271 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
272 // CHECK-RV64-NEXT: entry:
273 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 2)
274 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP0]], 0
275 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP0]], 1
276 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
277 // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
278 //
test_vle8ff_v_i8m8_tum(vbool1_t mask,vint8m8_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)279 vint8m8_t test_vle8ff_v_i8m8_tum(vbool1_t mask, vint8m8_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
280 return __riscv_vle8ff_tum(mask, maskedoff, base, new_vl, vl);
281 }
282
283 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_tum
284 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
285 // CHECK-RV64-NEXT: entry:
286 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
287 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP0]], 0
288 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP0]], 1
289 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
290 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
291 //
test_vle8ff_v_u8mf8_tum(vbool64_t mask,vuint8mf8_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)292 vuint8mf8_t test_vle8ff_v_u8mf8_tum(vbool64_t mask, vuint8mf8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
293 return __riscv_vle8ff_tum(mask, maskedoff, base, new_vl, vl);
294 }
295
296 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4_tum
297 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
298 // CHECK-RV64-NEXT: entry:
299 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
300 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP0]], 0
301 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP0]], 1
302 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
303 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
304 //
test_vle8ff_v_u8mf4_tum(vbool32_t mask,vuint8mf4_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)305 vuint8mf4_t test_vle8ff_v_u8mf4_tum(vbool32_t mask, vuint8mf4_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
306 return __riscv_vle8ff_tum(mask, maskedoff, base, new_vl, vl);
307 }
308
309 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vle8ff_v_u8mf2_tum
310 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
311 // CHECK-RV64-NEXT: entry:
312 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
313 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP0]], 0
314 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP0]], 1
315 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
316 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
317 //
test_vle8ff_v_u8mf2_tum(vbool16_t mask,vuint8mf2_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)318 vuint8mf2_t test_vle8ff_v_u8mf2_tum(vbool16_t mask, vuint8mf2_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
319 return __riscv_vle8ff_tum(mask, maskedoff, base, new_vl, vl);
320 }
321
322 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vle8ff_v_u8m1_tum
323 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
324 // CHECK-RV64-NEXT: entry:
325 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
326 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP0]], 0
327 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP0]], 1
328 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
329 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
330 //
test_vle8ff_v_u8m1_tum(vbool8_t mask,vuint8m1_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)331 vuint8m1_t test_vle8ff_v_u8m1_tum(vbool8_t mask, vuint8m1_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
332 return __riscv_vle8ff_tum(mask, maskedoff, base, new_vl, vl);
333 }
334
335 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vle8ff_v_u8m2_tum
336 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
337 // CHECK-RV64-NEXT: entry:
338 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
339 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP0]], 0
340 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP0]], 1
341 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
342 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
343 //
test_vle8ff_v_u8m2_tum(vbool4_t mask,vuint8m2_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)344 vuint8m2_t test_vle8ff_v_u8m2_tum(vbool4_t mask, vuint8m2_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
345 return __riscv_vle8ff_tum(mask, maskedoff, base, new_vl, vl);
346 }
347
348 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vle8ff_v_u8m4_tum
349 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
350 // CHECK-RV64-NEXT: entry:
351 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)
352 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP0]], 0
353 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP0]], 1
354 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
355 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
356 //
test_vle8ff_v_u8m4_tum(vbool2_t mask,vuint8m4_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)357 vuint8m4_t test_vle8ff_v_u8m4_tum(vbool2_t mask, vuint8m4_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
358 return __riscv_vle8ff_tum(mask, maskedoff, base, new_vl, vl);
359 }
360
361 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vle8ff_v_u8m8_tum
362 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
363 // CHECK-RV64-NEXT: entry:
364 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 2)
365 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP0]], 0
366 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP0]], 1
367 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
368 // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
369 //
test_vle8ff_v_u8m8_tum(vbool1_t mask,vuint8m8_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)370 vuint8m8_t test_vle8ff_v_u8m8_tum(vbool1_t mask, vuint8m8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
371 return __riscv_vle8ff_tum(mask, maskedoff, base, new_vl, vl);
372 }
373
374 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_tumu
375 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
376 // CHECK-RV64-NEXT: entry:
377 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
378 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP0]], 0
379 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP0]], 1
380 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
381 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
382 //
test_vle8ff_v_i8mf8_tumu(vbool64_t mask,vint8mf8_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)383 vint8mf8_t test_vle8ff_v_i8mf8_tumu(vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
384 return __riscv_vle8ff_tumu(mask, maskedoff, base, new_vl, vl);
385 }
386
387 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_tumu
388 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
389 // CHECK-RV64-NEXT: entry:
390 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
391 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP0]], 0
392 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP0]], 1
393 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
394 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
395 //
test_vle8ff_v_i8mf4_tumu(vbool32_t mask,vint8mf4_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)396 vint8mf4_t test_vle8ff_v_i8mf4_tumu(vbool32_t mask, vint8mf4_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
397 return __riscv_vle8ff_tumu(mask, maskedoff, base, new_vl, vl);
398 }
399
400 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_tumu
401 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
402 // CHECK-RV64-NEXT: entry:
403 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
404 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP0]], 0
405 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP0]], 1
406 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
407 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
408 //
test_vle8ff_v_i8mf2_tumu(vbool16_t mask,vint8mf2_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)409 vint8mf2_t test_vle8ff_v_i8mf2_tumu(vbool16_t mask, vint8mf2_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
410 return __riscv_vle8ff_tumu(mask, maskedoff, base, new_vl, vl);
411 }
412
413 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_tumu
414 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
415 // CHECK-RV64-NEXT: entry:
416 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
417 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP0]], 0
418 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP0]], 1
419 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
420 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
421 //
test_vle8ff_v_i8m1_tumu(vbool8_t mask,vint8m1_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)422 vint8m1_t test_vle8ff_v_i8m1_tumu(vbool8_t mask, vint8m1_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
423 return __riscv_vle8ff_tumu(mask, maskedoff, base, new_vl, vl);
424 }
425
426 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_tumu
427 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
428 // CHECK-RV64-NEXT: entry:
429 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
430 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP0]], 0
431 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP0]], 1
432 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
433 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
434 //
test_vle8ff_v_i8m2_tumu(vbool4_t mask,vint8m2_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)435 vint8m2_t test_vle8ff_v_i8m2_tumu(vbool4_t mask, vint8m2_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
436 return __riscv_vle8ff_tumu(mask, maskedoff, base, new_vl, vl);
437 }
438
439 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_tumu
440 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
441 // CHECK-RV64-NEXT: entry:
442 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)
443 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP0]], 0
444 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP0]], 1
445 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
446 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
447 //
test_vle8ff_v_i8m4_tumu(vbool2_t mask,vint8m4_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)448 vint8m4_t test_vle8ff_v_i8m4_tumu(vbool2_t mask, vint8m4_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
449 return __riscv_vle8ff_tumu(mask, maskedoff, base, new_vl, vl);
450 }
451
452 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_tumu
453 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
454 // CHECK-RV64-NEXT: entry:
455 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 0)
456 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP0]], 0
457 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP0]], 1
458 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
459 // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
460 //
test_vle8ff_v_i8m8_tumu(vbool1_t mask,vint8m8_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)461 vint8m8_t test_vle8ff_v_i8m8_tumu(vbool1_t mask, vint8m8_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
462 return __riscv_vle8ff_tumu(mask, maskedoff, base, new_vl, vl);
463 }
464
465 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_tumu
466 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
467 // CHECK-RV64-NEXT: entry:
468 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
469 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP0]], 0
470 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP0]], 1
471 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
472 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
473 //
test_vle8ff_v_u8mf8_tumu(vbool64_t mask,vuint8mf8_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)474 vuint8mf8_t test_vle8ff_v_u8mf8_tumu(vbool64_t mask, vuint8mf8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
475 return __riscv_vle8ff_tumu(mask, maskedoff, base, new_vl, vl);
476 }
477
478 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4_tumu
479 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
480 // CHECK-RV64-NEXT: entry:
481 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
482 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP0]], 0
483 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP0]], 1
484 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
485 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
486 //
test_vle8ff_v_u8mf4_tumu(vbool32_t mask,vuint8mf4_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)487 vuint8mf4_t test_vle8ff_v_u8mf4_tumu(vbool32_t mask, vuint8mf4_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
488 return __riscv_vle8ff_tumu(mask, maskedoff, base, new_vl, vl);
489 }
490
491 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vle8ff_v_u8mf2_tumu
492 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
493 // CHECK-RV64-NEXT: entry:
494 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
495 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP0]], 0
496 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP0]], 1
497 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
498 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
499 //
test_vle8ff_v_u8mf2_tumu(vbool16_t mask,vuint8mf2_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)500 vuint8mf2_t test_vle8ff_v_u8mf2_tumu(vbool16_t mask, vuint8mf2_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
501 return __riscv_vle8ff_tumu(mask, maskedoff, base, new_vl, vl);
502 }
503
504 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vle8ff_v_u8m1_tumu
505 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
506 // CHECK-RV64-NEXT: entry:
507 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
508 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP0]], 0
509 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP0]], 1
510 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
511 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
512 //
test_vle8ff_v_u8m1_tumu(vbool8_t mask,vuint8m1_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)513 vuint8m1_t test_vle8ff_v_u8m1_tumu(vbool8_t mask, vuint8m1_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
514 return __riscv_vle8ff_tumu(mask, maskedoff, base, new_vl, vl);
515 }
516
517 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vle8ff_v_u8m2_tumu
518 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
519 // CHECK-RV64-NEXT: entry:
520 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
521 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP0]], 0
522 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP0]], 1
523 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
524 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
525 //
test_vle8ff_v_u8m2_tumu(vbool4_t mask,vuint8m2_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)526 vuint8m2_t test_vle8ff_v_u8m2_tumu(vbool4_t mask, vuint8m2_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
527 return __riscv_vle8ff_tumu(mask, maskedoff, base, new_vl, vl);
528 }
529
530 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vle8ff_v_u8m4_tumu
531 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
532 // CHECK-RV64-NEXT: entry:
533 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)
534 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP0]], 0
535 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP0]], 1
536 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
537 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
538 //
test_vle8ff_v_u8m4_tumu(vbool2_t mask,vuint8m4_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)539 vuint8m4_t test_vle8ff_v_u8m4_tumu(vbool2_t mask, vuint8m4_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
540 return __riscv_vle8ff_tumu(mask, maskedoff, base, new_vl, vl);
541 }
542
543 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vle8ff_v_u8m8_tumu
544 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
545 // CHECK-RV64-NEXT: entry:
546 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 0)
547 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP0]], 0
548 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP0]], 1
549 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
550 // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
551 //
test_vle8ff_v_u8m8_tumu(vbool1_t mask,vuint8m8_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)552 vuint8m8_t test_vle8ff_v_u8m8_tumu(vbool1_t mask, vuint8m8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
553 return __riscv_vle8ff_tumu(mask, maskedoff, base, new_vl, vl);
554 }
555
556 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_mu
557 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
558 // CHECK-RV64-NEXT: entry:
559 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
560 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP0]], 0
561 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP0]], 1
562 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
563 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
564 //
test_vle8ff_v_i8mf8_mu(vbool64_t mask,vint8mf8_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)565 vint8mf8_t test_vle8ff_v_i8mf8_mu(vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
566 return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl);
567 }
568
569 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_mu
570 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
571 // CHECK-RV64-NEXT: entry:
572 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
573 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP0]], 0
574 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP0]], 1
575 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
576 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
577 //
test_vle8ff_v_i8mf4_mu(vbool32_t mask,vint8mf4_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)578 vint8mf4_t test_vle8ff_v_i8mf4_mu(vbool32_t mask, vint8mf4_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
579 return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl);
580 }
581
582 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_mu
583 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
584 // CHECK-RV64-NEXT: entry:
585 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
586 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP0]], 0
587 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP0]], 1
588 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
589 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
590 //
test_vle8ff_v_i8mf2_mu(vbool16_t mask,vint8mf2_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)591 vint8mf2_t test_vle8ff_v_i8mf2_mu(vbool16_t mask, vint8mf2_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
592 return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl);
593 }
594
595 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_mu
596 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
597 // CHECK-RV64-NEXT: entry:
598 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
599 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP0]], 0
600 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP0]], 1
601 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
602 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
603 //
test_vle8ff_v_i8m1_mu(vbool8_t mask,vint8m1_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)604 vint8m1_t test_vle8ff_v_i8m1_mu(vbool8_t mask, vint8m1_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
605 return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl);
606 }
607
608 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_mu
609 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
610 // CHECK-RV64-NEXT: entry:
611 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
612 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP0]], 0
613 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP0]], 1
614 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
615 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
616 //
test_vle8ff_v_i8m2_mu(vbool4_t mask,vint8m2_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)617 vint8m2_t test_vle8ff_v_i8m2_mu(vbool4_t mask, vint8m2_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
618 return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl);
619 }
620
621 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_mu
622 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
623 // CHECK-RV64-NEXT: entry:
624 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)
625 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP0]], 0
626 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP0]], 1
627 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
628 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
629 //
test_vle8ff_v_i8m4_mu(vbool2_t mask,vint8m4_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)630 vint8m4_t test_vle8ff_v_i8m4_mu(vbool2_t mask, vint8m4_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
631 return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl);
632 }
633
634 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_mu
635 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
636 // CHECK-RV64-NEXT: entry:
637 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 1)
638 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP0]], 0
639 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP0]], 1
640 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
641 // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
642 //
test_vle8ff_v_i8m8_mu(vbool1_t mask,vint8m8_t maskedoff,const int8_t * base,size_t * new_vl,size_t vl)643 vint8m8_t test_vle8ff_v_i8m8_mu(vbool1_t mask, vint8m8_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
644 return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl);
645 }
646
647 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_mu
648 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
649 // CHECK-RV64-NEXT: entry:
650 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
651 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP0]], 0
652 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i8>, i64 } [[TMP0]], 1
653 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
654 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
655 //
test_vle8ff_v_u8mf8_mu(vbool64_t mask,vuint8mf8_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)656 vuint8mf8_t test_vle8ff_v_u8mf8_mu(vbool64_t mask, vuint8mf8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
657 return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl);
658 }
659
660 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4_mu
661 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
662 // CHECK-RV64-NEXT: entry:
663 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
664 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP0]], 0
665 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i8>, i64 } [[TMP0]], 1
666 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
667 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
668 //
test_vle8ff_v_u8mf4_mu(vbool32_t mask,vuint8mf4_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)669 vuint8mf4_t test_vle8ff_v_u8mf4_mu(vbool32_t mask, vuint8mf4_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
670 return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl);
671 }
672
673 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vle8ff_v_u8mf2_mu
674 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
675 // CHECK-RV64-NEXT: entry:
676 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
677 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP0]], 0
678 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i8>, i64 } [[TMP0]], 1
679 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
680 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
681 //
test_vle8ff_v_u8mf2_mu(vbool16_t mask,vuint8mf2_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)682 vuint8mf2_t test_vle8ff_v_u8mf2_mu(vbool16_t mask, vuint8mf2_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
683 return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl);
684 }
685
686 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vle8ff_v_u8m1_mu
687 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
688 // CHECK-RV64-NEXT: entry:
689 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
690 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP0]], 0
691 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i8>, i64 } [[TMP0]], 1
692 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
693 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
694 //
test_vle8ff_v_u8m1_mu(vbool8_t mask,vuint8m1_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)695 vuint8m1_t test_vle8ff_v_u8m1_mu(vbool8_t mask, vuint8m1_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
696 return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl);
697 }
698
699 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vle8ff_v_u8m2_mu
700 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
701 // CHECK-RV64-NEXT: entry:
702 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
703 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP0]], 0
704 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 16 x i8>, i64 } [[TMP0]], 1
705 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
706 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
707 //
test_vle8ff_v_u8m2_mu(vbool4_t mask,vuint8m2_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)708 vuint8m2_t test_vle8ff_v_u8m2_mu(vbool4_t mask, vuint8m2_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
709 return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl);
710 }
711
712 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vle8ff_v_u8m4_mu
713 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
714 // CHECK-RV64-NEXT: entry:
715 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)
716 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP0]], 0
717 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 32 x i8>, i64 } [[TMP0]], 1
718 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
719 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
720 //
test_vle8ff_v_u8m4_mu(vbool2_t mask,vuint8m4_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)721 vuint8m4_t test_vle8ff_v_u8m4_mu(vbool2_t mask, vuint8m4_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
722 return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl);
723 }
724
725 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vle8ff_v_u8m8_mu
726 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
727 // CHECK-RV64-NEXT: entry:
728 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF]], ptr [[BASE]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 1)
729 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP0]], 0
730 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 64 x i8>, i64 } [[TMP0]], 1
731 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
732 // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
733 //
test_vle8ff_v_u8m8_mu(vbool1_t mask,vuint8m8_t maskedoff,const uint8_t * base,size_t * new_vl,size_t vl)734 vuint8m8_t test_vle8ff_v_u8m8_mu(vbool1_t mask, vuint8m8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
735 return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl);
736 }
737
738