1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4 // RUN: -target-feature +zvfh -disable-O0-optnone \
5 // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
6 // RUN: FileCheck --check-prefix=CHECK-RV64 %s
7
8 #include <riscv_vector.h>
9
10 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_tu
11 // CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
12 // CHECK-RV64-NEXT: entry:
13 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], <vscale x 1 x half> [[OP2]], i64 7, i64 [[VL]])
14 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
15 //
test_vfwadd_vv_f32mf2_tu(vfloat32mf2_t maskedoff,vfloat16mf4_t op1,vfloat16mf4_t op2,size_t vl)16 vfloat32mf2_t test_vfwadd_vv_f32mf2_tu(vfloat32mf2_t maskedoff, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
17 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, vl);
18 }
19
20 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_tu
21 // CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
22 // CHECK-RV64-NEXT: entry:
23 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], half [[OP2]], i64 7, i64 [[VL]])
24 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
25 //
test_vfwadd_vf_f32mf2_tu(vfloat32mf2_t maskedoff,vfloat16mf4_t op1,_Float16 op2,size_t vl)26 vfloat32mf2_t test_vfwadd_vf_f32mf2_tu(vfloat32mf2_t maskedoff, vfloat16mf4_t op1, _Float16 op2, size_t vl) {
27 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, vl);
28 }
29
30 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_tu
31 // CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
32 // CHECK-RV64-NEXT: entry:
33 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x half> [[OP2]], i64 7, i64 [[VL]])
34 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
35 //
test_vfwadd_wv_f32mf2_tu(vfloat32mf2_t maskedoff,vfloat32mf2_t op1,vfloat16mf4_t op2,size_t vl)36 vfloat32mf2_t test_vfwadd_wv_f32mf2_tu(vfloat32mf2_t maskedoff, vfloat32mf2_t op1, vfloat16mf4_t op2, size_t vl) {
37 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, vl);
38 }
39
40 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_tu
41 // CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
42 // CHECK-RV64-NEXT: entry:
43 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], half [[OP2]], i64 7, i64 [[VL]])
44 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
45 //
test_vfwadd_wf_f32mf2_tu(vfloat32mf2_t maskedoff,vfloat32mf2_t op1,_Float16 op2,size_t vl)46 vfloat32mf2_t test_vfwadd_wf_f32mf2_tu(vfloat32mf2_t maskedoff, vfloat32mf2_t op1, _Float16 op2, size_t vl) {
47 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, vl);
48 }
49
50 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_tu
51 // CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
52 // CHECK-RV64-NEXT: entry:
53 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], <vscale x 2 x half> [[OP2]], i64 7, i64 [[VL]])
54 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
55 //
test_vfwadd_vv_f32m1_tu(vfloat32m1_t maskedoff,vfloat16mf2_t op1,vfloat16mf2_t op2,size_t vl)56 vfloat32m1_t test_vfwadd_vv_f32m1_tu(vfloat32m1_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
57 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, vl);
58 }
59
60 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_tu
61 // CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
62 // CHECK-RV64-NEXT: entry:
63 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], half [[OP2]], i64 7, i64 [[VL]])
64 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
65 //
test_vfwadd_vf_f32m1_tu(vfloat32m1_t maskedoff,vfloat16mf2_t op1,_Float16 op2,size_t vl)66 vfloat32m1_t test_vfwadd_vf_f32m1_tu(vfloat32m1_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
67 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, vl);
68 }
69
70 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_tu
71 // CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
72 // CHECK-RV64-NEXT: entry:
73 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x half> [[OP2]], i64 7, i64 [[VL]])
74 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
75 //
test_vfwadd_wv_f32m1_tu(vfloat32m1_t maskedoff,vfloat32m1_t op1,vfloat16mf2_t op2,size_t vl)76 vfloat32m1_t test_vfwadd_wv_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
77 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, vl);
78 }
79
80 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_tu
81 // CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
82 // CHECK-RV64-NEXT: entry:
83 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], half [[OP2]], i64 7, i64 [[VL]])
84 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
85 //
test_vfwadd_wf_f32m1_tu(vfloat32m1_t maskedoff,vfloat32m1_t op1,_Float16 op2,size_t vl)86 vfloat32m1_t test_vfwadd_wf_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m1_t op1, _Float16 op2, size_t vl) {
87 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, vl);
88 }
89
90 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2_tu
91 // CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
92 // CHECK-RV64-NEXT: entry:
93 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], <vscale x 4 x half> [[OP2]], i64 7, i64 [[VL]])
94 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
95 //
test_vfwadd_vv_f32m2_tu(vfloat32m2_t maskedoff,vfloat16m1_t op1,vfloat16m1_t op2,size_t vl)96 vfloat32m2_t test_vfwadd_vv_f32m2_tu(vfloat32m2_t maskedoff, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
97 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, vl);
98 }
99
100 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2_tu
101 // CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
102 // CHECK-RV64-NEXT: entry:
103 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], half [[OP2]], i64 7, i64 [[VL]])
104 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
105 //
test_vfwadd_vf_f32m2_tu(vfloat32m2_t maskedoff,vfloat16m1_t op1,_Float16 op2,size_t vl)106 vfloat32m2_t test_vfwadd_vf_f32m2_tu(vfloat32m2_t maskedoff, vfloat16m1_t op1, _Float16 op2, size_t vl) {
107 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, vl);
108 }
109
110 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_wv_f32m2_tu
111 // CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
112 // CHECK-RV64-NEXT: entry:
113 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.nxv4f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x half> [[OP2]], i64 7, i64 [[VL]])
114 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
115 //
test_vfwadd_wv_f32m2_tu(vfloat32m2_t maskedoff,vfloat32m2_t op1,vfloat16m1_t op2,size_t vl)116 vfloat32m2_t test_vfwadd_wv_f32m2_tu(vfloat32m2_t maskedoff, vfloat32m2_t op1, vfloat16m1_t op2, size_t vl) {
117 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, vl);
118 }
119
120 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_wf_f32m2_tu
121 // CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
122 // CHECK-RV64-NEXT: entry:
123 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], half [[OP2]], i64 7, i64 [[VL]])
124 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
125 //
test_vfwadd_wf_f32m2_tu(vfloat32m2_t maskedoff,vfloat32m2_t op1,_Float16 op2,size_t vl)126 vfloat32m2_t test_vfwadd_wf_f32m2_tu(vfloat32m2_t maskedoff, vfloat32m2_t op1, _Float16 op2, size_t vl) {
127 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, vl);
128 }
129
130 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_vv_f32m4_tu
131 // CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
132 // CHECK-RV64-NEXT: entry:
133 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], <vscale x 8 x half> [[OP2]], i64 7, i64 [[VL]])
134 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
135 //
test_vfwadd_vv_f32m4_tu(vfloat32m4_t maskedoff,vfloat16m2_t op1,vfloat16m2_t op2,size_t vl)136 vfloat32m4_t test_vfwadd_vv_f32m4_tu(vfloat32m4_t maskedoff, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
137 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, vl);
138 }
139
140 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_vf_f32m4_tu
141 // CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
142 // CHECK-RV64-NEXT: entry:
143 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], half [[OP2]], i64 7, i64 [[VL]])
144 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
145 //
test_vfwadd_vf_f32m4_tu(vfloat32m4_t maskedoff,vfloat16m2_t op1,_Float16 op2,size_t vl)146 vfloat32m4_t test_vfwadd_vf_f32m4_tu(vfloat32m4_t maskedoff, vfloat16m2_t op1, _Float16 op2, size_t vl) {
147 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, vl);
148 }
149
150 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_wv_f32m4_tu
151 // CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
152 // CHECK-RV64-NEXT: entry:
153 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.nxv8f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x half> [[OP2]], i64 7, i64 [[VL]])
154 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
155 //
test_vfwadd_wv_f32m4_tu(vfloat32m4_t maskedoff,vfloat32m4_t op1,vfloat16m2_t op2,size_t vl)156 vfloat32m4_t test_vfwadd_wv_f32m4_tu(vfloat32m4_t maskedoff, vfloat32m4_t op1, vfloat16m2_t op2, size_t vl) {
157 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, vl);
158 }
159
160 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_wf_f32m4_tu
161 // CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
162 // CHECK-RV64-NEXT: entry:
163 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], half [[OP2]], i64 7, i64 [[VL]])
164 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
165 //
test_vfwadd_wf_f32m4_tu(vfloat32m4_t maskedoff,vfloat32m4_t op1,_Float16 op2,size_t vl)166 vfloat32m4_t test_vfwadd_wf_f32m4_tu(vfloat32m4_t maskedoff, vfloat32m4_t op1, _Float16 op2, size_t vl) {
167 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, vl);
168 }
169
170 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_vv_f32m8_tu
171 // CHECK-RV64-SAME: (<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
172 // CHECK-RV64-NEXT: entry:
173 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], <vscale x 16 x half> [[OP2]], i64 7, i64 [[VL]])
174 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
175 //
test_vfwadd_vv_f32m8_tu(vfloat32m8_t maskedoff,vfloat16m4_t op1,vfloat16m4_t op2,size_t vl)176 vfloat32m8_t test_vfwadd_vv_f32m8_tu(vfloat32m8_t maskedoff, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
177 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, vl);
178 }
179
180 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_vf_f32m8_tu
181 // CHECK-RV64-SAME: (<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
182 // CHECK-RV64-NEXT: entry:
183 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.nxv16f32.nxv16f16.f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], half [[OP2]], i64 7, i64 [[VL]])
184 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
185 //
test_vfwadd_vf_f32m8_tu(vfloat32m8_t maskedoff,vfloat16m4_t op1,_Float16 op2,size_t vl)186 vfloat32m8_t test_vfwadd_vf_f32m8_tu(vfloat32m8_t maskedoff, vfloat16m4_t op1, _Float16 op2, size_t vl) {
187 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, vl);
188 }
189
190 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_wv_f32m8_tu
191 // CHECK-RV64-SAME: (<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
192 // CHECK-RV64-NEXT: entry:
193 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f32.nxv16f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], <vscale x 16 x half> [[OP2]], i64 7, i64 [[VL]])
194 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
195 //
test_vfwadd_wv_f32m8_tu(vfloat32m8_t maskedoff,vfloat32m8_t op1,vfloat16m4_t op2,size_t vl)196 vfloat32m8_t test_vfwadd_wv_f32m8_tu(vfloat32m8_t maskedoff, vfloat32m8_t op1, vfloat16m4_t op2, size_t vl) {
197 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, vl);
198 }
199
200 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_wf_f32m8_tu
201 // CHECK-RV64-SAME: (<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
202 // CHECK-RV64-NEXT: entry:
203 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f32.f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], half [[OP2]], i64 7, i64 [[VL]])
204 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
205 //
test_vfwadd_wf_f32m8_tu(vfloat32m8_t maskedoff,vfloat32m8_t op1,_Float16 op2,size_t vl)206 vfloat32m8_t test_vfwadd_wf_f32m8_tu(vfloat32m8_t maskedoff, vfloat32m8_t op1, _Float16 op2, size_t vl) {
207 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, vl);
208 }
209
210 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_vv_f64m1_tu
211 // CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
212 // CHECK-RV64-NEXT: entry:
213 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x float> [[OP2]], i64 7, i64 [[VL]])
214 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
215 //
test_vfwadd_vv_f64m1_tu(vfloat64m1_t maskedoff,vfloat32mf2_t op1,vfloat32mf2_t op2,size_t vl)216 vfloat64m1_t test_vfwadd_vv_f64m1_tu(vfloat64m1_t maskedoff, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
217 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, vl);
218 }
219
220 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_vf_f64m1_tu
221 // CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
222 // CHECK-RV64-NEXT: entry:
223 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f64.nxv1f32.f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], float [[OP2]], i64 7, i64 [[VL]])
224 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
225 //
test_vfwadd_vf_f64m1_tu(vfloat64m1_t maskedoff,vfloat32mf2_t op1,float op2,size_t vl)226 vfloat64m1_t test_vfwadd_vf_f64m1_tu(vfloat64m1_t maskedoff, vfloat32mf2_t op1, float op2, size_t vl) {
227 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, vl);
228 }
229
230 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_wv_f64m1_tu
231 // CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
232 // CHECK-RV64-NEXT: entry:
233 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], <vscale x 1 x float> [[OP2]], i64 7, i64 [[VL]])
234 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
235 //
test_vfwadd_wv_f64m1_tu(vfloat64m1_t maskedoff,vfloat64m1_t op1,vfloat32mf2_t op2,size_t vl)236 vfloat64m1_t test_vfwadd_wv_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m1_t op1, vfloat32mf2_t op2, size_t vl) {
237 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, vl);
238 }
239
240 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_wf_f64m1_tu
241 // CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
242 // CHECK-RV64-NEXT: entry:
243 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.nxv1f64.f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], float [[OP2]], i64 7, i64 [[VL]])
244 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
245 //
test_vfwadd_wf_f64m1_tu(vfloat64m1_t maskedoff,vfloat64m1_t op1,float op2,size_t vl)246 vfloat64m1_t test_vfwadd_wf_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m1_t op1, float op2, size_t vl) {
247 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, vl);
248 }
249
250 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_vv_f64m2_tu
251 // CHECK-RV64-SAME: (<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
252 // CHECK-RV64-NEXT: entry:
253 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x float> [[OP2]], i64 7, i64 [[VL]])
254 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
255 //
test_vfwadd_vv_f64m2_tu(vfloat64m2_t maskedoff,vfloat32m1_t op1,vfloat32m1_t op2,size_t vl)256 vfloat64m2_t test_vfwadd_vv_f64m2_tu(vfloat64m2_t maskedoff, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
257 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, vl);
258 }
259
260 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_vf_f64m2_tu
261 // CHECK-RV64-SAME: (<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
262 // CHECK-RV64-NEXT: entry:
263 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.nxv2f64.nxv2f32.f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], float [[OP2]], i64 7, i64 [[VL]])
264 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
265 //
test_vfwadd_vf_f64m2_tu(vfloat64m2_t maskedoff,vfloat32m1_t op1,float op2,size_t vl)266 vfloat64m2_t test_vfwadd_vf_f64m2_tu(vfloat64m2_t maskedoff, vfloat32m1_t op1, float op2, size_t vl) {
267 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, vl);
268 }
269
270 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_wv_f64m2_tu
271 // CHECK-RV64-SAME: (<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
272 // CHECK-RV64-NEXT: entry:
273 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.nxv2f64.nxv2f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], <vscale x 2 x float> [[OP2]], i64 7, i64 [[VL]])
274 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
275 //
test_vfwadd_wv_f64m2_tu(vfloat64m2_t maskedoff,vfloat64m2_t op1,vfloat32m1_t op2,size_t vl)276 vfloat64m2_t test_vfwadd_wv_f64m2_tu(vfloat64m2_t maskedoff, vfloat64m2_t op1, vfloat32m1_t op2, size_t vl) {
277 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, vl);
278 }
279
280 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_wf_f64m2_tu
281 // CHECK-RV64-SAME: (<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
282 // CHECK-RV64-NEXT: entry:
283 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.nxv2f64.f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], float [[OP2]], i64 7, i64 [[VL]])
284 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
285 //
test_vfwadd_wf_f64m2_tu(vfloat64m2_t maskedoff,vfloat64m2_t op1,float op2,size_t vl)286 vfloat64m2_t test_vfwadd_wf_f64m2_tu(vfloat64m2_t maskedoff, vfloat64m2_t op1, float op2, size_t vl) {
287 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, vl);
288 }
289
290 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_vv_f64m4_tu
291 // CHECK-RV64-SAME: (<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
292 // CHECK-RV64-NEXT: entry:
293 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x float> [[OP2]], i64 7, i64 [[VL]])
294 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
295 //
test_vfwadd_vv_f64m4_tu(vfloat64m4_t maskedoff,vfloat32m2_t op1,vfloat32m2_t op2,size_t vl)296 vfloat64m4_t test_vfwadd_vv_f64m4_tu(vfloat64m4_t maskedoff, vfloat32m2_t op1, vfloat32m2_t op2, size_t vl) {
297 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, vl);
298 }
299
300 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_vf_f64m4_tu
301 // CHECK-RV64-SAME: (<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
302 // CHECK-RV64-NEXT: entry:
303 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.nxv4f64.nxv4f32.f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], float [[OP2]], i64 7, i64 [[VL]])
304 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
305 //
test_vfwadd_vf_f64m4_tu(vfloat64m4_t maskedoff,vfloat32m2_t op1,float op2,size_t vl)306 vfloat64m4_t test_vfwadd_vf_f64m4_tu(vfloat64m4_t maskedoff, vfloat32m2_t op1, float op2, size_t vl) {
307 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, vl);
308 }
309
310 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_wv_f64m4_tu
311 // CHECK-RV64-SAME: (<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
312 // CHECK-RV64-NEXT: entry:
313 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f64.nxv4f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], <vscale x 4 x float> [[OP2]], i64 7, i64 [[VL]])
314 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
315 //
test_vfwadd_wv_f64m4_tu(vfloat64m4_t maskedoff,vfloat64m4_t op1,vfloat32m2_t op2,size_t vl)316 vfloat64m4_t test_vfwadd_wv_f64m4_tu(vfloat64m4_t maskedoff, vfloat64m4_t op1, vfloat32m2_t op2, size_t vl) {
317 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, vl);
318 }
319
320 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_wf_f64m4_tu
321 // CHECK-RV64-SAME: (<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
322 // CHECK-RV64-NEXT: entry:
323 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f64.f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], float [[OP2]], i64 7, i64 [[VL]])
324 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
325 //
test_vfwadd_wf_f64m4_tu(vfloat64m4_t maskedoff,vfloat64m4_t op1,float op2,size_t vl)326 vfloat64m4_t test_vfwadd_wf_f64m4_tu(vfloat64m4_t maskedoff, vfloat64m4_t op1, float op2, size_t vl) {
327 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, vl);
328 }
329
330 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_vv_f64m8_tu
331 // CHECK-RV64-SAME: (<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
332 // CHECK-RV64-NEXT: entry:
333 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x float> [[OP2]], i64 7, i64 [[VL]])
334 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
335 //
test_vfwadd_vv_f64m8_tu(vfloat64m8_t maskedoff,vfloat32m4_t op1,vfloat32m4_t op2,size_t vl)336 vfloat64m8_t test_vfwadd_vv_f64m8_tu(vfloat64m8_t maskedoff, vfloat32m4_t op1, vfloat32m4_t op2, size_t vl) {
337 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, vl);
338 }
339
340 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_vf_f64m8_tu
341 // CHECK-RV64-SAME: (<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
342 // CHECK-RV64-NEXT: entry:
343 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.nxv8f64.nxv8f32.f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], float [[OP2]], i64 7, i64 [[VL]])
344 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
345 //
test_vfwadd_vf_f64m8_tu(vfloat64m8_t maskedoff,vfloat32m4_t op1,float op2,size_t vl)346 vfloat64m8_t test_vfwadd_vf_f64m8_tu(vfloat64m8_t maskedoff, vfloat32m4_t op1, float op2, size_t vl) {
347 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, vl);
348 }
349
350 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_wv_f64m8_tu
351 // CHECK-RV64-SAME: (<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
352 // CHECK-RV64-NEXT: entry:
353 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.nxv8f64.nxv8f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], <vscale x 8 x float> [[OP2]], i64 7, i64 [[VL]])
354 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
355 //
test_vfwadd_wv_f64m8_tu(vfloat64m8_t maskedoff,vfloat64m8_t op1,vfloat32m4_t op2,size_t vl)356 vfloat64m8_t test_vfwadd_wv_f64m8_tu(vfloat64m8_t maskedoff, vfloat64m8_t op1, vfloat32m4_t op2, size_t vl) {
357 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, vl);
358 }
359
360 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_wf_f64m8_tu
361 // CHECK-RV64-SAME: (<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
362 // CHECK-RV64-NEXT: entry:
363 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.nxv8f64.f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], float [[OP2]], i64 7, i64 [[VL]])
364 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
365 //
test_vfwadd_wf_f64m8_tu(vfloat64m8_t maskedoff,vfloat64m8_t op1,float op2,size_t vl)366 vfloat64m8_t test_vfwadd_wf_f64m8_tu(vfloat64m8_t maskedoff, vfloat64m8_t op1, float op2, size_t vl) {
367 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, vl);
368 }
369
370 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_tum
371 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
372 // CHECK-RV64-NEXT: entry:
373 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], <vscale x 1 x half> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
374 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
375 //
test_vfwadd_vv_f32mf2_tum(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat16mf4_t op1,vfloat16mf4_t op2,size_t vl)376 vfloat32mf2_t test_vfwadd_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
377 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, vl);
378 }
379
380 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_tum
381 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
382 // CHECK-RV64-NEXT: entry:
383 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], half [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
384 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
385 //
test_vfwadd_vf_f32mf2_tum(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat16mf4_t op1,_Float16 op2,size_t vl)386 vfloat32mf2_t test_vfwadd_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat16mf4_t op1, _Float16 op2, size_t vl) {
387 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, vl);
388 }
389
390 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_tum
391 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
392 // CHECK-RV64-NEXT: entry:
393 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x half> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
394 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
395 //
test_vfwadd_wv_f32mf2_tum(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,vfloat16mf4_t op2,size_t vl)396 vfloat32mf2_t test_vfwadd_wv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, vfloat16mf4_t op2, size_t vl) {
397 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, vl);
398 }
399
400 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_tum
401 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
402 // CHECK-RV64-NEXT: entry:
403 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], half [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
404 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
405 //
test_vfwadd_wf_f32mf2_tum(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,_Float16 op2,size_t vl)406 vfloat32mf2_t test_vfwadd_wf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, _Float16 op2, size_t vl) {
407 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, vl);
408 }
409
410 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_tum
411 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
412 // CHECK-RV64-NEXT: entry:
413 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], <vscale x 2 x half> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
414 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
415 //
test_vfwadd_vv_f32m1_tum(vbool32_t mask,vfloat32m1_t maskedoff,vfloat16mf2_t op1,vfloat16mf2_t op2,size_t vl)416 vfloat32m1_t test_vfwadd_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
417 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, vl);
418 }
419
420 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_tum
421 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
422 // CHECK-RV64-NEXT: entry:
423 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], half [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
424 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
425 //
test_vfwadd_vf_f32m1_tum(vbool32_t mask,vfloat32m1_t maskedoff,vfloat16mf2_t op1,_Float16 op2,size_t vl)426 vfloat32m1_t test_vfwadd_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
427 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, vl);
428 }
429
430 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_tum
431 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
432 // CHECK-RV64-NEXT: entry:
433 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x half> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
434 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
435 //
test_vfwadd_wv_f32m1_tum(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,vfloat16mf2_t op2,size_t vl)436 vfloat32m1_t test_vfwadd_wv_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
437 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, vl);
438 }
439
440 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_tum
441 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
442 // CHECK-RV64-NEXT: entry:
443 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], half [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
444 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
445 //
test_vfwadd_wf_f32m1_tum(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,_Float16 op2,size_t vl)446 vfloat32m1_t test_vfwadd_wf_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, _Float16 op2, size_t vl) {
447 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, vl);
448 }
449
450 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2_tum
451 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
452 // CHECK-RV64-NEXT: entry:
453 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], <vscale x 4 x half> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
454 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
455 //
test_vfwadd_vv_f32m2_tum(vbool16_t mask,vfloat32m2_t maskedoff,vfloat16m1_t op1,vfloat16m1_t op2,size_t vl)456 vfloat32m2_t test_vfwadd_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t maskedoff, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
457 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, vl);
458 }
459
460 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2_tum
461 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
462 // CHECK-RV64-NEXT: entry:
463 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], half [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
464 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
465 //
test_vfwadd_vf_f32m2_tum(vbool16_t mask,vfloat32m2_t maskedoff,vfloat16m1_t op1,_Float16 op2,size_t vl)466 vfloat32m2_t test_vfwadd_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t maskedoff, vfloat16m1_t op1, _Float16 op2, size_t vl) {
467 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, vl);
468 }
469
470 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_wv_f32m2_tum
471 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
472 // CHECK-RV64-NEXT: entry:
473 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.nxv4f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x half> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
474 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
475 //
test_vfwadd_wv_f32m2_tum(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,vfloat16m1_t op2,size_t vl)476 vfloat32m2_t test_vfwadd_wv_f32m2_tum(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, vfloat16m1_t op2, size_t vl) {
477 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, vl);
478 }
479
480 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_wf_f32m2_tum
481 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
482 // CHECK-RV64-NEXT: entry:
483 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], half [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
484 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
485 //
test_vfwadd_wf_f32m2_tum(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,_Float16 op2,size_t vl)486 vfloat32m2_t test_vfwadd_wf_f32m2_tum(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, _Float16 op2, size_t vl) {
487 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, vl);
488 }
489
490 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_vv_f32m4_tum
491 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
492 // CHECK-RV64-NEXT: entry:
493 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], <vscale x 8 x half> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
494 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
495 //
test_vfwadd_vv_f32m4_tum(vbool8_t mask,vfloat32m4_t maskedoff,vfloat16m2_t op1,vfloat16m2_t op2,size_t vl)496 vfloat32m4_t test_vfwadd_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t maskedoff, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
497 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, vl);
498 }
499
500 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_vf_f32m4_tum
501 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
502 // CHECK-RV64-NEXT: entry:
503 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], half [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
504 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
505 //
test_vfwadd_vf_f32m4_tum(vbool8_t mask,vfloat32m4_t maskedoff,vfloat16m2_t op1,_Float16 op2,size_t vl)506 vfloat32m4_t test_vfwadd_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t maskedoff, vfloat16m2_t op1, _Float16 op2, size_t vl) {
507 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, vl);
508 }
509
510 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_wv_f32m4_tum
511 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
512 // CHECK-RV64-NEXT: entry:
513 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.nxv8f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x half> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
514 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
515 //
test_vfwadd_wv_f32m4_tum(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,vfloat16m2_t op2,size_t vl)516 vfloat32m4_t test_vfwadd_wv_f32m4_tum(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, vfloat16m2_t op2, size_t vl) {
517 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, vl);
518 }
519
520 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_wf_f32m4_tum
521 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
522 // CHECK-RV64-NEXT: entry:
523 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], half [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
524 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
525 //
test_vfwadd_wf_f32m4_tum(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,_Float16 op2,size_t vl)526 vfloat32m4_t test_vfwadd_wf_f32m4_tum(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, _Float16 op2, size_t vl) {
527 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, vl);
528 }
529
530 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_vv_f32m8_tum
531 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
532 // CHECK-RV64-NEXT: entry:
533 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], <vscale x 16 x half> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
534 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
535 //
test_vfwadd_vv_f32m8_tum(vbool4_t mask,vfloat32m8_t maskedoff,vfloat16m4_t op1,vfloat16m4_t op2,size_t vl)536 vfloat32m8_t test_vfwadd_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t maskedoff, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
537 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, vl);
538 }
539
540 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_vf_f32m8_tum
541 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
542 // CHECK-RV64-NEXT: entry:
543 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], half [[OP2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
544 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
545 //
test_vfwadd_vf_f32m8_tum(vbool4_t mask,vfloat32m8_t maskedoff,vfloat16m4_t op1,_Float16 op2,size_t vl)546 vfloat32m8_t test_vfwadd_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t maskedoff, vfloat16m4_t op1, _Float16 op2, size_t vl) {
547 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, vl);
548 }
549
550 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_wv_f32m8_tum
551 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
552 // CHECK-RV64-NEXT: entry:
553 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], <vscale x 16 x half> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
554 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
555 //
test_vfwadd_wv_f32m8_tum(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,vfloat16m4_t op2,size_t vl)556 vfloat32m8_t test_vfwadd_wv_f32m8_tum(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, vfloat16m4_t op2, size_t vl) {
557 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, vl);
558 }
559
560 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_wf_f32m8_tum
561 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
562 // CHECK-RV64-NEXT: entry:
563 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], half [[OP2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
564 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
565 //
test_vfwadd_wf_f32m8_tum(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,_Float16 op2,size_t vl)566 vfloat32m8_t test_vfwadd_wf_f32m8_tum(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, _Float16 op2, size_t vl) {
567 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, vl);
568 }
569
570 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_vv_f64m1_tum
571 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
572 // CHECK-RV64-NEXT: entry:
573 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x float> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
574 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
575 //
test_vfwadd_vv_f64m1_tum(vbool64_t mask,vfloat64m1_t maskedoff,vfloat32mf2_t op1,vfloat32mf2_t op2,size_t vl)576 vfloat64m1_t test_vfwadd_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
577 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, vl);
578 }
579
580 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_vf_f64m1_tum
581 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
582 // CHECK-RV64-NEXT: entry:
583 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], float [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
584 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
585 //
test_vfwadd_vf_f64m1_tum(vbool64_t mask,vfloat64m1_t maskedoff,vfloat32mf2_t op1,float op2,size_t vl)586 vfloat64m1_t test_vfwadd_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t op1, float op2, size_t vl) {
587 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, vl);
588 }
589
590 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_wv_f64m1_tum
591 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
592 // CHECK-RV64-NEXT: entry:
593 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], <vscale x 1 x float> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
594 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
595 //
test_vfwadd_wv_f64m1_tum(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,vfloat32mf2_t op2,size_t vl)596 vfloat64m1_t test_vfwadd_wv_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, vfloat32mf2_t op2, size_t vl) {
597 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, vl);
598 }
599
600 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_wf_f64m1_tum
601 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
602 // CHECK-RV64-NEXT: entry:
603 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.mask.nxv1f64.f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], float [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
604 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
605 //
test_vfwadd_wf_f64m1_tum(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,float op2,size_t vl)606 vfloat64m1_t test_vfwadd_wf_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, float op2, size_t vl) {
607 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, vl);
608 }
609
610 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_vv_f64m2_tum
611 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
612 // CHECK-RV64-NEXT: entry:
613 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x float> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
614 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
615 //
test_vfwadd_vv_f64m2_tum(vbool32_t mask,vfloat64m2_t maskedoff,vfloat32m1_t op1,vfloat32m1_t op2,size_t vl)616 vfloat64m2_t test_vfwadd_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t maskedoff, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
617 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, vl);
618 }
619
620 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_vf_f64m2_tum
621 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
622 // CHECK-RV64-NEXT: entry:
623 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], float [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
624 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
625 //
test_vfwadd_vf_f64m2_tum(vbool32_t mask,vfloat64m2_t maskedoff,vfloat32m1_t op1,float op2,size_t vl)626 vfloat64m2_t test_vfwadd_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t maskedoff, vfloat32m1_t op1, float op2, size_t vl) {
627 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, vl);
628 }
629
630 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_wv_f64m2_tum
631 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
632 // CHECK-RV64-NEXT: entry:
633 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.mask.nxv2f64.nxv2f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], <vscale x 2 x float> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
634 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
635 //
test_vfwadd_wv_f64m2_tum(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,vfloat32m1_t op2,size_t vl)636 vfloat64m2_t test_vfwadd_wv_f64m2_tum(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, vfloat32m1_t op2, size_t vl) {
637 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, vl);
638 }
639
640 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_wf_f64m2_tum
641 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
642 // CHECK-RV64-NEXT: entry:
643 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.mask.nxv2f64.f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], float [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
644 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
645 //
test_vfwadd_wf_f64m2_tum(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,float op2,size_t vl)646 vfloat64m2_t test_vfwadd_wf_f64m2_tum(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, float op2, size_t vl) {
647 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, vl);
648 }
649
650 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_vv_f64m4_tum
651 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
652 // CHECK-RV64-NEXT: entry:
653 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x float> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
654 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
655 //
test_vfwadd_vv_f64m4_tum(vbool16_t mask,vfloat64m4_t maskedoff,vfloat32m2_t op1,vfloat32m2_t op2,size_t vl)656 vfloat64m4_t test_vfwadd_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t maskedoff, vfloat32m2_t op1, vfloat32m2_t op2, size_t vl) {
657 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, vl);
658 }
659
660 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_vf_f64m4_tum
661 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
662 // CHECK-RV64-NEXT: entry:
663 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], float [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
664 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
665 //
test_vfwadd_vf_f64m4_tum(vbool16_t mask,vfloat64m4_t maskedoff,vfloat32m2_t op1,float op2,size_t vl)666 vfloat64m4_t test_vfwadd_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t maskedoff, vfloat32m2_t op1, float op2, size_t vl) {
667 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, vl);
668 }
669
670 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_wv_f64m4_tum
671 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
672 // CHECK-RV64-NEXT: entry:
673 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.mask.nxv4f64.nxv4f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], <vscale x 4 x float> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
674 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
675 //
test_vfwadd_wv_f64m4_tum(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,vfloat32m2_t op2,size_t vl)676 vfloat64m4_t test_vfwadd_wv_f64m4_tum(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, vfloat32m2_t op2, size_t vl) {
677 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, vl);
678 }
679
680 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_wf_f64m4_tum
681 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
682 // CHECK-RV64-NEXT: entry:
683 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.mask.nxv4f64.f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], float [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
684 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
685 //
test_vfwadd_wf_f64m4_tum(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,float op2,size_t vl)686 vfloat64m4_t test_vfwadd_wf_f64m4_tum(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, float op2, size_t vl) {
687 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, vl);
688 }
689
690 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_vv_f64m8_tum
691 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
692 // CHECK-RV64-NEXT: entry:
693 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x float> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
694 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
695 //
test_vfwadd_vv_f64m8_tum(vbool8_t mask,vfloat64m8_t maskedoff,vfloat32m4_t op1,vfloat32m4_t op2,size_t vl)696 vfloat64m8_t test_vfwadd_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t maskedoff, vfloat32m4_t op1, vfloat32m4_t op2, size_t vl) {
697 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, vl);
698 }
699
700 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_vf_f64m8_tum
701 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
702 // CHECK-RV64-NEXT: entry:
703 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], float [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
704 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
705 //
test_vfwadd_vf_f64m8_tum(vbool8_t mask,vfloat64m8_t maskedoff,vfloat32m4_t op1,float op2,size_t vl)706 vfloat64m8_t test_vfwadd_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t maskedoff, vfloat32m4_t op1, float op2, size_t vl) {
707 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, vl);
708 }
709
710 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_wv_f64m8_tum
711 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
712 // CHECK-RV64-NEXT: entry:
713 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], <vscale x 8 x float> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
714 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
715 //
test_vfwadd_wv_f64m8_tum(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,vfloat32m4_t op2,size_t vl)716 vfloat64m8_t test_vfwadd_wv_f64m8_tum(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, vfloat32m4_t op2, size_t vl) {
717 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, vl);
718 }
719
720 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_wf_f64m8_tum
721 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
722 // CHECK-RV64-NEXT: entry:
723 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], float [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
724 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
725 //
test_vfwadd_wf_f64m8_tum(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,float op2,size_t vl)726 vfloat64m8_t test_vfwadd_wf_f64m8_tum(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, float op2, size_t vl) {
727 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, vl);
728 }
729
730 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_tumu
731 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
732 // CHECK-RV64-NEXT: entry:
733 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], <vscale x 1 x half> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
734 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
735 //
test_vfwadd_vv_f32mf2_tumu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat16mf4_t op1,vfloat16mf4_t op2,size_t vl)736 vfloat32mf2_t test_vfwadd_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
737 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, vl);
738 }
739
740 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_tumu
741 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
742 // CHECK-RV64-NEXT: entry:
743 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], half [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
744 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
745 //
test_vfwadd_vf_f32mf2_tumu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat16mf4_t op1,_Float16 op2,size_t vl)746 vfloat32mf2_t test_vfwadd_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat16mf4_t op1, _Float16 op2, size_t vl) {
747 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, vl);
748 }
749
750 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_tumu
751 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
752 // CHECK-RV64-NEXT: entry:
753 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x half> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
754 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
755 //
test_vfwadd_wv_f32mf2_tumu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,vfloat16mf4_t op2,size_t vl)756 vfloat32mf2_t test_vfwadd_wv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, vfloat16mf4_t op2, size_t vl) {
757 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, vl);
758 }
759
760 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_tumu
761 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
762 // CHECK-RV64-NEXT: entry:
763 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], half [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
764 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
765 //
test_vfwadd_wf_f32mf2_tumu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,_Float16 op2,size_t vl)766 vfloat32mf2_t test_vfwadd_wf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, _Float16 op2, size_t vl) {
767 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, vl);
768 }
769
770 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_tumu
771 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
772 // CHECK-RV64-NEXT: entry:
773 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], <vscale x 2 x half> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
774 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
775 //
test_vfwadd_vv_f32m1_tumu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat16mf2_t op1,vfloat16mf2_t op2,size_t vl)776 vfloat32m1_t test_vfwadd_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
777 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, vl);
778 }
779
780 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_tumu
781 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
782 // CHECK-RV64-NEXT: entry:
783 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], half [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
784 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
785 //
test_vfwadd_vf_f32m1_tumu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat16mf2_t op1,_Float16 op2,size_t vl)786 vfloat32m1_t test_vfwadd_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
787 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, vl);
788 }
789
790 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_tumu
791 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
792 // CHECK-RV64-NEXT: entry:
793 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x half> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
794 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
795 //
test_vfwadd_wv_f32m1_tumu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,vfloat16mf2_t op2,size_t vl)796 vfloat32m1_t test_vfwadd_wv_f32m1_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
797 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, vl);
798 }
799
800 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_tumu
801 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
802 // CHECK-RV64-NEXT: entry:
803 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], half [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
804 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
805 //
test_vfwadd_wf_f32m1_tumu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,_Float16 op2,size_t vl)806 vfloat32m1_t test_vfwadd_wf_f32m1_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, _Float16 op2, size_t vl) {
807 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, vl);
808 }
809
810 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2_tumu
811 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
812 // CHECK-RV64-NEXT: entry:
813 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], <vscale x 4 x half> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
814 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
815 //
test_vfwadd_vv_f32m2_tumu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat16m1_t op1,vfloat16m1_t op2,size_t vl)816 vfloat32m2_t test_vfwadd_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
817 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, vl);
818 }
819
820 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2_tumu
821 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
822 // CHECK-RV64-NEXT: entry:
823 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], half [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
824 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
825 //
test_vfwadd_vf_f32m2_tumu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat16m1_t op1,_Float16 op2,size_t vl)826 vfloat32m2_t test_vfwadd_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat16m1_t op1, _Float16 op2, size_t vl) {
827 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, vl);
828 }
829
830 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_wv_f32m2_tumu
831 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
832 // CHECK-RV64-NEXT: entry:
833 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.nxv4f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x half> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
834 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
835 //
test_vfwadd_wv_f32m2_tumu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,vfloat16m1_t op2,size_t vl)836 vfloat32m2_t test_vfwadd_wv_f32m2_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, vfloat16m1_t op2, size_t vl) {
837 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, vl);
838 }
839
840 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_wf_f32m2_tumu
841 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
842 // CHECK-RV64-NEXT: entry:
843 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], half [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
844 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
845 //
test_vfwadd_wf_f32m2_tumu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,_Float16 op2,size_t vl)846 vfloat32m2_t test_vfwadd_wf_f32m2_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, _Float16 op2, size_t vl) {
847 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, vl);
848 }
849
850 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_vv_f32m4_tumu
851 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
852 // CHECK-RV64-NEXT: entry:
853 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], <vscale x 8 x half> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
854 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
855 //
test_vfwadd_vv_f32m4_tumu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat16m2_t op1,vfloat16m2_t op2,size_t vl)856 vfloat32m4_t test_vfwadd_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
857 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, vl);
858 }
859
860 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_vf_f32m4_tumu
861 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
862 // CHECK-RV64-NEXT: entry:
863 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], half [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
864 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
865 //
test_vfwadd_vf_f32m4_tumu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat16m2_t op1,_Float16 op2,size_t vl)866 vfloat32m4_t test_vfwadd_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat16m2_t op1, _Float16 op2, size_t vl) {
867 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, vl);
868 }
869
870 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_wv_f32m4_tumu
871 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
872 // CHECK-RV64-NEXT: entry:
873 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.nxv8f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x half> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
874 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
875 //
test_vfwadd_wv_f32m4_tumu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,vfloat16m2_t op2,size_t vl)876 vfloat32m4_t test_vfwadd_wv_f32m4_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, vfloat16m2_t op2, size_t vl) {
877 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, vl);
878 }
879
880 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_wf_f32m4_tumu
881 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
882 // CHECK-RV64-NEXT: entry:
883 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], half [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
884 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
885 //
test_vfwadd_wf_f32m4_tumu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,_Float16 op2,size_t vl)886 vfloat32m4_t test_vfwadd_wf_f32m4_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, _Float16 op2, size_t vl) {
887 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, vl);
888 }
889
890 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_vv_f32m8_tumu
891 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
892 // CHECK-RV64-NEXT: entry:
893 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], <vscale x 16 x half> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
894 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
895 //
test_vfwadd_vv_f32m8_tumu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat16m4_t op1,vfloat16m4_t op2,size_t vl)896 vfloat32m8_t test_vfwadd_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
897 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, vl);
898 }
899
900 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_vf_f32m8_tumu
901 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
902 // CHECK-RV64-NEXT: entry:
903 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], half [[OP2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
904 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
905 //
test_vfwadd_vf_f32m8_tumu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat16m4_t op1,_Float16 op2,size_t vl)906 vfloat32m8_t test_vfwadd_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat16m4_t op1, _Float16 op2, size_t vl) {
907 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, vl);
908 }
909
910 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_wv_f32m8_tumu
911 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
912 // CHECK-RV64-NEXT: entry:
913 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], <vscale x 16 x half> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
914 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
915 //
test_vfwadd_wv_f32m8_tumu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,vfloat16m4_t op2,size_t vl)916 vfloat32m8_t test_vfwadd_wv_f32m8_tumu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, vfloat16m4_t op2, size_t vl) {
917 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, vl);
918 }
919
920 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_wf_f32m8_tumu
921 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
922 // CHECK-RV64-NEXT: entry:
923 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], half [[OP2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
924 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
925 //
test_vfwadd_wf_f32m8_tumu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,_Float16 op2,size_t vl)926 vfloat32m8_t test_vfwadd_wf_f32m8_tumu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, _Float16 op2, size_t vl) {
927 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, vl);
928 }
929
930 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_vv_f64m1_tumu
931 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
932 // CHECK-RV64-NEXT: entry:
933 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x float> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
934 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
935 //
test_vfwadd_vv_f64m1_tumu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat32mf2_t op1,vfloat32mf2_t op2,size_t vl)936 vfloat64m1_t test_vfwadd_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
937 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, vl);
938 }
939
940 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_vf_f64m1_tumu
941 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
942 // CHECK-RV64-NEXT: entry:
943 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], float [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
944 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
945 //
test_vfwadd_vf_f64m1_tumu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat32mf2_t op1,float op2,size_t vl)946 vfloat64m1_t test_vfwadd_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t op1, float op2, size_t vl) {
947 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, vl);
948 }
949
950 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_wv_f64m1_tumu
951 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
952 // CHECK-RV64-NEXT: entry:
953 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], <vscale x 1 x float> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
954 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
955 //
test_vfwadd_wv_f64m1_tumu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,vfloat32mf2_t op2,size_t vl)956 vfloat64m1_t test_vfwadd_wv_f64m1_tumu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, vfloat32mf2_t op2, size_t vl) {
957 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, vl);
958 }
959
960 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_wf_f64m1_tumu
961 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
962 // CHECK-RV64-NEXT: entry:
963 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.mask.nxv1f64.f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], float [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
964 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
965 //
test_vfwadd_wf_f64m1_tumu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,float op2,size_t vl)966 vfloat64m1_t test_vfwadd_wf_f64m1_tumu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, float op2, size_t vl) {
967 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, vl);
968 }
969
970 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_vv_f64m2_tumu
971 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
972 // CHECK-RV64-NEXT: entry:
973 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x float> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
974 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
975 //
test_vfwadd_vv_f64m2_tumu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat32m1_t op1,vfloat32m1_t op2,size_t vl)976 vfloat64m2_t test_vfwadd_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
977 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, vl);
978 }
979
980 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_vf_f64m2_tumu
981 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
982 // CHECK-RV64-NEXT: entry:
983 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], float [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
984 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
985 //
test_vfwadd_vf_f64m2_tumu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat32m1_t op1,float op2,size_t vl)986 vfloat64m2_t test_vfwadd_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat32m1_t op1, float op2, size_t vl) {
987 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, vl);
988 }
989
990 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_wv_f64m2_tumu
991 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
992 // CHECK-RV64-NEXT: entry:
993 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.mask.nxv2f64.nxv2f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], <vscale x 2 x float> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
994 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
995 //
test_vfwadd_wv_f64m2_tumu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,vfloat32m1_t op2,size_t vl)996 vfloat64m2_t test_vfwadd_wv_f64m2_tumu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, vfloat32m1_t op2, size_t vl) {
997 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, vl);
998 }
999
1000 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_wf_f64m2_tumu
1001 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1002 // CHECK-RV64-NEXT: entry:
1003 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.mask.nxv2f64.f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], float [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1004 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
1005 //
test_vfwadd_wf_f64m2_tumu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,float op2,size_t vl)1006 vfloat64m2_t test_vfwadd_wf_f64m2_tumu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, float op2, size_t vl) {
1007 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, vl);
1008 }
1009
1010 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_vv_f64m4_tumu
1011 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1012 // CHECK-RV64-NEXT: entry:
1013 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x float> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1014 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1015 //
test_vfwadd_vv_f64m4_tumu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat32m2_t op1,vfloat32m2_t op2,size_t vl)1016 vfloat64m4_t test_vfwadd_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat32m2_t op1, vfloat32m2_t op2, size_t vl) {
1017 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, vl);
1018 }
1019
1020 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_vf_f64m4_tumu
1021 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1022 // CHECK-RV64-NEXT: entry:
1023 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], float [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1024 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1025 //
test_vfwadd_vf_f64m4_tumu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat32m2_t op1,float op2,size_t vl)1026 vfloat64m4_t test_vfwadd_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat32m2_t op1, float op2, size_t vl) {
1027 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, vl);
1028 }
1029
1030 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_wv_f64m4_tumu
1031 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1032 // CHECK-RV64-NEXT: entry:
1033 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.mask.nxv4f64.nxv4f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], <vscale x 4 x float> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1034 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1035 //
test_vfwadd_wv_f64m4_tumu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,vfloat32m2_t op2,size_t vl)1036 vfloat64m4_t test_vfwadd_wv_f64m4_tumu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, vfloat32m2_t op2, size_t vl) {
1037 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, vl);
1038 }
1039
1040 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_wf_f64m4_tumu
1041 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1042 // CHECK-RV64-NEXT: entry:
1043 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.mask.nxv4f64.f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], float [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1044 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1045 //
test_vfwadd_wf_f64m4_tumu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,float op2,size_t vl)1046 vfloat64m4_t test_vfwadd_wf_f64m4_tumu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, float op2, size_t vl) {
1047 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, vl);
1048 }
1049
1050 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_vv_f64m8_tumu
1051 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1052 // CHECK-RV64-NEXT: entry:
1053 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x float> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1054 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1055 //
test_vfwadd_vv_f64m8_tumu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat32m4_t op1,vfloat32m4_t op2,size_t vl)1056 vfloat64m8_t test_vfwadd_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat32m4_t op1, vfloat32m4_t op2, size_t vl) {
1057 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, vl);
1058 }
1059
1060 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_vf_f64m8_tumu
1061 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1062 // CHECK-RV64-NEXT: entry:
1063 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], float [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1064 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1065 //
test_vfwadd_vf_f64m8_tumu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat32m4_t op1,float op2,size_t vl)1066 vfloat64m8_t test_vfwadd_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat32m4_t op1, float op2, size_t vl) {
1067 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, vl);
1068 }
1069
1070 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_wv_f64m8_tumu
1071 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1072 // CHECK-RV64-NEXT: entry:
1073 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], <vscale x 8 x float> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1074 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1075 //
test_vfwadd_wv_f64m8_tumu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,vfloat32m4_t op2,size_t vl)1076 vfloat64m8_t test_vfwadd_wv_f64m8_tumu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, vfloat32m4_t op2, size_t vl) {
1077 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, vl);
1078 }
1079
1080 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_wf_f64m8_tumu
1081 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1082 // CHECK-RV64-NEXT: entry:
1083 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], float [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1084 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1085 //
test_vfwadd_wf_f64m8_tumu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,float op2,size_t vl)1086 vfloat64m8_t test_vfwadd_wf_f64m8_tumu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, float op2, size_t vl) {
1087 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, vl);
1088 }
1089
1090 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_mu
1091 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1092 // CHECK-RV64-NEXT: entry:
1093 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], <vscale x 1 x half> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1094 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
1095 //
test_vfwadd_vv_f32mf2_mu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat16mf4_t op1,vfloat16mf4_t op2,size_t vl)1096 vfloat32mf2_t test_vfwadd_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
1097 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, vl);
1098 }
1099
1100 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_mu
1101 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1102 // CHECK-RV64-NEXT: entry:
1103 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], half [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1104 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
1105 //
test_vfwadd_vf_f32mf2_mu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat16mf4_t op1,_Float16 op2,size_t vl)1106 vfloat32mf2_t test_vfwadd_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat16mf4_t op1, _Float16 op2, size_t vl) {
1107 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, vl);
1108 }
1109
1110 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_mu
1111 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1112 // CHECK-RV64-NEXT: entry:
1113 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x half> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1114 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
1115 //
test_vfwadd_wv_f32mf2_mu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,vfloat16mf4_t op2,size_t vl)1116 vfloat32mf2_t test_vfwadd_wv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, vfloat16mf4_t op2, size_t vl) {
1117 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, vl);
1118 }
1119
1120 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_mu
1121 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1122 // CHECK-RV64-NEXT: entry:
1123 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], half [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1124 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
1125 //
test_vfwadd_wf_f32mf2_mu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,_Float16 op2,size_t vl)1126 vfloat32mf2_t test_vfwadd_wf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, _Float16 op2, size_t vl) {
1127 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, vl);
1128 }
1129
1130 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_mu
1131 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1132 // CHECK-RV64-NEXT: entry:
1133 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], <vscale x 2 x half> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1134 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
1135 //
test_vfwadd_vv_f32m1_mu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat16mf2_t op1,vfloat16mf2_t op2,size_t vl)1136 vfloat32m1_t test_vfwadd_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
1137 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, vl);
1138 }
1139
1140 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_mu
1141 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1142 // CHECK-RV64-NEXT: entry:
1143 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], half [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1144 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
1145 //
test_vfwadd_vf_f32m1_mu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat16mf2_t op1,_Float16 op2,size_t vl)1146 vfloat32m1_t test_vfwadd_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
1147 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, vl);
1148 }
1149
1150 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_mu
1151 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1152 // CHECK-RV64-NEXT: entry:
1153 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x half> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1154 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
1155 //
test_vfwadd_wv_f32m1_mu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,vfloat16mf2_t op2,size_t vl)1156 vfloat32m1_t test_vfwadd_wv_f32m1_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
1157 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, vl);
1158 }
1159
1160 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_mu
1161 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1162 // CHECK-RV64-NEXT: entry:
1163 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], half [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1164 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
1165 //
test_vfwadd_wf_f32m1_mu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,_Float16 op2,size_t vl)1166 vfloat32m1_t test_vfwadd_wf_f32m1_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, _Float16 op2, size_t vl) {
1167 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, vl);
1168 }
1169
1170 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2_mu
1171 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1172 // CHECK-RV64-NEXT: entry:
1173 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], <vscale x 4 x half> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1174 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
1175 //
test_vfwadd_vv_f32m2_mu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat16m1_t op1,vfloat16m1_t op2,size_t vl)1176 vfloat32m2_t test_vfwadd_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
1177 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, vl);
1178 }
1179
1180 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2_mu
1181 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1182 // CHECK-RV64-NEXT: entry:
1183 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], half [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1184 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
1185 //
test_vfwadd_vf_f32m2_mu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat16m1_t op1,_Float16 op2,size_t vl)1186 vfloat32m2_t test_vfwadd_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat16m1_t op1, _Float16 op2, size_t vl) {
1187 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, vl);
1188 }
1189
1190 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_wv_f32m2_mu
1191 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1192 // CHECK-RV64-NEXT: entry:
1193 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.nxv4f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x half> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1194 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
1195 //
test_vfwadd_wv_f32m2_mu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,vfloat16m1_t op2,size_t vl)1196 vfloat32m2_t test_vfwadd_wv_f32m2_mu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, vfloat16m1_t op2, size_t vl) {
1197 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, vl);
1198 }
1199
1200 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_wf_f32m2_mu
1201 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1202 // CHECK-RV64-NEXT: entry:
1203 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], half [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1204 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
1205 //
test_vfwadd_wf_f32m2_mu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,_Float16 op2,size_t vl)1206 vfloat32m2_t test_vfwadd_wf_f32m2_mu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, _Float16 op2, size_t vl) {
1207 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, vl);
1208 }
1209
1210 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_vv_f32m4_mu
1211 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1212 // CHECK-RV64-NEXT: entry:
1213 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], <vscale x 8 x half> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1214 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
1215 //
test_vfwadd_vv_f32m4_mu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat16m2_t op1,vfloat16m2_t op2,size_t vl)1216 vfloat32m4_t test_vfwadd_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
1217 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, vl);
1218 }
1219
1220 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_vf_f32m4_mu
1221 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1222 // CHECK-RV64-NEXT: entry:
1223 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], half [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1224 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
1225 //
test_vfwadd_vf_f32m4_mu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat16m2_t op1,_Float16 op2,size_t vl)1226 vfloat32m4_t test_vfwadd_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat16m2_t op1, _Float16 op2, size_t vl) {
1227 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, vl);
1228 }
1229
1230 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_wv_f32m4_mu
1231 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1232 // CHECK-RV64-NEXT: entry:
1233 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.nxv8f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x half> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1234 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
1235 //
test_vfwadd_wv_f32m4_mu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,vfloat16m2_t op2,size_t vl)1236 vfloat32m4_t test_vfwadd_wv_f32m4_mu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, vfloat16m2_t op2, size_t vl) {
1237 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, vl);
1238 }
1239
1240 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_wf_f32m4_mu
1241 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1242 // CHECK-RV64-NEXT: entry:
1243 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], half [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1244 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
1245 //
test_vfwadd_wf_f32m4_mu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,_Float16 op2,size_t vl)1246 vfloat32m4_t test_vfwadd_wf_f32m4_mu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, _Float16 op2, size_t vl) {
1247 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, vl);
1248 }
1249
1250 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_vv_f32m8_mu
1251 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1252 // CHECK-RV64-NEXT: entry:
1253 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], <vscale x 16 x half> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1254 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
1255 //
test_vfwadd_vv_f32m8_mu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat16m4_t op1,vfloat16m4_t op2,size_t vl)1256 vfloat32m8_t test_vfwadd_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
1257 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, vl);
1258 }
1259
1260 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_vf_f32m8_mu
1261 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1262 // CHECK-RV64-NEXT: entry:
1263 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], half [[OP2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1264 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
1265 //
test_vfwadd_vf_f32m8_mu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat16m4_t op1,_Float16 op2,size_t vl)1266 vfloat32m8_t test_vfwadd_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat16m4_t op1, _Float16 op2, size_t vl) {
1267 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, vl);
1268 }
1269
1270 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_wv_f32m8_mu
1271 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1272 // CHECK-RV64-NEXT: entry:
1273 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], <vscale x 16 x half> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1274 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
1275 //
test_vfwadd_wv_f32m8_mu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,vfloat16m4_t op2,size_t vl)1276 vfloat32m8_t test_vfwadd_wv_f32m8_mu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, vfloat16m4_t op2, size_t vl) {
1277 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, vl);
1278 }
1279
1280 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_wf_f32m8_mu
1281 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1282 // CHECK-RV64-NEXT: entry:
1283 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], half [[OP2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1284 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
1285 //
test_vfwadd_wf_f32m8_mu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,_Float16 op2,size_t vl)1286 vfloat32m8_t test_vfwadd_wf_f32m8_mu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, _Float16 op2, size_t vl) {
1287 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, vl);
1288 }
1289
1290 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_vv_f64m1_mu
1291 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1292 // CHECK-RV64-NEXT: entry:
1293 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x float> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1294 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
1295 //
test_vfwadd_vv_f64m1_mu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat32mf2_t op1,vfloat32mf2_t op2,size_t vl)1296 vfloat64m1_t test_vfwadd_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
1297 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, vl);
1298 }
1299
1300 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_vf_f64m1_mu
1301 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1302 // CHECK-RV64-NEXT: entry:
1303 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], float [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1304 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
1305 //
test_vfwadd_vf_f64m1_mu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat32mf2_t op1,float op2,size_t vl)1306 vfloat64m1_t test_vfwadd_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t op1, float op2, size_t vl) {
1307 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, vl);
1308 }
1309
1310 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_wv_f64m1_mu
1311 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1312 // CHECK-RV64-NEXT: entry:
1313 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], <vscale x 1 x float> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1314 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
1315 //
test_vfwadd_wv_f64m1_mu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,vfloat32mf2_t op2,size_t vl)1316 vfloat64m1_t test_vfwadd_wv_f64m1_mu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, vfloat32mf2_t op2, size_t vl) {
1317 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, vl);
1318 }
1319
1320 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_wf_f64m1_mu
1321 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1322 // CHECK-RV64-NEXT: entry:
1323 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.mask.nxv1f64.f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], float [[OP2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1324 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
1325 //
test_vfwadd_wf_f64m1_mu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,float op2,size_t vl)1326 vfloat64m1_t test_vfwadd_wf_f64m1_mu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, float op2, size_t vl) {
1327 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, vl);
1328 }
1329
1330 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_vv_f64m2_mu
1331 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1332 // CHECK-RV64-NEXT: entry:
1333 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x float> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1334 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
1335 //
test_vfwadd_vv_f64m2_mu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat32m1_t op1,vfloat32m1_t op2,size_t vl)1336 vfloat64m2_t test_vfwadd_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
1337 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, vl);
1338 }
1339
1340 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_vf_f64m2_mu
1341 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1342 // CHECK-RV64-NEXT: entry:
1343 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], float [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1344 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
1345 //
test_vfwadd_vf_f64m2_mu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat32m1_t op1,float op2,size_t vl)1346 vfloat64m2_t test_vfwadd_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat32m1_t op1, float op2, size_t vl) {
1347 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, vl);
1348 }
1349
1350 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_wv_f64m2_mu
1351 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1352 // CHECK-RV64-NEXT: entry:
1353 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.mask.nxv2f64.nxv2f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], <vscale x 2 x float> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1354 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
1355 //
test_vfwadd_wv_f64m2_mu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,vfloat32m1_t op2,size_t vl)1356 vfloat64m2_t test_vfwadd_wv_f64m2_mu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, vfloat32m1_t op2, size_t vl) {
1357 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, vl);
1358 }
1359
1360 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_wf_f64m2_mu
1361 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1362 // CHECK-RV64-NEXT: entry:
1363 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.mask.nxv2f64.f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], float [[OP2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1364 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
1365 //
test_vfwadd_wf_f64m2_mu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,float op2,size_t vl)1366 vfloat64m2_t test_vfwadd_wf_f64m2_mu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, float op2, size_t vl) {
1367 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, vl);
1368 }
1369
1370 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_vv_f64m4_mu
1371 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1372 // CHECK-RV64-NEXT: entry:
1373 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x float> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1374 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1375 //
test_vfwadd_vv_f64m4_mu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat32m2_t op1,vfloat32m2_t op2,size_t vl)1376 vfloat64m4_t test_vfwadd_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat32m2_t op1, vfloat32m2_t op2, size_t vl) {
1377 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, vl);
1378 }
1379
1380 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_vf_f64m4_mu
1381 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1382 // CHECK-RV64-NEXT: entry:
1383 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], float [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1384 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1385 //
test_vfwadd_vf_f64m4_mu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat32m2_t op1,float op2,size_t vl)1386 vfloat64m4_t test_vfwadd_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat32m2_t op1, float op2, size_t vl) {
1387 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, vl);
1388 }
1389
1390 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_wv_f64m4_mu
1391 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1392 // CHECK-RV64-NEXT: entry:
1393 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.mask.nxv4f64.nxv4f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], <vscale x 4 x float> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1394 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1395 //
test_vfwadd_wv_f64m4_mu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,vfloat32m2_t op2,size_t vl)1396 vfloat64m4_t test_vfwadd_wv_f64m4_mu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, vfloat32m2_t op2, size_t vl) {
1397 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, vl);
1398 }
1399
1400 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_wf_f64m4_mu
1401 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1402 // CHECK-RV64-NEXT: entry:
1403 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.mask.nxv4f64.f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], float [[OP2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1404 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1405 //
test_vfwadd_wf_f64m4_mu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,float op2,size_t vl)1406 vfloat64m4_t test_vfwadd_wf_f64m4_mu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, float op2, size_t vl) {
1407 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, vl);
1408 }
1409
1410 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_vv_f64m8_mu
1411 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1412 // CHECK-RV64-NEXT: entry:
1413 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x float> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1414 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1415 //
test_vfwadd_vv_f64m8_mu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat32m4_t op1,vfloat32m4_t op2,size_t vl)1416 vfloat64m8_t test_vfwadd_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat32m4_t op1, vfloat32m4_t op2, size_t vl) {
1417 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, vl);
1418 }
1419
1420 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_vf_f64m8_mu
1421 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1422 // CHECK-RV64-NEXT: entry:
1423 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], float [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1424 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1425 //
test_vfwadd_vf_f64m8_mu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat32m4_t op1,float op2,size_t vl)1426 vfloat64m8_t test_vfwadd_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat32m4_t op1, float op2, size_t vl) {
1427 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, vl);
1428 }
1429
1430 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_wv_f64m8_mu
1431 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1432 // CHECK-RV64-NEXT: entry:
1433 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], <vscale x 8 x float> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1434 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1435 //
test_vfwadd_wv_f64m8_mu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,vfloat32m4_t op2,size_t vl)1436 vfloat64m8_t test_vfwadd_wv_f64m8_mu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, vfloat32m4_t op2, size_t vl) {
1437 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, vl);
1438 }
1439
1440 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_wf_f64m8_mu
1441 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1442 // CHECK-RV64-NEXT: entry:
1443 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], float [[OP2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1444 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1445 //
test_vfwadd_wf_f64m8_mu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,float op2,size_t vl)1446 vfloat64m8_t test_vfwadd_wf_f64m8_mu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, float op2, size_t vl) {
1447 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, vl);
1448 }
1449
1450 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_rm_tu
1451 // CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1452 // CHECK-RV64-NEXT: entry:
1453 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], <vscale x 1 x half> [[OP2]], i64 0, i64 [[VL]])
1454 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
1455 //
test_vfwadd_vv_f32mf2_rm_tu(vfloat32mf2_t maskedoff,vfloat16mf4_t op1,vfloat16mf4_t op2,size_t vl)1456 vfloat32mf2_t test_vfwadd_vv_f32mf2_rm_tu(vfloat32mf2_t maskedoff, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
1457 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1458 }
1459
1460 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_rm_tu
1461 // CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1462 // CHECK-RV64-NEXT: entry:
1463 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], half [[OP2]], i64 0, i64 [[VL]])
1464 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
1465 //
test_vfwadd_vf_f32mf2_rm_tu(vfloat32mf2_t maskedoff,vfloat16mf4_t op1,_Float16 op2,size_t vl)1466 vfloat32mf2_t test_vfwadd_vf_f32mf2_rm_tu(vfloat32mf2_t maskedoff, vfloat16mf4_t op1, _Float16 op2, size_t vl) {
1467 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1468 }
1469
1470 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_rm_tu
1471 // CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1472 // CHECK-RV64-NEXT: entry:
1473 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x half> [[OP2]], i64 0, i64 [[VL]])
1474 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
1475 //
test_vfwadd_wv_f32mf2_rm_tu(vfloat32mf2_t maskedoff,vfloat32mf2_t op1,vfloat16mf4_t op2,size_t vl)1476 vfloat32mf2_t test_vfwadd_wv_f32mf2_rm_tu(vfloat32mf2_t maskedoff, vfloat32mf2_t op1, vfloat16mf4_t op2, size_t vl) {
1477 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1478 }
1479
1480 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_rm_tu
1481 // CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1482 // CHECK-RV64-NEXT: entry:
1483 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], half [[OP2]], i64 0, i64 [[VL]])
1484 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
1485 //
test_vfwadd_wf_f32mf2_rm_tu(vfloat32mf2_t maskedoff,vfloat32mf2_t op1,_Float16 op2,size_t vl)1486 vfloat32mf2_t test_vfwadd_wf_f32mf2_rm_tu(vfloat32mf2_t maskedoff, vfloat32mf2_t op1, _Float16 op2, size_t vl) {
1487 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1488 }
1489
1490 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_rm_tu
1491 // CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1492 // CHECK-RV64-NEXT: entry:
1493 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], <vscale x 2 x half> [[OP2]], i64 0, i64 [[VL]])
1494 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
1495 //
test_vfwadd_vv_f32m1_rm_tu(vfloat32m1_t maskedoff,vfloat16mf2_t op1,vfloat16mf2_t op2,size_t vl)1496 vfloat32m1_t test_vfwadd_vv_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
1497 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1498 }
1499
1500 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_rm_tu
1501 // CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1502 // CHECK-RV64-NEXT: entry:
1503 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], half [[OP2]], i64 0, i64 [[VL]])
1504 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
1505 //
test_vfwadd_vf_f32m1_rm_tu(vfloat32m1_t maskedoff,vfloat16mf2_t op1,_Float16 op2,size_t vl)1506 vfloat32m1_t test_vfwadd_vf_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
1507 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1508 }
1509
1510 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_rm_tu
1511 // CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1512 // CHECK-RV64-NEXT: entry:
1513 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x half> [[OP2]], i64 0, i64 [[VL]])
1514 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
1515 //
test_vfwadd_wv_f32m1_rm_tu(vfloat32m1_t maskedoff,vfloat32m1_t op1,vfloat16mf2_t op2,size_t vl)1516 vfloat32m1_t test_vfwadd_wv_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
1517 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1518 }
1519
1520 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_rm_tu
1521 // CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1522 // CHECK-RV64-NEXT: entry:
1523 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], half [[OP2]], i64 0, i64 [[VL]])
1524 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
1525 //
test_vfwadd_wf_f32m1_rm_tu(vfloat32m1_t maskedoff,vfloat32m1_t op1,_Float16 op2,size_t vl)1526 vfloat32m1_t test_vfwadd_wf_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m1_t op1, _Float16 op2, size_t vl) {
1527 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1528 }
1529
1530 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2_rm_tu
1531 // CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1532 // CHECK-RV64-NEXT: entry:
1533 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], <vscale x 4 x half> [[OP2]], i64 0, i64 [[VL]])
1534 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
1535 //
test_vfwadd_vv_f32m2_rm_tu(vfloat32m2_t maskedoff,vfloat16m1_t op1,vfloat16m1_t op2,size_t vl)1536 vfloat32m2_t test_vfwadd_vv_f32m2_rm_tu(vfloat32m2_t maskedoff, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
1537 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1538 }
1539
1540 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2_rm_tu
1541 // CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1542 // CHECK-RV64-NEXT: entry:
1543 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], half [[OP2]], i64 0, i64 [[VL]])
1544 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
1545 //
test_vfwadd_vf_f32m2_rm_tu(vfloat32m2_t maskedoff,vfloat16m1_t op1,_Float16 op2,size_t vl)1546 vfloat32m2_t test_vfwadd_vf_f32m2_rm_tu(vfloat32m2_t maskedoff, vfloat16m1_t op1, _Float16 op2, size_t vl) {
1547 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1548 }
1549
1550 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_wv_f32m2_rm_tu
1551 // CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1552 // CHECK-RV64-NEXT: entry:
1553 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.nxv4f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x half> [[OP2]], i64 0, i64 [[VL]])
1554 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
1555 //
test_vfwadd_wv_f32m2_rm_tu(vfloat32m2_t maskedoff,vfloat32m2_t op1,vfloat16m1_t op2,size_t vl)1556 vfloat32m2_t test_vfwadd_wv_f32m2_rm_tu(vfloat32m2_t maskedoff, vfloat32m2_t op1, vfloat16m1_t op2, size_t vl) {
1557 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1558 }
1559
1560 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_wf_f32m2_rm_tu
1561 // CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1562 // CHECK-RV64-NEXT: entry:
1563 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], half [[OP2]], i64 0, i64 [[VL]])
1564 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
1565 //
test_vfwadd_wf_f32m2_rm_tu(vfloat32m2_t maskedoff,vfloat32m2_t op1,_Float16 op2,size_t vl)1566 vfloat32m2_t test_vfwadd_wf_f32m2_rm_tu(vfloat32m2_t maskedoff, vfloat32m2_t op1, _Float16 op2, size_t vl) {
1567 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1568 }
1569
1570 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_vv_f32m4_rm_tu
1571 // CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1572 // CHECK-RV64-NEXT: entry:
1573 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], <vscale x 8 x half> [[OP2]], i64 0, i64 [[VL]])
1574 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
1575 //
test_vfwadd_vv_f32m4_rm_tu(vfloat32m4_t maskedoff,vfloat16m2_t op1,vfloat16m2_t op2,size_t vl)1576 vfloat32m4_t test_vfwadd_vv_f32m4_rm_tu(vfloat32m4_t maskedoff, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
1577 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1578 }
1579
1580 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_vf_f32m4_rm_tu
1581 // CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1582 // CHECK-RV64-NEXT: entry:
1583 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], half [[OP2]], i64 0, i64 [[VL]])
1584 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
1585 //
test_vfwadd_vf_f32m4_rm_tu(vfloat32m4_t maskedoff,vfloat16m2_t op1,_Float16 op2,size_t vl)1586 vfloat32m4_t test_vfwadd_vf_f32m4_rm_tu(vfloat32m4_t maskedoff, vfloat16m2_t op1, _Float16 op2, size_t vl) {
1587 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1588 }
1589
1590 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_wv_f32m4_rm_tu
1591 // CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1592 // CHECK-RV64-NEXT: entry:
1593 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.nxv8f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x half> [[OP2]], i64 0, i64 [[VL]])
1594 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
1595 //
test_vfwadd_wv_f32m4_rm_tu(vfloat32m4_t maskedoff,vfloat32m4_t op1,vfloat16m2_t op2,size_t vl)1596 vfloat32m4_t test_vfwadd_wv_f32m4_rm_tu(vfloat32m4_t maskedoff, vfloat32m4_t op1, vfloat16m2_t op2, size_t vl) {
1597 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1598 }
1599
1600 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_wf_f32m4_rm_tu
1601 // CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1602 // CHECK-RV64-NEXT: entry:
1603 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], half [[OP2]], i64 0, i64 [[VL]])
1604 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
1605 //
test_vfwadd_wf_f32m4_rm_tu(vfloat32m4_t maskedoff,vfloat32m4_t op1,_Float16 op2,size_t vl)1606 vfloat32m4_t test_vfwadd_wf_f32m4_rm_tu(vfloat32m4_t maskedoff, vfloat32m4_t op1, _Float16 op2, size_t vl) {
1607 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1608 }
1609
1610 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_vv_f32m8_rm_tu
1611 // CHECK-RV64-SAME: (<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1612 // CHECK-RV64-NEXT: entry:
1613 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], <vscale x 16 x half> [[OP2]], i64 0, i64 [[VL]])
1614 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
1615 //
test_vfwadd_vv_f32m8_rm_tu(vfloat32m8_t maskedoff,vfloat16m4_t op1,vfloat16m4_t op2,size_t vl)1616 vfloat32m8_t test_vfwadd_vv_f32m8_rm_tu(vfloat32m8_t maskedoff, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
1617 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1618 }
1619
1620 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_vf_f32m8_rm_tu
1621 // CHECK-RV64-SAME: (<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1622 // CHECK-RV64-NEXT: entry:
1623 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.nxv16f32.nxv16f16.f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], half [[OP2]], i64 0, i64 [[VL]])
1624 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
1625 //
test_vfwadd_vf_f32m8_rm_tu(vfloat32m8_t maskedoff,vfloat16m4_t op1,_Float16 op2,size_t vl)1626 vfloat32m8_t test_vfwadd_vf_f32m8_rm_tu(vfloat32m8_t maskedoff, vfloat16m4_t op1, _Float16 op2, size_t vl) {
1627 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1628 }
1629
1630 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_wv_f32m8_rm_tu
1631 // CHECK-RV64-SAME: (<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1632 // CHECK-RV64-NEXT: entry:
1633 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f32.nxv16f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], <vscale x 16 x half> [[OP2]], i64 0, i64 [[VL]])
1634 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
1635 //
test_vfwadd_wv_f32m8_rm_tu(vfloat32m8_t maskedoff,vfloat32m8_t op1,vfloat16m4_t op2,size_t vl)1636 vfloat32m8_t test_vfwadd_wv_f32m8_rm_tu(vfloat32m8_t maskedoff, vfloat32m8_t op1, vfloat16m4_t op2, size_t vl) {
1637 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1638 }
1639
1640 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_wf_f32m8_rm_tu
1641 // CHECK-RV64-SAME: (<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1642 // CHECK-RV64-NEXT: entry:
1643 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f32.f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], half [[OP2]], i64 0, i64 [[VL]])
1644 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
1645 //
test_vfwadd_wf_f32m8_rm_tu(vfloat32m8_t maskedoff,vfloat32m8_t op1,_Float16 op2,size_t vl)1646 vfloat32m8_t test_vfwadd_wf_f32m8_rm_tu(vfloat32m8_t maskedoff, vfloat32m8_t op1, _Float16 op2, size_t vl) {
1647 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1648 }
1649
1650 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_vv_f64m1_rm_tu
1651 // CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1652 // CHECK-RV64-NEXT: entry:
1653 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x float> [[OP2]], i64 0, i64 [[VL]])
1654 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
1655 //
test_vfwadd_vv_f64m1_rm_tu(vfloat64m1_t maskedoff,vfloat32mf2_t op1,vfloat32mf2_t op2,size_t vl)1656 vfloat64m1_t test_vfwadd_vv_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
1657 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1658 }
1659
1660 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_vf_f64m1_rm_tu
1661 // CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1662 // CHECK-RV64-NEXT: entry:
1663 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f64.nxv1f32.f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], float [[OP2]], i64 0, i64 [[VL]])
1664 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
1665 //
test_vfwadd_vf_f64m1_rm_tu(vfloat64m1_t maskedoff,vfloat32mf2_t op1,float op2,size_t vl)1666 vfloat64m1_t test_vfwadd_vf_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32mf2_t op1, float op2, size_t vl) {
1667 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1668 }
1669
1670 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_wv_f64m1_rm_tu
1671 // CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1672 // CHECK-RV64-NEXT: entry:
1673 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], <vscale x 1 x float> [[OP2]], i64 0, i64 [[VL]])
1674 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
1675 //
test_vfwadd_wv_f64m1_rm_tu(vfloat64m1_t maskedoff,vfloat64m1_t op1,vfloat32mf2_t op2,size_t vl)1676 vfloat64m1_t test_vfwadd_wv_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m1_t op1, vfloat32mf2_t op2, size_t vl) {
1677 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1678 }
1679
1680 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_wf_f64m1_rm_tu
1681 // CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1682 // CHECK-RV64-NEXT: entry:
1683 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.nxv1f64.f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], float [[OP2]], i64 0, i64 [[VL]])
1684 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
1685 //
test_vfwadd_wf_f64m1_rm_tu(vfloat64m1_t maskedoff,vfloat64m1_t op1,float op2,size_t vl)1686 vfloat64m1_t test_vfwadd_wf_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m1_t op1, float op2, size_t vl) {
1687 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1688 }
1689
1690 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_vv_f64m2_rm_tu
1691 // CHECK-RV64-SAME: (<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1692 // CHECK-RV64-NEXT: entry:
1693 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x float> [[OP2]], i64 0, i64 [[VL]])
1694 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
1695 //
test_vfwadd_vv_f64m2_rm_tu(vfloat64m2_t maskedoff,vfloat32m1_t op1,vfloat32m1_t op2,size_t vl)1696 vfloat64m2_t test_vfwadd_vv_f64m2_rm_tu(vfloat64m2_t maskedoff, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
1697 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1698 }
1699
1700 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_vf_f64m2_rm_tu
1701 // CHECK-RV64-SAME: (<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1702 // CHECK-RV64-NEXT: entry:
1703 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.nxv2f64.nxv2f32.f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], float [[OP2]], i64 0, i64 [[VL]])
1704 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
1705 //
test_vfwadd_vf_f64m2_rm_tu(vfloat64m2_t maskedoff,vfloat32m1_t op1,float op2,size_t vl)1706 vfloat64m2_t test_vfwadd_vf_f64m2_rm_tu(vfloat64m2_t maskedoff, vfloat32m1_t op1, float op2, size_t vl) {
1707 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1708 }
1709
1710 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_wv_f64m2_rm_tu
1711 // CHECK-RV64-SAME: (<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1712 // CHECK-RV64-NEXT: entry:
1713 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.nxv2f64.nxv2f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], <vscale x 2 x float> [[OP2]], i64 0, i64 [[VL]])
1714 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
1715 //
test_vfwadd_wv_f64m2_rm_tu(vfloat64m2_t maskedoff,vfloat64m2_t op1,vfloat32m1_t op2,size_t vl)1716 vfloat64m2_t test_vfwadd_wv_f64m2_rm_tu(vfloat64m2_t maskedoff, vfloat64m2_t op1, vfloat32m1_t op2, size_t vl) {
1717 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1718 }
1719
1720 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_wf_f64m2_rm_tu
1721 // CHECK-RV64-SAME: (<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1722 // CHECK-RV64-NEXT: entry:
1723 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.nxv2f64.f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], float [[OP2]], i64 0, i64 [[VL]])
1724 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
1725 //
test_vfwadd_wf_f64m2_rm_tu(vfloat64m2_t maskedoff,vfloat64m2_t op1,float op2,size_t vl)1726 vfloat64m2_t test_vfwadd_wf_f64m2_rm_tu(vfloat64m2_t maskedoff, vfloat64m2_t op1, float op2, size_t vl) {
1727 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1728 }
1729
1730 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_vv_f64m4_rm_tu
1731 // CHECK-RV64-SAME: (<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1732 // CHECK-RV64-NEXT: entry:
1733 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x float> [[OP2]], i64 0, i64 [[VL]])
1734 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1735 //
test_vfwadd_vv_f64m4_rm_tu(vfloat64m4_t maskedoff,vfloat32m2_t op1,vfloat32m2_t op2,size_t vl)1736 vfloat64m4_t test_vfwadd_vv_f64m4_rm_tu(vfloat64m4_t maskedoff, vfloat32m2_t op1, vfloat32m2_t op2, size_t vl) {
1737 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1738 }
1739
1740 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_vf_f64m4_rm_tu
1741 // CHECK-RV64-SAME: (<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1742 // CHECK-RV64-NEXT: entry:
1743 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.nxv4f64.nxv4f32.f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], float [[OP2]], i64 0, i64 [[VL]])
1744 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1745 //
test_vfwadd_vf_f64m4_rm_tu(vfloat64m4_t maskedoff,vfloat32m2_t op1,float op2,size_t vl)1746 vfloat64m4_t test_vfwadd_vf_f64m4_rm_tu(vfloat64m4_t maskedoff, vfloat32m2_t op1, float op2, size_t vl) {
1747 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1748 }
1749
1750 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_wv_f64m4_rm_tu
1751 // CHECK-RV64-SAME: (<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1752 // CHECK-RV64-NEXT: entry:
1753 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f64.nxv4f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], <vscale x 4 x float> [[OP2]], i64 0, i64 [[VL]])
1754 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1755 //
test_vfwadd_wv_f64m4_rm_tu(vfloat64m4_t maskedoff,vfloat64m4_t op1,vfloat32m2_t op2,size_t vl)1756 vfloat64m4_t test_vfwadd_wv_f64m4_rm_tu(vfloat64m4_t maskedoff, vfloat64m4_t op1, vfloat32m2_t op2, size_t vl) {
1757 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1758 }
1759
1760 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_wf_f64m4_rm_tu
1761 // CHECK-RV64-SAME: (<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1762 // CHECK-RV64-NEXT: entry:
1763 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f64.f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], float [[OP2]], i64 0, i64 [[VL]])
1764 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1765 //
test_vfwadd_wf_f64m4_rm_tu(vfloat64m4_t maskedoff,vfloat64m4_t op1,float op2,size_t vl)1766 vfloat64m4_t test_vfwadd_wf_f64m4_rm_tu(vfloat64m4_t maskedoff, vfloat64m4_t op1, float op2, size_t vl) {
1767 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1768 }
1769
1770 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_vv_f64m8_rm_tu
1771 // CHECK-RV64-SAME: (<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1772 // CHECK-RV64-NEXT: entry:
1773 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x float> [[OP2]], i64 0, i64 [[VL]])
1774 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1775 //
test_vfwadd_vv_f64m8_rm_tu(vfloat64m8_t maskedoff,vfloat32m4_t op1,vfloat32m4_t op2,size_t vl)1776 vfloat64m8_t test_vfwadd_vv_f64m8_rm_tu(vfloat64m8_t maskedoff, vfloat32m4_t op1, vfloat32m4_t op2, size_t vl) {
1777 return __riscv_vfwadd_vv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1778 }
1779
1780 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_vf_f64m8_rm_tu
1781 // CHECK-RV64-SAME: (<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1782 // CHECK-RV64-NEXT: entry:
1783 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.nxv8f64.nxv8f32.f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], float [[OP2]], i64 0, i64 [[VL]])
1784 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1785 //
test_vfwadd_vf_f64m8_rm_tu(vfloat64m8_t maskedoff,vfloat32m4_t op1,float op2,size_t vl)1786 vfloat64m8_t test_vfwadd_vf_f64m8_rm_tu(vfloat64m8_t maskedoff, vfloat32m4_t op1, float op2, size_t vl) {
1787 return __riscv_vfwadd_vf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1788 }
1789
1790 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_wv_f64m8_rm_tu
1791 // CHECK-RV64-SAME: (<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1792 // CHECK-RV64-NEXT: entry:
1793 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.nxv8f64.nxv8f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], <vscale x 8 x float> [[OP2]], i64 0, i64 [[VL]])
1794 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1795 //
test_vfwadd_wv_f64m8_rm_tu(vfloat64m8_t maskedoff,vfloat64m8_t op1,vfloat32m4_t op2,size_t vl)1796 vfloat64m8_t test_vfwadd_wv_f64m8_rm_tu(vfloat64m8_t maskedoff, vfloat64m8_t op1, vfloat32m4_t op2, size_t vl) {
1797 return __riscv_vfwadd_wv_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1798 }
1799
1800 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_wf_f64m8_rm_tu
1801 // CHECK-RV64-SAME: (<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1802 // CHECK-RV64-NEXT: entry:
1803 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.nxv8f64.f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], float [[OP2]], i64 0, i64 [[VL]])
1804 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1805 //
test_vfwadd_wf_f64m8_rm_tu(vfloat64m8_t maskedoff,vfloat64m8_t op1,float op2,size_t vl)1806 vfloat64m8_t test_vfwadd_wf_f64m8_rm_tu(vfloat64m8_t maskedoff, vfloat64m8_t op1, float op2, size_t vl) {
1807 return __riscv_vfwadd_wf_tu(maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1808 }
1809
1810 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_rm_tum
1811 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1812 // CHECK-RV64-NEXT: entry:
1813 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], <vscale x 1 x half> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1814 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
1815 //
test_vfwadd_vv_f32mf2_rm_tum(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat16mf4_t op1,vfloat16mf4_t op2,size_t vl)1816 vfloat32mf2_t test_vfwadd_vv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
1817 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1818 }
1819
1820 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_rm_tum
1821 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1822 // CHECK-RV64-NEXT: entry:
1823 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], half [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1824 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
1825 //
test_vfwadd_vf_f32mf2_rm_tum(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat16mf4_t op1,_Float16 op2,size_t vl)1826 vfloat32mf2_t test_vfwadd_vf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat16mf4_t op1, _Float16 op2, size_t vl) {
1827 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1828 }
1829
1830 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_rm_tum
1831 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1832 // CHECK-RV64-NEXT: entry:
1833 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x half> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1834 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
1835 //
test_vfwadd_wv_f32mf2_rm_tum(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,vfloat16mf4_t op2,size_t vl)1836 vfloat32mf2_t test_vfwadd_wv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, vfloat16mf4_t op2, size_t vl) {
1837 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1838 }
1839
1840 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_rm_tum
1841 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1842 // CHECK-RV64-NEXT: entry:
1843 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], half [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1844 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
1845 //
test_vfwadd_wf_f32mf2_rm_tum(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,_Float16 op2,size_t vl)1846 vfloat32mf2_t test_vfwadd_wf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, _Float16 op2, size_t vl) {
1847 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1848 }
1849
1850 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_rm_tum
1851 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1852 // CHECK-RV64-NEXT: entry:
1853 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], <vscale x 2 x half> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1854 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
1855 //
test_vfwadd_vv_f32m1_rm_tum(vbool32_t mask,vfloat32m1_t maskedoff,vfloat16mf2_t op1,vfloat16mf2_t op2,size_t vl)1856 vfloat32m1_t test_vfwadd_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
1857 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1858 }
1859
1860 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_rm_tum
1861 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1862 // CHECK-RV64-NEXT: entry:
1863 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], half [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1864 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
1865 //
test_vfwadd_vf_f32m1_rm_tum(vbool32_t mask,vfloat32m1_t maskedoff,vfloat16mf2_t op1,_Float16 op2,size_t vl)1866 vfloat32m1_t test_vfwadd_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
1867 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1868 }
1869
1870 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_rm_tum
1871 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1872 // CHECK-RV64-NEXT: entry:
1873 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x half> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1874 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
1875 //
test_vfwadd_wv_f32m1_rm_tum(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,vfloat16mf2_t op2,size_t vl)1876 vfloat32m1_t test_vfwadd_wv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
1877 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1878 }
1879
1880 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_rm_tum
1881 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1882 // CHECK-RV64-NEXT: entry:
1883 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], half [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1884 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
1885 //
test_vfwadd_wf_f32m1_rm_tum(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,_Float16 op2,size_t vl)1886 vfloat32m1_t test_vfwadd_wf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, _Float16 op2, size_t vl) {
1887 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1888 }
1889
1890 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2_rm_tum
1891 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1892 // CHECK-RV64-NEXT: entry:
1893 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], <vscale x 4 x half> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1894 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
1895 //
test_vfwadd_vv_f32m2_rm_tum(vbool16_t mask,vfloat32m2_t maskedoff,vfloat16m1_t op1,vfloat16m1_t op2,size_t vl)1896 vfloat32m2_t test_vfwadd_vv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t maskedoff, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
1897 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1898 }
1899
1900 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2_rm_tum
1901 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1902 // CHECK-RV64-NEXT: entry:
1903 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], half [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1904 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
1905 //
test_vfwadd_vf_f32m2_rm_tum(vbool16_t mask,vfloat32m2_t maskedoff,vfloat16m1_t op1,_Float16 op2,size_t vl)1906 vfloat32m2_t test_vfwadd_vf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t maskedoff, vfloat16m1_t op1, _Float16 op2, size_t vl) {
1907 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1908 }
1909
1910 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_wv_f32m2_rm_tum
1911 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1912 // CHECK-RV64-NEXT: entry:
1913 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.nxv4f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x half> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1914 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
1915 //
test_vfwadd_wv_f32m2_rm_tum(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,vfloat16m1_t op2,size_t vl)1916 vfloat32m2_t test_vfwadd_wv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, vfloat16m1_t op2, size_t vl) {
1917 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1918 }
1919
1920 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_wf_f32m2_rm_tum
1921 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1922 // CHECK-RV64-NEXT: entry:
1923 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], half [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1924 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
1925 //
test_vfwadd_wf_f32m2_rm_tum(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,_Float16 op2,size_t vl)1926 vfloat32m2_t test_vfwadd_wf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, _Float16 op2, size_t vl) {
1927 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1928 }
1929
1930 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_vv_f32m4_rm_tum
1931 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1932 // CHECK-RV64-NEXT: entry:
1933 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], <vscale x 8 x half> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1934 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
1935 //
test_vfwadd_vv_f32m4_rm_tum(vbool8_t mask,vfloat32m4_t maskedoff,vfloat16m2_t op1,vfloat16m2_t op2,size_t vl)1936 vfloat32m4_t test_vfwadd_vv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t maskedoff, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
1937 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1938 }
1939
1940 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_vf_f32m4_rm_tum
1941 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1942 // CHECK-RV64-NEXT: entry:
1943 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], half [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1944 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
1945 //
test_vfwadd_vf_f32m4_rm_tum(vbool8_t mask,vfloat32m4_t maskedoff,vfloat16m2_t op1,_Float16 op2,size_t vl)1946 vfloat32m4_t test_vfwadd_vf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t maskedoff, vfloat16m2_t op1, _Float16 op2, size_t vl) {
1947 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1948 }
1949
1950 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_wv_f32m4_rm_tum
1951 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1952 // CHECK-RV64-NEXT: entry:
1953 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.nxv8f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x half> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1954 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
1955 //
test_vfwadd_wv_f32m4_rm_tum(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,vfloat16m2_t op2,size_t vl)1956 vfloat32m4_t test_vfwadd_wv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, vfloat16m2_t op2, size_t vl) {
1957 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1958 }
1959
1960 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_wf_f32m4_rm_tum
1961 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1962 // CHECK-RV64-NEXT: entry:
1963 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], half [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1964 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
1965 //
test_vfwadd_wf_f32m4_rm_tum(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,_Float16 op2,size_t vl)1966 vfloat32m4_t test_vfwadd_wf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, _Float16 op2, size_t vl) {
1967 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1968 }
1969
1970 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_vv_f32m8_rm_tum
1971 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1972 // CHECK-RV64-NEXT: entry:
1973 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], <vscale x 16 x half> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1974 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
1975 //
test_vfwadd_vv_f32m8_rm_tum(vbool4_t mask,vfloat32m8_t maskedoff,vfloat16m4_t op1,vfloat16m4_t op2,size_t vl)1976 vfloat32m8_t test_vfwadd_vv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t maskedoff, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
1977 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1978 }
1979
1980 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_vf_f32m8_rm_tum
1981 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1982 // CHECK-RV64-NEXT: entry:
1983 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], half [[OP2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1984 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
1985 //
test_vfwadd_vf_f32m8_rm_tum(vbool4_t mask,vfloat32m8_t maskedoff,vfloat16m4_t op1,_Float16 op2,size_t vl)1986 vfloat32m8_t test_vfwadd_vf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t maskedoff, vfloat16m4_t op1, _Float16 op2, size_t vl) {
1987 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1988 }
1989
1990 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_wv_f32m8_rm_tum
1991 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1992 // CHECK-RV64-NEXT: entry:
1993 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], <vscale x 16 x half> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
1994 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
1995 //
test_vfwadd_wv_f32m8_rm_tum(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,vfloat16m4_t op2,size_t vl)1996 vfloat32m8_t test_vfwadd_wv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, vfloat16m4_t op2, size_t vl) {
1997 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
1998 }
1999
2000 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_wf_f32m8_rm_tum
2001 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2002 // CHECK-RV64-NEXT: entry:
2003 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], half [[OP2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
2004 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
2005 //
test_vfwadd_wf_f32m8_rm_tum(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,_Float16 op2,size_t vl)2006 vfloat32m8_t test_vfwadd_wf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, _Float16 op2, size_t vl) {
2007 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2008 }
2009
2010 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_vv_f64m1_rm_tum
2011 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2012 // CHECK-RV64-NEXT: entry:
2013 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x float> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
2014 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
2015 //
test_vfwadd_vv_f64m1_rm_tum(vbool64_t mask,vfloat64m1_t maskedoff,vfloat32mf2_t op1,vfloat32mf2_t op2,size_t vl)2016 vfloat64m1_t test_vfwadd_vv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
2017 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2018 }
2019
2020 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_vf_f64m1_rm_tum
2021 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2022 // CHECK-RV64-NEXT: entry:
2023 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], float [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
2024 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
2025 //
test_vfwadd_vf_f64m1_rm_tum(vbool64_t mask,vfloat64m1_t maskedoff,vfloat32mf2_t op1,float op2,size_t vl)2026 vfloat64m1_t test_vfwadd_vf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t op1, float op2, size_t vl) {
2027 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2028 }
2029
2030 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_wv_f64m1_rm_tum
2031 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2032 // CHECK-RV64-NEXT: entry:
2033 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], <vscale x 1 x float> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
2034 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
2035 //
test_vfwadd_wv_f64m1_rm_tum(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,vfloat32mf2_t op2,size_t vl)2036 vfloat64m1_t test_vfwadd_wv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, vfloat32mf2_t op2, size_t vl) {
2037 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2038 }
2039
2040 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_wf_f64m1_rm_tum
2041 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2042 // CHECK-RV64-NEXT: entry:
2043 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.mask.nxv1f64.f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], float [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
2044 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
2045 //
test_vfwadd_wf_f64m1_rm_tum(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,float op2,size_t vl)2046 vfloat64m1_t test_vfwadd_wf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, float op2, size_t vl) {
2047 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2048 }
2049
2050 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_vv_f64m2_rm_tum
2051 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2052 // CHECK-RV64-NEXT: entry:
2053 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x float> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
2054 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
2055 //
test_vfwadd_vv_f64m2_rm_tum(vbool32_t mask,vfloat64m2_t maskedoff,vfloat32m1_t op1,vfloat32m1_t op2,size_t vl)2056 vfloat64m2_t test_vfwadd_vv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t maskedoff, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
2057 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2058 }
2059
2060 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_vf_f64m2_rm_tum
2061 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2062 // CHECK-RV64-NEXT: entry:
2063 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], float [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
2064 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
2065 //
test_vfwadd_vf_f64m2_rm_tum(vbool32_t mask,vfloat64m2_t maskedoff,vfloat32m1_t op1,float op2,size_t vl)2066 vfloat64m2_t test_vfwadd_vf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t maskedoff, vfloat32m1_t op1, float op2, size_t vl) {
2067 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2068 }
2069
2070 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_wv_f64m2_rm_tum
2071 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2072 // CHECK-RV64-NEXT: entry:
2073 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.mask.nxv2f64.nxv2f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], <vscale x 2 x float> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
2074 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
2075 //
test_vfwadd_wv_f64m2_rm_tum(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,vfloat32m1_t op2,size_t vl)2076 vfloat64m2_t test_vfwadd_wv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, vfloat32m1_t op2, size_t vl) {
2077 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2078 }
2079
2080 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_wf_f64m2_rm_tum
2081 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2082 // CHECK-RV64-NEXT: entry:
2083 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.mask.nxv2f64.f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], float [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
2084 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
2085 //
test_vfwadd_wf_f64m2_rm_tum(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,float op2,size_t vl)2086 vfloat64m2_t test_vfwadd_wf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, float op2, size_t vl) {
2087 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2088 }
2089
2090 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_vv_f64m4_rm_tum
2091 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2092 // CHECK-RV64-NEXT: entry:
2093 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x float> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
2094 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
2095 //
test_vfwadd_vv_f64m4_rm_tum(vbool16_t mask,vfloat64m4_t maskedoff,vfloat32m2_t op1,vfloat32m2_t op2,size_t vl)2096 vfloat64m4_t test_vfwadd_vv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t maskedoff, vfloat32m2_t op1, vfloat32m2_t op2, size_t vl) {
2097 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2098 }
2099
2100 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_vf_f64m4_rm_tum
2101 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2102 // CHECK-RV64-NEXT: entry:
2103 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], float [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
2104 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
2105 //
test_vfwadd_vf_f64m4_rm_tum(vbool16_t mask,vfloat64m4_t maskedoff,vfloat32m2_t op1,float op2,size_t vl)2106 vfloat64m4_t test_vfwadd_vf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t maskedoff, vfloat32m2_t op1, float op2, size_t vl) {
2107 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2108 }
2109
2110 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_wv_f64m4_rm_tum
2111 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2112 // CHECK-RV64-NEXT: entry:
2113 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.mask.nxv4f64.nxv4f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], <vscale x 4 x float> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
2114 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
2115 //
test_vfwadd_wv_f64m4_rm_tum(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,vfloat32m2_t op2,size_t vl)2116 vfloat64m4_t test_vfwadd_wv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, vfloat32m2_t op2, size_t vl) {
2117 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2118 }
2119
2120 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_wf_f64m4_rm_tum
2121 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2122 // CHECK-RV64-NEXT: entry:
2123 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.mask.nxv4f64.f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], float [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
2124 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
2125 //
test_vfwadd_wf_f64m4_rm_tum(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,float op2,size_t vl)2126 vfloat64m4_t test_vfwadd_wf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, float op2, size_t vl) {
2127 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2128 }
2129
2130 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_vv_f64m8_rm_tum
2131 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2132 // CHECK-RV64-NEXT: entry:
2133 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x float> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
2134 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
2135 //
test_vfwadd_vv_f64m8_rm_tum(vbool8_t mask,vfloat64m8_t maskedoff,vfloat32m4_t op1,vfloat32m4_t op2,size_t vl)2136 vfloat64m8_t test_vfwadd_vv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t maskedoff, vfloat32m4_t op1, vfloat32m4_t op2, size_t vl) {
2137 return __riscv_vfwadd_vv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2138 }
2139
2140 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_vf_f64m8_rm_tum
2141 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2142 // CHECK-RV64-NEXT: entry:
2143 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], float [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
2144 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
2145 //
test_vfwadd_vf_f64m8_rm_tum(vbool8_t mask,vfloat64m8_t maskedoff,vfloat32m4_t op1,float op2,size_t vl)2146 vfloat64m8_t test_vfwadd_vf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t maskedoff, vfloat32m4_t op1, float op2, size_t vl) {
2147 return __riscv_vfwadd_vf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2148 }
2149
2150 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_wv_f64m8_rm_tum
2151 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2152 // CHECK-RV64-NEXT: entry:
2153 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], <vscale x 8 x float> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
2154 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
2155 //
test_vfwadd_wv_f64m8_rm_tum(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,vfloat32m4_t op2,size_t vl)2156 vfloat64m8_t test_vfwadd_wv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, vfloat32m4_t op2, size_t vl) {
2157 return __riscv_vfwadd_wv_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2158 }
2159
2160 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_wf_f64m8_rm_tum
2161 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2162 // CHECK-RV64-NEXT: entry:
2163 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], float [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
2164 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
2165 //
test_vfwadd_wf_f64m8_rm_tum(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,float op2,size_t vl)2166 vfloat64m8_t test_vfwadd_wf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, float op2, size_t vl) {
2167 return __riscv_vfwadd_wf_tum(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2168 }
2169
2170 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_rm_tumu
2171 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2172 // CHECK-RV64-NEXT: entry:
2173 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], <vscale x 1 x half> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2174 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
2175 //
test_vfwadd_vv_f32mf2_rm_tumu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat16mf4_t op1,vfloat16mf4_t op2,size_t vl)2176 vfloat32mf2_t test_vfwadd_vv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
2177 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2178 }
2179
2180 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_rm_tumu
2181 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2182 // CHECK-RV64-NEXT: entry:
2183 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], half [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2184 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
2185 //
test_vfwadd_vf_f32mf2_rm_tumu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat16mf4_t op1,_Float16 op2,size_t vl)2186 vfloat32mf2_t test_vfwadd_vf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat16mf4_t op1, _Float16 op2, size_t vl) {
2187 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2188 }
2189
2190 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_rm_tumu
2191 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2192 // CHECK-RV64-NEXT: entry:
2193 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x half> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2194 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
2195 //
test_vfwadd_wv_f32mf2_rm_tumu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,vfloat16mf4_t op2,size_t vl)2196 vfloat32mf2_t test_vfwadd_wv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, vfloat16mf4_t op2, size_t vl) {
2197 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2198 }
2199
2200 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_rm_tumu
2201 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2202 // CHECK-RV64-NEXT: entry:
2203 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], half [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2204 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
2205 //
test_vfwadd_wf_f32mf2_rm_tumu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,_Float16 op2,size_t vl)2206 vfloat32mf2_t test_vfwadd_wf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, _Float16 op2, size_t vl) {
2207 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2208 }
2209
2210 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_rm_tumu
2211 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2212 // CHECK-RV64-NEXT: entry:
2213 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], <vscale x 2 x half> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2214 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
2215 //
test_vfwadd_vv_f32m1_rm_tumu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat16mf2_t op1,vfloat16mf2_t op2,size_t vl)2216 vfloat32m1_t test_vfwadd_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
2217 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2218 }
2219
2220 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_rm_tumu
2221 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2222 // CHECK-RV64-NEXT: entry:
2223 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], half [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2224 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
2225 //
test_vfwadd_vf_f32m1_rm_tumu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat16mf2_t op1,_Float16 op2,size_t vl)2226 vfloat32m1_t test_vfwadd_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
2227 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2228 }
2229
2230 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_rm_tumu
2231 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2232 // CHECK-RV64-NEXT: entry:
2233 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x half> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2234 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
2235 //
test_vfwadd_wv_f32m1_rm_tumu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,vfloat16mf2_t op2,size_t vl)2236 vfloat32m1_t test_vfwadd_wv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
2237 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2238 }
2239
2240 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_rm_tumu
2241 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2242 // CHECK-RV64-NEXT: entry:
2243 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], half [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2244 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
2245 //
test_vfwadd_wf_f32m1_rm_tumu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,_Float16 op2,size_t vl)2246 vfloat32m1_t test_vfwadd_wf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, _Float16 op2, size_t vl) {
2247 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2248 }
2249
2250 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2_rm_tumu
2251 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2252 // CHECK-RV64-NEXT: entry:
2253 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], <vscale x 4 x half> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2254 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
2255 //
test_vfwadd_vv_f32m2_rm_tumu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat16m1_t op1,vfloat16m1_t op2,size_t vl)2256 vfloat32m2_t test_vfwadd_vv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
2257 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2258 }
2259
2260 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2_rm_tumu
2261 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2262 // CHECK-RV64-NEXT: entry:
2263 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], half [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2264 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
2265 //
test_vfwadd_vf_f32m2_rm_tumu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat16m1_t op1,_Float16 op2,size_t vl)2266 vfloat32m2_t test_vfwadd_vf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat16m1_t op1, _Float16 op2, size_t vl) {
2267 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2268 }
2269
2270 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_wv_f32m2_rm_tumu
2271 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2272 // CHECK-RV64-NEXT: entry:
2273 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.nxv4f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x half> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2274 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
2275 //
test_vfwadd_wv_f32m2_rm_tumu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,vfloat16m1_t op2,size_t vl)2276 vfloat32m2_t test_vfwadd_wv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, vfloat16m1_t op2, size_t vl) {
2277 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2278 }
2279
2280 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_wf_f32m2_rm_tumu
2281 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2282 // CHECK-RV64-NEXT: entry:
2283 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], half [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2284 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
2285 //
test_vfwadd_wf_f32m2_rm_tumu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,_Float16 op2,size_t vl)2286 vfloat32m2_t test_vfwadd_wf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, _Float16 op2, size_t vl) {
2287 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2288 }
2289
2290 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_vv_f32m4_rm_tumu
2291 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2292 // CHECK-RV64-NEXT: entry:
2293 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], <vscale x 8 x half> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2294 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
2295 //
test_vfwadd_vv_f32m4_rm_tumu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat16m2_t op1,vfloat16m2_t op2,size_t vl)2296 vfloat32m4_t test_vfwadd_vv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
2297 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2298 }
2299
2300 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_vf_f32m4_rm_tumu
2301 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2302 // CHECK-RV64-NEXT: entry:
2303 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], half [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2304 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
2305 //
test_vfwadd_vf_f32m4_rm_tumu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat16m2_t op1,_Float16 op2,size_t vl)2306 vfloat32m4_t test_vfwadd_vf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat16m2_t op1, _Float16 op2, size_t vl) {
2307 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2308 }
2309
2310 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_wv_f32m4_rm_tumu
2311 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2312 // CHECK-RV64-NEXT: entry:
2313 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.nxv8f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x half> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2314 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
2315 //
test_vfwadd_wv_f32m4_rm_tumu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,vfloat16m2_t op2,size_t vl)2316 vfloat32m4_t test_vfwadd_wv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, vfloat16m2_t op2, size_t vl) {
2317 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2318 }
2319
2320 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_wf_f32m4_rm_tumu
2321 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2322 // CHECK-RV64-NEXT: entry:
2323 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], half [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2324 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
2325 //
test_vfwadd_wf_f32m4_rm_tumu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,_Float16 op2,size_t vl)2326 vfloat32m4_t test_vfwadd_wf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, _Float16 op2, size_t vl) {
2327 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2328 }
2329
2330 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_vv_f32m8_rm_tumu
2331 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2332 // CHECK-RV64-NEXT: entry:
2333 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], <vscale x 16 x half> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2334 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
2335 //
test_vfwadd_vv_f32m8_rm_tumu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat16m4_t op1,vfloat16m4_t op2,size_t vl)2336 vfloat32m8_t test_vfwadd_vv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
2337 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2338 }
2339
2340 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_vf_f32m8_rm_tumu
2341 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2342 // CHECK-RV64-NEXT: entry:
2343 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], half [[OP2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2344 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
2345 //
test_vfwadd_vf_f32m8_rm_tumu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat16m4_t op1,_Float16 op2,size_t vl)2346 vfloat32m8_t test_vfwadd_vf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat16m4_t op1, _Float16 op2, size_t vl) {
2347 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2348 }
2349
2350 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_wv_f32m8_rm_tumu
2351 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2352 // CHECK-RV64-NEXT: entry:
2353 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], <vscale x 16 x half> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2354 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
2355 //
test_vfwadd_wv_f32m8_rm_tumu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,vfloat16m4_t op2,size_t vl)2356 vfloat32m8_t test_vfwadd_wv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, vfloat16m4_t op2, size_t vl) {
2357 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2358 }
2359
2360 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_wf_f32m8_rm_tumu
2361 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2362 // CHECK-RV64-NEXT: entry:
2363 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], half [[OP2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2364 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
2365 //
test_vfwadd_wf_f32m8_rm_tumu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,_Float16 op2,size_t vl)2366 vfloat32m8_t test_vfwadd_wf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, _Float16 op2, size_t vl) {
2367 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2368 }
2369
2370 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_vv_f64m1_rm_tumu
2371 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2372 // CHECK-RV64-NEXT: entry:
2373 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x float> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2374 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
2375 //
test_vfwadd_vv_f64m1_rm_tumu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat32mf2_t op1,vfloat32mf2_t op2,size_t vl)2376 vfloat64m1_t test_vfwadd_vv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
2377 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2378 }
2379
2380 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_vf_f64m1_rm_tumu
2381 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2382 // CHECK-RV64-NEXT: entry:
2383 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], float [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2384 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
2385 //
test_vfwadd_vf_f64m1_rm_tumu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat32mf2_t op1,float op2,size_t vl)2386 vfloat64m1_t test_vfwadd_vf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t op1, float op2, size_t vl) {
2387 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2388 }
2389
2390 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_wv_f64m1_rm_tumu
2391 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2392 // CHECK-RV64-NEXT: entry:
2393 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], <vscale x 1 x float> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2394 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
2395 //
test_vfwadd_wv_f64m1_rm_tumu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,vfloat32mf2_t op2,size_t vl)2396 vfloat64m1_t test_vfwadd_wv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, vfloat32mf2_t op2, size_t vl) {
2397 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2398 }
2399
2400 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_wf_f64m1_rm_tumu
2401 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2402 // CHECK-RV64-NEXT: entry:
2403 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.mask.nxv1f64.f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], float [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2404 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
2405 //
test_vfwadd_wf_f64m1_rm_tumu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,float op2,size_t vl)2406 vfloat64m1_t test_vfwadd_wf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, float op2, size_t vl) {
2407 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2408 }
2409
2410 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_vv_f64m2_rm_tumu
2411 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2412 // CHECK-RV64-NEXT: entry:
2413 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x float> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2414 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
2415 //
test_vfwadd_vv_f64m2_rm_tumu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat32m1_t op1,vfloat32m1_t op2,size_t vl)2416 vfloat64m2_t test_vfwadd_vv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
2417 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2418 }
2419
2420 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_vf_f64m2_rm_tumu
2421 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2422 // CHECK-RV64-NEXT: entry:
2423 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], float [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2424 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
2425 //
test_vfwadd_vf_f64m2_rm_tumu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat32m1_t op1,float op2,size_t vl)2426 vfloat64m2_t test_vfwadd_vf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat32m1_t op1, float op2, size_t vl) {
2427 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2428 }
2429
2430 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_wv_f64m2_rm_tumu
2431 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2432 // CHECK-RV64-NEXT: entry:
2433 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.mask.nxv2f64.nxv2f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], <vscale x 2 x float> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2434 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
2435 //
test_vfwadd_wv_f64m2_rm_tumu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,vfloat32m1_t op2,size_t vl)2436 vfloat64m2_t test_vfwadd_wv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, vfloat32m1_t op2, size_t vl) {
2437 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2438 }
2439
2440 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_wf_f64m2_rm_tumu
2441 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2442 // CHECK-RV64-NEXT: entry:
2443 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.mask.nxv2f64.f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], float [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2444 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
2445 //
test_vfwadd_wf_f64m2_rm_tumu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,float op2,size_t vl)2446 vfloat64m2_t test_vfwadd_wf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, float op2, size_t vl) {
2447 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2448 }
2449
2450 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_vv_f64m4_rm_tumu
2451 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2452 // CHECK-RV64-NEXT: entry:
2453 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x float> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2454 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
2455 //
test_vfwadd_vv_f64m4_rm_tumu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat32m2_t op1,vfloat32m2_t op2,size_t vl)2456 vfloat64m4_t test_vfwadd_vv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat32m2_t op1, vfloat32m2_t op2, size_t vl) {
2457 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2458 }
2459
2460 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_vf_f64m4_rm_tumu
2461 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2462 // CHECK-RV64-NEXT: entry:
2463 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], float [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2464 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
2465 //
test_vfwadd_vf_f64m4_rm_tumu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat32m2_t op1,float op2,size_t vl)2466 vfloat64m4_t test_vfwadd_vf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat32m2_t op1, float op2, size_t vl) {
2467 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2468 }
2469
2470 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_wv_f64m4_rm_tumu
2471 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2472 // CHECK-RV64-NEXT: entry:
2473 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.mask.nxv4f64.nxv4f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], <vscale x 4 x float> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2474 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
2475 //
test_vfwadd_wv_f64m4_rm_tumu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,vfloat32m2_t op2,size_t vl)2476 vfloat64m4_t test_vfwadd_wv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, vfloat32m2_t op2, size_t vl) {
2477 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2478 }
2479
2480 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_wf_f64m4_rm_tumu
2481 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2482 // CHECK-RV64-NEXT: entry:
2483 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.mask.nxv4f64.f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], float [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2484 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
2485 //
test_vfwadd_wf_f64m4_rm_tumu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,float op2,size_t vl)2486 vfloat64m4_t test_vfwadd_wf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, float op2, size_t vl) {
2487 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2488 }
2489
2490 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_vv_f64m8_rm_tumu
2491 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2492 // CHECK-RV64-NEXT: entry:
2493 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x float> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2494 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
2495 //
test_vfwadd_vv_f64m8_rm_tumu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat32m4_t op1,vfloat32m4_t op2,size_t vl)2496 vfloat64m8_t test_vfwadd_vv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat32m4_t op1, vfloat32m4_t op2, size_t vl) {
2497 return __riscv_vfwadd_vv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2498 }
2499
2500 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_vf_f64m8_rm_tumu
2501 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2502 // CHECK-RV64-NEXT: entry:
2503 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], float [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2504 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
2505 //
test_vfwadd_vf_f64m8_rm_tumu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat32m4_t op1,float op2,size_t vl)2506 vfloat64m8_t test_vfwadd_vf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat32m4_t op1, float op2, size_t vl) {
2507 return __riscv_vfwadd_vf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2508 }
2509
2510 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_wv_f64m8_rm_tumu
2511 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2512 // CHECK-RV64-NEXT: entry:
2513 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], <vscale x 8 x float> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2514 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
2515 //
test_vfwadd_wv_f64m8_rm_tumu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,vfloat32m4_t op2,size_t vl)2516 vfloat64m8_t test_vfwadd_wv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, vfloat32m4_t op2, size_t vl) {
2517 return __riscv_vfwadd_wv_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2518 }
2519
2520 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_wf_f64m8_rm_tumu
2521 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2522 // CHECK-RV64-NEXT: entry:
2523 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], float [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
2524 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
2525 //
test_vfwadd_wf_f64m8_rm_tumu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,float op2,size_t vl)2526 vfloat64m8_t test_vfwadd_wf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, float op2, size_t vl) {
2527 return __riscv_vfwadd_wf_tumu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2528 }
2529
2530 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_rm_mu
2531 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2532 // CHECK-RV64-NEXT: entry:
2533 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], <vscale x 1 x half> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2534 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
2535 //
test_vfwadd_vv_f32mf2_rm_mu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat16mf4_t op1,vfloat16mf4_t op2,size_t vl)2536 vfloat32mf2_t test_vfwadd_vv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
2537 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2538 }
2539
2540 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_rm_mu
2541 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2542 // CHECK-RV64-NEXT: entry:
2543 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], half [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2544 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
2545 //
test_vfwadd_vf_f32mf2_rm_mu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat16mf4_t op1,_Float16 op2,size_t vl)2546 vfloat32mf2_t test_vfwadd_vf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat16mf4_t op1, _Float16 op2, size_t vl) {
2547 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2548 }
2549
2550 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_rm_mu
2551 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2552 // CHECK-RV64-NEXT: entry:
2553 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x half> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2554 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
2555 //
test_vfwadd_wv_f32mf2_rm_mu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,vfloat16mf4_t op2,size_t vl)2556 vfloat32mf2_t test_vfwadd_wv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, vfloat16mf4_t op2, size_t vl) {
2557 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2558 }
2559
2560 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_rm_mu
2561 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2562 // CHECK-RV64-NEXT: entry:
2563 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.f16.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], half [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2564 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
2565 //
test_vfwadd_wf_f32mf2_rm_mu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,_Float16 op2,size_t vl)2566 vfloat32mf2_t test_vfwadd_wf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, _Float16 op2, size_t vl) {
2567 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2568 }
2569
2570 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_rm_mu
2571 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2572 // CHECK-RV64-NEXT: entry:
2573 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], <vscale x 2 x half> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2574 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
2575 //
test_vfwadd_vv_f32m1_rm_mu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat16mf2_t op1,vfloat16mf2_t op2,size_t vl)2576 vfloat32m1_t test_vfwadd_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
2577 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2578 }
2579
2580 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_rm_mu
2581 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2582 // CHECK-RV64-NEXT: entry:
2583 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], half [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2584 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
2585 //
test_vfwadd_vf_f32m1_rm_mu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat16mf2_t op1,_Float16 op2,size_t vl)2586 vfloat32m1_t test_vfwadd_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
2587 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2588 }
2589
2590 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_rm_mu
2591 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2592 // CHECK-RV64-NEXT: entry:
2593 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x half> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2594 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
2595 //
test_vfwadd_wv_f32m1_rm_mu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,vfloat16mf2_t op2,size_t vl)2596 vfloat32m1_t test_vfwadd_wv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
2597 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2598 }
2599
2600 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_rm_mu
2601 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2602 // CHECK-RV64-NEXT: entry:
2603 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], half [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2604 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
2605 //
test_vfwadd_wf_f32m1_rm_mu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,_Float16 op2,size_t vl)2606 vfloat32m1_t test_vfwadd_wf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, _Float16 op2, size_t vl) {
2607 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2608 }
2609
2610 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2_rm_mu
2611 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2612 // CHECK-RV64-NEXT: entry:
2613 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], <vscale x 4 x half> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2614 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
2615 //
test_vfwadd_vv_f32m2_rm_mu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat16m1_t op1,vfloat16m1_t op2,size_t vl)2616 vfloat32m2_t test_vfwadd_vv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
2617 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2618 }
2619
2620 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2_rm_mu
2621 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2622 // CHECK-RV64-NEXT: entry:
2623 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], half [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2624 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
2625 //
test_vfwadd_vf_f32m2_rm_mu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat16m1_t op1,_Float16 op2,size_t vl)2626 vfloat32m2_t test_vfwadd_vf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat16m1_t op1, _Float16 op2, size_t vl) {
2627 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2628 }
2629
2630 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_wv_f32m2_rm_mu
2631 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2632 // CHECK-RV64-NEXT: entry:
2633 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.nxv4f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x half> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2634 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
2635 //
test_vfwadd_wv_f32m2_rm_mu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,vfloat16m1_t op2,size_t vl)2636 vfloat32m2_t test_vfwadd_wv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, vfloat16m1_t op2, size_t vl) {
2637 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2638 }
2639
2640 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwadd_wf_f32m2_rm_mu
2641 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2642 // CHECK-RV64-NEXT: entry:
2643 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.f16.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], half [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2644 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
2645 //
test_vfwadd_wf_f32m2_rm_mu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,_Float16 op2,size_t vl)2646 vfloat32m2_t test_vfwadd_wf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, _Float16 op2, size_t vl) {
2647 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2648 }
2649
2650 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_vv_f32m4_rm_mu
2651 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2652 // CHECK-RV64-NEXT: entry:
2653 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], <vscale x 8 x half> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2654 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
2655 //
test_vfwadd_vv_f32m4_rm_mu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat16m2_t op1,vfloat16m2_t op2,size_t vl)2656 vfloat32m4_t test_vfwadd_vv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
2657 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2658 }
2659
2660 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_vf_f32m4_rm_mu
2661 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2662 // CHECK-RV64-NEXT: entry:
2663 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], half [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2664 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
2665 //
test_vfwadd_vf_f32m4_rm_mu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat16m2_t op1,_Float16 op2,size_t vl)2666 vfloat32m4_t test_vfwadd_vf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat16m2_t op1, _Float16 op2, size_t vl) {
2667 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2668 }
2669
2670 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_wv_f32m4_rm_mu
2671 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2672 // CHECK-RV64-NEXT: entry:
2673 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.nxv8f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x half> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2674 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
2675 //
test_vfwadd_wv_f32m4_rm_mu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,vfloat16m2_t op2,size_t vl)2676 vfloat32m4_t test_vfwadd_wv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, vfloat16m2_t op2, size_t vl) {
2677 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2678 }
2679
2680 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwadd_wf_f32m4_rm_mu
2681 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2682 // CHECK-RV64-NEXT: entry:
2683 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.f16.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], half [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2684 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
2685 //
test_vfwadd_wf_f32m4_rm_mu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,_Float16 op2,size_t vl)2686 vfloat32m4_t test_vfwadd_wf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, _Float16 op2, size_t vl) {
2687 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2688 }
2689
2690 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_vv_f32m8_rm_mu
2691 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2692 // CHECK-RV64-NEXT: entry:
2693 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], <vscale x 16 x half> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2694 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
2695 //
test_vfwadd_vv_f32m8_rm_mu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat16m4_t op1,vfloat16m4_t op2,size_t vl)2696 vfloat32m8_t test_vfwadd_vv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
2697 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2698 }
2699
2700 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_vf_f32m8_rm_mu
2701 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2702 // CHECK-RV64-NEXT: entry:
2703 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], half [[OP2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2704 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
2705 //
test_vfwadd_vf_f32m8_rm_mu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat16m4_t op1,_Float16 op2,size_t vl)2706 vfloat32m8_t test_vfwadd_vf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat16m4_t op1, _Float16 op2, size_t vl) {
2707 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2708 }
2709
2710 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_wv_f32m8_rm_mu
2711 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2712 // CHECK-RV64-NEXT: entry:
2713 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], <vscale x 16 x half> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2714 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
2715 //
test_vfwadd_wv_f32m8_rm_mu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,vfloat16m4_t op2,size_t vl)2716 vfloat32m8_t test_vfwadd_wv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, vfloat16m4_t op2, size_t vl) {
2717 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2718 }
2719
2720 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwadd_wf_f32m8_rm_mu
2721 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2722 // CHECK-RV64-NEXT: entry:
2723 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.f16.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], half [[OP2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2724 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
2725 //
test_vfwadd_wf_f32m8_rm_mu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,_Float16 op2,size_t vl)2726 vfloat32m8_t test_vfwadd_wf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, _Float16 op2, size_t vl) {
2727 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2728 }
2729
2730 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_vv_f64m1_rm_mu
2731 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2732 // CHECK-RV64-NEXT: entry:
2733 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x float> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2734 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
2735 //
test_vfwadd_vv_f64m1_rm_mu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat32mf2_t op1,vfloat32mf2_t op2,size_t vl)2736 vfloat64m1_t test_vfwadd_vv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
2737 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2738 }
2739
2740 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_vf_f64m1_rm_mu
2741 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2742 // CHECK-RV64-NEXT: entry:
2743 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], float [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2744 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
2745 //
test_vfwadd_vf_f64m1_rm_mu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat32mf2_t op1,float op2,size_t vl)2746 vfloat64m1_t test_vfwadd_vf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t op1, float op2, size_t vl) {
2747 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2748 }
2749
2750 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_wv_f64m1_rm_mu
2751 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2752 // CHECK-RV64-NEXT: entry:
2753 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], <vscale x 1 x float> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2754 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
2755 //
test_vfwadd_wv_f64m1_rm_mu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,vfloat32mf2_t op2,size_t vl)2756 vfloat64m1_t test_vfwadd_wv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, vfloat32mf2_t op2, size_t vl) {
2757 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2758 }
2759
2760 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwadd_wf_f64m1_rm_mu
2761 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2762 // CHECK-RV64-NEXT: entry:
2763 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.mask.nxv1f64.f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], float [[OP2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2764 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
2765 //
test_vfwadd_wf_f64m1_rm_mu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,float op2,size_t vl)2766 vfloat64m1_t test_vfwadd_wf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, float op2, size_t vl) {
2767 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2768 }
2769
2770 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_vv_f64m2_rm_mu
2771 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2772 // CHECK-RV64-NEXT: entry:
2773 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x float> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2774 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
2775 //
test_vfwadd_vv_f64m2_rm_mu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat32m1_t op1,vfloat32m1_t op2,size_t vl)2776 vfloat64m2_t test_vfwadd_vv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
2777 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2778 }
2779
2780 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_vf_f64m2_rm_mu
2781 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2782 // CHECK-RV64-NEXT: entry:
2783 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], float [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2784 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
2785 //
test_vfwadd_vf_f64m2_rm_mu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat32m1_t op1,float op2,size_t vl)2786 vfloat64m2_t test_vfwadd_vf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat32m1_t op1, float op2, size_t vl) {
2787 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2788 }
2789
2790 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_wv_f64m2_rm_mu
2791 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2792 // CHECK-RV64-NEXT: entry:
2793 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.mask.nxv2f64.nxv2f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], <vscale x 2 x float> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2794 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
2795 //
test_vfwadd_wv_f64m2_rm_mu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,vfloat32m1_t op2,size_t vl)2796 vfloat64m2_t test_vfwadd_wv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, vfloat32m1_t op2, size_t vl) {
2797 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2798 }
2799
2800 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwadd_wf_f64m2_rm_mu
2801 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2802 // CHECK-RV64-NEXT: entry:
2803 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.mask.nxv2f64.f32.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], float [[OP2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2804 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
2805 //
test_vfwadd_wf_f64m2_rm_mu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,float op2,size_t vl)2806 vfloat64m2_t test_vfwadd_wf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, float op2, size_t vl) {
2807 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2808 }
2809
2810 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_vv_f64m4_rm_mu
2811 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2812 // CHECK-RV64-NEXT: entry:
2813 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x float> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2814 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
2815 //
test_vfwadd_vv_f64m4_rm_mu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat32m2_t op1,vfloat32m2_t op2,size_t vl)2816 vfloat64m4_t test_vfwadd_vv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat32m2_t op1, vfloat32m2_t op2, size_t vl) {
2817 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2818 }
2819
2820 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_vf_f64m4_rm_mu
2821 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2822 // CHECK-RV64-NEXT: entry:
2823 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], float [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2824 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
2825 //
test_vfwadd_vf_f64m4_rm_mu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat32m2_t op1,float op2,size_t vl)2826 vfloat64m4_t test_vfwadd_vf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat32m2_t op1, float op2, size_t vl) {
2827 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2828 }
2829
2830 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_wv_f64m4_rm_mu
2831 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2832 // CHECK-RV64-NEXT: entry:
2833 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.mask.nxv4f64.nxv4f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], <vscale x 4 x float> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2834 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
2835 //
test_vfwadd_wv_f64m4_rm_mu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,vfloat32m2_t op2,size_t vl)2836 vfloat64m4_t test_vfwadd_wv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, vfloat32m2_t op2, size_t vl) {
2837 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2838 }
2839
2840 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwadd_wf_f64m4_rm_mu
2841 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2842 // CHECK-RV64-NEXT: entry:
2843 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.mask.nxv4f64.f32.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], float [[OP2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2844 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
2845 //
test_vfwadd_wf_f64m4_rm_mu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,float op2,size_t vl)2846 vfloat64m4_t test_vfwadd_wf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, float op2, size_t vl) {
2847 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2848 }
2849
2850 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_vv_f64m8_rm_mu
2851 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2852 // CHECK-RV64-NEXT: entry:
2853 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x float> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2854 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
2855 //
test_vfwadd_vv_f64m8_rm_mu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat32m4_t op1,vfloat32m4_t op2,size_t vl)2856 vfloat64m8_t test_vfwadd_vv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat32m4_t op1, vfloat32m4_t op2, size_t vl) {
2857 return __riscv_vfwadd_vv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2858 }
2859
2860 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_vf_f64m8_rm_mu
2861 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2862 // CHECK-RV64-NEXT: entry:
2863 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], float [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2864 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
2865 //
test_vfwadd_vf_f64m8_rm_mu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat32m4_t op1,float op2,size_t vl)2866 vfloat64m8_t test_vfwadd_vf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat32m4_t op1, float op2, size_t vl) {
2867 return __riscv_vfwadd_vf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2868 }
2869
2870 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_wv_f64m8_rm_mu
2871 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2872 // CHECK-RV64-NEXT: entry:
2873 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], <vscale x 8 x float> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2874 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
2875 //
test_vfwadd_wv_f64m8_rm_mu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,vfloat32m4_t op2,size_t vl)2876 vfloat64m8_t test_vfwadd_wv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, vfloat32m4_t op2, size_t vl) {
2877 return __riscv_vfwadd_wv_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2878 }
2879
2880 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwadd_wf_f64m8_rm_mu
2881 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2882 // CHECK-RV64-NEXT: entry:
2883 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.f32.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], float [[OP2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
2884 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
2885 //
test_vfwadd_wf_f64m8_rm_mu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,float op2,size_t vl)2886 vfloat64m8_t test_vfwadd_wf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, float op2, size_t vl) {
2887 return __riscv_vfwadd_wf_mu(mask, maskedoff, op1, op2, __RISCV_FRM_RNE, vl);
2888 }
2889
2890