1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4 // RUN: -target-feature +zvfh -disable-O0-optnone \
5 // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
6 // RUN: FileCheck --check-prefix=CHECK-RV64 %s
7
8 #include <riscv_vector.h>
9
10 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4_tu
11 // CHECK-RV64-SAME: (<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
12 // CHECK-RV64-NEXT: entry:
13 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], half [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
14 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
15 //
test_vfmerge_vfm_f16mf4_tu(vfloat16mf4_t maskedoff,vfloat16mf4_t op1,_Float16 op2,vbool64_t mask,size_t vl)16 vfloat16mf4_t test_vfmerge_vfm_f16mf4_tu(vfloat16mf4_t maskedoff, vfloat16mf4_t op1, _Float16 op2, vbool64_t mask, size_t vl) {
17 return __riscv_vfmerge_tu(maskedoff, op1, op2, mask, vl);
18 }
19
20 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2_tu
21 // CHECK-RV64-SAME: (<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
22 // CHECK-RV64-NEXT: entry:
23 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], half [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
24 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
25 //
test_vfmerge_vfm_f16mf2_tu(vfloat16mf2_t maskedoff,vfloat16mf2_t op1,_Float16 op2,vbool32_t mask,size_t vl)26 vfloat16mf2_t test_vfmerge_vfm_f16mf2_tu(vfloat16mf2_t maskedoff, vfloat16mf2_t op1, _Float16 op2, vbool32_t mask, size_t vl) {
27 return __riscv_vfmerge_tu(maskedoff, op1, op2, mask, vl);
28 }
29
30 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1_tu
31 // CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
32 // CHECK-RV64-NEXT: entry:
33 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], half [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
34 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
35 //
test_vfmerge_vfm_f16m1_tu(vfloat16m1_t maskedoff,vfloat16m1_t op1,_Float16 op2,vbool16_t mask,size_t vl)36 vfloat16m1_t test_vfmerge_vfm_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m1_t op1, _Float16 op2, vbool16_t mask, size_t vl) {
37 return __riscv_vfmerge_tu(maskedoff, op1, op2, mask, vl);
38 }
39
40 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2_tu
41 // CHECK-RV64-SAME: (<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
42 // CHECK-RV64-NEXT: entry:
43 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], half [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
44 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
45 //
test_vfmerge_vfm_f16m2_tu(vfloat16m2_t maskedoff,vfloat16m2_t op1,_Float16 op2,vbool8_t mask,size_t vl)46 vfloat16m2_t test_vfmerge_vfm_f16m2_tu(vfloat16m2_t maskedoff, vfloat16m2_t op1, _Float16 op2, vbool8_t mask, size_t vl) {
47 return __riscv_vfmerge_tu(maskedoff, op1, op2, mask, vl);
48 }
49
50 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4_tu
51 // CHECK-RV64-SAME: (<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
52 // CHECK-RV64-NEXT: entry:
53 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], half [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
54 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
55 //
test_vfmerge_vfm_f16m4_tu(vfloat16m4_t maskedoff,vfloat16m4_t op1,_Float16 op2,vbool4_t mask,size_t vl)56 vfloat16m4_t test_vfmerge_vfm_f16m4_tu(vfloat16m4_t maskedoff, vfloat16m4_t op1, _Float16 op2, vbool4_t mask, size_t vl) {
57 return __riscv_vfmerge_tu(maskedoff, op1, op2, mask, vl);
58 }
59
60 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8_tu
61 // CHECK-RV64-SAME: (<vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
62 // CHECK-RV64-NEXT: entry:
63 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x half> [[OP1]], half [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
64 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
65 //
test_vfmerge_vfm_f16m8_tu(vfloat16m8_t maskedoff,vfloat16m8_t op1,_Float16 op2,vbool2_t mask,size_t vl)66 vfloat16m8_t test_vfmerge_vfm_f16m8_tu(vfloat16m8_t maskedoff, vfloat16m8_t op1, _Float16 op2, vbool2_t mask, size_t vl) {
67 return __riscv_vfmerge_tu(maskedoff, op1, op2, mask, vl);
68 }
69
70 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2_tu
71 // CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
72 // CHECK-RV64-NEXT: entry:
73 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], float [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
74 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
75 //
test_vfmerge_vfm_f32mf2_tu(vfloat32mf2_t maskedoff,vfloat32mf2_t op1,float op2,vbool64_t mask,size_t vl)76 vfloat32mf2_t test_vfmerge_vfm_f32mf2_tu(vfloat32mf2_t maskedoff, vfloat32mf2_t op1, float op2, vbool64_t mask, size_t vl) {
77 return __riscv_vfmerge_tu(maskedoff, op1, op2, mask, vl);
78 }
79
80 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmerge_vfm_f32m1_tu
81 // CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
82 // CHECK-RV64-NEXT: entry:
83 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], float [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
84 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
85 //
test_vfmerge_vfm_f32m1_tu(vfloat32m1_t maskedoff,vfloat32m1_t op1,float op2,vbool32_t mask,size_t vl)86 vfloat32m1_t test_vfmerge_vfm_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m1_t op1, float op2, vbool32_t mask, size_t vl) {
87 return __riscv_vfmerge_tu(maskedoff, op1, op2, mask, vl);
88 }
89
90 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmerge_vfm_f32m2_tu
91 // CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
92 // CHECK-RV64-NEXT: entry:
93 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmerge.nxv4f32.f32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], float [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
94 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
95 //
test_vfmerge_vfm_f32m2_tu(vfloat32m2_t maskedoff,vfloat32m2_t op1,float op2,vbool16_t mask,size_t vl)96 vfloat32m2_t test_vfmerge_vfm_f32m2_tu(vfloat32m2_t maskedoff, vfloat32m2_t op1, float op2, vbool16_t mask, size_t vl) {
97 return __riscv_vfmerge_tu(maskedoff, op1, op2, mask, vl);
98 }
99
100 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmerge_vfm_f32m4_tu
101 // CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
102 // CHECK-RV64-NEXT: entry:
103 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmerge.nxv8f32.f32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], float [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
104 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
105 //
test_vfmerge_vfm_f32m4_tu(vfloat32m4_t maskedoff,vfloat32m4_t op1,float op2,vbool8_t mask,size_t vl)106 vfloat32m4_t test_vfmerge_vfm_f32m4_tu(vfloat32m4_t maskedoff, vfloat32m4_t op1, float op2, vbool8_t mask, size_t vl) {
107 return __riscv_vfmerge_tu(maskedoff, op1, op2, mask, vl);
108 }
109
110 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmerge_vfm_f32m8_tu
111 // CHECK-RV64-SAME: (<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
112 // CHECK-RV64-NEXT: entry:
113 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.f32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], float [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
114 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
115 //
test_vfmerge_vfm_f32m8_tu(vfloat32m8_t maskedoff,vfloat32m8_t op1,float op2,vbool4_t mask,size_t vl)116 vfloat32m8_t test_vfmerge_vfm_f32m8_tu(vfloat32m8_t maskedoff, vfloat32m8_t op1, float op2, vbool4_t mask, size_t vl) {
117 return __riscv_vfmerge_tu(maskedoff, op1, op2, mask, vl);
118 }
119
120 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmerge_vfm_f64m1_tu
121 // CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
122 // CHECK-RV64-NEXT: entry:
123 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmerge.nxv1f64.f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], double [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
124 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
125 //
test_vfmerge_vfm_f64m1_tu(vfloat64m1_t maskedoff,vfloat64m1_t op1,double op2,vbool64_t mask,size_t vl)126 vfloat64m1_t test_vfmerge_vfm_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m1_t op1, double op2, vbool64_t mask, size_t vl) {
127 return __riscv_vfmerge_tu(maskedoff, op1, op2, mask, vl);
128 }
129
130 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmerge_vfm_f64m2_tu
131 // CHECK-RV64-SAME: (<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
132 // CHECK-RV64-NEXT: entry:
133 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmerge.nxv2f64.f64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], double [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
134 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
135 //
test_vfmerge_vfm_f64m2_tu(vfloat64m2_t maskedoff,vfloat64m2_t op1,double op2,vbool32_t mask,size_t vl)136 vfloat64m2_t test_vfmerge_vfm_f64m2_tu(vfloat64m2_t maskedoff, vfloat64m2_t op1, double op2, vbool32_t mask, size_t vl) {
137 return __riscv_vfmerge_tu(maskedoff, op1, op2, mask, vl);
138 }
139
140 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmerge_vfm_f64m4_tu
141 // CHECK-RV64-SAME: (<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
142 // CHECK-RV64-NEXT: entry:
143 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmerge.nxv4f64.f64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], double [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
144 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
145 //
test_vfmerge_vfm_f64m4_tu(vfloat64m4_t maskedoff,vfloat64m4_t op1,double op2,vbool16_t mask,size_t vl)146 vfloat64m4_t test_vfmerge_vfm_f64m4_tu(vfloat64m4_t maskedoff, vfloat64m4_t op1, double op2, vbool16_t mask, size_t vl) {
147 return __riscv_vfmerge_tu(maskedoff, op1, op2, mask, vl);
148 }
149
150 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmerge_vfm_f64m8_tu
151 // CHECK-RV64-SAME: (<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
152 // CHECK-RV64-NEXT: entry:
153 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.f64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], double [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
154 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
155 //
test_vfmerge_vfm_f64m8_tu(vfloat64m8_t maskedoff,vfloat64m8_t op1,double op2,vbool8_t mask,size_t vl)156 vfloat64m8_t test_vfmerge_vfm_f64m8_tu(vfloat64m8_t maskedoff, vfloat64m8_t op1, double op2, vbool8_t mask, size_t vl) {
157 return __riscv_vfmerge_tu(maskedoff, op1, op2, mask, vl);
158 }
159
160