1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4 // RUN: -target-feature +zvfh -disable-O0-optnone \
5 // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
6 // RUN: FileCheck --check-prefix=CHECK-RV64 %s
7
8 #include <riscv_vector.h>
9
10 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4_tu
11 // CHECK-RV64-SAME: (<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
12 // CHECK-RV64-NEXT: entry:
13 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], <vscale x 1 x half> [[OP2]], i64 [[VL]])
14 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
15 //
test_vfmax_vv_f16mf4_tu(vfloat16mf4_t maskedoff,vfloat16mf4_t op1,vfloat16mf4_t op2,size_t vl)16 vfloat16mf4_t test_vfmax_vv_f16mf4_tu(vfloat16mf4_t maskedoff, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
17 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
18 }
19
20 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4_tu
21 // CHECK-RV64-SAME: (<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
22 // CHECK-RV64-NEXT: entry:
23 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], half [[OP2]], i64 [[VL]])
24 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
25 //
test_vfmax_vf_f16mf4_tu(vfloat16mf4_t maskedoff,vfloat16mf4_t op1,_Float16 op2,size_t vl)26 vfloat16mf4_t test_vfmax_vf_f16mf4_tu(vfloat16mf4_t maskedoff, vfloat16mf4_t op1, _Float16 op2, size_t vl) {
27 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
28 }
29
30 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2_tu
31 // CHECK-RV64-SAME: (<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
32 // CHECK-RV64-NEXT: entry:
33 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], <vscale x 2 x half> [[OP2]], i64 [[VL]])
34 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
35 //
test_vfmax_vv_f16mf2_tu(vfloat16mf2_t maskedoff,vfloat16mf2_t op1,vfloat16mf2_t op2,size_t vl)36 vfloat16mf2_t test_vfmax_vv_f16mf2_tu(vfloat16mf2_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
37 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
38 }
39
40 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2_tu
41 // CHECK-RV64-SAME: (<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
42 // CHECK-RV64-NEXT: entry:
43 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], half [[OP2]], i64 [[VL]])
44 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
45 //
test_vfmax_vf_f16mf2_tu(vfloat16mf2_t maskedoff,vfloat16mf2_t op1,_Float16 op2,size_t vl)46 vfloat16mf2_t test_vfmax_vf_f16mf2_tu(vfloat16mf2_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
47 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
48 }
49
50 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1_tu
51 // CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
52 // CHECK-RV64-NEXT: entry:
53 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], <vscale x 4 x half> [[OP2]], i64 [[VL]])
54 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
55 //
test_vfmax_vv_f16m1_tu(vfloat16m1_t maskedoff,vfloat16m1_t op1,vfloat16m1_t op2,size_t vl)56 vfloat16m1_t test_vfmax_vv_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
57 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
58 }
59
60 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1_tu
61 // CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
62 // CHECK-RV64-NEXT: entry:
63 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], half [[OP2]], i64 [[VL]])
64 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
65 //
test_vfmax_vf_f16m1_tu(vfloat16m1_t maskedoff,vfloat16m1_t op1,_Float16 op2,size_t vl)66 vfloat16m1_t test_vfmax_vf_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m1_t op1, _Float16 op2, size_t vl) {
67 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
68 }
69
70 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2_tu
71 // CHECK-RV64-SAME: (<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
72 // CHECK-RV64-NEXT: entry:
73 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], <vscale x 8 x half> [[OP2]], i64 [[VL]])
74 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
75 //
test_vfmax_vv_f16m2_tu(vfloat16m2_t maskedoff,vfloat16m2_t op1,vfloat16m2_t op2,size_t vl)76 vfloat16m2_t test_vfmax_vv_f16m2_tu(vfloat16m2_t maskedoff, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
77 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
78 }
79
80 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2_tu
81 // CHECK-RV64-SAME: (<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
82 // CHECK-RV64-NEXT: entry:
83 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], half [[OP2]], i64 [[VL]])
84 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
85 //
test_vfmax_vf_f16m2_tu(vfloat16m2_t maskedoff,vfloat16m2_t op1,_Float16 op2,size_t vl)86 vfloat16m2_t test_vfmax_vf_f16m2_tu(vfloat16m2_t maskedoff, vfloat16m2_t op1, _Float16 op2, size_t vl) {
87 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
88 }
89
90 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4_tu
91 // CHECK-RV64-SAME: (<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
92 // CHECK-RV64-NEXT: entry:
93 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], <vscale x 16 x half> [[OP2]], i64 [[VL]])
94 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
95 //
test_vfmax_vv_f16m4_tu(vfloat16m4_t maskedoff,vfloat16m4_t op1,vfloat16m4_t op2,size_t vl)96 vfloat16m4_t test_vfmax_vv_f16m4_tu(vfloat16m4_t maskedoff, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
97 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
98 }
99
100 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmax_vf_f16m4_tu
101 // CHECK-RV64-SAME: (<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
102 // CHECK-RV64-NEXT: entry:
103 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.f16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], half [[OP2]], i64 [[VL]])
104 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
105 //
test_vfmax_vf_f16m4_tu(vfloat16m4_t maskedoff,vfloat16m4_t op1,_Float16 op2,size_t vl)106 vfloat16m4_t test_vfmax_vf_f16m4_tu(vfloat16m4_t maskedoff, vfloat16m4_t op1, _Float16 op2, size_t vl) {
107 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
108 }
109
110 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmax_vv_f16m8_tu
111 // CHECK-RV64-SAME: (<vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], <vscale x 32 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
112 // CHECK-RV64-NEXT: entry:
113 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmax.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x half> [[OP1]], <vscale x 32 x half> [[OP2]], i64 [[VL]])
114 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
115 //
test_vfmax_vv_f16m8_tu(vfloat16m8_t maskedoff,vfloat16m8_t op1,vfloat16m8_t op2,size_t vl)116 vfloat16m8_t test_vfmax_vv_f16m8_tu(vfloat16m8_t maskedoff, vfloat16m8_t op1, vfloat16m8_t op2, size_t vl) {
117 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
118 }
119
120 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmax_vf_f16m8_tu
121 // CHECK-RV64-SAME: (<vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
122 // CHECK-RV64-NEXT: entry:
123 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmax.nxv32f16.f16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x half> [[OP1]], half [[OP2]], i64 [[VL]])
124 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
125 //
test_vfmax_vf_f16m8_tu(vfloat16m8_t maskedoff,vfloat16m8_t op1,_Float16 op2,size_t vl)126 vfloat16m8_t test_vfmax_vf_f16m8_tu(vfloat16m8_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {
127 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
128 }
129
130 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmax_vv_f32mf2_tu
131 // CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
132 // CHECK-RV64-NEXT: entry:
133 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmax.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x float> [[OP2]], i64 [[VL]])
134 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
135 //
test_vfmax_vv_f32mf2_tu(vfloat32mf2_t maskedoff,vfloat32mf2_t op1,vfloat32mf2_t op2,size_t vl)136 vfloat32mf2_t test_vfmax_vv_f32mf2_tu(vfloat32mf2_t maskedoff, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
137 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
138 }
139
140 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmax_vf_f32mf2_tu
141 // CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
142 // CHECK-RV64-NEXT: entry:
143 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmax.nxv1f32.f32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], float [[OP2]], i64 [[VL]])
144 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
145 //
test_vfmax_vf_f32mf2_tu(vfloat32mf2_t maskedoff,vfloat32mf2_t op1,float op2,size_t vl)146 vfloat32mf2_t test_vfmax_vf_f32mf2_tu(vfloat32mf2_t maskedoff, vfloat32mf2_t op1, float op2, size_t vl) {
147 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
148 }
149
150 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmax_vv_f32m1_tu
151 // CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
152 // CHECK-RV64-NEXT: entry:
153 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x float> [[OP2]], i64 [[VL]])
154 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
155 //
test_vfmax_vv_f32m1_tu(vfloat32m1_t maskedoff,vfloat32m1_t op1,vfloat32m1_t op2,size_t vl)156 vfloat32m1_t test_vfmax_vv_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
157 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
158 }
159
160 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmax_vf_f32m1_tu
161 // CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
162 // CHECK-RV64-NEXT: entry:
163 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmax.nxv2f32.f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], float [[OP2]], i64 [[VL]])
164 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
165 //
test_vfmax_vf_f32m1_tu(vfloat32m1_t maskedoff,vfloat32m1_t op1,float op2,size_t vl)166 vfloat32m1_t test_vfmax_vf_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m1_t op1, float op2, size_t vl) {
167 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
168 }
169
170 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmax_vv_f32m2_tu
171 // CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
172 // CHECK-RV64-NEXT: entry:
173 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmax.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x float> [[OP2]], i64 [[VL]])
174 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
175 //
test_vfmax_vv_f32m2_tu(vfloat32m2_t maskedoff,vfloat32m2_t op1,vfloat32m2_t op2,size_t vl)176 vfloat32m2_t test_vfmax_vv_f32m2_tu(vfloat32m2_t maskedoff, vfloat32m2_t op1, vfloat32m2_t op2, size_t vl) {
177 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
178 }
179
180 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmax_vf_f32m2_tu
181 // CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
182 // CHECK-RV64-NEXT: entry:
183 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmax.nxv4f32.f32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], float [[OP2]], i64 [[VL]])
184 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
185 //
test_vfmax_vf_f32m2_tu(vfloat32m2_t maskedoff,vfloat32m2_t op1,float op2,size_t vl)186 vfloat32m2_t test_vfmax_vf_f32m2_tu(vfloat32m2_t maskedoff, vfloat32m2_t op1, float op2, size_t vl) {
187 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
188 }
189
190 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmax_vv_f32m4_tu
191 // CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
192 // CHECK-RV64-NEXT: entry:
193 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmax.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x float> [[OP2]], i64 [[VL]])
194 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
195 //
test_vfmax_vv_f32m4_tu(vfloat32m4_t maskedoff,vfloat32m4_t op1,vfloat32m4_t op2,size_t vl)196 vfloat32m4_t test_vfmax_vv_f32m4_tu(vfloat32m4_t maskedoff, vfloat32m4_t op1, vfloat32m4_t op2, size_t vl) {
197 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
198 }
199
200 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmax_vf_f32m4_tu
201 // CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
202 // CHECK-RV64-NEXT: entry:
203 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmax.nxv8f32.f32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], float [[OP2]], i64 [[VL]])
204 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
205 //
test_vfmax_vf_f32m4_tu(vfloat32m4_t maskedoff,vfloat32m4_t op1,float op2,size_t vl)206 vfloat32m4_t test_vfmax_vf_f32m4_tu(vfloat32m4_t maskedoff, vfloat32m4_t op1, float op2, size_t vl) {
207 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
208 }
209
210 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmax_vv_f32m8_tu
211 // CHECK-RV64-SAME: (<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
212 // CHECK-RV64-NEXT: entry:
213 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmax.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], <vscale x 16 x float> [[OP2]], i64 [[VL]])
214 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
215 //
test_vfmax_vv_f32m8_tu(vfloat32m8_t maskedoff,vfloat32m8_t op1,vfloat32m8_t op2,size_t vl)216 vfloat32m8_t test_vfmax_vv_f32m8_tu(vfloat32m8_t maskedoff, vfloat32m8_t op1, vfloat32m8_t op2, size_t vl) {
217 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
218 }
219
220 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmax_vf_f32m8_tu
221 // CHECK-RV64-SAME: (<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
222 // CHECK-RV64-NEXT: entry:
223 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmax.nxv16f32.f32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], float [[OP2]], i64 [[VL]])
224 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
225 //
test_vfmax_vf_f32m8_tu(vfloat32m8_t maskedoff,vfloat32m8_t op1,float op2,size_t vl)226 vfloat32m8_t test_vfmax_vf_f32m8_tu(vfloat32m8_t maskedoff, vfloat32m8_t op1, float op2, size_t vl) {
227 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
228 }
229
230 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmax_vv_f64m1_tu
231 // CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
232 // CHECK-RV64-NEXT: entry:
233 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmax.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], <vscale x 1 x double> [[OP2]], i64 [[VL]])
234 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
235 //
test_vfmax_vv_f64m1_tu(vfloat64m1_t maskedoff,vfloat64m1_t op1,vfloat64m1_t op2,size_t vl)236 vfloat64m1_t test_vfmax_vv_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m1_t op1, vfloat64m1_t op2, size_t vl) {
237 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
238 }
239
240 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmax_vf_f64m1_tu
241 // CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
242 // CHECK-RV64-NEXT: entry:
243 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmax.nxv1f64.f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], double [[OP2]], i64 [[VL]])
244 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
245 //
test_vfmax_vf_f64m1_tu(vfloat64m1_t maskedoff,vfloat64m1_t op1,double op2,size_t vl)246 vfloat64m1_t test_vfmax_vf_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m1_t op1, double op2, size_t vl) {
247 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
248 }
249
250 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmax_vv_f64m2_tu
251 // CHECK-RV64-SAME: (<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
252 // CHECK-RV64-NEXT: entry:
253 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmax.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], <vscale x 2 x double> [[OP2]], i64 [[VL]])
254 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
255 //
test_vfmax_vv_f64m2_tu(vfloat64m2_t maskedoff,vfloat64m2_t op1,vfloat64m2_t op2,size_t vl)256 vfloat64m2_t test_vfmax_vv_f64m2_tu(vfloat64m2_t maskedoff, vfloat64m2_t op1, vfloat64m2_t op2, size_t vl) {
257 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
258 }
259
260 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmax_vf_f64m2_tu
261 // CHECK-RV64-SAME: (<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
262 // CHECK-RV64-NEXT: entry:
263 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmax.nxv2f64.f64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], double [[OP2]], i64 [[VL]])
264 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
265 //
test_vfmax_vf_f64m2_tu(vfloat64m2_t maskedoff,vfloat64m2_t op1,double op2,size_t vl)266 vfloat64m2_t test_vfmax_vf_f64m2_tu(vfloat64m2_t maskedoff, vfloat64m2_t op1, double op2, size_t vl) {
267 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
268 }
269
270 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmax_vv_f64m4_tu
271 // CHECK-RV64-SAME: (<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
272 // CHECK-RV64-NEXT: entry:
273 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmax.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], <vscale x 4 x double> [[OP2]], i64 [[VL]])
274 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
275 //
test_vfmax_vv_f64m4_tu(vfloat64m4_t maskedoff,vfloat64m4_t op1,vfloat64m4_t op2,size_t vl)276 vfloat64m4_t test_vfmax_vv_f64m4_tu(vfloat64m4_t maskedoff, vfloat64m4_t op1, vfloat64m4_t op2, size_t vl) {
277 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
278 }
279
280 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmax_vf_f64m4_tu
281 // CHECK-RV64-SAME: (<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
282 // CHECK-RV64-NEXT: entry:
283 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmax.nxv4f64.f64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], double [[OP2]], i64 [[VL]])
284 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
285 //
test_vfmax_vf_f64m4_tu(vfloat64m4_t maskedoff,vfloat64m4_t op1,double op2,size_t vl)286 vfloat64m4_t test_vfmax_vf_f64m4_tu(vfloat64m4_t maskedoff, vfloat64m4_t op1, double op2, size_t vl) {
287 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
288 }
289
290 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmax_vv_f64m8_tu
291 // CHECK-RV64-SAME: (<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
292 // CHECK-RV64-NEXT: entry:
293 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmax.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], <vscale x 8 x double> [[OP2]], i64 [[VL]])
294 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
295 //
test_vfmax_vv_f64m8_tu(vfloat64m8_t maskedoff,vfloat64m8_t op1,vfloat64m8_t op2,size_t vl)296 vfloat64m8_t test_vfmax_vv_f64m8_tu(vfloat64m8_t maskedoff, vfloat64m8_t op1, vfloat64m8_t op2, size_t vl) {
297 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
298 }
299
300 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmax_vf_f64m8_tu
301 // CHECK-RV64-SAME: (<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
302 // CHECK-RV64-NEXT: entry:
303 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmax.nxv8f64.f64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], double [[OP2]], i64 [[VL]])
304 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
305 //
test_vfmax_vf_f64m8_tu(vfloat64m8_t maskedoff,vfloat64m8_t op1,double op2,size_t vl)306 vfloat64m8_t test_vfmax_vf_f64m8_tu(vfloat64m8_t maskedoff, vfloat64m8_t op1, double op2, size_t vl) {
307 return __riscv_vfmax_tu(maskedoff, op1, op2, vl);
308 }
309
310 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4_tum
311 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
312 // CHECK-RV64-NEXT: entry:
313 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmax.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], <vscale x 1 x half> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
314 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
315 //
test_vfmax_vv_f16mf4_tum(vbool64_t mask,vfloat16mf4_t maskedoff,vfloat16mf4_t op1,vfloat16mf4_t op2,size_t vl)316 vfloat16mf4_t test_vfmax_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t maskedoff, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
317 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
318 }
319
320 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4_tum
321 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
322 // CHECK-RV64-NEXT: entry:
323 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmax.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], half [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
324 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
325 //
test_vfmax_vf_f16mf4_tum(vbool64_t mask,vfloat16mf4_t maskedoff,vfloat16mf4_t op1,_Float16 op2,size_t vl)326 vfloat16mf4_t test_vfmax_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t maskedoff, vfloat16mf4_t op1, _Float16 op2, size_t vl) {
327 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
328 }
329
330 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2_tum
331 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
332 // CHECK-RV64-NEXT: entry:
333 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmax.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], <vscale x 2 x half> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
334 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
335 //
test_vfmax_vv_f16mf2_tum(vbool32_t mask,vfloat16mf2_t maskedoff,vfloat16mf2_t op1,vfloat16mf2_t op2,size_t vl)336 vfloat16mf2_t test_vfmax_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
337 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
338 }
339
340 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2_tum
341 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
342 // CHECK-RV64-NEXT: entry:
343 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmax.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], half [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
344 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
345 //
test_vfmax_vf_f16mf2_tum(vbool32_t mask,vfloat16mf2_t maskedoff,vfloat16mf2_t op1,_Float16 op2,size_t vl)346 vfloat16mf2_t test_vfmax_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
347 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
348 }
349
350 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1_tum
351 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
352 // CHECK-RV64-NEXT: entry:
353 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmax.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], <vscale x 4 x half> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
354 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
355 //
test_vfmax_vv_f16m1_tum(vbool16_t mask,vfloat16m1_t maskedoff,vfloat16m1_t op1,vfloat16m1_t op2,size_t vl)356 vfloat16m1_t test_vfmax_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t maskedoff, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
357 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
358 }
359
360 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1_tum
361 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
362 // CHECK-RV64-NEXT: entry:
363 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmax.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], half [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
364 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
365 //
test_vfmax_vf_f16m1_tum(vbool16_t mask,vfloat16m1_t maskedoff,vfloat16m1_t op1,_Float16 op2,size_t vl)366 vfloat16m1_t test_vfmax_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t maskedoff, vfloat16m1_t op1, _Float16 op2, size_t vl) {
367 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
368 }
369
370 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2_tum
371 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
372 // CHECK-RV64-NEXT: entry:
373 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmax.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], <vscale x 8 x half> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
374 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
375 //
test_vfmax_vv_f16m2_tum(vbool8_t mask,vfloat16m2_t maskedoff,vfloat16m2_t op1,vfloat16m2_t op2,size_t vl)376 vfloat16m2_t test_vfmax_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t maskedoff, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
377 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
378 }
379
380 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2_tum
381 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
382 // CHECK-RV64-NEXT: entry:
383 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmax.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], half [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
384 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
385 //
test_vfmax_vf_f16m2_tum(vbool8_t mask,vfloat16m2_t maskedoff,vfloat16m2_t op1,_Float16 op2,size_t vl)386 vfloat16m2_t test_vfmax_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t maskedoff, vfloat16m2_t op1, _Float16 op2, size_t vl) {
387 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
388 }
389
390 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4_tum
391 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
392 // CHECK-RV64-NEXT: entry:
393 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmax.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], <vscale x 16 x half> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
394 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
395 //
test_vfmax_vv_f16m4_tum(vbool4_t mask,vfloat16m4_t maskedoff,vfloat16m4_t op1,vfloat16m4_t op2,size_t vl)396 vfloat16m4_t test_vfmax_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t maskedoff, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
397 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
398 }
399
400 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmax_vf_f16m4_tum
401 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
402 // CHECK-RV64-NEXT: entry:
403 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmax.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], half [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
404 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
405 //
test_vfmax_vf_f16m4_tum(vbool4_t mask,vfloat16m4_t maskedoff,vfloat16m4_t op1,_Float16 op2,size_t vl)406 vfloat16m4_t test_vfmax_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t maskedoff, vfloat16m4_t op1, _Float16 op2, size_t vl) {
407 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
408 }
409
410 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmax_vv_f16m8_tum
411 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], <vscale x 32 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
412 // CHECK-RV64-NEXT: entry:
413 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x half> [[OP1]], <vscale x 32 x half> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)
414 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
415 //
test_vfmax_vv_f16m8_tum(vbool2_t mask,vfloat16m8_t maskedoff,vfloat16m8_t op1,vfloat16m8_t op2,size_t vl)416 vfloat16m8_t test_vfmax_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t maskedoff, vfloat16m8_t op1, vfloat16m8_t op2, size_t vl) {
417 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
418 }
419
420 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmax_vf_f16m8_tum
421 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
422 // CHECK-RV64-NEXT: entry:
423 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x half> [[OP1]], half [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2)
424 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
425 //
test_vfmax_vf_f16m8_tum(vbool2_t mask,vfloat16m8_t maskedoff,vfloat16m8_t op1,_Float16 op2,size_t vl)426 vfloat16m8_t test_vfmax_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {
427 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
428 }
429
430 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmax_vv_f32mf2_tum
431 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
432 // CHECK-RV64-NEXT: entry:
433 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmax.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x float> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
434 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
435 //
test_vfmax_vv_f32mf2_tum(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,vfloat32mf2_t op2,size_t vl)436 vfloat32mf2_t test_vfmax_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
437 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
438 }
439
440 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmax_vf_f32mf2_tum
441 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
442 // CHECK-RV64-NEXT: entry:
443 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmax.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], float [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
444 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
445 //
test_vfmax_vf_f32mf2_tum(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,float op2,size_t vl)446 vfloat32mf2_t test_vfmax_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, float op2, size_t vl) {
447 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
448 }
449
450 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmax_vv_f32m1_tum
451 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
452 // CHECK-RV64-NEXT: entry:
453 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmax.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x float> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
454 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
455 //
test_vfmax_vv_f32m1_tum(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,vfloat32m1_t op2,size_t vl)456 vfloat32m1_t test_vfmax_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
457 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
458 }
459
460 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmax_vf_f32m1_tum
461 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
462 // CHECK-RV64-NEXT: entry:
463 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmax.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], float [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
464 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
465 //
test_vfmax_vf_f32m1_tum(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,float op2,size_t vl)466 vfloat32m1_t test_vfmax_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, float op2, size_t vl) {
467 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
468 }
469
470 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmax_vv_f32m2_tum
471 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
472 // CHECK-RV64-NEXT: entry:
473 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmax.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x float> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
474 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
475 //
test_vfmax_vv_f32m2_tum(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,vfloat32m2_t op2,size_t vl)476 vfloat32m2_t test_vfmax_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, vfloat32m2_t op2, size_t vl) {
477 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
478 }
479
480 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmax_vf_f32m2_tum
481 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
482 // CHECK-RV64-NEXT: entry:
483 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmax.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], float [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
484 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
485 //
test_vfmax_vf_f32m2_tum(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,float op2,size_t vl)486 vfloat32m2_t test_vfmax_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, float op2, size_t vl) {
487 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
488 }
489
490 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmax_vv_f32m4_tum
491 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
492 // CHECK-RV64-NEXT: entry:
493 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmax.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x float> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
494 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
495 //
test_vfmax_vv_f32m4_tum(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,vfloat32m4_t op2,size_t vl)496 vfloat32m4_t test_vfmax_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, vfloat32m4_t op2, size_t vl) {
497 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
498 }
499
500 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmax_vf_f32m4_tum
501 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
502 // CHECK-RV64-NEXT: entry:
503 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmax.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], float [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
504 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
505 //
test_vfmax_vf_f32m4_tum(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,float op2,size_t vl)506 vfloat32m4_t test_vfmax_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, float op2, size_t vl) {
507 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
508 }
509
510 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmax_vv_f32m8_tum
511 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
512 // CHECK-RV64-NEXT: entry:
513 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], <vscale x 16 x float> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
514 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
515 //
test_vfmax_vv_f32m8_tum(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,vfloat32m8_t op2,size_t vl)516 vfloat32m8_t test_vfmax_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, vfloat32m8_t op2, size_t vl) {
517 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
518 }
519
520 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmax_vf_f32m8_tum
521 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
522 // CHECK-RV64-NEXT: entry:
523 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], float [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2)
524 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
525 //
test_vfmax_vf_f32m8_tum(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,float op2,size_t vl)526 vfloat32m8_t test_vfmax_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, float op2, size_t vl) {
527 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
528 }
529
530 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmax_vv_f64m1_tum
531 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
532 // CHECK-RV64-NEXT: entry:
533 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmax.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], <vscale x 1 x double> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
534 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
535 //
test_vfmax_vv_f64m1_tum(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,vfloat64m1_t op2,size_t vl)536 vfloat64m1_t test_vfmax_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, vfloat64m1_t op2, size_t vl) {
537 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
538 }
539
540 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmax_vf_f64m1_tum
541 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
542 // CHECK-RV64-NEXT: entry:
543 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmax.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], double [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2)
544 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
545 //
test_vfmax_vf_f64m1_tum(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,double op2,size_t vl)546 vfloat64m1_t test_vfmax_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, double op2, size_t vl) {
547 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
548 }
549
550 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmax_vv_f64m2_tum
551 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
552 // CHECK-RV64-NEXT: entry:
553 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmax.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], <vscale x 2 x double> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
554 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
555 //
test_vfmax_vv_f64m2_tum(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,vfloat64m2_t op2,size_t vl)556 vfloat64m2_t test_vfmax_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, vfloat64m2_t op2, size_t vl) {
557 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
558 }
559
560 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmax_vf_f64m2_tum
561 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
562 // CHECK-RV64-NEXT: entry:
563 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmax.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], double [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2)
564 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
565 //
test_vfmax_vf_f64m2_tum(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,double op2,size_t vl)566 vfloat64m2_t test_vfmax_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, double op2, size_t vl) {
567 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
568 }
569
570 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmax_vv_f64m4_tum
571 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
572 // CHECK-RV64-NEXT: entry:
573 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmax.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], <vscale x 4 x double> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
574 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
575 //
test_vfmax_vv_f64m4_tum(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,vfloat64m4_t op2,size_t vl)576 vfloat64m4_t test_vfmax_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, vfloat64m4_t op2, size_t vl) {
577 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
578 }
579
580 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmax_vf_f64m4_tum
581 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
582 // CHECK-RV64-NEXT: entry:
583 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmax.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], double [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2)
584 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
585 //
test_vfmax_vf_f64m4_tum(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,double op2,size_t vl)586 vfloat64m4_t test_vfmax_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, double op2, size_t vl) {
587 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
588 }
589
590 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmax_vv_f64m8_tum
591 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
592 // CHECK-RV64-NEXT: entry:
593 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmax.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], <vscale x 8 x double> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
594 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
595 //
test_vfmax_vv_f64m8_tum(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,vfloat64m8_t op2,size_t vl)596 vfloat64m8_t test_vfmax_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, vfloat64m8_t op2, size_t vl) {
597 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
598 }
599
600 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmax_vf_f64m8_tum
601 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
602 // CHECK-RV64-NEXT: entry:
603 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmax.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], double [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2)
604 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
605 //
test_vfmax_vf_f64m8_tum(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,double op2,size_t vl)606 vfloat64m8_t test_vfmax_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, double op2, size_t vl) {
607 return __riscv_vfmax_tum(mask, maskedoff, op1, op2, vl);
608 }
609
610 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4_tumu
611 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
612 // CHECK-RV64-NEXT: entry:
613 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmax.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], <vscale x 1 x half> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
614 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
615 //
test_vfmax_vv_f16mf4_tumu(vbool64_t mask,vfloat16mf4_t maskedoff,vfloat16mf4_t op1,vfloat16mf4_t op2,size_t vl)616 vfloat16mf4_t test_vfmax_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t maskedoff, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
617 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
618 }
619
620 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4_tumu
621 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
622 // CHECK-RV64-NEXT: entry:
623 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmax.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], half [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
624 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
625 //
test_vfmax_vf_f16mf4_tumu(vbool64_t mask,vfloat16mf4_t maskedoff,vfloat16mf4_t op1,_Float16 op2,size_t vl)626 vfloat16mf4_t test_vfmax_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t maskedoff, vfloat16mf4_t op1, _Float16 op2, size_t vl) {
627 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
628 }
629
630 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2_tumu
631 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
632 // CHECK-RV64-NEXT: entry:
633 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmax.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], <vscale x 2 x half> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
634 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
635 //
test_vfmax_vv_f16mf2_tumu(vbool32_t mask,vfloat16mf2_t maskedoff,vfloat16mf2_t op1,vfloat16mf2_t op2,size_t vl)636 vfloat16mf2_t test_vfmax_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
637 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
638 }
639
640 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2_tumu
641 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
642 // CHECK-RV64-NEXT: entry:
643 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmax.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], half [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
644 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
645 //
test_vfmax_vf_f16mf2_tumu(vbool32_t mask,vfloat16mf2_t maskedoff,vfloat16mf2_t op1,_Float16 op2,size_t vl)646 vfloat16mf2_t test_vfmax_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
647 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
648 }
649
650 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1_tumu
651 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
652 // CHECK-RV64-NEXT: entry:
653 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmax.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], <vscale x 4 x half> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
654 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
655 //
test_vfmax_vv_f16m1_tumu(vbool16_t mask,vfloat16m1_t maskedoff,vfloat16m1_t op1,vfloat16m1_t op2,size_t vl)656 vfloat16m1_t test_vfmax_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t maskedoff, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
657 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
658 }
659
660 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1_tumu
661 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
662 // CHECK-RV64-NEXT: entry:
663 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmax.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], half [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
664 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
665 //
test_vfmax_vf_f16m1_tumu(vbool16_t mask,vfloat16m1_t maskedoff,vfloat16m1_t op1,_Float16 op2,size_t vl)666 vfloat16m1_t test_vfmax_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t maskedoff, vfloat16m1_t op1, _Float16 op2, size_t vl) {
667 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
668 }
669
670 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2_tumu
671 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
672 // CHECK-RV64-NEXT: entry:
673 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmax.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], <vscale x 8 x half> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
674 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
675 //
test_vfmax_vv_f16m2_tumu(vbool8_t mask,vfloat16m2_t maskedoff,vfloat16m2_t op1,vfloat16m2_t op2,size_t vl)676 vfloat16m2_t test_vfmax_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t maskedoff, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
677 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
678 }
679
680 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2_tumu
681 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
682 // CHECK-RV64-NEXT: entry:
683 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmax.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], half [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
684 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
685 //
test_vfmax_vf_f16m2_tumu(vbool8_t mask,vfloat16m2_t maskedoff,vfloat16m2_t op1,_Float16 op2,size_t vl)686 vfloat16m2_t test_vfmax_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t maskedoff, vfloat16m2_t op1, _Float16 op2, size_t vl) {
687 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
688 }
689
690 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4_tumu
691 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
692 // CHECK-RV64-NEXT: entry:
693 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmax.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], <vscale x 16 x half> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
694 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
695 //
test_vfmax_vv_f16m4_tumu(vbool4_t mask,vfloat16m4_t maskedoff,vfloat16m4_t op1,vfloat16m4_t op2,size_t vl)696 vfloat16m4_t test_vfmax_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t maskedoff, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
697 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
698 }
699
700 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmax_vf_f16m4_tumu
701 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
702 // CHECK-RV64-NEXT: entry:
703 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmax.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], half [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
704 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
705 //
test_vfmax_vf_f16m4_tumu(vbool4_t mask,vfloat16m4_t maskedoff,vfloat16m4_t op1,_Float16 op2,size_t vl)706 vfloat16m4_t test_vfmax_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t maskedoff, vfloat16m4_t op1, _Float16 op2, size_t vl) {
707 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
708 }
709
710 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmax_vv_f16m8_tumu
711 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], <vscale x 32 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
712 // CHECK-RV64-NEXT: entry:
713 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x half> [[OP1]], <vscale x 32 x half> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)
714 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
715 //
test_vfmax_vv_f16m8_tumu(vbool2_t mask,vfloat16m8_t maskedoff,vfloat16m8_t op1,vfloat16m8_t op2,size_t vl)716 vfloat16m8_t test_vfmax_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t maskedoff, vfloat16m8_t op1, vfloat16m8_t op2, size_t vl) {
717 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
718 }
719
720 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmax_vf_f16m8_tumu
721 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
722 // CHECK-RV64-NEXT: entry:
723 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x half> [[OP1]], half [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0)
724 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
725 //
test_vfmax_vf_f16m8_tumu(vbool2_t mask,vfloat16m8_t maskedoff,vfloat16m8_t op1,_Float16 op2,size_t vl)726 vfloat16m8_t test_vfmax_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {
727 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
728 }
729
730 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmax_vv_f32mf2_tumu
731 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
732 // CHECK-RV64-NEXT: entry:
733 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmax.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x float> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
734 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
735 //
test_vfmax_vv_f32mf2_tumu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,vfloat32mf2_t op2,size_t vl)736 vfloat32mf2_t test_vfmax_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
737 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
738 }
739
740 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmax_vf_f32mf2_tumu
741 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
742 // CHECK-RV64-NEXT: entry:
743 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmax.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], float [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
744 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
745 //
test_vfmax_vf_f32mf2_tumu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,float op2,size_t vl)746 vfloat32mf2_t test_vfmax_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, float op2, size_t vl) {
747 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
748 }
749
750 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmax_vv_f32m1_tumu
751 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
752 // CHECK-RV64-NEXT: entry:
753 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmax.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x float> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
754 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
755 //
test_vfmax_vv_f32m1_tumu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,vfloat32m1_t op2,size_t vl)756 vfloat32m1_t test_vfmax_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
757 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
758 }
759
760 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmax_vf_f32m1_tumu
761 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
762 // CHECK-RV64-NEXT: entry:
763 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmax.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], float [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
764 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
765 //
test_vfmax_vf_f32m1_tumu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,float op2,size_t vl)766 vfloat32m1_t test_vfmax_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, float op2, size_t vl) {
767 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
768 }
769
770 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmax_vv_f32m2_tumu
771 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
772 // CHECK-RV64-NEXT: entry:
773 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmax.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x float> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
774 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
775 //
test_vfmax_vv_f32m2_tumu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,vfloat32m2_t op2,size_t vl)776 vfloat32m2_t test_vfmax_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, vfloat32m2_t op2, size_t vl) {
777 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
778 }
779
780 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmax_vf_f32m2_tumu
781 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
782 // CHECK-RV64-NEXT: entry:
783 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmax.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], float [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
784 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
785 //
test_vfmax_vf_f32m2_tumu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,float op2,size_t vl)786 vfloat32m2_t test_vfmax_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, float op2, size_t vl) {
787 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
788 }
789
790 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmax_vv_f32m4_tumu
791 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
792 // CHECK-RV64-NEXT: entry:
793 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmax.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x float> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
794 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
795 //
test_vfmax_vv_f32m4_tumu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,vfloat32m4_t op2,size_t vl)796 vfloat32m4_t test_vfmax_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, vfloat32m4_t op2, size_t vl) {
797 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
798 }
799
800 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmax_vf_f32m4_tumu
801 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
802 // CHECK-RV64-NEXT: entry:
803 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmax.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], float [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
804 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
805 //
test_vfmax_vf_f32m4_tumu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,float op2,size_t vl)806 vfloat32m4_t test_vfmax_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, float op2, size_t vl) {
807 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
808 }
809
810 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmax_vv_f32m8_tumu
811 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
812 // CHECK-RV64-NEXT: entry:
813 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], <vscale x 16 x float> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
814 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
815 //
test_vfmax_vv_f32m8_tumu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,vfloat32m8_t op2,size_t vl)816 vfloat32m8_t test_vfmax_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, vfloat32m8_t op2, size_t vl) {
817 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
818 }
819
820 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmax_vf_f32m8_tumu
821 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
822 // CHECK-RV64-NEXT: entry:
823 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], float [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0)
824 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
825 //
test_vfmax_vf_f32m8_tumu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,float op2,size_t vl)826 vfloat32m8_t test_vfmax_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, float op2, size_t vl) {
827 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
828 }
829
830 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmax_vv_f64m1_tumu
831 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
832 // CHECK-RV64-NEXT: entry:
833 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmax.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], <vscale x 1 x double> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
834 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
835 //
test_vfmax_vv_f64m1_tumu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,vfloat64m1_t op2,size_t vl)836 vfloat64m1_t test_vfmax_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, vfloat64m1_t op2, size_t vl) {
837 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
838 }
839
840 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmax_vf_f64m1_tumu
841 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
842 // CHECK-RV64-NEXT: entry:
843 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmax.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], double [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0)
844 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
845 //
test_vfmax_vf_f64m1_tumu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,double op2,size_t vl)846 vfloat64m1_t test_vfmax_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, double op2, size_t vl) {
847 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
848 }
849
850 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmax_vv_f64m2_tumu
851 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
852 // CHECK-RV64-NEXT: entry:
853 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmax.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], <vscale x 2 x double> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
854 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
855 //
test_vfmax_vv_f64m2_tumu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,vfloat64m2_t op2,size_t vl)856 vfloat64m2_t test_vfmax_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, vfloat64m2_t op2, size_t vl) {
857 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
858 }
859
860 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmax_vf_f64m2_tumu
861 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
862 // CHECK-RV64-NEXT: entry:
863 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmax.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], double [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0)
864 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
865 //
test_vfmax_vf_f64m2_tumu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,double op2,size_t vl)866 vfloat64m2_t test_vfmax_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, double op2, size_t vl) {
867 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
868 }
869
870 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmax_vv_f64m4_tumu
871 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
872 // CHECK-RV64-NEXT: entry:
873 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmax.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], <vscale x 4 x double> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
874 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
875 //
test_vfmax_vv_f64m4_tumu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,vfloat64m4_t op2,size_t vl)876 vfloat64m4_t test_vfmax_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, vfloat64m4_t op2, size_t vl) {
877 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
878 }
879
880 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmax_vf_f64m4_tumu
881 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
882 // CHECK-RV64-NEXT: entry:
883 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmax.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], double [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0)
884 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
885 //
test_vfmax_vf_f64m4_tumu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,double op2,size_t vl)886 vfloat64m4_t test_vfmax_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, double op2, size_t vl) {
887 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
888 }
889
890 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmax_vv_f64m8_tumu
891 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
892 // CHECK-RV64-NEXT: entry:
893 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmax.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], <vscale x 8 x double> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
894 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
895 //
test_vfmax_vv_f64m8_tumu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,vfloat64m8_t op2,size_t vl)896 vfloat64m8_t test_vfmax_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, vfloat64m8_t op2, size_t vl) {
897 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
898 }
899
900 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmax_vf_f64m8_tumu
901 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
902 // CHECK-RV64-NEXT: entry:
903 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmax.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], double [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0)
904 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
905 //
test_vfmax_vf_f64m8_tumu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,double op2,size_t vl)906 vfloat64m8_t test_vfmax_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, double op2, size_t vl) {
907 return __riscv_vfmax_tumu(mask, maskedoff, op1, op2, vl);
908 }
909
910 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4_mu
911 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], <vscale x 1 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
912 // CHECK-RV64-NEXT: entry:
913 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmax.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], <vscale x 1 x half> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
914 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
915 //
test_vfmax_vv_f16mf4_mu(vbool64_t mask,vfloat16mf4_t maskedoff,vfloat16mf4_t op1,vfloat16mf4_t op2,size_t vl)916 vfloat16mf4_t test_vfmax_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t maskedoff, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
917 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
918 }
919
920 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4_mu
921 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
922 // CHECK-RV64-NEXT: entry:
923 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmax.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x half> [[OP1]], half [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
924 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
925 //
test_vfmax_vf_f16mf4_mu(vbool64_t mask,vfloat16mf4_t maskedoff,vfloat16mf4_t op1,_Float16 op2,size_t vl)926 vfloat16mf4_t test_vfmax_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t maskedoff, vfloat16mf4_t op1, _Float16 op2, size_t vl) {
927 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
928 }
929
930 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2_mu
931 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], <vscale x 2 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
932 // CHECK-RV64-NEXT: entry:
933 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmax.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], <vscale x 2 x half> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
934 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
935 //
test_vfmax_vv_f16mf2_mu(vbool32_t mask,vfloat16mf2_t maskedoff,vfloat16mf2_t op1,vfloat16mf2_t op2,size_t vl)936 vfloat16mf2_t test_vfmax_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
937 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
938 }
939
940 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2_mu
941 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
942 // CHECK-RV64-NEXT: entry:
943 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmax.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x half> [[OP1]], half [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
944 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
945 //
test_vfmax_vf_f16mf2_mu(vbool32_t mask,vfloat16mf2_t maskedoff,vfloat16mf2_t op1,_Float16 op2,size_t vl)946 vfloat16mf2_t test_vfmax_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
947 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
948 }
949
950 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1_mu
951 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
952 // CHECK-RV64-NEXT: entry:
953 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmax.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], <vscale x 4 x half> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
954 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
955 //
test_vfmax_vv_f16m1_mu(vbool16_t mask,vfloat16m1_t maskedoff,vfloat16m1_t op1,vfloat16m1_t op2,size_t vl)956 vfloat16m1_t test_vfmax_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t maskedoff, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
957 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
958 }
959
960 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1_mu
961 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
962 // CHECK-RV64-NEXT: entry:
963 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmax.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[OP1]], half [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
964 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
965 //
test_vfmax_vf_f16m1_mu(vbool16_t mask,vfloat16m1_t maskedoff,vfloat16m1_t op1,_Float16 op2,size_t vl)966 vfloat16m1_t test_vfmax_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t maskedoff, vfloat16m1_t op1, _Float16 op2, size_t vl) {
967 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
968 }
969
970 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2_mu
971 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
972 // CHECK-RV64-NEXT: entry:
973 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmax.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], <vscale x 8 x half> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
974 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
975 //
test_vfmax_vv_f16m2_mu(vbool8_t mask,vfloat16m2_t maskedoff,vfloat16m2_t op1,vfloat16m2_t op2,size_t vl)976 vfloat16m2_t test_vfmax_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t maskedoff, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
977 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
978 }
979
980 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2_mu
981 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
982 // CHECK-RV64-NEXT: entry:
983 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmax.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x half> [[OP1]], half [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
984 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
985 //
test_vfmax_vf_f16m2_mu(vbool8_t mask,vfloat16m2_t maskedoff,vfloat16m2_t op1,_Float16 op2,size_t vl)986 vfloat16m2_t test_vfmax_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t maskedoff, vfloat16m2_t op1, _Float16 op2, size_t vl) {
987 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
988 }
989
990 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4_mu
991 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], <vscale x 16 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
992 // CHECK-RV64-NEXT: entry:
993 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmax.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], <vscale x 16 x half> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
994 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
995 //
test_vfmax_vv_f16m4_mu(vbool4_t mask,vfloat16m4_t maskedoff,vfloat16m4_t op1,vfloat16m4_t op2,size_t vl)996 vfloat16m4_t test_vfmax_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t maskedoff, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
997 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
998 }
999
1000 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmax_vf_f16m4_mu
1001 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1002 // CHECK-RV64-NEXT: entry:
1003 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmax.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x half> [[OP1]], half [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
1004 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
1005 //
test_vfmax_vf_f16m4_mu(vbool4_t mask,vfloat16m4_t maskedoff,vfloat16m4_t op1,_Float16 op2,size_t vl)1006 vfloat16m4_t test_vfmax_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t maskedoff, vfloat16m4_t op1, _Float16 op2, size_t vl) {
1007 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1008 }
1009
1010 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmax_vv_f16m8_mu
1011 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], <vscale x 32 x half> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1012 // CHECK-RV64-NEXT: entry:
1013 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x half> [[OP1]], <vscale x 32 x half> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)
1014 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
1015 //
test_vfmax_vv_f16m8_mu(vbool2_t mask,vfloat16m8_t maskedoff,vfloat16m8_t op1,vfloat16m8_t op2,size_t vl)1016 vfloat16m8_t test_vfmax_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t maskedoff, vfloat16m8_t op1, vfloat16m8_t op2, size_t vl) {
1017 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1018 }
1019
1020 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmax_vf_f16m8_mu
1021 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], half noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1022 // CHECK-RV64-NEXT: entry:
1023 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x half> [[OP1]], half [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1)
1024 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
1025 //
test_vfmax_vf_f16m8_mu(vbool2_t mask,vfloat16m8_t maskedoff,vfloat16m8_t op1,_Float16 op2,size_t vl)1026 vfloat16m8_t test_vfmax_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t maskedoff, vfloat16m8_t op1, _Float16 op2, size_t vl) {
1027 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1028 }
1029
1030 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmax_vv_f32mf2_mu
1031 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1032 // CHECK-RV64-NEXT: entry:
1033 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmax.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], <vscale x 1 x float> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
1034 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
1035 //
test_vfmax_vv_f32mf2_mu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,vfloat32mf2_t op2,size_t vl)1036 vfloat32mf2_t test_vfmax_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, vfloat32mf2_t op2, size_t vl) {
1037 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1038 }
1039
1040 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmax_vf_f32mf2_mu
1041 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1042 // CHECK-RV64-NEXT: entry:
1043 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmax.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x float> [[OP1]], float [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
1044 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
1045 //
test_vfmax_vf_f32mf2_mu(vbool64_t mask,vfloat32mf2_t maskedoff,vfloat32mf2_t op1,float op2,size_t vl)1046 vfloat32mf2_t test_vfmax_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vfloat32mf2_t op1, float op2, size_t vl) {
1047 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1048 }
1049
1050 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmax_vv_f32m1_mu
1051 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1052 // CHECK-RV64-NEXT: entry:
1053 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmax.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], <vscale x 2 x float> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
1054 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
1055 //
test_vfmax_vv_f32m1_mu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,vfloat32m1_t op2,size_t vl)1056 vfloat32m1_t test_vfmax_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
1057 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1058 }
1059
1060 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmax_vf_f32m1_mu
1061 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1062 // CHECK-RV64-NEXT: entry:
1063 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmax.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[OP1]], float [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
1064 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
1065 //
test_vfmax_vf_f32m1_mu(vbool32_t mask,vfloat32m1_t maskedoff,vfloat32m1_t op1,float op2,size_t vl)1066 vfloat32m1_t test_vfmax_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, float op2, size_t vl) {
1067 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1068 }
1069
1070 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmax_vv_f32m2_mu
1071 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1072 // CHECK-RV64-NEXT: entry:
1073 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmax.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], <vscale x 4 x float> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
1074 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
1075 //
test_vfmax_vv_f32m2_mu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,vfloat32m2_t op2,size_t vl)1076 vfloat32m2_t test_vfmax_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, vfloat32m2_t op2, size_t vl) {
1077 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1078 }
1079
1080 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmax_vf_f32m2_mu
1081 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1082 // CHECK-RV64-NEXT: entry:
1083 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmax.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x float> [[OP1]], float [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
1084 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
1085 //
test_vfmax_vf_f32m2_mu(vbool16_t mask,vfloat32m2_t maskedoff,vfloat32m2_t op1,float op2,size_t vl)1086 vfloat32m2_t test_vfmax_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t maskedoff, vfloat32m2_t op1, float op2, size_t vl) {
1087 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1088 }
1089
1090 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmax_vv_f32m4_mu
1091 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1092 // CHECK-RV64-NEXT: entry:
1093 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmax.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], <vscale x 8 x float> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
1094 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
1095 //
test_vfmax_vv_f32m4_mu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,vfloat32m4_t op2,size_t vl)1096 vfloat32m4_t test_vfmax_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, vfloat32m4_t op2, size_t vl) {
1097 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1098 }
1099
1100 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmax_vf_f32m4_mu
1101 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1102 // CHECK-RV64-NEXT: entry:
1103 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmax.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x float> [[OP1]], float [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
1104 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
1105 //
test_vfmax_vf_f32m4_mu(vbool8_t mask,vfloat32m4_t maskedoff,vfloat32m4_t op1,float op2,size_t vl)1106 vfloat32m4_t test_vfmax_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t maskedoff, vfloat32m4_t op1, float op2, size_t vl) {
1107 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1108 }
1109
1110 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmax_vv_f32m8_mu
1111 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x float> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1112 // CHECK-RV64-NEXT: entry:
1113 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], <vscale x 16 x float> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
1114 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
1115 //
test_vfmax_vv_f32m8_mu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,vfloat32m8_t op2,size_t vl)1116 vfloat32m8_t test_vfmax_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, vfloat32m8_t op2, size_t vl) {
1117 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1118 }
1119
1120 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmax_vf_f32m8_mu
1121 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], float noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1122 // CHECK-RV64-NEXT: entry:
1123 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x float> [[OP1]], float [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1)
1124 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
1125 //
test_vfmax_vf_f32m8_mu(vbool4_t mask,vfloat32m8_t maskedoff,vfloat32m8_t op1,float op2,size_t vl)1126 vfloat32m8_t test_vfmax_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t maskedoff, vfloat32m8_t op1, float op2, size_t vl) {
1127 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1128 }
1129
1130 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmax_vv_f64m1_mu
1131 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1132 // CHECK-RV64-NEXT: entry:
1133 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmax.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], <vscale x 1 x double> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
1134 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
1135 //
test_vfmax_vv_f64m1_mu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,vfloat64m1_t op2,size_t vl)1136 vfloat64m1_t test_vfmax_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, vfloat64m1_t op2, size_t vl) {
1137 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1138 }
1139
1140 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmax_vf_f64m1_mu
1141 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1142 // CHECK-RV64-NEXT: entry:
1143 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmax.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[OP1]], double [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1)
1144 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
1145 //
test_vfmax_vf_f64m1_mu(vbool64_t mask,vfloat64m1_t maskedoff,vfloat64m1_t op1,double op2,size_t vl)1146 vfloat64m1_t test_vfmax_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t op1, double op2, size_t vl) {
1147 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1148 }
1149
1150 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmax_vv_f64m2_mu
1151 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1152 // CHECK-RV64-NEXT: entry:
1153 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmax.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], <vscale x 2 x double> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
1154 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
1155 //
test_vfmax_vv_f64m2_mu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,vfloat64m2_t op2,size_t vl)1156 vfloat64m2_t test_vfmax_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, vfloat64m2_t op2, size_t vl) {
1157 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1158 }
1159
1160 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmax_vf_f64m2_mu
1161 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1162 // CHECK-RV64-NEXT: entry:
1163 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmax.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x double> [[OP1]], double [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1)
1164 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
1165 //
test_vfmax_vf_f64m2_mu(vbool32_t mask,vfloat64m2_t maskedoff,vfloat64m2_t op1,double op2,size_t vl)1166 vfloat64m2_t test_vfmax_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t maskedoff, vfloat64m2_t op1, double op2, size_t vl) {
1167 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1168 }
1169
1170 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmax_vv_f64m4_mu
1171 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1172 // CHECK-RV64-NEXT: entry:
1173 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmax.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], <vscale x 4 x double> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
1174 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1175 //
test_vfmax_vv_f64m4_mu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,vfloat64m4_t op2,size_t vl)1176 vfloat64m4_t test_vfmax_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, vfloat64m4_t op2, size_t vl) {
1177 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1178 }
1179
1180 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmax_vf_f64m4_mu
1181 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1182 // CHECK-RV64-NEXT: entry:
1183 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmax.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x double> [[OP1]], double [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1)
1184 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1185 //
test_vfmax_vf_f64m4_mu(vbool16_t mask,vfloat64m4_t maskedoff,vfloat64m4_t op1,double op2,size_t vl)1186 vfloat64m4_t test_vfmax_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t maskedoff, vfloat64m4_t op1, double op2, size_t vl) {
1187 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1188 }
1189
1190 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmax_vv_f64m8_mu
1191 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x double> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1192 // CHECK-RV64-NEXT: entry:
1193 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmax.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], <vscale x 8 x double> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
1194 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1195 //
test_vfmax_vv_f64m8_mu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,vfloat64m8_t op2,size_t vl)1196 vfloat64m8_t test_vfmax_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, vfloat64m8_t op2, size_t vl) {
1197 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1198 }
1199
1200 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmax_vf_f64m8_mu
1201 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], double noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1202 // CHECK-RV64-NEXT: entry:
1203 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmax.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x double> [[OP1]], double [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1)
1204 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1205 //
test_vfmax_vf_f64m8_mu(vbool8_t mask,vfloat64m8_t maskedoff,vfloat64m8_t op1,double op2,size_t vl)1206 vfloat64m8_t test_vfmax_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t op1, double op2, size_t vl) {
1207 return __riscv_vfmax_mu(mask, maskedoff, op1, op2, vl);
1208 }
1209
1210