1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4 // RUN: -target-feature +zvfh -disable-O0-optnone \
5 // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
6 // RUN: FileCheck --check-prefix=CHECK-RV64 %s
7
8 #include <riscv_vector.h>
9
10 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_tu
11 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
12 // CHECK-RV64-NEXT: entry:
13 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], i64 7, i64 [[VL]])
14 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
15 //
test_vfcvt_x_f_v_i16mf4_tu(vint16mf4_t maskedoff,vfloat16mf4_t src,size_t vl)16 vint16mf4_t test_vfcvt_x_f_v_i16mf4_tu(vint16mf4_t maskedoff, vfloat16mf4_t src, size_t vl) {
17 return __riscv_vfcvt_x_tu(maskedoff, src, vl);
18 }
19
20 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_tu
21 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
22 // CHECK-RV64-NEXT: entry:
23 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], i64 7, i64 [[VL]])
24 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
25 //
test_vfcvt_x_f_v_i16mf2_tu(vint16mf2_t maskedoff,vfloat16mf2_t src,size_t vl)26 vint16mf2_t test_vfcvt_x_f_v_i16mf2_tu(vint16mf2_t maskedoff, vfloat16mf2_t src, size_t vl) {
27 return __riscv_vfcvt_x_tu(maskedoff, src, vl);
28 }
29
30 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_tu
31 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
32 // CHECK-RV64-NEXT: entry:
33 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], i64 7, i64 [[VL]])
34 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
35 //
test_vfcvt_x_f_v_i16m1_tu(vint16m1_t maskedoff,vfloat16m1_t src,size_t vl)36 vint16m1_t test_vfcvt_x_f_v_i16m1_tu(vint16m1_t maskedoff, vfloat16m1_t src, size_t vl) {
37 return __riscv_vfcvt_x_tu(maskedoff, src, vl);
38 }
39
40 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_tu
41 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
42 // CHECK-RV64-NEXT: entry:
43 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], i64 7, i64 [[VL]])
44 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
45 //
test_vfcvt_x_f_v_i16m2_tu(vint16m2_t maskedoff,vfloat16m2_t src,size_t vl)46 vint16m2_t test_vfcvt_x_f_v_i16m2_tu(vint16m2_t maskedoff, vfloat16m2_t src, size_t vl) {
47 return __riscv_vfcvt_x_tu(maskedoff, src, vl);
48 }
49
50 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_tu
51 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
52 // CHECK-RV64-NEXT: entry:
53 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], i64 7, i64 [[VL]])
54 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
55 //
test_vfcvt_x_f_v_i16m4_tu(vint16m4_t maskedoff,vfloat16m4_t src,size_t vl)56 vint16m4_t test_vfcvt_x_f_v_i16m4_tu(vint16m4_t maskedoff, vfloat16m4_t src, size_t vl) {
57 return __riscv_vfcvt_x_tu(maskedoff, src, vl);
58 }
59
60 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_tu
61 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
62 // CHECK-RV64-NEXT: entry:
63 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], i64 7, i64 [[VL]])
64 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
65 //
test_vfcvt_x_f_v_i16m8_tu(vint16m8_t maskedoff,vfloat16m8_t src,size_t vl)66 vint16m8_t test_vfcvt_x_f_v_i16m8_tu(vint16m8_t maskedoff, vfloat16m8_t src, size_t vl) {
67 return __riscv_vfcvt_x_tu(maskedoff, src, vl);
68 }
69
70 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_tu
71 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
72 // CHECK-RV64-NEXT: entry:
73 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], i64 7, i64 [[VL]])
74 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
75 //
test_vfcvt_xu_f_v_u16mf4_tu(vuint16mf4_t maskedoff,vfloat16mf4_t src,size_t vl)76 vuint16mf4_t test_vfcvt_xu_f_v_u16mf4_tu(vuint16mf4_t maskedoff, vfloat16mf4_t src, size_t vl) {
77 return __riscv_vfcvt_xu_tu(maskedoff, src, vl);
78 }
79
80 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_tu
81 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
82 // CHECK-RV64-NEXT: entry:
83 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], i64 7, i64 [[VL]])
84 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
85 //
test_vfcvt_xu_f_v_u16mf2_tu(vuint16mf2_t maskedoff,vfloat16mf2_t src,size_t vl)86 vuint16mf2_t test_vfcvt_xu_f_v_u16mf2_tu(vuint16mf2_t maskedoff, vfloat16mf2_t src, size_t vl) {
87 return __riscv_vfcvt_xu_tu(maskedoff, src, vl);
88 }
89
90 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_tu
91 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
92 // CHECK-RV64-NEXT: entry:
93 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], i64 7, i64 [[VL]])
94 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
95 //
test_vfcvt_xu_f_v_u16m1_tu(vuint16m1_t maskedoff,vfloat16m1_t src,size_t vl)96 vuint16m1_t test_vfcvt_xu_f_v_u16m1_tu(vuint16m1_t maskedoff, vfloat16m1_t src, size_t vl) {
97 return __riscv_vfcvt_xu_tu(maskedoff, src, vl);
98 }
99
100 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_tu
101 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
102 // CHECK-RV64-NEXT: entry:
103 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], i64 7, i64 [[VL]])
104 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
105 //
test_vfcvt_xu_f_v_u16m2_tu(vuint16m2_t maskedoff,vfloat16m2_t src,size_t vl)106 vuint16m2_t test_vfcvt_xu_f_v_u16m2_tu(vuint16m2_t maskedoff, vfloat16m2_t src, size_t vl) {
107 return __riscv_vfcvt_xu_tu(maskedoff, src, vl);
108 }
109
110 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4_tu
111 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
112 // CHECK-RV64-NEXT: entry:
113 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], i64 7, i64 [[VL]])
114 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
115 //
test_vfcvt_xu_f_v_u16m4_tu(vuint16m4_t maskedoff,vfloat16m4_t src,size_t vl)116 vuint16m4_t test_vfcvt_xu_f_v_u16m4_tu(vuint16m4_t maskedoff, vfloat16m4_t src, size_t vl) {
117 return __riscv_vfcvt_xu_tu(maskedoff, src, vl);
118 }
119
120 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8_tu
121 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
122 // CHECK-RV64-NEXT: entry:
123 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], i64 7, i64 [[VL]])
124 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
125 //
test_vfcvt_xu_f_v_u16m8_tu(vuint16m8_t maskedoff,vfloat16m8_t src,size_t vl)126 vuint16m8_t test_vfcvt_xu_f_v_u16m8_tu(vuint16m8_t maskedoff, vfloat16m8_t src, size_t vl) {
127 return __riscv_vfcvt_xu_tu(maskedoff, src, vl);
128 }
129
130 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_x_v_f16mf4_tu
131 // CHECK-RV64-SAME: (<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
132 // CHECK-RV64-NEXT: entry:
133 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], i64 7, i64 [[VL]])
134 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
135 //
test_vfcvt_f_x_v_f16mf4_tu(vfloat16mf4_t maskedoff,vint16mf4_t src,size_t vl)136 vfloat16mf4_t test_vfcvt_f_x_v_f16mf4_tu(vfloat16mf4_t maskedoff, vint16mf4_t src, size_t vl) {
137 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
138 }
139
140 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_x_v_f16mf2_tu
141 // CHECK-RV64-SAME: (<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
142 // CHECK-RV64-NEXT: entry:
143 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], i64 7, i64 [[VL]])
144 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
145 //
test_vfcvt_f_x_v_f16mf2_tu(vfloat16mf2_t maskedoff,vint16mf2_t src,size_t vl)146 vfloat16mf2_t test_vfcvt_f_x_v_f16mf2_tu(vfloat16mf2_t maskedoff, vint16mf2_t src, size_t vl) {
147 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
148 }
149
150 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_x_v_f16m1_tu
151 // CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
152 // CHECK-RV64-NEXT: entry:
153 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], i64 7, i64 [[VL]])
154 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
155 //
test_vfcvt_f_x_v_f16m1_tu(vfloat16m1_t maskedoff,vint16m1_t src,size_t vl)156 vfloat16m1_t test_vfcvt_f_x_v_f16m1_tu(vfloat16m1_t maskedoff, vint16m1_t src, size_t vl) {
157 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
158 }
159
160 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_x_v_f16m2_tu
161 // CHECK-RV64-SAME: (<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
162 // CHECK-RV64-NEXT: entry:
163 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], i64 7, i64 [[VL]])
164 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
165 //
test_vfcvt_f_x_v_f16m2_tu(vfloat16m2_t maskedoff,vint16m2_t src,size_t vl)166 vfloat16m2_t test_vfcvt_f_x_v_f16m2_tu(vfloat16m2_t maskedoff, vint16m2_t src, size_t vl) {
167 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
168 }
169
170 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_x_v_f16m4_tu
171 // CHECK-RV64-SAME: (<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
172 // CHECK-RV64-NEXT: entry:
173 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], i64 7, i64 [[VL]])
174 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
175 //
test_vfcvt_f_x_v_f16m4_tu(vfloat16m4_t maskedoff,vint16m4_t src,size_t vl)176 vfloat16m4_t test_vfcvt_f_x_v_f16m4_tu(vfloat16m4_t maskedoff, vint16m4_t src, size_t vl) {
177 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
178 }
179
180 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_x_v_f16m8_tu
181 // CHECK-RV64-SAME: (<vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
182 // CHECK-RV64-NEXT: entry:
183 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i16> [[SRC]], i64 7, i64 [[VL]])
184 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
185 //
test_vfcvt_f_x_v_f16m8_tu(vfloat16m8_t maskedoff,vint16m8_t src,size_t vl)186 vfloat16m8_t test_vfcvt_f_x_v_f16m8_tu(vfloat16m8_t maskedoff, vint16m8_t src, size_t vl) {
187 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
188 }
189
190 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_xu_v_f16mf4_tu
191 // CHECK-RV64-SAME: (<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
192 // CHECK-RV64-NEXT: entry:
193 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], i64 7, i64 [[VL]])
194 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
195 //
test_vfcvt_f_xu_v_f16mf4_tu(vfloat16mf4_t maskedoff,vuint16mf4_t src,size_t vl)196 vfloat16mf4_t test_vfcvt_f_xu_v_f16mf4_tu(vfloat16mf4_t maskedoff, vuint16mf4_t src, size_t vl) {
197 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
198 }
199
200 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_xu_v_f16mf2_tu
201 // CHECK-RV64-SAME: (<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
202 // CHECK-RV64-NEXT: entry:
203 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], i64 7, i64 [[VL]])
204 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
205 //
test_vfcvt_f_xu_v_f16mf2_tu(vfloat16mf2_t maskedoff,vuint16mf2_t src,size_t vl)206 vfloat16mf2_t test_vfcvt_f_xu_v_f16mf2_tu(vfloat16mf2_t maskedoff, vuint16mf2_t src, size_t vl) {
207 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
208 }
209
210 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_xu_v_f16m1_tu
211 // CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
212 // CHECK-RV64-NEXT: entry:
213 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], i64 7, i64 [[VL]])
214 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
215 //
test_vfcvt_f_xu_v_f16m1_tu(vfloat16m1_t maskedoff,vuint16m1_t src,size_t vl)216 vfloat16m1_t test_vfcvt_f_xu_v_f16m1_tu(vfloat16m1_t maskedoff, vuint16m1_t src, size_t vl) {
217 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
218 }
219
220 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_xu_v_f16m2_tu
221 // CHECK-RV64-SAME: (<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
222 // CHECK-RV64-NEXT: entry:
223 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], i64 7, i64 [[VL]])
224 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
225 //
test_vfcvt_f_xu_v_f16m2_tu(vfloat16m2_t maskedoff,vuint16m2_t src,size_t vl)226 vfloat16m2_t test_vfcvt_f_xu_v_f16m2_tu(vfloat16m2_t maskedoff, vuint16m2_t src, size_t vl) {
227 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
228 }
229
230 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_xu_v_f16m4_tu
231 // CHECK-RV64-SAME: (<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
232 // CHECK-RV64-NEXT: entry:
233 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], i64 7, i64 [[VL]])
234 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
235 //
test_vfcvt_f_xu_v_f16m4_tu(vfloat16m4_t maskedoff,vuint16m4_t src,size_t vl)236 vfloat16m4_t test_vfcvt_f_xu_v_f16m4_tu(vfloat16m4_t maskedoff, vuint16m4_t src, size_t vl) {
237 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
238 }
239
240 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_xu_v_f16m8_tu
241 // CHECK-RV64-SAME: (<vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
242 // CHECK-RV64-NEXT: entry:
243 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i16> [[SRC]], i64 7, i64 [[VL]])
244 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
245 //
test_vfcvt_f_xu_v_f16m8_tu(vfloat16m8_t maskedoff,vuint16m8_t src,size_t vl)246 vfloat16m8_t test_vfcvt_f_xu_v_f16m8_tu(vfloat16m8_t maskedoff, vuint16m8_t src, size_t vl) {
247 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
248 }
249
250 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_x_f_v_i32mf2_tu
251 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
252 // CHECK-RV64-NEXT: entry:
253 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], i64 7, i64 [[VL]])
254 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
255 //
test_vfcvt_x_f_v_i32mf2_tu(vint32mf2_t maskedoff,vfloat32mf2_t src,size_t vl)256 vint32mf2_t test_vfcvt_x_f_v_i32mf2_tu(vint32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
257 return __riscv_vfcvt_x_tu(maskedoff, src, vl);
258 }
259
260 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_x_f_v_i32m1_tu
261 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
262 // CHECK-RV64-NEXT: entry:
263 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], i64 7, i64 [[VL]])
264 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
265 //
test_vfcvt_x_f_v_i32m1_tu(vint32m1_t maskedoff,vfloat32m1_t src,size_t vl)266 vint32m1_t test_vfcvt_x_f_v_i32m1_tu(vint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
267 return __riscv_vfcvt_x_tu(maskedoff, src, vl);
268 }
269
270 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_x_f_v_i32m2_tu
271 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
272 // CHECK-RV64-NEXT: entry:
273 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], i64 7, i64 [[VL]])
274 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
275 //
test_vfcvt_x_f_v_i32m2_tu(vint32m2_t maskedoff,vfloat32m2_t src,size_t vl)276 vint32m2_t test_vfcvt_x_f_v_i32m2_tu(vint32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
277 return __riscv_vfcvt_x_tu(maskedoff, src, vl);
278 }
279
280 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_x_f_v_i32m4_tu
281 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
282 // CHECK-RV64-NEXT: entry:
283 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], i64 7, i64 [[VL]])
284 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
285 //
test_vfcvt_x_f_v_i32m4_tu(vint32m4_t maskedoff,vfloat32m4_t src,size_t vl)286 vint32m4_t test_vfcvt_x_f_v_i32m4_tu(vint32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
287 return __riscv_vfcvt_x_tu(maskedoff, src, vl);
288 }
289
290 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_x_f_v_i32m8_tu
291 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
292 // CHECK-RV64-NEXT: entry:
293 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], i64 7, i64 [[VL]])
294 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
295 //
test_vfcvt_x_f_v_i32m8_tu(vint32m8_t maskedoff,vfloat32m8_t src,size_t vl)296 vint32m8_t test_vfcvt_x_f_v_i32m8_tu(vint32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
297 return __riscv_vfcvt_x_tu(maskedoff, src, vl);
298 }
299
300 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_xu_f_v_u32mf2_tu
301 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
302 // CHECK-RV64-NEXT: entry:
303 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], i64 7, i64 [[VL]])
304 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
305 //
test_vfcvt_xu_f_v_u32mf2_tu(vuint32mf2_t maskedoff,vfloat32mf2_t src,size_t vl)306 vuint32mf2_t test_vfcvt_xu_f_v_u32mf2_tu(vuint32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
307 return __riscv_vfcvt_xu_tu(maskedoff, src, vl);
308 }
309
310 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_xu_f_v_u32m1_tu
311 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
312 // CHECK-RV64-NEXT: entry:
313 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], i64 7, i64 [[VL]])
314 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
315 //
test_vfcvt_xu_f_v_u32m1_tu(vuint32m1_t maskedoff,vfloat32m1_t src,size_t vl)316 vuint32m1_t test_vfcvt_xu_f_v_u32m1_tu(vuint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
317 return __riscv_vfcvt_xu_tu(maskedoff, src, vl);
318 }
319
320 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_xu_f_v_u32m2_tu
321 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
322 // CHECK-RV64-NEXT: entry:
323 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], i64 7, i64 [[VL]])
324 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
325 //
test_vfcvt_xu_f_v_u32m2_tu(vuint32m2_t maskedoff,vfloat32m2_t src,size_t vl)326 vuint32m2_t test_vfcvt_xu_f_v_u32m2_tu(vuint32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
327 return __riscv_vfcvt_xu_tu(maskedoff, src, vl);
328 }
329
330 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_xu_f_v_u32m4_tu
331 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
332 // CHECK-RV64-NEXT: entry:
333 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], i64 7, i64 [[VL]])
334 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
335 //
test_vfcvt_xu_f_v_u32m4_tu(vuint32m4_t maskedoff,vfloat32m4_t src,size_t vl)336 vuint32m4_t test_vfcvt_xu_f_v_u32m4_tu(vuint32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
337 return __riscv_vfcvt_xu_tu(maskedoff, src, vl);
338 }
339
340 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_xu_f_v_u32m8_tu
341 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
342 // CHECK-RV64-NEXT: entry:
343 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], i64 7, i64 [[VL]])
344 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
345 //
test_vfcvt_xu_f_v_u32m8_tu(vuint32m8_t maskedoff,vfloat32m8_t src,size_t vl)346 vuint32m8_t test_vfcvt_xu_f_v_u32m8_tu(vuint32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
347 return __riscv_vfcvt_xu_tu(maskedoff, src, vl);
348 }
349
350 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_x_v_f32mf2_tu
351 // CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
352 // CHECK-RV64-NEXT: entry:
353 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], i64 7, i64 [[VL]])
354 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
355 //
test_vfcvt_f_x_v_f32mf2_tu(vfloat32mf2_t maskedoff,vint32mf2_t src,size_t vl)356 vfloat32mf2_t test_vfcvt_f_x_v_f32mf2_tu(vfloat32mf2_t maskedoff, vint32mf2_t src, size_t vl) {
357 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
358 }
359
360 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_x_v_f32m1_tu
361 // CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
362 // CHECK-RV64-NEXT: entry:
363 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], i64 7, i64 [[VL]])
364 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
365 //
test_vfcvt_f_x_v_f32m1_tu(vfloat32m1_t maskedoff,vint32m1_t src,size_t vl)366 vfloat32m1_t test_vfcvt_f_x_v_f32m1_tu(vfloat32m1_t maskedoff, vint32m1_t src, size_t vl) {
367 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
368 }
369
370 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_x_v_f32m2_tu
371 // CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
372 // CHECK-RV64-NEXT: entry:
373 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], i64 7, i64 [[VL]])
374 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
375 //
test_vfcvt_f_x_v_f32m2_tu(vfloat32m2_t maskedoff,vint32m2_t src,size_t vl)376 vfloat32m2_t test_vfcvt_f_x_v_f32m2_tu(vfloat32m2_t maskedoff, vint32m2_t src, size_t vl) {
377 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
378 }
379
380 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_x_v_f32m4_tu
381 // CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
382 // CHECK-RV64-NEXT: entry:
383 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], i64 7, i64 [[VL]])
384 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
385 //
test_vfcvt_f_x_v_f32m4_tu(vfloat32m4_t maskedoff,vint32m4_t src,size_t vl)386 vfloat32m4_t test_vfcvt_f_x_v_f32m4_tu(vfloat32m4_t maskedoff, vint32m4_t src, size_t vl) {
387 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
388 }
389
390 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_x_v_f32m8_tu
391 // CHECK-RV64-SAME: (<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
392 // CHECK-RV64-NEXT: entry:
393 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], i64 7, i64 [[VL]])
394 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
395 //
test_vfcvt_f_x_v_f32m8_tu(vfloat32m8_t maskedoff,vint32m8_t src,size_t vl)396 vfloat32m8_t test_vfcvt_f_x_v_f32m8_tu(vfloat32m8_t maskedoff, vint32m8_t src, size_t vl) {
397 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
398 }
399
400 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_xu_v_f32mf2_tu
401 // CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
402 // CHECK-RV64-NEXT: entry:
403 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], i64 7, i64 [[VL]])
404 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
405 //
test_vfcvt_f_xu_v_f32mf2_tu(vfloat32mf2_t maskedoff,vuint32mf2_t src,size_t vl)406 vfloat32mf2_t test_vfcvt_f_xu_v_f32mf2_tu(vfloat32mf2_t maskedoff, vuint32mf2_t src, size_t vl) {
407 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
408 }
409
410 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_xu_v_f32m1_tu
411 // CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
412 // CHECK-RV64-NEXT: entry:
413 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], i64 7, i64 [[VL]])
414 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
415 //
test_vfcvt_f_xu_v_f32m1_tu(vfloat32m1_t maskedoff,vuint32m1_t src,size_t vl)416 vfloat32m1_t test_vfcvt_f_xu_v_f32m1_tu(vfloat32m1_t maskedoff, vuint32m1_t src, size_t vl) {
417 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
418 }
419
420 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_xu_v_f32m2_tu
421 // CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
422 // CHECK-RV64-NEXT: entry:
423 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], i64 7, i64 [[VL]])
424 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
425 //
test_vfcvt_f_xu_v_f32m2_tu(vfloat32m2_t maskedoff,vuint32m2_t src,size_t vl)426 vfloat32m2_t test_vfcvt_f_xu_v_f32m2_tu(vfloat32m2_t maskedoff, vuint32m2_t src, size_t vl) {
427 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
428 }
429
430 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_xu_v_f32m4_tu
431 // CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
432 // CHECK-RV64-NEXT: entry:
433 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], i64 7, i64 [[VL]])
434 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
435 //
test_vfcvt_f_xu_v_f32m4_tu(vfloat32m4_t maskedoff,vuint32m4_t src,size_t vl)436 vfloat32m4_t test_vfcvt_f_xu_v_f32m4_tu(vfloat32m4_t maskedoff, vuint32m4_t src, size_t vl) {
437 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
438 }
439
440 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_xu_v_f32m8_tu
441 // CHECK-RV64-SAME: (<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
442 // CHECK-RV64-NEXT: entry:
443 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], i64 7, i64 [[VL]])
444 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
445 //
test_vfcvt_f_xu_v_f32m8_tu(vfloat32m8_t maskedoff,vuint32m8_t src,size_t vl)446 vfloat32m8_t test_vfcvt_f_xu_v_f32m8_tu(vfloat32m8_t maskedoff, vuint32m8_t src, size_t vl) {
447 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
448 }
449
450 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_x_f_v_i64m1_tu
451 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
452 // CHECK-RV64-NEXT: entry:
453 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], i64 7, i64 [[VL]])
454 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
455 //
test_vfcvt_x_f_v_i64m1_tu(vint64m1_t maskedoff,vfloat64m1_t src,size_t vl)456 vint64m1_t test_vfcvt_x_f_v_i64m1_tu(vint64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
457 return __riscv_vfcvt_x_tu(maskedoff, src, vl);
458 }
459
460 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_x_f_v_i64m2_tu
461 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
462 // CHECK-RV64-NEXT: entry:
463 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], i64 7, i64 [[VL]])
464 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
465 //
test_vfcvt_x_f_v_i64m2_tu(vint64m2_t maskedoff,vfloat64m2_t src,size_t vl)466 vint64m2_t test_vfcvt_x_f_v_i64m2_tu(vint64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
467 return __riscv_vfcvt_x_tu(maskedoff, src, vl);
468 }
469
470 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_x_f_v_i64m4_tu
471 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
472 // CHECK-RV64-NEXT: entry:
473 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], i64 7, i64 [[VL]])
474 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
475 //
test_vfcvt_x_f_v_i64m4_tu(vint64m4_t maskedoff,vfloat64m4_t src,size_t vl)476 vint64m4_t test_vfcvt_x_f_v_i64m4_tu(vint64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
477 return __riscv_vfcvt_x_tu(maskedoff, src, vl);
478 }
479
480 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_x_f_v_i64m8_tu
481 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
482 // CHECK-RV64-NEXT: entry:
483 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], i64 7, i64 [[VL]])
484 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
485 //
test_vfcvt_x_f_v_i64m8_tu(vint64m8_t maskedoff,vfloat64m8_t src,size_t vl)486 vint64m8_t test_vfcvt_x_f_v_i64m8_tu(vint64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
487 return __riscv_vfcvt_x_tu(maskedoff, src, vl);
488 }
489
490 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_xu_f_v_u64m1_tu
491 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
492 // CHECK-RV64-NEXT: entry:
493 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], i64 7, i64 [[VL]])
494 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
495 //
test_vfcvt_xu_f_v_u64m1_tu(vuint64m1_t maskedoff,vfloat64m1_t src,size_t vl)496 vuint64m1_t test_vfcvt_xu_f_v_u64m1_tu(vuint64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
497 return __riscv_vfcvt_xu_tu(maskedoff, src, vl);
498 }
499
500 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_xu_f_v_u64m2_tu
501 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
502 // CHECK-RV64-NEXT: entry:
503 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], i64 7, i64 [[VL]])
504 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
505 //
test_vfcvt_xu_f_v_u64m2_tu(vuint64m2_t maskedoff,vfloat64m2_t src,size_t vl)506 vuint64m2_t test_vfcvt_xu_f_v_u64m2_tu(vuint64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
507 return __riscv_vfcvt_xu_tu(maskedoff, src, vl);
508 }
509
510 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_xu_f_v_u64m4_tu
511 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
512 // CHECK-RV64-NEXT: entry:
513 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], i64 7, i64 [[VL]])
514 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
515 //
test_vfcvt_xu_f_v_u64m4_tu(vuint64m4_t maskedoff,vfloat64m4_t src,size_t vl)516 vuint64m4_t test_vfcvt_xu_f_v_u64m4_tu(vuint64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
517 return __riscv_vfcvt_xu_tu(maskedoff, src, vl);
518 }
519
520 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_xu_f_v_u64m8_tu
521 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
522 // CHECK-RV64-NEXT: entry:
523 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], i64 7, i64 [[VL]])
524 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
525 //
test_vfcvt_xu_f_v_u64m8_tu(vuint64m8_t maskedoff,vfloat64m8_t src,size_t vl)526 vuint64m8_t test_vfcvt_xu_f_v_u64m8_tu(vuint64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
527 return __riscv_vfcvt_xu_tu(maskedoff, src, vl);
528 }
529
530 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_x_v_f64m1_tu
531 // CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
532 // CHECK-RV64-NEXT: entry:
533 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.nxv1f64.nxv1i64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], i64 7, i64 [[VL]])
534 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
535 //
test_vfcvt_f_x_v_f64m1_tu(vfloat64m1_t maskedoff,vint64m1_t src,size_t vl)536 vfloat64m1_t test_vfcvt_f_x_v_f64m1_tu(vfloat64m1_t maskedoff, vint64m1_t src, size_t vl) {
537 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
538 }
539
540 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_x_v_f64m2_tu
541 // CHECK-RV64-SAME: (<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
542 // CHECK-RV64-NEXT: entry:
543 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.nxv2f64.nxv2i64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], i64 7, i64 [[VL]])
544 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
545 //
test_vfcvt_f_x_v_f64m2_tu(vfloat64m2_t maskedoff,vint64m2_t src,size_t vl)546 vfloat64m2_t test_vfcvt_f_x_v_f64m2_tu(vfloat64m2_t maskedoff, vint64m2_t src, size_t vl) {
547 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
548 }
549
550 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_x_v_f64m4_tu
551 // CHECK-RV64-SAME: (<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
552 // CHECK-RV64-NEXT: entry:
553 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.nxv4f64.nxv4i64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], i64 7, i64 [[VL]])
554 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
555 //
test_vfcvt_f_x_v_f64m4_tu(vfloat64m4_t maskedoff,vint64m4_t src,size_t vl)556 vfloat64m4_t test_vfcvt_f_x_v_f64m4_tu(vfloat64m4_t maskedoff, vint64m4_t src, size_t vl) {
557 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
558 }
559
560 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_x_v_f64m8_tu
561 // CHECK-RV64-SAME: (<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
562 // CHECK-RV64-NEXT: entry:
563 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.nxv8f64.nxv8i64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], i64 7, i64 [[VL]])
564 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
565 //
test_vfcvt_f_x_v_f64m8_tu(vfloat64m8_t maskedoff,vint64m8_t src,size_t vl)566 vfloat64m8_t test_vfcvt_f_x_v_f64m8_tu(vfloat64m8_t maskedoff, vint64m8_t src, size_t vl) {
567 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
568 }
569
570 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_xu_v_f64m1_tu
571 // CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
572 // CHECK-RV64-NEXT: entry:
573 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.nxv1f64.nxv1i64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], i64 7, i64 [[VL]])
574 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
575 //
test_vfcvt_f_xu_v_f64m1_tu(vfloat64m1_t maskedoff,vuint64m1_t src,size_t vl)576 vfloat64m1_t test_vfcvt_f_xu_v_f64m1_tu(vfloat64m1_t maskedoff, vuint64m1_t src, size_t vl) {
577 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
578 }
579
580 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_xu_v_f64m2_tu
581 // CHECK-RV64-SAME: (<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
582 // CHECK-RV64-NEXT: entry:
583 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.nxv2f64.nxv2i64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], i64 7, i64 [[VL]])
584 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
585 //
test_vfcvt_f_xu_v_f64m2_tu(vfloat64m2_t maskedoff,vuint64m2_t src,size_t vl)586 vfloat64m2_t test_vfcvt_f_xu_v_f64m2_tu(vfloat64m2_t maskedoff, vuint64m2_t src, size_t vl) {
587 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
588 }
589
590 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_xu_v_f64m4_tu
591 // CHECK-RV64-SAME: (<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
592 // CHECK-RV64-NEXT: entry:
593 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.nxv4f64.nxv4i64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], i64 7, i64 [[VL]])
594 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
595 //
test_vfcvt_f_xu_v_f64m4_tu(vfloat64m4_t maskedoff,vuint64m4_t src,size_t vl)596 vfloat64m4_t test_vfcvt_f_xu_v_f64m4_tu(vfloat64m4_t maskedoff, vuint64m4_t src, size_t vl) {
597 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
598 }
599
600 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_xu_v_f64m8_tu
601 // CHECK-RV64-SAME: (<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
602 // CHECK-RV64-NEXT: entry:
603 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.nxv8f64.nxv8i64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], i64 7, i64 [[VL]])
604 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
605 //
test_vfcvt_f_xu_v_f64m8_tu(vfloat64m8_t maskedoff,vuint64m8_t src,size_t vl)606 vfloat64m8_t test_vfcvt_f_xu_v_f64m8_tu(vfloat64m8_t maskedoff, vuint64m8_t src, size_t vl) {
607 return __riscv_vfcvt_f_tu(maskedoff, src, vl);
608 }
609
610 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_tum
611 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
612 // CHECK-RV64-NEXT: entry:
613 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
614 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
615 //
test_vfcvt_x_f_v_i16mf4_tum(vbool64_t mask,vint16mf4_t maskedoff,vfloat16mf4_t src,size_t vl)616 vint16mf4_t test_vfcvt_x_f_v_i16mf4_tum(vbool64_t mask, vint16mf4_t maskedoff, vfloat16mf4_t src, size_t vl) {
617 return __riscv_vfcvt_x_tum(mask, maskedoff, src, vl);
618 }
619
620 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_tum
621 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
622 // CHECK-RV64-NEXT: entry:
623 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
624 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
625 //
test_vfcvt_x_f_v_i16mf2_tum(vbool32_t mask,vint16mf2_t maskedoff,vfloat16mf2_t src,size_t vl)626 vint16mf2_t test_vfcvt_x_f_v_i16mf2_tum(vbool32_t mask, vint16mf2_t maskedoff, vfloat16mf2_t src, size_t vl) {
627 return __riscv_vfcvt_x_tum(mask, maskedoff, src, vl);
628 }
629
630 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_tum
631 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
632 // CHECK-RV64-NEXT: entry:
633 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
634 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
635 //
test_vfcvt_x_f_v_i16m1_tum(vbool16_t mask,vint16m1_t maskedoff,vfloat16m1_t src,size_t vl)636 vint16m1_t test_vfcvt_x_f_v_i16m1_tum(vbool16_t mask, vint16m1_t maskedoff, vfloat16m1_t src, size_t vl) {
637 return __riscv_vfcvt_x_tum(mask, maskedoff, src, vl);
638 }
639
640 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_tum
641 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
642 // CHECK-RV64-NEXT: entry:
643 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
644 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
645 //
test_vfcvt_x_f_v_i16m2_tum(vbool8_t mask,vint16m2_t maskedoff,vfloat16m2_t src,size_t vl)646 vint16m2_t test_vfcvt_x_f_v_i16m2_tum(vbool8_t mask, vint16m2_t maskedoff, vfloat16m2_t src, size_t vl) {
647 return __riscv_vfcvt_x_tum(mask, maskedoff, src, vl);
648 }
649
650 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_tum
651 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
652 // CHECK-RV64-NEXT: entry:
653 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
654 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
655 //
test_vfcvt_x_f_v_i16m4_tum(vbool4_t mask,vint16m4_t maskedoff,vfloat16m4_t src,size_t vl)656 vint16m4_t test_vfcvt_x_f_v_i16m4_tum(vbool4_t mask, vint16m4_t maskedoff, vfloat16m4_t src, size_t vl) {
657 return __riscv_vfcvt_x_tum(mask, maskedoff, src, vl);
658 }
659
660 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_tum
661 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
662 // CHECK-RV64-NEXT: entry:
663 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
664 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
665 //
test_vfcvt_x_f_v_i16m8_tum(vbool2_t mask,vint16m8_t maskedoff,vfloat16m8_t src,size_t vl)666 vint16m8_t test_vfcvt_x_f_v_i16m8_tum(vbool2_t mask, vint16m8_t maskedoff, vfloat16m8_t src, size_t vl) {
667 return __riscv_vfcvt_x_tum(mask, maskedoff, src, vl);
668 }
669
670 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_tum
671 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
672 // CHECK-RV64-NEXT: entry:
673 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
674 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
675 //
test_vfcvt_xu_f_v_u16mf4_tum(vbool64_t mask,vuint16mf4_t maskedoff,vfloat16mf4_t src,size_t vl)676 vuint16mf4_t test_vfcvt_xu_f_v_u16mf4_tum(vbool64_t mask, vuint16mf4_t maskedoff, vfloat16mf4_t src, size_t vl) {
677 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, vl);
678 }
679
680 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_tum
681 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
682 // CHECK-RV64-NEXT: entry:
683 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
684 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
685 //
test_vfcvt_xu_f_v_u16mf2_tum(vbool32_t mask,vuint16mf2_t maskedoff,vfloat16mf2_t src,size_t vl)686 vuint16mf2_t test_vfcvt_xu_f_v_u16mf2_tum(vbool32_t mask, vuint16mf2_t maskedoff, vfloat16mf2_t src, size_t vl) {
687 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, vl);
688 }
689
690 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_tum
691 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
692 // CHECK-RV64-NEXT: entry:
693 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
694 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
695 //
test_vfcvt_xu_f_v_u16m1_tum(vbool16_t mask,vuint16m1_t maskedoff,vfloat16m1_t src,size_t vl)696 vuint16m1_t test_vfcvt_xu_f_v_u16m1_tum(vbool16_t mask, vuint16m1_t maskedoff, vfloat16m1_t src, size_t vl) {
697 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, vl);
698 }
699
700 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_tum
701 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
702 // CHECK-RV64-NEXT: entry:
703 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
704 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
705 //
test_vfcvt_xu_f_v_u16m2_tum(vbool8_t mask,vuint16m2_t maskedoff,vfloat16m2_t src,size_t vl)706 vuint16m2_t test_vfcvt_xu_f_v_u16m2_tum(vbool8_t mask, vuint16m2_t maskedoff, vfloat16m2_t src, size_t vl) {
707 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, vl);
708 }
709
710 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4_tum
711 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
712 // CHECK-RV64-NEXT: entry:
713 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
714 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
715 //
test_vfcvt_xu_f_v_u16m4_tum(vbool4_t mask,vuint16m4_t maskedoff,vfloat16m4_t src,size_t vl)716 vuint16m4_t test_vfcvt_xu_f_v_u16m4_tum(vbool4_t mask, vuint16m4_t maskedoff, vfloat16m4_t src, size_t vl) {
717 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, vl);
718 }
719
720 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8_tum
721 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
722 // CHECK-RV64-NEXT: entry:
723 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
724 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
725 //
test_vfcvt_xu_f_v_u16m8_tum(vbool2_t mask,vuint16m8_t maskedoff,vfloat16m8_t src,size_t vl)726 vuint16m8_t test_vfcvt_xu_f_v_u16m8_tum(vbool2_t mask, vuint16m8_t maskedoff, vfloat16m8_t src, size_t vl) {
727 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, vl);
728 }
729
730 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_x_v_f16mf4_tum
731 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
732 // CHECK-RV64-NEXT: entry:
733 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
734 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
735 //
test_vfcvt_f_x_v_f16mf4_tum(vbool64_t mask,vfloat16mf4_t maskedoff,vint16mf4_t src,size_t vl)736 vfloat16mf4_t test_vfcvt_f_x_v_f16mf4_tum(vbool64_t mask, vfloat16mf4_t maskedoff, vint16mf4_t src, size_t vl) {
737 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
738 }
739
740 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_x_v_f16mf2_tum
741 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
742 // CHECK-RV64-NEXT: entry:
743 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
744 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
745 //
test_vfcvt_f_x_v_f16mf2_tum(vbool32_t mask,vfloat16mf2_t maskedoff,vint16mf2_t src,size_t vl)746 vfloat16mf2_t test_vfcvt_f_x_v_f16mf2_tum(vbool32_t mask, vfloat16mf2_t maskedoff, vint16mf2_t src, size_t vl) {
747 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
748 }
749
750 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_x_v_f16m1_tum
751 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
752 // CHECK-RV64-NEXT: entry:
753 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
754 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
755 //
test_vfcvt_f_x_v_f16m1_tum(vbool16_t mask,vfloat16m1_t maskedoff,vint16m1_t src,size_t vl)756 vfloat16m1_t test_vfcvt_f_x_v_f16m1_tum(vbool16_t mask, vfloat16m1_t maskedoff, vint16m1_t src, size_t vl) {
757 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
758 }
759
760 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_x_v_f16m2_tum
761 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
762 // CHECK-RV64-NEXT: entry:
763 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
764 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
765 //
test_vfcvt_f_x_v_f16m2_tum(vbool8_t mask,vfloat16m2_t maskedoff,vint16m2_t src,size_t vl)766 vfloat16m2_t test_vfcvt_f_x_v_f16m2_tum(vbool8_t mask, vfloat16m2_t maskedoff, vint16m2_t src, size_t vl) {
767 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
768 }
769
770 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_x_v_f16m4_tum
771 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
772 // CHECK-RV64-NEXT: entry:
773 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
774 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
775 //
test_vfcvt_f_x_v_f16m4_tum(vbool4_t mask,vfloat16m4_t maskedoff,vint16m4_t src,size_t vl)776 vfloat16m4_t test_vfcvt_f_x_v_f16m4_tum(vbool4_t mask, vfloat16m4_t maskedoff, vint16m4_t src, size_t vl) {
777 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
778 }
779
780 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_x_v_f16m8_tum
781 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
782 // CHECK-RV64-NEXT: entry:
783 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i16> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
784 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
785 //
test_vfcvt_f_x_v_f16m8_tum(vbool2_t mask,vfloat16m8_t maskedoff,vint16m8_t src,size_t vl)786 vfloat16m8_t test_vfcvt_f_x_v_f16m8_tum(vbool2_t mask, vfloat16m8_t maskedoff, vint16m8_t src, size_t vl) {
787 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
788 }
789
790 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_xu_v_f16mf4_tum
791 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
792 // CHECK-RV64-NEXT: entry:
793 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
794 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
795 //
test_vfcvt_f_xu_v_f16mf4_tum(vbool64_t mask,vfloat16mf4_t maskedoff,vuint16mf4_t src,size_t vl)796 vfloat16mf4_t test_vfcvt_f_xu_v_f16mf4_tum(vbool64_t mask, vfloat16mf4_t maskedoff, vuint16mf4_t src, size_t vl) {
797 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
798 }
799
800 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_xu_v_f16mf2_tum
801 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
802 // CHECK-RV64-NEXT: entry:
803 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
804 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
805 //
test_vfcvt_f_xu_v_f16mf2_tum(vbool32_t mask,vfloat16mf2_t maskedoff,vuint16mf2_t src,size_t vl)806 vfloat16mf2_t test_vfcvt_f_xu_v_f16mf2_tum(vbool32_t mask, vfloat16mf2_t maskedoff, vuint16mf2_t src, size_t vl) {
807 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
808 }
809
810 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_xu_v_f16m1_tum
811 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
812 // CHECK-RV64-NEXT: entry:
813 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
814 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
815 //
test_vfcvt_f_xu_v_f16m1_tum(vbool16_t mask,vfloat16m1_t maskedoff,vuint16m1_t src,size_t vl)816 vfloat16m1_t test_vfcvt_f_xu_v_f16m1_tum(vbool16_t mask, vfloat16m1_t maskedoff, vuint16m1_t src, size_t vl) {
817 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
818 }
819
820 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_xu_v_f16m2_tum
821 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
822 // CHECK-RV64-NEXT: entry:
823 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
824 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
825 //
test_vfcvt_f_xu_v_f16m2_tum(vbool8_t mask,vfloat16m2_t maskedoff,vuint16m2_t src,size_t vl)826 vfloat16m2_t test_vfcvt_f_xu_v_f16m2_tum(vbool8_t mask, vfloat16m2_t maskedoff, vuint16m2_t src, size_t vl) {
827 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
828 }
829
830 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_xu_v_f16m4_tum
831 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
832 // CHECK-RV64-NEXT: entry:
833 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
834 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
835 //
test_vfcvt_f_xu_v_f16m4_tum(vbool4_t mask,vfloat16m4_t maskedoff,vuint16m4_t src,size_t vl)836 vfloat16m4_t test_vfcvt_f_xu_v_f16m4_tum(vbool4_t mask, vfloat16m4_t maskedoff, vuint16m4_t src, size_t vl) {
837 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
838 }
839
840 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_xu_v_f16m8_tum
841 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
842 // CHECK-RV64-NEXT: entry:
843 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i16> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
844 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
845 //
test_vfcvt_f_xu_v_f16m8_tum(vbool2_t mask,vfloat16m8_t maskedoff,vuint16m8_t src,size_t vl)846 vfloat16m8_t test_vfcvt_f_xu_v_f16m8_tum(vbool2_t mask, vfloat16m8_t maskedoff, vuint16m8_t src, size_t vl) {
847 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
848 }
849
850 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_x_f_v_i32mf2_tum
851 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
852 // CHECK-RV64-NEXT: entry:
853 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
854 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
855 //
test_vfcvt_x_f_v_i32mf2_tum(vbool64_t mask,vint32mf2_t maskedoff,vfloat32mf2_t src,size_t vl)856 vint32mf2_t test_vfcvt_x_f_v_i32mf2_tum(vbool64_t mask, vint32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
857 return __riscv_vfcvt_x_tum(mask, maskedoff, src, vl);
858 }
859
860 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_x_f_v_i32m1_tum
861 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
862 // CHECK-RV64-NEXT: entry:
863 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
864 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
865 //
test_vfcvt_x_f_v_i32m1_tum(vbool32_t mask,vint32m1_t maskedoff,vfloat32m1_t src,size_t vl)866 vint32m1_t test_vfcvt_x_f_v_i32m1_tum(vbool32_t mask, vint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
867 return __riscv_vfcvt_x_tum(mask, maskedoff, src, vl);
868 }
869
870 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_x_f_v_i32m2_tum
871 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
872 // CHECK-RV64-NEXT: entry:
873 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
874 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
875 //
test_vfcvt_x_f_v_i32m2_tum(vbool16_t mask,vint32m2_t maskedoff,vfloat32m2_t src,size_t vl)876 vint32m2_t test_vfcvt_x_f_v_i32m2_tum(vbool16_t mask, vint32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
877 return __riscv_vfcvt_x_tum(mask, maskedoff, src, vl);
878 }
879
880 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_x_f_v_i32m4_tum
881 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
882 // CHECK-RV64-NEXT: entry:
883 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
884 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
885 //
test_vfcvt_x_f_v_i32m4_tum(vbool8_t mask,vint32m4_t maskedoff,vfloat32m4_t src,size_t vl)886 vint32m4_t test_vfcvt_x_f_v_i32m4_tum(vbool8_t mask, vint32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
887 return __riscv_vfcvt_x_tum(mask, maskedoff, src, vl);
888 }
889
890 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_x_f_v_i32m8_tum
891 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
892 // CHECK-RV64-NEXT: entry:
893 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
894 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
895 //
test_vfcvt_x_f_v_i32m8_tum(vbool4_t mask,vint32m8_t maskedoff,vfloat32m8_t src,size_t vl)896 vint32m8_t test_vfcvt_x_f_v_i32m8_tum(vbool4_t mask, vint32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
897 return __riscv_vfcvt_x_tum(mask, maskedoff, src, vl);
898 }
899
900 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_xu_f_v_u32mf2_tum
901 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
902 // CHECK-RV64-NEXT: entry:
903 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
904 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
905 //
test_vfcvt_xu_f_v_u32mf2_tum(vbool64_t mask,vuint32mf2_t maskedoff,vfloat32mf2_t src,size_t vl)906 vuint32mf2_t test_vfcvt_xu_f_v_u32mf2_tum(vbool64_t mask, vuint32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
907 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, vl);
908 }
909
910 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_xu_f_v_u32m1_tum
911 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
912 // CHECK-RV64-NEXT: entry:
913 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
914 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
915 //
test_vfcvt_xu_f_v_u32m1_tum(vbool32_t mask,vuint32m1_t maskedoff,vfloat32m1_t src,size_t vl)916 vuint32m1_t test_vfcvt_xu_f_v_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
917 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, vl);
918 }
919
920 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_xu_f_v_u32m2_tum
921 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
922 // CHECK-RV64-NEXT: entry:
923 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
924 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
925 //
test_vfcvt_xu_f_v_u32m2_tum(vbool16_t mask,vuint32m2_t maskedoff,vfloat32m2_t src,size_t vl)926 vuint32m2_t test_vfcvt_xu_f_v_u32m2_tum(vbool16_t mask, vuint32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
927 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, vl);
928 }
929
930 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_xu_f_v_u32m4_tum
931 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
932 // CHECK-RV64-NEXT: entry:
933 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
934 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
935 //
test_vfcvt_xu_f_v_u32m4_tum(vbool8_t mask,vuint32m4_t maskedoff,vfloat32m4_t src,size_t vl)936 vuint32m4_t test_vfcvt_xu_f_v_u32m4_tum(vbool8_t mask, vuint32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
937 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, vl);
938 }
939
940 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_xu_f_v_u32m8_tum
941 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
942 // CHECK-RV64-NEXT: entry:
943 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
944 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
945 //
test_vfcvt_xu_f_v_u32m8_tum(vbool4_t mask,vuint32m8_t maskedoff,vfloat32m8_t src,size_t vl)946 vuint32m8_t test_vfcvt_xu_f_v_u32m8_tum(vbool4_t mask, vuint32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
947 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, vl);
948 }
949
950 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_x_v_f32mf2_tum
951 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
952 // CHECK-RV64-NEXT: entry:
953 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
954 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
955 //
test_vfcvt_f_x_v_f32mf2_tum(vbool64_t mask,vfloat32mf2_t maskedoff,vint32mf2_t src,size_t vl)956 vfloat32mf2_t test_vfcvt_f_x_v_f32mf2_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vint32mf2_t src, size_t vl) {
957 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
958 }
959
960 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_x_v_f32m1_tum
961 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
962 // CHECK-RV64-NEXT: entry:
963 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f32.nxv2i32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
964 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
965 //
test_vfcvt_f_x_v_f32m1_tum(vbool32_t mask,vfloat32m1_t maskedoff,vint32m1_t src,size_t vl)966 vfloat32m1_t test_vfcvt_f_x_v_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vint32m1_t src, size_t vl) {
967 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
968 }
969
970 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_x_v_f32m2_tum
971 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
972 // CHECK-RV64-NEXT: entry:
973 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f32.nxv4i32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
974 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
975 //
test_vfcvt_f_x_v_f32m2_tum(vbool16_t mask,vfloat32m2_t maskedoff,vint32m2_t src,size_t vl)976 vfloat32m2_t test_vfcvt_f_x_v_f32m2_tum(vbool16_t mask, vfloat32m2_t maskedoff, vint32m2_t src, size_t vl) {
977 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
978 }
979
980 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_x_v_f32m4_tum
981 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
982 // CHECK-RV64-NEXT: entry:
983 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f32.nxv8i32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
984 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
985 //
test_vfcvt_f_x_v_f32m4_tum(vbool8_t mask,vfloat32m4_t maskedoff,vint32m4_t src,size_t vl)986 vfloat32m4_t test_vfcvt_f_x_v_f32m4_tum(vbool8_t mask, vfloat32m4_t maskedoff, vint32m4_t src, size_t vl) {
987 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
988 }
989
990 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_x_v_f32m8_tum
991 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
992 // CHECK-RV64-NEXT: entry:
993 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f32.nxv16i32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
994 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
995 //
test_vfcvt_f_x_v_f32m8_tum(vbool4_t mask,vfloat32m8_t maskedoff,vint32m8_t src,size_t vl)996 vfloat32m8_t test_vfcvt_f_x_v_f32m8_tum(vbool4_t mask, vfloat32m8_t maskedoff, vint32m8_t src, size_t vl) {
997 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
998 }
999
1000 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_xu_v_f32mf2_tum
1001 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1002 // CHECK-RV64-NEXT: entry:
1003 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1004 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
1005 //
test_vfcvt_f_xu_v_f32mf2_tum(vbool64_t mask,vfloat32mf2_t maskedoff,vuint32mf2_t src,size_t vl)1006 vfloat32mf2_t test_vfcvt_f_xu_v_f32mf2_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vuint32mf2_t src, size_t vl) {
1007 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
1008 }
1009
1010 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_xu_v_f32m1_tum
1011 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1012 // CHECK-RV64-NEXT: entry:
1013 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1014 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
1015 //
test_vfcvt_f_xu_v_f32m1_tum(vbool32_t mask,vfloat32m1_t maskedoff,vuint32m1_t src,size_t vl)1016 vfloat32m1_t test_vfcvt_f_xu_v_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vuint32m1_t src, size_t vl) {
1017 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
1018 }
1019
1020 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_xu_v_f32m2_tum
1021 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1022 // CHECK-RV64-NEXT: entry:
1023 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1024 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
1025 //
test_vfcvt_f_xu_v_f32m2_tum(vbool16_t mask,vfloat32m2_t maskedoff,vuint32m2_t src,size_t vl)1026 vfloat32m2_t test_vfcvt_f_xu_v_f32m2_tum(vbool16_t mask, vfloat32m2_t maskedoff, vuint32m2_t src, size_t vl) {
1027 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
1028 }
1029
1030 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_xu_v_f32m4_tum
1031 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1032 // CHECK-RV64-NEXT: entry:
1033 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1034 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
1035 //
test_vfcvt_f_xu_v_f32m4_tum(vbool8_t mask,vfloat32m4_t maskedoff,vuint32m4_t src,size_t vl)1036 vfloat32m4_t test_vfcvt_f_xu_v_f32m4_tum(vbool8_t mask, vfloat32m4_t maskedoff, vuint32m4_t src, size_t vl) {
1037 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
1038 }
1039
1040 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_xu_v_f32m8_tum
1041 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1042 // CHECK-RV64-NEXT: entry:
1043 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1044 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
1045 //
test_vfcvt_f_xu_v_f32m8_tum(vbool4_t mask,vfloat32m8_t maskedoff,vuint32m8_t src,size_t vl)1046 vfloat32m8_t test_vfcvt_f_xu_v_f32m8_tum(vbool4_t mask, vfloat32m8_t maskedoff, vuint32m8_t src, size_t vl) {
1047 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
1048 }
1049
1050 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_x_f_v_i64m1_tum
1051 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1052 // CHECK-RV64-NEXT: entry:
1053 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1054 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
1055 //
test_vfcvt_x_f_v_i64m1_tum(vbool64_t mask,vint64m1_t maskedoff,vfloat64m1_t src,size_t vl)1056 vint64m1_t test_vfcvt_x_f_v_i64m1_tum(vbool64_t mask, vint64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
1057 return __riscv_vfcvt_x_tum(mask, maskedoff, src, vl);
1058 }
1059
1060 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_x_f_v_i64m2_tum
1061 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1062 // CHECK-RV64-NEXT: entry:
1063 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1064 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
1065 //
test_vfcvt_x_f_v_i64m2_tum(vbool32_t mask,vint64m2_t maskedoff,vfloat64m2_t src,size_t vl)1066 vint64m2_t test_vfcvt_x_f_v_i64m2_tum(vbool32_t mask, vint64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
1067 return __riscv_vfcvt_x_tum(mask, maskedoff, src, vl);
1068 }
1069
1070 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_x_f_v_i64m4_tum
1071 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1072 // CHECK-RV64-NEXT: entry:
1073 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1074 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
1075 //
test_vfcvt_x_f_v_i64m4_tum(vbool16_t mask,vint64m4_t maskedoff,vfloat64m4_t src,size_t vl)1076 vint64m4_t test_vfcvt_x_f_v_i64m4_tum(vbool16_t mask, vint64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
1077 return __riscv_vfcvt_x_tum(mask, maskedoff, src, vl);
1078 }
1079
1080 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_x_f_v_i64m8_tum
1081 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1082 // CHECK-RV64-NEXT: entry:
1083 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1084 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
1085 //
test_vfcvt_x_f_v_i64m8_tum(vbool8_t mask,vint64m8_t maskedoff,vfloat64m8_t src,size_t vl)1086 vint64m8_t test_vfcvt_x_f_v_i64m8_tum(vbool8_t mask, vint64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
1087 return __riscv_vfcvt_x_tum(mask, maskedoff, src, vl);
1088 }
1089
1090 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_xu_f_v_u64m1_tum
1091 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1092 // CHECK-RV64-NEXT: entry:
1093 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1094 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
1095 //
test_vfcvt_xu_f_v_u64m1_tum(vbool64_t mask,vuint64m1_t maskedoff,vfloat64m1_t src,size_t vl)1096 vuint64m1_t test_vfcvt_xu_f_v_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
1097 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, vl);
1098 }
1099
1100 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_xu_f_v_u64m2_tum
1101 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1102 // CHECK-RV64-NEXT: entry:
1103 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1104 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
1105 //
test_vfcvt_xu_f_v_u64m2_tum(vbool32_t mask,vuint64m2_t maskedoff,vfloat64m2_t src,size_t vl)1106 vuint64m2_t test_vfcvt_xu_f_v_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
1107 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, vl);
1108 }
1109
1110 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_xu_f_v_u64m4_tum
1111 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1112 // CHECK-RV64-NEXT: entry:
1113 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1114 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
1115 //
test_vfcvt_xu_f_v_u64m4_tum(vbool16_t mask,vuint64m4_t maskedoff,vfloat64m4_t src,size_t vl)1116 vuint64m4_t test_vfcvt_xu_f_v_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
1117 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, vl);
1118 }
1119
1120 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_xu_f_v_u64m8_tum
1121 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1122 // CHECK-RV64-NEXT: entry:
1123 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1124 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
1125 //
test_vfcvt_xu_f_v_u64m8_tum(vbool8_t mask,vuint64m8_t maskedoff,vfloat64m8_t src,size_t vl)1126 vuint64m8_t test_vfcvt_xu_f_v_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
1127 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, vl);
1128 }
1129
1130 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_x_v_f64m1_tum
1131 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1132 // CHECK-RV64-NEXT: entry:
1133 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f64.nxv1i64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1134 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
1135 //
test_vfcvt_f_x_v_f64m1_tum(vbool64_t mask,vfloat64m1_t maskedoff,vint64m1_t src,size_t vl)1136 vfloat64m1_t test_vfcvt_f_x_v_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vint64m1_t src, size_t vl) {
1137 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
1138 }
1139
1140 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_x_v_f64m2_tum
1141 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1142 // CHECK-RV64-NEXT: entry:
1143 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f64.nxv2i64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1144 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
1145 //
test_vfcvt_f_x_v_f64m2_tum(vbool32_t mask,vfloat64m2_t maskedoff,vint64m2_t src,size_t vl)1146 vfloat64m2_t test_vfcvt_f_x_v_f64m2_tum(vbool32_t mask, vfloat64m2_t maskedoff, vint64m2_t src, size_t vl) {
1147 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
1148 }
1149
1150 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_x_v_f64m4_tum
1151 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1152 // CHECK-RV64-NEXT: entry:
1153 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f64.nxv4i64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1154 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1155 //
test_vfcvt_f_x_v_f64m4_tum(vbool16_t mask,vfloat64m4_t maskedoff,vint64m4_t src,size_t vl)1156 vfloat64m4_t test_vfcvt_f_x_v_f64m4_tum(vbool16_t mask, vfloat64m4_t maskedoff, vint64m4_t src, size_t vl) {
1157 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
1158 }
1159
1160 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_x_v_f64m8_tum
1161 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1162 // CHECK-RV64-NEXT: entry:
1163 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f64.nxv8i64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1164 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1165 //
test_vfcvt_f_x_v_f64m8_tum(vbool8_t mask,vfloat64m8_t maskedoff,vint64m8_t src,size_t vl)1166 vfloat64m8_t test_vfcvt_f_x_v_f64m8_tum(vbool8_t mask, vfloat64m8_t maskedoff, vint64m8_t src, size_t vl) {
1167 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
1168 }
1169
1170 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_xu_v_f64m1_tum
1171 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1172 // CHECK-RV64-NEXT: entry:
1173 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f64.nxv1i64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1174 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
1175 //
test_vfcvt_f_xu_v_f64m1_tum(vbool64_t mask,vfloat64m1_t maskedoff,vuint64m1_t src,size_t vl)1176 vfloat64m1_t test_vfcvt_f_xu_v_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vuint64m1_t src, size_t vl) {
1177 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
1178 }
1179
1180 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_xu_v_f64m2_tum
1181 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1182 // CHECK-RV64-NEXT: entry:
1183 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f64.nxv2i64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1184 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
1185 //
test_vfcvt_f_xu_v_f64m2_tum(vbool32_t mask,vfloat64m2_t maskedoff,vuint64m2_t src,size_t vl)1186 vfloat64m2_t test_vfcvt_f_xu_v_f64m2_tum(vbool32_t mask, vfloat64m2_t maskedoff, vuint64m2_t src, size_t vl) {
1187 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
1188 }
1189
1190 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_xu_v_f64m4_tum
1191 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1192 // CHECK-RV64-NEXT: entry:
1193 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f64.nxv4i64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1194 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1195 //
test_vfcvt_f_xu_v_f64m4_tum(vbool16_t mask,vfloat64m4_t maskedoff,vuint64m4_t src,size_t vl)1196 vfloat64m4_t test_vfcvt_f_xu_v_f64m4_tum(vbool16_t mask, vfloat64m4_t maskedoff, vuint64m4_t src, size_t vl) {
1197 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
1198 }
1199
1200 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_xu_v_f64m8_tum
1201 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1202 // CHECK-RV64-NEXT: entry:
1203 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f64.nxv8i64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
1204 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1205 //
test_vfcvt_f_xu_v_f64m8_tum(vbool8_t mask,vfloat64m8_t maskedoff,vuint64m8_t src,size_t vl)1206 vfloat64m8_t test_vfcvt_f_xu_v_f64m8_tum(vbool8_t mask, vfloat64m8_t maskedoff, vuint64m8_t src, size_t vl) {
1207 return __riscv_vfcvt_f_tum(mask, maskedoff, src, vl);
1208 }
1209
1210 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_tumu
1211 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1212 // CHECK-RV64-NEXT: entry:
1213 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1214 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
1215 //
test_vfcvt_x_f_v_i16mf4_tumu(vbool64_t mask,vint16mf4_t maskedoff,vfloat16mf4_t src,size_t vl)1216 vint16mf4_t test_vfcvt_x_f_v_i16mf4_tumu(vbool64_t mask, vint16mf4_t maskedoff, vfloat16mf4_t src, size_t vl) {
1217 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, vl);
1218 }
1219
1220 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_tumu
1221 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1222 // CHECK-RV64-NEXT: entry:
1223 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1224 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
1225 //
test_vfcvt_x_f_v_i16mf2_tumu(vbool32_t mask,vint16mf2_t maskedoff,vfloat16mf2_t src,size_t vl)1226 vint16mf2_t test_vfcvt_x_f_v_i16mf2_tumu(vbool32_t mask, vint16mf2_t maskedoff, vfloat16mf2_t src, size_t vl) {
1227 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, vl);
1228 }
1229
1230 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_tumu
1231 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1232 // CHECK-RV64-NEXT: entry:
1233 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1234 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
1235 //
test_vfcvt_x_f_v_i16m1_tumu(vbool16_t mask,vint16m1_t maskedoff,vfloat16m1_t src,size_t vl)1236 vint16m1_t test_vfcvt_x_f_v_i16m1_tumu(vbool16_t mask, vint16m1_t maskedoff, vfloat16m1_t src, size_t vl) {
1237 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, vl);
1238 }
1239
1240 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_tumu
1241 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1242 // CHECK-RV64-NEXT: entry:
1243 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1244 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
1245 //
test_vfcvt_x_f_v_i16m2_tumu(vbool8_t mask,vint16m2_t maskedoff,vfloat16m2_t src,size_t vl)1246 vint16m2_t test_vfcvt_x_f_v_i16m2_tumu(vbool8_t mask, vint16m2_t maskedoff, vfloat16m2_t src, size_t vl) {
1247 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, vl);
1248 }
1249
1250 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_tumu
1251 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1252 // CHECK-RV64-NEXT: entry:
1253 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1254 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
1255 //
test_vfcvt_x_f_v_i16m4_tumu(vbool4_t mask,vint16m4_t maskedoff,vfloat16m4_t src,size_t vl)1256 vint16m4_t test_vfcvt_x_f_v_i16m4_tumu(vbool4_t mask, vint16m4_t maskedoff, vfloat16m4_t src, size_t vl) {
1257 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, vl);
1258 }
1259
1260 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_tumu
1261 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1262 // CHECK-RV64-NEXT: entry:
1263 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1264 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
1265 //
test_vfcvt_x_f_v_i16m8_tumu(vbool2_t mask,vint16m8_t maskedoff,vfloat16m8_t src,size_t vl)1266 vint16m8_t test_vfcvt_x_f_v_i16m8_tumu(vbool2_t mask, vint16m8_t maskedoff, vfloat16m8_t src, size_t vl) {
1267 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, vl);
1268 }
1269
1270 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_tumu
1271 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1272 // CHECK-RV64-NEXT: entry:
1273 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1274 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
1275 //
test_vfcvt_xu_f_v_u16mf4_tumu(vbool64_t mask,vuint16mf4_t maskedoff,vfloat16mf4_t src,size_t vl)1276 vuint16mf4_t test_vfcvt_xu_f_v_u16mf4_tumu(vbool64_t mask, vuint16mf4_t maskedoff, vfloat16mf4_t src, size_t vl) {
1277 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, vl);
1278 }
1279
1280 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_tumu
1281 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1282 // CHECK-RV64-NEXT: entry:
1283 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1284 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
1285 //
test_vfcvt_xu_f_v_u16mf2_tumu(vbool32_t mask,vuint16mf2_t maskedoff,vfloat16mf2_t src,size_t vl)1286 vuint16mf2_t test_vfcvt_xu_f_v_u16mf2_tumu(vbool32_t mask, vuint16mf2_t maskedoff, vfloat16mf2_t src, size_t vl) {
1287 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, vl);
1288 }
1289
1290 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_tumu
1291 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1292 // CHECK-RV64-NEXT: entry:
1293 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1294 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
1295 //
test_vfcvt_xu_f_v_u16m1_tumu(vbool16_t mask,vuint16m1_t maskedoff,vfloat16m1_t src,size_t vl)1296 vuint16m1_t test_vfcvt_xu_f_v_u16m1_tumu(vbool16_t mask, vuint16m1_t maskedoff, vfloat16m1_t src, size_t vl) {
1297 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, vl);
1298 }
1299
1300 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_tumu
1301 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1302 // CHECK-RV64-NEXT: entry:
1303 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1304 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
1305 //
test_vfcvt_xu_f_v_u16m2_tumu(vbool8_t mask,vuint16m2_t maskedoff,vfloat16m2_t src,size_t vl)1306 vuint16m2_t test_vfcvt_xu_f_v_u16m2_tumu(vbool8_t mask, vuint16m2_t maskedoff, vfloat16m2_t src, size_t vl) {
1307 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, vl);
1308 }
1309
1310 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4_tumu
1311 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1312 // CHECK-RV64-NEXT: entry:
1313 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1314 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
1315 //
test_vfcvt_xu_f_v_u16m4_tumu(vbool4_t mask,vuint16m4_t maskedoff,vfloat16m4_t src,size_t vl)1316 vuint16m4_t test_vfcvt_xu_f_v_u16m4_tumu(vbool4_t mask, vuint16m4_t maskedoff, vfloat16m4_t src, size_t vl) {
1317 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, vl);
1318 }
1319
1320 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8_tumu
1321 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1322 // CHECK-RV64-NEXT: entry:
1323 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1324 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
1325 //
test_vfcvt_xu_f_v_u16m8_tumu(vbool2_t mask,vuint16m8_t maskedoff,vfloat16m8_t src,size_t vl)1326 vuint16m8_t test_vfcvt_xu_f_v_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, vfloat16m8_t src, size_t vl) {
1327 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, vl);
1328 }
1329
1330 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_x_v_f16mf4_tumu
1331 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1332 // CHECK-RV64-NEXT: entry:
1333 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1334 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
1335 //
test_vfcvt_f_x_v_f16mf4_tumu(vbool64_t mask,vfloat16mf4_t maskedoff,vint16mf4_t src,size_t vl)1336 vfloat16mf4_t test_vfcvt_f_x_v_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t maskedoff, vint16mf4_t src, size_t vl) {
1337 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1338 }
1339
1340 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_x_v_f16mf2_tumu
1341 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1342 // CHECK-RV64-NEXT: entry:
1343 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1344 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
1345 //
test_vfcvt_f_x_v_f16mf2_tumu(vbool32_t mask,vfloat16mf2_t maskedoff,vint16mf2_t src,size_t vl)1346 vfloat16mf2_t test_vfcvt_f_x_v_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t maskedoff, vint16mf2_t src, size_t vl) {
1347 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1348 }
1349
1350 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_x_v_f16m1_tumu
1351 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1352 // CHECK-RV64-NEXT: entry:
1353 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1354 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
1355 //
test_vfcvt_f_x_v_f16m1_tumu(vbool16_t mask,vfloat16m1_t maskedoff,vint16m1_t src,size_t vl)1356 vfloat16m1_t test_vfcvt_f_x_v_f16m1_tumu(vbool16_t mask, vfloat16m1_t maskedoff, vint16m1_t src, size_t vl) {
1357 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1358 }
1359
1360 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_x_v_f16m2_tumu
1361 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1362 // CHECK-RV64-NEXT: entry:
1363 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1364 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
1365 //
test_vfcvt_f_x_v_f16m2_tumu(vbool8_t mask,vfloat16m2_t maskedoff,vint16m2_t src,size_t vl)1366 vfloat16m2_t test_vfcvt_f_x_v_f16m2_tumu(vbool8_t mask, vfloat16m2_t maskedoff, vint16m2_t src, size_t vl) {
1367 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1368 }
1369
1370 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_x_v_f16m4_tumu
1371 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1372 // CHECK-RV64-NEXT: entry:
1373 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1374 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
1375 //
test_vfcvt_f_x_v_f16m4_tumu(vbool4_t mask,vfloat16m4_t maskedoff,vint16m4_t src,size_t vl)1376 vfloat16m4_t test_vfcvt_f_x_v_f16m4_tumu(vbool4_t mask, vfloat16m4_t maskedoff, vint16m4_t src, size_t vl) {
1377 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1378 }
1379
1380 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_x_v_f16m8_tumu
1381 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1382 // CHECK-RV64-NEXT: entry:
1383 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i16> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1384 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
1385 //
test_vfcvt_f_x_v_f16m8_tumu(vbool2_t mask,vfloat16m8_t maskedoff,vint16m8_t src,size_t vl)1386 vfloat16m8_t test_vfcvt_f_x_v_f16m8_tumu(vbool2_t mask, vfloat16m8_t maskedoff, vint16m8_t src, size_t vl) {
1387 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1388 }
1389
1390 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_xu_v_f16mf4_tumu
1391 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1392 // CHECK-RV64-NEXT: entry:
1393 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1394 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
1395 //
test_vfcvt_f_xu_v_f16mf4_tumu(vbool64_t mask,vfloat16mf4_t maskedoff,vuint16mf4_t src,size_t vl)1396 vfloat16mf4_t test_vfcvt_f_xu_v_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t maskedoff, vuint16mf4_t src, size_t vl) {
1397 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1398 }
1399
1400 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_xu_v_f16mf2_tumu
1401 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1402 // CHECK-RV64-NEXT: entry:
1403 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1404 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
1405 //
test_vfcvt_f_xu_v_f16mf2_tumu(vbool32_t mask,vfloat16mf2_t maskedoff,vuint16mf2_t src,size_t vl)1406 vfloat16mf2_t test_vfcvt_f_xu_v_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t maskedoff, vuint16mf2_t src, size_t vl) {
1407 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1408 }
1409
1410 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_xu_v_f16m1_tumu
1411 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1412 // CHECK-RV64-NEXT: entry:
1413 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1414 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
1415 //
test_vfcvt_f_xu_v_f16m1_tumu(vbool16_t mask,vfloat16m1_t maskedoff,vuint16m1_t src,size_t vl)1416 vfloat16m1_t test_vfcvt_f_xu_v_f16m1_tumu(vbool16_t mask, vfloat16m1_t maskedoff, vuint16m1_t src, size_t vl) {
1417 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1418 }
1419
1420 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_xu_v_f16m2_tumu
1421 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1422 // CHECK-RV64-NEXT: entry:
1423 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1424 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
1425 //
test_vfcvt_f_xu_v_f16m2_tumu(vbool8_t mask,vfloat16m2_t maskedoff,vuint16m2_t src,size_t vl)1426 vfloat16m2_t test_vfcvt_f_xu_v_f16m2_tumu(vbool8_t mask, vfloat16m2_t maskedoff, vuint16m2_t src, size_t vl) {
1427 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1428 }
1429
1430 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_xu_v_f16m4_tumu
1431 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1432 // CHECK-RV64-NEXT: entry:
1433 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1434 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
1435 //
test_vfcvt_f_xu_v_f16m4_tumu(vbool4_t mask,vfloat16m4_t maskedoff,vuint16m4_t src,size_t vl)1436 vfloat16m4_t test_vfcvt_f_xu_v_f16m4_tumu(vbool4_t mask, vfloat16m4_t maskedoff, vuint16m4_t src, size_t vl) {
1437 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1438 }
1439
1440 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_xu_v_f16m8_tumu
1441 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1442 // CHECK-RV64-NEXT: entry:
1443 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i16> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1444 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
1445 //
test_vfcvt_f_xu_v_f16m8_tumu(vbool2_t mask,vfloat16m8_t maskedoff,vuint16m8_t src,size_t vl)1446 vfloat16m8_t test_vfcvt_f_xu_v_f16m8_tumu(vbool2_t mask, vfloat16m8_t maskedoff, vuint16m8_t src, size_t vl) {
1447 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1448 }
1449
1450 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_x_f_v_i32mf2_tumu
1451 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1452 // CHECK-RV64-NEXT: entry:
1453 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1454 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
1455 //
test_vfcvt_x_f_v_i32mf2_tumu(vbool64_t mask,vint32mf2_t maskedoff,vfloat32mf2_t src,size_t vl)1456 vint32mf2_t test_vfcvt_x_f_v_i32mf2_tumu(vbool64_t mask, vint32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
1457 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, vl);
1458 }
1459
1460 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_x_f_v_i32m1_tumu
1461 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1462 // CHECK-RV64-NEXT: entry:
1463 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1464 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
1465 //
test_vfcvt_x_f_v_i32m1_tumu(vbool32_t mask,vint32m1_t maskedoff,vfloat32m1_t src,size_t vl)1466 vint32m1_t test_vfcvt_x_f_v_i32m1_tumu(vbool32_t mask, vint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
1467 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, vl);
1468 }
1469
1470 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_x_f_v_i32m2_tumu
1471 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1472 // CHECK-RV64-NEXT: entry:
1473 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1474 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
1475 //
test_vfcvt_x_f_v_i32m2_tumu(vbool16_t mask,vint32m2_t maskedoff,vfloat32m2_t src,size_t vl)1476 vint32m2_t test_vfcvt_x_f_v_i32m2_tumu(vbool16_t mask, vint32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
1477 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, vl);
1478 }
1479
1480 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_x_f_v_i32m4_tumu
1481 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1482 // CHECK-RV64-NEXT: entry:
1483 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1484 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
1485 //
test_vfcvt_x_f_v_i32m4_tumu(vbool8_t mask,vint32m4_t maskedoff,vfloat32m4_t src,size_t vl)1486 vint32m4_t test_vfcvt_x_f_v_i32m4_tumu(vbool8_t mask, vint32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
1487 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, vl);
1488 }
1489
1490 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_x_f_v_i32m8_tumu
1491 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1492 // CHECK-RV64-NEXT: entry:
1493 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1494 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
1495 //
test_vfcvt_x_f_v_i32m8_tumu(vbool4_t mask,vint32m8_t maskedoff,vfloat32m8_t src,size_t vl)1496 vint32m8_t test_vfcvt_x_f_v_i32m8_tumu(vbool4_t mask, vint32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
1497 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, vl);
1498 }
1499
1500 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_xu_f_v_u32mf2_tumu
1501 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1502 // CHECK-RV64-NEXT: entry:
1503 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1504 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
1505 //
test_vfcvt_xu_f_v_u32mf2_tumu(vbool64_t mask,vuint32mf2_t maskedoff,vfloat32mf2_t src,size_t vl)1506 vuint32mf2_t test_vfcvt_xu_f_v_u32mf2_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
1507 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, vl);
1508 }
1509
1510 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_xu_f_v_u32m1_tumu
1511 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1512 // CHECK-RV64-NEXT: entry:
1513 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1514 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
1515 //
test_vfcvt_xu_f_v_u32m1_tumu(vbool32_t mask,vuint32m1_t maskedoff,vfloat32m1_t src,size_t vl)1516 vuint32m1_t test_vfcvt_xu_f_v_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
1517 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, vl);
1518 }
1519
1520 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_xu_f_v_u32m2_tumu
1521 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1522 // CHECK-RV64-NEXT: entry:
1523 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1524 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
1525 //
test_vfcvt_xu_f_v_u32m2_tumu(vbool16_t mask,vuint32m2_t maskedoff,vfloat32m2_t src,size_t vl)1526 vuint32m2_t test_vfcvt_xu_f_v_u32m2_tumu(vbool16_t mask, vuint32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
1527 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, vl);
1528 }
1529
1530 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_xu_f_v_u32m4_tumu
1531 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1532 // CHECK-RV64-NEXT: entry:
1533 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1534 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
1535 //
test_vfcvt_xu_f_v_u32m4_tumu(vbool8_t mask,vuint32m4_t maskedoff,vfloat32m4_t src,size_t vl)1536 vuint32m4_t test_vfcvt_xu_f_v_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
1537 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, vl);
1538 }
1539
1540 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_xu_f_v_u32m8_tumu
1541 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1542 // CHECK-RV64-NEXT: entry:
1543 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1544 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
1545 //
test_vfcvt_xu_f_v_u32m8_tumu(vbool4_t mask,vuint32m8_t maskedoff,vfloat32m8_t src,size_t vl)1546 vuint32m8_t test_vfcvt_xu_f_v_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
1547 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, vl);
1548 }
1549
1550 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_x_v_f32mf2_tumu
1551 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1552 // CHECK-RV64-NEXT: entry:
1553 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1554 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
1555 //
test_vfcvt_f_x_v_f32mf2_tumu(vbool64_t mask,vfloat32mf2_t maskedoff,vint32mf2_t src,size_t vl)1556 vfloat32mf2_t test_vfcvt_f_x_v_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vint32mf2_t src, size_t vl) {
1557 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1558 }
1559
1560 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_x_v_f32m1_tumu
1561 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1562 // CHECK-RV64-NEXT: entry:
1563 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f32.nxv2i32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1564 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
1565 //
test_vfcvt_f_x_v_f32m1_tumu(vbool32_t mask,vfloat32m1_t maskedoff,vint32m1_t src,size_t vl)1566 vfloat32m1_t test_vfcvt_f_x_v_f32m1_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vint32m1_t src, size_t vl) {
1567 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1568 }
1569
1570 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_x_v_f32m2_tumu
1571 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1572 // CHECK-RV64-NEXT: entry:
1573 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f32.nxv4i32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1574 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
1575 //
test_vfcvt_f_x_v_f32m2_tumu(vbool16_t mask,vfloat32m2_t maskedoff,vint32m2_t src,size_t vl)1576 vfloat32m2_t test_vfcvt_f_x_v_f32m2_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vint32m2_t src, size_t vl) {
1577 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1578 }
1579
1580 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_x_v_f32m4_tumu
1581 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1582 // CHECK-RV64-NEXT: entry:
1583 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f32.nxv8i32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1584 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
1585 //
test_vfcvt_f_x_v_f32m4_tumu(vbool8_t mask,vfloat32m4_t maskedoff,vint32m4_t src,size_t vl)1586 vfloat32m4_t test_vfcvt_f_x_v_f32m4_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vint32m4_t src, size_t vl) {
1587 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1588 }
1589
1590 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_x_v_f32m8_tumu
1591 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1592 // CHECK-RV64-NEXT: entry:
1593 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f32.nxv16i32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1594 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
1595 //
test_vfcvt_f_x_v_f32m8_tumu(vbool4_t mask,vfloat32m8_t maskedoff,vint32m8_t src,size_t vl)1596 vfloat32m8_t test_vfcvt_f_x_v_f32m8_tumu(vbool4_t mask, vfloat32m8_t maskedoff, vint32m8_t src, size_t vl) {
1597 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1598 }
1599
1600 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_xu_v_f32mf2_tumu
1601 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1602 // CHECK-RV64-NEXT: entry:
1603 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1604 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
1605 //
test_vfcvt_f_xu_v_f32mf2_tumu(vbool64_t mask,vfloat32mf2_t maskedoff,vuint32mf2_t src,size_t vl)1606 vfloat32mf2_t test_vfcvt_f_xu_v_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vuint32mf2_t src, size_t vl) {
1607 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1608 }
1609
1610 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_xu_v_f32m1_tumu
1611 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1612 // CHECK-RV64-NEXT: entry:
1613 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1614 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
1615 //
test_vfcvt_f_xu_v_f32m1_tumu(vbool32_t mask,vfloat32m1_t maskedoff,vuint32m1_t src,size_t vl)1616 vfloat32m1_t test_vfcvt_f_xu_v_f32m1_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vuint32m1_t src, size_t vl) {
1617 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1618 }
1619
1620 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_xu_v_f32m2_tumu
1621 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1622 // CHECK-RV64-NEXT: entry:
1623 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1624 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
1625 //
test_vfcvt_f_xu_v_f32m2_tumu(vbool16_t mask,vfloat32m2_t maskedoff,vuint32m2_t src,size_t vl)1626 vfloat32m2_t test_vfcvt_f_xu_v_f32m2_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vuint32m2_t src, size_t vl) {
1627 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1628 }
1629
1630 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_xu_v_f32m4_tumu
1631 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1632 // CHECK-RV64-NEXT: entry:
1633 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1634 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
1635 //
test_vfcvt_f_xu_v_f32m4_tumu(vbool8_t mask,vfloat32m4_t maskedoff,vuint32m4_t src,size_t vl)1636 vfloat32m4_t test_vfcvt_f_xu_v_f32m4_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vuint32m4_t src, size_t vl) {
1637 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1638 }
1639
1640 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_xu_v_f32m8_tumu
1641 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1642 // CHECK-RV64-NEXT: entry:
1643 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1644 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
1645 //
test_vfcvt_f_xu_v_f32m8_tumu(vbool4_t mask,vfloat32m8_t maskedoff,vuint32m8_t src,size_t vl)1646 vfloat32m8_t test_vfcvt_f_xu_v_f32m8_tumu(vbool4_t mask, vfloat32m8_t maskedoff, vuint32m8_t src, size_t vl) {
1647 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1648 }
1649
1650 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_x_f_v_i64m1_tumu
1651 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1652 // CHECK-RV64-NEXT: entry:
1653 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1654 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
1655 //
test_vfcvt_x_f_v_i64m1_tumu(vbool64_t mask,vint64m1_t maskedoff,vfloat64m1_t src,size_t vl)1656 vint64m1_t test_vfcvt_x_f_v_i64m1_tumu(vbool64_t mask, vint64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
1657 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, vl);
1658 }
1659
1660 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_x_f_v_i64m2_tumu
1661 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1662 // CHECK-RV64-NEXT: entry:
1663 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1664 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
1665 //
test_vfcvt_x_f_v_i64m2_tumu(vbool32_t mask,vint64m2_t maskedoff,vfloat64m2_t src,size_t vl)1666 vint64m2_t test_vfcvt_x_f_v_i64m2_tumu(vbool32_t mask, vint64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
1667 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, vl);
1668 }
1669
1670 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_x_f_v_i64m4_tumu
1671 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1672 // CHECK-RV64-NEXT: entry:
1673 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1674 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
1675 //
test_vfcvt_x_f_v_i64m4_tumu(vbool16_t mask,vint64m4_t maskedoff,vfloat64m4_t src,size_t vl)1676 vint64m4_t test_vfcvt_x_f_v_i64m4_tumu(vbool16_t mask, vint64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
1677 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, vl);
1678 }
1679
1680 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_x_f_v_i64m8_tumu
1681 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1682 // CHECK-RV64-NEXT: entry:
1683 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1684 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
1685 //
test_vfcvt_x_f_v_i64m8_tumu(vbool8_t mask,vint64m8_t maskedoff,vfloat64m8_t src,size_t vl)1686 vint64m8_t test_vfcvt_x_f_v_i64m8_tumu(vbool8_t mask, vint64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
1687 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, vl);
1688 }
1689
1690 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_xu_f_v_u64m1_tumu
1691 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1692 // CHECK-RV64-NEXT: entry:
1693 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1694 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
1695 //
test_vfcvt_xu_f_v_u64m1_tumu(vbool64_t mask,vuint64m1_t maskedoff,vfloat64m1_t src,size_t vl)1696 vuint64m1_t test_vfcvt_xu_f_v_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
1697 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, vl);
1698 }
1699
1700 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_xu_f_v_u64m2_tumu
1701 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1702 // CHECK-RV64-NEXT: entry:
1703 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1704 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
1705 //
test_vfcvt_xu_f_v_u64m2_tumu(vbool32_t mask,vuint64m2_t maskedoff,vfloat64m2_t src,size_t vl)1706 vuint64m2_t test_vfcvt_xu_f_v_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
1707 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, vl);
1708 }
1709
1710 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_xu_f_v_u64m4_tumu
1711 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1712 // CHECK-RV64-NEXT: entry:
1713 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1714 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
1715 //
test_vfcvt_xu_f_v_u64m4_tumu(vbool16_t mask,vuint64m4_t maskedoff,vfloat64m4_t src,size_t vl)1716 vuint64m4_t test_vfcvt_xu_f_v_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
1717 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, vl);
1718 }
1719
1720 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_xu_f_v_u64m8_tumu
1721 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1722 // CHECK-RV64-NEXT: entry:
1723 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1724 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
1725 //
test_vfcvt_xu_f_v_u64m8_tumu(vbool8_t mask,vuint64m8_t maskedoff,vfloat64m8_t src,size_t vl)1726 vuint64m8_t test_vfcvt_xu_f_v_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
1727 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, vl);
1728 }
1729
1730 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_x_v_f64m1_tumu
1731 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1732 // CHECK-RV64-NEXT: entry:
1733 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f64.nxv1i64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1734 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
1735 //
test_vfcvt_f_x_v_f64m1_tumu(vbool64_t mask,vfloat64m1_t maskedoff,vint64m1_t src,size_t vl)1736 vfloat64m1_t test_vfcvt_f_x_v_f64m1_tumu(vbool64_t mask, vfloat64m1_t maskedoff, vint64m1_t src, size_t vl) {
1737 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1738 }
1739
1740 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_x_v_f64m2_tumu
1741 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1742 // CHECK-RV64-NEXT: entry:
1743 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f64.nxv2i64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1744 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
1745 //
test_vfcvt_f_x_v_f64m2_tumu(vbool32_t mask,vfloat64m2_t maskedoff,vint64m2_t src,size_t vl)1746 vfloat64m2_t test_vfcvt_f_x_v_f64m2_tumu(vbool32_t mask, vfloat64m2_t maskedoff, vint64m2_t src, size_t vl) {
1747 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1748 }
1749
1750 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_x_v_f64m4_tumu
1751 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1752 // CHECK-RV64-NEXT: entry:
1753 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f64.nxv4i64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1754 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1755 //
test_vfcvt_f_x_v_f64m4_tumu(vbool16_t mask,vfloat64m4_t maskedoff,vint64m4_t src,size_t vl)1756 vfloat64m4_t test_vfcvt_f_x_v_f64m4_tumu(vbool16_t mask, vfloat64m4_t maskedoff, vint64m4_t src, size_t vl) {
1757 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1758 }
1759
1760 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_x_v_f64m8_tumu
1761 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1762 // CHECK-RV64-NEXT: entry:
1763 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f64.nxv8i64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1764 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1765 //
test_vfcvt_f_x_v_f64m8_tumu(vbool8_t mask,vfloat64m8_t maskedoff,vint64m8_t src,size_t vl)1766 vfloat64m8_t test_vfcvt_f_x_v_f64m8_tumu(vbool8_t mask, vfloat64m8_t maskedoff, vint64m8_t src, size_t vl) {
1767 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1768 }
1769
1770 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_xu_v_f64m1_tumu
1771 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1772 // CHECK-RV64-NEXT: entry:
1773 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f64.nxv1i64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1774 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
1775 //
test_vfcvt_f_xu_v_f64m1_tumu(vbool64_t mask,vfloat64m1_t maskedoff,vuint64m1_t src,size_t vl)1776 vfloat64m1_t test_vfcvt_f_xu_v_f64m1_tumu(vbool64_t mask, vfloat64m1_t maskedoff, vuint64m1_t src, size_t vl) {
1777 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1778 }
1779
1780 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_xu_v_f64m2_tumu
1781 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1782 // CHECK-RV64-NEXT: entry:
1783 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f64.nxv2i64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1784 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
1785 //
test_vfcvt_f_xu_v_f64m2_tumu(vbool32_t mask,vfloat64m2_t maskedoff,vuint64m2_t src,size_t vl)1786 vfloat64m2_t test_vfcvt_f_xu_v_f64m2_tumu(vbool32_t mask, vfloat64m2_t maskedoff, vuint64m2_t src, size_t vl) {
1787 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1788 }
1789
1790 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_xu_v_f64m4_tumu
1791 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1792 // CHECK-RV64-NEXT: entry:
1793 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f64.nxv4i64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1794 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1795 //
test_vfcvt_f_xu_v_f64m4_tumu(vbool16_t mask,vfloat64m4_t maskedoff,vuint64m4_t src,size_t vl)1796 vfloat64m4_t test_vfcvt_f_xu_v_f64m4_tumu(vbool16_t mask, vfloat64m4_t maskedoff, vuint64m4_t src, size_t vl) {
1797 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1798 }
1799
1800 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_xu_v_f64m8_tumu
1801 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1802 // CHECK-RV64-NEXT: entry:
1803 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f64.nxv8i64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
1804 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1805 //
test_vfcvt_f_xu_v_f64m8_tumu(vbool8_t mask,vfloat64m8_t maskedoff,vuint64m8_t src,size_t vl)1806 vfloat64m8_t test_vfcvt_f_xu_v_f64m8_tumu(vbool8_t mask, vfloat64m8_t maskedoff, vuint64m8_t src, size_t vl) {
1807 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, vl);
1808 }
1809
1810 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_mu
1811 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1812 // CHECK-RV64-NEXT: entry:
1813 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1814 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
1815 //
test_vfcvt_x_f_v_i16mf4_mu(vbool64_t mask,vint16mf4_t maskedoff,vfloat16mf4_t src,size_t vl)1816 vint16mf4_t test_vfcvt_x_f_v_i16mf4_mu(vbool64_t mask, vint16mf4_t maskedoff, vfloat16mf4_t src, size_t vl) {
1817 return __riscv_vfcvt_x_mu(mask, maskedoff, src, vl);
1818 }
1819
1820 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_mu
1821 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1822 // CHECK-RV64-NEXT: entry:
1823 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1824 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
1825 //
test_vfcvt_x_f_v_i16mf2_mu(vbool32_t mask,vint16mf2_t maskedoff,vfloat16mf2_t src,size_t vl)1826 vint16mf2_t test_vfcvt_x_f_v_i16mf2_mu(vbool32_t mask, vint16mf2_t maskedoff, vfloat16mf2_t src, size_t vl) {
1827 return __riscv_vfcvt_x_mu(mask, maskedoff, src, vl);
1828 }
1829
1830 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_mu
1831 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1832 // CHECK-RV64-NEXT: entry:
1833 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1834 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
1835 //
test_vfcvt_x_f_v_i16m1_mu(vbool16_t mask,vint16m1_t maskedoff,vfloat16m1_t src,size_t vl)1836 vint16m1_t test_vfcvt_x_f_v_i16m1_mu(vbool16_t mask, vint16m1_t maskedoff, vfloat16m1_t src, size_t vl) {
1837 return __riscv_vfcvt_x_mu(mask, maskedoff, src, vl);
1838 }
1839
1840 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_mu
1841 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1842 // CHECK-RV64-NEXT: entry:
1843 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1844 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
1845 //
test_vfcvt_x_f_v_i16m2_mu(vbool8_t mask,vint16m2_t maskedoff,vfloat16m2_t src,size_t vl)1846 vint16m2_t test_vfcvt_x_f_v_i16m2_mu(vbool8_t mask, vint16m2_t maskedoff, vfloat16m2_t src, size_t vl) {
1847 return __riscv_vfcvt_x_mu(mask, maskedoff, src, vl);
1848 }
1849
1850 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_mu
1851 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1852 // CHECK-RV64-NEXT: entry:
1853 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1854 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
1855 //
test_vfcvt_x_f_v_i16m4_mu(vbool4_t mask,vint16m4_t maskedoff,vfloat16m4_t src,size_t vl)1856 vint16m4_t test_vfcvt_x_f_v_i16m4_mu(vbool4_t mask, vint16m4_t maskedoff, vfloat16m4_t src, size_t vl) {
1857 return __riscv_vfcvt_x_mu(mask, maskedoff, src, vl);
1858 }
1859
1860 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_mu
1861 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1862 // CHECK-RV64-NEXT: entry:
1863 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1864 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
1865 //
test_vfcvt_x_f_v_i16m8_mu(vbool2_t mask,vint16m8_t maskedoff,vfloat16m8_t src,size_t vl)1866 vint16m8_t test_vfcvt_x_f_v_i16m8_mu(vbool2_t mask, vint16m8_t maskedoff, vfloat16m8_t src, size_t vl) {
1867 return __riscv_vfcvt_x_mu(mask, maskedoff, src, vl);
1868 }
1869
1870 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_mu
1871 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1872 // CHECK-RV64-NEXT: entry:
1873 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1874 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
1875 //
test_vfcvt_xu_f_v_u16mf4_mu(vbool64_t mask,vuint16mf4_t maskedoff,vfloat16mf4_t src,size_t vl)1876 vuint16mf4_t test_vfcvt_xu_f_v_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, vfloat16mf4_t src, size_t vl) {
1877 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, vl);
1878 }
1879
1880 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_mu
1881 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1882 // CHECK-RV64-NEXT: entry:
1883 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1884 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
1885 //
test_vfcvt_xu_f_v_u16mf2_mu(vbool32_t mask,vuint16mf2_t maskedoff,vfloat16mf2_t src,size_t vl)1886 vuint16mf2_t test_vfcvt_xu_f_v_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, vfloat16mf2_t src, size_t vl) {
1887 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, vl);
1888 }
1889
1890 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_mu
1891 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1892 // CHECK-RV64-NEXT: entry:
1893 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1894 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
1895 //
test_vfcvt_xu_f_v_u16m1_mu(vbool16_t mask,vuint16m1_t maskedoff,vfloat16m1_t src,size_t vl)1896 vuint16m1_t test_vfcvt_xu_f_v_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, vfloat16m1_t src, size_t vl) {
1897 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, vl);
1898 }
1899
1900 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_mu
1901 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1902 // CHECK-RV64-NEXT: entry:
1903 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1904 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
1905 //
test_vfcvt_xu_f_v_u16m2_mu(vbool8_t mask,vuint16m2_t maskedoff,vfloat16m2_t src,size_t vl)1906 vuint16m2_t test_vfcvt_xu_f_v_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, vfloat16m2_t src, size_t vl) {
1907 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, vl);
1908 }
1909
1910 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4_mu
1911 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1912 // CHECK-RV64-NEXT: entry:
1913 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1914 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
1915 //
test_vfcvt_xu_f_v_u16m4_mu(vbool4_t mask,vuint16m4_t maskedoff,vfloat16m4_t src,size_t vl)1916 vuint16m4_t test_vfcvt_xu_f_v_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, vfloat16m4_t src, size_t vl) {
1917 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, vl);
1918 }
1919
1920 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8_mu
1921 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1922 // CHECK-RV64-NEXT: entry:
1923 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1924 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
1925 //
test_vfcvt_xu_f_v_u16m8_mu(vbool2_t mask,vuint16m8_t maskedoff,vfloat16m8_t src,size_t vl)1926 vuint16m8_t test_vfcvt_xu_f_v_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, vfloat16m8_t src, size_t vl) {
1927 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, vl);
1928 }
1929
1930 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_x_v_f16mf4_mu
1931 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1932 // CHECK-RV64-NEXT: entry:
1933 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1934 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
1935 //
test_vfcvt_f_x_v_f16mf4_mu(vbool64_t mask,vfloat16mf4_t maskedoff,vint16mf4_t src,size_t vl)1936 vfloat16mf4_t test_vfcvt_f_x_v_f16mf4_mu(vbool64_t mask, vfloat16mf4_t maskedoff, vint16mf4_t src, size_t vl) {
1937 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
1938 }
1939
1940 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_x_v_f16mf2_mu
1941 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1942 // CHECK-RV64-NEXT: entry:
1943 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1944 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
1945 //
test_vfcvt_f_x_v_f16mf2_mu(vbool32_t mask,vfloat16mf2_t maskedoff,vint16mf2_t src,size_t vl)1946 vfloat16mf2_t test_vfcvt_f_x_v_f16mf2_mu(vbool32_t mask, vfloat16mf2_t maskedoff, vint16mf2_t src, size_t vl) {
1947 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
1948 }
1949
1950 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_x_v_f16m1_mu
1951 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1952 // CHECK-RV64-NEXT: entry:
1953 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1954 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
1955 //
test_vfcvt_f_x_v_f16m1_mu(vbool16_t mask,vfloat16m1_t maskedoff,vint16m1_t src,size_t vl)1956 vfloat16m1_t test_vfcvt_f_x_v_f16m1_mu(vbool16_t mask, vfloat16m1_t maskedoff, vint16m1_t src, size_t vl) {
1957 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
1958 }
1959
1960 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_x_v_f16m2_mu
1961 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1962 // CHECK-RV64-NEXT: entry:
1963 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1964 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
1965 //
test_vfcvt_f_x_v_f16m2_mu(vbool8_t mask,vfloat16m2_t maskedoff,vint16m2_t src,size_t vl)1966 vfloat16m2_t test_vfcvt_f_x_v_f16m2_mu(vbool8_t mask, vfloat16m2_t maskedoff, vint16m2_t src, size_t vl) {
1967 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
1968 }
1969
1970 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_x_v_f16m4_mu
1971 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1972 // CHECK-RV64-NEXT: entry:
1973 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1974 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
1975 //
test_vfcvt_f_x_v_f16m4_mu(vbool4_t mask,vfloat16m4_t maskedoff,vint16m4_t src,size_t vl)1976 vfloat16m4_t test_vfcvt_f_x_v_f16m4_mu(vbool4_t mask, vfloat16m4_t maskedoff, vint16m4_t src, size_t vl) {
1977 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
1978 }
1979
1980 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_x_v_f16m8_mu
1981 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1982 // CHECK-RV64-NEXT: entry:
1983 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i16> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1984 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
1985 //
test_vfcvt_f_x_v_f16m8_mu(vbool2_t mask,vfloat16m8_t maskedoff,vint16m8_t src,size_t vl)1986 vfloat16m8_t test_vfcvt_f_x_v_f16m8_mu(vbool2_t mask, vfloat16m8_t maskedoff, vint16m8_t src, size_t vl) {
1987 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
1988 }
1989
1990 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_xu_v_f16mf4_mu
1991 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1992 // CHECK-RV64-NEXT: entry:
1993 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
1994 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
1995 //
test_vfcvt_f_xu_v_f16mf4_mu(vbool64_t mask,vfloat16mf4_t maskedoff,vuint16mf4_t src,size_t vl)1996 vfloat16mf4_t test_vfcvt_f_xu_v_f16mf4_mu(vbool64_t mask, vfloat16mf4_t maskedoff, vuint16mf4_t src, size_t vl) {
1997 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
1998 }
1999
2000 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_xu_v_f16mf2_mu
2001 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2002 // CHECK-RV64-NEXT: entry:
2003 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2004 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
2005 //
test_vfcvt_f_xu_v_f16mf2_mu(vbool32_t mask,vfloat16mf2_t maskedoff,vuint16mf2_t src,size_t vl)2006 vfloat16mf2_t test_vfcvt_f_xu_v_f16mf2_mu(vbool32_t mask, vfloat16mf2_t maskedoff, vuint16mf2_t src, size_t vl) {
2007 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2008 }
2009
2010 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_xu_v_f16m1_mu
2011 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2012 // CHECK-RV64-NEXT: entry:
2013 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2014 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
2015 //
test_vfcvt_f_xu_v_f16m1_mu(vbool16_t mask,vfloat16m1_t maskedoff,vuint16m1_t src,size_t vl)2016 vfloat16m1_t test_vfcvt_f_xu_v_f16m1_mu(vbool16_t mask, vfloat16m1_t maskedoff, vuint16m1_t src, size_t vl) {
2017 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2018 }
2019
2020 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_xu_v_f16m2_mu
2021 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2022 // CHECK-RV64-NEXT: entry:
2023 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2024 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
2025 //
test_vfcvt_f_xu_v_f16m2_mu(vbool8_t mask,vfloat16m2_t maskedoff,vuint16m2_t src,size_t vl)2026 vfloat16m2_t test_vfcvt_f_xu_v_f16m2_mu(vbool8_t mask, vfloat16m2_t maskedoff, vuint16m2_t src, size_t vl) {
2027 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2028 }
2029
2030 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_xu_v_f16m4_mu
2031 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2032 // CHECK-RV64-NEXT: entry:
2033 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2034 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
2035 //
test_vfcvt_f_xu_v_f16m4_mu(vbool4_t mask,vfloat16m4_t maskedoff,vuint16m4_t src,size_t vl)2036 vfloat16m4_t test_vfcvt_f_xu_v_f16m4_mu(vbool4_t mask, vfloat16m4_t maskedoff, vuint16m4_t src, size_t vl) {
2037 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2038 }
2039
2040 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_xu_v_f16m8_mu
2041 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2042 // CHECK-RV64-NEXT: entry:
2043 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i16> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2044 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
2045 //
test_vfcvt_f_xu_v_f16m8_mu(vbool2_t mask,vfloat16m8_t maskedoff,vuint16m8_t src,size_t vl)2046 vfloat16m8_t test_vfcvt_f_xu_v_f16m8_mu(vbool2_t mask, vfloat16m8_t maskedoff, vuint16m8_t src, size_t vl) {
2047 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2048 }
2049
2050 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_x_f_v_i32mf2_mu
2051 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2052 // CHECK-RV64-NEXT: entry:
2053 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2054 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
2055 //
test_vfcvt_x_f_v_i32mf2_mu(vbool64_t mask,vint32mf2_t maskedoff,vfloat32mf2_t src,size_t vl)2056 vint32mf2_t test_vfcvt_x_f_v_i32mf2_mu(vbool64_t mask, vint32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
2057 return __riscv_vfcvt_x_mu(mask, maskedoff, src, vl);
2058 }
2059
2060 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_x_f_v_i32m1_mu
2061 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2062 // CHECK-RV64-NEXT: entry:
2063 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2064 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
2065 //
test_vfcvt_x_f_v_i32m1_mu(vbool32_t mask,vint32m1_t maskedoff,vfloat32m1_t src,size_t vl)2066 vint32m1_t test_vfcvt_x_f_v_i32m1_mu(vbool32_t mask, vint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
2067 return __riscv_vfcvt_x_mu(mask, maskedoff, src, vl);
2068 }
2069
2070 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_x_f_v_i32m2_mu
2071 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2072 // CHECK-RV64-NEXT: entry:
2073 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2074 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
2075 //
test_vfcvt_x_f_v_i32m2_mu(vbool16_t mask,vint32m2_t maskedoff,vfloat32m2_t src,size_t vl)2076 vint32m2_t test_vfcvt_x_f_v_i32m2_mu(vbool16_t mask, vint32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
2077 return __riscv_vfcvt_x_mu(mask, maskedoff, src, vl);
2078 }
2079
2080 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_x_f_v_i32m4_mu
2081 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2082 // CHECK-RV64-NEXT: entry:
2083 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2084 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
2085 //
test_vfcvt_x_f_v_i32m4_mu(vbool8_t mask,vint32m4_t maskedoff,vfloat32m4_t src,size_t vl)2086 vint32m4_t test_vfcvt_x_f_v_i32m4_mu(vbool8_t mask, vint32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
2087 return __riscv_vfcvt_x_mu(mask, maskedoff, src, vl);
2088 }
2089
2090 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_x_f_v_i32m8_mu
2091 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2092 // CHECK-RV64-NEXT: entry:
2093 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2094 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
2095 //
test_vfcvt_x_f_v_i32m8_mu(vbool4_t mask,vint32m8_t maskedoff,vfloat32m8_t src,size_t vl)2096 vint32m8_t test_vfcvt_x_f_v_i32m8_mu(vbool4_t mask, vint32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
2097 return __riscv_vfcvt_x_mu(mask, maskedoff, src, vl);
2098 }
2099
2100 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_xu_f_v_u32mf2_mu
2101 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2102 // CHECK-RV64-NEXT: entry:
2103 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2104 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
2105 //
test_vfcvt_xu_f_v_u32mf2_mu(vbool64_t mask,vuint32mf2_t maskedoff,vfloat32mf2_t src,size_t vl)2106 vuint32mf2_t test_vfcvt_xu_f_v_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
2107 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, vl);
2108 }
2109
2110 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_xu_f_v_u32m1_mu
2111 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2112 // CHECK-RV64-NEXT: entry:
2113 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2114 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
2115 //
test_vfcvt_xu_f_v_u32m1_mu(vbool32_t mask,vuint32m1_t maskedoff,vfloat32m1_t src,size_t vl)2116 vuint32m1_t test_vfcvt_xu_f_v_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
2117 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, vl);
2118 }
2119
2120 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_xu_f_v_u32m2_mu
2121 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2122 // CHECK-RV64-NEXT: entry:
2123 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2124 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
2125 //
test_vfcvt_xu_f_v_u32m2_mu(vbool16_t mask,vuint32m2_t maskedoff,vfloat32m2_t src,size_t vl)2126 vuint32m2_t test_vfcvt_xu_f_v_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
2127 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, vl);
2128 }
2129
2130 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_xu_f_v_u32m4_mu
2131 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2132 // CHECK-RV64-NEXT: entry:
2133 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2134 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
2135 //
test_vfcvt_xu_f_v_u32m4_mu(vbool8_t mask,vuint32m4_t maskedoff,vfloat32m4_t src,size_t vl)2136 vuint32m4_t test_vfcvt_xu_f_v_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
2137 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, vl);
2138 }
2139
2140 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_xu_f_v_u32m8_mu
2141 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2142 // CHECK-RV64-NEXT: entry:
2143 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2144 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
2145 //
test_vfcvt_xu_f_v_u32m8_mu(vbool4_t mask,vuint32m8_t maskedoff,vfloat32m8_t src,size_t vl)2146 vuint32m8_t test_vfcvt_xu_f_v_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
2147 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, vl);
2148 }
2149
2150 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_x_v_f32mf2_mu
2151 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2152 // CHECK-RV64-NEXT: entry:
2153 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2154 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
2155 //
test_vfcvt_f_x_v_f32mf2_mu(vbool64_t mask,vfloat32mf2_t maskedoff,vint32mf2_t src,size_t vl)2156 vfloat32mf2_t test_vfcvt_f_x_v_f32mf2_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vint32mf2_t src, size_t vl) {
2157 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2158 }
2159
2160 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_x_v_f32m1_mu
2161 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2162 // CHECK-RV64-NEXT: entry:
2163 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f32.nxv2i32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2164 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
2165 //
test_vfcvt_f_x_v_f32m1_mu(vbool32_t mask,vfloat32m1_t maskedoff,vint32m1_t src,size_t vl)2166 vfloat32m1_t test_vfcvt_f_x_v_f32m1_mu(vbool32_t mask, vfloat32m1_t maskedoff, vint32m1_t src, size_t vl) {
2167 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2168 }
2169
2170 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_x_v_f32m2_mu
2171 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2172 // CHECK-RV64-NEXT: entry:
2173 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f32.nxv4i32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2174 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
2175 //
test_vfcvt_f_x_v_f32m2_mu(vbool16_t mask,vfloat32m2_t maskedoff,vint32m2_t src,size_t vl)2176 vfloat32m2_t test_vfcvt_f_x_v_f32m2_mu(vbool16_t mask, vfloat32m2_t maskedoff, vint32m2_t src, size_t vl) {
2177 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2178 }
2179
2180 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_x_v_f32m4_mu
2181 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2182 // CHECK-RV64-NEXT: entry:
2183 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f32.nxv8i32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2184 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
2185 //
test_vfcvt_f_x_v_f32m4_mu(vbool8_t mask,vfloat32m4_t maskedoff,vint32m4_t src,size_t vl)2186 vfloat32m4_t test_vfcvt_f_x_v_f32m4_mu(vbool8_t mask, vfloat32m4_t maskedoff, vint32m4_t src, size_t vl) {
2187 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2188 }
2189
2190 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_x_v_f32m8_mu
2191 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2192 // CHECK-RV64-NEXT: entry:
2193 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f32.nxv16i32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2194 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
2195 //
test_vfcvt_f_x_v_f32m8_mu(vbool4_t mask,vfloat32m8_t maskedoff,vint32m8_t src,size_t vl)2196 vfloat32m8_t test_vfcvt_f_x_v_f32m8_mu(vbool4_t mask, vfloat32m8_t maskedoff, vint32m8_t src, size_t vl) {
2197 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2198 }
2199
2200 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_xu_v_f32mf2_mu
2201 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2202 // CHECK-RV64-NEXT: entry:
2203 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2204 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
2205 //
test_vfcvt_f_xu_v_f32mf2_mu(vbool64_t mask,vfloat32mf2_t maskedoff,vuint32mf2_t src,size_t vl)2206 vfloat32mf2_t test_vfcvt_f_xu_v_f32mf2_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vuint32mf2_t src, size_t vl) {
2207 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2208 }
2209
2210 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_xu_v_f32m1_mu
2211 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2212 // CHECK-RV64-NEXT: entry:
2213 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2214 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
2215 //
test_vfcvt_f_xu_v_f32m1_mu(vbool32_t mask,vfloat32m1_t maskedoff,vuint32m1_t src,size_t vl)2216 vfloat32m1_t test_vfcvt_f_xu_v_f32m1_mu(vbool32_t mask, vfloat32m1_t maskedoff, vuint32m1_t src, size_t vl) {
2217 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2218 }
2219
2220 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_xu_v_f32m2_mu
2221 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2222 // CHECK-RV64-NEXT: entry:
2223 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2224 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
2225 //
test_vfcvt_f_xu_v_f32m2_mu(vbool16_t mask,vfloat32m2_t maskedoff,vuint32m2_t src,size_t vl)2226 vfloat32m2_t test_vfcvt_f_xu_v_f32m2_mu(vbool16_t mask, vfloat32m2_t maskedoff, vuint32m2_t src, size_t vl) {
2227 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2228 }
2229
2230 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_xu_v_f32m4_mu
2231 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2232 // CHECK-RV64-NEXT: entry:
2233 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2234 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
2235 //
test_vfcvt_f_xu_v_f32m4_mu(vbool8_t mask,vfloat32m4_t maskedoff,vuint32m4_t src,size_t vl)2236 vfloat32m4_t test_vfcvt_f_xu_v_f32m4_mu(vbool8_t mask, vfloat32m4_t maskedoff, vuint32m4_t src, size_t vl) {
2237 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2238 }
2239
2240 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_xu_v_f32m8_mu
2241 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2242 // CHECK-RV64-NEXT: entry:
2243 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2244 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
2245 //
test_vfcvt_f_xu_v_f32m8_mu(vbool4_t mask,vfloat32m8_t maskedoff,vuint32m8_t src,size_t vl)2246 vfloat32m8_t test_vfcvt_f_xu_v_f32m8_mu(vbool4_t mask, vfloat32m8_t maskedoff, vuint32m8_t src, size_t vl) {
2247 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2248 }
2249
2250 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_x_f_v_i64m1_mu
2251 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2252 // CHECK-RV64-NEXT: entry:
2253 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2254 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
2255 //
test_vfcvt_x_f_v_i64m1_mu(vbool64_t mask,vint64m1_t maskedoff,vfloat64m1_t src,size_t vl)2256 vint64m1_t test_vfcvt_x_f_v_i64m1_mu(vbool64_t mask, vint64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
2257 return __riscv_vfcvt_x_mu(mask, maskedoff, src, vl);
2258 }
2259
2260 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_x_f_v_i64m2_mu
2261 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2262 // CHECK-RV64-NEXT: entry:
2263 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2264 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
2265 //
test_vfcvt_x_f_v_i64m2_mu(vbool32_t mask,vint64m2_t maskedoff,vfloat64m2_t src,size_t vl)2266 vint64m2_t test_vfcvt_x_f_v_i64m2_mu(vbool32_t mask, vint64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
2267 return __riscv_vfcvt_x_mu(mask, maskedoff, src, vl);
2268 }
2269
2270 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_x_f_v_i64m4_mu
2271 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2272 // CHECK-RV64-NEXT: entry:
2273 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2274 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
2275 //
test_vfcvt_x_f_v_i64m4_mu(vbool16_t mask,vint64m4_t maskedoff,vfloat64m4_t src,size_t vl)2276 vint64m4_t test_vfcvt_x_f_v_i64m4_mu(vbool16_t mask, vint64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
2277 return __riscv_vfcvt_x_mu(mask, maskedoff, src, vl);
2278 }
2279
2280 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_x_f_v_i64m8_mu
2281 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2282 // CHECK-RV64-NEXT: entry:
2283 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2284 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
2285 //
test_vfcvt_x_f_v_i64m8_mu(vbool8_t mask,vint64m8_t maskedoff,vfloat64m8_t src,size_t vl)2286 vint64m8_t test_vfcvt_x_f_v_i64m8_mu(vbool8_t mask, vint64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
2287 return __riscv_vfcvt_x_mu(mask, maskedoff, src, vl);
2288 }
2289
2290 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_xu_f_v_u64m1_mu
2291 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2292 // CHECK-RV64-NEXT: entry:
2293 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2294 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
2295 //
test_vfcvt_xu_f_v_u64m1_mu(vbool64_t mask,vuint64m1_t maskedoff,vfloat64m1_t src,size_t vl)2296 vuint64m1_t test_vfcvt_xu_f_v_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
2297 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, vl);
2298 }
2299
2300 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_xu_f_v_u64m2_mu
2301 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2302 // CHECK-RV64-NEXT: entry:
2303 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2304 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
2305 //
test_vfcvt_xu_f_v_u64m2_mu(vbool32_t mask,vuint64m2_t maskedoff,vfloat64m2_t src,size_t vl)2306 vuint64m2_t test_vfcvt_xu_f_v_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
2307 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, vl);
2308 }
2309
2310 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_xu_f_v_u64m4_mu
2311 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2312 // CHECK-RV64-NEXT: entry:
2313 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2314 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
2315 //
test_vfcvt_xu_f_v_u64m4_mu(vbool16_t mask,vuint64m4_t maskedoff,vfloat64m4_t src,size_t vl)2316 vuint64m4_t test_vfcvt_xu_f_v_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
2317 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, vl);
2318 }
2319
2320 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_xu_f_v_u64m8_mu
2321 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2322 // CHECK-RV64-NEXT: entry:
2323 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2324 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
2325 //
test_vfcvt_xu_f_v_u64m8_mu(vbool8_t mask,vuint64m8_t maskedoff,vfloat64m8_t src,size_t vl)2326 vuint64m8_t test_vfcvt_xu_f_v_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
2327 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, vl);
2328 }
2329
2330 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_x_v_f64m1_mu
2331 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2332 // CHECK-RV64-NEXT: entry:
2333 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f64.nxv1i64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2334 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
2335 //
test_vfcvt_f_x_v_f64m1_mu(vbool64_t mask,vfloat64m1_t maskedoff,vint64m1_t src,size_t vl)2336 vfloat64m1_t test_vfcvt_f_x_v_f64m1_mu(vbool64_t mask, vfloat64m1_t maskedoff, vint64m1_t src, size_t vl) {
2337 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2338 }
2339
2340 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_x_v_f64m2_mu
2341 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2342 // CHECK-RV64-NEXT: entry:
2343 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f64.nxv2i64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2344 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
2345 //
test_vfcvt_f_x_v_f64m2_mu(vbool32_t mask,vfloat64m2_t maskedoff,vint64m2_t src,size_t vl)2346 vfloat64m2_t test_vfcvt_f_x_v_f64m2_mu(vbool32_t mask, vfloat64m2_t maskedoff, vint64m2_t src, size_t vl) {
2347 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2348 }
2349
2350 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_x_v_f64m4_mu
2351 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2352 // CHECK-RV64-NEXT: entry:
2353 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f64.nxv4i64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2354 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
2355 //
test_vfcvt_f_x_v_f64m4_mu(vbool16_t mask,vfloat64m4_t maskedoff,vint64m4_t src,size_t vl)2356 vfloat64m4_t test_vfcvt_f_x_v_f64m4_mu(vbool16_t mask, vfloat64m4_t maskedoff, vint64m4_t src, size_t vl) {
2357 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2358 }
2359
2360 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_x_v_f64m8_mu
2361 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2362 // CHECK-RV64-NEXT: entry:
2363 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f64.nxv8i64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2364 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
2365 //
test_vfcvt_f_x_v_f64m8_mu(vbool8_t mask,vfloat64m8_t maskedoff,vint64m8_t src,size_t vl)2366 vfloat64m8_t test_vfcvt_f_x_v_f64m8_mu(vbool8_t mask, vfloat64m8_t maskedoff, vint64m8_t src, size_t vl) {
2367 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2368 }
2369
2370 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_xu_v_f64m1_mu
2371 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2372 // CHECK-RV64-NEXT: entry:
2373 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f64.nxv1i64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2374 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
2375 //
test_vfcvt_f_xu_v_f64m1_mu(vbool64_t mask,vfloat64m1_t maskedoff,vuint64m1_t src,size_t vl)2376 vfloat64m1_t test_vfcvt_f_xu_v_f64m1_mu(vbool64_t mask, vfloat64m1_t maskedoff, vuint64m1_t src, size_t vl) {
2377 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2378 }
2379
2380 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_xu_v_f64m2_mu
2381 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2382 // CHECK-RV64-NEXT: entry:
2383 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f64.nxv2i64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2384 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
2385 //
test_vfcvt_f_xu_v_f64m2_mu(vbool32_t mask,vfloat64m2_t maskedoff,vuint64m2_t src,size_t vl)2386 vfloat64m2_t test_vfcvt_f_xu_v_f64m2_mu(vbool32_t mask, vfloat64m2_t maskedoff, vuint64m2_t src, size_t vl) {
2387 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2388 }
2389
2390 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_xu_v_f64m4_mu
2391 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2392 // CHECK-RV64-NEXT: entry:
2393 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f64.nxv4i64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2394 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
2395 //
test_vfcvt_f_xu_v_f64m4_mu(vbool16_t mask,vfloat64m4_t maskedoff,vuint64m4_t src,size_t vl)2396 vfloat64m4_t test_vfcvt_f_xu_v_f64m4_mu(vbool16_t mask, vfloat64m4_t maskedoff, vuint64m4_t src, size_t vl) {
2397 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2398 }
2399
2400 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_xu_v_f64m8_mu
2401 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2402 // CHECK-RV64-NEXT: entry:
2403 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f64.nxv8i64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
2404 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
2405 //
test_vfcvt_f_xu_v_f64m8_mu(vbool8_t mask,vfloat64m8_t maskedoff,vuint64m8_t src,size_t vl)2406 vfloat64m8_t test_vfcvt_f_xu_v_f64m8_mu(vbool8_t mask, vfloat64m8_t maskedoff, vuint64m8_t src, size_t vl) {
2407 return __riscv_vfcvt_f_mu(mask, maskedoff, src, vl);
2408 }
2409
2410 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_rm_tu
2411 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2412 // CHECK-RV64-NEXT: entry:
2413 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], i64 0, i64 [[VL]])
2414 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
2415 //
test_vfcvt_x_f_v_i16mf4_rm_tu(vint16mf4_t maskedoff,vfloat16mf4_t src,size_t vl)2416 vint16mf4_t test_vfcvt_x_f_v_i16mf4_rm_tu(vint16mf4_t maskedoff, vfloat16mf4_t src, size_t vl) {
2417 return __riscv_vfcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2418 }
2419
2420 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_rm_tu
2421 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2422 // CHECK-RV64-NEXT: entry:
2423 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], i64 0, i64 [[VL]])
2424 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
2425 //
test_vfcvt_x_f_v_i16mf2_rm_tu(vint16mf2_t maskedoff,vfloat16mf2_t src,size_t vl)2426 vint16mf2_t test_vfcvt_x_f_v_i16mf2_rm_tu(vint16mf2_t maskedoff, vfloat16mf2_t src, size_t vl) {
2427 return __riscv_vfcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2428 }
2429
2430 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_rm_tu
2431 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2432 // CHECK-RV64-NEXT: entry:
2433 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], i64 0, i64 [[VL]])
2434 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
2435 //
test_vfcvt_x_f_v_i16m1_rm_tu(vint16m1_t maskedoff,vfloat16m1_t src,size_t vl)2436 vint16m1_t test_vfcvt_x_f_v_i16m1_rm_tu(vint16m1_t maskedoff, vfloat16m1_t src, size_t vl) {
2437 return __riscv_vfcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2438 }
2439
2440 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_rm_tu
2441 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2442 // CHECK-RV64-NEXT: entry:
2443 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], i64 0, i64 [[VL]])
2444 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
2445 //
test_vfcvt_x_f_v_i16m2_rm_tu(vint16m2_t maskedoff,vfloat16m2_t src,size_t vl)2446 vint16m2_t test_vfcvt_x_f_v_i16m2_rm_tu(vint16m2_t maskedoff, vfloat16m2_t src, size_t vl) {
2447 return __riscv_vfcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2448 }
2449
2450 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_rm_tu
2451 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2452 // CHECK-RV64-NEXT: entry:
2453 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], i64 0, i64 [[VL]])
2454 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
2455 //
test_vfcvt_x_f_v_i16m4_rm_tu(vint16m4_t maskedoff,vfloat16m4_t src,size_t vl)2456 vint16m4_t test_vfcvt_x_f_v_i16m4_rm_tu(vint16m4_t maskedoff, vfloat16m4_t src, size_t vl) {
2457 return __riscv_vfcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2458 }
2459
2460 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_rm_tu
2461 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2462 // CHECK-RV64-NEXT: entry:
2463 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], i64 0, i64 [[VL]])
2464 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
2465 //
test_vfcvt_x_f_v_i16m8_rm_tu(vint16m8_t maskedoff,vfloat16m8_t src,size_t vl)2466 vint16m8_t test_vfcvt_x_f_v_i16m8_rm_tu(vint16m8_t maskedoff, vfloat16m8_t src, size_t vl) {
2467 return __riscv_vfcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2468 }
2469
2470 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_rm_tu
2471 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2472 // CHECK-RV64-NEXT: entry:
2473 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], i64 0, i64 [[VL]])
2474 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
2475 //
test_vfcvt_xu_f_v_u16mf4_rm_tu(vuint16mf4_t maskedoff,vfloat16mf4_t src,size_t vl)2476 vuint16mf4_t test_vfcvt_xu_f_v_u16mf4_rm_tu(vuint16mf4_t maskedoff, vfloat16mf4_t src, size_t vl) {
2477 return __riscv_vfcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2478 }
2479
2480 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_rm_tu
2481 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2482 // CHECK-RV64-NEXT: entry:
2483 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], i64 0, i64 [[VL]])
2484 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
2485 //
test_vfcvt_xu_f_v_u16mf2_rm_tu(vuint16mf2_t maskedoff,vfloat16mf2_t src,size_t vl)2486 vuint16mf2_t test_vfcvt_xu_f_v_u16mf2_rm_tu(vuint16mf2_t maskedoff, vfloat16mf2_t src, size_t vl) {
2487 return __riscv_vfcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2488 }
2489
2490 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_rm_tu
2491 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2492 // CHECK-RV64-NEXT: entry:
2493 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], i64 0, i64 [[VL]])
2494 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
2495 //
test_vfcvt_xu_f_v_u16m1_rm_tu(vuint16m1_t maskedoff,vfloat16m1_t src,size_t vl)2496 vuint16m1_t test_vfcvt_xu_f_v_u16m1_rm_tu(vuint16m1_t maskedoff, vfloat16m1_t src, size_t vl) {
2497 return __riscv_vfcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2498 }
2499
2500 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_rm_tu
2501 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2502 // CHECK-RV64-NEXT: entry:
2503 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], i64 0, i64 [[VL]])
2504 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
2505 //
test_vfcvt_xu_f_v_u16m2_rm_tu(vuint16m2_t maskedoff,vfloat16m2_t src,size_t vl)2506 vuint16m2_t test_vfcvt_xu_f_v_u16m2_rm_tu(vuint16m2_t maskedoff, vfloat16m2_t src, size_t vl) {
2507 return __riscv_vfcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2508 }
2509
2510 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4_rm_tu
2511 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2512 // CHECK-RV64-NEXT: entry:
2513 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], i64 0, i64 [[VL]])
2514 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
2515 //
test_vfcvt_xu_f_v_u16m4_rm_tu(vuint16m4_t maskedoff,vfloat16m4_t src,size_t vl)2516 vuint16m4_t test_vfcvt_xu_f_v_u16m4_rm_tu(vuint16m4_t maskedoff, vfloat16m4_t src, size_t vl) {
2517 return __riscv_vfcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2518 }
2519
2520 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8_rm_tu
2521 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2522 // CHECK-RV64-NEXT: entry:
2523 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], i64 0, i64 [[VL]])
2524 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
2525 //
test_vfcvt_xu_f_v_u16m8_rm_tu(vuint16m8_t maskedoff,vfloat16m8_t src,size_t vl)2526 vuint16m8_t test_vfcvt_xu_f_v_u16m8_rm_tu(vuint16m8_t maskedoff, vfloat16m8_t src, size_t vl) {
2527 return __riscv_vfcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2528 }
2529
2530 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_x_v_f16mf4_rm_tu
2531 // CHECK-RV64-SAME: (<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2532 // CHECK-RV64-NEXT: entry:
2533 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], i64 0, i64 [[VL]])
2534 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
2535 //
test_vfcvt_f_x_v_f16mf4_rm_tu(vfloat16mf4_t maskedoff,vint16mf4_t src,size_t vl)2536 vfloat16mf4_t test_vfcvt_f_x_v_f16mf4_rm_tu(vfloat16mf4_t maskedoff, vint16mf4_t src, size_t vl) {
2537 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2538 }
2539
2540 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_x_v_f16mf2_rm_tu
2541 // CHECK-RV64-SAME: (<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2542 // CHECK-RV64-NEXT: entry:
2543 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], i64 0, i64 [[VL]])
2544 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
2545 //
test_vfcvt_f_x_v_f16mf2_rm_tu(vfloat16mf2_t maskedoff,vint16mf2_t src,size_t vl)2546 vfloat16mf2_t test_vfcvt_f_x_v_f16mf2_rm_tu(vfloat16mf2_t maskedoff, vint16mf2_t src, size_t vl) {
2547 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2548 }
2549
2550 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_x_v_f16m1_rm_tu
2551 // CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2552 // CHECK-RV64-NEXT: entry:
2553 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], i64 0, i64 [[VL]])
2554 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
2555 //
test_vfcvt_f_x_v_f16m1_rm_tu(vfloat16m1_t maskedoff,vint16m1_t src,size_t vl)2556 vfloat16m1_t test_vfcvt_f_x_v_f16m1_rm_tu(vfloat16m1_t maskedoff, vint16m1_t src, size_t vl) {
2557 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2558 }
2559
2560 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_x_v_f16m2_rm_tu
2561 // CHECK-RV64-SAME: (<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2562 // CHECK-RV64-NEXT: entry:
2563 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], i64 0, i64 [[VL]])
2564 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
2565 //
test_vfcvt_f_x_v_f16m2_rm_tu(vfloat16m2_t maskedoff,vint16m2_t src,size_t vl)2566 vfloat16m2_t test_vfcvt_f_x_v_f16m2_rm_tu(vfloat16m2_t maskedoff, vint16m2_t src, size_t vl) {
2567 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2568 }
2569
2570 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_x_v_f16m4_rm_tu
2571 // CHECK-RV64-SAME: (<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2572 // CHECK-RV64-NEXT: entry:
2573 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], i64 0, i64 [[VL]])
2574 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
2575 //
test_vfcvt_f_x_v_f16m4_rm_tu(vfloat16m4_t maskedoff,vint16m4_t src,size_t vl)2576 vfloat16m4_t test_vfcvt_f_x_v_f16m4_rm_tu(vfloat16m4_t maskedoff, vint16m4_t src, size_t vl) {
2577 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2578 }
2579
2580 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_x_v_f16m8_rm_tu
2581 // CHECK-RV64-SAME: (<vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2582 // CHECK-RV64-NEXT: entry:
2583 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i16> [[SRC]], i64 0, i64 [[VL]])
2584 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
2585 //
test_vfcvt_f_x_v_f16m8_rm_tu(vfloat16m8_t maskedoff,vint16m8_t src,size_t vl)2586 vfloat16m8_t test_vfcvt_f_x_v_f16m8_rm_tu(vfloat16m8_t maskedoff, vint16m8_t src, size_t vl) {
2587 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2588 }
2589
2590 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_xu_v_f16mf4_rm_tu
2591 // CHECK-RV64-SAME: (<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2592 // CHECK-RV64-NEXT: entry:
2593 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], i64 0, i64 [[VL]])
2594 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
2595 //
test_vfcvt_f_xu_v_f16mf4_rm_tu(vfloat16mf4_t maskedoff,vuint16mf4_t src,size_t vl)2596 vfloat16mf4_t test_vfcvt_f_xu_v_f16mf4_rm_tu(vfloat16mf4_t maskedoff, vuint16mf4_t src, size_t vl) {
2597 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2598 }
2599
2600 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_xu_v_f16mf2_rm_tu
2601 // CHECK-RV64-SAME: (<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2602 // CHECK-RV64-NEXT: entry:
2603 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], i64 0, i64 [[VL]])
2604 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
2605 //
test_vfcvt_f_xu_v_f16mf2_rm_tu(vfloat16mf2_t maskedoff,vuint16mf2_t src,size_t vl)2606 vfloat16mf2_t test_vfcvt_f_xu_v_f16mf2_rm_tu(vfloat16mf2_t maskedoff, vuint16mf2_t src, size_t vl) {
2607 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2608 }
2609
2610 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_xu_v_f16m1_rm_tu
2611 // CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2612 // CHECK-RV64-NEXT: entry:
2613 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], i64 0, i64 [[VL]])
2614 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
2615 //
test_vfcvt_f_xu_v_f16m1_rm_tu(vfloat16m1_t maskedoff,vuint16m1_t src,size_t vl)2616 vfloat16m1_t test_vfcvt_f_xu_v_f16m1_rm_tu(vfloat16m1_t maskedoff, vuint16m1_t src, size_t vl) {
2617 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2618 }
2619
2620 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_xu_v_f16m2_rm_tu
2621 // CHECK-RV64-SAME: (<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2622 // CHECK-RV64-NEXT: entry:
2623 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], i64 0, i64 [[VL]])
2624 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
2625 //
test_vfcvt_f_xu_v_f16m2_rm_tu(vfloat16m2_t maskedoff,vuint16m2_t src,size_t vl)2626 vfloat16m2_t test_vfcvt_f_xu_v_f16m2_rm_tu(vfloat16m2_t maskedoff, vuint16m2_t src, size_t vl) {
2627 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2628 }
2629
2630 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_xu_v_f16m4_rm_tu
2631 // CHECK-RV64-SAME: (<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2632 // CHECK-RV64-NEXT: entry:
2633 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], i64 0, i64 [[VL]])
2634 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
2635 //
test_vfcvt_f_xu_v_f16m4_rm_tu(vfloat16m4_t maskedoff,vuint16m4_t src,size_t vl)2636 vfloat16m4_t test_vfcvt_f_xu_v_f16m4_rm_tu(vfloat16m4_t maskedoff, vuint16m4_t src, size_t vl) {
2637 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2638 }
2639
2640 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_xu_v_f16m8_rm_tu
2641 // CHECK-RV64-SAME: (<vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2642 // CHECK-RV64-NEXT: entry:
2643 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i16> [[SRC]], i64 0, i64 [[VL]])
2644 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
2645 //
test_vfcvt_f_xu_v_f16m8_rm_tu(vfloat16m8_t maskedoff,vuint16m8_t src,size_t vl)2646 vfloat16m8_t test_vfcvt_f_xu_v_f16m8_rm_tu(vfloat16m8_t maskedoff, vuint16m8_t src, size_t vl) {
2647 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2648 }
2649
2650 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_x_f_v_i32mf2_rm_tu
2651 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2652 // CHECK-RV64-NEXT: entry:
2653 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], i64 0, i64 [[VL]])
2654 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
2655 //
test_vfcvt_x_f_v_i32mf2_rm_tu(vint32mf2_t maskedoff,vfloat32mf2_t src,size_t vl)2656 vint32mf2_t test_vfcvt_x_f_v_i32mf2_rm_tu(vint32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
2657 return __riscv_vfcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2658 }
2659
2660 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_x_f_v_i32m1_rm_tu
2661 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2662 // CHECK-RV64-NEXT: entry:
2663 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], i64 0, i64 [[VL]])
2664 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
2665 //
test_vfcvt_x_f_v_i32m1_rm_tu(vint32m1_t maskedoff,vfloat32m1_t src,size_t vl)2666 vint32m1_t test_vfcvt_x_f_v_i32m1_rm_tu(vint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
2667 return __riscv_vfcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2668 }
2669
2670 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_x_f_v_i32m2_rm_tu
2671 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2672 // CHECK-RV64-NEXT: entry:
2673 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], i64 0, i64 [[VL]])
2674 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
2675 //
test_vfcvt_x_f_v_i32m2_rm_tu(vint32m2_t maskedoff,vfloat32m2_t src,size_t vl)2676 vint32m2_t test_vfcvt_x_f_v_i32m2_rm_tu(vint32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
2677 return __riscv_vfcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2678 }
2679
2680 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_x_f_v_i32m4_rm_tu
2681 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2682 // CHECK-RV64-NEXT: entry:
2683 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], i64 0, i64 [[VL]])
2684 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
2685 //
test_vfcvt_x_f_v_i32m4_rm_tu(vint32m4_t maskedoff,vfloat32m4_t src,size_t vl)2686 vint32m4_t test_vfcvt_x_f_v_i32m4_rm_tu(vint32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
2687 return __riscv_vfcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2688 }
2689
2690 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_x_f_v_i32m8_rm_tu
2691 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2692 // CHECK-RV64-NEXT: entry:
2693 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], i64 0, i64 [[VL]])
2694 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
2695 //
test_vfcvt_x_f_v_i32m8_rm_tu(vint32m8_t maskedoff,vfloat32m8_t src,size_t vl)2696 vint32m8_t test_vfcvt_x_f_v_i32m8_rm_tu(vint32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
2697 return __riscv_vfcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2698 }
2699
2700 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_xu_f_v_u32mf2_rm_tu
2701 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2702 // CHECK-RV64-NEXT: entry:
2703 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], i64 0, i64 [[VL]])
2704 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
2705 //
test_vfcvt_xu_f_v_u32mf2_rm_tu(vuint32mf2_t maskedoff,vfloat32mf2_t src,size_t vl)2706 vuint32mf2_t test_vfcvt_xu_f_v_u32mf2_rm_tu(vuint32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
2707 return __riscv_vfcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2708 }
2709
2710 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_xu_f_v_u32m1_rm_tu
2711 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2712 // CHECK-RV64-NEXT: entry:
2713 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], i64 0, i64 [[VL]])
2714 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
2715 //
test_vfcvt_xu_f_v_u32m1_rm_tu(vuint32m1_t maskedoff,vfloat32m1_t src,size_t vl)2716 vuint32m1_t test_vfcvt_xu_f_v_u32m1_rm_tu(vuint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
2717 return __riscv_vfcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2718 }
2719
2720 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_xu_f_v_u32m2_rm_tu
2721 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2722 // CHECK-RV64-NEXT: entry:
2723 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], i64 0, i64 [[VL]])
2724 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
2725 //
test_vfcvt_xu_f_v_u32m2_rm_tu(vuint32m2_t maskedoff,vfloat32m2_t src,size_t vl)2726 vuint32m2_t test_vfcvt_xu_f_v_u32m2_rm_tu(vuint32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
2727 return __riscv_vfcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2728 }
2729
2730 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_xu_f_v_u32m4_rm_tu
2731 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2732 // CHECK-RV64-NEXT: entry:
2733 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], i64 0, i64 [[VL]])
2734 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
2735 //
test_vfcvt_xu_f_v_u32m4_rm_tu(vuint32m4_t maskedoff,vfloat32m4_t src,size_t vl)2736 vuint32m4_t test_vfcvt_xu_f_v_u32m4_rm_tu(vuint32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
2737 return __riscv_vfcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2738 }
2739
2740 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_xu_f_v_u32m8_rm_tu
2741 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2742 // CHECK-RV64-NEXT: entry:
2743 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], i64 0, i64 [[VL]])
2744 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
2745 //
test_vfcvt_xu_f_v_u32m8_rm_tu(vuint32m8_t maskedoff,vfloat32m8_t src,size_t vl)2746 vuint32m8_t test_vfcvt_xu_f_v_u32m8_rm_tu(vuint32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
2747 return __riscv_vfcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2748 }
2749
2750 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_x_v_f32mf2_rm_tu
2751 // CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2752 // CHECK-RV64-NEXT: entry:
2753 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], i64 0, i64 [[VL]])
2754 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
2755 //
test_vfcvt_f_x_v_f32mf2_rm_tu(vfloat32mf2_t maskedoff,vint32mf2_t src,size_t vl)2756 vfloat32mf2_t test_vfcvt_f_x_v_f32mf2_rm_tu(vfloat32mf2_t maskedoff, vint32mf2_t src, size_t vl) {
2757 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2758 }
2759
2760 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_x_v_f32m1_rm_tu
2761 // CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2762 // CHECK-RV64-NEXT: entry:
2763 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], i64 0, i64 [[VL]])
2764 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
2765 //
test_vfcvt_f_x_v_f32m1_rm_tu(vfloat32m1_t maskedoff,vint32m1_t src,size_t vl)2766 vfloat32m1_t test_vfcvt_f_x_v_f32m1_rm_tu(vfloat32m1_t maskedoff, vint32m1_t src, size_t vl) {
2767 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2768 }
2769
2770 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_x_v_f32m2_rm_tu
2771 // CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2772 // CHECK-RV64-NEXT: entry:
2773 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], i64 0, i64 [[VL]])
2774 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
2775 //
test_vfcvt_f_x_v_f32m2_rm_tu(vfloat32m2_t maskedoff,vint32m2_t src,size_t vl)2776 vfloat32m2_t test_vfcvt_f_x_v_f32m2_rm_tu(vfloat32m2_t maskedoff, vint32m2_t src, size_t vl) {
2777 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2778 }
2779
2780 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_x_v_f32m4_rm_tu
2781 // CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2782 // CHECK-RV64-NEXT: entry:
2783 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], i64 0, i64 [[VL]])
2784 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
2785 //
test_vfcvt_f_x_v_f32m4_rm_tu(vfloat32m4_t maskedoff,vint32m4_t src,size_t vl)2786 vfloat32m4_t test_vfcvt_f_x_v_f32m4_rm_tu(vfloat32m4_t maskedoff, vint32m4_t src, size_t vl) {
2787 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2788 }
2789
2790 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_x_v_f32m8_rm_tu
2791 // CHECK-RV64-SAME: (<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2792 // CHECK-RV64-NEXT: entry:
2793 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], i64 0, i64 [[VL]])
2794 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
2795 //
test_vfcvt_f_x_v_f32m8_rm_tu(vfloat32m8_t maskedoff,vint32m8_t src,size_t vl)2796 vfloat32m8_t test_vfcvt_f_x_v_f32m8_rm_tu(vfloat32m8_t maskedoff, vint32m8_t src, size_t vl) {
2797 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2798 }
2799
2800 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_xu_v_f32mf2_rm_tu
2801 // CHECK-RV64-SAME: (<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2802 // CHECK-RV64-NEXT: entry:
2803 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], i64 0, i64 [[VL]])
2804 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
2805 //
test_vfcvt_f_xu_v_f32mf2_rm_tu(vfloat32mf2_t maskedoff,vuint32mf2_t src,size_t vl)2806 vfloat32mf2_t test_vfcvt_f_xu_v_f32mf2_rm_tu(vfloat32mf2_t maskedoff, vuint32mf2_t src, size_t vl) {
2807 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2808 }
2809
2810 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_xu_v_f32m1_rm_tu
2811 // CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2812 // CHECK-RV64-NEXT: entry:
2813 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], i64 0, i64 [[VL]])
2814 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
2815 //
test_vfcvt_f_xu_v_f32m1_rm_tu(vfloat32m1_t maskedoff,vuint32m1_t src,size_t vl)2816 vfloat32m1_t test_vfcvt_f_xu_v_f32m1_rm_tu(vfloat32m1_t maskedoff, vuint32m1_t src, size_t vl) {
2817 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2818 }
2819
2820 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_xu_v_f32m2_rm_tu
2821 // CHECK-RV64-SAME: (<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2822 // CHECK-RV64-NEXT: entry:
2823 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], i64 0, i64 [[VL]])
2824 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
2825 //
test_vfcvt_f_xu_v_f32m2_rm_tu(vfloat32m2_t maskedoff,vuint32m2_t src,size_t vl)2826 vfloat32m2_t test_vfcvt_f_xu_v_f32m2_rm_tu(vfloat32m2_t maskedoff, vuint32m2_t src, size_t vl) {
2827 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2828 }
2829
2830 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_xu_v_f32m4_rm_tu
2831 // CHECK-RV64-SAME: (<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2832 // CHECK-RV64-NEXT: entry:
2833 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], i64 0, i64 [[VL]])
2834 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
2835 //
test_vfcvt_f_xu_v_f32m4_rm_tu(vfloat32m4_t maskedoff,vuint32m4_t src,size_t vl)2836 vfloat32m4_t test_vfcvt_f_xu_v_f32m4_rm_tu(vfloat32m4_t maskedoff, vuint32m4_t src, size_t vl) {
2837 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2838 }
2839
2840 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_xu_v_f32m8_rm_tu
2841 // CHECK-RV64-SAME: (<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2842 // CHECK-RV64-NEXT: entry:
2843 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], i64 0, i64 [[VL]])
2844 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
2845 //
test_vfcvt_f_xu_v_f32m8_rm_tu(vfloat32m8_t maskedoff,vuint32m8_t src,size_t vl)2846 vfloat32m8_t test_vfcvt_f_xu_v_f32m8_rm_tu(vfloat32m8_t maskedoff, vuint32m8_t src, size_t vl) {
2847 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2848 }
2849
2850 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_x_f_v_i64m1_rm_tu
2851 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2852 // CHECK-RV64-NEXT: entry:
2853 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], i64 0, i64 [[VL]])
2854 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
2855 //
test_vfcvt_x_f_v_i64m1_rm_tu(vint64m1_t maskedoff,vfloat64m1_t src,size_t vl)2856 vint64m1_t test_vfcvt_x_f_v_i64m1_rm_tu(vint64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
2857 return __riscv_vfcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2858 }
2859
2860 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_x_f_v_i64m2_rm_tu
2861 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2862 // CHECK-RV64-NEXT: entry:
2863 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], i64 0, i64 [[VL]])
2864 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
2865 //
test_vfcvt_x_f_v_i64m2_rm_tu(vint64m2_t maskedoff,vfloat64m2_t src,size_t vl)2866 vint64m2_t test_vfcvt_x_f_v_i64m2_rm_tu(vint64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
2867 return __riscv_vfcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2868 }
2869
2870 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_x_f_v_i64m4_rm_tu
2871 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2872 // CHECK-RV64-NEXT: entry:
2873 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], i64 0, i64 [[VL]])
2874 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
2875 //
test_vfcvt_x_f_v_i64m4_rm_tu(vint64m4_t maskedoff,vfloat64m4_t src,size_t vl)2876 vint64m4_t test_vfcvt_x_f_v_i64m4_rm_tu(vint64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
2877 return __riscv_vfcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2878 }
2879
2880 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_x_f_v_i64m8_rm_tu
2881 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2882 // CHECK-RV64-NEXT: entry:
2883 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], i64 0, i64 [[VL]])
2884 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
2885 //
test_vfcvt_x_f_v_i64m8_rm_tu(vint64m8_t maskedoff,vfloat64m8_t src,size_t vl)2886 vint64m8_t test_vfcvt_x_f_v_i64m8_rm_tu(vint64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
2887 return __riscv_vfcvt_x_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2888 }
2889
2890 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_xu_f_v_u64m1_rm_tu
2891 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2892 // CHECK-RV64-NEXT: entry:
2893 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], i64 0, i64 [[VL]])
2894 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
2895 //
test_vfcvt_xu_f_v_u64m1_rm_tu(vuint64m1_t maskedoff,vfloat64m1_t src,size_t vl)2896 vuint64m1_t test_vfcvt_xu_f_v_u64m1_rm_tu(vuint64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
2897 return __riscv_vfcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2898 }
2899
2900 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_xu_f_v_u64m2_rm_tu
2901 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2902 // CHECK-RV64-NEXT: entry:
2903 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], i64 0, i64 [[VL]])
2904 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
2905 //
test_vfcvt_xu_f_v_u64m2_rm_tu(vuint64m2_t maskedoff,vfloat64m2_t src,size_t vl)2906 vuint64m2_t test_vfcvt_xu_f_v_u64m2_rm_tu(vuint64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
2907 return __riscv_vfcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2908 }
2909
2910 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_xu_f_v_u64m4_rm_tu
2911 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2912 // CHECK-RV64-NEXT: entry:
2913 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], i64 0, i64 [[VL]])
2914 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
2915 //
test_vfcvt_xu_f_v_u64m4_rm_tu(vuint64m4_t maskedoff,vfloat64m4_t src,size_t vl)2916 vuint64m4_t test_vfcvt_xu_f_v_u64m4_rm_tu(vuint64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
2917 return __riscv_vfcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2918 }
2919
2920 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_xu_f_v_u64m8_rm_tu
2921 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2922 // CHECK-RV64-NEXT: entry:
2923 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], i64 0, i64 [[VL]])
2924 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
2925 //
test_vfcvt_xu_f_v_u64m8_rm_tu(vuint64m8_t maskedoff,vfloat64m8_t src,size_t vl)2926 vuint64m8_t test_vfcvt_xu_f_v_u64m8_rm_tu(vuint64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
2927 return __riscv_vfcvt_xu_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2928 }
2929
2930 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_x_v_f64m1_rm_tu
2931 // CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2932 // CHECK-RV64-NEXT: entry:
2933 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.nxv1f64.nxv1i64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], i64 0, i64 [[VL]])
2934 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
2935 //
test_vfcvt_f_x_v_f64m1_rm_tu(vfloat64m1_t maskedoff,vint64m1_t src,size_t vl)2936 vfloat64m1_t test_vfcvt_f_x_v_f64m1_rm_tu(vfloat64m1_t maskedoff, vint64m1_t src, size_t vl) {
2937 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2938 }
2939
2940 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_x_v_f64m2_rm_tu
2941 // CHECK-RV64-SAME: (<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2942 // CHECK-RV64-NEXT: entry:
2943 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.nxv2f64.nxv2i64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], i64 0, i64 [[VL]])
2944 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
2945 //
test_vfcvt_f_x_v_f64m2_rm_tu(vfloat64m2_t maskedoff,vint64m2_t src,size_t vl)2946 vfloat64m2_t test_vfcvt_f_x_v_f64m2_rm_tu(vfloat64m2_t maskedoff, vint64m2_t src, size_t vl) {
2947 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2948 }
2949
2950 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_x_v_f64m4_rm_tu
2951 // CHECK-RV64-SAME: (<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2952 // CHECK-RV64-NEXT: entry:
2953 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.nxv4f64.nxv4i64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], i64 0, i64 [[VL]])
2954 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
2955 //
test_vfcvt_f_x_v_f64m4_rm_tu(vfloat64m4_t maskedoff,vint64m4_t src,size_t vl)2956 vfloat64m4_t test_vfcvt_f_x_v_f64m4_rm_tu(vfloat64m4_t maskedoff, vint64m4_t src, size_t vl) {
2957 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2958 }
2959
2960 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_x_v_f64m8_rm_tu
2961 // CHECK-RV64-SAME: (<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2962 // CHECK-RV64-NEXT: entry:
2963 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.nxv8f64.nxv8i64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], i64 0, i64 [[VL]])
2964 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
2965 //
test_vfcvt_f_x_v_f64m8_rm_tu(vfloat64m8_t maskedoff,vint64m8_t src,size_t vl)2966 vfloat64m8_t test_vfcvt_f_x_v_f64m8_rm_tu(vfloat64m8_t maskedoff, vint64m8_t src, size_t vl) {
2967 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2968 }
2969
2970 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_xu_v_f64m1_rm_tu
2971 // CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2972 // CHECK-RV64-NEXT: entry:
2973 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.nxv1f64.nxv1i64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], i64 0, i64 [[VL]])
2974 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
2975 //
test_vfcvt_f_xu_v_f64m1_rm_tu(vfloat64m1_t maskedoff,vuint64m1_t src,size_t vl)2976 vfloat64m1_t test_vfcvt_f_xu_v_f64m1_rm_tu(vfloat64m1_t maskedoff, vuint64m1_t src, size_t vl) {
2977 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2978 }
2979
2980 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_xu_v_f64m2_rm_tu
2981 // CHECK-RV64-SAME: (<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2982 // CHECK-RV64-NEXT: entry:
2983 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.nxv2f64.nxv2i64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], i64 0, i64 [[VL]])
2984 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
2985 //
test_vfcvt_f_xu_v_f64m2_rm_tu(vfloat64m2_t maskedoff,vuint64m2_t src,size_t vl)2986 vfloat64m2_t test_vfcvt_f_xu_v_f64m2_rm_tu(vfloat64m2_t maskedoff, vuint64m2_t src, size_t vl) {
2987 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2988 }
2989
2990 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_xu_v_f64m4_rm_tu
2991 // CHECK-RV64-SAME: (<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2992 // CHECK-RV64-NEXT: entry:
2993 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.nxv4f64.nxv4i64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], i64 0, i64 [[VL]])
2994 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
2995 //
test_vfcvt_f_xu_v_f64m4_rm_tu(vfloat64m4_t maskedoff,vuint64m4_t src,size_t vl)2996 vfloat64m4_t test_vfcvt_f_xu_v_f64m4_rm_tu(vfloat64m4_t maskedoff, vuint64m4_t src, size_t vl) {
2997 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
2998 }
2999
3000 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_xu_v_f64m8_rm_tu
3001 // CHECK-RV64-SAME: (<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3002 // CHECK-RV64-NEXT: entry:
3003 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.nxv8f64.nxv8i64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], i64 0, i64 [[VL]])
3004 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
3005 //
test_vfcvt_f_xu_v_f64m8_rm_tu(vfloat64m8_t maskedoff,vuint64m8_t src,size_t vl)3006 vfloat64m8_t test_vfcvt_f_xu_v_f64m8_rm_tu(vfloat64m8_t maskedoff, vuint64m8_t src, size_t vl) {
3007 return __riscv_vfcvt_f_tu(maskedoff, src, __RISCV_FRM_RNE, vl);
3008 }
3009
3010 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_rm_tum
3011 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3012 // CHECK-RV64-NEXT: entry:
3013 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3014 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
3015 //
test_vfcvt_x_f_v_i16mf4_rm_tum(vbool64_t mask,vint16mf4_t maskedoff,vfloat16mf4_t src,size_t vl)3016 vint16mf4_t test_vfcvt_x_f_v_i16mf4_rm_tum(vbool64_t mask, vint16mf4_t maskedoff, vfloat16mf4_t src, size_t vl) {
3017 return __riscv_vfcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3018 }
3019
3020 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_rm_tum
3021 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3022 // CHECK-RV64-NEXT: entry:
3023 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3024 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
3025 //
test_vfcvt_x_f_v_i16mf2_rm_tum(vbool32_t mask,vint16mf2_t maskedoff,vfloat16mf2_t src,size_t vl)3026 vint16mf2_t test_vfcvt_x_f_v_i16mf2_rm_tum(vbool32_t mask, vint16mf2_t maskedoff, vfloat16mf2_t src, size_t vl) {
3027 return __riscv_vfcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3028 }
3029
3030 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_rm_tum
3031 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3032 // CHECK-RV64-NEXT: entry:
3033 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3034 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
3035 //
test_vfcvt_x_f_v_i16m1_rm_tum(vbool16_t mask,vint16m1_t maskedoff,vfloat16m1_t src,size_t vl)3036 vint16m1_t test_vfcvt_x_f_v_i16m1_rm_tum(vbool16_t mask, vint16m1_t maskedoff, vfloat16m1_t src, size_t vl) {
3037 return __riscv_vfcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3038 }
3039
3040 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_rm_tum
3041 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3042 // CHECK-RV64-NEXT: entry:
3043 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3044 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
3045 //
test_vfcvt_x_f_v_i16m2_rm_tum(vbool8_t mask,vint16m2_t maskedoff,vfloat16m2_t src,size_t vl)3046 vint16m2_t test_vfcvt_x_f_v_i16m2_rm_tum(vbool8_t mask, vint16m2_t maskedoff, vfloat16m2_t src, size_t vl) {
3047 return __riscv_vfcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3048 }
3049
3050 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_rm_tum
3051 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3052 // CHECK-RV64-NEXT: entry:
3053 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3054 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
3055 //
test_vfcvt_x_f_v_i16m4_rm_tum(vbool4_t mask,vint16m4_t maskedoff,vfloat16m4_t src,size_t vl)3056 vint16m4_t test_vfcvt_x_f_v_i16m4_rm_tum(vbool4_t mask, vint16m4_t maskedoff, vfloat16m4_t src, size_t vl) {
3057 return __riscv_vfcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3058 }
3059
3060 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_rm_tum
3061 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3062 // CHECK-RV64-NEXT: entry:
3063 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3064 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
3065 //
test_vfcvt_x_f_v_i16m8_rm_tum(vbool2_t mask,vint16m8_t maskedoff,vfloat16m8_t src,size_t vl)3066 vint16m8_t test_vfcvt_x_f_v_i16m8_rm_tum(vbool2_t mask, vint16m8_t maskedoff, vfloat16m8_t src, size_t vl) {
3067 return __riscv_vfcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3068 }
3069
3070 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_rm_tum
3071 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3072 // CHECK-RV64-NEXT: entry:
3073 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3074 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
3075 //
test_vfcvt_xu_f_v_u16mf4_rm_tum(vbool64_t mask,vuint16mf4_t maskedoff,vfloat16mf4_t src,size_t vl)3076 vuint16mf4_t test_vfcvt_xu_f_v_u16mf4_rm_tum(vbool64_t mask, vuint16mf4_t maskedoff, vfloat16mf4_t src, size_t vl) {
3077 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3078 }
3079
3080 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_rm_tum
3081 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3082 // CHECK-RV64-NEXT: entry:
3083 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3084 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
3085 //
test_vfcvt_xu_f_v_u16mf2_rm_tum(vbool32_t mask,vuint16mf2_t maskedoff,vfloat16mf2_t src,size_t vl)3086 vuint16mf2_t test_vfcvt_xu_f_v_u16mf2_rm_tum(vbool32_t mask, vuint16mf2_t maskedoff, vfloat16mf2_t src, size_t vl) {
3087 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3088 }
3089
3090 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_rm_tum
3091 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3092 // CHECK-RV64-NEXT: entry:
3093 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3094 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
3095 //
test_vfcvt_xu_f_v_u16m1_rm_tum(vbool16_t mask,vuint16m1_t maskedoff,vfloat16m1_t src,size_t vl)3096 vuint16m1_t test_vfcvt_xu_f_v_u16m1_rm_tum(vbool16_t mask, vuint16m1_t maskedoff, vfloat16m1_t src, size_t vl) {
3097 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3098 }
3099
3100 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_rm_tum
3101 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3102 // CHECK-RV64-NEXT: entry:
3103 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3104 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
3105 //
test_vfcvt_xu_f_v_u16m2_rm_tum(vbool8_t mask,vuint16m2_t maskedoff,vfloat16m2_t src,size_t vl)3106 vuint16m2_t test_vfcvt_xu_f_v_u16m2_rm_tum(vbool8_t mask, vuint16m2_t maskedoff, vfloat16m2_t src, size_t vl) {
3107 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3108 }
3109
3110 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4_rm_tum
3111 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3112 // CHECK-RV64-NEXT: entry:
3113 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3114 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
3115 //
test_vfcvt_xu_f_v_u16m4_rm_tum(vbool4_t mask,vuint16m4_t maskedoff,vfloat16m4_t src,size_t vl)3116 vuint16m4_t test_vfcvt_xu_f_v_u16m4_rm_tum(vbool4_t mask, vuint16m4_t maskedoff, vfloat16m4_t src, size_t vl) {
3117 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3118 }
3119
3120 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8_rm_tum
3121 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3122 // CHECK-RV64-NEXT: entry:
3123 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3124 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
3125 //
test_vfcvt_xu_f_v_u16m8_rm_tum(vbool2_t mask,vuint16m8_t maskedoff,vfloat16m8_t src,size_t vl)3126 vuint16m8_t test_vfcvt_xu_f_v_u16m8_rm_tum(vbool2_t mask, vuint16m8_t maskedoff, vfloat16m8_t src, size_t vl) {
3127 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3128 }
3129
3130 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_x_v_f16mf4_rm_tum
3131 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3132 // CHECK-RV64-NEXT: entry:
3133 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3134 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
3135 //
test_vfcvt_f_x_v_f16mf4_rm_tum(vbool64_t mask,vfloat16mf4_t maskedoff,vint16mf4_t src,size_t vl)3136 vfloat16mf4_t test_vfcvt_f_x_v_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t maskedoff, vint16mf4_t src, size_t vl) {
3137 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3138 }
3139
3140 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_x_v_f16mf2_rm_tum
3141 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3142 // CHECK-RV64-NEXT: entry:
3143 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3144 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
3145 //
test_vfcvt_f_x_v_f16mf2_rm_tum(vbool32_t mask,vfloat16mf2_t maskedoff,vint16mf2_t src,size_t vl)3146 vfloat16mf2_t test_vfcvt_f_x_v_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t maskedoff, vint16mf2_t src, size_t vl) {
3147 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3148 }
3149
3150 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_x_v_f16m1_rm_tum
3151 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3152 // CHECK-RV64-NEXT: entry:
3153 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3154 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
3155 //
test_vfcvt_f_x_v_f16m1_rm_tum(vbool16_t mask,vfloat16m1_t maskedoff,vint16m1_t src,size_t vl)3156 vfloat16m1_t test_vfcvt_f_x_v_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t maskedoff, vint16m1_t src, size_t vl) {
3157 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3158 }
3159
3160 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_x_v_f16m2_rm_tum
3161 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3162 // CHECK-RV64-NEXT: entry:
3163 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3164 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
3165 //
test_vfcvt_f_x_v_f16m2_rm_tum(vbool8_t mask,vfloat16m2_t maskedoff,vint16m2_t src,size_t vl)3166 vfloat16m2_t test_vfcvt_f_x_v_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t maskedoff, vint16m2_t src, size_t vl) {
3167 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3168 }
3169
3170 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_x_v_f16m4_rm_tum
3171 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3172 // CHECK-RV64-NEXT: entry:
3173 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3174 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
3175 //
test_vfcvt_f_x_v_f16m4_rm_tum(vbool4_t mask,vfloat16m4_t maskedoff,vint16m4_t src,size_t vl)3176 vfloat16m4_t test_vfcvt_f_x_v_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t maskedoff, vint16m4_t src, size_t vl) {
3177 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3178 }
3179
3180 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_x_v_f16m8_rm_tum
3181 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3182 // CHECK-RV64-NEXT: entry:
3183 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i16> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3184 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
3185 //
test_vfcvt_f_x_v_f16m8_rm_tum(vbool2_t mask,vfloat16m8_t maskedoff,vint16m8_t src,size_t vl)3186 vfloat16m8_t test_vfcvt_f_x_v_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t maskedoff, vint16m8_t src, size_t vl) {
3187 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3188 }
3189
3190 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_xu_v_f16mf4_rm_tum
3191 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3192 // CHECK-RV64-NEXT: entry:
3193 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3194 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
3195 //
test_vfcvt_f_xu_v_f16mf4_rm_tum(vbool64_t mask,vfloat16mf4_t maskedoff,vuint16mf4_t src,size_t vl)3196 vfloat16mf4_t test_vfcvt_f_xu_v_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t maskedoff, vuint16mf4_t src, size_t vl) {
3197 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3198 }
3199
3200 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_xu_v_f16mf2_rm_tum
3201 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3202 // CHECK-RV64-NEXT: entry:
3203 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3204 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
3205 //
test_vfcvt_f_xu_v_f16mf2_rm_tum(vbool32_t mask,vfloat16mf2_t maskedoff,vuint16mf2_t src,size_t vl)3206 vfloat16mf2_t test_vfcvt_f_xu_v_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t maskedoff, vuint16mf2_t src, size_t vl) {
3207 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3208 }
3209
3210 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_xu_v_f16m1_rm_tum
3211 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3212 // CHECK-RV64-NEXT: entry:
3213 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3214 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
3215 //
test_vfcvt_f_xu_v_f16m1_rm_tum(vbool16_t mask,vfloat16m1_t maskedoff,vuint16m1_t src,size_t vl)3216 vfloat16m1_t test_vfcvt_f_xu_v_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t maskedoff, vuint16m1_t src, size_t vl) {
3217 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3218 }
3219
3220 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_xu_v_f16m2_rm_tum
3221 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3222 // CHECK-RV64-NEXT: entry:
3223 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3224 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
3225 //
test_vfcvt_f_xu_v_f16m2_rm_tum(vbool8_t mask,vfloat16m2_t maskedoff,vuint16m2_t src,size_t vl)3226 vfloat16m2_t test_vfcvt_f_xu_v_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t maskedoff, vuint16m2_t src, size_t vl) {
3227 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3228 }
3229
3230 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_xu_v_f16m4_rm_tum
3231 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3232 // CHECK-RV64-NEXT: entry:
3233 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3234 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
3235 //
test_vfcvt_f_xu_v_f16m4_rm_tum(vbool4_t mask,vfloat16m4_t maskedoff,vuint16m4_t src,size_t vl)3236 vfloat16m4_t test_vfcvt_f_xu_v_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t maskedoff, vuint16m4_t src, size_t vl) {
3237 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3238 }
3239
3240 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_xu_v_f16m8_rm_tum
3241 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3242 // CHECK-RV64-NEXT: entry:
3243 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i16> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3244 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
3245 //
test_vfcvt_f_xu_v_f16m8_rm_tum(vbool2_t mask,vfloat16m8_t maskedoff,vuint16m8_t src,size_t vl)3246 vfloat16m8_t test_vfcvt_f_xu_v_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t maskedoff, vuint16m8_t src, size_t vl) {
3247 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3248 }
3249
3250 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_x_f_v_i32mf2_rm_tum
3251 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3252 // CHECK-RV64-NEXT: entry:
3253 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3254 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
3255 //
test_vfcvt_x_f_v_i32mf2_rm_tum(vbool64_t mask,vint32mf2_t maskedoff,vfloat32mf2_t src,size_t vl)3256 vint32mf2_t test_vfcvt_x_f_v_i32mf2_rm_tum(vbool64_t mask, vint32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
3257 return __riscv_vfcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3258 }
3259
3260 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_x_f_v_i32m1_rm_tum
3261 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3262 // CHECK-RV64-NEXT: entry:
3263 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3264 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
3265 //
test_vfcvt_x_f_v_i32m1_rm_tum(vbool32_t mask,vint32m1_t maskedoff,vfloat32m1_t src,size_t vl)3266 vint32m1_t test_vfcvt_x_f_v_i32m1_rm_tum(vbool32_t mask, vint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
3267 return __riscv_vfcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3268 }
3269
3270 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_x_f_v_i32m2_rm_tum
3271 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3272 // CHECK-RV64-NEXT: entry:
3273 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3274 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
3275 //
test_vfcvt_x_f_v_i32m2_rm_tum(vbool16_t mask,vint32m2_t maskedoff,vfloat32m2_t src,size_t vl)3276 vint32m2_t test_vfcvt_x_f_v_i32m2_rm_tum(vbool16_t mask, vint32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
3277 return __riscv_vfcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3278 }
3279
3280 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_x_f_v_i32m4_rm_tum
3281 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3282 // CHECK-RV64-NEXT: entry:
3283 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3284 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
3285 //
test_vfcvt_x_f_v_i32m4_rm_tum(vbool8_t mask,vint32m4_t maskedoff,vfloat32m4_t src,size_t vl)3286 vint32m4_t test_vfcvt_x_f_v_i32m4_rm_tum(vbool8_t mask, vint32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
3287 return __riscv_vfcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3288 }
3289
3290 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_x_f_v_i32m8_rm_tum
3291 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3292 // CHECK-RV64-NEXT: entry:
3293 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3294 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
3295 //
test_vfcvt_x_f_v_i32m8_rm_tum(vbool4_t mask,vint32m8_t maskedoff,vfloat32m8_t src,size_t vl)3296 vint32m8_t test_vfcvt_x_f_v_i32m8_rm_tum(vbool4_t mask, vint32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
3297 return __riscv_vfcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3298 }
3299
3300 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_xu_f_v_u32mf2_rm_tum
3301 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3302 // CHECK-RV64-NEXT: entry:
3303 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3304 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
3305 //
test_vfcvt_xu_f_v_u32mf2_rm_tum(vbool64_t mask,vuint32mf2_t maskedoff,vfloat32mf2_t src,size_t vl)3306 vuint32mf2_t test_vfcvt_xu_f_v_u32mf2_rm_tum(vbool64_t mask, vuint32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
3307 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3308 }
3309
3310 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_xu_f_v_u32m1_rm_tum
3311 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3312 // CHECK-RV64-NEXT: entry:
3313 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3314 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
3315 //
test_vfcvt_xu_f_v_u32m1_rm_tum(vbool32_t mask,vuint32m1_t maskedoff,vfloat32m1_t src,size_t vl)3316 vuint32m1_t test_vfcvt_xu_f_v_u32m1_rm_tum(vbool32_t mask, vuint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
3317 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3318 }
3319
3320 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_xu_f_v_u32m2_rm_tum
3321 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3322 // CHECK-RV64-NEXT: entry:
3323 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3324 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
3325 //
test_vfcvt_xu_f_v_u32m2_rm_tum(vbool16_t mask,vuint32m2_t maskedoff,vfloat32m2_t src,size_t vl)3326 vuint32m2_t test_vfcvt_xu_f_v_u32m2_rm_tum(vbool16_t mask, vuint32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
3327 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3328 }
3329
3330 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_xu_f_v_u32m4_rm_tum
3331 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3332 // CHECK-RV64-NEXT: entry:
3333 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3334 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
3335 //
test_vfcvt_xu_f_v_u32m4_rm_tum(vbool8_t mask,vuint32m4_t maskedoff,vfloat32m4_t src,size_t vl)3336 vuint32m4_t test_vfcvt_xu_f_v_u32m4_rm_tum(vbool8_t mask, vuint32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
3337 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3338 }
3339
3340 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_xu_f_v_u32m8_rm_tum
3341 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3342 // CHECK-RV64-NEXT: entry:
3343 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3344 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
3345 //
test_vfcvt_xu_f_v_u32m8_rm_tum(vbool4_t mask,vuint32m8_t maskedoff,vfloat32m8_t src,size_t vl)3346 vuint32m8_t test_vfcvt_xu_f_v_u32m8_rm_tum(vbool4_t mask, vuint32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
3347 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3348 }
3349
3350 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_x_v_f32mf2_rm_tum
3351 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3352 // CHECK-RV64-NEXT: entry:
3353 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3354 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
3355 //
test_vfcvt_f_x_v_f32mf2_rm_tum(vbool64_t mask,vfloat32mf2_t maskedoff,vint32mf2_t src,size_t vl)3356 vfloat32mf2_t test_vfcvt_f_x_v_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vint32mf2_t src, size_t vl) {
3357 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3358 }
3359
3360 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_x_v_f32m1_rm_tum
3361 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3362 // CHECK-RV64-NEXT: entry:
3363 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f32.nxv2i32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3364 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
3365 //
test_vfcvt_f_x_v_f32m1_rm_tum(vbool32_t mask,vfloat32m1_t maskedoff,vint32m1_t src,size_t vl)3366 vfloat32m1_t test_vfcvt_f_x_v_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vint32m1_t src, size_t vl) {
3367 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3368 }
3369
3370 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_x_v_f32m2_rm_tum
3371 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3372 // CHECK-RV64-NEXT: entry:
3373 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f32.nxv4i32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3374 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
3375 //
test_vfcvt_f_x_v_f32m2_rm_tum(vbool16_t mask,vfloat32m2_t maskedoff,vint32m2_t src,size_t vl)3376 vfloat32m2_t test_vfcvt_f_x_v_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t maskedoff, vint32m2_t src, size_t vl) {
3377 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3378 }
3379
3380 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_x_v_f32m4_rm_tum
3381 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3382 // CHECK-RV64-NEXT: entry:
3383 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f32.nxv8i32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3384 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
3385 //
test_vfcvt_f_x_v_f32m4_rm_tum(vbool8_t mask,vfloat32m4_t maskedoff,vint32m4_t src,size_t vl)3386 vfloat32m4_t test_vfcvt_f_x_v_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t maskedoff, vint32m4_t src, size_t vl) {
3387 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3388 }
3389
3390 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_x_v_f32m8_rm_tum
3391 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3392 // CHECK-RV64-NEXT: entry:
3393 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f32.nxv16i32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3394 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
3395 //
test_vfcvt_f_x_v_f32m8_rm_tum(vbool4_t mask,vfloat32m8_t maskedoff,vint32m8_t src,size_t vl)3396 vfloat32m8_t test_vfcvt_f_x_v_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t maskedoff, vint32m8_t src, size_t vl) {
3397 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3398 }
3399
3400 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_xu_v_f32mf2_rm_tum
3401 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3402 // CHECK-RV64-NEXT: entry:
3403 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3404 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
3405 //
test_vfcvt_f_xu_v_f32mf2_rm_tum(vbool64_t mask,vfloat32mf2_t maskedoff,vuint32mf2_t src,size_t vl)3406 vfloat32mf2_t test_vfcvt_f_xu_v_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t maskedoff, vuint32mf2_t src, size_t vl) {
3407 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3408 }
3409
3410 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_xu_v_f32m1_rm_tum
3411 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3412 // CHECK-RV64-NEXT: entry:
3413 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3414 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
3415 //
test_vfcvt_f_xu_v_f32m1_rm_tum(vbool32_t mask,vfloat32m1_t maskedoff,vuint32m1_t src,size_t vl)3416 vfloat32m1_t test_vfcvt_f_xu_v_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vuint32m1_t src, size_t vl) {
3417 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3418 }
3419
3420 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_xu_v_f32m2_rm_tum
3421 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3422 // CHECK-RV64-NEXT: entry:
3423 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3424 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
3425 //
test_vfcvt_f_xu_v_f32m2_rm_tum(vbool16_t mask,vfloat32m2_t maskedoff,vuint32m2_t src,size_t vl)3426 vfloat32m2_t test_vfcvt_f_xu_v_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t maskedoff, vuint32m2_t src, size_t vl) {
3427 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3428 }
3429
3430 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_xu_v_f32m4_rm_tum
3431 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3432 // CHECK-RV64-NEXT: entry:
3433 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3434 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
3435 //
test_vfcvt_f_xu_v_f32m4_rm_tum(vbool8_t mask,vfloat32m4_t maskedoff,vuint32m4_t src,size_t vl)3436 vfloat32m4_t test_vfcvt_f_xu_v_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t maskedoff, vuint32m4_t src, size_t vl) {
3437 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3438 }
3439
3440 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_xu_v_f32m8_rm_tum
3441 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3442 // CHECK-RV64-NEXT: entry:
3443 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3444 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
3445 //
test_vfcvt_f_xu_v_f32m8_rm_tum(vbool4_t mask,vfloat32m8_t maskedoff,vuint32m8_t src,size_t vl)3446 vfloat32m8_t test_vfcvt_f_xu_v_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t maskedoff, vuint32m8_t src, size_t vl) {
3447 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3448 }
3449
3450 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_x_f_v_i64m1_rm_tum
3451 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3452 // CHECK-RV64-NEXT: entry:
3453 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3454 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
3455 //
test_vfcvt_x_f_v_i64m1_rm_tum(vbool64_t mask,vint64m1_t maskedoff,vfloat64m1_t src,size_t vl)3456 vint64m1_t test_vfcvt_x_f_v_i64m1_rm_tum(vbool64_t mask, vint64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
3457 return __riscv_vfcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3458 }
3459
3460 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_x_f_v_i64m2_rm_tum
3461 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3462 // CHECK-RV64-NEXT: entry:
3463 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3464 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
3465 //
test_vfcvt_x_f_v_i64m2_rm_tum(vbool32_t mask,vint64m2_t maskedoff,vfloat64m2_t src,size_t vl)3466 vint64m2_t test_vfcvt_x_f_v_i64m2_rm_tum(vbool32_t mask, vint64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
3467 return __riscv_vfcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3468 }
3469
3470 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_x_f_v_i64m4_rm_tum
3471 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3472 // CHECK-RV64-NEXT: entry:
3473 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3474 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
3475 //
test_vfcvt_x_f_v_i64m4_rm_tum(vbool16_t mask,vint64m4_t maskedoff,vfloat64m4_t src,size_t vl)3476 vint64m4_t test_vfcvt_x_f_v_i64m4_rm_tum(vbool16_t mask, vint64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
3477 return __riscv_vfcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3478 }
3479
3480 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_x_f_v_i64m8_rm_tum
3481 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3482 // CHECK-RV64-NEXT: entry:
3483 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3484 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
3485 //
test_vfcvt_x_f_v_i64m8_rm_tum(vbool8_t mask,vint64m8_t maskedoff,vfloat64m8_t src,size_t vl)3486 vint64m8_t test_vfcvt_x_f_v_i64m8_rm_tum(vbool8_t mask, vint64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
3487 return __riscv_vfcvt_x_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3488 }
3489
3490 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_xu_f_v_u64m1_rm_tum
3491 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3492 // CHECK-RV64-NEXT: entry:
3493 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3494 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
3495 //
test_vfcvt_xu_f_v_u64m1_rm_tum(vbool64_t mask,vuint64m1_t maskedoff,vfloat64m1_t src,size_t vl)3496 vuint64m1_t test_vfcvt_xu_f_v_u64m1_rm_tum(vbool64_t mask, vuint64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
3497 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3498 }
3499
3500 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_xu_f_v_u64m2_rm_tum
3501 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3502 // CHECK-RV64-NEXT: entry:
3503 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3504 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
3505 //
test_vfcvt_xu_f_v_u64m2_rm_tum(vbool32_t mask,vuint64m2_t maskedoff,vfloat64m2_t src,size_t vl)3506 vuint64m2_t test_vfcvt_xu_f_v_u64m2_rm_tum(vbool32_t mask, vuint64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
3507 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3508 }
3509
3510 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_xu_f_v_u64m4_rm_tum
3511 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3512 // CHECK-RV64-NEXT: entry:
3513 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3514 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
3515 //
test_vfcvt_xu_f_v_u64m4_rm_tum(vbool16_t mask,vuint64m4_t maskedoff,vfloat64m4_t src,size_t vl)3516 vuint64m4_t test_vfcvt_xu_f_v_u64m4_rm_tum(vbool16_t mask, vuint64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
3517 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3518 }
3519
3520 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_xu_f_v_u64m8_rm_tum
3521 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3522 // CHECK-RV64-NEXT: entry:
3523 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3524 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
3525 //
test_vfcvt_xu_f_v_u64m8_rm_tum(vbool8_t mask,vuint64m8_t maskedoff,vfloat64m8_t src,size_t vl)3526 vuint64m8_t test_vfcvt_xu_f_v_u64m8_rm_tum(vbool8_t mask, vuint64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
3527 return __riscv_vfcvt_xu_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3528 }
3529
3530 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_x_v_f64m1_rm_tum
3531 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3532 // CHECK-RV64-NEXT: entry:
3533 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f64.nxv1i64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3534 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
3535 //
test_vfcvt_f_x_v_f64m1_rm_tum(vbool64_t mask,vfloat64m1_t maskedoff,vint64m1_t src,size_t vl)3536 vfloat64m1_t test_vfcvt_f_x_v_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t maskedoff, vint64m1_t src, size_t vl) {
3537 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3538 }
3539
3540 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_x_v_f64m2_rm_tum
3541 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3542 // CHECK-RV64-NEXT: entry:
3543 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f64.nxv2i64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3544 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
3545 //
test_vfcvt_f_x_v_f64m2_rm_tum(vbool32_t mask,vfloat64m2_t maskedoff,vint64m2_t src,size_t vl)3546 vfloat64m2_t test_vfcvt_f_x_v_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t maskedoff, vint64m2_t src, size_t vl) {
3547 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3548 }
3549
3550 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_x_v_f64m4_rm_tum
3551 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3552 // CHECK-RV64-NEXT: entry:
3553 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f64.nxv4i64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3554 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
3555 //
test_vfcvt_f_x_v_f64m4_rm_tum(vbool16_t mask,vfloat64m4_t maskedoff,vint64m4_t src,size_t vl)3556 vfloat64m4_t test_vfcvt_f_x_v_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t maskedoff, vint64m4_t src, size_t vl) {
3557 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3558 }
3559
3560 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_x_v_f64m8_rm_tum
3561 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3562 // CHECK-RV64-NEXT: entry:
3563 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f64.nxv8i64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3564 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
3565 //
test_vfcvt_f_x_v_f64m8_rm_tum(vbool8_t mask,vfloat64m8_t maskedoff,vint64m8_t src,size_t vl)3566 vfloat64m8_t test_vfcvt_f_x_v_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t maskedoff, vint64m8_t src, size_t vl) {
3567 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3568 }
3569
3570 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_xu_v_f64m1_rm_tum
3571 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3572 // CHECK-RV64-NEXT: entry:
3573 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f64.nxv1i64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3574 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
3575 //
test_vfcvt_f_xu_v_f64m1_rm_tum(vbool64_t mask,vfloat64m1_t maskedoff,vuint64m1_t src,size_t vl)3576 vfloat64m1_t test_vfcvt_f_xu_v_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t maskedoff, vuint64m1_t src, size_t vl) {
3577 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3578 }
3579
3580 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_xu_v_f64m2_rm_tum
3581 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3582 // CHECK-RV64-NEXT: entry:
3583 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f64.nxv2i64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3584 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
3585 //
test_vfcvt_f_xu_v_f64m2_rm_tum(vbool32_t mask,vfloat64m2_t maskedoff,vuint64m2_t src,size_t vl)3586 vfloat64m2_t test_vfcvt_f_xu_v_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t maskedoff, vuint64m2_t src, size_t vl) {
3587 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3588 }
3589
3590 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_xu_v_f64m4_rm_tum
3591 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3592 // CHECK-RV64-NEXT: entry:
3593 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f64.nxv4i64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3594 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
3595 //
test_vfcvt_f_xu_v_f64m4_rm_tum(vbool16_t mask,vfloat64m4_t maskedoff,vuint64m4_t src,size_t vl)3596 vfloat64m4_t test_vfcvt_f_xu_v_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t maskedoff, vuint64m4_t src, size_t vl) {
3597 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3598 }
3599
3600 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_xu_v_f64m8_rm_tum
3601 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3602 // CHECK-RV64-NEXT: entry:
3603 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f64.nxv8i64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
3604 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
3605 //
test_vfcvt_f_xu_v_f64m8_rm_tum(vbool8_t mask,vfloat64m8_t maskedoff,vuint64m8_t src,size_t vl)3606 vfloat64m8_t test_vfcvt_f_xu_v_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t maskedoff, vuint64m8_t src, size_t vl) {
3607 return __riscv_vfcvt_f_tum(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3608 }
3609
3610 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_rm_tumu
3611 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3612 // CHECK-RV64-NEXT: entry:
3613 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3614 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
3615 //
test_vfcvt_x_f_v_i16mf4_rm_tumu(vbool64_t mask,vint16mf4_t maskedoff,vfloat16mf4_t src,size_t vl)3616 vint16mf4_t test_vfcvt_x_f_v_i16mf4_rm_tumu(vbool64_t mask, vint16mf4_t maskedoff, vfloat16mf4_t src, size_t vl) {
3617 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3618 }
3619
3620 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_rm_tumu
3621 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3622 // CHECK-RV64-NEXT: entry:
3623 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3624 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
3625 //
test_vfcvt_x_f_v_i16mf2_rm_tumu(vbool32_t mask,vint16mf2_t maskedoff,vfloat16mf2_t src,size_t vl)3626 vint16mf2_t test_vfcvt_x_f_v_i16mf2_rm_tumu(vbool32_t mask, vint16mf2_t maskedoff, vfloat16mf2_t src, size_t vl) {
3627 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3628 }
3629
3630 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_rm_tumu
3631 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3632 // CHECK-RV64-NEXT: entry:
3633 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3634 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
3635 //
test_vfcvt_x_f_v_i16m1_rm_tumu(vbool16_t mask,vint16m1_t maskedoff,vfloat16m1_t src,size_t vl)3636 vint16m1_t test_vfcvt_x_f_v_i16m1_rm_tumu(vbool16_t mask, vint16m1_t maskedoff, vfloat16m1_t src, size_t vl) {
3637 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3638 }
3639
3640 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_rm_tumu
3641 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3642 // CHECK-RV64-NEXT: entry:
3643 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3644 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
3645 //
test_vfcvt_x_f_v_i16m2_rm_tumu(vbool8_t mask,vint16m2_t maskedoff,vfloat16m2_t src,size_t vl)3646 vint16m2_t test_vfcvt_x_f_v_i16m2_rm_tumu(vbool8_t mask, vint16m2_t maskedoff, vfloat16m2_t src, size_t vl) {
3647 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3648 }
3649
3650 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_rm_tumu
3651 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3652 // CHECK-RV64-NEXT: entry:
3653 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3654 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
3655 //
test_vfcvt_x_f_v_i16m4_rm_tumu(vbool4_t mask,vint16m4_t maskedoff,vfloat16m4_t src,size_t vl)3656 vint16m4_t test_vfcvt_x_f_v_i16m4_rm_tumu(vbool4_t mask, vint16m4_t maskedoff, vfloat16m4_t src, size_t vl) {
3657 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3658 }
3659
3660 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_rm_tumu
3661 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3662 // CHECK-RV64-NEXT: entry:
3663 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3664 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
3665 //
test_vfcvt_x_f_v_i16m8_rm_tumu(vbool2_t mask,vint16m8_t maskedoff,vfloat16m8_t src,size_t vl)3666 vint16m8_t test_vfcvt_x_f_v_i16m8_rm_tumu(vbool2_t mask, vint16m8_t maskedoff, vfloat16m8_t src, size_t vl) {
3667 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3668 }
3669
3670 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_rm_tumu
3671 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3672 // CHECK-RV64-NEXT: entry:
3673 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3674 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
3675 //
test_vfcvt_xu_f_v_u16mf4_rm_tumu(vbool64_t mask,vuint16mf4_t maskedoff,vfloat16mf4_t src,size_t vl)3676 vuint16mf4_t test_vfcvt_xu_f_v_u16mf4_rm_tumu(vbool64_t mask, vuint16mf4_t maskedoff, vfloat16mf4_t src, size_t vl) {
3677 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3678 }
3679
3680 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_rm_tumu
3681 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3682 // CHECK-RV64-NEXT: entry:
3683 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3684 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
3685 //
test_vfcvt_xu_f_v_u16mf2_rm_tumu(vbool32_t mask,vuint16mf2_t maskedoff,vfloat16mf2_t src,size_t vl)3686 vuint16mf2_t test_vfcvt_xu_f_v_u16mf2_rm_tumu(vbool32_t mask, vuint16mf2_t maskedoff, vfloat16mf2_t src, size_t vl) {
3687 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3688 }
3689
3690 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_rm_tumu
3691 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3692 // CHECK-RV64-NEXT: entry:
3693 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3694 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
3695 //
test_vfcvt_xu_f_v_u16m1_rm_tumu(vbool16_t mask,vuint16m1_t maskedoff,vfloat16m1_t src,size_t vl)3696 vuint16m1_t test_vfcvt_xu_f_v_u16m1_rm_tumu(vbool16_t mask, vuint16m1_t maskedoff, vfloat16m1_t src, size_t vl) {
3697 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3698 }
3699
3700 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_rm_tumu
3701 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3702 // CHECK-RV64-NEXT: entry:
3703 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3704 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
3705 //
test_vfcvt_xu_f_v_u16m2_rm_tumu(vbool8_t mask,vuint16m2_t maskedoff,vfloat16m2_t src,size_t vl)3706 vuint16m2_t test_vfcvt_xu_f_v_u16m2_rm_tumu(vbool8_t mask, vuint16m2_t maskedoff, vfloat16m2_t src, size_t vl) {
3707 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3708 }
3709
3710 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4_rm_tumu
3711 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3712 // CHECK-RV64-NEXT: entry:
3713 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3714 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
3715 //
test_vfcvt_xu_f_v_u16m4_rm_tumu(vbool4_t mask,vuint16m4_t maskedoff,vfloat16m4_t src,size_t vl)3716 vuint16m4_t test_vfcvt_xu_f_v_u16m4_rm_tumu(vbool4_t mask, vuint16m4_t maskedoff, vfloat16m4_t src, size_t vl) {
3717 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3718 }
3719
3720 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8_rm_tumu
3721 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3722 // CHECK-RV64-NEXT: entry:
3723 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3724 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
3725 //
test_vfcvt_xu_f_v_u16m8_rm_tumu(vbool2_t mask,vuint16m8_t maskedoff,vfloat16m8_t src,size_t vl)3726 vuint16m8_t test_vfcvt_xu_f_v_u16m8_rm_tumu(vbool2_t mask, vuint16m8_t maskedoff, vfloat16m8_t src, size_t vl) {
3727 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3728 }
3729
3730 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_x_v_f16mf4_rm_tumu
3731 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3732 // CHECK-RV64-NEXT: entry:
3733 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3734 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
3735 //
test_vfcvt_f_x_v_f16mf4_rm_tumu(vbool64_t mask,vfloat16mf4_t maskedoff,vint16mf4_t src,size_t vl)3736 vfloat16mf4_t test_vfcvt_f_x_v_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t maskedoff, vint16mf4_t src, size_t vl) {
3737 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3738 }
3739
3740 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_x_v_f16mf2_rm_tumu
3741 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3742 // CHECK-RV64-NEXT: entry:
3743 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3744 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
3745 //
test_vfcvt_f_x_v_f16mf2_rm_tumu(vbool32_t mask,vfloat16mf2_t maskedoff,vint16mf2_t src,size_t vl)3746 vfloat16mf2_t test_vfcvt_f_x_v_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t maskedoff, vint16mf2_t src, size_t vl) {
3747 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3748 }
3749
3750 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_x_v_f16m1_rm_tumu
3751 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3752 // CHECK-RV64-NEXT: entry:
3753 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3754 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
3755 //
test_vfcvt_f_x_v_f16m1_rm_tumu(vbool16_t mask,vfloat16m1_t maskedoff,vint16m1_t src,size_t vl)3756 vfloat16m1_t test_vfcvt_f_x_v_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t maskedoff, vint16m1_t src, size_t vl) {
3757 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3758 }
3759
3760 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_x_v_f16m2_rm_tumu
3761 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3762 // CHECK-RV64-NEXT: entry:
3763 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3764 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
3765 //
test_vfcvt_f_x_v_f16m2_rm_tumu(vbool8_t mask,vfloat16m2_t maskedoff,vint16m2_t src,size_t vl)3766 vfloat16m2_t test_vfcvt_f_x_v_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t maskedoff, vint16m2_t src, size_t vl) {
3767 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3768 }
3769
3770 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_x_v_f16m4_rm_tumu
3771 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3772 // CHECK-RV64-NEXT: entry:
3773 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3774 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
3775 //
test_vfcvt_f_x_v_f16m4_rm_tumu(vbool4_t mask,vfloat16m4_t maskedoff,vint16m4_t src,size_t vl)3776 vfloat16m4_t test_vfcvt_f_x_v_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t maskedoff, vint16m4_t src, size_t vl) {
3777 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3778 }
3779
3780 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_x_v_f16m8_rm_tumu
3781 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3782 // CHECK-RV64-NEXT: entry:
3783 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i16> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3784 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
3785 //
test_vfcvt_f_x_v_f16m8_rm_tumu(vbool2_t mask,vfloat16m8_t maskedoff,vint16m8_t src,size_t vl)3786 vfloat16m8_t test_vfcvt_f_x_v_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t maskedoff, vint16m8_t src, size_t vl) {
3787 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3788 }
3789
3790 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_xu_v_f16mf4_rm_tumu
3791 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3792 // CHECK-RV64-NEXT: entry:
3793 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3794 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
3795 //
test_vfcvt_f_xu_v_f16mf4_rm_tumu(vbool64_t mask,vfloat16mf4_t maskedoff,vuint16mf4_t src,size_t vl)3796 vfloat16mf4_t test_vfcvt_f_xu_v_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t maskedoff, vuint16mf4_t src, size_t vl) {
3797 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3798 }
3799
3800 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_xu_v_f16mf2_rm_tumu
3801 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3802 // CHECK-RV64-NEXT: entry:
3803 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3804 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
3805 //
test_vfcvt_f_xu_v_f16mf2_rm_tumu(vbool32_t mask,vfloat16mf2_t maskedoff,vuint16mf2_t src,size_t vl)3806 vfloat16mf2_t test_vfcvt_f_xu_v_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t maskedoff, vuint16mf2_t src, size_t vl) {
3807 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3808 }
3809
3810 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_xu_v_f16m1_rm_tumu
3811 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3812 // CHECK-RV64-NEXT: entry:
3813 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3814 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
3815 //
test_vfcvt_f_xu_v_f16m1_rm_tumu(vbool16_t mask,vfloat16m1_t maskedoff,vuint16m1_t src,size_t vl)3816 vfloat16m1_t test_vfcvt_f_xu_v_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t maskedoff, vuint16m1_t src, size_t vl) {
3817 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3818 }
3819
3820 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_xu_v_f16m2_rm_tumu
3821 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3822 // CHECK-RV64-NEXT: entry:
3823 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3824 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
3825 //
test_vfcvt_f_xu_v_f16m2_rm_tumu(vbool8_t mask,vfloat16m2_t maskedoff,vuint16m2_t src,size_t vl)3826 vfloat16m2_t test_vfcvt_f_xu_v_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t maskedoff, vuint16m2_t src, size_t vl) {
3827 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3828 }
3829
3830 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_xu_v_f16m4_rm_tumu
3831 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3832 // CHECK-RV64-NEXT: entry:
3833 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3834 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
3835 //
test_vfcvt_f_xu_v_f16m4_rm_tumu(vbool4_t mask,vfloat16m4_t maskedoff,vuint16m4_t src,size_t vl)3836 vfloat16m4_t test_vfcvt_f_xu_v_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t maskedoff, vuint16m4_t src, size_t vl) {
3837 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3838 }
3839
3840 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_xu_v_f16m8_rm_tumu
3841 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3842 // CHECK-RV64-NEXT: entry:
3843 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i16> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3844 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
3845 //
test_vfcvt_f_xu_v_f16m8_rm_tumu(vbool2_t mask,vfloat16m8_t maskedoff,vuint16m8_t src,size_t vl)3846 vfloat16m8_t test_vfcvt_f_xu_v_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t maskedoff, vuint16m8_t src, size_t vl) {
3847 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3848 }
3849
3850 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_x_f_v_i32mf2_rm_tumu
3851 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3852 // CHECK-RV64-NEXT: entry:
3853 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3854 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
3855 //
test_vfcvt_x_f_v_i32mf2_rm_tumu(vbool64_t mask,vint32mf2_t maskedoff,vfloat32mf2_t src,size_t vl)3856 vint32mf2_t test_vfcvt_x_f_v_i32mf2_rm_tumu(vbool64_t mask, vint32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
3857 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3858 }
3859
3860 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_x_f_v_i32m1_rm_tumu
3861 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3862 // CHECK-RV64-NEXT: entry:
3863 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3864 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
3865 //
test_vfcvt_x_f_v_i32m1_rm_tumu(vbool32_t mask,vint32m1_t maskedoff,vfloat32m1_t src,size_t vl)3866 vint32m1_t test_vfcvt_x_f_v_i32m1_rm_tumu(vbool32_t mask, vint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
3867 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3868 }
3869
3870 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_x_f_v_i32m2_rm_tumu
3871 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3872 // CHECK-RV64-NEXT: entry:
3873 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3874 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
3875 //
test_vfcvt_x_f_v_i32m2_rm_tumu(vbool16_t mask,vint32m2_t maskedoff,vfloat32m2_t src,size_t vl)3876 vint32m2_t test_vfcvt_x_f_v_i32m2_rm_tumu(vbool16_t mask, vint32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
3877 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3878 }
3879
3880 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_x_f_v_i32m4_rm_tumu
3881 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3882 // CHECK-RV64-NEXT: entry:
3883 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3884 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
3885 //
test_vfcvt_x_f_v_i32m4_rm_tumu(vbool8_t mask,vint32m4_t maskedoff,vfloat32m4_t src,size_t vl)3886 vint32m4_t test_vfcvt_x_f_v_i32m4_rm_tumu(vbool8_t mask, vint32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
3887 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3888 }
3889
3890 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_x_f_v_i32m8_rm_tumu
3891 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3892 // CHECK-RV64-NEXT: entry:
3893 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3894 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
3895 //
test_vfcvt_x_f_v_i32m8_rm_tumu(vbool4_t mask,vint32m8_t maskedoff,vfloat32m8_t src,size_t vl)3896 vint32m8_t test_vfcvt_x_f_v_i32m8_rm_tumu(vbool4_t mask, vint32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
3897 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3898 }
3899
3900 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_xu_f_v_u32mf2_rm_tumu
3901 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3902 // CHECK-RV64-NEXT: entry:
3903 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3904 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
3905 //
test_vfcvt_xu_f_v_u32mf2_rm_tumu(vbool64_t mask,vuint32mf2_t maskedoff,vfloat32mf2_t src,size_t vl)3906 vuint32mf2_t test_vfcvt_xu_f_v_u32mf2_rm_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
3907 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3908 }
3909
3910 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_xu_f_v_u32m1_rm_tumu
3911 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3912 // CHECK-RV64-NEXT: entry:
3913 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3914 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
3915 //
test_vfcvt_xu_f_v_u32m1_rm_tumu(vbool32_t mask,vuint32m1_t maskedoff,vfloat32m1_t src,size_t vl)3916 vuint32m1_t test_vfcvt_xu_f_v_u32m1_rm_tumu(vbool32_t mask, vuint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
3917 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3918 }
3919
3920 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_xu_f_v_u32m2_rm_tumu
3921 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3922 // CHECK-RV64-NEXT: entry:
3923 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3924 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
3925 //
test_vfcvt_xu_f_v_u32m2_rm_tumu(vbool16_t mask,vuint32m2_t maskedoff,vfloat32m2_t src,size_t vl)3926 vuint32m2_t test_vfcvt_xu_f_v_u32m2_rm_tumu(vbool16_t mask, vuint32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
3927 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3928 }
3929
3930 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_xu_f_v_u32m4_rm_tumu
3931 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3932 // CHECK-RV64-NEXT: entry:
3933 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3934 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
3935 //
test_vfcvt_xu_f_v_u32m4_rm_tumu(vbool8_t mask,vuint32m4_t maskedoff,vfloat32m4_t src,size_t vl)3936 vuint32m4_t test_vfcvt_xu_f_v_u32m4_rm_tumu(vbool8_t mask, vuint32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
3937 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3938 }
3939
3940 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_xu_f_v_u32m8_rm_tumu
3941 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3942 // CHECK-RV64-NEXT: entry:
3943 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3944 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
3945 //
test_vfcvt_xu_f_v_u32m8_rm_tumu(vbool4_t mask,vuint32m8_t maskedoff,vfloat32m8_t src,size_t vl)3946 vuint32m8_t test_vfcvt_xu_f_v_u32m8_rm_tumu(vbool4_t mask, vuint32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
3947 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3948 }
3949
3950 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_x_v_f32mf2_rm_tumu
3951 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3952 // CHECK-RV64-NEXT: entry:
3953 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3954 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
3955 //
test_vfcvt_f_x_v_f32mf2_rm_tumu(vbool64_t mask,vfloat32mf2_t maskedoff,vint32mf2_t src,size_t vl)3956 vfloat32mf2_t test_vfcvt_f_x_v_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vint32mf2_t src, size_t vl) {
3957 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3958 }
3959
3960 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_x_v_f32m1_rm_tumu
3961 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3962 // CHECK-RV64-NEXT: entry:
3963 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f32.nxv2i32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3964 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
3965 //
test_vfcvt_f_x_v_f32m1_rm_tumu(vbool32_t mask,vfloat32m1_t maskedoff,vint32m1_t src,size_t vl)3966 vfloat32m1_t test_vfcvt_f_x_v_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vint32m1_t src, size_t vl) {
3967 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3968 }
3969
3970 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_x_v_f32m2_rm_tumu
3971 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3972 // CHECK-RV64-NEXT: entry:
3973 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f32.nxv4i32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3974 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
3975 //
test_vfcvt_f_x_v_f32m2_rm_tumu(vbool16_t mask,vfloat32m2_t maskedoff,vint32m2_t src,size_t vl)3976 vfloat32m2_t test_vfcvt_f_x_v_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vint32m2_t src, size_t vl) {
3977 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3978 }
3979
3980 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_x_v_f32m4_rm_tumu
3981 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3982 // CHECK-RV64-NEXT: entry:
3983 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f32.nxv8i32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3984 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
3985 //
test_vfcvt_f_x_v_f32m4_rm_tumu(vbool8_t mask,vfloat32m4_t maskedoff,vint32m4_t src,size_t vl)3986 vfloat32m4_t test_vfcvt_f_x_v_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vint32m4_t src, size_t vl) {
3987 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3988 }
3989
3990 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_x_v_f32m8_rm_tumu
3991 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3992 // CHECK-RV64-NEXT: entry:
3993 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f32.nxv16i32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
3994 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
3995 //
test_vfcvt_f_x_v_f32m8_rm_tumu(vbool4_t mask,vfloat32m8_t maskedoff,vint32m8_t src,size_t vl)3996 vfloat32m8_t test_vfcvt_f_x_v_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t maskedoff, vint32m8_t src, size_t vl) {
3997 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
3998 }
3999
4000 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_xu_v_f32mf2_rm_tumu
4001 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4002 // CHECK-RV64-NEXT: entry:
4003 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4004 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
4005 //
test_vfcvt_f_xu_v_f32mf2_rm_tumu(vbool64_t mask,vfloat32mf2_t maskedoff,vuint32mf2_t src,size_t vl)4006 vfloat32mf2_t test_vfcvt_f_xu_v_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t maskedoff, vuint32mf2_t src, size_t vl) {
4007 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4008 }
4009
4010 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_xu_v_f32m1_rm_tumu
4011 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4012 // CHECK-RV64-NEXT: entry:
4013 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4014 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
4015 //
test_vfcvt_f_xu_v_f32m1_rm_tumu(vbool32_t mask,vfloat32m1_t maskedoff,vuint32m1_t src,size_t vl)4016 vfloat32m1_t test_vfcvt_f_xu_v_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vuint32m1_t src, size_t vl) {
4017 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4018 }
4019
4020 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_xu_v_f32m2_rm_tumu
4021 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4022 // CHECK-RV64-NEXT: entry:
4023 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4024 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
4025 //
test_vfcvt_f_xu_v_f32m2_rm_tumu(vbool16_t mask,vfloat32m2_t maskedoff,vuint32m2_t src,size_t vl)4026 vfloat32m2_t test_vfcvt_f_xu_v_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t maskedoff, vuint32m2_t src, size_t vl) {
4027 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4028 }
4029
4030 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_xu_v_f32m4_rm_tumu
4031 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4032 // CHECK-RV64-NEXT: entry:
4033 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4034 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
4035 //
test_vfcvt_f_xu_v_f32m4_rm_tumu(vbool8_t mask,vfloat32m4_t maskedoff,vuint32m4_t src,size_t vl)4036 vfloat32m4_t test_vfcvt_f_xu_v_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t maskedoff, vuint32m4_t src, size_t vl) {
4037 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4038 }
4039
4040 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_xu_v_f32m8_rm_tumu
4041 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4042 // CHECK-RV64-NEXT: entry:
4043 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4044 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
4045 //
test_vfcvt_f_xu_v_f32m8_rm_tumu(vbool4_t mask,vfloat32m8_t maskedoff,vuint32m8_t src,size_t vl)4046 vfloat32m8_t test_vfcvt_f_xu_v_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t maskedoff, vuint32m8_t src, size_t vl) {
4047 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4048 }
4049
4050 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_x_f_v_i64m1_rm_tumu
4051 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4052 // CHECK-RV64-NEXT: entry:
4053 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4054 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
4055 //
test_vfcvt_x_f_v_i64m1_rm_tumu(vbool64_t mask,vint64m1_t maskedoff,vfloat64m1_t src,size_t vl)4056 vint64m1_t test_vfcvt_x_f_v_i64m1_rm_tumu(vbool64_t mask, vint64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
4057 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4058 }
4059
4060 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_x_f_v_i64m2_rm_tumu
4061 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4062 // CHECK-RV64-NEXT: entry:
4063 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4064 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
4065 //
test_vfcvt_x_f_v_i64m2_rm_tumu(vbool32_t mask,vint64m2_t maskedoff,vfloat64m2_t src,size_t vl)4066 vint64m2_t test_vfcvt_x_f_v_i64m2_rm_tumu(vbool32_t mask, vint64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
4067 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4068 }
4069
4070 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_x_f_v_i64m4_rm_tumu
4071 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4072 // CHECK-RV64-NEXT: entry:
4073 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4074 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
4075 //
test_vfcvt_x_f_v_i64m4_rm_tumu(vbool16_t mask,vint64m4_t maskedoff,vfloat64m4_t src,size_t vl)4076 vint64m4_t test_vfcvt_x_f_v_i64m4_rm_tumu(vbool16_t mask, vint64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
4077 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4078 }
4079
4080 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_x_f_v_i64m8_rm_tumu
4081 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4082 // CHECK-RV64-NEXT: entry:
4083 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4084 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
4085 //
test_vfcvt_x_f_v_i64m8_rm_tumu(vbool8_t mask,vint64m8_t maskedoff,vfloat64m8_t src,size_t vl)4086 vint64m8_t test_vfcvt_x_f_v_i64m8_rm_tumu(vbool8_t mask, vint64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
4087 return __riscv_vfcvt_x_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4088 }
4089
4090 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_xu_f_v_u64m1_rm_tumu
4091 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4092 // CHECK-RV64-NEXT: entry:
4093 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4094 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
4095 //
test_vfcvt_xu_f_v_u64m1_rm_tumu(vbool64_t mask,vuint64m1_t maskedoff,vfloat64m1_t src,size_t vl)4096 vuint64m1_t test_vfcvt_xu_f_v_u64m1_rm_tumu(vbool64_t mask, vuint64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
4097 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4098 }
4099
4100 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_xu_f_v_u64m2_rm_tumu
4101 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4102 // CHECK-RV64-NEXT: entry:
4103 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4104 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
4105 //
test_vfcvt_xu_f_v_u64m2_rm_tumu(vbool32_t mask,vuint64m2_t maskedoff,vfloat64m2_t src,size_t vl)4106 vuint64m2_t test_vfcvt_xu_f_v_u64m2_rm_tumu(vbool32_t mask, vuint64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
4107 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4108 }
4109
4110 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_xu_f_v_u64m4_rm_tumu
4111 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4112 // CHECK-RV64-NEXT: entry:
4113 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4114 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
4115 //
test_vfcvt_xu_f_v_u64m4_rm_tumu(vbool16_t mask,vuint64m4_t maskedoff,vfloat64m4_t src,size_t vl)4116 vuint64m4_t test_vfcvt_xu_f_v_u64m4_rm_tumu(vbool16_t mask, vuint64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
4117 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4118 }
4119
4120 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_xu_f_v_u64m8_rm_tumu
4121 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4122 // CHECK-RV64-NEXT: entry:
4123 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4124 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
4125 //
test_vfcvt_xu_f_v_u64m8_rm_tumu(vbool8_t mask,vuint64m8_t maskedoff,vfloat64m8_t src,size_t vl)4126 vuint64m8_t test_vfcvt_xu_f_v_u64m8_rm_tumu(vbool8_t mask, vuint64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
4127 return __riscv_vfcvt_xu_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4128 }
4129
4130 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_x_v_f64m1_rm_tumu
4131 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4132 // CHECK-RV64-NEXT: entry:
4133 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f64.nxv1i64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4134 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
4135 //
test_vfcvt_f_x_v_f64m1_rm_tumu(vbool64_t mask,vfloat64m1_t maskedoff,vint64m1_t src,size_t vl)4136 vfloat64m1_t test_vfcvt_f_x_v_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t maskedoff, vint64m1_t src, size_t vl) {
4137 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4138 }
4139
4140 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_x_v_f64m2_rm_tumu
4141 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4142 // CHECK-RV64-NEXT: entry:
4143 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f64.nxv2i64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4144 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
4145 //
test_vfcvt_f_x_v_f64m2_rm_tumu(vbool32_t mask,vfloat64m2_t maskedoff,vint64m2_t src,size_t vl)4146 vfloat64m2_t test_vfcvt_f_x_v_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t maskedoff, vint64m2_t src, size_t vl) {
4147 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4148 }
4149
4150 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_x_v_f64m4_rm_tumu
4151 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4152 // CHECK-RV64-NEXT: entry:
4153 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f64.nxv4i64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4154 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
4155 //
test_vfcvt_f_x_v_f64m4_rm_tumu(vbool16_t mask,vfloat64m4_t maskedoff,vint64m4_t src,size_t vl)4156 vfloat64m4_t test_vfcvt_f_x_v_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t maskedoff, vint64m4_t src, size_t vl) {
4157 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4158 }
4159
4160 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_x_v_f64m8_rm_tumu
4161 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4162 // CHECK-RV64-NEXT: entry:
4163 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f64.nxv8i64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4164 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
4165 //
test_vfcvt_f_x_v_f64m8_rm_tumu(vbool8_t mask,vfloat64m8_t maskedoff,vint64m8_t src,size_t vl)4166 vfloat64m8_t test_vfcvt_f_x_v_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t maskedoff, vint64m8_t src, size_t vl) {
4167 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4168 }
4169
4170 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_xu_v_f64m1_rm_tumu
4171 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4172 // CHECK-RV64-NEXT: entry:
4173 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f64.nxv1i64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4174 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
4175 //
test_vfcvt_f_xu_v_f64m1_rm_tumu(vbool64_t mask,vfloat64m1_t maskedoff,vuint64m1_t src,size_t vl)4176 vfloat64m1_t test_vfcvt_f_xu_v_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t maskedoff, vuint64m1_t src, size_t vl) {
4177 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4178 }
4179
4180 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_xu_v_f64m2_rm_tumu
4181 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4182 // CHECK-RV64-NEXT: entry:
4183 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f64.nxv2i64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4184 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
4185 //
test_vfcvt_f_xu_v_f64m2_rm_tumu(vbool32_t mask,vfloat64m2_t maskedoff,vuint64m2_t src,size_t vl)4186 vfloat64m2_t test_vfcvt_f_xu_v_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t maskedoff, vuint64m2_t src, size_t vl) {
4187 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4188 }
4189
4190 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_xu_v_f64m4_rm_tumu
4191 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4192 // CHECK-RV64-NEXT: entry:
4193 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f64.nxv4i64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4194 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
4195 //
test_vfcvt_f_xu_v_f64m4_rm_tumu(vbool16_t mask,vfloat64m4_t maskedoff,vuint64m4_t src,size_t vl)4196 vfloat64m4_t test_vfcvt_f_xu_v_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t maskedoff, vuint64m4_t src, size_t vl) {
4197 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4198 }
4199
4200 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_xu_v_f64m8_rm_tumu
4201 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4202 // CHECK-RV64-NEXT: entry:
4203 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f64.nxv8i64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
4204 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
4205 //
test_vfcvt_f_xu_v_f64m8_rm_tumu(vbool8_t mask,vfloat64m8_t maskedoff,vuint64m8_t src,size_t vl)4206 vfloat64m8_t test_vfcvt_f_xu_v_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t maskedoff, vuint64m8_t src, size_t vl) {
4207 return __riscv_vfcvt_f_tumu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4208 }
4209
4210 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_rm_mu
4211 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4212 // CHECK-RV64-NEXT: entry:
4213 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4214 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
4215 //
test_vfcvt_x_f_v_i16mf4_rm_mu(vbool64_t mask,vint16mf4_t maskedoff,vfloat16mf4_t src,size_t vl)4216 vint16mf4_t test_vfcvt_x_f_v_i16mf4_rm_mu(vbool64_t mask, vint16mf4_t maskedoff, vfloat16mf4_t src, size_t vl) {
4217 return __riscv_vfcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4218 }
4219
4220 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_rm_mu
4221 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4222 // CHECK-RV64-NEXT: entry:
4223 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4224 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
4225 //
test_vfcvt_x_f_v_i16mf2_rm_mu(vbool32_t mask,vint16mf2_t maskedoff,vfloat16mf2_t src,size_t vl)4226 vint16mf2_t test_vfcvt_x_f_v_i16mf2_rm_mu(vbool32_t mask, vint16mf2_t maskedoff, vfloat16mf2_t src, size_t vl) {
4227 return __riscv_vfcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4228 }
4229
4230 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_rm_mu
4231 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4232 // CHECK-RV64-NEXT: entry:
4233 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4234 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
4235 //
test_vfcvt_x_f_v_i16m1_rm_mu(vbool16_t mask,vint16m1_t maskedoff,vfloat16m1_t src,size_t vl)4236 vint16m1_t test_vfcvt_x_f_v_i16m1_rm_mu(vbool16_t mask, vint16m1_t maskedoff, vfloat16m1_t src, size_t vl) {
4237 return __riscv_vfcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4238 }
4239
4240 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_rm_mu
4241 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4242 // CHECK-RV64-NEXT: entry:
4243 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4244 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
4245 //
test_vfcvt_x_f_v_i16m2_rm_mu(vbool8_t mask,vint16m2_t maskedoff,vfloat16m2_t src,size_t vl)4246 vint16m2_t test_vfcvt_x_f_v_i16m2_rm_mu(vbool8_t mask, vint16m2_t maskedoff, vfloat16m2_t src, size_t vl) {
4247 return __riscv_vfcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4248 }
4249
4250 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_rm_mu
4251 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4252 // CHECK-RV64-NEXT: entry:
4253 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4254 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
4255 //
test_vfcvt_x_f_v_i16m4_rm_mu(vbool4_t mask,vint16m4_t maskedoff,vfloat16m4_t src,size_t vl)4256 vint16m4_t test_vfcvt_x_f_v_i16m4_rm_mu(vbool4_t mask, vint16m4_t maskedoff, vfloat16m4_t src, size_t vl) {
4257 return __riscv_vfcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4258 }
4259
4260 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_rm_mu
4261 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4262 // CHECK-RV64-NEXT: entry:
4263 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4264 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
4265 //
test_vfcvt_x_f_v_i16m8_rm_mu(vbool2_t mask,vint16m8_t maskedoff,vfloat16m8_t src,size_t vl)4266 vint16m8_t test_vfcvt_x_f_v_i16m8_rm_mu(vbool2_t mask, vint16m8_t maskedoff, vfloat16m8_t src, size_t vl) {
4267 return __riscv_vfcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4268 }
4269
4270 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_rm_mu
4271 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4272 // CHECK-RV64-NEXT: entry:
4273 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF]], <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4274 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
4275 //
test_vfcvt_xu_f_v_u16mf4_rm_mu(vbool64_t mask,vuint16mf4_t maskedoff,vfloat16mf4_t src,size_t vl)4276 vuint16mf4_t test_vfcvt_xu_f_v_u16mf4_rm_mu(vbool64_t mask, vuint16mf4_t maskedoff, vfloat16mf4_t src, size_t vl) {
4277 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4278 }
4279
4280 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_rm_mu
4281 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4282 // CHECK-RV64-NEXT: entry:
4283 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF]], <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4284 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
4285 //
test_vfcvt_xu_f_v_u16mf2_rm_mu(vbool32_t mask,vuint16mf2_t maskedoff,vfloat16mf2_t src,size_t vl)4286 vuint16mf2_t test_vfcvt_xu_f_v_u16mf2_rm_mu(vbool32_t mask, vuint16mf2_t maskedoff, vfloat16mf2_t src, size_t vl) {
4287 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4288 }
4289
4290 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_rm_mu
4291 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4292 // CHECK-RV64-NEXT: entry:
4293 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF]], <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4294 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
4295 //
test_vfcvt_xu_f_v_u16m1_rm_mu(vbool16_t mask,vuint16m1_t maskedoff,vfloat16m1_t src,size_t vl)4296 vuint16m1_t test_vfcvt_xu_f_v_u16m1_rm_mu(vbool16_t mask, vuint16m1_t maskedoff, vfloat16m1_t src, size_t vl) {
4297 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4298 }
4299
4300 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_rm_mu
4301 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4302 // CHECK-RV64-NEXT: entry:
4303 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF]], <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4304 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
4305 //
test_vfcvt_xu_f_v_u16m2_rm_mu(vbool8_t mask,vuint16m2_t maskedoff,vfloat16m2_t src,size_t vl)4306 vuint16m2_t test_vfcvt_xu_f_v_u16m2_rm_mu(vbool8_t mask, vuint16m2_t maskedoff, vfloat16m2_t src, size_t vl) {
4307 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4308 }
4309
4310 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4_rm_mu
4311 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4312 // CHECK-RV64-NEXT: entry:
4313 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF]], <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4314 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
4315 //
test_vfcvt_xu_f_v_u16m4_rm_mu(vbool4_t mask,vuint16m4_t maskedoff,vfloat16m4_t src,size_t vl)4316 vuint16m4_t test_vfcvt_xu_f_v_u16m4_rm_mu(vbool4_t mask, vuint16m4_t maskedoff, vfloat16m4_t src, size_t vl) {
4317 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4318 }
4319
4320 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8_rm_mu
4321 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4322 // CHECK-RV64-NEXT: entry:
4323 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF]], <vscale x 32 x half> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4324 // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
4325 //
test_vfcvt_xu_f_v_u16m8_rm_mu(vbool2_t mask,vuint16m8_t maskedoff,vfloat16m8_t src,size_t vl)4326 vuint16m8_t test_vfcvt_xu_f_v_u16m8_rm_mu(vbool2_t mask, vuint16m8_t maskedoff, vfloat16m8_t src, size_t vl) {
4327 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4328 }
4329
4330 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_x_v_f16mf4_rm_mu
4331 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4332 // CHECK-RV64-NEXT: entry:
4333 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4334 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
4335 //
test_vfcvt_f_x_v_f16mf4_rm_mu(vbool64_t mask,vfloat16mf4_t maskedoff,vint16mf4_t src,size_t vl)4336 vfloat16mf4_t test_vfcvt_f_x_v_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t maskedoff, vint16mf4_t src, size_t vl) {
4337 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4338 }
4339
4340 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_x_v_f16mf2_rm_mu
4341 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4342 // CHECK-RV64-NEXT: entry:
4343 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4344 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
4345 //
test_vfcvt_f_x_v_f16mf2_rm_mu(vbool32_t mask,vfloat16mf2_t maskedoff,vint16mf2_t src,size_t vl)4346 vfloat16mf2_t test_vfcvt_f_x_v_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t maskedoff, vint16mf2_t src, size_t vl) {
4347 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4348 }
4349
4350 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_x_v_f16m1_rm_mu
4351 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4352 // CHECK-RV64-NEXT: entry:
4353 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4354 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
4355 //
test_vfcvt_f_x_v_f16m1_rm_mu(vbool16_t mask,vfloat16m1_t maskedoff,vint16m1_t src,size_t vl)4356 vfloat16m1_t test_vfcvt_f_x_v_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t maskedoff, vint16m1_t src, size_t vl) {
4357 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4358 }
4359
4360 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_x_v_f16m2_rm_mu
4361 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4362 // CHECK-RV64-NEXT: entry:
4363 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4364 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
4365 //
test_vfcvt_f_x_v_f16m2_rm_mu(vbool8_t mask,vfloat16m2_t maskedoff,vint16m2_t src,size_t vl)4366 vfloat16m2_t test_vfcvt_f_x_v_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t maskedoff, vint16m2_t src, size_t vl) {
4367 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4368 }
4369
4370 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_x_v_f16m4_rm_mu
4371 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4372 // CHECK-RV64-NEXT: entry:
4373 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4374 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
4375 //
test_vfcvt_f_x_v_f16m4_rm_mu(vbool4_t mask,vfloat16m4_t maskedoff,vint16m4_t src,size_t vl)4376 vfloat16m4_t test_vfcvt_f_x_v_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t maskedoff, vint16m4_t src, size_t vl) {
4377 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4378 }
4379
4380 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_x_v_f16m8_rm_mu
4381 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4382 // CHECK-RV64-NEXT: entry:
4383 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i16> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4384 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
4385 //
test_vfcvt_f_x_v_f16m8_rm_mu(vbool2_t mask,vfloat16m8_t maskedoff,vint16m8_t src,size_t vl)4386 vfloat16m8_t test_vfcvt_f_x_v_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t maskedoff, vint16m8_t src, size_t vl) {
4387 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4388 }
4389
4390 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfcvt_f_xu_v_f16mf4_rm_mu
4391 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4392 // CHECK-RV64-NEXT: entry:
4393 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF]], <vscale x 1 x i16> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4394 // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
4395 //
test_vfcvt_f_xu_v_f16mf4_rm_mu(vbool64_t mask,vfloat16mf4_t maskedoff,vuint16mf4_t src,size_t vl)4396 vfloat16mf4_t test_vfcvt_f_xu_v_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t maskedoff, vuint16mf4_t src, size_t vl) {
4397 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4398 }
4399
4400 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfcvt_f_xu_v_f16mf2_rm_mu
4401 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4402 // CHECK-RV64-NEXT: entry:
4403 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF]], <vscale x 2 x i16> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4404 // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
4405 //
test_vfcvt_f_xu_v_f16mf2_rm_mu(vbool32_t mask,vfloat16mf2_t maskedoff,vuint16mf2_t src,size_t vl)4406 vfloat16mf2_t test_vfcvt_f_xu_v_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t maskedoff, vuint16mf2_t src, size_t vl) {
4407 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4408 }
4409
4410 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfcvt_f_xu_v_f16m1_rm_mu
4411 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4412 // CHECK-RV64-NEXT: entry:
4413 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x i16> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4414 // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
4415 //
test_vfcvt_f_xu_v_f16m1_rm_mu(vbool16_t mask,vfloat16m1_t maskedoff,vuint16m1_t src,size_t vl)4416 vfloat16m1_t test_vfcvt_f_xu_v_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t maskedoff, vuint16m1_t src, size_t vl) {
4417 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4418 }
4419
4420 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfcvt_f_xu_v_f16m2_rm_mu
4421 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4422 // CHECK-RV64-NEXT: entry:
4423 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF]], <vscale x 8 x i16> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4424 // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
4425 //
test_vfcvt_f_xu_v_f16m2_rm_mu(vbool8_t mask,vfloat16m2_t maskedoff,vuint16m2_t src,size_t vl)4426 vfloat16m2_t test_vfcvt_f_xu_v_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t maskedoff, vuint16m2_t src, size_t vl) {
4427 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4428 }
4429
4430 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfcvt_f_xu_v_f16m4_rm_mu
4431 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4432 // CHECK-RV64-NEXT: entry:
4433 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF]], <vscale x 16 x i16> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4434 // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
4435 //
test_vfcvt_f_xu_v_f16m4_rm_mu(vbool4_t mask,vfloat16m4_t maskedoff,vuint16m4_t src,size_t vl)4436 vfloat16m4_t test_vfcvt_f_xu_v_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t maskedoff, vuint16m4_t src, size_t vl) {
4437 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4438 }
4439
4440 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfcvt_f_xu_v_f16m8_rm_mu
4441 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4442 // CHECK-RV64-NEXT: entry:
4443 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF]], <vscale x 32 x i16> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4444 // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
4445 //
test_vfcvt_f_xu_v_f16m8_rm_mu(vbool2_t mask,vfloat16m8_t maskedoff,vuint16m8_t src,size_t vl)4446 vfloat16m8_t test_vfcvt_f_xu_v_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t maskedoff, vuint16m8_t src, size_t vl) {
4447 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4448 }
4449
4450 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_x_f_v_i32mf2_rm_mu
4451 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4452 // CHECK-RV64-NEXT: entry:
4453 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4454 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
4455 //
test_vfcvt_x_f_v_i32mf2_rm_mu(vbool64_t mask,vint32mf2_t maskedoff,vfloat32mf2_t src,size_t vl)4456 vint32mf2_t test_vfcvt_x_f_v_i32mf2_rm_mu(vbool64_t mask, vint32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
4457 return __riscv_vfcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4458 }
4459
4460 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_x_f_v_i32m1_rm_mu
4461 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4462 // CHECK-RV64-NEXT: entry:
4463 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4464 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
4465 //
test_vfcvt_x_f_v_i32m1_rm_mu(vbool32_t mask,vint32m1_t maskedoff,vfloat32m1_t src,size_t vl)4466 vint32m1_t test_vfcvt_x_f_v_i32m1_rm_mu(vbool32_t mask, vint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
4467 return __riscv_vfcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4468 }
4469
4470 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_x_f_v_i32m2_rm_mu
4471 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4472 // CHECK-RV64-NEXT: entry:
4473 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4474 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
4475 //
test_vfcvt_x_f_v_i32m2_rm_mu(vbool16_t mask,vint32m2_t maskedoff,vfloat32m2_t src,size_t vl)4476 vint32m2_t test_vfcvt_x_f_v_i32m2_rm_mu(vbool16_t mask, vint32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
4477 return __riscv_vfcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4478 }
4479
4480 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_x_f_v_i32m4_rm_mu
4481 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4482 // CHECK-RV64-NEXT: entry:
4483 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4484 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
4485 //
test_vfcvt_x_f_v_i32m4_rm_mu(vbool8_t mask,vint32m4_t maskedoff,vfloat32m4_t src,size_t vl)4486 vint32m4_t test_vfcvt_x_f_v_i32m4_rm_mu(vbool8_t mask, vint32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
4487 return __riscv_vfcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4488 }
4489
4490 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_x_f_v_i32m8_rm_mu
4491 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4492 // CHECK-RV64-NEXT: entry:
4493 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4494 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
4495 //
test_vfcvt_x_f_v_i32m8_rm_mu(vbool4_t mask,vint32m8_t maskedoff,vfloat32m8_t src,size_t vl)4496 vint32m8_t test_vfcvt_x_f_v_i32m8_rm_mu(vbool4_t mask, vint32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
4497 return __riscv_vfcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4498 }
4499
4500 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfcvt_xu_f_v_u32mf2_rm_mu
4501 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4502 // CHECK-RV64-NEXT: entry:
4503 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF]], <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4504 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
4505 //
test_vfcvt_xu_f_v_u32mf2_rm_mu(vbool64_t mask,vuint32mf2_t maskedoff,vfloat32mf2_t src,size_t vl)4506 vuint32mf2_t test_vfcvt_xu_f_v_u32mf2_rm_mu(vbool64_t mask, vuint32mf2_t maskedoff, vfloat32mf2_t src, size_t vl) {
4507 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4508 }
4509
4510 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfcvt_xu_f_v_u32m1_rm_mu
4511 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4512 // CHECK-RV64-NEXT: entry:
4513 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF]], <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4514 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
4515 //
test_vfcvt_xu_f_v_u32m1_rm_mu(vbool32_t mask,vuint32m1_t maskedoff,vfloat32m1_t src,size_t vl)4516 vuint32m1_t test_vfcvt_xu_f_v_u32m1_rm_mu(vbool32_t mask, vuint32m1_t maskedoff, vfloat32m1_t src, size_t vl) {
4517 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4518 }
4519
4520 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfcvt_xu_f_v_u32m2_rm_mu
4521 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4522 // CHECK-RV64-NEXT: entry:
4523 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF]], <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4524 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
4525 //
test_vfcvt_xu_f_v_u32m2_rm_mu(vbool16_t mask,vuint32m2_t maskedoff,vfloat32m2_t src,size_t vl)4526 vuint32m2_t test_vfcvt_xu_f_v_u32m2_rm_mu(vbool16_t mask, vuint32m2_t maskedoff, vfloat32m2_t src, size_t vl) {
4527 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4528 }
4529
4530 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfcvt_xu_f_v_u32m4_rm_mu
4531 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4532 // CHECK-RV64-NEXT: entry:
4533 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF]], <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4534 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
4535 //
test_vfcvt_xu_f_v_u32m4_rm_mu(vbool8_t mask,vuint32m4_t maskedoff,vfloat32m4_t src,size_t vl)4536 vuint32m4_t test_vfcvt_xu_f_v_u32m4_rm_mu(vbool8_t mask, vuint32m4_t maskedoff, vfloat32m4_t src, size_t vl) {
4537 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4538 }
4539
4540 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfcvt_xu_f_v_u32m8_rm_mu
4541 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4542 // CHECK-RV64-NEXT: entry:
4543 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF]], <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4544 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
4545 //
test_vfcvt_xu_f_v_u32m8_rm_mu(vbool4_t mask,vuint32m8_t maskedoff,vfloat32m8_t src,size_t vl)4546 vuint32m8_t test_vfcvt_xu_f_v_u32m8_rm_mu(vbool4_t mask, vuint32m8_t maskedoff, vfloat32m8_t src, size_t vl) {
4547 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4548 }
4549
4550 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_x_v_f32mf2_rm_mu
4551 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4552 // CHECK-RV64-NEXT: entry:
4553 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4554 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
4555 //
test_vfcvt_f_x_v_f32mf2_rm_mu(vbool64_t mask,vfloat32mf2_t maskedoff,vint32mf2_t src,size_t vl)4556 vfloat32mf2_t test_vfcvt_f_x_v_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vint32mf2_t src, size_t vl) {
4557 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4558 }
4559
4560 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_x_v_f32m1_rm_mu
4561 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4562 // CHECK-RV64-NEXT: entry:
4563 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f32.nxv2i32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4564 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
4565 //
test_vfcvt_f_x_v_f32m1_rm_mu(vbool32_t mask,vfloat32m1_t maskedoff,vint32m1_t src,size_t vl)4566 vfloat32m1_t test_vfcvt_f_x_v_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vint32m1_t src, size_t vl) {
4567 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4568 }
4569
4570 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_x_v_f32m2_rm_mu
4571 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4572 // CHECK-RV64-NEXT: entry:
4573 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f32.nxv4i32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4574 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
4575 //
test_vfcvt_f_x_v_f32m2_rm_mu(vbool16_t mask,vfloat32m2_t maskedoff,vint32m2_t src,size_t vl)4576 vfloat32m2_t test_vfcvt_f_x_v_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t maskedoff, vint32m2_t src, size_t vl) {
4577 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4578 }
4579
4580 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_x_v_f32m4_rm_mu
4581 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4582 // CHECK-RV64-NEXT: entry:
4583 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f32.nxv8i32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4584 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
4585 //
test_vfcvt_f_x_v_f32m4_rm_mu(vbool8_t mask,vfloat32m4_t maskedoff,vint32m4_t src,size_t vl)4586 vfloat32m4_t test_vfcvt_f_x_v_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t maskedoff, vint32m4_t src, size_t vl) {
4587 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4588 }
4589
4590 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_x_v_f32m8_rm_mu
4591 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4592 // CHECK-RV64-NEXT: entry:
4593 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f32.nxv16i32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4594 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
4595 //
test_vfcvt_f_x_v_f32m8_rm_mu(vbool4_t mask,vfloat32m8_t maskedoff,vint32m8_t src,size_t vl)4596 vfloat32m8_t test_vfcvt_f_x_v_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t maskedoff, vint32m8_t src, size_t vl) {
4597 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4598 }
4599
4600 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfcvt_f_xu_v_f32mf2_rm_mu
4601 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4602 // CHECK-RV64-NEXT: entry:
4603 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MASKEDOFF]], <vscale x 1 x i32> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4604 // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
4605 //
test_vfcvt_f_xu_v_f32mf2_rm_mu(vbool64_t mask,vfloat32mf2_t maskedoff,vuint32mf2_t src,size_t vl)4606 vfloat32mf2_t test_vfcvt_f_xu_v_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t maskedoff, vuint32mf2_t src, size_t vl) {
4607 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4608 }
4609
4610 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfcvt_f_xu_v_f32m1_rm_mu
4611 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4612 // CHECK-RV64-NEXT: entry:
4613 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x i32> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4614 // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
4615 //
test_vfcvt_f_xu_v_f32m1_rm_mu(vbool32_t mask,vfloat32m1_t maskedoff,vuint32m1_t src,size_t vl)4616 vfloat32m1_t test_vfcvt_f_xu_v_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vuint32m1_t src, size_t vl) {
4617 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4618 }
4619
4620 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfcvt_f_xu_v_f32m2_rm_mu
4621 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4622 // CHECK-RV64-NEXT: entry:
4623 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32.i64(<vscale x 4 x float> [[MASKEDOFF]], <vscale x 4 x i32> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4624 // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
4625 //
test_vfcvt_f_xu_v_f32m2_rm_mu(vbool16_t mask,vfloat32m2_t maskedoff,vuint32m2_t src,size_t vl)4626 vfloat32m2_t test_vfcvt_f_xu_v_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t maskedoff, vuint32m2_t src, size_t vl) {
4627 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4628 }
4629
4630 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfcvt_f_xu_v_f32m4_rm_mu
4631 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4632 // CHECK-RV64-NEXT: entry:
4633 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32.i64(<vscale x 8 x float> [[MASKEDOFF]], <vscale x 8 x i32> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4634 // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
4635 //
test_vfcvt_f_xu_v_f32m4_rm_mu(vbool8_t mask,vfloat32m4_t maskedoff,vuint32m4_t src,size_t vl)4636 vfloat32m4_t test_vfcvt_f_xu_v_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t maskedoff, vuint32m4_t src, size_t vl) {
4637 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4638 }
4639
4640 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfcvt_f_xu_v_f32m8_rm_mu
4641 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4642 // CHECK-RV64-NEXT: entry:
4643 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32.i64(<vscale x 16 x float> [[MASKEDOFF]], <vscale x 16 x i32> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4644 // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
4645 //
test_vfcvt_f_xu_v_f32m8_rm_mu(vbool4_t mask,vfloat32m8_t maskedoff,vuint32m8_t src,size_t vl)4646 vfloat32m8_t test_vfcvt_f_xu_v_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t maskedoff, vuint32m8_t src, size_t vl) {
4647 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4648 }
4649
4650 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_x_f_v_i64m1_rm_mu
4651 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4652 // CHECK-RV64-NEXT: entry:
4653 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4654 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
4655 //
test_vfcvt_x_f_v_i64m1_rm_mu(vbool64_t mask,vint64m1_t maskedoff,vfloat64m1_t src,size_t vl)4656 vint64m1_t test_vfcvt_x_f_v_i64m1_rm_mu(vbool64_t mask, vint64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
4657 return __riscv_vfcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4658 }
4659
4660 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_x_f_v_i64m2_rm_mu
4661 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4662 // CHECK-RV64-NEXT: entry:
4663 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4664 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
4665 //
test_vfcvt_x_f_v_i64m2_rm_mu(vbool32_t mask,vint64m2_t maskedoff,vfloat64m2_t src,size_t vl)4666 vint64m2_t test_vfcvt_x_f_v_i64m2_rm_mu(vbool32_t mask, vint64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
4667 return __riscv_vfcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4668 }
4669
4670 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_x_f_v_i64m4_rm_mu
4671 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4672 // CHECK-RV64-NEXT: entry:
4673 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4674 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
4675 //
test_vfcvt_x_f_v_i64m4_rm_mu(vbool16_t mask,vint64m4_t maskedoff,vfloat64m4_t src,size_t vl)4676 vint64m4_t test_vfcvt_x_f_v_i64m4_rm_mu(vbool16_t mask, vint64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
4677 return __riscv_vfcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4678 }
4679
4680 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_x_f_v_i64m8_rm_mu
4681 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4682 // CHECK-RV64-NEXT: entry:
4683 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4684 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
4685 //
test_vfcvt_x_f_v_i64m8_rm_mu(vbool8_t mask,vint64m8_t maskedoff,vfloat64m8_t src,size_t vl)4686 vint64m8_t test_vfcvt_x_f_v_i64m8_rm_mu(vbool8_t mask, vint64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
4687 return __riscv_vfcvt_x_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4688 }
4689
4690 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfcvt_xu_f_v_u64m1_rm_mu
4691 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4692 // CHECK-RV64-NEXT: entry:
4693 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF]], <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4694 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
4695 //
test_vfcvt_xu_f_v_u64m1_rm_mu(vbool64_t mask,vuint64m1_t maskedoff,vfloat64m1_t src,size_t vl)4696 vuint64m1_t test_vfcvt_xu_f_v_u64m1_rm_mu(vbool64_t mask, vuint64m1_t maskedoff, vfloat64m1_t src, size_t vl) {
4697 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4698 }
4699
4700 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfcvt_xu_f_v_u64m2_rm_mu
4701 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4702 // CHECK-RV64-NEXT: entry:
4703 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF]], <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4704 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
4705 //
test_vfcvt_xu_f_v_u64m2_rm_mu(vbool32_t mask,vuint64m2_t maskedoff,vfloat64m2_t src,size_t vl)4706 vuint64m2_t test_vfcvt_xu_f_v_u64m2_rm_mu(vbool32_t mask, vuint64m2_t maskedoff, vfloat64m2_t src, size_t vl) {
4707 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4708 }
4709
4710 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfcvt_xu_f_v_u64m4_rm_mu
4711 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4712 // CHECK-RV64-NEXT: entry:
4713 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF]], <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4714 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
4715 //
test_vfcvt_xu_f_v_u64m4_rm_mu(vbool16_t mask,vuint64m4_t maskedoff,vfloat64m4_t src,size_t vl)4716 vuint64m4_t test_vfcvt_xu_f_v_u64m4_rm_mu(vbool16_t mask, vuint64m4_t maskedoff, vfloat64m4_t src, size_t vl) {
4717 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4718 }
4719
4720 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfcvt_xu_f_v_u64m8_rm_mu
4721 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4722 // CHECK-RV64-NEXT: entry:
4723 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF]], <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4724 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
4725 //
test_vfcvt_xu_f_v_u64m8_rm_mu(vbool8_t mask,vuint64m8_t maskedoff,vfloat64m8_t src,size_t vl)4726 vuint64m8_t test_vfcvt_xu_f_v_u64m8_rm_mu(vbool8_t mask, vuint64m8_t maskedoff, vfloat64m8_t src, size_t vl) {
4727 return __riscv_vfcvt_xu_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4728 }
4729
4730 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_x_v_f64m1_rm_mu
4731 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4732 // CHECK-RV64-NEXT: entry:
4733 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f64.nxv1i64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4734 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
4735 //
test_vfcvt_f_x_v_f64m1_rm_mu(vbool64_t mask,vfloat64m1_t maskedoff,vint64m1_t src,size_t vl)4736 vfloat64m1_t test_vfcvt_f_x_v_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t maskedoff, vint64m1_t src, size_t vl) {
4737 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4738 }
4739
4740 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_x_v_f64m2_rm_mu
4741 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4742 // CHECK-RV64-NEXT: entry:
4743 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f64.nxv2i64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4744 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
4745 //
test_vfcvt_f_x_v_f64m2_rm_mu(vbool32_t mask,vfloat64m2_t maskedoff,vint64m2_t src,size_t vl)4746 vfloat64m2_t test_vfcvt_f_x_v_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t maskedoff, vint64m2_t src, size_t vl) {
4747 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4748 }
4749
4750 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_x_v_f64m4_rm_mu
4751 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4752 // CHECK-RV64-NEXT: entry:
4753 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f64.nxv4i64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4754 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
4755 //
test_vfcvt_f_x_v_f64m4_rm_mu(vbool16_t mask,vfloat64m4_t maskedoff,vint64m4_t src,size_t vl)4756 vfloat64m4_t test_vfcvt_f_x_v_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t maskedoff, vint64m4_t src, size_t vl) {
4757 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4758 }
4759
4760 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_x_v_f64m8_rm_mu
4761 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4762 // CHECK-RV64-NEXT: entry:
4763 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f64.nxv8i64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4764 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
4765 //
test_vfcvt_f_x_v_f64m8_rm_mu(vbool8_t mask,vfloat64m8_t maskedoff,vint64m8_t src,size_t vl)4766 vfloat64m8_t test_vfcvt_f_x_v_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t maskedoff, vint64m8_t src, size_t vl) {
4767 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4768 }
4769
4770 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfcvt_f_xu_v_f64m1_rm_mu
4771 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4772 // CHECK-RV64-NEXT: entry:
4773 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f64.nxv1i64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x i64> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4774 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
4775 //
test_vfcvt_f_xu_v_f64m1_rm_mu(vbool64_t mask,vfloat64m1_t maskedoff,vuint64m1_t src,size_t vl)4776 vfloat64m1_t test_vfcvt_f_xu_v_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t maskedoff, vuint64m1_t src, size_t vl) {
4777 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4778 }
4779
4780 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfcvt_f_xu_v_f64m2_rm_mu
4781 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4782 // CHECK-RV64-NEXT: entry:
4783 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f64.nxv2i64.i64(<vscale x 2 x double> [[MASKEDOFF]], <vscale x 2 x i64> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4784 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
4785 //
test_vfcvt_f_xu_v_f64m2_rm_mu(vbool32_t mask,vfloat64m2_t maskedoff,vuint64m2_t src,size_t vl)4786 vfloat64m2_t test_vfcvt_f_xu_v_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t maskedoff, vuint64m2_t src, size_t vl) {
4787 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4788 }
4789
4790 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfcvt_f_xu_v_f64m4_rm_mu
4791 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4792 // CHECK-RV64-NEXT: entry:
4793 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f64.nxv4i64.i64(<vscale x 4 x double> [[MASKEDOFF]], <vscale x 4 x i64> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4794 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
4795 //
test_vfcvt_f_xu_v_f64m4_rm_mu(vbool16_t mask,vfloat64m4_t maskedoff,vuint64m4_t src,size_t vl)4796 vfloat64m4_t test_vfcvt_f_xu_v_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t maskedoff, vuint64m4_t src, size_t vl) {
4797 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4798 }
4799
4800 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfcvt_f_xu_v_f64m8_rm_mu
4801 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4802 // CHECK-RV64-NEXT: entry:
4803 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f64.nxv8i64.i64(<vscale x 8 x double> [[MASKEDOFF]], <vscale x 8 x i64> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
4804 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
4805 //
test_vfcvt_f_xu_v_f64m8_rm_mu(vbool8_t mask,vfloat64m8_t maskedoff,vuint64m8_t src,size_t vl)4806 vfloat64m8_t test_vfcvt_f_xu_v_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t maskedoff, vuint64m8_t src, size_t vl) {
4807 return __riscv_vfcvt_f_mu(mask, maskedoff, src, __RISCV_FRM_RNE, vl);
4808 }
4809
4810