1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4 // RUN: -target-feature +zvfh -disable-O0-optnone \
5 // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
6 // RUN: FileCheck --check-prefix=CHECK-RV64 %s
7
8 #include <riscv_vector.h>
9
10 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_f64m1
11 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 1 x double> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
12 // CHECK-RV64-NEXT: entry:
13 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> [[VALUE]], ptr [[BASE]], i64 [[VL]])
14 // CHECK-RV64-NEXT: ret void
15 //
test_vse64_v_f64m1(double * base,vfloat64m1_t value,size_t vl)16 void test_vse64_v_f64m1(double *base, vfloat64m1_t value, size_t vl) {
17 return __riscv_vse64(base, value, vl);
18 }
19
20 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_f64m2
21 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 2 x double> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
22 // CHECK-RV64-NEXT: entry:
23 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2f64.i64(<vscale x 2 x double> [[VALUE]], ptr [[BASE]], i64 [[VL]])
24 // CHECK-RV64-NEXT: ret void
25 //
test_vse64_v_f64m2(double * base,vfloat64m2_t value,size_t vl)26 void test_vse64_v_f64m2(double *base, vfloat64m2_t value, size_t vl) {
27 return __riscv_vse64(base, value, vl);
28 }
29
30 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_f64m4
31 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 4 x double> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
32 // CHECK-RV64-NEXT: entry:
33 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4f64.i64(<vscale x 4 x double> [[VALUE]], ptr [[BASE]], i64 [[VL]])
34 // CHECK-RV64-NEXT: ret void
35 //
test_vse64_v_f64m4(double * base,vfloat64m4_t value,size_t vl)36 void test_vse64_v_f64m4(double *base, vfloat64m4_t value, size_t vl) {
37 return __riscv_vse64(base, value, vl);
38 }
39
40 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_f64m8
41 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 8 x double> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
42 // CHECK-RV64-NEXT: entry:
43 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8f64.i64(<vscale x 8 x double> [[VALUE]], ptr [[BASE]], i64 [[VL]])
44 // CHECK-RV64-NEXT: ret void
45 //
test_vse64_v_f64m8(double * base,vfloat64m8_t value,size_t vl)46 void test_vse64_v_f64m8(double *base, vfloat64m8_t value, size_t vl) {
47 return __riscv_vse64(base, value, vl);
48 }
49
50 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_i64m1
51 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 1 x i64> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
52 // CHECK-RV64-NEXT: entry:
53 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64> [[VALUE]], ptr [[BASE]], i64 [[VL]])
54 // CHECK-RV64-NEXT: ret void
55 //
test_vse64_v_i64m1(int64_t * base,vint64m1_t value,size_t vl)56 void test_vse64_v_i64m1(int64_t *base, vint64m1_t value, size_t vl) {
57 return __riscv_vse64(base, value, vl);
58 }
59
60 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_i64m2
61 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 2 x i64> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
62 // CHECK-RV64-NEXT: entry:
63 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i64.i64(<vscale x 2 x i64> [[VALUE]], ptr [[BASE]], i64 [[VL]])
64 // CHECK-RV64-NEXT: ret void
65 //
test_vse64_v_i64m2(int64_t * base,vint64m2_t value,size_t vl)66 void test_vse64_v_i64m2(int64_t *base, vint64m2_t value, size_t vl) {
67 return __riscv_vse64(base, value, vl);
68 }
69
70 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_i64m4
71 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 4 x i64> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
72 // CHECK-RV64-NEXT: entry:
73 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i64.i64(<vscale x 4 x i64> [[VALUE]], ptr [[BASE]], i64 [[VL]])
74 // CHECK-RV64-NEXT: ret void
75 //
test_vse64_v_i64m4(int64_t * base,vint64m4_t value,size_t vl)76 void test_vse64_v_i64m4(int64_t *base, vint64m4_t value, size_t vl) {
77 return __riscv_vse64(base, value, vl);
78 }
79
80 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_i64m8
81 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 8 x i64> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
82 // CHECK-RV64-NEXT: entry:
83 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i64.i64(<vscale x 8 x i64> [[VALUE]], ptr [[BASE]], i64 [[VL]])
84 // CHECK-RV64-NEXT: ret void
85 //
test_vse64_v_i64m8(int64_t * base,vint64m8_t value,size_t vl)86 void test_vse64_v_i64m8(int64_t *base, vint64m8_t value, size_t vl) {
87 return __riscv_vse64(base, value, vl);
88 }
89
90 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_u64m1
91 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 1 x i64> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
92 // CHECK-RV64-NEXT: entry:
93 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64> [[VALUE]], ptr [[BASE]], i64 [[VL]])
94 // CHECK-RV64-NEXT: ret void
95 //
test_vse64_v_u64m1(uint64_t * base,vuint64m1_t value,size_t vl)96 void test_vse64_v_u64m1(uint64_t *base, vuint64m1_t value, size_t vl) {
97 return __riscv_vse64(base, value, vl);
98 }
99
100 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_u64m2
101 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 2 x i64> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
102 // CHECK-RV64-NEXT: entry:
103 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2i64.i64(<vscale x 2 x i64> [[VALUE]], ptr [[BASE]], i64 [[VL]])
104 // CHECK-RV64-NEXT: ret void
105 //
test_vse64_v_u64m2(uint64_t * base,vuint64m2_t value,size_t vl)106 void test_vse64_v_u64m2(uint64_t *base, vuint64m2_t value, size_t vl) {
107 return __riscv_vse64(base, value, vl);
108 }
109
110 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_u64m4
111 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 4 x i64> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
112 // CHECK-RV64-NEXT: entry:
113 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4i64.i64(<vscale x 4 x i64> [[VALUE]], ptr [[BASE]], i64 [[VL]])
114 // CHECK-RV64-NEXT: ret void
115 //
test_vse64_v_u64m4(uint64_t * base,vuint64m4_t value,size_t vl)116 void test_vse64_v_u64m4(uint64_t *base, vuint64m4_t value, size_t vl) {
117 return __riscv_vse64(base, value, vl);
118 }
119
120 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_u64m8
121 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], <vscale x 8 x i64> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
122 // CHECK-RV64-NEXT: entry:
123 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8i64.i64(<vscale x 8 x i64> [[VALUE]], ptr [[BASE]], i64 [[VL]])
124 // CHECK-RV64-NEXT: ret void
125 //
test_vse64_v_u64m8(uint64_t * base,vuint64m8_t value,size_t vl)126 void test_vse64_v_u64m8(uint64_t *base, vuint64m8_t value, size_t vl) {
127 return __riscv_vse64(base, value, vl);
128 }
129
130 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_f64m1_m
131 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 1 x double> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
132 // CHECK-RV64-NEXT: entry:
133 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1f64.i64(<vscale x 1 x double> [[VALUE]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
134 // CHECK-RV64-NEXT: ret void
135 //
test_vse64_v_f64m1_m(vbool64_t mask,double * base,vfloat64m1_t value,size_t vl)136 void test_vse64_v_f64m1_m(vbool64_t mask, double *base, vfloat64m1_t value, size_t vl) {
137 return __riscv_vse64(mask, base, value, vl);
138 }
139
140 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_f64m2_m
141 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 2 x double> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
142 // CHECK-RV64-NEXT: entry:
143 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2f64.i64(<vscale x 2 x double> [[VALUE]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
144 // CHECK-RV64-NEXT: ret void
145 //
test_vse64_v_f64m2_m(vbool32_t mask,double * base,vfloat64m2_t value,size_t vl)146 void test_vse64_v_f64m2_m(vbool32_t mask, double *base, vfloat64m2_t value, size_t vl) {
147 return __riscv_vse64(mask, base, value, vl);
148 }
149
150 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_f64m4_m
151 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 4 x double> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
152 // CHECK-RV64-NEXT: entry:
153 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4f64.i64(<vscale x 4 x double> [[VALUE]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
154 // CHECK-RV64-NEXT: ret void
155 //
test_vse64_v_f64m4_m(vbool16_t mask,double * base,vfloat64m4_t value,size_t vl)156 void test_vse64_v_f64m4_m(vbool16_t mask, double *base, vfloat64m4_t value, size_t vl) {
157 return __riscv_vse64(mask, base, value, vl);
158 }
159
160 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_f64m8_m
161 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 8 x double> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
162 // CHECK-RV64-NEXT: entry:
163 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8f64.i64(<vscale x 8 x double> [[VALUE]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
164 // CHECK-RV64-NEXT: ret void
165 //
test_vse64_v_f64m8_m(vbool8_t mask,double * base,vfloat64m8_t value,size_t vl)166 void test_vse64_v_f64m8_m(vbool8_t mask, double *base, vfloat64m8_t value, size_t vl) {
167 return __riscv_vse64(mask, base, value, vl);
168 }
169
170 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_i64m1_m
171 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 1 x i64> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
172 // CHECK-RV64-NEXT: entry:
173 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i64.i64(<vscale x 1 x i64> [[VALUE]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
174 // CHECK-RV64-NEXT: ret void
175 //
test_vse64_v_i64m1_m(vbool64_t mask,int64_t * base,vint64m1_t value,size_t vl)176 void test_vse64_v_i64m1_m(vbool64_t mask, int64_t *base, vint64m1_t value, size_t vl) {
177 return __riscv_vse64(mask, base, value, vl);
178 }
179
180 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_i64m2_m
181 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 2 x i64> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
182 // CHECK-RV64-NEXT: entry:
183 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i64.i64(<vscale x 2 x i64> [[VALUE]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
184 // CHECK-RV64-NEXT: ret void
185 //
test_vse64_v_i64m2_m(vbool32_t mask,int64_t * base,vint64m2_t value,size_t vl)186 void test_vse64_v_i64m2_m(vbool32_t mask, int64_t *base, vint64m2_t value, size_t vl) {
187 return __riscv_vse64(mask, base, value, vl);
188 }
189
190 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_i64m4_m
191 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 4 x i64> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
192 // CHECK-RV64-NEXT: entry:
193 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i64.i64(<vscale x 4 x i64> [[VALUE]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
194 // CHECK-RV64-NEXT: ret void
195 //
test_vse64_v_i64m4_m(vbool16_t mask,int64_t * base,vint64m4_t value,size_t vl)196 void test_vse64_v_i64m4_m(vbool16_t mask, int64_t *base, vint64m4_t value, size_t vl) {
197 return __riscv_vse64(mask, base, value, vl);
198 }
199
200 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_i64m8_m
201 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 8 x i64> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
202 // CHECK-RV64-NEXT: entry:
203 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i64.i64(<vscale x 8 x i64> [[VALUE]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
204 // CHECK-RV64-NEXT: ret void
205 //
test_vse64_v_i64m8_m(vbool8_t mask,int64_t * base,vint64m8_t value,size_t vl)206 void test_vse64_v_i64m8_m(vbool8_t mask, int64_t *base, vint64m8_t value, size_t vl) {
207 return __riscv_vse64(mask, base, value, vl);
208 }
209
210 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_u64m1_m
211 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 1 x i64> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
212 // CHECK-RV64-NEXT: entry:
213 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1i64.i64(<vscale x 1 x i64> [[VALUE]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
214 // CHECK-RV64-NEXT: ret void
215 //
test_vse64_v_u64m1_m(vbool64_t mask,uint64_t * base,vuint64m1_t value,size_t vl)216 void test_vse64_v_u64m1_m(vbool64_t mask, uint64_t *base, vuint64m1_t value, size_t vl) {
217 return __riscv_vse64(mask, base, value, vl);
218 }
219
220 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_u64m2_m
221 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 2 x i64> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
222 // CHECK-RV64-NEXT: entry:
223 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2i64.i64(<vscale x 2 x i64> [[VALUE]], ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
224 // CHECK-RV64-NEXT: ret void
225 //
test_vse64_v_u64m2_m(vbool32_t mask,uint64_t * base,vuint64m2_t value,size_t vl)226 void test_vse64_v_u64m2_m(vbool32_t mask, uint64_t *base, vuint64m2_t value, size_t vl) {
227 return __riscv_vse64(mask, base, value, vl);
228 }
229
230 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_u64m4_m
231 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 4 x i64> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
232 // CHECK-RV64-NEXT: entry:
233 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4i64.i64(<vscale x 4 x i64> [[VALUE]], ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
234 // CHECK-RV64-NEXT: ret void
235 //
test_vse64_v_u64m4_m(vbool16_t mask,uint64_t * base,vuint64m4_t value,size_t vl)236 void test_vse64_v_u64m4_m(vbool16_t mask, uint64_t *base, vuint64m4_t value, size_t vl) {
237 return __riscv_vse64(mask, base, value, vl);
238 }
239
240 // CHECK-RV64-LABEL: define dso_local void @test_vse64_v_u64m8_m
241 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], <vscale x 8 x i64> [[VALUE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
242 // CHECK-RV64-NEXT: entry:
243 // CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8i64.i64(<vscale x 8 x i64> [[VALUE]], ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
244 // CHECK-RV64-NEXT: ret void
245 //
test_vse64_v_u64m8_m(vbool8_t mask,uint64_t * base,vuint64m8_t value,size_t vl)246 void test_vse64_v_u64m8_m(vbool8_t mask, uint64_t *base, vuint64m8_t value, size_t vl) {
247 return __riscv_vse64(mask, base, value, vl);
248 }
249
250