1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
4 // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
5 // RUN: FileCheck --check-prefix=CHECK-RV64 %s
6
7 #include <riscv_vector.h>
8
9 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8
10 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
11 // CHECK-RV64-NEXT: entry:
12 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> [[SRC]], i64 0, i64 [[VL]])
13 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
14 //
test_vncvt_x_x_w_i8mf8(vint16mf4_t src,size_t vl)15 vint8mf8_t test_vncvt_x_x_w_i8mf8(vint16mf4_t src, size_t vl) {
16 return __riscv_vncvt_x(src, vl);
17 }
18
19 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4
20 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
21 // CHECK-RV64-NEXT: entry:
22 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> [[SRC]], i64 0, i64 [[VL]])
23 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
24 //
test_vncvt_x_x_w_i8mf4(vint16mf2_t src,size_t vl)25 vint8mf4_t test_vncvt_x_x_w_i8mf4(vint16mf2_t src, size_t vl) {
26 return __riscv_vncvt_x(src, vl);
27 }
28
29 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2
30 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
31 // CHECK-RV64-NEXT: entry:
32 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> [[SRC]], i64 0, i64 [[VL]])
33 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
34 //
test_vncvt_x_x_w_i8mf2(vint16m1_t src,size_t vl)35 vint8mf2_t test_vncvt_x_x_w_i8mf2(vint16m1_t src, size_t vl) {
36 return __riscv_vncvt_x(src, vl);
37 }
38
39 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1
40 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
41 // CHECK-RV64-NEXT: entry:
42 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> [[SRC]], i64 0, i64 [[VL]])
43 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
44 //
test_vncvt_x_x_w_i8m1(vint16m2_t src,size_t vl)45 vint8m1_t test_vncvt_x_x_w_i8m1(vint16m2_t src, size_t vl) {
46 return __riscv_vncvt_x(src, vl);
47 }
48
49 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2
50 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
51 // CHECK-RV64-NEXT: entry:
52 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> [[SRC]], i64 0, i64 [[VL]])
53 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
54 //
test_vncvt_x_x_w_i8m2(vint16m4_t src,size_t vl)55 vint8m2_t test_vncvt_x_x_w_i8m2(vint16m4_t src, size_t vl) {
56 return __riscv_vncvt_x(src, vl);
57 }
58
59 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4
60 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
61 // CHECK-RV64-NEXT: entry:
62 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> [[SRC]], i64 0, i64 [[VL]])
63 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
64 //
test_vncvt_x_x_w_i8m4(vint16m8_t src,size_t vl)65 vint8m4_t test_vncvt_x_x_w_i8m4(vint16m8_t src, size_t vl) {
66 return __riscv_vncvt_x(src, vl);
67 }
68
69 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8
70 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
71 // CHECK-RV64-NEXT: entry:
72 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> [[SRC]], i64 0, i64 [[VL]])
73 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
74 //
test_vncvt_x_x_w_u8mf8(vuint16mf4_t src,size_t vl)75 vuint8mf8_t test_vncvt_x_x_w_u8mf8(vuint16mf4_t src, size_t vl) {
76 return __riscv_vncvt_x(src, vl);
77 }
78
79 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4
80 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
81 // CHECK-RV64-NEXT: entry:
82 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> [[SRC]], i64 0, i64 [[VL]])
83 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
84 //
test_vncvt_x_x_w_u8mf4(vuint16mf2_t src,size_t vl)85 vuint8mf4_t test_vncvt_x_x_w_u8mf4(vuint16mf2_t src, size_t vl) {
86 return __riscv_vncvt_x(src, vl);
87 }
88
89 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2
90 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
91 // CHECK-RV64-NEXT: entry:
92 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> [[SRC]], i64 0, i64 [[VL]])
93 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
94 //
test_vncvt_x_x_w_u8mf2(vuint16m1_t src,size_t vl)95 vuint8mf2_t test_vncvt_x_x_w_u8mf2(vuint16m1_t src, size_t vl) {
96 return __riscv_vncvt_x(src, vl);
97 }
98
99 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1
100 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
101 // CHECK-RV64-NEXT: entry:
102 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> [[SRC]], i64 0, i64 [[VL]])
103 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
104 //
test_vncvt_x_x_w_u8m1(vuint16m2_t src,size_t vl)105 vuint8m1_t test_vncvt_x_x_w_u8m1(vuint16m2_t src, size_t vl) {
106 return __riscv_vncvt_x(src, vl);
107 }
108
109 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2
110 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
111 // CHECK-RV64-NEXT: entry:
112 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> [[SRC]], i64 0, i64 [[VL]])
113 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
114 //
test_vncvt_x_x_w_u8m2(vuint16m4_t src,size_t vl)115 vuint8m2_t test_vncvt_x_x_w_u8m2(vuint16m4_t src, size_t vl) {
116 return __riscv_vncvt_x(src, vl);
117 }
118
119 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_u8m4
120 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
121 // CHECK-RV64-NEXT: entry:
122 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> [[SRC]], i64 0, i64 [[VL]])
123 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
124 //
test_vncvt_x_x_w_u8m4(vuint16m8_t src,size_t vl)125 vuint8m4_t test_vncvt_x_x_w_u8m4(vuint16m8_t src, size_t vl) {
126 return __riscv_vncvt_x(src, vl);
127 }
128
129 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vncvt_x_x_w_i16mf4
130 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
131 // CHECK-RV64-NEXT: entry:
132 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> [[SRC]], i64 0, i64 [[VL]])
133 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
134 //
test_vncvt_x_x_w_i16mf4(vint32mf2_t src,size_t vl)135 vint16mf4_t test_vncvt_x_x_w_i16mf4(vint32mf2_t src, size_t vl) {
136 return __riscv_vncvt_x(src, vl);
137 }
138
139 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vncvt_x_x_w_i16mf2
140 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
141 // CHECK-RV64-NEXT: entry:
142 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i32> [[SRC]], i64 0, i64 [[VL]])
143 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
144 //
test_vncvt_x_x_w_i16mf2(vint32m1_t src,size_t vl)145 vint16mf2_t test_vncvt_x_x_w_i16mf2(vint32m1_t src, size_t vl) {
146 return __riscv_vncvt_x(src, vl);
147 }
148
149 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vncvt_x_x_w_i16m1
150 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
151 // CHECK-RV64-NEXT: entry:
152 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i32> [[SRC]], i64 0, i64 [[VL]])
153 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
154 //
test_vncvt_x_x_w_i16m1(vint32m2_t src,size_t vl)155 vint16m1_t test_vncvt_x_x_w_i16m1(vint32m2_t src, size_t vl) {
156 return __riscv_vncvt_x(src, vl);
157 }
158
159 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vncvt_x_x_w_i16m2
160 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
161 // CHECK-RV64-NEXT: entry:
162 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i32> [[SRC]], i64 0, i64 [[VL]])
163 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
164 //
test_vncvt_x_x_w_i16m2(vint32m4_t src,size_t vl)165 vint16m2_t test_vncvt_x_x_w_i16m2(vint32m4_t src, size_t vl) {
166 return __riscv_vncvt_x(src, vl);
167 }
168
169 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vncvt_x_x_w_i16m4
170 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
171 // CHECK-RV64-NEXT: entry:
172 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i32> [[SRC]], i64 0, i64 [[VL]])
173 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
174 //
test_vncvt_x_x_w_i16m4(vint32m8_t src,size_t vl)175 vint16m4_t test_vncvt_x_x_w_i16m4(vint32m8_t src, size_t vl) {
176 return __riscv_vncvt_x(src, vl);
177 }
178
179 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vncvt_x_x_w_u16mf4
180 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
181 // CHECK-RV64-NEXT: entry:
182 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> [[SRC]], i64 0, i64 [[VL]])
183 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
184 //
test_vncvt_x_x_w_u16mf4(vuint32mf2_t src,size_t vl)185 vuint16mf4_t test_vncvt_x_x_w_u16mf4(vuint32mf2_t src, size_t vl) {
186 return __riscv_vncvt_x(src, vl);
187 }
188
189 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vncvt_x_x_w_u16mf2
190 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
191 // CHECK-RV64-NEXT: entry:
192 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i32> [[SRC]], i64 0, i64 [[VL]])
193 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
194 //
test_vncvt_x_x_w_u16mf2(vuint32m1_t src,size_t vl)195 vuint16mf2_t test_vncvt_x_x_w_u16mf2(vuint32m1_t src, size_t vl) {
196 return __riscv_vncvt_x(src, vl);
197 }
198
199 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vncvt_x_x_w_u16m1
200 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
201 // CHECK-RV64-NEXT: entry:
202 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i32> [[SRC]], i64 0, i64 [[VL]])
203 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
204 //
test_vncvt_x_x_w_u16m1(vuint32m2_t src,size_t vl)205 vuint16m1_t test_vncvt_x_x_w_u16m1(vuint32m2_t src, size_t vl) {
206 return __riscv_vncvt_x(src, vl);
207 }
208
209 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vncvt_x_x_w_u16m2
210 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
211 // CHECK-RV64-NEXT: entry:
212 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i32> [[SRC]], i64 0, i64 [[VL]])
213 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
214 //
test_vncvt_x_x_w_u16m2(vuint32m4_t src,size_t vl)215 vuint16m2_t test_vncvt_x_x_w_u16m2(vuint32m4_t src, size_t vl) {
216 return __riscv_vncvt_x(src, vl);
217 }
218
219 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vncvt_x_x_w_u16m4
220 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
221 // CHECK-RV64-NEXT: entry:
222 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i32> [[SRC]], i64 0, i64 [[VL]])
223 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
224 //
test_vncvt_x_x_w_u16m4(vuint32m8_t src,size_t vl)225 vuint16m4_t test_vncvt_x_x_w_u16m4(vuint32m8_t src, size_t vl) {
226 return __riscv_vncvt_x(src, vl);
227 }
228
229 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vncvt_x_x_w_i32mf2
230 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
231 // CHECK-RV64-NEXT: entry:
232 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i64> [[SRC]], i64 0, i64 [[VL]])
233 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
234 //
test_vncvt_x_x_w_i32mf2(vint64m1_t src,size_t vl)235 vint32mf2_t test_vncvt_x_x_w_i32mf2(vint64m1_t src, size_t vl) {
236 return __riscv_vncvt_x(src, vl);
237 }
238
239 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vncvt_x_x_w_i32m1
240 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
241 // CHECK-RV64-NEXT: entry:
242 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i64> [[SRC]], i64 0, i64 [[VL]])
243 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
244 //
test_vncvt_x_x_w_i32m1(vint64m2_t src,size_t vl)245 vint32m1_t test_vncvt_x_x_w_i32m1(vint64m2_t src, size_t vl) {
246 return __riscv_vncvt_x(src, vl);
247 }
248
249 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vncvt_x_x_w_i32m2
250 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
251 // CHECK-RV64-NEXT: entry:
252 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i64> [[SRC]], i64 0, i64 [[VL]])
253 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
254 //
test_vncvt_x_x_w_i32m2(vint64m4_t src,size_t vl)255 vint32m2_t test_vncvt_x_x_w_i32m2(vint64m4_t src, size_t vl) {
256 return __riscv_vncvt_x(src, vl);
257 }
258
259 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vncvt_x_x_w_i32m4
260 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
261 // CHECK-RV64-NEXT: entry:
262 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i64> [[SRC]], i64 0, i64 [[VL]])
263 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
264 //
test_vncvt_x_x_w_i32m4(vint64m8_t src,size_t vl)265 vint32m4_t test_vncvt_x_x_w_i32m4(vint64m8_t src, size_t vl) {
266 return __riscv_vncvt_x(src, vl);
267 }
268
269 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vncvt_x_x_w_u32mf2
270 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
271 // CHECK-RV64-NEXT: entry:
272 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i64> [[SRC]], i64 0, i64 [[VL]])
273 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
274 //
test_vncvt_x_x_w_u32mf2(vuint64m1_t src,size_t vl)275 vuint32mf2_t test_vncvt_x_x_w_u32mf2(vuint64m1_t src, size_t vl) {
276 return __riscv_vncvt_x(src, vl);
277 }
278
279 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vncvt_x_x_w_u32m1
280 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
281 // CHECK-RV64-NEXT: entry:
282 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i64> [[SRC]], i64 0, i64 [[VL]])
283 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
284 //
test_vncvt_x_x_w_u32m1(vuint64m2_t src,size_t vl)285 vuint32m1_t test_vncvt_x_x_w_u32m1(vuint64m2_t src, size_t vl) {
286 return __riscv_vncvt_x(src, vl);
287 }
288
289 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vncvt_x_x_w_u32m2
290 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
291 // CHECK-RV64-NEXT: entry:
292 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i64> [[SRC]], i64 0, i64 [[VL]])
293 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
294 //
test_vncvt_x_x_w_u32m2(vuint64m4_t src,size_t vl)295 vuint32m2_t test_vncvt_x_x_w_u32m2(vuint64m4_t src, size_t vl) {
296 return __riscv_vncvt_x(src, vl);
297 }
298
299 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vncvt_x_x_w_u32m4
300 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
301 // CHECK-RV64-NEXT: entry:
302 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i64> [[SRC]], i64 0, i64 [[VL]])
303 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
304 //
test_vncvt_x_x_w_u32m4(vuint64m8_t src,size_t vl)305 vuint32m4_t test_vncvt_x_x_w_u32m4(vuint64m8_t src, size_t vl) {
306 return __riscv_vncvt_x(src, vl);
307 }
308
309 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8_m
310 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
311 // CHECK-RV64-NEXT: entry:
312 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> [[SRC]], i64 0, <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
313 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
314 //
test_vncvt_x_x_w_i8mf8_m(vbool64_t mask,vint16mf4_t src,size_t vl)315 vint8mf8_t test_vncvt_x_x_w_i8mf8_m(vbool64_t mask, vint16mf4_t src, size_t vl) {
316 return __riscv_vncvt_x(mask, src, vl);
317 }
318
319 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4_m
320 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
321 // CHECK-RV64-NEXT: entry:
322 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> [[SRC]], i64 0, <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
323 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
324 //
test_vncvt_x_x_w_i8mf4_m(vbool32_t mask,vint16mf2_t src,size_t vl)325 vint8mf4_t test_vncvt_x_x_w_i8mf4_m(vbool32_t mask, vint16mf2_t src, size_t vl) {
326 return __riscv_vncvt_x(mask, src, vl);
327 }
328
329 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2_m
330 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
331 // CHECK-RV64-NEXT: entry:
332 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> [[SRC]], i64 0, <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
333 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
334 //
test_vncvt_x_x_w_i8mf2_m(vbool16_t mask,vint16m1_t src,size_t vl)335 vint8mf2_t test_vncvt_x_x_w_i8mf2_m(vbool16_t mask, vint16m1_t src, size_t vl) {
336 return __riscv_vncvt_x(mask, src, vl);
337 }
338
339 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1_m
340 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
341 // CHECK-RV64-NEXT: entry:
342 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> [[SRC]], i64 0, <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
343 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
344 //
test_vncvt_x_x_w_i8m1_m(vbool8_t mask,vint16m2_t src,size_t vl)345 vint8m1_t test_vncvt_x_x_w_i8m1_m(vbool8_t mask, vint16m2_t src, size_t vl) {
346 return __riscv_vncvt_x(mask, src, vl);
347 }
348
349 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2_m
350 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
351 // CHECK-RV64-NEXT: entry:
352 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> [[SRC]], i64 0, <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
353 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
354 //
test_vncvt_x_x_w_i8m2_m(vbool4_t mask,vint16m4_t src,size_t vl)355 vint8m2_t test_vncvt_x_x_w_i8m2_m(vbool4_t mask, vint16m4_t src, size_t vl) {
356 return __riscv_vncvt_x(mask, src, vl);
357 }
358
359 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4_m
360 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
361 // CHECK-RV64-NEXT: entry:
362 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> [[SRC]], i64 0, <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)
363 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
364 //
test_vncvt_x_x_w_i8m4_m(vbool2_t mask,vint16m8_t src,size_t vl)365 vint8m4_t test_vncvt_x_x_w_i8m4_m(vbool2_t mask, vint16m8_t src, size_t vl) {
366 return __riscv_vncvt_x(mask, src, vl);
367 }
368
369 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8_m
370 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
371 // CHECK-RV64-NEXT: entry:
372 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> [[SRC]], i64 0, <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
373 // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
374 //
test_vncvt_x_x_w_u8mf8_m(vbool64_t mask,vuint16mf4_t src,size_t vl)375 vuint8mf8_t test_vncvt_x_x_w_u8mf8_m(vbool64_t mask, vuint16mf4_t src, size_t vl) {
376 return __riscv_vncvt_x(mask, src, vl);
377 }
378
379 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4_m
380 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
381 // CHECK-RV64-NEXT: entry:
382 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> [[SRC]], i64 0, <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
383 // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
384 //
test_vncvt_x_x_w_u8mf4_m(vbool32_t mask,vuint16mf2_t src,size_t vl)385 vuint8mf4_t test_vncvt_x_x_w_u8mf4_m(vbool32_t mask, vuint16mf2_t src, size_t vl) {
386 return __riscv_vncvt_x(mask, src, vl);
387 }
388
389 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2_m
390 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
391 // CHECK-RV64-NEXT: entry:
392 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> [[SRC]], i64 0, <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
393 // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
394 //
test_vncvt_x_x_w_u8mf2_m(vbool16_t mask,vuint16m1_t src,size_t vl)395 vuint8mf2_t test_vncvt_x_x_w_u8mf2_m(vbool16_t mask, vuint16m1_t src, size_t vl) {
396 return __riscv_vncvt_x(mask, src, vl);
397 }
398
399 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1_m
400 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
401 // CHECK-RV64-NEXT: entry:
402 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> [[SRC]], i64 0, <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
403 // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
404 //
test_vncvt_x_x_w_u8m1_m(vbool8_t mask,vuint16m2_t src,size_t vl)405 vuint8m1_t test_vncvt_x_x_w_u8m1_m(vbool8_t mask, vuint16m2_t src, size_t vl) {
406 return __riscv_vncvt_x(mask, src, vl);
407 }
408
409 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2_m
410 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
411 // CHECK-RV64-NEXT: entry:
412 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> [[SRC]], i64 0, <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
413 // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
414 //
test_vncvt_x_x_w_u8m2_m(vbool4_t mask,vuint16m4_t src,size_t vl)415 vuint8m2_t test_vncvt_x_x_w_u8m2_m(vbool4_t mask, vuint16m4_t src, size_t vl) {
416 return __riscv_vncvt_x(mask, src, vl);
417 }
418
419 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_u8m4_m
420 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
421 // CHECK-RV64-NEXT: entry:
422 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> [[SRC]], i64 0, <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)
423 // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
424 //
test_vncvt_x_x_w_u8m4_m(vbool2_t mask,vuint16m8_t src,size_t vl)425 vuint8m4_t test_vncvt_x_x_w_u8m4_m(vbool2_t mask, vuint16m8_t src, size_t vl) {
426 return __riscv_vncvt_x(mask, src, vl);
427 }
428
429 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vncvt_x_x_w_i16mf4_m
430 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
431 // CHECK-RV64-NEXT: entry:
432 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> [[SRC]], i64 0, <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
433 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
434 //
test_vncvt_x_x_w_i16mf4_m(vbool64_t mask,vint32mf2_t src,size_t vl)435 vint16mf4_t test_vncvt_x_x_w_i16mf4_m(vbool64_t mask, vint32mf2_t src, size_t vl) {
436 return __riscv_vncvt_x(mask, src, vl);
437 }
438
439 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vncvt_x_x_w_i16mf2_m
440 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
441 // CHECK-RV64-NEXT: entry:
442 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i32> [[SRC]], i64 0, <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
443 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
444 //
test_vncvt_x_x_w_i16mf2_m(vbool32_t mask,vint32m1_t src,size_t vl)445 vint16mf2_t test_vncvt_x_x_w_i16mf2_m(vbool32_t mask, vint32m1_t src, size_t vl) {
446 return __riscv_vncvt_x(mask, src, vl);
447 }
448
449 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vncvt_x_x_w_i16m1_m
450 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
451 // CHECK-RV64-NEXT: entry:
452 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i32> [[SRC]], i64 0, <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
453 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
454 //
test_vncvt_x_x_w_i16m1_m(vbool16_t mask,vint32m2_t src,size_t vl)455 vint16m1_t test_vncvt_x_x_w_i16m1_m(vbool16_t mask, vint32m2_t src, size_t vl) {
456 return __riscv_vncvt_x(mask, src, vl);
457 }
458
459 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vncvt_x_x_w_i16m2_m
460 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
461 // CHECK-RV64-NEXT: entry:
462 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i32> [[SRC]], i64 0, <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
463 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
464 //
test_vncvt_x_x_w_i16m2_m(vbool8_t mask,vint32m4_t src,size_t vl)465 vint16m2_t test_vncvt_x_x_w_i16m2_m(vbool8_t mask, vint32m4_t src, size_t vl) {
466 return __riscv_vncvt_x(mask, src, vl);
467 }
468
469 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vncvt_x_x_w_i16m4_m
470 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
471 // CHECK-RV64-NEXT: entry:
472 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i32> [[SRC]], i64 0, <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
473 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
474 //
test_vncvt_x_x_w_i16m4_m(vbool4_t mask,vint32m8_t src,size_t vl)475 vint16m4_t test_vncvt_x_x_w_i16m4_m(vbool4_t mask, vint32m8_t src, size_t vl) {
476 return __riscv_vncvt_x(mask, src, vl);
477 }
478
479 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vncvt_x_x_w_u16mf4_m
480 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
481 // CHECK-RV64-NEXT: entry:
482 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> [[SRC]], i64 0, <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
483 // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
484 //
test_vncvt_x_x_w_u16mf4_m(vbool64_t mask,vuint32mf2_t src,size_t vl)485 vuint16mf4_t test_vncvt_x_x_w_u16mf4_m(vbool64_t mask, vuint32mf2_t src, size_t vl) {
486 return __riscv_vncvt_x(mask, src, vl);
487 }
488
489 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vncvt_x_x_w_u16mf2_m
490 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
491 // CHECK-RV64-NEXT: entry:
492 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i32> [[SRC]], i64 0, <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
493 // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
494 //
test_vncvt_x_x_w_u16mf2_m(vbool32_t mask,vuint32m1_t src,size_t vl)495 vuint16mf2_t test_vncvt_x_x_w_u16mf2_m(vbool32_t mask, vuint32m1_t src, size_t vl) {
496 return __riscv_vncvt_x(mask, src, vl);
497 }
498
499 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vncvt_x_x_w_u16m1_m
500 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
501 // CHECK-RV64-NEXT: entry:
502 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i32> [[SRC]], i64 0, <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
503 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
504 //
test_vncvt_x_x_w_u16m1_m(vbool16_t mask,vuint32m2_t src,size_t vl)505 vuint16m1_t test_vncvt_x_x_w_u16m1_m(vbool16_t mask, vuint32m2_t src, size_t vl) {
506 return __riscv_vncvt_x(mask, src, vl);
507 }
508
509 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vncvt_x_x_w_u16m2_m
510 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
511 // CHECK-RV64-NEXT: entry:
512 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i32> [[SRC]], i64 0, <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
513 // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
514 //
test_vncvt_x_x_w_u16m2_m(vbool8_t mask,vuint32m4_t src,size_t vl)515 vuint16m2_t test_vncvt_x_x_w_u16m2_m(vbool8_t mask, vuint32m4_t src, size_t vl) {
516 return __riscv_vncvt_x(mask, src, vl);
517 }
518
519 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vncvt_x_x_w_u16m4_m
520 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
521 // CHECK-RV64-NEXT: entry:
522 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i32> [[SRC]], i64 0, <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
523 // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
524 //
test_vncvt_x_x_w_u16m4_m(vbool4_t mask,vuint32m8_t src,size_t vl)525 vuint16m4_t test_vncvt_x_x_w_u16m4_m(vbool4_t mask, vuint32m8_t src, size_t vl) {
526 return __riscv_vncvt_x(mask, src, vl);
527 }
528
529 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vncvt_x_x_w_i32mf2_m
530 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
531 // CHECK-RV64-NEXT: entry:
532 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i64> [[SRC]], i64 0, <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
533 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
534 //
test_vncvt_x_x_w_i32mf2_m(vbool64_t mask,vint64m1_t src,size_t vl)535 vint32mf2_t test_vncvt_x_x_w_i32mf2_m(vbool64_t mask, vint64m1_t src, size_t vl) {
536 return __riscv_vncvt_x(mask, src, vl);
537 }
538
539 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vncvt_x_x_w_i32m1_m
540 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
541 // CHECK-RV64-NEXT: entry:
542 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i64> [[SRC]], i64 0, <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
543 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
544 //
test_vncvt_x_x_w_i32m1_m(vbool32_t mask,vint64m2_t src,size_t vl)545 vint32m1_t test_vncvt_x_x_w_i32m1_m(vbool32_t mask, vint64m2_t src, size_t vl) {
546 return __riscv_vncvt_x(mask, src, vl);
547 }
548
549 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vncvt_x_x_w_i32m2_m
550 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
551 // CHECK-RV64-NEXT: entry:
552 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i64> [[SRC]], i64 0, <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
553 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
554 //
test_vncvt_x_x_w_i32m2_m(vbool16_t mask,vint64m4_t src,size_t vl)555 vint32m2_t test_vncvt_x_x_w_i32m2_m(vbool16_t mask, vint64m4_t src, size_t vl) {
556 return __riscv_vncvt_x(mask, src, vl);
557 }
558
559 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vncvt_x_x_w_i32m4_m
560 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
561 // CHECK-RV64-NEXT: entry:
562 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i64> [[SRC]], i64 0, <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
563 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
564 //
test_vncvt_x_x_w_i32m4_m(vbool8_t mask,vint64m8_t src,size_t vl)565 vint32m4_t test_vncvt_x_x_w_i32m4_m(vbool8_t mask, vint64m8_t src, size_t vl) {
566 return __riscv_vncvt_x(mask, src, vl);
567 }
568
569 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vncvt_x_x_w_u32mf2_m
570 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
571 // CHECK-RV64-NEXT: entry:
572 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i64> [[SRC]], i64 0, <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
573 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
574 //
test_vncvt_x_x_w_u32mf2_m(vbool64_t mask,vuint64m1_t src,size_t vl)575 vuint32mf2_t test_vncvt_x_x_w_u32mf2_m(vbool64_t mask, vuint64m1_t src, size_t vl) {
576 return __riscv_vncvt_x(mask, src, vl);
577 }
578
579 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vncvt_x_x_w_u32m1_m
580 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
581 // CHECK-RV64-NEXT: entry:
582 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i64> [[SRC]], i64 0, <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
583 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
584 //
test_vncvt_x_x_w_u32m1_m(vbool32_t mask,vuint64m2_t src,size_t vl)585 vuint32m1_t test_vncvt_x_x_w_u32m1_m(vbool32_t mask, vuint64m2_t src, size_t vl) {
586 return __riscv_vncvt_x(mask, src, vl);
587 }
588
589 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vncvt_x_x_w_u32m2_m
590 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
591 // CHECK-RV64-NEXT: entry:
592 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i64> [[SRC]], i64 0, <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
593 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
594 //
test_vncvt_x_x_w_u32m2_m(vbool16_t mask,vuint64m4_t src,size_t vl)595 vuint32m2_t test_vncvt_x_x_w_u32m2_m(vbool16_t mask, vuint64m4_t src, size_t vl) {
596 return __riscv_vncvt_x(mask, src, vl);
597 }
598
599 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vncvt_x_x_w_u32m4_m
600 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
601 // CHECK-RV64-NEXT: entry:
602 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i64> [[SRC]], i64 0, <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
603 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
604 //
test_vncvt_x_x_w_u32m4_m(vbool8_t mask,vuint64m8_t src,size_t vl)605 vuint32m4_t test_vncvt_x_x_w_u32m4_m(vbool8_t mask, vuint64m8_t src, size_t vl) {
606 return __riscv_vncvt_x(mask, src, vl);
607 }
608
609