1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
4 // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
5 // RUN: FileCheck --check-prefix=CHECK-RV64 %s
6
7 #include <riscv_vector.h>
8
9 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmsof_m_b1
10 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
11 // CHECK-RV64-NEXT: entry:
12 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1> [[OP1]], i64 [[VL]])
13 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
14 //
test_vmsof_m_b1(vbool1_t op1,size_t vl)15 vbool1_t test_vmsof_m_b1(vbool1_t op1, size_t vl) {
16 return __riscv_vmsof(op1, vl);
17 }
18
19 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsof_m_b2
20 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
21 // CHECK-RV64-NEXT: entry:
22 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1> [[OP1]], i64 [[VL]])
23 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
24 //
test_vmsof_m_b2(vbool2_t op1,size_t vl)25 vbool2_t test_vmsof_m_b2(vbool2_t op1, size_t vl) {
26 return __riscv_vmsof(op1, vl);
27 }
28
29 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsof_m_b4
30 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
31 // CHECK-RV64-NEXT: entry:
32 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1> [[OP1]], i64 [[VL]])
33 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
34 //
test_vmsof_m_b4(vbool4_t op1,size_t vl)35 vbool4_t test_vmsof_m_b4(vbool4_t op1, size_t vl) {
36 return __riscv_vmsof(op1, vl);
37 }
38
39 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsof_m_b8
40 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
41 // CHECK-RV64-NEXT: entry:
42 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1> [[OP1]], i64 [[VL]])
43 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
44 //
test_vmsof_m_b8(vbool8_t op1,size_t vl)45 vbool8_t test_vmsof_m_b8(vbool8_t op1, size_t vl) {
46 return __riscv_vmsof(op1, vl);
47 }
48
49 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsof_m_b16
50 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
51 // CHECK-RV64-NEXT: entry:
52 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1> [[OP1]], i64 [[VL]])
53 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
54 //
test_vmsof_m_b16(vbool16_t op1,size_t vl)55 vbool16_t test_vmsof_m_b16(vbool16_t op1, size_t vl) {
56 return __riscv_vmsof(op1, vl);
57 }
58
59 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsof_m_b32
60 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
61 // CHECK-RV64-NEXT: entry:
62 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1> [[OP1]], i64 [[VL]])
63 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
64 //
test_vmsof_m_b32(vbool32_t op1,size_t vl)65 vbool32_t test_vmsof_m_b32(vbool32_t op1, size_t vl) {
66 return __riscv_vmsof(op1, vl);
67 }
68
69 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsof_m_b64
70 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
71 // CHECK-RV64-NEXT: entry:
72 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1> [[OP1]], i64 [[VL]])
73 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
74 //
test_vmsof_m_b64(vbool64_t op1,size_t vl)75 vbool64_t test_vmsof_m_b64(vbool64_t op1, size_t vl) {
76 return __riscv_vmsof(op1, vl);
77 }
78
79 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_m
80 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
81 // CHECK-RV64-NEXT: entry:
82 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> [[OP1]], <vscale x 64 x i1> [[MASK]], i64 [[VL]])
83 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
84 //
test_vmsof_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)85 vbool1_t test_vmsof_m_b1_m(vbool1_t mask, vbool1_t op1, size_t vl) {
86 return __riscv_vmsof(mask, op1, vl);
87 }
88
89 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_m
90 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
91 // CHECK-RV64-NEXT: entry:
92 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> [[OP1]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
93 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
94 //
test_vmsof_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)95 vbool2_t test_vmsof_m_b2_m(vbool2_t mask, vbool2_t op1, size_t vl) {
96 return __riscv_vmsof(mask, op1, vl);
97 }
98
99 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_m
100 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
101 // CHECK-RV64-NEXT: entry:
102 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> [[OP1]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
103 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
104 //
test_vmsof_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)105 vbool4_t test_vmsof_m_b4_m(vbool4_t mask, vbool4_t op1, size_t vl) {
106 return __riscv_vmsof(mask, op1, vl);
107 }
108
109 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_m
110 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
111 // CHECK-RV64-NEXT: entry:
112 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> [[OP1]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
113 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
114 //
test_vmsof_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)115 vbool8_t test_vmsof_m_b8_m(vbool8_t mask, vbool8_t op1, size_t vl) {
116 return __riscv_vmsof(mask, op1, vl);
117 }
118
119 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_m
120 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
121 // CHECK-RV64-NEXT: entry:
122 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> [[OP1]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
123 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
124 //
test_vmsof_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)125 vbool16_t test_vmsof_m_b16_m(vbool16_t mask, vbool16_t op1, size_t vl) {
126 return __riscv_vmsof(mask, op1, vl);
127 }
128
129 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsof_m_b32_m
130 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
131 // CHECK-RV64-NEXT: entry:
132 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1> poison, <vscale x 2 x i1> [[OP1]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
133 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
134 //
test_vmsof_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)135 vbool32_t test_vmsof_m_b32_m(vbool32_t mask, vbool32_t op1, size_t vl) {
136 return __riscv_vmsof(mask, op1, vl);
137 }
138
139 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsof_m_b64_m
140 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
141 // CHECK-RV64-NEXT: entry:
142 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1> poison, <vscale x 1 x i1> [[OP1]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
143 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
144 //
test_vmsof_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)145 vbool64_t test_vmsof_m_b64_m(vbool64_t mask, vbool64_t op1, size_t vl) {
146 return __riscv_vmsof(mask, op1, vl);
147 }
148
149