1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4 // RUN: -target-feature +zvfh -disable-O0-optnone \
5 // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
6 // RUN: FileCheck --check-prefix=CHECK-RV64 %s
7
8 #include <riscv_vector.h>
9
10 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1_m
11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
12 // CHECK-RV64-NEXT: entry:
13 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.mask.nxv1f64.i64(<vscale x 1 x double> poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
14 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x double>, i64 } [[TMP0]], 0
15 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x double>, i64 } [[TMP0]], 1
16 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
17 // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
18 //
test_vle64ff_v_f64m1_m(vbool64_t mask,const double * base,size_t * new_vl,size_t vl)19 vfloat64m1_t test_vle64ff_v_f64m1_m(vbool64_t mask, const double *base, size_t *new_vl, size_t vl) {
20 return __riscv_vle64ff(mask, base, new_vl, vl);
21 }
22
23 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2_m
24 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
25 // CHECK-RV64-NEXT: entry:
26 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.mask.nxv2f64.i64(<vscale x 2 x double> poison, ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
27 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x double>, i64 } [[TMP0]], 0
28 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x double>, i64 } [[TMP0]], 1
29 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
30 // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
31 //
test_vle64ff_v_f64m2_m(vbool32_t mask,const double * base,size_t * new_vl,size_t vl)32 vfloat64m2_t test_vle64ff_v_f64m2_m(vbool32_t mask, const double *base, size_t *new_vl, size_t vl) {
33 return __riscv_vle64ff(mask, base, new_vl, vl);
34 }
35
36 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4_m
37 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
38 // CHECK-RV64-NEXT: entry:
39 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.mask.nxv4f64.i64(<vscale x 4 x double> poison, ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
40 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x double>, i64 } [[TMP0]], 0
41 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x double>, i64 } [[TMP0]], 1
42 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
43 // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
44 //
test_vle64ff_v_f64m4_m(vbool16_t mask,const double * base,size_t * new_vl,size_t vl)45 vfloat64m4_t test_vle64ff_v_f64m4_m(vbool16_t mask, const double *base, size_t *new_vl, size_t vl) {
46 return __riscv_vle64ff(mask, base, new_vl, vl);
47 }
48
49 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8_m
50 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
51 // CHECK-RV64-NEXT: entry:
52 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.mask.nxv8f64.i64(<vscale x 8 x double> poison, ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
53 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x double>, i64 } [[TMP0]], 0
54 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x double>, i64 } [[TMP0]], 1
55 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
56 // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
57 //
test_vle64ff_v_f64m8_m(vbool8_t mask,const double * base,size_t * new_vl,size_t vl)58 vfloat64m8_t test_vle64ff_v_f64m8_m(vbool8_t mask, const double *base, size_t *new_vl, size_t vl) {
59 return __riscv_vle64ff(mask, base, new_vl, vl);
60 }
61
62 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1_m
63 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
64 // CHECK-RV64-NEXT: entry:
65 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.mask.nxv1i64.i64(<vscale x 1 x i64> poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
66 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP0]], 0
67 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP0]], 1
68 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
69 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
70 //
test_vle64ff_v_i64m1_m(vbool64_t mask,const int64_t * base,size_t * new_vl,size_t vl)71 vint64m1_t test_vle64ff_v_i64m1_m(vbool64_t mask, const int64_t *base, size_t *new_vl, size_t vl) {
72 return __riscv_vle64ff(mask, base, new_vl, vl);
73 }
74
75 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2_m
76 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
77 // CHECK-RV64-NEXT: entry:
78 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.mask.nxv2i64.i64(<vscale x 2 x i64> poison, ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
79 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP0]], 0
80 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP0]], 1
81 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
82 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
83 //
test_vle64ff_v_i64m2_m(vbool32_t mask,const int64_t * base,size_t * new_vl,size_t vl)84 vint64m2_t test_vle64ff_v_i64m2_m(vbool32_t mask, const int64_t *base, size_t *new_vl, size_t vl) {
85 return __riscv_vle64ff(mask, base, new_vl, vl);
86 }
87
88 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4_m
89 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
90 // CHECK-RV64-NEXT: entry:
91 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.mask.nxv4i64.i64(<vscale x 4 x i64> poison, ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
92 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP0]], 0
93 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP0]], 1
94 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
95 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
96 //
test_vle64ff_v_i64m4_m(vbool16_t mask,const int64_t * base,size_t * new_vl,size_t vl)97 vint64m4_t test_vle64ff_v_i64m4_m(vbool16_t mask, const int64_t *base, size_t *new_vl, size_t vl) {
98 return __riscv_vle64ff(mask, base, new_vl, vl);
99 }
100
101 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8_m
102 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
103 // CHECK-RV64-NEXT: entry:
104 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.mask.nxv8i64.i64(<vscale x 8 x i64> poison, ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
105 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP0]], 0
106 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP0]], 1
107 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
108 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
109 //
test_vle64ff_v_i64m8_m(vbool8_t mask,const int64_t * base,size_t * new_vl,size_t vl)110 vint64m8_t test_vle64ff_v_i64m8_m(vbool8_t mask, const int64_t *base, size_t *new_vl, size_t vl) {
111 return __riscv_vle64ff(mask, base, new_vl, vl);
112 }
113
114 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vle64ff_v_u64m1_m
115 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
116 // CHECK-RV64-NEXT: entry:
117 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.mask.nxv1i64.i64(<vscale x 1 x i64> poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
118 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP0]], 0
119 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i64>, i64 } [[TMP0]], 1
120 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
121 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
122 //
test_vle64ff_v_u64m1_m(vbool64_t mask,const uint64_t * base,size_t * new_vl,size_t vl)123 vuint64m1_t test_vle64ff_v_u64m1_m(vbool64_t mask, const uint64_t *base, size_t *new_vl, size_t vl) {
124 return __riscv_vle64ff(mask, base, new_vl, vl);
125 }
126
127 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vle64ff_v_u64m2_m
128 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
129 // CHECK-RV64-NEXT: entry:
130 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.mask.nxv2i64.i64(<vscale x 2 x i64> poison, ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
131 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP0]], 0
132 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 2 x i64>, i64 } [[TMP0]], 1
133 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
134 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
135 //
test_vle64ff_v_u64m2_m(vbool32_t mask,const uint64_t * base,size_t * new_vl,size_t vl)136 vuint64m2_t test_vle64ff_v_u64m2_m(vbool32_t mask, const uint64_t *base, size_t *new_vl, size_t vl) {
137 return __riscv_vle64ff(mask, base, new_vl, vl);
138 }
139
140 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vle64ff_v_u64m4_m
141 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
142 // CHECK-RV64-NEXT: entry:
143 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.mask.nxv4i64.i64(<vscale x 4 x i64> poison, ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
144 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP0]], 0
145 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 4 x i64>, i64 } [[TMP0]], 1
146 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
147 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
148 //
test_vle64ff_v_u64m4_m(vbool16_t mask,const uint64_t * base,size_t * new_vl,size_t vl)149 vuint64m4_t test_vle64ff_v_u64m4_m(vbool16_t mask, const uint64_t *base, size_t *new_vl, size_t vl) {
150 return __riscv_vle64ff(mask, base, new_vl, vl);
151 }
152
153 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vle64ff_v_u64m8_m
154 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
155 // CHECK-RV64-NEXT: entry:
156 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.mask.nxv8i64.i64(<vscale x 8 x i64> poison, ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
157 // CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP0]], 0
158 // CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 8 x i64>, i64 } [[TMP0]], 1
159 // CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8
160 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
161 //
test_vle64ff_v_u64m8_m(vbool8_t mask,const uint64_t * base,size_t * new_vl,size_t vl)162 vuint64m8_t test_vle64ff_v_u64m8_m(vbool8_t mask, const uint64_t *base, size_t *new_vl, size_t vl) {
163 return __riscv_vle64ff(mask, base, new_vl, vl);
164 }
165
166