1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4 // RUN: -target-feature +zvfh -disable-O0-optnone \
5 // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
6 // RUN: FileCheck --check-prefix=CHECK-RV64 %s
7
8 #include <riscv_vector.h>
9
10 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2
11 // CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
12 // CHECK-RV64-NEXT: entry:
13 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> [[SRC]], i64 [[VL]])
14 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
15 //
test_vfwcvt_rtz_x_f_v_i32mf2(vfloat16mf4_t src,size_t vl)16 vint32mf2_t test_vfwcvt_rtz_x_f_v_i32mf2(vfloat16mf4_t src, size_t vl) {
17 return __riscv_vfwcvt_rtz_x(src, vl);
18 }
19
20 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1
21 // CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
22 // CHECK-RV64-NEXT: entry:
23 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> [[SRC]], i64 [[VL]])
24 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
25 //
test_vfwcvt_rtz_x_f_v_i32m1(vfloat16mf2_t src,size_t vl)26 vint32m1_t test_vfwcvt_rtz_x_f_v_i32m1(vfloat16mf2_t src, size_t vl) {
27 return __riscv_vfwcvt_rtz_x(src, vl);
28 }
29
30 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2
31 // CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
32 // CHECK-RV64-NEXT: entry:
33 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> [[SRC]], i64 [[VL]])
34 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
35 //
test_vfwcvt_rtz_x_f_v_i32m2(vfloat16m1_t src,size_t vl)36 vint32m2_t test_vfwcvt_rtz_x_f_v_i32m2(vfloat16m1_t src, size_t vl) {
37 return __riscv_vfwcvt_rtz_x(src, vl);
38 }
39
40 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4
41 // CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
42 // CHECK-RV64-NEXT: entry:
43 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> [[SRC]], i64 [[VL]])
44 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
45 //
test_vfwcvt_rtz_x_f_v_i32m4(vfloat16m2_t src,size_t vl)46 vint32m4_t test_vfwcvt_rtz_x_f_v_i32m4(vfloat16m2_t src, size_t vl) {
47 return __riscv_vfwcvt_rtz_x(src, vl);
48 }
49
50 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8
51 // CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
52 // CHECK-RV64-NEXT: entry:
53 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> [[SRC]], i64 [[VL]])
54 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
55 //
test_vfwcvt_rtz_x_f_v_i32m8(vfloat16m4_t src,size_t vl)56 vint32m8_t test_vfwcvt_rtz_x_f_v_i32m8(vfloat16m4_t src, size_t vl) {
57 return __riscv_vfwcvt_rtz_x(src, vl);
58 }
59
60 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2
61 // CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
62 // CHECK-RV64-NEXT: entry:
63 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> [[SRC]], i64 [[VL]])
64 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
65 //
test_vfwcvt_rtz_xu_f_v_u32mf2(vfloat16mf4_t src,size_t vl)66 vuint32mf2_t test_vfwcvt_rtz_xu_f_v_u32mf2(vfloat16mf4_t src, size_t vl) {
67 return __riscv_vfwcvt_rtz_xu(src, vl);
68 }
69
70 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1
71 // CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
72 // CHECK-RV64-NEXT: entry:
73 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> [[SRC]], i64 [[VL]])
74 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
75 //
test_vfwcvt_rtz_xu_f_v_u32m1(vfloat16mf2_t src,size_t vl)76 vuint32m1_t test_vfwcvt_rtz_xu_f_v_u32m1(vfloat16mf2_t src, size_t vl) {
77 return __riscv_vfwcvt_rtz_xu(src, vl);
78 }
79
80 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2
81 // CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
82 // CHECK-RV64-NEXT: entry:
83 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> [[SRC]], i64 [[VL]])
84 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
85 //
test_vfwcvt_rtz_xu_f_v_u32m2(vfloat16m1_t src,size_t vl)86 vuint32m2_t test_vfwcvt_rtz_xu_f_v_u32m2(vfloat16m1_t src, size_t vl) {
87 return __riscv_vfwcvt_rtz_xu(src, vl);
88 }
89
90 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4
91 // CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
92 // CHECK-RV64-NEXT: entry:
93 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> [[SRC]], i64 [[VL]])
94 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
95 //
test_vfwcvt_rtz_xu_f_v_u32m4(vfloat16m2_t src,size_t vl)96 vuint32m4_t test_vfwcvt_rtz_xu_f_v_u32m4(vfloat16m2_t src, size_t vl) {
97 return __riscv_vfwcvt_rtz_xu(src, vl);
98 }
99
100 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8
101 // CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
102 // CHECK-RV64-NEXT: entry:
103 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> [[SRC]], i64 [[VL]])
104 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
105 //
test_vfwcvt_rtz_xu_f_v_u32m8(vfloat16m4_t src,size_t vl)106 vuint32m8_t test_vfwcvt_rtz_xu_f_v_u32m8(vfloat16m4_t src, size_t vl) {
107 return __riscv_vfwcvt_rtz_xu(src, vl);
108 }
109
110 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_x_f_v_i64m1
111 // CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
112 // CHECK-RV64-NEXT: entry:
113 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> [[SRC]], i64 [[VL]])
114 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
115 //
test_vfwcvt_rtz_x_f_v_i64m1(vfloat32mf2_t src,size_t vl)116 vint64m1_t test_vfwcvt_rtz_x_f_v_i64m1(vfloat32mf2_t src, size_t vl) {
117 return __riscv_vfwcvt_rtz_x(src, vl);
118 }
119
120 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_x_f_v_i64m2
121 // CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
122 // CHECK-RV64-NEXT: entry:
123 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> [[SRC]], i64 [[VL]])
124 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
125 //
test_vfwcvt_rtz_x_f_v_i64m2(vfloat32m1_t src,size_t vl)126 vint64m2_t test_vfwcvt_rtz_x_f_v_i64m2(vfloat32m1_t src, size_t vl) {
127 return __riscv_vfwcvt_rtz_x(src, vl);
128 }
129
130 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_rtz_x_f_v_i64m4
131 // CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
132 // CHECK-RV64-NEXT: entry:
133 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> poison, <vscale x 4 x float> [[SRC]], i64 [[VL]])
134 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
135 //
test_vfwcvt_rtz_x_f_v_i64m4(vfloat32m2_t src,size_t vl)136 vint64m4_t test_vfwcvt_rtz_x_f_v_i64m4(vfloat32m2_t src, size_t vl) {
137 return __riscv_vfwcvt_rtz_x(src, vl);
138 }
139
140 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_rtz_x_f_v_i64m8
141 // CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
142 // CHECK-RV64-NEXT: entry:
143 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> poison, <vscale x 8 x float> [[SRC]], i64 [[VL]])
144 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
145 //
test_vfwcvt_rtz_x_f_v_i64m8(vfloat32m4_t src,size_t vl)146 vint64m8_t test_vfwcvt_rtz_x_f_v_i64m8(vfloat32m4_t src, size_t vl) {
147 return __riscv_vfwcvt_rtz_x(src, vl);
148 }
149
150 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_xu_f_v_u64m1
151 // CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
152 // CHECK-RV64-NEXT: entry:
153 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> [[SRC]], i64 [[VL]])
154 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
155 //
test_vfwcvt_rtz_xu_f_v_u64m1(vfloat32mf2_t src,size_t vl)156 vuint64m1_t test_vfwcvt_rtz_xu_f_v_u64m1(vfloat32mf2_t src, size_t vl) {
157 return __riscv_vfwcvt_rtz_xu(src, vl);
158 }
159
160 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_xu_f_v_u64m2
161 // CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
162 // CHECK-RV64-NEXT: entry:
163 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> [[SRC]], i64 [[VL]])
164 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
165 //
test_vfwcvt_rtz_xu_f_v_u64m2(vfloat32m1_t src,size_t vl)166 vuint64m2_t test_vfwcvt_rtz_xu_f_v_u64m2(vfloat32m1_t src, size_t vl) {
167 return __riscv_vfwcvt_rtz_xu(src, vl);
168 }
169
170 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_rtz_xu_f_v_u64m4
171 // CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
172 // CHECK-RV64-NEXT: entry:
173 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> poison, <vscale x 4 x float> [[SRC]], i64 [[VL]])
174 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
175 //
test_vfwcvt_rtz_xu_f_v_u64m4(vfloat32m2_t src,size_t vl)176 vuint64m4_t test_vfwcvt_rtz_xu_f_v_u64m4(vfloat32m2_t src, size_t vl) {
177 return __riscv_vfwcvt_rtz_xu(src, vl);
178 }
179
180 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_rtz_xu_f_v_u64m8
181 // CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
182 // CHECK-RV64-NEXT: entry:
183 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> poison, <vscale x 8 x float> [[SRC]], i64 [[VL]])
184 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
185 //
test_vfwcvt_rtz_xu_f_v_u64m8(vfloat32m4_t src,size_t vl)186 vuint64m8_t test_vfwcvt_rtz_xu_f_v_u64m8(vfloat32m4_t src, size_t vl) {
187 return __riscv_vfwcvt_rtz_xu(src, vl);
188 }
189
190 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2_m
191 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
192 // CHECK-RV64-NEXT: entry:
193 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
194 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
195 //
test_vfwcvt_rtz_x_f_v_i32mf2_m(vbool64_t mask,vfloat16mf4_t src,size_t vl)196 vint32mf2_t test_vfwcvt_rtz_x_f_v_i32mf2_m(vbool64_t mask, vfloat16mf4_t src, size_t vl) {
197 return __riscv_vfwcvt_rtz_x(mask, src, vl);
198 }
199
200 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1_m
201 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
202 // CHECK-RV64-NEXT: entry:
203 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
204 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
205 //
test_vfwcvt_rtz_x_f_v_i32m1_m(vbool32_t mask,vfloat16mf2_t src,size_t vl)206 vint32m1_t test_vfwcvt_rtz_x_f_v_i32m1_m(vbool32_t mask, vfloat16mf2_t src, size_t vl) {
207 return __riscv_vfwcvt_rtz_x(mask, src, vl);
208 }
209
210 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2_m
211 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
212 // CHECK-RV64-NEXT: entry:
213 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
214 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
215 //
test_vfwcvt_rtz_x_f_v_i32m2_m(vbool16_t mask,vfloat16m1_t src,size_t vl)216 vint32m2_t test_vfwcvt_rtz_x_f_v_i32m2_m(vbool16_t mask, vfloat16m1_t src, size_t vl) {
217 return __riscv_vfwcvt_rtz_x(mask, src, vl);
218 }
219
220 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4_m
221 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
222 // CHECK-RV64-NEXT: entry:
223 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
224 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
225 //
test_vfwcvt_rtz_x_f_v_i32m4_m(vbool8_t mask,vfloat16m2_t src,size_t vl)226 vint32m4_t test_vfwcvt_rtz_x_f_v_i32m4_m(vbool8_t mask, vfloat16m2_t src, size_t vl) {
227 return __riscv_vfwcvt_rtz_x(mask, src, vl);
228 }
229
230 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8_m
231 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
232 // CHECK-RV64-NEXT: entry:
233 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
234 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
235 //
test_vfwcvt_rtz_x_f_v_i32m8_m(vbool4_t mask,vfloat16m4_t src,size_t vl)236 vint32m8_t test_vfwcvt_rtz_x_f_v_i32m8_m(vbool4_t mask, vfloat16m4_t src, size_t vl) {
237 return __riscv_vfwcvt_rtz_x(mask, src, vl);
238 }
239
240 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2_m
241 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
242 // CHECK-RV64-NEXT: entry:
243 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
244 // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
245 //
test_vfwcvt_rtz_xu_f_v_u32mf2_m(vbool64_t mask,vfloat16mf4_t src,size_t vl)246 vuint32mf2_t test_vfwcvt_rtz_xu_f_v_u32mf2_m(vbool64_t mask, vfloat16mf4_t src, size_t vl) {
247 return __riscv_vfwcvt_rtz_xu(mask, src, vl);
248 }
249
250 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1_m
251 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
252 // CHECK-RV64-NEXT: entry:
253 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
254 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
255 //
test_vfwcvt_rtz_xu_f_v_u32m1_m(vbool32_t mask,vfloat16mf2_t src,size_t vl)256 vuint32m1_t test_vfwcvt_rtz_xu_f_v_u32m1_m(vbool32_t mask, vfloat16mf2_t src, size_t vl) {
257 return __riscv_vfwcvt_rtz_xu(mask, src, vl);
258 }
259
260 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2_m
261 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
262 // CHECK-RV64-NEXT: entry:
263 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
264 // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
265 //
test_vfwcvt_rtz_xu_f_v_u32m2_m(vbool16_t mask,vfloat16m1_t src,size_t vl)266 vuint32m2_t test_vfwcvt_rtz_xu_f_v_u32m2_m(vbool16_t mask, vfloat16m1_t src, size_t vl) {
267 return __riscv_vfwcvt_rtz_xu(mask, src, vl);
268 }
269
270 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4_m
271 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
272 // CHECK-RV64-NEXT: entry:
273 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
274 // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
275 //
test_vfwcvt_rtz_xu_f_v_u32m4_m(vbool8_t mask,vfloat16m2_t src,size_t vl)276 vuint32m4_t test_vfwcvt_rtz_xu_f_v_u32m4_m(vbool8_t mask, vfloat16m2_t src, size_t vl) {
277 return __riscv_vfwcvt_rtz_xu(mask, src, vl);
278 }
279
280 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8_m
281 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
282 // CHECK-RV64-NEXT: entry:
283 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
284 // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
285 //
test_vfwcvt_rtz_xu_f_v_u32m8_m(vbool4_t mask,vfloat16m4_t src,size_t vl)286 vuint32m8_t test_vfwcvt_rtz_xu_f_v_u32m8_m(vbool4_t mask, vfloat16m4_t src, size_t vl) {
287 return __riscv_vfwcvt_rtz_xu(mask, src, vl);
288 }
289
290 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_x_f_v_i64m1_m
291 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
292 // CHECK-RV64-NEXT: entry:
293 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
294 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
295 //
test_vfwcvt_rtz_x_f_v_i64m1_m(vbool64_t mask,vfloat32mf2_t src,size_t vl)296 vint64m1_t test_vfwcvt_rtz_x_f_v_i64m1_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {
297 return __riscv_vfwcvt_rtz_x(mask, src, vl);
298 }
299
300 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_x_f_v_i64m2_m
301 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
302 // CHECK-RV64-NEXT: entry:
303 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
304 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
305 //
test_vfwcvt_rtz_x_f_v_i64m2_m(vbool32_t mask,vfloat32m1_t src,size_t vl)306 vint64m2_t test_vfwcvt_rtz_x_f_v_i64m2_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {
307 return __riscv_vfwcvt_rtz_x(mask, src, vl);
308 }
309
310 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_rtz_x_f_v_i64m4_m
311 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
312 // CHECK-RV64-NEXT: entry:
313 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> poison, <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
314 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
315 //
test_vfwcvt_rtz_x_f_v_i64m4_m(vbool16_t mask,vfloat32m2_t src,size_t vl)316 vint64m4_t test_vfwcvt_rtz_x_f_v_i64m4_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {
317 return __riscv_vfwcvt_rtz_x(mask, src, vl);
318 }
319
320 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_rtz_x_f_v_i64m8_m
321 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
322 // CHECK-RV64-NEXT: entry:
323 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> poison, <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
324 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
325 //
test_vfwcvt_rtz_x_f_v_i64m8_m(vbool8_t mask,vfloat32m4_t src,size_t vl)326 vint64m8_t test_vfwcvt_rtz_x_f_v_i64m8_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {
327 return __riscv_vfwcvt_rtz_x(mask, src, vl);
328 }
329
330 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_xu_f_v_u64m1_m
331 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
332 // CHECK-RV64-NEXT: entry:
333 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
334 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
335 //
test_vfwcvt_rtz_xu_f_v_u64m1_m(vbool64_t mask,vfloat32mf2_t src,size_t vl)336 vuint64m1_t test_vfwcvt_rtz_xu_f_v_u64m1_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {
337 return __riscv_vfwcvt_rtz_xu(mask, src, vl);
338 }
339
340 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_xu_f_v_u64m2_m
341 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
342 // CHECK-RV64-NEXT: entry:
343 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
344 // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
345 //
test_vfwcvt_rtz_xu_f_v_u64m2_m(vbool32_t mask,vfloat32m1_t src,size_t vl)346 vuint64m2_t test_vfwcvt_rtz_xu_f_v_u64m2_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {
347 return __riscv_vfwcvt_rtz_xu(mask, src, vl);
348 }
349
350 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vfwcvt_rtz_xu_f_v_u64m4_m
351 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
352 // CHECK-RV64-NEXT: entry:
353 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> poison, <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
354 // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
355 //
test_vfwcvt_rtz_xu_f_v_u64m4_m(vbool16_t mask,vfloat32m2_t src,size_t vl)356 vuint64m4_t test_vfwcvt_rtz_xu_f_v_u64m4_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {
357 return __riscv_vfwcvt_rtz_xu(mask, src, vl);
358 }
359
360 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vfwcvt_rtz_xu_f_v_u64m8_m
361 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
362 // CHECK-RV64-NEXT: entry:
363 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> poison, <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
364 // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
365 //
test_vfwcvt_rtz_xu_f_v_u64m8_m(vbool8_t mask,vfloat32m4_t src,size_t vl)366 vuint64m8_t test_vfwcvt_rtz_xu_f_v_u64m8_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {
367 return __riscv_vfwcvt_rtz_xu(mask, src, vl);
368 }
369
370