1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4 // RUN: -target-feature +zvfh -disable-O0-optnone \
5 // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
6 // RUN: FileCheck --check-prefix=CHECK-RV64 %s
7
8 #include <riscv_vector.h>
9
10 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64
11 // CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
12 // CHECK-RV64-NEXT: entry:
13 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], i64 [[VL]])
14 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
15 //
test_vmsne_vv_i8mf8_b64(vint8mf8_t op1,vint8mf8_t op2,size_t vl)16 vbool64_t test_vmsne_vv_i8mf8_b64(vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
17 return __riscv_vmsne_vv_i8mf8_b64(op1, op2, vl);
18 }
19
20 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64
21 // CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
22 // CHECK-RV64-NEXT: entry:
23 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
24 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
25 //
test_vmsne_vx_i8mf8_b64(vint8mf8_t op1,int8_t op2,size_t vl)26 vbool64_t test_vmsne_vx_i8mf8_b64(vint8mf8_t op1, int8_t op2, size_t vl) {
27 return __riscv_vmsne_vx_i8mf8_b64(op1, op2, vl);
28 }
29
30 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32
31 // CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
32 // CHECK-RV64-NEXT: entry:
33 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], i64 [[VL]])
34 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
35 //
test_vmsne_vv_i8mf4_b32(vint8mf4_t op1,vint8mf4_t op2,size_t vl)36 vbool32_t test_vmsne_vv_i8mf4_b32(vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
37 return __riscv_vmsne_vv_i8mf4_b32(op1, op2, vl);
38 }
39
40 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32
41 // CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
42 // CHECK-RV64-NEXT: entry:
43 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
44 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
45 //
test_vmsne_vx_i8mf4_b32(vint8mf4_t op1,int8_t op2,size_t vl)46 vbool32_t test_vmsne_vx_i8mf4_b32(vint8mf4_t op1, int8_t op2, size_t vl) {
47 return __riscv_vmsne_vx_i8mf4_b32(op1, op2, vl);
48 }
49
50 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16
51 // CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
52 // CHECK-RV64-NEXT: entry:
53 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], i64 [[VL]])
54 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
55 //
test_vmsne_vv_i8mf2_b16(vint8mf2_t op1,vint8mf2_t op2,size_t vl)56 vbool16_t test_vmsne_vv_i8mf2_b16(vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
57 return __riscv_vmsne_vv_i8mf2_b16(op1, op2, vl);
58 }
59
60 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16
61 // CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
62 // CHECK-RV64-NEXT: entry:
63 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
64 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
65 //
test_vmsne_vx_i8mf2_b16(vint8mf2_t op1,int8_t op2,size_t vl)66 vbool16_t test_vmsne_vx_i8mf2_b16(vint8mf2_t op1, int8_t op2, size_t vl) {
67 return __riscv_vmsne_vx_i8mf2_b16(op1, op2, vl);
68 }
69
70 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8
71 // CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
72 // CHECK-RV64-NEXT: entry:
73 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], i64 [[VL]])
74 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
75 //
test_vmsne_vv_i8m1_b8(vint8m1_t op1,vint8m1_t op2,size_t vl)76 vbool8_t test_vmsne_vv_i8m1_b8(vint8m1_t op1, vint8m1_t op2, size_t vl) {
77 return __riscv_vmsne_vv_i8m1_b8(op1, op2, vl);
78 }
79
80 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vx_i8m1_b8
81 // CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
82 // CHECK-RV64-NEXT: entry:
83 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
84 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
85 //
test_vmsne_vx_i8m1_b8(vint8m1_t op1,int8_t op2,size_t vl)86 vbool8_t test_vmsne_vx_i8m1_b8(vint8m1_t op1, int8_t op2, size_t vl) {
87 return __riscv_vmsne_vx_i8m1_b8(op1, op2, vl);
88 }
89
90 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vv_i8m2_b4
91 // CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
92 // CHECK-RV64-NEXT: entry:
93 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], i64 [[VL]])
94 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
95 //
test_vmsne_vv_i8m2_b4(vint8m2_t op1,vint8m2_t op2,size_t vl)96 vbool4_t test_vmsne_vv_i8m2_b4(vint8m2_t op1, vint8m2_t op2, size_t vl) {
97 return __riscv_vmsne_vv_i8m2_b4(op1, op2, vl);
98 }
99
100 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vx_i8m2_b4
101 // CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
102 // CHECK-RV64-NEXT: entry:
103 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
104 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
105 //
test_vmsne_vx_i8m2_b4(vint8m2_t op1,int8_t op2,size_t vl)106 vbool4_t test_vmsne_vx_i8m2_b4(vint8m2_t op1, int8_t op2, size_t vl) {
107 return __riscv_vmsne_vx_i8m2_b4(op1, op2, vl);
108 }
109
110 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsne_vv_i8m4_b2
111 // CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
112 // CHECK-RV64-NEXT: entry:
113 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], i64 [[VL]])
114 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
115 //
test_vmsne_vv_i8m4_b2(vint8m4_t op1,vint8m4_t op2,size_t vl)116 vbool2_t test_vmsne_vv_i8m4_b2(vint8m4_t op1, vint8m4_t op2, size_t vl) {
117 return __riscv_vmsne_vv_i8m4_b2(op1, op2, vl);
118 }
119
120 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsne_vx_i8m4_b2
121 // CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
122 // CHECK-RV64-NEXT: entry:
123 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.i8.i64(<vscale x 32 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
124 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
125 //
test_vmsne_vx_i8m4_b2(vint8m4_t op1,int8_t op2,size_t vl)126 vbool2_t test_vmsne_vx_i8m4_b2(vint8m4_t op1, int8_t op2, size_t vl) {
127 return __riscv_vmsne_vx_i8m4_b2(op1, op2, vl);
128 }
129
130 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmsne_vv_i8m8_b1
131 // CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
132 // CHECK-RV64-NEXT: entry:
133 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsne.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], i64 [[VL]])
134 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
135 //
test_vmsne_vv_i8m8_b1(vint8m8_t op1,vint8m8_t op2,size_t vl)136 vbool1_t test_vmsne_vv_i8m8_b1(vint8m8_t op1, vint8m8_t op2, size_t vl) {
137 return __riscv_vmsne_vv_i8m8_b1(op1, op2, vl);
138 }
139
140 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmsne_vx_i8m8_b1
141 // CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
142 // CHECK-RV64-NEXT: entry:
143 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsne.nxv64i8.i8.i64(<vscale x 64 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
144 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
145 //
test_vmsne_vx_i8m8_b1(vint8m8_t op1,int8_t op2,size_t vl)146 vbool1_t test_vmsne_vx_i8m8_b1(vint8m8_t op1, int8_t op2, size_t vl) {
147 return __riscv_vmsne_vx_i8m8_b1(op1, op2, vl);
148 }
149
150 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vv_i16mf4_b64
151 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
152 // CHECK-RV64-NEXT: entry:
153 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], i64 [[VL]])
154 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
155 //
test_vmsne_vv_i16mf4_b64(vint16mf4_t op1,vint16mf4_t op2,size_t vl)156 vbool64_t test_vmsne_vv_i16mf4_b64(vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
157 return __riscv_vmsne_vv_i16mf4_b64(op1, op2, vl);
158 }
159
160 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vx_i16mf4_b64
161 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
162 // CHECK-RV64-NEXT: entry:
163 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16.i16.i64(<vscale x 1 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
164 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
165 //
test_vmsne_vx_i16mf4_b64(vint16mf4_t op1,int16_t op2,size_t vl)166 vbool64_t test_vmsne_vx_i16mf4_b64(vint16mf4_t op1, int16_t op2, size_t vl) {
167 return __riscv_vmsne_vx_i16mf4_b64(op1, op2, vl);
168 }
169
170 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vv_i16mf2_b32
171 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
172 // CHECK-RV64-NEXT: entry:
173 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], i64 [[VL]])
174 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
175 //
test_vmsne_vv_i16mf2_b32(vint16mf2_t op1,vint16mf2_t op2,size_t vl)176 vbool32_t test_vmsne_vv_i16mf2_b32(vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
177 return __riscv_vmsne_vv_i16mf2_b32(op1, op2, vl);
178 }
179
180 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vx_i16mf2_b32
181 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
182 // CHECK-RV64-NEXT: entry:
183 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16.i16.i64(<vscale x 2 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
184 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
185 //
test_vmsne_vx_i16mf2_b32(vint16mf2_t op1,int16_t op2,size_t vl)186 vbool32_t test_vmsne_vx_i16mf2_b32(vint16mf2_t op1, int16_t op2, size_t vl) {
187 return __riscv_vmsne_vx_i16mf2_b32(op1, op2, vl);
188 }
189
190 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vv_i16m1_b16
191 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
192 // CHECK-RV64-NEXT: entry:
193 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], i64 [[VL]])
194 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
195 //
test_vmsne_vv_i16m1_b16(vint16m1_t op1,vint16m1_t op2,size_t vl)196 vbool16_t test_vmsne_vv_i16m1_b16(vint16m1_t op1, vint16m1_t op2, size_t vl) {
197 return __riscv_vmsne_vv_i16m1_b16(op1, op2, vl);
198 }
199
200 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vx_i16m1_b16
201 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
202 // CHECK-RV64-NEXT: entry:
203 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16.i16.i64(<vscale x 4 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
204 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
205 //
test_vmsne_vx_i16m1_b16(vint16m1_t op1,int16_t op2,size_t vl)206 vbool16_t test_vmsne_vx_i16m1_b16(vint16m1_t op1, int16_t op2, size_t vl) {
207 return __riscv_vmsne_vx_i16m1_b16(op1, op2, vl);
208 }
209
210 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vv_i16m2_b8
211 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
212 // CHECK-RV64-NEXT: entry:
213 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], i64 [[VL]])
214 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
215 //
test_vmsne_vv_i16m2_b8(vint16m2_t op1,vint16m2_t op2,size_t vl)216 vbool8_t test_vmsne_vv_i16m2_b8(vint16m2_t op1, vint16m2_t op2, size_t vl) {
217 return __riscv_vmsne_vv_i16m2_b8(op1, op2, vl);
218 }
219
220 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vx_i16m2_b8
221 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
222 // CHECK-RV64-NEXT: entry:
223 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16.i16.i64(<vscale x 8 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
224 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
225 //
test_vmsne_vx_i16m2_b8(vint16m2_t op1,int16_t op2,size_t vl)226 vbool8_t test_vmsne_vx_i16m2_b8(vint16m2_t op1, int16_t op2, size_t vl) {
227 return __riscv_vmsne_vx_i16m2_b8(op1, op2, vl);
228 }
229
230 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vv_i16m4_b4
231 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
232 // CHECK-RV64-NEXT: entry:
233 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], i64 [[VL]])
234 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
235 //
test_vmsne_vv_i16m4_b4(vint16m4_t op1,vint16m4_t op2,size_t vl)236 vbool4_t test_vmsne_vv_i16m4_b4(vint16m4_t op1, vint16m4_t op2, size_t vl) {
237 return __riscv_vmsne_vv_i16m4_b4(op1, op2, vl);
238 }
239
240 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vx_i16m4_b4
241 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
242 // CHECK-RV64-NEXT: entry:
243 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16.i16.i64(<vscale x 16 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
244 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
245 //
test_vmsne_vx_i16m4_b4(vint16m4_t op1,int16_t op2,size_t vl)246 vbool4_t test_vmsne_vx_i16m4_b4(vint16m4_t op1, int16_t op2, size_t vl) {
247 return __riscv_vmsne_vx_i16m4_b4(op1, op2, vl);
248 }
249
250 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsne_vv_i16m8_b2
251 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
252 // CHECK-RV64-NEXT: entry:
253 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], i64 [[VL]])
254 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
255 //
test_vmsne_vv_i16m8_b2(vint16m8_t op1,vint16m8_t op2,size_t vl)256 vbool2_t test_vmsne_vv_i16m8_b2(vint16m8_t op1, vint16m8_t op2, size_t vl) {
257 return __riscv_vmsne_vv_i16m8_b2(op1, op2, vl);
258 }
259
260 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsne_vx_i16m8_b2
261 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
262 // CHECK-RV64-NEXT: entry:
263 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i16.i16.i64(<vscale x 32 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
264 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
265 //
test_vmsne_vx_i16m8_b2(vint16m8_t op1,int16_t op2,size_t vl)266 vbool2_t test_vmsne_vx_i16m8_b2(vint16m8_t op1, int16_t op2, size_t vl) {
267 return __riscv_vmsne_vx_i16m8_b2(op1, op2, vl);
268 }
269
270 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vv_i32mf2_b64
271 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
272 // CHECK-RV64-NEXT: entry:
273 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], i64 [[VL]])
274 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
275 //
test_vmsne_vv_i32mf2_b64(vint32mf2_t op1,vint32mf2_t op2,size_t vl)276 vbool64_t test_vmsne_vv_i32mf2_b64(vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
277 return __riscv_vmsne_vv_i32mf2_b64(op1, op2, vl);
278 }
279
280 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vx_i32mf2_b64
281 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
282 // CHECK-RV64-NEXT: entry:
283 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32.i32.i64(<vscale x 1 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
284 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
285 //
test_vmsne_vx_i32mf2_b64(vint32mf2_t op1,int32_t op2,size_t vl)286 vbool64_t test_vmsne_vx_i32mf2_b64(vint32mf2_t op1, int32_t op2, size_t vl) {
287 return __riscv_vmsne_vx_i32mf2_b64(op1, op2, vl);
288 }
289
290 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vv_i32m1_b32
291 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
292 // CHECK-RV64-NEXT: entry:
293 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], i64 [[VL]])
294 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
295 //
test_vmsne_vv_i32m1_b32(vint32m1_t op1,vint32m1_t op2,size_t vl)296 vbool32_t test_vmsne_vv_i32m1_b32(vint32m1_t op1, vint32m1_t op2, size_t vl) {
297 return __riscv_vmsne_vv_i32m1_b32(op1, op2, vl);
298 }
299
300 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vx_i32m1_b32
301 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
302 // CHECK-RV64-NEXT: entry:
303 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32.i32.i64(<vscale x 2 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
304 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
305 //
test_vmsne_vx_i32m1_b32(vint32m1_t op1,int32_t op2,size_t vl)306 vbool32_t test_vmsne_vx_i32m1_b32(vint32m1_t op1, int32_t op2, size_t vl) {
307 return __riscv_vmsne_vx_i32m1_b32(op1, op2, vl);
308 }
309
310 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vv_i32m2_b16
311 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
312 // CHECK-RV64-NEXT: entry:
313 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], i64 [[VL]])
314 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
315 //
test_vmsne_vv_i32m2_b16(vint32m2_t op1,vint32m2_t op2,size_t vl)316 vbool16_t test_vmsne_vv_i32m2_b16(vint32m2_t op1, vint32m2_t op2, size_t vl) {
317 return __riscv_vmsne_vv_i32m2_b16(op1, op2, vl);
318 }
319
320 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vx_i32m2_b16
321 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
322 // CHECK-RV64-NEXT: entry:
323 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32.i32.i64(<vscale x 4 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
324 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
325 //
test_vmsne_vx_i32m2_b16(vint32m2_t op1,int32_t op2,size_t vl)326 vbool16_t test_vmsne_vx_i32m2_b16(vint32m2_t op1, int32_t op2, size_t vl) {
327 return __riscv_vmsne_vx_i32m2_b16(op1, op2, vl);
328 }
329
330 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vv_i32m4_b8
331 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
332 // CHECK-RV64-NEXT: entry:
333 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], i64 [[VL]])
334 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
335 //
test_vmsne_vv_i32m4_b8(vint32m4_t op1,vint32m4_t op2,size_t vl)336 vbool8_t test_vmsne_vv_i32m4_b8(vint32m4_t op1, vint32m4_t op2, size_t vl) {
337 return __riscv_vmsne_vv_i32m4_b8(op1, op2, vl);
338 }
339
340 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vx_i32m4_b8
341 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
342 // CHECK-RV64-NEXT: entry:
343 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32.i32.i64(<vscale x 8 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
344 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
345 //
test_vmsne_vx_i32m4_b8(vint32m4_t op1,int32_t op2,size_t vl)346 vbool8_t test_vmsne_vx_i32m4_b8(vint32m4_t op1, int32_t op2, size_t vl) {
347 return __riscv_vmsne_vx_i32m4_b8(op1, op2, vl);
348 }
349
350 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vv_i32m8_b4
351 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
352 // CHECK-RV64-NEXT: entry:
353 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], i64 [[VL]])
354 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
355 //
test_vmsne_vv_i32m8_b4(vint32m8_t op1,vint32m8_t op2,size_t vl)356 vbool4_t test_vmsne_vv_i32m8_b4(vint32m8_t op1, vint32m8_t op2, size_t vl) {
357 return __riscv_vmsne_vv_i32m8_b4(op1, op2, vl);
358 }
359
360 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vx_i32m8_b4
361 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
362 // CHECK-RV64-NEXT: entry:
363 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i32.i32.i64(<vscale x 16 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
364 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
365 //
test_vmsne_vx_i32m8_b4(vint32m8_t op1,int32_t op2,size_t vl)366 vbool4_t test_vmsne_vx_i32m8_b4(vint32m8_t op1, int32_t op2, size_t vl) {
367 return __riscv_vmsne_vx_i32m8_b4(op1, op2, vl);
368 }
369
370 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vv_i64m1_b64
371 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
372 // CHECK-RV64-NEXT: entry:
373 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], i64 [[VL]])
374 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
375 //
test_vmsne_vv_i64m1_b64(vint64m1_t op1,vint64m1_t op2,size_t vl)376 vbool64_t test_vmsne_vv_i64m1_b64(vint64m1_t op1, vint64m1_t op2, size_t vl) {
377 return __riscv_vmsne_vv_i64m1_b64(op1, op2, vl);
378 }
379
380 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vx_i64m1_b64
381 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
382 // CHECK-RV64-NEXT: entry:
383 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64.i64.i64(<vscale x 1 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
384 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
385 //
test_vmsne_vx_i64m1_b64(vint64m1_t op1,int64_t op2,size_t vl)386 vbool64_t test_vmsne_vx_i64m1_b64(vint64m1_t op1, int64_t op2, size_t vl) {
387 return __riscv_vmsne_vx_i64m1_b64(op1, op2, vl);
388 }
389
390 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vv_i64m2_b32
391 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
392 // CHECK-RV64-NEXT: entry:
393 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], i64 [[VL]])
394 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
395 //
test_vmsne_vv_i64m2_b32(vint64m2_t op1,vint64m2_t op2,size_t vl)396 vbool32_t test_vmsne_vv_i64m2_b32(vint64m2_t op1, vint64m2_t op2, size_t vl) {
397 return __riscv_vmsne_vv_i64m2_b32(op1, op2, vl);
398 }
399
400 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vx_i64m2_b32
401 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
402 // CHECK-RV64-NEXT: entry:
403 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64.i64.i64(<vscale x 2 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
404 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
405 //
test_vmsne_vx_i64m2_b32(vint64m2_t op1,int64_t op2,size_t vl)406 vbool32_t test_vmsne_vx_i64m2_b32(vint64m2_t op1, int64_t op2, size_t vl) {
407 return __riscv_vmsne_vx_i64m2_b32(op1, op2, vl);
408 }
409
410 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vv_i64m4_b16
411 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
412 // CHECK-RV64-NEXT: entry:
413 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], i64 [[VL]])
414 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
415 //
test_vmsne_vv_i64m4_b16(vint64m4_t op1,vint64m4_t op2,size_t vl)416 vbool16_t test_vmsne_vv_i64m4_b16(vint64m4_t op1, vint64m4_t op2, size_t vl) {
417 return __riscv_vmsne_vv_i64m4_b16(op1, op2, vl);
418 }
419
420 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vx_i64m4_b16
421 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
422 // CHECK-RV64-NEXT: entry:
423 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64.i64.i64(<vscale x 4 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
424 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
425 //
test_vmsne_vx_i64m4_b16(vint64m4_t op1,int64_t op2,size_t vl)426 vbool16_t test_vmsne_vx_i64m4_b16(vint64m4_t op1, int64_t op2, size_t vl) {
427 return __riscv_vmsne_vx_i64m4_b16(op1, op2, vl);
428 }
429
430 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vv_i64m8_b8
431 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
432 // CHECK-RV64-NEXT: entry:
433 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], i64 [[VL]])
434 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
435 //
test_vmsne_vv_i64m8_b8(vint64m8_t op1,vint64m8_t op2,size_t vl)436 vbool8_t test_vmsne_vv_i64m8_b8(vint64m8_t op1, vint64m8_t op2, size_t vl) {
437 return __riscv_vmsne_vv_i64m8_b8(op1, op2, vl);
438 }
439
440 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vx_i64m8_b8
441 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
442 // CHECK-RV64-NEXT: entry:
443 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i64.i64.i64(<vscale x 8 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
444 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
445 //
test_vmsne_vx_i64m8_b8(vint64m8_t op1,int64_t op2,size_t vl)446 vbool8_t test_vmsne_vx_i64m8_b8(vint64m8_t op1, int64_t op2, size_t vl) {
447 return __riscv_vmsne_vx_i64m8_b8(op1, op2, vl);
448 }
449
450 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vv_u8mf8_b64
451 // CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
452 // CHECK-RV64-NEXT: entry:
453 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], i64 [[VL]])
454 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
455 //
test_vmsne_vv_u8mf8_b64(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)456 vbool64_t test_vmsne_vv_u8mf8_b64(vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
457 return __riscv_vmsne_vv_u8mf8_b64(op1, op2, vl);
458 }
459
460 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vx_u8mf8_b64
461 // CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
462 // CHECK-RV64-NEXT: entry:
463 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
464 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
465 //
test_vmsne_vx_u8mf8_b64(vuint8mf8_t op1,uint8_t op2,size_t vl)466 vbool64_t test_vmsne_vx_u8mf8_b64(vuint8mf8_t op1, uint8_t op2, size_t vl) {
467 return __riscv_vmsne_vx_u8mf8_b64(op1, op2, vl);
468 }
469
470 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vv_u8mf4_b32
471 // CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
472 // CHECK-RV64-NEXT: entry:
473 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], i64 [[VL]])
474 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
475 //
test_vmsne_vv_u8mf4_b32(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)476 vbool32_t test_vmsne_vv_u8mf4_b32(vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
477 return __riscv_vmsne_vv_u8mf4_b32(op1, op2, vl);
478 }
479
480 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vx_u8mf4_b32
481 // CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
482 // CHECK-RV64-NEXT: entry:
483 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
484 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
485 //
test_vmsne_vx_u8mf4_b32(vuint8mf4_t op1,uint8_t op2,size_t vl)486 vbool32_t test_vmsne_vx_u8mf4_b32(vuint8mf4_t op1, uint8_t op2, size_t vl) {
487 return __riscv_vmsne_vx_u8mf4_b32(op1, op2, vl);
488 }
489
490 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vv_u8mf2_b16
491 // CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
492 // CHECK-RV64-NEXT: entry:
493 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], i64 [[VL]])
494 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
495 //
test_vmsne_vv_u8mf2_b16(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)496 vbool16_t test_vmsne_vv_u8mf2_b16(vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
497 return __riscv_vmsne_vv_u8mf2_b16(op1, op2, vl);
498 }
499
500 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vx_u8mf2_b16
501 // CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
502 // CHECK-RV64-NEXT: entry:
503 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
504 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
505 //
test_vmsne_vx_u8mf2_b16(vuint8mf2_t op1,uint8_t op2,size_t vl)506 vbool16_t test_vmsne_vx_u8mf2_b16(vuint8mf2_t op1, uint8_t op2, size_t vl) {
507 return __riscv_vmsne_vx_u8mf2_b16(op1, op2, vl);
508 }
509
510 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vv_u8m1_b8
511 // CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
512 // CHECK-RV64-NEXT: entry:
513 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], i64 [[VL]])
514 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
515 //
test_vmsne_vv_u8m1_b8(vuint8m1_t op1,vuint8m1_t op2,size_t vl)516 vbool8_t test_vmsne_vv_u8m1_b8(vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
517 return __riscv_vmsne_vv_u8m1_b8(op1, op2, vl);
518 }
519
520 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vx_u8m1_b8
521 // CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
522 // CHECK-RV64-NEXT: entry:
523 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
524 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
525 //
test_vmsne_vx_u8m1_b8(vuint8m1_t op1,uint8_t op2,size_t vl)526 vbool8_t test_vmsne_vx_u8m1_b8(vuint8m1_t op1, uint8_t op2, size_t vl) {
527 return __riscv_vmsne_vx_u8m1_b8(op1, op2, vl);
528 }
529
530 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vv_u8m2_b4
531 // CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
532 // CHECK-RV64-NEXT: entry:
533 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], i64 [[VL]])
534 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
535 //
test_vmsne_vv_u8m2_b4(vuint8m2_t op1,vuint8m2_t op2,size_t vl)536 vbool4_t test_vmsne_vv_u8m2_b4(vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
537 return __riscv_vmsne_vv_u8m2_b4(op1, op2, vl);
538 }
539
540 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vx_u8m2_b4
541 // CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
542 // CHECK-RV64-NEXT: entry:
543 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
544 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
545 //
test_vmsne_vx_u8m2_b4(vuint8m2_t op1,uint8_t op2,size_t vl)546 vbool4_t test_vmsne_vx_u8m2_b4(vuint8m2_t op1, uint8_t op2, size_t vl) {
547 return __riscv_vmsne_vx_u8m2_b4(op1, op2, vl);
548 }
549
550 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsne_vv_u8m4_b2
551 // CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
552 // CHECK-RV64-NEXT: entry:
553 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], i64 [[VL]])
554 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
555 //
test_vmsne_vv_u8m4_b2(vuint8m4_t op1,vuint8m4_t op2,size_t vl)556 vbool2_t test_vmsne_vv_u8m4_b2(vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
557 return __riscv_vmsne_vv_u8m4_b2(op1, op2, vl);
558 }
559
560 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsne_vx_u8m4_b2
561 // CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
562 // CHECK-RV64-NEXT: entry:
563 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.i8.i64(<vscale x 32 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
564 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
565 //
test_vmsne_vx_u8m4_b2(vuint8m4_t op1,uint8_t op2,size_t vl)566 vbool2_t test_vmsne_vx_u8m4_b2(vuint8m4_t op1, uint8_t op2, size_t vl) {
567 return __riscv_vmsne_vx_u8m4_b2(op1, op2, vl);
568 }
569
570 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmsne_vv_u8m8_b1
571 // CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
572 // CHECK-RV64-NEXT: entry:
573 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsne.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], i64 [[VL]])
574 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
575 //
test_vmsne_vv_u8m8_b1(vuint8m8_t op1,vuint8m8_t op2,size_t vl)576 vbool1_t test_vmsne_vv_u8m8_b1(vuint8m8_t op1, vuint8m8_t op2, size_t vl) {
577 return __riscv_vmsne_vv_u8m8_b1(op1, op2, vl);
578 }
579
580 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmsne_vx_u8m8_b1
581 // CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
582 // CHECK-RV64-NEXT: entry:
583 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsne.nxv64i8.i8.i64(<vscale x 64 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
584 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
585 //
test_vmsne_vx_u8m8_b1(vuint8m8_t op1,uint8_t op2,size_t vl)586 vbool1_t test_vmsne_vx_u8m8_b1(vuint8m8_t op1, uint8_t op2, size_t vl) {
587 return __riscv_vmsne_vx_u8m8_b1(op1, op2, vl);
588 }
589
590 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vv_u16mf4_b64
591 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
592 // CHECK-RV64-NEXT: entry:
593 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], i64 [[VL]])
594 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
595 //
test_vmsne_vv_u16mf4_b64(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)596 vbool64_t test_vmsne_vv_u16mf4_b64(vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
597 return __riscv_vmsne_vv_u16mf4_b64(op1, op2, vl);
598 }
599
600 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vx_u16mf4_b64
601 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
602 // CHECK-RV64-NEXT: entry:
603 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16.i16.i64(<vscale x 1 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
604 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
605 //
test_vmsne_vx_u16mf4_b64(vuint16mf4_t op1,uint16_t op2,size_t vl)606 vbool64_t test_vmsne_vx_u16mf4_b64(vuint16mf4_t op1, uint16_t op2, size_t vl) {
607 return __riscv_vmsne_vx_u16mf4_b64(op1, op2, vl);
608 }
609
610 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vv_u16mf2_b32
611 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
612 // CHECK-RV64-NEXT: entry:
613 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], i64 [[VL]])
614 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
615 //
test_vmsne_vv_u16mf2_b32(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)616 vbool32_t test_vmsne_vv_u16mf2_b32(vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
617 return __riscv_vmsne_vv_u16mf2_b32(op1, op2, vl);
618 }
619
620 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vx_u16mf2_b32
621 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
622 // CHECK-RV64-NEXT: entry:
623 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16.i16.i64(<vscale x 2 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
624 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
625 //
test_vmsne_vx_u16mf2_b32(vuint16mf2_t op1,uint16_t op2,size_t vl)626 vbool32_t test_vmsne_vx_u16mf2_b32(vuint16mf2_t op1, uint16_t op2, size_t vl) {
627 return __riscv_vmsne_vx_u16mf2_b32(op1, op2, vl);
628 }
629
630 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vv_u16m1_b16
631 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
632 // CHECK-RV64-NEXT: entry:
633 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], i64 [[VL]])
634 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
635 //
test_vmsne_vv_u16m1_b16(vuint16m1_t op1,vuint16m1_t op2,size_t vl)636 vbool16_t test_vmsne_vv_u16m1_b16(vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
637 return __riscv_vmsne_vv_u16m1_b16(op1, op2, vl);
638 }
639
640 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vx_u16m1_b16
641 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
642 // CHECK-RV64-NEXT: entry:
643 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16.i16.i64(<vscale x 4 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
644 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
645 //
test_vmsne_vx_u16m1_b16(vuint16m1_t op1,uint16_t op2,size_t vl)646 vbool16_t test_vmsne_vx_u16m1_b16(vuint16m1_t op1, uint16_t op2, size_t vl) {
647 return __riscv_vmsne_vx_u16m1_b16(op1, op2, vl);
648 }
649
650 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vv_u16m2_b8
651 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
652 // CHECK-RV64-NEXT: entry:
653 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], i64 [[VL]])
654 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
655 //
test_vmsne_vv_u16m2_b8(vuint16m2_t op1,vuint16m2_t op2,size_t vl)656 vbool8_t test_vmsne_vv_u16m2_b8(vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
657 return __riscv_vmsne_vv_u16m2_b8(op1, op2, vl);
658 }
659
660 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vx_u16m2_b8
661 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
662 // CHECK-RV64-NEXT: entry:
663 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16.i16.i64(<vscale x 8 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
664 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
665 //
test_vmsne_vx_u16m2_b8(vuint16m2_t op1,uint16_t op2,size_t vl)666 vbool8_t test_vmsne_vx_u16m2_b8(vuint16m2_t op1, uint16_t op2, size_t vl) {
667 return __riscv_vmsne_vx_u16m2_b8(op1, op2, vl);
668 }
669
670 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vv_u16m4_b4
671 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
672 // CHECK-RV64-NEXT: entry:
673 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], i64 [[VL]])
674 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
675 //
test_vmsne_vv_u16m4_b4(vuint16m4_t op1,vuint16m4_t op2,size_t vl)676 vbool4_t test_vmsne_vv_u16m4_b4(vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
677 return __riscv_vmsne_vv_u16m4_b4(op1, op2, vl);
678 }
679
680 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vx_u16m4_b4
681 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
682 // CHECK-RV64-NEXT: entry:
683 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16.i16.i64(<vscale x 16 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
684 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
685 //
test_vmsne_vx_u16m4_b4(vuint16m4_t op1,uint16_t op2,size_t vl)686 vbool4_t test_vmsne_vx_u16m4_b4(vuint16m4_t op1, uint16_t op2, size_t vl) {
687 return __riscv_vmsne_vx_u16m4_b4(op1, op2, vl);
688 }
689
690 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsne_vv_u16m8_b2
691 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
692 // CHECK-RV64-NEXT: entry:
693 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], i64 [[VL]])
694 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
695 //
test_vmsne_vv_u16m8_b2(vuint16m8_t op1,vuint16m8_t op2,size_t vl)696 vbool2_t test_vmsne_vv_u16m8_b2(vuint16m8_t op1, vuint16m8_t op2, size_t vl) {
697 return __riscv_vmsne_vv_u16m8_b2(op1, op2, vl);
698 }
699
700 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsne_vx_u16m8_b2
701 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
702 // CHECK-RV64-NEXT: entry:
703 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i16.i16.i64(<vscale x 32 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
704 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
705 //
test_vmsne_vx_u16m8_b2(vuint16m8_t op1,uint16_t op2,size_t vl)706 vbool2_t test_vmsne_vx_u16m8_b2(vuint16m8_t op1, uint16_t op2, size_t vl) {
707 return __riscv_vmsne_vx_u16m8_b2(op1, op2, vl);
708 }
709
710 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vv_u32mf2_b64
711 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
712 // CHECK-RV64-NEXT: entry:
713 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], i64 [[VL]])
714 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
715 //
test_vmsne_vv_u32mf2_b64(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)716 vbool64_t test_vmsne_vv_u32mf2_b64(vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
717 return __riscv_vmsne_vv_u32mf2_b64(op1, op2, vl);
718 }
719
720 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vx_u32mf2_b64
721 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
722 // CHECK-RV64-NEXT: entry:
723 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32.i32.i64(<vscale x 1 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
724 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
725 //
test_vmsne_vx_u32mf2_b64(vuint32mf2_t op1,uint32_t op2,size_t vl)726 vbool64_t test_vmsne_vx_u32mf2_b64(vuint32mf2_t op1, uint32_t op2, size_t vl) {
727 return __riscv_vmsne_vx_u32mf2_b64(op1, op2, vl);
728 }
729
730 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vv_u32m1_b32
731 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
732 // CHECK-RV64-NEXT: entry:
733 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], i64 [[VL]])
734 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
735 //
test_vmsne_vv_u32m1_b32(vuint32m1_t op1,vuint32m1_t op2,size_t vl)736 vbool32_t test_vmsne_vv_u32m1_b32(vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
737 return __riscv_vmsne_vv_u32m1_b32(op1, op2, vl);
738 }
739
740 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vx_u32m1_b32
741 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
742 // CHECK-RV64-NEXT: entry:
743 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32.i32.i64(<vscale x 2 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
744 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
745 //
test_vmsne_vx_u32m1_b32(vuint32m1_t op1,uint32_t op2,size_t vl)746 vbool32_t test_vmsne_vx_u32m1_b32(vuint32m1_t op1, uint32_t op2, size_t vl) {
747 return __riscv_vmsne_vx_u32m1_b32(op1, op2, vl);
748 }
749
750 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vv_u32m2_b16
751 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
752 // CHECK-RV64-NEXT: entry:
753 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], i64 [[VL]])
754 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
755 //
test_vmsne_vv_u32m2_b16(vuint32m2_t op1,vuint32m2_t op2,size_t vl)756 vbool16_t test_vmsne_vv_u32m2_b16(vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
757 return __riscv_vmsne_vv_u32m2_b16(op1, op2, vl);
758 }
759
760 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vx_u32m2_b16
761 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
762 // CHECK-RV64-NEXT: entry:
763 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32.i32.i64(<vscale x 4 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
764 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
765 //
test_vmsne_vx_u32m2_b16(vuint32m2_t op1,uint32_t op2,size_t vl)766 vbool16_t test_vmsne_vx_u32m2_b16(vuint32m2_t op1, uint32_t op2, size_t vl) {
767 return __riscv_vmsne_vx_u32m2_b16(op1, op2, vl);
768 }
769
770 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vv_u32m4_b8
771 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
772 // CHECK-RV64-NEXT: entry:
773 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], i64 [[VL]])
774 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
775 //
test_vmsne_vv_u32m4_b8(vuint32m4_t op1,vuint32m4_t op2,size_t vl)776 vbool8_t test_vmsne_vv_u32m4_b8(vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
777 return __riscv_vmsne_vv_u32m4_b8(op1, op2, vl);
778 }
779
780 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vx_u32m4_b8
781 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
782 // CHECK-RV64-NEXT: entry:
783 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32.i32.i64(<vscale x 8 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
784 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
785 //
test_vmsne_vx_u32m4_b8(vuint32m4_t op1,uint32_t op2,size_t vl)786 vbool8_t test_vmsne_vx_u32m4_b8(vuint32m4_t op1, uint32_t op2, size_t vl) {
787 return __riscv_vmsne_vx_u32m4_b8(op1, op2, vl);
788 }
789
790 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vv_u32m8_b4
791 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
792 // CHECK-RV64-NEXT: entry:
793 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], i64 [[VL]])
794 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
795 //
test_vmsne_vv_u32m8_b4(vuint32m8_t op1,vuint32m8_t op2,size_t vl)796 vbool4_t test_vmsne_vv_u32m8_b4(vuint32m8_t op1, vuint32m8_t op2, size_t vl) {
797 return __riscv_vmsne_vv_u32m8_b4(op1, op2, vl);
798 }
799
800 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vx_u32m8_b4
801 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
802 // CHECK-RV64-NEXT: entry:
803 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i32.i32.i64(<vscale x 16 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
804 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
805 //
test_vmsne_vx_u32m8_b4(vuint32m8_t op1,uint32_t op2,size_t vl)806 vbool4_t test_vmsne_vx_u32m8_b4(vuint32m8_t op1, uint32_t op2, size_t vl) {
807 return __riscv_vmsne_vx_u32m8_b4(op1, op2, vl);
808 }
809
810 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vv_u64m1_b64
811 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
812 // CHECK-RV64-NEXT: entry:
813 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], i64 [[VL]])
814 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
815 //
test_vmsne_vv_u64m1_b64(vuint64m1_t op1,vuint64m1_t op2,size_t vl)816 vbool64_t test_vmsne_vv_u64m1_b64(vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
817 return __riscv_vmsne_vv_u64m1_b64(op1, op2, vl);
818 }
819
820 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vx_u64m1_b64
821 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
822 // CHECK-RV64-NEXT: entry:
823 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64.i64.i64(<vscale x 1 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
824 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
825 //
test_vmsne_vx_u64m1_b64(vuint64m1_t op1,uint64_t op2,size_t vl)826 vbool64_t test_vmsne_vx_u64m1_b64(vuint64m1_t op1, uint64_t op2, size_t vl) {
827 return __riscv_vmsne_vx_u64m1_b64(op1, op2, vl);
828 }
829
830 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vv_u64m2_b32
831 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
832 // CHECK-RV64-NEXT: entry:
833 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], i64 [[VL]])
834 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
835 //
test_vmsne_vv_u64m2_b32(vuint64m2_t op1,vuint64m2_t op2,size_t vl)836 vbool32_t test_vmsne_vv_u64m2_b32(vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
837 return __riscv_vmsne_vv_u64m2_b32(op1, op2, vl);
838 }
839
840 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vx_u64m2_b32
841 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
842 // CHECK-RV64-NEXT: entry:
843 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64.i64.i64(<vscale x 2 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
844 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
845 //
test_vmsne_vx_u64m2_b32(vuint64m2_t op1,uint64_t op2,size_t vl)846 vbool32_t test_vmsne_vx_u64m2_b32(vuint64m2_t op1, uint64_t op2, size_t vl) {
847 return __riscv_vmsne_vx_u64m2_b32(op1, op2, vl);
848 }
849
850 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vv_u64m4_b16
851 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
852 // CHECK-RV64-NEXT: entry:
853 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], i64 [[VL]])
854 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
855 //
test_vmsne_vv_u64m4_b16(vuint64m4_t op1,vuint64m4_t op2,size_t vl)856 vbool16_t test_vmsne_vv_u64m4_b16(vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
857 return __riscv_vmsne_vv_u64m4_b16(op1, op2, vl);
858 }
859
860 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vx_u64m4_b16
861 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
862 // CHECK-RV64-NEXT: entry:
863 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64.i64.i64(<vscale x 4 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
864 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
865 //
test_vmsne_vx_u64m4_b16(vuint64m4_t op1,uint64_t op2,size_t vl)866 vbool16_t test_vmsne_vx_u64m4_b16(vuint64m4_t op1, uint64_t op2, size_t vl) {
867 return __riscv_vmsne_vx_u64m4_b16(op1, op2, vl);
868 }
869
870 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vv_u64m8_b8
871 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
872 // CHECK-RV64-NEXT: entry:
873 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], i64 [[VL]])
874 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
875 //
test_vmsne_vv_u64m8_b8(vuint64m8_t op1,vuint64m8_t op2,size_t vl)876 vbool8_t test_vmsne_vv_u64m8_b8(vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
877 return __riscv_vmsne_vv_u64m8_b8(op1, op2, vl);
878 }
879
880 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vx_u64m8_b8
881 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
882 // CHECK-RV64-NEXT: entry:
883 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i64.i64.i64(<vscale x 8 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
884 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
885 //
test_vmsne_vx_u64m8_b8(vuint64m8_t op1,uint64_t op2,size_t vl)886 vbool8_t test_vmsne_vx_u64m8_b8(vuint64m8_t op1, uint64_t op2, size_t vl) {
887 return __riscv_vmsne_vx_u64m8_b8(op1, op2, vl);
888 }
889
890 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64_m
891 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
892 // CHECK-RV64-NEXT: entry:
893 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> poison, <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
894 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
895 //
test_vmsne_vv_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)896 vbool64_t test_vmsne_vv_i8mf8_b64_m(vbool64_t mask, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
897 return __riscv_vmsne_vv_i8mf8_b64_m(mask, op1, op2, vl);
898 }
899
900 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64_m
901 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
902 // CHECK-RV64-NEXT: entry:
903 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1> poison, <vscale x 1 x i8> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
904 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
905 //
test_vmsne_vx_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)906 vbool64_t test_vmsne_vx_i8mf8_b64_m(vbool64_t mask, vint8mf8_t op1, int8_t op2, size_t vl) {
907 return __riscv_vmsne_vx_i8mf8_b64_m(mask, op1, op2, vl);
908 }
909
910 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32_m
911 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
912 // CHECK-RV64-NEXT: entry:
913 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> poison, <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
914 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
915 //
test_vmsne_vv_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)916 vbool32_t test_vmsne_vv_i8mf4_b32_m(vbool32_t mask, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
917 return __riscv_vmsne_vv_i8mf4_b32_m(mask, op1, op2, vl);
918 }
919
920 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32_m
921 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
922 // CHECK-RV64-NEXT: entry:
923 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1> poison, <vscale x 2 x i8> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
924 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
925 //
test_vmsne_vx_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)926 vbool32_t test_vmsne_vx_i8mf4_b32_m(vbool32_t mask, vint8mf4_t op1, int8_t op2, size_t vl) {
927 return __riscv_vmsne_vx_i8mf4_b32_m(mask, op1, op2, vl);
928 }
929
930 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16_m
931 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
932 // CHECK-RV64-NEXT: entry:
933 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> poison, <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
934 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
935 //
test_vmsne_vv_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)936 vbool16_t test_vmsne_vv_i8mf2_b16_m(vbool16_t mask, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
937 return __riscv_vmsne_vv_i8mf2_b16_m(mask, op1, op2, vl);
938 }
939
940 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16_m
941 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
942 // CHECK-RV64-NEXT: entry:
943 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1> poison, <vscale x 4 x i8> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
944 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
945 //
test_vmsne_vx_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)946 vbool16_t test_vmsne_vx_i8mf2_b16_m(vbool16_t mask, vint8mf2_t op1, int8_t op2, size_t vl) {
947 return __riscv_vmsne_vx_i8mf2_b16_m(mask, op1, op2, vl);
948 }
949
950 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8_m
951 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
952 // CHECK-RV64-NEXT: entry:
953 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> poison, <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
954 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
955 //
test_vmsne_vv_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)956 vbool8_t test_vmsne_vv_i8m1_b8_m(vbool8_t mask, vint8m1_t op1, vint8m1_t op2, size_t vl) {
957 return __riscv_vmsne_vv_i8m1_b8_m(mask, op1, op2, vl);
958 }
959
960 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vx_i8m1_b8_m
961 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
962 // CHECK-RV64-NEXT: entry:
963 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8.i64(<vscale x 8 x i1> poison, <vscale x 8 x i8> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
964 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
965 //
test_vmsne_vx_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)966 vbool8_t test_vmsne_vx_i8m1_b8_m(vbool8_t mask, vint8m1_t op1, int8_t op2, size_t vl) {
967 return __riscv_vmsne_vx_i8m1_b8_m(mask, op1, op2, vl);
968 }
969
970 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vv_i8m2_b4_m
971 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
972 // CHECK-RV64-NEXT: entry:
973 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i1> poison, <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
974 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
975 //
test_vmsne_vv_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)976 vbool4_t test_vmsne_vv_i8m2_b4_m(vbool4_t mask, vint8m2_t op1, vint8m2_t op2, size_t vl) {
977 return __riscv_vmsne_vv_i8m2_b4_m(mask, op1, op2, vl);
978 }
979
980 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vx_i8m2_b4_m
981 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
982 // CHECK-RV64-NEXT: entry:
983 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8.i64(<vscale x 16 x i1> poison, <vscale x 16 x i8> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
984 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
985 //
test_vmsne_vx_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)986 vbool4_t test_vmsne_vx_i8m2_b4_m(vbool4_t mask, vint8m2_t op1, int8_t op2, size_t vl) {
987 return __riscv_vmsne_vx_i8m2_b4_m(mask, op1, op2, vl);
988 }
989
990 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsne_vv_i8m4_b2_m
991 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
992 // CHECK-RV64-NEXT: entry:
993 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i1> poison, <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
994 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
995 //
test_vmsne_vv_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)996 vbool2_t test_vmsne_vv_i8m4_b2_m(vbool2_t mask, vint8m4_t op1, vint8m4_t op2, size_t vl) {
997 return __riscv_vmsne_vv_i8m4_b2_m(mask, op1, op2, vl);
998 }
999
1000 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsne_vx_i8m4_b2_m
1001 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1002 // CHECK-RV64-NEXT: entry:
1003 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8.i64(<vscale x 32 x i1> poison, <vscale x 32 x i8> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
1004 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
1005 //
test_vmsne_vx_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)1006 vbool2_t test_vmsne_vx_i8m4_b2_m(vbool2_t mask, vint8m4_t op1, int8_t op2, size_t vl) {
1007 return __riscv_vmsne_vx_i8m4_b2_m(mask, op1, op2, vl);
1008 }
1009
1010 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmsne_vv_i8m8_b1_m
1011 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1012 // CHECK-RV64-NEXT: entry:
1013 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsne.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i1> poison, <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]])
1014 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
1015 //
test_vmsne_vv_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)1016 vbool1_t test_vmsne_vv_i8m8_b1_m(vbool1_t mask, vint8m8_t op1, vint8m8_t op2, size_t vl) {
1017 return __riscv_vmsne_vv_i8m8_b1_m(mask, op1, op2, vl);
1018 }
1019
1020 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmsne_vx_i8m8_b1_m
1021 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1022 // CHECK-RV64-NEXT: entry:
1023 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsne.mask.nxv64i8.i8.i64(<vscale x 64 x i1> poison, <vscale x 64 x i8> [[OP1]], i8 [[OP2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]])
1024 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
1025 //
test_vmsne_vx_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)1026 vbool1_t test_vmsne_vx_i8m8_b1_m(vbool1_t mask, vint8m8_t op1, int8_t op2, size_t vl) {
1027 return __riscv_vmsne_vx_i8m8_b1_m(mask, op1, op2, vl);
1028 }
1029
1030 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vv_i16mf4_b64_m
1031 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1032 // CHECK-RV64-NEXT: entry:
1033 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i1> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
1034 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1035 //
test_vmsne_vv_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)1036 vbool64_t test_vmsne_vv_i16mf4_b64_m(vbool64_t mask, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
1037 return __riscv_vmsne_vv_i16mf4_b64_m(mask, op1, op2, vl);
1038 }
1039
1040 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vx_i16mf4_b64_m
1041 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1042 // CHECK-RV64-NEXT: entry:
1043 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16.i64(<vscale x 1 x i1> poison, <vscale x 1 x i16> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
1044 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1045 //
test_vmsne_vx_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)1046 vbool64_t test_vmsne_vx_i16mf4_b64_m(vbool64_t mask, vint16mf4_t op1, int16_t op2, size_t vl) {
1047 return __riscv_vmsne_vx_i16mf4_b64_m(mask, op1, op2, vl);
1048 }
1049
1050 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vv_i16mf2_b32_m
1051 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1052 // CHECK-RV64-NEXT: entry:
1053 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i1> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
1054 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1055 //
test_vmsne_vv_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)1056 vbool32_t test_vmsne_vv_i16mf2_b32_m(vbool32_t mask, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
1057 return __riscv_vmsne_vv_i16mf2_b32_m(mask, op1, op2, vl);
1058 }
1059
1060 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vx_i16mf2_b32_m
1061 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1062 // CHECK-RV64-NEXT: entry:
1063 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16.i64(<vscale x 2 x i1> poison, <vscale x 2 x i16> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
1064 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1065 //
test_vmsne_vx_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)1066 vbool32_t test_vmsne_vx_i16mf2_b32_m(vbool32_t mask, vint16mf2_t op1, int16_t op2, size_t vl) {
1067 return __riscv_vmsne_vx_i16mf2_b32_m(mask, op1, op2, vl);
1068 }
1069
1070 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vv_i16m1_b16_m
1071 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1072 // CHECK-RV64-NEXT: entry:
1073 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i1> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
1074 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1075 //
test_vmsne_vv_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)1076 vbool16_t test_vmsne_vv_i16m1_b16_m(vbool16_t mask, vint16m1_t op1, vint16m1_t op2, size_t vl) {
1077 return __riscv_vmsne_vv_i16m1_b16_m(mask, op1, op2, vl);
1078 }
1079
1080 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vx_i16m1_b16_m
1081 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1082 // CHECK-RV64-NEXT: entry:
1083 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16.i64(<vscale x 4 x i1> poison, <vscale x 4 x i16> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
1084 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1085 //
test_vmsne_vx_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)1086 vbool16_t test_vmsne_vx_i16m1_b16_m(vbool16_t mask, vint16m1_t op1, int16_t op2, size_t vl) {
1087 return __riscv_vmsne_vx_i16m1_b16_m(mask, op1, op2, vl);
1088 }
1089
1090 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vv_i16m2_b8_m
1091 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1092 // CHECK-RV64-NEXT: entry:
1093 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i1> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
1094 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1095 //
test_vmsne_vv_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)1096 vbool8_t test_vmsne_vv_i16m2_b8_m(vbool8_t mask, vint16m2_t op1, vint16m2_t op2, size_t vl) {
1097 return __riscv_vmsne_vv_i16m2_b8_m(mask, op1, op2, vl);
1098 }
1099
1100 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vx_i16m2_b8_m
1101 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1102 // CHECK-RV64-NEXT: entry:
1103 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16.i64(<vscale x 8 x i1> poison, <vscale x 8 x i16> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
1104 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1105 //
test_vmsne_vx_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)1106 vbool8_t test_vmsne_vx_i16m2_b8_m(vbool8_t mask, vint16m2_t op1, int16_t op2, size_t vl) {
1107 return __riscv_vmsne_vx_i16m2_b8_m(mask, op1, op2, vl);
1108 }
1109
1110 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vv_i16m4_b4_m
1111 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1112 // CHECK-RV64-NEXT: entry:
1113 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i1> poison, <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
1114 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1115 //
test_vmsne_vv_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)1116 vbool4_t test_vmsne_vv_i16m4_b4_m(vbool4_t mask, vint16m4_t op1, vint16m4_t op2, size_t vl) {
1117 return __riscv_vmsne_vv_i16m4_b4_m(mask, op1, op2, vl);
1118 }
1119
1120 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vx_i16m4_b4_m
1121 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1122 // CHECK-RV64-NEXT: entry:
1123 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16.i64(<vscale x 16 x i1> poison, <vscale x 16 x i16> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
1124 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1125 //
test_vmsne_vx_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)1126 vbool4_t test_vmsne_vx_i16m4_b4_m(vbool4_t mask, vint16m4_t op1, int16_t op2, size_t vl) {
1127 return __riscv_vmsne_vx_i16m4_b4_m(mask, op1, op2, vl);
1128 }
1129
1130 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsne_vv_i16m8_b2_m
1131 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1132 // CHECK-RV64-NEXT: entry:
1133 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i1> poison, <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
1134 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
1135 //
test_vmsne_vv_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)1136 vbool2_t test_vmsne_vv_i16m8_b2_m(vbool2_t mask, vint16m8_t op1, vint16m8_t op2, size_t vl) {
1137 return __riscv_vmsne_vv_i16m8_b2_m(mask, op1, op2, vl);
1138 }
1139
1140 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsne_vx_i16m8_b2_m
1141 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1142 // CHECK-RV64-NEXT: entry:
1143 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i16.i16.i64(<vscale x 32 x i1> poison, <vscale x 32 x i16> [[OP1]], i16 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
1144 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
1145 //
test_vmsne_vx_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)1146 vbool2_t test_vmsne_vx_i16m8_b2_m(vbool2_t mask, vint16m8_t op1, int16_t op2, size_t vl) {
1147 return __riscv_vmsne_vx_i16m8_b2_m(mask, op1, op2, vl);
1148 }
1149
1150 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vv_i32mf2_b64_m
1151 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1152 // CHECK-RV64-NEXT: entry:
1153 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> poison, <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
1154 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1155 //
test_vmsne_vv_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)1156 vbool64_t test_vmsne_vv_i32mf2_b64_m(vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
1157 return __riscv_vmsne_vv_i32mf2_b64_m(mask, op1, op2, vl);
1158 }
1159
1160 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vx_i32mf2_b64_m
1161 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1162 // CHECK-RV64-NEXT: entry:
1163 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32.i64(<vscale x 1 x i1> poison, <vscale x 1 x i32> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
1164 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1165 //
test_vmsne_vx_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)1166 vbool64_t test_vmsne_vx_i32mf2_b64_m(vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
1167 return __riscv_vmsne_vx_i32mf2_b64_m(mask, op1, op2, vl);
1168 }
1169
1170 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vv_i32m1_b32_m
1171 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1172 // CHECK-RV64-NEXT: entry:
1173 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i1> poison, <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
1174 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1175 //
test_vmsne_vv_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)1176 vbool32_t test_vmsne_vv_i32m1_b32_m(vbool32_t mask, vint32m1_t op1, vint32m1_t op2, size_t vl) {
1177 return __riscv_vmsne_vv_i32m1_b32_m(mask, op1, op2, vl);
1178 }
1179
1180 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vx_i32m1_b32_m
1181 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1182 // CHECK-RV64-NEXT: entry:
1183 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32.i64(<vscale x 2 x i1> poison, <vscale x 2 x i32> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
1184 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1185 //
test_vmsne_vx_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)1186 vbool32_t test_vmsne_vx_i32m1_b32_m(vbool32_t mask, vint32m1_t op1, int32_t op2, size_t vl) {
1187 return __riscv_vmsne_vx_i32m1_b32_m(mask, op1, op2, vl);
1188 }
1189
1190 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vv_i32m2_b16_m
1191 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1192 // CHECK-RV64-NEXT: entry:
1193 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i1> poison, <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
1194 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1195 //
test_vmsne_vv_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)1196 vbool16_t test_vmsne_vv_i32m2_b16_m(vbool16_t mask, vint32m2_t op1, vint32m2_t op2, size_t vl) {
1197 return __riscv_vmsne_vv_i32m2_b16_m(mask, op1, op2, vl);
1198 }
1199
1200 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vx_i32m2_b16_m
1201 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1202 // CHECK-RV64-NEXT: entry:
1203 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32.i64(<vscale x 4 x i1> poison, <vscale x 4 x i32> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
1204 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1205 //
test_vmsne_vx_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)1206 vbool16_t test_vmsne_vx_i32m2_b16_m(vbool16_t mask, vint32m2_t op1, int32_t op2, size_t vl) {
1207 return __riscv_vmsne_vx_i32m2_b16_m(mask, op1, op2, vl);
1208 }
1209
1210 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vv_i32m4_b8_m
1211 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1212 // CHECK-RV64-NEXT: entry:
1213 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i1> poison, <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
1214 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1215 //
test_vmsne_vv_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)1216 vbool8_t test_vmsne_vv_i32m4_b8_m(vbool8_t mask, vint32m4_t op1, vint32m4_t op2, size_t vl) {
1217 return __riscv_vmsne_vv_i32m4_b8_m(mask, op1, op2, vl);
1218 }
1219
1220 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vx_i32m4_b8_m
1221 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1222 // CHECK-RV64-NEXT: entry:
1223 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32.i64(<vscale x 8 x i1> poison, <vscale x 8 x i32> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
1224 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1225 //
test_vmsne_vx_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)1226 vbool8_t test_vmsne_vx_i32m4_b8_m(vbool8_t mask, vint32m4_t op1, int32_t op2, size_t vl) {
1227 return __riscv_vmsne_vx_i32m4_b8_m(mask, op1, op2, vl);
1228 }
1229
1230 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vv_i32m8_b4_m
1231 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1232 // CHECK-RV64-NEXT: entry:
1233 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i1> poison, <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
1234 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1235 //
test_vmsne_vv_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)1236 vbool4_t test_vmsne_vv_i32m8_b4_m(vbool4_t mask, vint32m8_t op1, vint32m8_t op2, size_t vl) {
1237 return __riscv_vmsne_vv_i32m8_b4_m(mask, op1, op2, vl);
1238 }
1239
1240 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vx_i32m8_b4_m
1241 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1242 // CHECK-RV64-NEXT: entry:
1243 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i32.i32.i64(<vscale x 16 x i1> poison, <vscale x 16 x i32> [[OP1]], i32 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
1244 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1245 //
test_vmsne_vx_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)1246 vbool4_t test_vmsne_vx_i32m8_b4_m(vbool4_t mask, vint32m8_t op1, int32_t op2, size_t vl) {
1247 return __riscv_vmsne_vx_i32m8_b4_m(mask, op1, op2, vl);
1248 }
1249
1250 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vv_i64m1_b64_m
1251 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1252 // CHECK-RV64-NEXT: entry:
1253 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i1> poison, <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
1254 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1255 //
test_vmsne_vv_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)1256 vbool64_t test_vmsne_vv_i64m1_b64_m(vbool64_t mask, vint64m1_t op1, vint64m1_t op2, size_t vl) {
1257 return __riscv_vmsne_vv_i64m1_b64_m(mask, op1, op2, vl);
1258 }
1259
1260 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vx_i64m1_b64_m
1261 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1262 // CHECK-RV64-NEXT: entry:
1263 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64.i64(<vscale x 1 x i1> poison, <vscale x 1 x i64> [[OP1]], i64 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
1264 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1265 //
test_vmsne_vx_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)1266 vbool64_t test_vmsne_vx_i64m1_b64_m(vbool64_t mask, vint64m1_t op1, int64_t op2, size_t vl) {
1267 return __riscv_vmsne_vx_i64m1_b64_m(mask, op1, op2, vl);
1268 }
1269
1270 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vv_i64m2_b32_m
1271 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1272 // CHECK-RV64-NEXT: entry:
1273 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i1> poison, <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
1274 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1275 //
test_vmsne_vv_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)1276 vbool32_t test_vmsne_vv_i64m2_b32_m(vbool32_t mask, vint64m2_t op1, vint64m2_t op2, size_t vl) {
1277 return __riscv_vmsne_vv_i64m2_b32_m(mask, op1, op2, vl);
1278 }
1279
1280 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vx_i64m2_b32_m
1281 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1282 // CHECK-RV64-NEXT: entry:
1283 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64.i64(<vscale x 2 x i1> poison, <vscale x 2 x i64> [[OP1]], i64 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
1284 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1285 //
test_vmsne_vx_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)1286 vbool32_t test_vmsne_vx_i64m2_b32_m(vbool32_t mask, vint64m2_t op1, int64_t op2, size_t vl) {
1287 return __riscv_vmsne_vx_i64m2_b32_m(mask, op1, op2, vl);
1288 }
1289
1290 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vv_i64m4_b16_m
1291 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1292 // CHECK-RV64-NEXT: entry:
1293 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i1> poison, <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
1294 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1295 //
test_vmsne_vv_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)1296 vbool16_t test_vmsne_vv_i64m4_b16_m(vbool16_t mask, vint64m4_t op1, vint64m4_t op2, size_t vl) {
1297 return __riscv_vmsne_vv_i64m4_b16_m(mask, op1, op2, vl);
1298 }
1299
1300 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vx_i64m4_b16_m
1301 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1302 // CHECK-RV64-NEXT: entry:
1303 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64.i64(<vscale x 4 x i1> poison, <vscale x 4 x i64> [[OP1]], i64 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
1304 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1305 //
test_vmsne_vx_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)1306 vbool16_t test_vmsne_vx_i64m4_b16_m(vbool16_t mask, vint64m4_t op1, int64_t op2, size_t vl) {
1307 return __riscv_vmsne_vx_i64m4_b16_m(mask, op1, op2, vl);
1308 }
1309
1310 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vv_i64m8_b8_m
1311 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1312 // CHECK-RV64-NEXT: entry:
1313 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i1> poison, <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
1314 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1315 //
test_vmsne_vv_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)1316 vbool8_t test_vmsne_vv_i64m8_b8_m(vbool8_t mask, vint64m8_t op1, vint64m8_t op2, size_t vl) {
1317 return __riscv_vmsne_vv_i64m8_b8_m(mask, op1, op2, vl);
1318 }
1319
1320 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vx_i64m8_b8_m
1321 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1322 // CHECK-RV64-NEXT: entry:
1323 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i64.i64.i64(<vscale x 8 x i1> poison, <vscale x 8 x i64> [[OP1]], i64 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
1324 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1325 //
test_vmsne_vx_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)1326 vbool8_t test_vmsne_vx_i64m8_b8_m(vbool8_t mask, vint64m8_t op1, int64_t op2, size_t vl) {
1327 return __riscv_vmsne_vx_i64m8_b8_m(mask, op1, op2, vl);
1328 }
1329
1330 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vv_u8mf8_b64_m
1331 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1332 // CHECK-RV64-NEXT: entry:
1333 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> poison, <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
1334 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1335 //
test_vmsne_vv_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)1336 vbool64_t test_vmsne_vv_u8mf8_b64_m(vbool64_t mask, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
1337 return __riscv_vmsne_vv_u8mf8_b64_m(mask, op1, op2, vl);
1338 }
1339
1340 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vx_u8mf8_b64_m
1341 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1342 // CHECK-RV64-NEXT: entry:
1343 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1> poison, <vscale x 1 x i8> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
1344 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1345 //
test_vmsne_vx_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)1346 vbool64_t test_vmsne_vx_u8mf8_b64_m(vbool64_t mask, vuint8mf8_t op1, uint8_t op2, size_t vl) {
1347 return __riscv_vmsne_vx_u8mf8_b64_m(mask, op1, op2, vl);
1348 }
1349
1350 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vv_u8mf4_b32_m
1351 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1352 // CHECK-RV64-NEXT: entry:
1353 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> poison, <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
1354 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1355 //
test_vmsne_vv_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)1356 vbool32_t test_vmsne_vv_u8mf4_b32_m(vbool32_t mask, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
1357 return __riscv_vmsne_vv_u8mf4_b32_m(mask, op1, op2, vl);
1358 }
1359
1360 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vx_u8mf4_b32_m
1361 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1362 // CHECK-RV64-NEXT: entry:
1363 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1> poison, <vscale x 2 x i8> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
1364 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1365 //
test_vmsne_vx_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)1366 vbool32_t test_vmsne_vx_u8mf4_b32_m(vbool32_t mask, vuint8mf4_t op1, uint8_t op2, size_t vl) {
1367 return __riscv_vmsne_vx_u8mf4_b32_m(mask, op1, op2, vl);
1368 }
1369
1370 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vv_u8mf2_b16_m
1371 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1372 // CHECK-RV64-NEXT: entry:
1373 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> poison, <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
1374 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1375 //
test_vmsne_vv_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)1376 vbool16_t test_vmsne_vv_u8mf2_b16_m(vbool16_t mask, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
1377 return __riscv_vmsne_vv_u8mf2_b16_m(mask, op1, op2, vl);
1378 }
1379
1380 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vx_u8mf2_b16_m
1381 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1382 // CHECK-RV64-NEXT: entry:
1383 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1> poison, <vscale x 4 x i8> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
1384 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1385 //
test_vmsne_vx_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)1386 vbool16_t test_vmsne_vx_u8mf2_b16_m(vbool16_t mask, vuint8mf2_t op1, uint8_t op2, size_t vl) {
1387 return __riscv_vmsne_vx_u8mf2_b16_m(mask, op1, op2, vl);
1388 }
1389
1390 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vv_u8m1_b8_m
1391 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1392 // CHECK-RV64-NEXT: entry:
1393 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> poison, <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
1394 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1395 //
test_vmsne_vv_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)1396 vbool8_t test_vmsne_vv_u8m1_b8_m(vbool8_t mask, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
1397 return __riscv_vmsne_vv_u8m1_b8_m(mask, op1, op2, vl);
1398 }
1399
1400 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vx_u8m1_b8_m
1401 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1402 // CHECK-RV64-NEXT: entry:
1403 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8.i64(<vscale x 8 x i1> poison, <vscale x 8 x i8> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
1404 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1405 //
test_vmsne_vx_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)1406 vbool8_t test_vmsne_vx_u8m1_b8_m(vbool8_t mask, vuint8m1_t op1, uint8_t op2, size_t vl) {
1407 return __riscv_vmsne_vx_u8m1_b8_m(mask, op1, op2, vl);
1408 }
1409
1410 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vv_u8m2_b4_m
1411 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1412 // CHECK-RV64-NEXT: entry:
1413 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i1> poison, <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
1414 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1415 //
test_vmsne_vv_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)1416 vbool4_t test_vmsne_vv_u8m2_b4_m(vbool4_t mask, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
1417 return __riscv_vmsne_vv_u8m2_b4_m(mask, op1, op2, vl);
1418 }
1419
1420 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vx_u8m2_b4_m
1421 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1422 // CHECK-RV64-NEXT: entry:
1423 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8.i64(<vscale x 16 x i1> poison, <vscale x 16 x i8> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
1424 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1425 //
test_vmsne_vx_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)1426 vbool4_t test_vmsne_vx_u8m2_b4_m(vbool4_t mask, vuint8m2_t op1, uint8_t op2, size_t vl) {
1427 return __riscv_vmsne_vx_u8m2_b4_m(mask, op1, op2, vl);
1428 }
1429
1430 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsne_vv_u8m4_b2_m
1431 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1432 // CHECK-RV64-NEXT: entry:
1433 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i1> poison, <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
1434 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
1435 //
test_vmsne_vv_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)1436 vbool2_t test_vmsne_vv_u8m4_b2_m(vbool2_t mask, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
1437 return __riscv_vmsne_vv_u8m4_b2_m(mask, op1, op2, vl);
1438 }
1439
1440 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsne_vx_u8m4_b2_m
1441 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1442 // CHECK-RV64-NEXT: entry:
1443 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8.i64(<vscale x 32 x i1> poison, <vscale x 32 x i8> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
1444 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
1445 //
test_vmsne_vx_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)1446 vbool2_t test_vmsne_vx_u8m4_b2_m(vbool2_t mask, vuint8m4_t op1, uint8_t op2, size_t vl) {
1447 return __riscv_vmsne_vx_u8m4_b2_m(mask, op1, op2, vl);
1448 }
1449
1450 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmsne_vv_u8m8_b1_m
1451 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1452 // CHECK-RV64-NEXT: entry:
1453 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsne.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i1> poison, <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]])
1454 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
1455 //
test_vmsne_vv_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)1456 vbool1_t test_vmsne_vv_u8m8_b1_m(vbool1_t mask, vuint8m8_t op1, vuint8m8_t op2, size_t vl) {
1457 return __riscv_vmsne_vv_u8m8_b1_m(mask, op1, op2, vl);
1458 }
1459
1460 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmsne_vx_u8m8_b1_m
1461 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1462 // CHECK-RV64-NEXT: entry:
1463 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsne.mask.nxv64i8.i8.i64(<vscale x 64 x i1> poison, <vscale x 64 x i8> [[OP1]], i8 [[OP2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]])
1464 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
1465 //
test_vmsne_vx_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)1466 vbool1_t test_vmsne_vx_u8m8_b1_m(vbool1_t mask, vuint8m8_t op1, uint8_t op2, size_t vl) {
1467 return __riscv_vmsne_vx_u8m8_b1_m(mask, op1, op2, vl);
1468 }
1469
1470 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vv_u16mf4_b64_m
1471 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1472 // CHECK-RV64-NEXT: entry:
1473 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i1> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
1474 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1475 //
test_vmsne_vv_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)1476 vbool64_t test_vmsne_vv_u16mf4_b64_m(vbool64_t mask, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
1477 return __riscv_vmsne_vv_u16mf4_b64_m(mask, op1, op2, vl);
1478 }
1479
1480 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vx_u16mf4_b64_m
1481 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1482 // CHECK-RV64-NEXT: entry:
1483 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16.i64(<vscale x 1 x i1> poison, <vscale x 1 x i16> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
1484 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1485 //
test_vmsne_vx_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)1486 vbool64_t test_vmsne_vx_u16mf4_b64_m(vbool64_t mask, vuint16mf4_t op1, uint16_t op2, size_t vl) {
1487 return __riscv_vmsne_vx_u16mf4_b64_m(mask, op1, op2, vl);
1488 }
1489
1490 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vv_u16mf2_b32_m
1491 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1492 // CHECK-RV64-NEXT: entry:
1493 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i1> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
1494 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1495 //
test_vmsne_vv_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)1496 vbool32_t test_vmsne_vv_u16mf2_b32_m(vbool32_t mask, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
1497 return __riscv_vmsne_vv_u16mf2_b32_m(mask, op1, op2, vl);
1498 }
1499
1500 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vx_u16mf2_b32_m
1501 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1502 // CHECK-RV64-NEXT: entry:
1503 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16.i64(<vscale x 2 x i1> poison, <vscale x 2 x i16> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
1504 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1505 //
test_vmsne_vx_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)1506 vbool32_t test_vmsne_vx_u16mf2_b32_m(vbool32_t mask, vuint16mf2_t op1, uint16_t op2, size_t vl) {
1507 return __riscv_vmsne_vx_u16mf2_b32_m(mask, op1, op2, vl);
1508 }
1509
1510 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vv_u16m1_b16_m
1511 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1512 // CHECK-RV64-NEXT: entry:
1513 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i1> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
1514 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1515 //
test_vmsne_vv_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)1516 vbool16_t test_vmsne_vv_u16m1_b16_m(vbool16_t mask, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
1517 return __riscv_vmsne_vv_u16m1_b16_m(mask, op1, op2, vl);
1518 }
1519
1520 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vx_u16m1_b16_m
1521 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1522 // CHECK-RV64-NEXT: entry:
1523 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16.i64(<vscale x 4 x i1> poison, <vscale x 4 x i16> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
1524 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1525 //
test_vmsne_vx_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)1526 vbool16_t test_vmsne_vx_u16m1_b16_m(vbool16_t mask, vuint16m1_t op1, uint16_t op2, size_t vl) {
1527 return __riscv_vmsne_vx_u16m1_b16_m(mask, op1, op2, vl);
1528 }
1529
1530 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vv_u16m2_b8_m
1531 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1532 // CHECK-RV64-NEXT: entry:
1533 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i1> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
1534 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1535 //
test_vmsne_vv_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)1536 vbool8_t test_vmsne_vv_u16m2_b8_m(vbool8_t mask, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
1537 return __riscv_vmsne_vv_u16m2_b8_m(mask, op1, op2, vl);
1538 }
1539
1540 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vx_u16m2_b8_m
1541 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1542 // CHECK-RV64-NEXT: entry:
1543 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16.i64(<vscale x 8 x i1> poison, <vscale x 8 x i16> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
1544 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1545 //
test_vmsne_vx_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)1546 vbool8_t test_vmsne_vx_u16m2_b8_m(vbool8_t mask, vuint16m2_t op1, uint16_t op2, size_t vl) {
1547 return __riscv_vmsne_vx_u16m2_b8_m(mask, op1, op2, vl);
1548 }
1549
1550 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vv_u16m4_b4_m
1551 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1552 // CHECK-RV64-NEXT: entry:
1553 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i1> poison, <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
1554 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1555 //
test_vmsne_vv_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)1556 vbool4_t test_vmsne_vv_u16m4_b4_m(vbool4_t mask, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
1557 return __riscv_vmsne_vv_u16m4_b4_m(mask, op1, op2, vl);
1558 }
1559
1560 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vx_u16m4_b4_m
1561 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1562 // CHECK-RV64-NEXT: entry:
1563 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16.i64(<vscale x 16 x i1> poison, <vscale x 16 x i16> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
1564 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1565 //
test_vmsne_vx_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)1566 vbool4_t test_vmsne_vx_u16m4_b4_m(vbool4_t mask, vuint16m4_t op1, uint16_t op2, size_t vl) {
1567 return __riscv_vmsne_vx_u16m4_b4_m(mask, op1, op2, vl);
1568 }
1569
1570 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsne_vv_u16m8_b2_m
1571 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1572 // CHECK-RV64-NEXT: entry:
1573 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i1> poison, <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
1574 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
1575 //
test_vmsne_vv_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)1576 vbool2_t test_vmsne_vv_u16m8_b2_m(vbool2_t mask, vuint16m8_t op1, vuint16m8_t op2, size_t vl) {
1577 return __riscv_vmsne_vv_u16m8_b2_m(mask, op1, op2, vl);
1578 }
1579
1580 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmsne_vx_u16m8_b2_m
1581 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 noundef zeroext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1582 // CHECK-RV64-NEXT: entry:
1583 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i16.i16.i64(<vscale x 32 x i1> poison, <vscale x 32 x i16> [[OP1]], i16 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
1584 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
1585 //
test_vmsne_vx_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)1586 vbool2_t test_vmsne_vx_u16m8_b2_m(vbool2_t mask, vuint16m8_t op1, uint16_t op2, size_t vl) {
1587 return __riscv_vmsne_vx_u16m8_b2_m(mask, op1, op2, vl);
1588 }
1589
1590 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vv_u32mf2_b64_m
1591 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1592 // CHECK-RV64-NEXT: entry:
1593 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> poison, <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
1594 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1595 //
test_vmsne_vv_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)1596 vbool64_t test_vmsne_vv_u32mf2_b64_m(vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
1597 return __riscv_vmsne_vv_u32mf2_b64_m(mask, op1, op2, vl);
1598 }
1599
1600 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vx_u32mf2_b64_m
1601 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1602 // CHECK-RV64-NEXT: entry:
1603 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32.i64(<vscale x 1 x i1> poison, <vscale x 1 x i32> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
1604 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1605 //
test_vmsne_vx_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)1606 vbool64_t test_vmsne_vx_u32mf2_b64_m(vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
1607 return __riscv_vmsne_vx_u32mf2_b64_m(mask, op1, op2, vl);
1608 }
1609
1610 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vv_u32m1_b32_m
1611 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1612 // CHECK-RV64-NEXT: entry:
1613 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i1> poison, <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
1614 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1615 //
test_vmsne_vv_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)1616 vbool32_t test_vmsne_vv_u32m1_b32_m(vbool32_t mask, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
1617 return __riscv_vmsne_vv_u32m1_b32_m(mask, op1, op2, vl);
1618 }
1619
1620 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vx_u32m1_b32_m
1621 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1622 // CHECK-RV64-NEXT: entry:
1623 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32.i64(<vscale x 2 x i1> poison, <vscale x 2 x i32> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
1624 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1625 //
test_vmsne_vx_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)1626 vbool32_t test_vmsne_vx_u32m1_b32_m(vbool32_t mask, vuint32m1_t op1, uint32_t op2, size_t vl) {
1627 return __riscv_vmsne_vx_u32m1_b32_m(mask, op1, op2, vl);
1628 }
1629
1630 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vv_u32m2_b16_m
1631 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1632 // CHECK-RV64-NEXT: entry:
1633 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i1> poison, <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
1634 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1635 //
test_vmsne_vv_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)1636 vbool16_t test_vmsne_vv_u32m2_b16_m(vbool16_t mask, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
1637 return __riscv_vmsne_vv_u32m2_b16_m(mask, op1, op2, vl);
1638 }
1639
1640 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vx_u32m2_b16_m
1641 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1642 // CHECK-RV64-NEXT: entry:
1643 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32.i64(<vscale x 4 x i1> poison, <vscale x 4 x i32> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
1644 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1645 //
test_vmsne_vx_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)1646 vbool16_t test_vmsne_vx_u32m2_b16_m(vbool16_t mask, vuint32m2_t op1, uint32_t op2, size_t vl) {
1647 return __riscv_vmsne_vx_u32m2_b16_m(mask, op1, op2, vl);
1648 }
1649
1650 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vv_u32m4_b8_m
1651 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1652 // CHECK-RV64-NEXT: entry:
1653 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i1> poison, <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
1654 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1655 //
test_vmsne_vv_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)1656 vbool8_t test_vmsne_vv_u32m4_b8_m(vbool8_t mask, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
1657 return __riscv_vmsne_vv_u32m4_b8_m(mask, op1, op2, vl);
1658 }
1659
1660 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vx_u32m4_b8_m
1661 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1662 // CHECK-RV64-NEXT: entry:
1663 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32.i64(<vscale x 8 x i1> poison, <vscale x 8 x i32> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
1664 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1665 //
test_vmsne_vx_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)1666 vbool8_t test_vmsne_vx_u32m4_b8_m(vbool8_t mask, vuint32m4_t op1, uint32_t op2, size_t vl) {
1667 return __riscv_vmsne_vx_u32m4_b8_m(mask, op1, op2, vl);
1668 }
1669
1670 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vv_u32m8_b4_m
1671 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1672 // CHECK-RV64-NEXT: entry:
1673 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i1> poison, <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
1674 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1675 //
test_vmsne_vv_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)1676 vbool4_t test_vmsne_vv_u32m8_b4_m(vbool4_t mask, vuint32m8_t op1, vuint32m8_t op2, size_t vl) {
1677 return __riscv_vmsne_vv_u32m8_b4_m(mask, op1, op2, vl);
1678 }
1679
1680 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmsne_vx_u32m8_b4_m
1681 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 noundef signext [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1682 // CHECK-RV64-NEXT: entry:
1683 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i32.i32.i64(<vscale x 16 x i1> poison, <vscale x 16 x i32> [[OP1]], i32 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
1684 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
1685 //
test_vmsne_vx_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)1686 vbool4_t test_vmsne_vx_u32m8_b4_m(vbool4_t mask, vuint32m8_t op1, uint32_t op2, size_t vl) {
1687 return __riscv_vmsne_vx_u32m8_b4_m(mask, op1, op2, vl);
1688 }
1689
1690 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vv_u64m1_b64_m
1691 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1692 // CHECK-RV64-NEXT: entry:
1693 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i1> poison, <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
1694 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1695 //
test_vmsne_vv_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)1696 vbool64_t test_vmsne_vv_u64m1_b64_m(vbool64_t mask, vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
1697 return __riscv_vmsne_vv_u64m1_b64_m(mask, op1, op2, vl);
1698 }
1699
1700 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmsne_vx_u64m1_b64_m
1701 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1702 // CHECK-RV64-NEXT: entry:
1703 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64.i64(<vscale x 1 x i1> poison, <vscale x 1 x i64> [[OP1]], i64 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
1704 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
1705 //
test_vmsne_vx_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)1706 vbool64_t test_vmsne_vx_u64m1_b64_m(vbool64_t mask, vuint64m1_t op1, uint64_t op2, size_t vl) {
1707 return __riscv_vmsne_vx_u64m1_b64_m(mask, op1, op2, vl);
1708 }
1709
1710 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vv_u64m2_b32_m
1711 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1712 // CHECK-RV64-NEXT: entry:
1713 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i1> poison, <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
1714 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1715 //
test_vmsne_vv_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)1716 vbool32_t test_vmsne_vv_u64m2_b32_m(vbool32_t mask, vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
1717 return __riscv_vmsne_vv_u64m2_b32_m(mask, op1, op2, vl);
1718 }
1719
1720 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmsne_vx_u64m2_b32_m
1721 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1722 // CHECK-RV64-NEXT: entry:
1723 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64.i64(<vscale x 2 x i1> poison, <vscale x 2 x i64> [[OP1]], i64 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
1724 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
1725 //
test_vmsne_vx_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)1726 vbool32_t test_vmsne_vx_u64m2_b32_m(vbool32_t mask, vuint64m2_t op1, uint64_t op2, size_t vl) {
1727 return __riscv_vmsne_vx_u64m2_b32_m(mask, op1, op2, vl);
1728 }
1729
1730 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vv_u64m4_b16_m
1731 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1732 // CHECK-RV64-NEXT: entry:
1733 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i1> poison, <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
1734 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1735 //
test_vmsne_vv_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)1736 vbool16_t test_vmsne_vv_u64m4_b16_m(vbool16_t mask, vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
1737 return __riscv_vmsne_vv_u64m4_b16_m(mask, op1, op2, vl);
1738 }
1739
1740 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmsne_vx_u64m4_b16_m
1741 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1742 // CHECK-RV64-NEXT: entry:
1743 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64.i64(<vscale x 4 x i1> poison, <vscale x 4 x i64> [[OP1]], i64 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
1744 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
1745 //
test_vmsne_vx_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)1746 vbool16_t test_vmsne_vx_u64m4_b16_m(vbool16_t mask, vuint64m4_t op1, uint64_t op2, size_t vl) {
1747 return __riscv_vmsne_vx_u64m4_b16_m(mask, op1, op2, vl);
1748 }
1749
1750 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vv_u64m8_b8_m
1751 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1752 // CHECK-RV64-NEXT: entry:
1753 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i1> poison, <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
1754 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1755 //
test_vmsne_vv_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)1756 vbool8_t test_vmsne_vv_u64m8_b8_m(vbool8_t mask, vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
1757 return __riscv_vmsne_vv_u64m8_b8_m(mask, op1, op2, vl);
1758 }
1759
1760 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmsne_vx_u64m8_b8_m
1761 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1762 // CHECK-RV64-NEXT: entry:
1763 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i64.i64.i64(<vscale x 8 x i1> poison, <vscale x 8 x i64> [[OP1]], i64 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
1764 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
1765 //
test_vmsne_vx_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)1766 vbool8_t test_vmsne_vx_u64m8_b8_m(vbool8_t mask, vuint64m8_t op1, uint64_t op2, size_t vl) {
1767 return __riscv_vmsne_vx_u64m8_b8_m(mask, op1, op2, vl);
1768 }
1769
1770