xref: /llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c (revision 051054e6f74303bc880221e88671745f363964cc) 
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
4 // RUN:   -target-feature +zvbb \
5 // RUN:   -target-feature +zvbc \
6 // RUN:   -target-feature +zvkb \
7 // RUN:   -target-feature +zvkg \
8 // RUN:   -target-feature +zvkned \
9 // RUN:   -target-feature +zvknhb \
10 // RUN:   -target-feature +zvksed \
11 // RUN:   -target-feature +zvksh \
12 // RUN:   -disable-O0-optnone \
13 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
14 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
15 
16 #include <riscv_vector.h>
17 
18 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8
19 // CHECK-RV64-SAME: (<vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
20 // CHECK-RV64-NEXT:  entry:
21 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[VS2]], i64 [[VL]])
22 // CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
23 //
24 vuint8mf8_t test_vbrev8_v_u8mf8(vuint8mf8_t vs2, size_t vl) {
25   return __riscv_vbrev8_v_u8mf8(vs2, vl);
26 }
27 
28 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4
29 // CHECK-RV64-SAME: (<vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
30 // CHECK-RV64-NEXT:  entry:
31 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[VS2]], i64 [[VL]])
32 // CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
33 //
34 vuint8mf4_t test_vbrev8_v_u8mf4(vuint8mf4_t vs2, size_t vl) {
35   return __riscv_vbrev8_v_u8mf4(vs2, vl);
36 }
37 
38 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2
39 // CHECK-RV64-SAME: (<vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
40 // CHECK-RV64-NEXT:  entry:
41 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[VS2]], i64 [[VL]])
42 // CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
43 //
44 vuint8mf2_t test_vbrev8_v_u8mf2(vuint8mf2_t vs2, size_t vl) {
45   return __riscv_vbrev8_v_u8mf2(vs2, vl);
46 }
47 
48 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1
49 // CHECK-RV64-SAME: (<vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
50 // CHECK-RV64-NEXT:  entry:
51 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[VS2]], i64 [[VL]])
52 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
53 //
54 vuint8m1_t test_vbrev8_v_u8m1(vuint8m1_t vs2, size_t vl) {
55   return __riscv_vbrev8_v_u8m1(vs2, vl);
56 }
57 
58 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2
59 // CHECK-RV64-SAME: (<vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
60 // CHECK-RV64-NEXT:  entry:
61 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[VS2]], i64 [[VL]])
62 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
63 //
64 vuint8m2_t test_vbrev8_v_u8m2(vuint8m2_t vs2, size_t vl) {
65   return __riscv_vbrev8_v_u8m2(vs2, vl);
66 }
67 
68 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4
69 // CHECK-RV64-SAME: (<vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
70 // CHECK-RV64-NEXT:  entry:
71 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[VS2]], i64 [[VL]])
72 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
73 //
74 vuint8m4_t test_vbrev8_v_u8m4(vuint8m4_t vs2, size_t vl) {
75   return __riscv_vbrev8_v_u8m4(vs2, vl);
76 }
77 
78 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8
79 // CHECK-RV64-SAME: (<vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
80 // CHECK-RV64-NEXT:  entry:
81 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[VS2]], i64 [[VL]])
82 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
83 //
84 vuint8m8_t test_vbrev8_v_u8m8(vuint8m8_t vs2, size_t vl) {
85   return __riscv_vbrev8_v_u8m8(vs2, vl);
86 }
87 
88 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4
89 // CHECK-RV64-SAME: (<vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
90 // CHECK-RV64-NEXT:  entry:
91 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[VS2]], i64 [[VL]])
92 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
93 //
94 vuint16mf4_t test_vbrev8_v_u16mf4(vuint16mf4_t vs2, size_t vl) {
95   return __riscv_vbrev8_v_u16mf4(vs2, vl);
96 }
97 
98 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2
99 // CHECK-RV64-SAME: (<vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
100 // CHECK-RV64-NEXT:  entry:
101 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[VS2]], i64 [[VL]])
102 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
103 //
104 vuint16mf2_t test_vbrev8_v_u16mf2(vuint16mf2_t vs2, size_t vl) {
105   return __riscv_vbrev8_v_u16mf2(vs2, vl);
106 }
107 
108 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1
109 // CHECK-RV64-SAME: (<vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
110 // CHECK-RV64-NEXT:  entry:
111 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[VS2]], i64 [[VL]])
112 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
113 //
114 vuint16m1_t test_vbrev8_v_u16m1(vuint16m1_t vs2, size_t vl) {
115   return __riscv_vbrev8_v_u16m1(vs2, vl);
116 }
117 
118 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vbrev8_v_u16m2
119 // CHECK-RV64-SAME: (<vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
120 // CHECK-RV64-NEXT:  entry:
121 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[VS2]], i64 [[VL]])
122 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
123 //
124 vuint16m2_t test_vbrev8_v_u16m2(vuint16m2_t vs2, size_t vl) {
125   return __riscv_vbrev8_v_u16m2(vs2, vl);
126 }
127 
128 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vbrev8_v_u16m4
129 // CHECK-RV64-SAME: (<vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
130 // CHECK-RV64-NEXT:  entry:
131 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[VS2]], i64 [[VL]])
132 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
133 //
134 vuint16m4_t test_vbrev8_v_u16m4(vuint16m4_t vs2, size_t vl) {
135   return __riscv_vbrev8_v_u16m4(vs2, vl);
136 }
137 
138 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vbrev8_v_u16m8
139 // CHECK-RV64-SAME: (<vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
140 // CHECK-RV64-NEXT:  entry:
141 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vbrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[VS2]], i64 [[VL]])
142 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
143 //
144 vuint16m8_t test_vbrev8_v_u16m8(vuint16m8_t vs2, size_t vl) {
145   return __riscv_vbrev8_v_u16m8(vs2, vl);
146 }
147 
148 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vbrev8_v_u32mf2
149 // CHECK-RV64-SAME: (<vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
150 // CHECK-RV64-NEXT:  entry:
151 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vbrev8.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[VS2]], i64 [[VL]])
152 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
153 //
154 vuint32mf2_t test_vbrev8_v_u32mf2(vuint32mf2_t vs2, size_t vl) {
155   return __riscv_vbrev8_v_u32mf2(vs2, vl);
156 }
157 
158 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vbrev8_v_u32m1
159 // CHECK-RV64-SAME: (<vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
160 // CHECK-RV64-NEXT:  entry:
161 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vbrev8.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[VS2]], i64 [[VL]])
162 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
163 //
164 vuint32m1_t test_vbrev8_v_u32m1(vuint32m1_t vs2, size_t vl) {
165   return __riscv_vbrev8_v_u32m1(vs2, vl);
166 }
167 
168 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vbrev8_v_u32m2
169 // CHECK-RV64-SAME: (<vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
170 // CHECK-RV64-NEXT:  entry:
171 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vbrev8.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[VS2]], i64 [[VL]])
172 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
173 //
174 vuint32m2_t test_vbrev8_v_u32m2(vuint32m2_t vs2, size_t vl) {
175   return __riscv_vbrev8_v_u32m2(vs2, vl);
176 }
177 
178 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vbrev8_v_u32m4
179 // CHECK-RV64-SAME: (<vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
180 // CHECK-RV64-NEXT:  entry:
181 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vbrev8.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[VS2]], i64 [[VL]])
182 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
183 //
184 vuint32m4_t test_vbrev8_v_u32m4(vuint32m4_t vs2, size_t vl) {
185   return __riscv_vbrev8_v_u32m4(vs2, vl);
186 }
187 
188 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vbrev8_v_u32m8
189 // CHECK-RV64-SAME: (<vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
190 // CHECK-RV64-NEXT:  entry:
191 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vbrev8.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[VS2]], i64 [[VL]])
192 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
193 //
194 vuint32m8_t test_vbrev8_v_u32m8(vuint32m8_t vs2, size_t vl) {
195   return __riscv_vbrev8_v_u32m8(vs2, vl);
196 }
197 
198 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vbrev8_v_u64m1
199 // CHECK-RV64-SAME: (<vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
200 // CHECK-RV64-NEXT:  entry:
201 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vbrev8.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[VS2]], i64 [[VL]])
202 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
203 //
204 vuint64m1_t test_vbrev8_v_u64m1(vuint64m1_t vs2, size_t vl) {
205   return __riscv_vbrev8_v_u64m1(vs2, vl);
206 }
207 
208 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vbrev8_v_u64m2
209 // CHECK-RV64-SAME: (<vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
210 // CHECK-RV64-NEXT:  entry:
211 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vbrev8.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[VS2]], i64 [[VL]])
212 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
213 //
214 vuint64m2_t test_vbrev8_v_u64m2(vuint64m2_t vs2, size_t vl) {
215   return __riscv_vbrev8_v_u64m2(vs2, vl);
216 }
217 
218 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vbrev8_v_u64m4
219 // CHECK-RV64-SAME: (<vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
220 // CHECK-RV64-NEXT:  entry:
221 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vbrev8.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[VS2]], i64 [[VL]])
222 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
223 //
224 vuint64m4_t test_vbrev8_v_u64m4(vuint64m4_t vs2, size_t vl) {
225   return __riscv_vbrev8_v_u64m4(vs2, vl);
226 }
227 
228 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vbrev8_v_u64m8
229 // CHECK-RV64-SAME: (<vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
230 // CHECK-RV64-NEXT:  entry:
231 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vbrev8.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[VS2]], i64 [[VL]])
232 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
233 //
234 vuint64m8_t test_vbrev8_v_u64m8(vuint64m8_t vs2, size_t vl) {
235   return __riscv_vbrev8_v_u64m8(vs2, vl);
236 }
237 
238 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8_m
239 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
240 // CHECK-RV64-NEXT:  entry:
241 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vbrev8.mask.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
242 // CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
243 //
244 vuint8mf8_t test_vbrev8_v_u8mf8_m(vbool64_t mask, vuint8mf8_t vs2, size_t vl) {
245   return __riscv_vbrev8_v_u8mf8_m(mask, vs2, vl);
246 }
247 
248 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4_m
249 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
250 // CHECK-RV64-NEXT:  entry:
251 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vbrev8.mask.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
252 // CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
253 //
254 vuint8mf4_t test_vbrev8_v_u8mf4_m(vbool32_t mask, vuint8mf4_t vs2, size_t vl) {
255   return __riscv_vbrev8_v_u8mf4_m(mask, vs2, vl);
256 }
257 
258 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2_m
259 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
260 // CHECK-RV64-NEXT:  entry:
261 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vbrev8.mask.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
262 // CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
263 //
264 vuint8mf2_t test_vbrev8_v_u8mf2_m(vbool16_t mask, vuint8mf2_t vs2, size_t vl) {
265   return __riscv_vbrev8_v_u8mf2_m(mask, vs2, vl);
266 }
267 
268 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1_m
269 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
270 // CHECK-RV64-NEXT:  entry:
271 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vbrev8.mask.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
272 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
273 //
274 vuint8m1_t test_vbrev8_v_u8m1_m(vbool8_t mask, vuint8m1_t vs2, size_t vl) {
275   return __riscv_vbrev8_v_u8m1_m(mask, vs2, vl);
276 }
277 
278 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2_m
279 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
280 // CHECK-RV64-NEXT:  entry:
281 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vbrev8.mask.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
282 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
283 //
284 vuint8m2_t test_vbrev8_v_u8m2_m(vbool4_t mask, vuint8m2_t vs2, size_t vl) {
285   return __riscv_vbrev8_v_u8m2_m(mask, vs2, vl);
286 }
287 
288 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4_m
289 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
290 // CHECK-RV64-NEXT:  entry:
291 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vbrev8.mask.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)
292 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
293 //
294 vuint8m4_t test_vbrev8_v_u8m4_m(vbool2_t mask, vuint8m4_t vs2, size_t vl) {
295   return __riscv_vbrev8_v_u8m4_m(mask, vs2, vl);
296 }
297 
298 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8_m
299 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
300 // CHECK-RV64-NEXT:  entry:
301 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vbrev8.mask.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[VS2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 3)
302 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
303 //
304 vuint8m8_t test_vbrev8_v_u8m8_m(vbool1_t mask, vuint8m8_t vs2, size_t vl) {
305   return __riscv_vbrev8_v_u8m8_m(mask, vs2, vl);
306 }
307 
308 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4_m
309 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
310 // CHECK-RV64-NEXT:  entry:
311 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vbrev8.mask.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
312 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
313 //
314 vuint16mf4_t test_vbrev8_v_u16mf4_m(vbool64_t mask, vuint16mf4_t vs2, size_t vl) {
315   return __riscv_vbrev8_v_u16mf4_m(mask, vs2, vl);
316 }
317 
318 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2_m
319 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
320 // CHECK-RV64-NEXT:  entry:
321 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vbrev8.mask.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
322 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
323 //
324 vuint16mf2_t test_vbrev8_v_u16mf2_m(vbool32_t mask, vuint16mf2_t vs2, size_t vl) {
325   return __riscv_vbrev8_v_u16mf2_m(mask, vs2, vl);
326 }
327 
328 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1_m
329 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
330 // CHECK-RV64-NEXT:  entry:
331 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vbrev8.mask.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
332 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
333 //
334 vuint16m1_t test_vbrev8_v_u16m1_m(vbool16_t mask, vuint16m1_t vs2, size_t vl) {
335   return __riscv_vbrev8_v_u16m1_m(mask, vs2, vl);
336 }
337 
338 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vbrev8_v_u16m2_m
339 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
340 // CHECK-RV64-NEXT:  entry:
341 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vbrev8.mask.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
342 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
343 //
344 vuint16m2_t test_vbrev8_v_u16m2_m(vbool8_t mask, vuint16m2_t vs2, size_t vl) {
345   return __riscv_vbrev8_v_u16m2_m(mask, vs2, vl);
346 }
347 
348 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vbrev8_v_u16m4_m
349 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
350 // CHECK-RV64-NEXT:  entry:
351 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vbrev8.mask.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
352 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
353 //
354 vuint16m4_t test_vbrev8_v_u16m4_m(vbool4_t mask, vuint16m4_t vs2, size_t vl) {
355   return __riscv_vbrev8_v_u16m4_m(mask, vs2, vl);
356 }
357 
358 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vbrev8_v_u16m8_m
359 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
360 // CHECK-RV64-NEXT:  entry:
361 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vbrev8.mask.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3)
362 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
363 //
364 vuint16m8_t test_vbrev8_v_u16m8_m(vbool2_t mask, vuint16m8_t vs2, size_t vl) {
365   return __riscv_vbrev8_v_u16m8_m(mask, vs2, vl);
366 }
367 
368 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vbrev8_v_u32mf2_m
369 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
370 // CHECK-RV64-NEXT:  entry:
371 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vbrev8.mask.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
372 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
373 //
374 vuint32mf2_t test_vbrev8_v_u32mf2_m(vbool64_t mask, vuint32mf2_t vs2, size_t vl) {
375   return __riscv_vbrev8_v_u32mf2_m(mask, vs2, vl);
376 }
377 
378 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vbrev8_v_u32m1_m
379 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
380 // CHECK-RV64-NEXT:  entry:
381 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vbrev8.mask.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
382 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
383 //
384 vuint32m1_t test_vbrev8_v_u32m1_m(vbool32_t mask, vuint32m1_t vs2, size_t vl) {
385   return __riscv_vbrev8_v_u32m1_m(mask, vs2, vl);
386 }
387 
388 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vbrev8_v_u32m2_m
389 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
390 // CHECK-RV64-NEXT:  entry:
391 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vbrev8.mask.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
392 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
393 //
394 vuint32m2_t test_vbrev8_v_u32m2_m(vbool16_t mask, vuint32m2_t vs2, size_t vl) {
395   return __riscv_vbrev8_v_u32m2_m(mask, vs2, vl);
396 }
397 
398 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vbrev8_v_u32m4_m
399 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
400 // CHECK-RV64-NEXT:  entry:
401 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vbrev8.mask.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
402 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
403 //
404 vuint32m4_t test_vbrev8_v_u32m4_m(vbool8_t mask, vuint32m4_t vs2, size_t vl) {
405   return __riscv_vbrev8_v_u32m4_m(mask, vs2, vl);
406 }
407 
408 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vbrev8_v_u32m8_m
409 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
410 // CHECK-RV64-NEXT:  entry:
411 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vbrev8.mask.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
412 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
413 //
414 vuint32m8_t test_vbrev8_v_u32m8_m(vbool4_t mask, vuint32m8_t vs2, size_t vl) {
415   return __riscv_vbrev8_v_u32m8_m(mask, vs2, vl);
416 }
417 
418 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vbrev8_v_u64m1_m
419 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
420 // CHECK-RV64-NEXT:  entry:
421 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vbrev8.mask.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
422 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
423 //
424 vuint64m1_t test_vbrev8_v_u64m1_m(vbool64_t mask, vuint64m1_t vs2, size_t vl) {
425   return __riscv_vbrev8_v_u64m1_m(mask, vs2, vl);
426 }
427 
428 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vbrev8_v_u64m2_m
429 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
430 // CHECK-RV64-NEXT:  entry:
431 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vbrev8.mask.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
432 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
433 //
434 vuint64m2_t test_vbrev8_v_u64m2_m(vbool32_t mask, vuint64m2_t vs2, size_t vl) {
435   return __riscv_vbrev8_v_u64m2_m(mask, vs2, vl);
436 }
437 
438 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vbrev8_v_u64m4_m
439 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
440 // CHECK-RV64-NEXT:  entry:
441 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vbrev8.mask.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
442 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
443 //
444 vuint64m4_t test_vbrev8_v_u64m4_m(vbool16_t mask, vuint64m4_t vs2, size_t vl) {
445   return __riscv_vbrev8_v_u64m4_m(mask, vs2, vl);
446 }
447 
448 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vbrev8_v_u64m8_m
449 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
450 // CHECK-RV64-NEXT:  entry:
451 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vbrev8.mask.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
452 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
453 //
454 vuint64m8_t test_vbrev8_v_u64m8_m(vbool8_t mask, vuint64m8_t vs2, size_t vl) {
455   return __riscv_vbrev8_v_u64m8_m(mask, vs2, vl);
456 }
457 
458