1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // RUN: %clang_cc1 -triple riscv32 -target-feature +zksh -emit-llvm %s -o - \
3 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
4 // RUN: | FileCheck %s -check-prefix=RV32ZKSH
5 // RUN: %clang_cc1 -triple riscv64 -target-feature +zksh -emit-llvm %s -o - \
6 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
7 // RUN: | FileCheck %s -check-prefix=RV64ZKSH
8
9 #include <riscv_crypto.h>
10
11 // RV32ZKSH-LABEL: @sm3p0(
12 // RV32ZKSH-NEXT: entry:
13 // RV32ZKSH-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[RS1:%.*]])
14 // RV32ZKSH-NEXT: ret i32 [[TMP0]]
15 //
16 // RV64ZKSH-LABEL: @sm3p0(
17 // RV64ZKSH-NEXT: entry:
18 // RV64ZKSH-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[RS1:%.*]])
19 // RV64ZKSH-NEXT: ret i32 [[TMP0]]
20 //
sm3p0(uint32_t rs1)21 uint32_t sm3p0(uint32_t rs1) {
22 return __riscv_sm3p0(rs1);
23 }
24
25
26 // RV32ZKSH-LABEL: @sm3p1(
27 // RV32ZKSH-NEXT: entry:
28 // RV32ZKSH-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[RS1:%.*]])
29 // RV32ZKSH-NEXT: ret i32 [[TMP0]]
30 //
31 // RV64ZKSH-LABEL: @sm3p1(
32 // RV64ZKSH-NEXT: entry:
33 // RV64ZKSH-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[RS1:%.*]])
34 // RV64ZKSH-NEXT: ret i32 [[TMP0]]
35 //
sm3p1(uint32_t rs1)36 uint32_t sm3p1(uint32_t rs1) {
37 return __riscv_sm3p1(rs1);
38 }
39