1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // RUN: %clang_cc1 -triple riscv32 -target-feature +zbkx -emit-llvm %s -o - \
3 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
4 // RUN: | FileCheck %s -check-prefix=RV32ZBKX
5 // RUN: %clang_cc1 -triple riscv64 -target-feature +zbkx -emit-llvm %s -o - \
6 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
7 // RUN: | FileCheck %s -check-prefix=RV64ZBKX
8
9 #include <riscv_bitmanip.h>
10
11 #if __riscv_xlen == 32
12 // RV32ZBKX-LABEL: @xperm8_32(
13 // RV32ZBKX-NEXT: entry:
14 // RV32ZBKX-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.xperm8.i32(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
15 // RV32ZBKX-NEXT: ret i32 [[TMP0]]
16 //
xperm8_32(uint32_t rs1,uint32_t rs2)17 uint32_t xperm8_32(uint32_t rs1, uint32_t rs2)
18 {
19 return __riscv_xperm8_32(rs1, rs2);
20 }
21
22 // RV32ZBKX-LABEL: @xperm4_32(
23 // RV32ZBKX-NEXT: entry:
24 // RV32ZBKX-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.xperm4.i32(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
25 // RV32ZBKX-NEXT: ret i32 [[TMP0]]
26 //
xperm4_32(uint32_t rs1,uint32_t rs2)27 uint32_t xperm4_32(uint32_t rs1, uint32_t rs2)
28 {
29 return __riscv_xperm4_32(rs1, rs2);
30 }
31 #endif
32
33 #if __riscv_xlen == 64
34 // RV64ZBKX-LABEL: @xperm8_64(
35 // RV64ZBKX-NEXT: entry:
36 // RV64ZBKX-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.xperm8.i64(i64 [[RS1:%.*]], i64 [[RS2:%.*]])
37 // RV64ZBKX-NEXT: ret i64 [[TMP0]]
38 //
xperm8_64(uint64_t rs1,uint64_t rs2)39 uint64_t xperm8_64(uint64_t rs1, uint64_t rs2)
40 {
41 return __riscv_xperm8_64(rs1, rs2);
42 }
43
44 // RV64ZBKX-LABEL: @xperm4_64(
45 // RV64ZBKX-NEXT: entry:
46 // RV64ZBKX-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.xperm4.i64(i64 [[RS1:%.*]], i64 [[RS2:%.*]])
47 // RV64ZBKX-NEXT: ret i64 [[TMP0]]
48 //
xperm4_64(uint64_t rs1,uint64_t rs2)49 uint64_t xperm4_64(uint64_t rs1, uint64_t rs2)
50 {
51 return __riscv_xperm4_64(rs1, rs2);
52 }
53 #endif
54