1 // REQUIRES: riscv-registered-target
2 // RUN: %clang_cc1 -triple riscv64 -target-feature +v \
3 // RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s
4 // RUN: %clang_cc1 -std=c23 -triple riscv64 -target-feature +v \
5 // RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s
6
7 #include <riscv_vector.h>
8
9 // CHECK-LLVM: call riscv_vector_cc <vscale x 2 x i32> @bar
10 vint32m1_t __attribute__((riscv_vector_cc)) bar(vint32m1_t input);
test_vector_cc_attr(vint32m1_t input,int32_t * base,size_t vl)11 vint32m1_t test_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) {
12 vint32m1_t val = __riscv_vle32_v_i32m1(base, vl);
13 vint32m1_t ret = bar(input);
14 __riscv_vse32_v_i32m1(base, val, vl);
15 return ret;
16 }
17
18 // CHECK-LLVM: call riscv_vector_cc <vscale x 2 x i32> @bar
19 [[riscv::vector_cc]] vint32m1_t bar(vint32m1_t input);
test_vector_cc_attr2(vint32m1_t input,int32_t * base,size_t vl)20 vint32m1_t test_vector_cc_attr2(vint32m1_t input, int32_t *base, size_t vl) {
21 vint32m1_t val = __riscv_vle32_v_i32m1(base, vl);
22 vint32m1_t ret = bar(input);
23 __riscv_vse32_v_i32m1(base, val, vl);
24 return ret;
25 }
26
27 // CHECK-LLVM: call <vscale x 2 x i32> @baz
28 vint32m1_t baz(vint32m1_t input);
test_no_vector_cc_attr(vint32m1_t input,int32_t * base,size_t vl)29 vint32m1_t test_no_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) {
30 vint32m1_t val = __riscv_vle32_v_i32m1(base, vl);
31 vint32m1_t ret = baz(input);
32 __riscv_vse32_v_i32m1(base, val, vl);
33 return ret;
34 }
35