1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv32 -O2 -emit-llvm %s -o - \
4 // RUN: | FileCheck %s
5 // RUN: %clang_cc1 -triple riscv64 -O2 -emit-llvm %s -o - \
6 // RUN: | FileCheck %s
7
8 // Test RISC-V specific clobbered registers in inline assembly.
9
10 // CHECK-LABEL: define {{.*}} void @test_fflags
11 // CHECK: tail call void asm sideeffect "", "~{fflags}"()
test_fflags(void)12 void test_fflags(void) {
13 asm volatile ("" :::"fflags");
14 }
15
16 // CHECK-LABEL: define {{.*}} void @test_frm
17 // CHECK: tail call void asm sideeffect "", "~{frm}"()
test_frm(void)18 void test_frm(void) {
19 asm volatile ("" :::"frm");
20 }
21
22 // CHECK-LABEL: define {{.*}} void @test_vtype
23 // CHECK: tail call void asm sideeffect "", "~{vtype}"()
test_vtype(void)24 void test_vtype(void) {
25 asm volatile ("" :::"vtype");
26 }
27
28 // CHECK-LABEL: define {{.*}} void @test_vl
29 // CHECK: tail call void asm sideeffect "", "~{vl}"()
test_vl(void)30 void test_vl(void) {
31 asm volatile ("" :::"vl");
32 }
33
34 // CHECK-LABEL: define {{.*}} void @test_vxsat
35 // CHECK: tail call void asm sideeffect "", "~{vxsat}"()
test_vxsat(void)36 void test_vxsat(void) {
37 asm volatile ("" :::"vxsat");
38 }
39
40 // CHECK-LABEL: define {{.*}} void @test_vxrm
41 // CHECK: tail call void asm sideeffect "", "~{vxrm}"()
test_vxrm(void)42 void test_vxrm(void) {
43 asm volatile ("" :::"vxrm");
44 }
45