1 // REQUIRES: riscv-registered-target 2 // RUN: %clang_cc1 -triple riscv64 -target-feature +zifencei -target-feature +m \ 3 // RUN: -target-feature +a -target-feature +save-restore -target-feature -zbb \ 4 // RUN: -target-feature -relax -target-feature -zfa \ 5 // RUN: -emit-llvm %s -o - | FileCheck %s 6 7 #include <riscv_vector.h> 8 9 // CHECK-LABEL: define dso_local void @testDefault 10 // CHECK-SAME: () #0 { 11 void testDefault() {} 12 // CHECK-LABEL: define dso_local void @testMultiAttrStr 13 // CHECK-SAME: () #1 { 14 __attribute__((target("cpu=rocket-rv64;tune=generic-rv64;arch=+v"))) void 15 testMultiAttrStr() {} 16 // CHECK-LABEL: define dso_local void @testSingleExtension 17 // CHECK-SAME: () #2 { 18 __attribute__((target("arch=+zbb"))) void testSingleExtension() {} 19 // CHECK-LABEL: define dso_local void @testMultiExtension 20 // CHECK-SAME: () #3 { 21 __attribute__((target("arch=+zbb,+v,+zicond"))) void testMultiExtension() {} 22 // CHECK-LABEL: define dso_local void @testFullArch 23 // CHECK-SAME: () #4 { 24 __attribute__((target("arch=rv64gc_zbb"))) void testFullArch() {} 25 // CHECK-LABEL: define dso_local void @testFullArchButSmallThanCmdArch 26 // CHECK-SAME: () #5 { 27 __attribute__((target("arch=rv64im"))) void testFullArchButSmallThanCmdArch() {} 28 // CHECK-LABEL: define dso_local void @testAttrArchAndAttrCpu 29 // CHECK-SAME: () #6 { 30 __attribute__((target("cpu=sifive-u54;arch=+zbb"))) void 31 testAttrArchAndAttrCpu() {} 32 // CHECK-LABEL: define dso_local void @testAttrFullArchAndAttrCpu 33 // CHECK-SAME: () #7 { 34 __attribute__((target("cpu=sifive-u54;arch=rv64im"))) void 35 testAttrFullArchAndAttrCpu() {} 36 // CHECK-LABEL: define dso_local void @testAttrCpuOnly 37 // CHECK-SAME: () #8 { 38 __attribute__((target("cpu=sifive-u54"))) void testAttrCpuOnly() {} 39 40 __attribute__((target("arch=+zve32x"))) 41 void test_builtin_w_zve32x() { 42 // CHECK-LABEL: test_builtin_w_zve32x 43 // CHECK-SAME: #9 44 __riscv_vsetvl_e8m8(1); 45 } 46 47 __attribute__((target("arch=+zve32x"))) 48 void test_rvv_i32_type_w_zve32x() { 49 // CHECK-LABEL: test_rvv_i32_type_w_zve32x 50 // CHECK-SAME: #9 51 vint32m1_t v; 52 } 53 54 __attribute__((target("arch=+zve32f"))) 55 void test_rvv_f32_type_w_zve32f() { 56 // CHECK-LABEL: test_rvv_f32_type_w_zve32f 57 // CHECK-SAME: #11 58 vfloat32m1_t v; 59 } 60 61 __attribute__((target("arch=+zve64d"))) 62 void test_rvv_f64_type_w_zve64d() { 63 // CHECK-LABEL: test_rvv_f64_type_w_zve64d 64 // CHECK-SAME: #12 65 vfloat64m1_t v; 66 } 67 68 //. 69 // CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zifencei,+zmmul,-relax,-zbb,-zfa" } 70 // CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" } 71 // CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa" } 72 // CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" } 73 // Make sure we append negative features if we override the arch 74 // CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } 75 // CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } 76 // CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa" } 77 // CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } 78 // CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } 79 // CHECK: attributes #9 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa" } 80 // CHECK: attributes #11 = { {{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa" } 81 // CHECK: attributes #12 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa" } 82