1 // REQUIRES: powerpc-registered-target
2 // RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
3 // RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s \
4 // RUN: -check-prefixes=PPC64,CHECK
5 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
6 // RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s \
7 // RUN: -check-prefixes=PPC64,CHECK
8 // RUN: %clang_cc1 -triple powerpc-unknown-aix \
9 // RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
10 // RUN: %clang_cc1 -triple powerpc64-unknown-aix \
11 // RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
12
13 extern unsigned int ui;
14 extern unsigned long long ull;
15
16 #ifdef __PPC64__
test_builtin_ppc_rldimi()17 void test_builtin_ppc_rldimi() {
18 // PPC64-LABEL: test_builtin_ppc_rldimi
19 // PPC64: %res = alloca i64, align 8
20 // PPC64-NEXT: [[RA:%[0-9]+]] = load i64, ptr @ull, align 8
21 // PPC64-NEXT: [[RB:%[0-9]+]] = load i64, ptr @ull, align 8
22 // PPC64-NEXT: [[RC:%[0-9]+]] = call i64 @llvm.ppc.rldimi(i64 [[RA]], i64 [[RB]], i32 63, i64 72057593769492480)
23 // PPC64-NEXT: store i64 [[RC]], ptr %res, align 8
24 // PPC64-NEXT: ret void
25
26 /*shift = 63, mask = 0x00FFFFFFF0000000 = 72057593769492480, ~mask = 0xFF0000000FFFFFFF = -72057593769492481*/
27 unsigned long long res = __builtin_ppc_rldimi(ull, ull, 63, 0x00FFFFFFF0000000);
28 }
29 #endif
30
test_builtin_ppc_rlwimi()31 void test_builtin_ppc_rlwimi() {
32 // CHECK-LABEL: test_builtin_ppc_rlwimi
33 // CHECK: %res = alloca i32, align 4
34 // CHECK-NEXT: [[RA:%[0-9]+]] = load i32, ptr @ui, align 4
35 // CHECK-NEXT: [[RB:%[0-9]+]] = load i32, ptr @ui, align 4
36 // CHECK-NEXT: [[RC:%[0-9]+]] = call i32 @llvm.ppc.rlwimi(i32 [[RA]], i32 [[RB]], i32 31, i32 16776960)
37 // CHECK-NEXT: store i32 [[RC]], ptr %res, align 4
38 // CHECK-NEXT: ret void
39
40 /*shift = 31, mask = 0xFFFF00 = 16776960, ~mask = 0xFFFFFFFFFF0000FF = -16776961*/
41 unsigned int res = __builtin_ppc_rlwimi(ui, ui, 31, 0xFFFF00);
42 }
43
test_builtin_ppc_rlwnm()44 void test_builtin_ppc_rlwnm() {
45 // CHECK-LABEL: test_builtin_ppc_rlwnm
46 // CHECK: %res = alloca i32, align 4
47 // CHECK-NEXT: [[RA:%[0-9]+]] = load i32, ptr @ui, align 4
48 // CHECK-NEXT: [[RB:%[0-9]+]] = call i32 @llvm.ppc.rlwnm(i32 [[RA]], i32 31, i32 511)
49 // CHECK-NEXT: store i32 [[RB]], ptr %res, align 4
50 // CHECK-NEXT: ret void
51
52 /*shift = 31, mask = 0x1FF = 511*/
53 unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
54 }
55
test_builtin_ppc_rlwnm2(unsigned int shift)56 void test_builtin_ppc_rlwnm2(unsigned int shift) {
57 // CHECK-LABEL: test_builtin_ppc_rlwnm2
58 // CHECK: %shift.addr = alloca i32, align 4
59 // CHECK-NEXT: %res = alloca i32, align 4
60 // CHECK-NEXT: store i32 %shift, ptr %shift.addr, align 4
61 // CHECK-NEXT: [[RA:%[0-9]+]] = load i32, ptr @ui, align 4
62 // CHECK-NEXT: [[RB:%[0-9]+]] = load i32, ptr %shift.addr, align 4
63 // CHECK-NEXT: [[RC:%[0-9]+]] = call i32 @llvm.ppc.rlwnm(i32 [[RA]], i32 [[RB]], i32 511)
64 // CHECK-NEXT: store i32 [[RC]], ptr %res, align 4
65 // CHECK-NEXT: ret void
66
67 /*mask = 0x1FF = 511*/
68 unsigned int res = __builtin_ppc_rlwnm(ui, shift, 0x1FF);
69 }
70
71 // CHECK-LABEL: @testrotatel4(
72 // CHECK: [[TMP:%.*]] = call i32 @llvm.fshl.i32(i32 {{%.*}}, i32 {{%.*}}, i32 {{%.*}})
73 // CHECK-NEXT: ret i32 [[TMP]]
74 //
testrotatel4(unsigned int rs,unsigned int shift)75 unsigned int testrotatel4(unsigned int rs, unsigned int shift) {
76 return __rotatel4(rs, shift);
77 }
78
79 // CHECK-LABEL: @testrotatel8(
80 // CHECK: [[TMP:%.*]] = call i64 @llvm.fshl.i64(i64 {{%.*}}, i64 {{%.*}}, i64 {{%.*}})
81 // CHECK-NEXT: ret i64 [[TMP]]
82 //
testrotatel8(unsigned long long rs,unsigned long long shift)83 unsigned long long testrotatel8(unsigned long long rs, unsigned long long shift) {
84 return __rotatel8(rs, shift);
85 }
86
87 // CHECK-LABEL: @testrdlam(
88 // CHECK: [[TMP0:%.*]] = call i64 @llvm.fshl.i64(i64 {{%.*}}, i64 {{%.*}}, i64 {{%.*}})
89 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 7
90 // CHECK-NEXT: ret i64 [[TMP1]]
91 //
testrdlam(unsigned long long rs,unsigned int shift)92 unsigned long long testrdlam(unsigned long long rs, unsigned int shift) {
93 // The third parameter is a mask that must be a constant that represents a
94 // contiguous bit field.
95 return __rdlam(rs, shift, 7);
96 }
97