1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // RUN: %clang_cc1 -triple loongarch32 -O2 -emit-llvm %s -o - | FileCheck %s
3 // RUN: %clang_cc1 -triple loongarch64 -O2 -emit-llvm %s -o - | FileCheck %s
4
5 /// Test LoongArch specific operand modifiers (i.e. operand codes).
6
7 // CHECK-LABEL: @test_z_zero(
8 // CHECK-NEXT: entry:
9 // CHECK-NEXT: [[TMP0:%.*]] = tail call i32 asm sideeffect "add.w $0, $1, ${2:z}", "=r,r,ri"(i32 [[A:%.*]], i32 0) #[[ATTR1:[0-9]+]], !srcloc !2
10 // CHECK-NEXT: ret void
11 //
test_z_zero(int a)12 void test_z_zero(int a) {
13 int tmp;
14 asm volatile ("add.w %0, %1, %z2" : "=r" (tmp) : "r" (a), "ri" (0));
15 }
16
17 // CHECK-LABEL: @test_z_nonzero(
18 // CHECK-NEXT: entry:
19 // CHECK-NEXT: [[TMP0:%.*]] = tail call i32 asm sideeffect "add.w $0, $1, ${2:z}", "=r,r,ri"(i32 [[A:%.*]], i32 1) #[[ATTR1]], !srcloc !3
20 // CHECK-NEXT: ret void
21 //
test_z_nonzero(int a)22 void test_z_nonzero(int a) {
23 int tmp;
24 asm volatile ("add.w %0, %1, %z2" : "=r" (tmp) : "r" (a), "ri" (1));
25 }
26