1.. title:: clang-tidy - altera-kernel-name-restriction 2 3altera-kernel-name-restriction 4============================== 5 6Finds kernel files and include directives whose filename is `kernel.cl`, 7`Verilog.cl`, or `VHDL.cl`. The check is case insensitive. 8 9Such kernel file names cause the offline compiler to generate intermediate 10design files that have the same names as certain internal files, which 11leads to a compilation error. 12 13Based on the `Guidelines for Naming the Kernel` section in the 14`Intel FPGA SDK for OpenCL Pro Edition: Programming Guide 15<https://www.intel.com/content/www/us/en/programmable/documentation/mwh1391807965224.html#ewa1412973930963>`_. 16