1;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2; Copyright(c) 2011-2016 Intel Corporation All rights reserved. 3; 4; Redistribution and use in source and binary forms, with or without 5; modification, are permitted provided that the following conditions 6; are met: 7; * Redistributions of source code must retain the above copyright 8; notice, this list of conditions and the following disclaimer. 9; * Redistributions in binary form must reproduce the above copyright 10; notice, this list of conditions and the following disclaimer in 11; the documentation and/or other materials provided with the 12; distribution. 13; * Neither the name of Intel Corporation nor the names of its 14; contributors may be used to endorse or promote products derived 15; from this software without specific prior written permission. 16; 17; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 29 30%include "reg_sizes.asm" 31%include "multibinary.asm" 32default rel 33[bits 64] 34 35; declare the L3 ctx level symbols (these will then call the appropriate 36; L2 symbols) 37extern _sha256_ctx_mgr_init_sse 38extern _sha256_ctx_mgr_submit_sse 39extern _sha256_ctx_mgr_flush_sse 40 41extern _sha256_ctx_mgr_init_avx 42extern _sha256_ctx_mgr_submit_avx 43extern _sha256_ctx_mgr_flush_avx 44 45extern _sha256_ctx_mgr_init_avx2 46extern _sha256_ctx_mgr_submit_avx2 47extern _sha256_ctx_mgr_flush_avx2 48 49extern _sha256_ctx_mgr_init_base 50extern _sha256_ctx_mgr_submit_base 51extern _sha256_ctx_mgr_flush_base 52 53extern _sha256_ctx_mgr_init_avx512 54extern _sha256_ctx_mgr_submit_avx512 55extern _sha256_ctx_mgr_flush_avx512 56 57extern _sha256_ctx_mgr_init_sse_ni 58extern _sha256_ctx_mgr_submit_sse_ni 59extern _sha256_ctx_mgr_flush_sse_ni 60 61extern _sha256_ctx_mgr_init_avx512_ni 62extern _sha256_ctx_mgr_submit_avx512_ni 63extern _sha256_ctx_mgr_flush_avx512_ni 64 65;;; *_mbinit are initial values for *_dispatched; is updated on first call. 66;;; Therefore, *_dispatch_init is only executed on first call. 67 68; Initialise symbols 69mbin_interface _sha256_ctx_mgr_init 70mbin_interface _sha256_ctx_mgr_submit 71mbin_interface _sha256_ctx_mgr_flush 72 73mbin_dispatch_base_to_avx512_shani _sha256_ctx_mgr_init, _sha256_ctx_mgr_init_base, \ 74 _sha256_ctx_mgr_init_sse, _sha256_ctx_mgr_init_avx, _sha256_ctx_mgr_init_avx2, \ 75 _sha256_ctx_mgr_init_avx512, _sha256_ctx_mgr_init_sse_ni, _sha256_ctx_mgr_init_avx512_ni 76mbin_dispatch_base_to_avx512_shani _sha256_ctx_mgr_submit, _sha256_ctx_mgr_submit_base, \ 77 _sha256_ctx_mgr_submit_sse, _sha256_ctx_mgr_submit_avx, _sha256_ctx_mgr_submit_avx2, \ 78 _sha256_ctx_mgr_submit_avx512, _sha256_ctx_mgr_submit_sse_ni, _sha256_ctx_mgr_submit_avx512_ni 79mbin_dispatch_base_to_avx512_shani _sha256_ctx_mgr_flush, _sha256_ctx_mgr_flush_base, \ 80 _sha256_ctx_mgr_flush_sse, _sha256_ctx_mgr_flush_avx, _sha256_ctx_mgr_flush_avx2, \ 81 _sha256_ctx_mgr_flush_avx512, _sha256_ctx_mgr_flush_sse_ni, _sha256_ctx_mgr_flush_avx512_ni 82 83;;; func core, ver, snum 84slversion sha256_ctx_mgr_init, 00, 04, 0160 85slversion sha256_ctx_mgr_submit, 00, 04, 0161 86slversion sha256_ctx_mgr_flush, 00, 04, 0162 87