1;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2; Copyright(c) 2011-2016 Intel Corporation All rights reserved. 3; 4; Redistribution and use in source and binary forms, with or without 5; modification, are permitted provided that the following conditions 6; are met: 7; * Redistributions of source code must retain the above copyright 8; notice, this list of conditions and the following disclaimer. 9; * Redistributions in binary form must reproduce the above copyright 10; notice, this list of conditions and the following disclaimer in 11; the documentation and/or other materials provided with the 12; distribution. 13; * Neither the name of Intel Corporation nor the names of its 14; contributors may be used to endorse or promote products derived 15; from this software without specific prior written permission. 16; 17; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 29 30%include "sha256_job.asm" 31%include "memcpy.asm" 32%include "sha256_mb_mgr_datastruct.asm" 33%include "reg_sizes.asm" 34 35extern sha256_mb_x16_avx512 36 37[bits 64] 38default rel 39section .text 40 41%ifidn __OUTPUT_FORMAT__, elf64 42; Linux register definitions 43%define arg1 rdi ; rcx 44%define arg2 rsi ; rdx 45 46%define size_offset rcx ; rdi 47%define tmp2 rcx ; rdi 48 49%else 50; WINDOWS register definitions 51%define arg1 rcx 52%define arg2 rdx 53 54%define size_offset rdi 55%define tmp2 rdi 56 57%endif 58 59; Common definitions 60%define state arg1 61%define job arg2 62%define len2 arg2 63%define p2 arg2 64 65%define idx r8 66%define last_len r8 67%define p r11 68%define start_offset r11 69%define num_lanes_inuse r11 70 71%define unused_lanes rbx 72 73%define job_rax rax 74%define len rax 75 76%define lane rbp 77%define tmp3 rbp 78 79%define tmp r9 80 81%define lane_data r10 82 83 84; STACK_SPACE needs to be an odd multiple of 8 85%define STACK_SPACE 8*8 + 16*10 + 8 86 87; ISAL_SHA256_JOB* _sha256_mb_mgr_submit_avx512(ISAL_SHA256_MB_JOB_MGR *state, ISAL_SHA256_JOB *job) 88; arg 1 : rcx : state 89; arg 2 : rdx : job 90mk_global _sha256_mb_mgr_submit_avx512, function, internal 91_sha256_mb_mgr_submit_avx512: 92 endbranch 93 94 sub rsp, STACK_SPACE 95 mov [rsp + 8*0], rbx 96 mov [rsp + 8*3], rbp 97 mov [rsp + 8*4], r12 98 mov [rsp + 8*5], r13 99 mov [rsp + 8*6], r14 100 mov [rsp + 8*7], r15 101%ifidn __OUTPUT_FORMAT__, win64 102 mov [rsp + 8*1], rsi 103 mov [rsp + 8*2], rdi 104 vmovdqa [rsp + 8*8 + 16*0], xmm6 105 vmovdqa [rsp + 8*8 + 16*1], xmm7 106 vmovdqa [rsp + 8*8 + 16*2], xmm8 107 vmovdqa [rsp + 8*8 + 16*3], xmm9 108 vmovdqa [rsp + 8*8 + 16*4], xmm10 109 vmovdqa [rsp + 8*8 + 16*5], xmm11 110 vmovdqa [rsp + 8*8 + 16*6], xmm12 111 vmovdqa [rsp + 8*8 + 16*7], xmm13 112 vmovdqa [rsp + 8*8 + 16*8], xmm14 113 vmovdqa [rsp + 8*8 + 16*9], xmm15 114%endif 115 mov unused_lanes, [state + _unused_lanes] 116 mov lane, unused_lanes 117 and lane, 0xF 118 shr unused_lanes, 4 119 imul lane_data, lane, _LANE_DATA_size 120 mov dword [job + _status], ISAL_STS_BEING_PROCESSED 121 lea lane_data, [state + _ldata + lane_data] 122 mov [state + _unused_lanes], unused_lanes 123 mov DWORD(len), [job + _len] 124 125 shl len, 4 126 or len, lane 127 mov [state + _lens + 4*lane], DWORD(len) 128 129 mov [lane_data + _job_in_lane], job 130 131 ; Load digest words from result_digest 132 vmovdqu xmm0, [job + _result_digest + 0*16] 133 vmovdqu xmm1, [job + _result_digest + 1*16] 134 vmovd [state + _args_digest + 4*lane + 0*4*16], xmm0 135 vpextrd [state + _args_digest + 4*lane + 1*4*16], xmm0, 1 136 vpextrd [state + _args_digest + 4*lane + 2*4*16], xmm0, 2 137 vpextrd [state + _args_digest + 4*lane + 3*4*16], xmm0, 3 138 vmovd [state + _args_digest + 4*lane + 4*4*16], xmm1 139 vpextrd [state + _args_digest + 4*lane + 5*4*16], xmm1, 1 140 vpextrd [state + _args_digest + 4*lane + 6*4*16], xmm1, 2 141 vpextrd [state + _args_digest + 4*lane + 7*4*16], xmm1, 3 142 143 144 mov p, [job + _buffer] 145 mov [state + _args_data_ptr + 8*lane], p 146 147 mov DWORD(num_lanes_inuse), [state + _num_lanes_inuse] 148 add num_lanes_inuse, 1 149 mov [state + _num_lanes_inuse], DWORD(num_lanes_inuse) 150 cmp num_lanes_inuse, 16 151 jne return_null 152 153start_loop: 154 ; Find min length, ymm0 holds ahead 8, ymm1 holds rear 8 155 vmovdqu ymm0, [state + _lens + 0*32] 156 vmovdqu ymm1, [state + _lens + 1*32] 157 158 vpminud ymm2, ymm0, ymm1 ; ymm2 has {H1,G1,F1,E1,D1,C1,B1,A1} 159 vpalignr ymm3, ymm3, ymm2, 8 ; ymm3 has {x,x,H1,G1,x,x,D1,C1} 160 vpminud ymm2, ymm2, ymm3 ; ymm2 has {x,x,H2,G2,x,x,D2,C2} 161 vpalignr ymm3, ymm3, ymm2, 4 ; ymm3 has {x,x, x,H2,x,x, x,D2} 162 vpminud ymm2, ymm2, ymm3 ; ymm2 has {x,x, x,G3,x,x, x,C3} 163 vperm2i128 ymm3, ymm2, ymm2, 1 ; ymm3 has {x,x, x, x,x,x, x,C3} 164 vpminud ymm2, ymm2, ymm3 ; ymm2 has min value in low dword 165 166 vmovd DWORD(idx), xmm2 167 mov len2, idx 168 and idx, 0xF 169 shr len2, 4 170 jz len_is_0 171 172 vpand ymm2, ymm2, [rel clear_low_nibble] 173 vpshufd ymm2, ymm2, 0 174 175 vpsubd ymm0, ymm0, ymm2 176 vpsubd ymm1, ymm1, ymm2 177 178 vmovdqu [state + _lens + 0*32], ymm0 179 vmovdqu [state + _lens + 1*32], ymm1 180 181 182 183 ; "state" and "args" are the same address, arg1 184 ; len is arg2 185 call sha256_mb_x16_avx512 186 187 ; state and idx are intact 188 189len_is_0: 190 ; process completed job "idx" 191 imul lane_data, idx, _LANE_DATA_size 192 lea lane_data, [state + _ldata + lane_data] 193 194 mov job_rax, [lane_data + _job_in_lane] 195 mov unused_lanes, [state + _unused_lanes] 196 mov qword [lane_data + _job_in_lane], 0 197 mov dword [job_rax + _status], ISAL_STS_COMPLETED 198 shl unused_lanes, 4 199 or unused_lanes, idx 200 mov [state + _unused_lanes], unused_lanes 201 202 mov DWORD(num_lanes_inuse), [state + _num_lanes_inuse] 203 sub num_lanes_inuse, 1 204 mov [state + _num_lanes_inuse], DWORD(num_lanes_inuse) 205 vmovd xmm0, [state + _args_digest + 4*idx + 0*4*16] 206 vpinsrd xmm0, [state + _args_digest + 4*idx + 1*4*16], 1 207 vpinsrd xmm0, [state + _args_digest + 4*idx + 2*4*16], 2 208 vpinsrd xmm0, [state + _args_digest + 4*idx + 3*4*16], 3 209 vmovd xmm1, [state + _args_digest + 4*idx + 4*4*16] 210 vpinsrd xmm1, [state + _args_digest + 4*idx + 5*4*16], 1 211 vpinsrd xmm1, [state + _args_digest + 4*idx + 6*4*16], 2 212 vpinsrd xmm1, [state + _args_digest + 4*idx + 7*4*16], 3 213 214 vmovdqa [job_rax + _result_digest + 0*16], xmm0 215 vmovdqa [job_rax + _result_digest + 1*16], xmm1 216 217return: 218 219%ifidn __OUTPUT_FORMAT__, win64 220 vmovdqa xmm6, [rsp + 8*8 + 16*0] 221 vmovdqa xmm7, [rsp + 8*8 + 16*1] 222 vmovdqa xmm8, [rsp + 8*8 + 16*2] 223 vmovdqa xmm9, [rsp + 8*8 + 16*3] 224 vmovdqa xmm10, [rsp + 8*8 + 16*4] 225 vmovdqa xmm11, [rsp + 8*8 + 16*5] 226 vmovdqa xmm12, [rsp + 8*8 + 16*6] 227 vmovdqa xmm13, [rsp + 8*8 + 16*7] 228 vmovdqa xmm14, [rsp + 8*8 + 16*8] 229 vmovdqa xmm15, [rsp + 8*8 + 16*9] 230 mov rsi, [rsp + 8*1] 231 mov rdi, [rsp + 8*2] 232%endif 233 mov rbx, [rsp + 8*0] 234 mov rbp, [rsp + 8*3] 235 mov r12, [rsp + 8*4] 236 mov r13, [rsp + 8*5] 237 mov r14, [rsp + 8*6] 238 mov r15, [rsp + 8*7] 239 add rsp, STACK_SPACE 240 241 ret 242 243return_null: 244 xor job_rax, job_rax 245 jmp return 246 247section .data align=32 248 249align 32 250clear_low_nibble: 251 dq 0x00000000FFFFFFF0, 0x0000000000000000 252 dq 0x00000000FFFFFFF0, 0x0000000000000000 253