1 /**********************************************************************
2 Copyright(c) 2011-2016 Intel Corporation All rights reserved.
3
4 Redistribution and use in source and binary forms, with or without
5 modification, are permitted provided that the following conditions
6 are met:
7 * Redistributions of source code must retain the above copyright
8 notice, this list of conditions and the following disclaimer.
9 * Redistributions in binary form must reproduce the above copyright
10 notice, this list of conditions and the following disclaimer in
11 the documentation and/or other materials provided with the
12 distribution.
13 * Neither the name of Intel Corporation nor the names of its
14 contributors may be used to endorse or promote products derived
15 from this software without specific prior written permission.
16
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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23 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 **********************************************************************/
29
30 #if defined(__clang__)
31 #pragma clang attribute push(__attribute__((target("avx2"))), apply_to = function)
32 #elif defined(__ICC)
33 #pragma intel optimization_parameter target_arch = AVX2
34 #elif defined(__ICL)
35 #pragma[intel] optimization_parameter target_arch = AVX2
36 #elif (__GNUC__ >= 5)
37 #pragma GCC target("avx2")
38 #endif
39
40 #include "sha256_mb_internal.h"
41 #include "memcpy_inline.h"
42 #include "endian_helper.h"
43
44 #ifdef _MSC_VER
45 #include <intrin.h>
46 #define inline __inline
47 #endif
48
49 static inline void
50 hash_init_digest(ISAL_SHA256_WORD_T *digest);
51 static inline uint32_t
52 hash_pad(uint8_t padblock[ISAL_SHA256_BLOCK_SIZE * 2], uint64_t total_len);
53 static ISAL_SHA256_HASH_CTX *
54 sha256_ctx_mgr_resubmit(ISAL_SHA256_HASH_CTX_MGR *mgr, ISAL_SHA256_HASH_CTX *ctx);
55
56 void
_sha256_ctx_mgr_init_avx512(ISAL_SHA256_HASH_CTX_MGR * mgr)57 _sha256_ctx_mgr_init_avx512(ISAL_SHA256_HASH_CTX_MGR *mgr)
58 {
59 _sha256_mb_mgr_init_avx512(&mgr->mgr);
60 }
61
62 ISAL_SHA256_HASH_CTX *
_sha256_ctx_mgr_submit_avx512(ISAL_SHA256_HASH_CTX_MGR * mgr,ISAL_SHA256_HASH_CTX * ctx,const void * buffer,uint32_t len,ISAL_HASH_CTX_FLAG flags)63 _sha256_ctx_mgr_submit_avx512(ISAL_SHA256_HASH_CTX_MGR *mgr, ISAL_SHA256_HASH_CTX *ctx,
64 const void *buffer, uint32_t len, ISAL_HASH_CTX_FLAG flags)
65 {
66 if (flags & (~ISAL_HASH_ENTIRE)) {
67 // User should not pass anything other than FIRST, UPDATE, or LAST
68 ctx->error = ISAL_HASH_CTX_ERROR_INVALID_FLAGS;
69 return ctx;
70 }
71
72 if (ctx->status & ISAL_HASH_CTX_STS_PROCESSING) {
73 // Cannot submit to a currently processing job.
74 ctx->error = ISAL_HASH_CTX_ERROR_ALREADY_PROCESSING;
75 return ctx;
76 }
77
78 if ((ctx->status & ISAL_HASH_CTX_STS_COMPLETE) && !(flags & ISAL_HASH_FIRST)) {
79 // Cannot update a finished job.
80 ctx->error = ISAL_HASH_CTX_ERROR_ALREADY_COMPLETED;
81 return ctx;
82 }
83
84 if (flags & ISAL_HASH_FIRST) {
85 // Init digest
86 hash_init_digest(ctx->job.result_digest);
87
88 // Reset byte counter
89 ctx->total_length = 0;
90
91 // Clear extra blocks
92 ctx->partial_block_buffer_length = 0;
93 }
94 // If we made it here, there were no errors during this call to submit
95 ctx->error = ISAL_HASH_CTX_ERROR_NONE;
96
97 // Store buffer ptr info from user
98 ctx->incoming_buffer = buffer;
99 ctx->incoming_buffer_length = len;
100
101 // Store the user's request flags and mark this ctx as currently being processed.
102 ctx->status = (flags & ISAL_HASH_LAST) ? (ISAL_HASH_CTX_STS) (ISAL_HASH_CTX_STS_PROCESSING |
103 ISAL_HASH_CTX_STS_LAST)
104 : ISAL_HASH_CTX_STS_PROCESSING;
105
106 // Advance byte counter
107 ctx->total_length += len;
108
109 // If there is anything currently buffered in the extra blocks, append to it until it
110 // contains a whole block. Or if the user's buffer contains less than a whole block, append
111 // as much as possible to the extra block.
112 if ((ctx->partial_block_buffer_length) | (len < ISAL_SHA256_BLOCK_SIZE)) {
113 // Compute how many bytes to copy from user buffer into extra block
114 uint32_t copy_len = ISAL_SHA256_BLOCK_SIZE - ctx->partial_block_buffer_length;
115 if (len < copy_len)
116 copy_len = len;
117
118 if (copy_len) {
119 // Copy and update relevant pointers and counters
120 memcpy_varlen(&ctx->partial_block_buffer[ctx->partial_block_buffer_length],
121 buffer, copy_len);
122
123 ctx->partial_block_buffer_length += copy_len;
124 ctx->incoming_buffer = (const void *) ((const char *) buffer + copy_len);
125 ctx->incoming_buffer_length = len - copy_len;
126 }
127 // The extra block should never contain more than 1 block here
128 assert(ctx->partial_block_buffer_length <= ISAL_SHA256_BLOCK_SIZE);
129
130 // If the extra block buffer contains exactly 1 block, it can be hashed.
131 if (ctx->partial_block_buffer_length >= ISAL_SHA256_BLOCK_SIZE) {
132 ctx->partial_block_buffer_length = 0;
133
134 ctx->job.buffer = ctx->partial_block_buffer;
135 ctx->job.len = 1;
136 ctx = (ISAL_SHA256_HASH_CTX *) _sha256_mb_mgr_submit_avx512(&mgr->mgr,
137 &ctx->job);
138 }
139 }
140
141 return sha256_ctx_mgr_resubmit(mgr, ctx);
142 }
143
144 ISAL_SHA256_HASH_CTX *
_sha256_ctx_mgr_flush_avx512(ISAL_SHA256_HASH_CTX_MGR * mgr)145 _sha256_ctx_mgr_flush_avx512(ISAL_SHA256_HASH_CTX_MGR *mgr)
146 {
147 ISAL_SHA256_HASH_CTX *ctx;
148
149 while (1) {
150 ctx = (ISAL_SHA256_HASH_CTX *) _sha256_mb_mgr_flush_avx512(&mgr->mgr);
151
152 // If flush returned 0, there are no more jobs in flight.
153 if (!ctx)
154 return NULL;
155
156 // If flush returned a job, verify that it is safe to return to the user.
157 // If it is not ready, resubmit the job to finish processing.
158 ctx = sha256_ctx_mgr_resubmit(mgr, ctx);
159
160 // If sha256_ctx_mgr_resubmit returned a job, it is ready to be returned.
161 if (ctx)
162 return ctx;
163
164 // Otherwise, all jobs currently being managed by the ISAL_SHA256_HASH_CTX_MGR still
165 // need processing. Loop.
166 }
167 }
168
169 static ISAL_SHA256_HASH_CTX *
sha256_ctx_mgr_resubmit(ISAL_SHA256_HASH_CTX_MGR * mgr,ISAL_SHA256_HASH_CTX * ctx)170 sha256_ctx_mgr_resubmit(ISAL_SHA256_HASH_CTX_MGR *mgr, ISAL_SHA256_HASH_CTX *ctx)
171 {
172 while (ctx) {
173 if (ctx->status & ISAL_HASH_CTX_STS_COMPLETE) {
174 ctx->status = ISAL_HASH_CTX_STS_COMPLETE; // Clear PROCESSING bit
175 return ctx;
176 }
177 // If the extra blocks are empty, begin hashing what remains in the user's buffer.
178 if (ctx->partial_block_buffer_length == 0 && ctx->incoming_buffer_length) {
179 const void *buffer = ctx->incoming_buffer;
180 uint32_t len = ctx->incoming_buffer_length;
181
182 // Only entire blocks can be hashed. Copy remainder to extra blocks buffer.
183 uint32_t copy_len = len & (ISAL_SHA256_BLOCK_SIZE - 1);
184
185 if (copy_len) {
186 len -= copy_len;
187 memcpy_varlen(ctx->partial_block_buffer,
188 ((const char *) buffer + len), copy_len);
189 ctx->partial_block_buffer_length = copy_len;
190 }
191
192 ctx->incoming_buffer_length = 0;
193
194 // len should be a multiple of the block size now
195 assert((len % ISAL_SHA256_BLOCK_SIZE) == 0);
196
197 // Set len to the number of blocks to be hashed in the user's buffer
198 len >>= ISAL_SHA256_LOG2_BLOCK_SIZE;
199
200 if (len) {
201 ctx->job.buffer = (uint8_t *) buffer;
202 ctx->job.len = len;
203 ctx = (ISAL_SHA256_HASH_CTX *) _sha256_mb_mgr_submit_avx512(
204 &mgr->mgr, &ctx->job);
205 continue;
206 }
207 }
208 // If the extra blocks are not empty, then we are either on the last block(s)
209 // or we need more user input before continuing.
210 if (ctx->status & ISAL_HASH_CTX_STS_LAST) {
211 uint8_t *buf = ctx->partial_block_buffer;
212 uint32_t n_extra_blocks = hash_pad(buf, ctx->total_length);
213
214 ctx->status = (ISAL_HASH_CTX_STS) (ISAL_HASH_CTX_STS_PROCESSING |
215 ISAL_HASH_CTX_STS_COMPLETE);
216 ctx->job.buffer = buf;
217 ctx->job.len = (uint32_t) n_extra_blocks;
218 ctx = (ISAL_SHA256_HASH_CTX *) _sha256_mb_mgr_submit_avx512(&mgr->mgr,
219 &ctx->job);
220 continue;
221 }
222
223 if (ctx)
224 ctx->status = ISAL_HASH_CTX_STS_IDLE;
225 return ctx;
226 }
227
228 return NULL;
229 }
230
231 static inline void
hash_init_digest(ISAL_SHA256_WORD_T * digest)232 hash_init_digest(ISAL_SHA256_WORD_T *digest)
233 {
234 static const ISAL_SHA256_WORD_T hash_initial_digest[ISAL_SHA256_DIGEST_NWORDS] = {
235 ISAL_SHA256_INITIAL_DIGEST
236 };
237 memcpy_fixedlen(digest, hash_initial_digest, sizeof(hash_initial_digest));
238 }
239
240 static inline uint32_t
hash_pad(uint8_t padblock[ISAL_SHA256_BLOCK_SIZE * 2],uint64_t total_len)241 hash_pad(uint8_t padblock[ISAL_SHA256_BLOCK_SIZE * 2], uint64_t total_len)
242 {
243 uint32_t i = (uint32_t) (total_len & (ISAL_SHA256_BLOCK_SIZE - 1));
244
245 memclr_fixedlen(&padblock[i], ISAL_SHA256_BLOCK_SIZE);
246 padblock[i] = 0x80;
247
248 // Move i to the end of either 1st or 2nd extra block depending on length
249 i += ((ISAL_SHA256_BLOCK_SIZE - 1) &
250 (0 - (total_len + ISAL_SHA256_PADLENGTHFIELD_SIZE + 1))) +
251 1 + ISAL_SHA256_PADLENGTHFIELD_SIZE;
252
253 #if ISAL_SHA256_PADLENGTHFIELD_SIZE == 16
254 *((uint64_t *) &padblock[i - 16]) = 0;
255 #endif
256
257 *((uint64_t *) &padblock[i - 8]) = to_be64((uint64_t) total_len << 3);
258
259 return i >> ISAL_SHA256_LOG2_BLOCK_SIZE; // Number of extra blocks to hash
260 }
261
262 struct slver {
263 uint16_t snum;
264 uint8_t ver;
265 uint8_t core;
266 };
267 struct slver _sha256_ctx_mgr_init_avx512_slver_0600015a;
268 struct slver _sha256_ctx_mgr_init_avx512_slver = { 0x015a, 0x00, 0x06 };
269
270 struct slver _sha256_ctx_mgr_submit_avx512_slver_0600015b;
271 struct slver _sha256_ctx_mgr_submit_avx512_slver = { 0x015b, 0x00, 0x06 };
272
273 struct slver _sha256_ctx_mgr_flush_avx512_slver_0600015c;
274 struct slver _sha256_ctx_mgr_flush_avx512_slver = { 0x015c, 0x00, 0x06 };
275
276 #if defined(__clang__)
277 #pragma clang attribute pop
278 #endif
279