1;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2; Copyright(c) 2011-2016 Intel Corporation All rights reserved. 3; 4; Redistribution and use in source and binary forms, with or without 5; modification, are permitted provided that the following conditions 6; are met: 7; * Redistributions of source code must retain the above copyright 8; notice, this list of conditions and the following disclaimer. 9; * Redistributions in binary form must reproduce the above copyright 10; notice, this list of conditions and the following disclaimer in 11; the documentation and/or other materials provided with the 12; distribution. 13; * Neither the name of Intel Corporation nor the names of its 14; contributors may be used to endorse or promote products derived 15; from this software without specific prior written permission. 16; 17; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 29 30%include "sha1_job.asm" 31%include "sha1_mb_mgr_datastruct.asm" 32 33%include "reg_sizes.asm" 34 35extern sha1_mb_x4_sse 36 37[bits 64] 38default rel 39section .text 40 41%ifidn __OUTPUT_FORMAT__, win64 42; WINDOWS register definitions 43%define arg1 rcx 44%define arg2 rdx 45 46; idx needs to be other than ARG2, rax, r8-r11 47%define last_len rsi 48%define idx rsi 49 50%define size_offset rdi 51%define tmp2 rdi 52 53%else 54; LINUX register definitions 55%define arg1 rdi 56%define arg2 rsi 57 58; idx needs to be other than ARG2, rax, r8-r11 59%define last_len rdx 60%define idx rdx 61 62%define size_offset rcx 63%define tmp2 rcx 64 65%endif 66 67; Common definitions 68%define state arg1 69%define job arg2 70%define len2 arg2 71%define p2 arg2 72 73%define p r11 74%define start_offset r11 75 76%define unused_lanes rbx 77 78%define job_rax rax 79%define len rax 80 81%define lane rbp 82%define tmp3 rbp 83%define lens3 rbp 84 85%define extra_blocks r8 86%define lens0 r8 87 88%define tmp r9 89%define lens1 r9 90 91%define lane_data r10 92%define lens2 r10 93 94; STACK_SPACE needs to be an odd multiple of 8 95%define STACK_SPACE 8*4 + 16*10 + 8 96 97; SHA1_JOB* _sha1_mb_mgr_submit_sse(SHA1_MB_JOB_MGR *state, SHA1_JOB *job) 98; arg 1 : rcx : state 99; arg 2 : rdx : job 100mk_global _sha1_mb_mgr_submit_sse, function, internal 101_sha1_mb_mgr_submit_sse: 102 endbranch 103 104 sub rsp, STACK_SPACE 105 mov [rsp + 8*0], rbx 106 mov [rsp + 8*3], rbp 107%ifidn __OUTPUT_FORMAT__, win64 108 mov [rsp + 8*1], rsi 109 mov [rsp + 8*2], rdi 110 movdqa [rsp + 8*4 + 16*0], xmm6 111 movdqa [rsp + 8*4 + 16*1], xmm7 112 movdqa [rsp + 8*4 + 16*2], xmm8 113 movdqa [rsp + 8*4 + 16*3], xmm9 114 movdqa [rsp + 8*4 + 16*4], xmm10 115 movdqa [rsp + 8*4 + 16*5], xmm11 116 movdqa [rsp + 8*4 + 16*6], xmm12 117 movdqa [rsp + 8*4 + 16*7], xmm13 118 movdqa [rsp + 8*4 + 16*8], xmm14 119 movdqa [rsp + 8*4 + 16*9], xmm15 120%endif 121 122 mov unused_lanes, [state + _unused_lanes] 123 movzx lane, BYTE(unused_lanes) 124 and lane, 0xF 125 shr unused_lanes, 4 126 imul lane_data, lane, _LANE_DATA_size 127 mov dword [job + _status], ISAL_STS_BEING_PROCESSED 128 lea lane_data, [state + _ldata + lane_data] 129 mov [state + _unused_lanes], unused_lanes 130 mov DWORD(len), [job + _len] 131 132 shl len, 4 133 or len, lane 134 135 mov [lane_data + _job_in_lane], job 136 mov [state + _lens + 4*lane], DWORD(len) 137 138 ; Load digest words from result_digest 139 movdqa xmm0, [job + _result_digest + 0*16] 140 mov DWORD(tmp), [job + _result_digest + 1*16] 141 movd [state + _args_digest + 4*lane + 0*16], xmm0 142 pextrd [state + _args_digest + 4*lane + 1*16], xmm0, 1 143 pextrd [state + _args_digest + 4*lane + 2*16], xmm0, 2 144 pextrd [state + _args_digest + 4*lane + 3*16], xmm0, 3 145 mov [state + _args_digest + 4*lane + 4*16], DWORD(tmp) 146 147 mov p, [job + _buffer] 148 mov [state + _args_data_ptr + 8*lane], p 149 150 add dword [state + _num_lanes_inuse], 1 151 cmp unused_lanes, 0xF 152 jne return_null 153 154start_loop: 155 ; Find min length 156 mov DWORD(lens0), [state + _lens + 0*4] 157 mov idx, lens0 158 mov DWORD(lens1), [state + _lens + 1*4] 159 cmp lens1, idx 160 cmovb idx, lens1 161 mov DWORD(lens2), [state + _lens + 2*4] 162 cmp lens2, idx 163 cmovb idx, lens2 164 mov DWORD(lens3), [state + _lens + 3*4] 165 cmp lens3, idx 166 cmovb idx, lens3 167 mov len2, idx 168 and idx, 0xF 169 and len2, ~0xF 170 jz len_is_0 171 172 sub lens0, len2 173 sub lens1, len2 174 sub lens2, len2 175 sub lens3, len2 176 shr len2, 4 177 mov [state + _lens + 0*4], DWORD(lens0) 178 mov [state + _lens + 1*4], DWORD(lens1) 179 mov [state + _lens + 2*4], DWORD(lens2) 180 mov [state + _lens + 3*4], DWORD(lens3) 181 182 ; "state" and "args" are the same address, arg1 183 ; len is arg2 184 call sha1_mb_x4_sse 185 ; state and idx are intact 186 187len_is_0: 188 ; process completed job "idx" 189 imul lane_data, idx, _LANE_DATA_size 190 lea lane_data, [state + _ldata + lane_data] 191 192 mov job_rax, [lane_data + _job_in_lane] 193 mov unused_lanes, [state + _unused_lanes] 194 mov qword [lane_data + _job_in_lane], 0 195 mov dword [job_rax + _status], ISAL_STS_COMPLETED 196 shl unused_lanes, 4 197 or unused_lanes, idx 198 mov [state + _unused_lanes], unused_lanes 199 200 sub dword [state + _num_lanes_inuse], 1 201 202 movd xmm0, [state + _args_digest + 4*idx + 0*16] 203 pinsrd xmm0, [state + _args_digest + 4*idx + 1*16], 1 204 pinsrd xmm0, [state + _args_digest + 4*idx + 2*16], 2 205 pinsrd xmm0, [state + _args_digest + 4*idx + 3*16], 3 206 mov DWORD(tmp), [state + _args_digest + 4*idx + 4*16] 207 208 movdqa [job_rax + _result_digest + 0*16], xmm0 209 mov [job_rax + _result_digest + 1*16], DWORD(tmp) 210 211return: 212 213%ifidn __OUTPUT_FORMAT__, win64 214 movdqa xmm6, [rsp + 8*4 + 16*0] 215 movdqa xmm7, [rsp + 8*4 + 16*1] 216 movdqa xmm8, [rsp + 8*4 + 16*2] 217 movdqa xmm9, [rsp + 8*4 + 16*3] 218 movdqa xmm10, [rsp + 8*4 + 16*4] 219 movdqa xmm11, [rsp + 8*4 + 16*5] 220 movdqa xmm12, [rsp + 8*4 + 16*6] 221 movdqa xmm13, [rsp + 8*4 + 16*7] 222 movdqa xmm14, [rsp + 8*4 + 16*8] 223 movdqa xmm15, [rsp + 8*4 + 16*9] 224 mov rsi, [rsp + 8*1] 225 mov rdi, [rsp + 8*2] 226%endif 227 mov rbx, [rsp + 8*0] 228 mov rbp, [rsp + 8*3] 229 add rsp, STACK_SPACE 230 231 ret 232 233return_null: 234 xor job_rax, job_rax 235 jmp return 236 237 238section .data align=16 239 240align 16 241H0: dd 0x67452301 242H1: dd 0xefcdab89 243H2: dd 0x98badcfe 244H3: dd 0x10325476 245H4: dd 0xc3d2e1f0 246 247