1;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2; Copyright(c) 2011-2016 Intel Corporation All rights reserved. 3; 4; Redistribution and use in source and binary forms, with or without 5; modification, are permitted provided that the following conditions 6; are met: 7; * Redistributions of source code must retain the above copyright 8; notice, this list of conditions and the following disclaimer. 9; * Redistributions in binary form must reproduce the above copyright 10; notice, this list of conditions and the following disclaimer in 11; the documentation and/or other materials provided with the 12; distribution. 13; * Neither the name of Intel Corporation nor the names of its 14; contributors may be used to endorse or promote products derived 15; from this software without specific prior written permission. 16; 17; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 29 30%include "sha1_job.asm" 31%include "sha1_mb_mgr_datastruct.asm" 32 33%include "reg_sizes.asm" 34 35extern sha1_mb_x4_sse 36extern sha1_opt_x1 37 38[bits 64] 39default rel 40section .text 41 42%ifidn __OUTPUT_FORMAT__, elf64 43; LINUX register definitions 44%define arg1 rdi ; rcx 45%define arg2 rsi ; rdx 46 47; idx needs to be other than ARG1, ARG2, rax, r8-r11 48%define idx rdx ; rsi 49%else 50; WINDOWS register definitions 51%define arg1 rcx 52%define arg2 rdx 53 54; idx needs to be other than ARG1, ARG2, rax, r8-r11 55%define idx rsi 56%endif 57 58; Common definitions 59%define state arg1 60%define job arg2 61%define len2 arg2 62 63%define unused_lanes rbx 64%define lane_data rbx 65%define tmp2 rbx 66 67%define job_rax rax 68%define tmp1 rax 69%define size_offset rax 70%define tmp rax 71%define start_offset rax 72 73%define tmp3 arg1 74 75%define extra_blocks arg2 76%define p arg2 77 78%define tmp4 r8 79%define lens0 r8 80 81%define lens1 r9 82%define lens2 r10 83%define lens3 r11 84 85 86; STACK_SPACE needs to be an odd multiple of 8 87_XMM_SAVE_SIZE equ 10*16 88_GPR_SAVE_SIZE equ 8*2 89_ALIGN_SIZE equ 8 90 91_XMM_SAVE equ 0 92_GPR_SAVE equ _XMM_SAVE + _XMM_SAVE_SIZE 93STACK_SPACE equ _GPR_SAVE + _GPR_SAVE_SIZE + _ALIGN_SIZE 94 95%define APPEND(a,b) a %+ b 96 97; SHA1_JOB* _sha1_mb_mgr_flush_sse(SHA1_MB_JOB_MGR *state) 98; arg 1 : rcx : state 99mk_global _sha1_mb_mgr_flush_sse, function, internal 100_sha1_mb_mgr_flush_sse: 101 endbranch 102 103 sub rsp, STACK_SPACE 104 mov [rsp + _GPR_SAVE + 8*0], rbx 105%ifidn __OUTPUT_FORMAT__, win64 106 mov [rsp + _GPR_SAVE + 8*1], rsi 107 movdqa [rsp + _XMM_SAVE + 16*0], xmm6 108 movdqa [rsp + _XMM_SAVE + 16*1], xmm7 109 movdqa [rsp + _XMM_SAVE + 16*2], xmm8 110 movdqa [rsp + _XMM_SAVE + 16*3], xmm9 111 movdqa [rsp + _XMM_SAVE + 16*4], xmm10 112 movdqa [rsp + _XMM_SAVE + 16*5], xmm11 113 movdqa [rsp + _XMM_SAVE + 16*6], xmm12 114 movdqa [rsp + _XMM_SAVE + 16*7], xmm13 115 movdqa [rsp + _XMM_SAVE + 16*8], xmm14 116 movdqa [rsp + _XMM_SAVE + 16*9], xmm15 117%endif 118 119 ; use num_lanes_inuse to judge all lanes are empty 120 cmp dword [state + _num_lanes_inuse], 0 121 jz return_null 122 123 ; find a lane with a non-null job 124 xor idx, idx 125 cmp qword [state + _ldata + 1 * _LANE_DATA_size + _job_in_lane], 0 126 cmovne idx, [one] 127 cmp qword [state + _ldata + 2 * _LANE_DATA_size + _job_in_lane], 0 128 cmovne idx, [two] 129 cmp qword [state + _ldata + 3 * _LANE_DATA_size + _job_in_lane], 0 130 cmovne idx, [three] 131 132 ; copy idx to empty lanes 133copy_lane_data: 134 mov tmp, [state + _args + _data_ptr + 8*idx] 135 136%assign I 0 137%rep 4 138 cmp qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0 139 jne APPEND(skip_,I) 140 mov [state + _args + _data_ptr + 8*I], tmp 141 mov dword [state + _lens + 4*I], 0xFFFFFFFF 142APPEND(skip_,I): 143%assign I (I+1) 144%endrep 145 146 ; Find min length 147 mov DWORD(lens0), [state + _lens + 0*4] 148 mov idx, lens0 149 mov DWORD(lens1), [state + _lens + 1*4] 150 cmp lens1, idx 151 cmovb idx, lens1 152 mov DWORD(lens2), [state + _lens + 2*4] 153 cmp lens2, idx 154 cmovb idx, lens2 155 mov DWORD(lens3), [state + _lens + 3*4] 156 cmp lens3, idx 157 cmovb idx, lens3 158 mov len2, idx 159 and idx, 0xF 160 and len2, ~0xF 161 jz len_is_0 162 163 ; compare with sha-sb threshold, if num_lanes_inuse <= threshold, using sb func 164 cmp dword [state + _num_lanes_inuse], SHA1_SB_THRESHOLD_SSE 165 ja mb_processing 166 167 ; lensN-len2=idx 168 shr len2, 4 169 mov [state + _lens + idx*4], DWORD(idx) 170 mov r10, idx 171 or r10, 0x1000 ; sse has 4 lanes *4, r10b is idx, r10b2 is 16 172 ; "state" and "args" are the same address, arg1 173 ; len is arg2, idx and nlane in r10 174 call sha1_opt_x1 175 ; state and idx are intact 176 jmp len_is_0 177 178mb_processing: 179 180 sub lens0, len2 181 sub lens1, len2 182 sub lens2, len2 183 sub lens3, len2 184 shr len2, 4 185 mov [state + _lens + 0*4], DWORD(lens0) 186 mov [state + _lens + 1*4], DWORD(lens1) 187 mov [state + _lens + 2*4], DWORD(lens2) 188 mov [state + _lens + 3*4], DWORD(lens3) 189 190 ; "state" and "args" are the same address, arg1 191 ; len is arg2 192 call sha1_mb_x4_sse 193 ; state and idx are intact 194 195len_is_0: 196 ; process completed job "idx" 197 imul lane_data, idx, _LANE_DATA_size 198 lea lane_data, [state + _ldata + lane_data] 199 200 mov job_rax, [lane_data + _job_in_lane] 201 mov qword [lane_data + _job_in_lane], 0 202 mov dword [job_rax + _status], ISAL_STS_COMPLETED 203 mov unused_lanes, [state + _unused_lanes] 204 shl unused_lanes, 4 205 or unused_lanes, idx 206 mov [state + _unused_lanes], unused_lanes 207 208 sub dword [state + _num_lanes_inuse], 1 209 210 movd xmm0, [state + _args_digest + 4*idx + 0*16] 211 pinsrd xmm0, [state + _args_digest + 4*idx + 1*16], 1 212 pinsrd xmm0, [state + _args_digest + 4*idx + 2*16], 2 213 pinsrd xmm0, [state + _args_digest + 4*idx + 3*16], 3 214 mov DWORD(tmp2), [state + _args_digest + 4*idx + 4*16] 215 216 movdqa [job_rax + _result_digest + 0*16], xmm0 217 mov [job_rax + _result_digest + 1*16], DWORD(tmp2) 218 219return: 220 221%ifidn __OUTPUT_FORMAT__, win64 222 movdqa xmm6, [rsp + _XMM_SAVE + 16*0] 223 movdqa xmm7, [rsp + _XMM_SAVE + 16*1] 224 movdqa xmm8, [rsp + _XMM_SAVE + 16*2] 225 movdqa xmm9, [rsp + _XMM_SAVE + 16*3] 226 movdqa xmm10, [rsp + _XMM_SAVE + 16*4] 227 movdqa xmm11, [rsp + _XMM_SAVE + 16*5] 228 movdqa xmm12, [rsp + _XMM_SAVE + 16*6] 229 movdqa xmm13, [rsp + _XMM_SAVE + 16*7] 230 movdqa xmm14, [rsp + _XMM_SAVE + 16*8] 231 movdqa xmm15, [rsp + _XMM_SAVE + 16*9] 232 mov rsi, [rsp + _GPR_SAVE + 8*1] 233%endif 234 mov rbx, [rsp + _GPR_SAVE + 8*0] 235 add rsp, STACK_SPACE 236 237 ret 238 239return_null: 240 xor job_rax, job_rax 241 jmp return 242 243section .data align=16 244 245align 16 246one: dq 1 247two: dq 2 248three: dq 3 249 250