1 #include "l.h" 2 3 #define X 99 4 5 Optab optab[] = 6 { 7 { ATEXT, C_LEXT, C_NONE, C_LCON, 0, 0, 0 }, 8 { ATEXT, C_LEXT, C_REG, C_LCON, 0, 0, 0 }, 9 10 { AMOVW, C_REG, C_NONE, C_REG, 1, 4, 0 }, 11 { AMOVV, C_REG, C_NONE, C_REG, 1, 4, 0 }, 12 { AMOVB, C_REG, C_NONE, C_REG, 12, 8, 0 }, 13 { AMOVBU, C_REG, C_NONE, C_REG, 13, 4, 0 }, 14 { AMOVWU, C_REG, C_NONE, C_REG, 14, 8, 0 }, 15 16 { ASUB, C_REG, C_REG, C_REG, 2, 4, 0 }, 17 { AADD, C_REG, C_REG, C_REG, 2, 4, 0 }, 18 { AAND, C_REG, C_REG, C_REG, 2, 4, 0 }, 19 { ASUB, C_REG, C_NONE, C_REG, 2, 4, 0 }, 20 { AADD, C_REG, C_NONE, C_REG, 2, 4, 0 }, 21 { AAND, C_REG, C_NONE, C_REG, 2, 4, 0 }, 22 23 { ASLL, C_REG, C_NONE, C_REG, 9, 4, 0 }, 24 { ASLL, C_REG, C_REG, C_REG, 9, 4, 0 }, 25 26 { AADDF, C_FREG, C_NONE, C_FREG, 32, 4, 0 }, 27 { AADDF, C_FREG, C_REG, C_FREG, 32, 4, 0 }, 28 { ACMPEQF, C_FREG, C_REG, C_NONE, 32, 4, 0 }, 29 { AABSF, C_FREG, C_NONE, C_FREG, 33, 4, 0 }, 30 { AMOVF, C_FREG, C_NONE, C_FREG, 33, 4, 0 }, 31 { AMOVD, C_FREG, C_NONE, C_FREG, 33, 4, 0 }, 32 33 { AMOVW, C_REG, C_NONE, C_SEXT, 7, 4, REGSB }, 34 { AMOVV, C_REG, C_NONE, C_SEXT, 7, 4, REGSB }, 35 { AMOVB, C_REG, C_NONE, C_SEXT, 7, 4, REGSB }, 36 { AMOVBU, C_REG, C_NONE, C_SEXT, 7, 4, REGSB }, 37 { AMOVWL, C_REG, C_NONE, C_SEXT, 7, 4, REGSB }, 38 { AMOVW, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP }, 39 { AMOVV, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP }, 40 { AMOVB, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP }, 41 { AMOVBU, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP }, 42 { AMOVWL, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP }, 43 { AMOVW, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO }, 44 { AMOVV, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO }, 45 { AMOVB, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO }, 46 { AMOVBU, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO }, 47 { AMOVWL, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO }, 48 49 { AMOVW, C_SEXT, C_NONE, C_REG, 8, 4, REGSB }, 50 { AMOVV, C_SEXT, C_NONE, C_REG, 8, 4, REGSB }, 51 { AMOVB, C_SEXT, C_NONE, C_REG, 8, 4, REGSB }, 52 { AMOVBU, C_SEXT, C_NONE, C_REG, 8, 4, REGSB }, 53 { AMOVWL, C_SEXT, C_NONE, C_REG, 8, 4, REGSB }, 54 { AMOVW, C_SAUTO,C_NONE, C_REG, 8, 4, REGSP }, 55 { AMOVV, C_SAUTO,C_NONE, C_REG, 8, 4, REGSP }, 56 { AMOVB, C_SAUTO,C_NONE, C_REG, 8, 4, REGSP }, 57 { AMOVBU, C_SAUTO,C_NONE, C_REG, 8, 4, REGSP }, 58 { AMOVWL, C_SAUTO,C_NONE, C_REG, 8, 4, REGSP }, 59 { AMOVW, C_SOREG,C_NONE, C_REG, 8, 4, REGZERO }, 60 { AMOVV, C_SOREG,C_NONE, C_REG, 8, 4, REGZERO }, 61 { AMOVB, C_SOREG,C_NONE, C_REG, 8, 4, REGZERO }, 62 { AMOVBU, C_SOREG,C_NONE, C_REG, 8, 4, REGZERO }, 63 { AMOVWL, C_SOREG,C_NONE, C_REG, 8, 4, REGZERO }, 64 65 { AMOVW, C_REG, C_NONE, C_LEXT, 35, 16, REGSB }, 66 { AMOVV, C_REG, C_NONE, C_LEXT, 35, 16, REGSB }, 67 { AMOVB, C_REG, C_NONE, C_LEXT, 35, 16, REGSB }, 68 { AMOVBU, C_REG, C_NONE, C_LEXT, 35, 16, REGSB }, 69 { AMOVW, C_REG, C_NONE, C_LAUTO, 35, 16, REGSP }, 70 { AMOVV, C_REG, C_NONE, C_LAUTO, 35, 16, REGSP }, 71 { AMOVB, C_REG, C_NONE, C_LAUTO, 35, 16, REGSP }, 72 { AMOVBU, C_REG, C_NONE, C_LAUTO, 35, 16, REGSP }, 73 { AMOVW, C_REG, C_NONE, C_LOREG, 35, 16, REGZERO }, 74 { AMOVV, C_REG, C_NONE, C_LOREG, 35, 16, REGZERO }, 75 { AMOVB, C_REG, C_NONE, C_LOREG, 35, 16, REGZERO }, 76 { AMOVBU, C_REG, C_NONE, C_LOREG, 35, 16, REGZERO }, 77 78 { AMOVW, C_LEXT, C_NONE, C_REG, 36, 16, REGSB }, 79 { AMOVV, C_LEXT, C_NONE, C_REG, 36, 16, REGSB }, 80 { AMOVB, C_LEXT, C_NONE, C_REG, 36, 16, REGSB }, 81 { AMOVBU, C_LEXT, C_NONE, C_REG, 36, 16, REGSB }, 82 { AMOVW, C_LAUTO,C_NONE, C_REG, 36, 16, REGSP }, 83 { AMOVV, C_LAUTO,C_NONE, C_REG, 36, 16, REGSP }, 84 { AMOVB, C_LAUTO,C_NONE, C_REG, 36, 16, REGSP }, 85 { AMOVBU, C_LAUTO,C_NONE, C_REG, 36, 16, REGSP }, 86 { AMOVW, C_LOREG,C_NONE, C_REG, 36, 16, REGZERO }, 87 { AMOVV, C_LOREG,C_NONE, C_REG, 36, 16, REGZERO }, 88 { AMOVB, C_LOREG,C_NONE, C_REG, 36, 16, REGZERO }, 89 { AMOVBU, C_LOREG,C_NONE, C_REG, 36, 16, REGZERO }, 90 91 { AMOVW, C_SECON,C_NONE, C_REG, 3, 4, REGSB }, 92 { AMOVW, C_SACON,C_NONE, C_REG, 3, 4, REGSP }, 93 { AMOVW, C_LECON,C_NONE, C_REG, 26, 12, REGSB }, 94 { AMOVW, C_LACON,C_NONE, C_REG, 26, 12, REGSP }, 95 { AMOVW, C_ADDCON,C_NONE,C_REG, 3, 4, REGZERO }, 96 { AMOVV, C_ADDCON,C_NONE,C_REG, 3, 4, REGZERO }, 97 { AMOVW, C_ANDCON,C_NONE,C_REG, 3, 4, REGZERO }, 98 { AMOVV, C_ANDCON,C_NONE,C_REG, 3, 4, REGZERO }, 99 100 { AMOVW, C_UCON, C_NONE, C_REG, 24, 4, 0 }, 101 { AMOVV, C_UCON, C_NONE, C_REG, 24, 4, 0 }, 102 { AMOVW, C_LCON, C_NONE, C_REG, 19, 8, 0 }, 103 { AMOVV, C_LCON, C_NONE, C_REG, 19, 8, 0 }, 104 105 { AMOVW, C_HI, C_NONE, C_REG, 20, 4, 0 }, 106 { AMOVV, C_HI, C_NONE, C_REG, 20, 4, 0 }, 107 { AMOVW, C_LO, C_NONE, C_REG, 20, 4, 0 }, 108 { AMOVV, C_LO, C_NONE, C_REG, 20, 4, 0 }, 109 { AMOVW, C_REG, C_NONE, C_HI, 21, 4, 0 }, 110 { AMOVV, C_REG, C_NONE, C_HI, 21, 4, 0 }, 111 { AMOVW, C_REG, C_NONE, C_LO, 21, 4, 0 }, 112 { AMOVV, C_REG, C_NONE, C_LO, 21, 4, 0 }, 113 114 { AMUL, C_REG, C_REG, C_NONE, 22, 4, 0 }, 115 116 { AADD, C_ADD0CON,C_REG,C_REG, 4, 4, 0 }, 117 { AADD, C_ADD0CON,C_NONE,C_REG, 4, 4, 0 }, 118 { AADD, C_ANDCON,C_REG, C_REG, 10, 8, 0 }, 119 { AADD, C_ANDCON,C_NONE,C_REG, 10, 8, 0 }, 120 121 { AAND, C_AND0CON,C_REG,C_REG, 4, 4, 0 }, 122 { AAND, C_AND0CON,C_NONE,C_REG, 4, 4, 0 }, 123 { AAND, C_ADDCON,C_REG, C_REG, 10, 8, 0 }, 124 { AAND, C_ADDCON,C_NONE,C_REG, 10, 8, 0 }, 125 126 { AADD, C_UCON, C_REG, C_REG, 25, 8, 0 }, 127 { AADD, C_UCON, C_NONE, C_REG, 25, 8, 0 }, 128 { AAND, C_UCON, C_REG, C_REG, 25, 8, 0 }, 129 { AAND, C_UCON, C_NONE, C_REG, 25, 8, 0 }, 130 131 { AADD, C_LCON, C_NONE, C_REG, 23, 12, 0 }, 132 { AAND, C_LCON, C_NONE, C_REG, 23, 12, 0 }, 133 { AADD, C_LCON, C_REG, C_REG, 23, 12, 0 }, 134 { AAND, C_LCON, C_REG, C_REG, 23, 12, 0 }, 135 136 { ASLL, C_SCON, C_REG, C_REG, 16, 4, 0 }, 137 { ASLL, C_SCON, C_NONE, C_REG, 16, 4, 0 }, 138 139 { ASYSCALL, C_NONE, C_NONE, C_NONE, 5, 4, 0 }, 140 141 { ABEQ, C_REG, C_REG, C_SBRA, 6, 4, 0 }, 142 { ABEQ, C_REG, C_NONE, C_SBRA, 6, 4, 0 }, 143 { ABLEZ, C_REG, C_NONE, C_SBRA, 6, 4, 0 }, 144 { ABFPT, C_NONE, C_NONE, C_SBRA, 6, 4, 0 }, 145 146 { AJMP, C_NONE, C_NONE, C_LBRA, 11, 4, 0 }, 147 { AJAL, C_NONE, C_NONE, C_LBRA, 11, 4, 0 }, 148 149 { AJMP, C_NONE, C_NONE, C_ZOREG, 18, 4, REGZERO }, 150 { AJAL, C_NONE, C_NONE, C_ZOREG, 18, 4, REGLINK }, 151 152 { AMOVW, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB }, 153 { AMOVF, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB }, 154 { AMOVD, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB }, 155 { AMOVW, C_SAUTO,C_NONE, C_FREG, 27, 4, REGSP }, 156 { AMOVF, C_SAUTO,C_NONE, C_FREG, 27, 4, REGSP }, 157 { AMOVD, C_SAUTO,C_NONE, C_FREG, 27, 4, REGSP }, 158 { AMOVW, C_SOREG,C_NONE, C_FREG, 27, 4, REGZERO }, 159 { AMOVF, C_SOREG,C_NONE, C_FREG, 27, 4, REGZERO }, 160 { AMOVD, C_SOREG,C_NONE, C_FREG, 27, 4, REGZERO }, 161 162 { AMOVW, C_LEXT, C_NONE, C_FREG, 27, 16, REGSB }, 163 { AMOVF, C_LEXT, C_NONE, C_FREG, 27, 16, REGSB }, 164 { AMOVD, C_LEXT, C_NONE, C_FREG, 27, 16, REGSB }, 165 { AMOVW, C_LAUTO,C_NONE, C_FREG, 27, 16, REGSP }, 166 { AMOVF, C_LAUTO,C_NONE, C_FREG, 27, 16, REGSP }, 167 { AMOVD, C_LAUTO,C_NONE, C_FREG, 27, 16, REGSP }, 168 { AMOVW, C_LOREG,C_NONE, C_FREG, 27, 16, REGZERO }, 169 { AMOVF, C_LOREG,C_NONE, C_FREG, 27, 16, REGZERO }, 170 { AMOVD, C_LOREG,C_NONE, C_FREG, 27, 16, REGZERO }, 171 172 { AMOVW, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB }, 173 { AMOVF, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB }, 174 { AMOVD, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB }, 175 { AMOVW, C_FREG, C_NONE, C_SAUTO, 28, 4, REGSP }, 176 { AMOVF, C_FREG, C_NONE, C_SAUTO, 28, 4, REGSP }, 177 { AMOVD, C_FREG, C_NONE, C_SAUTO, 28, 4, REGSP }, 178 { AMOVW, C_FREG, C_NONE, C_SOREG, 28, 4, REGZERO }, 179 { AMOVF, C_FREG, C_NONE, C_SOREG, 28, 4, REGZERO }, 180 { AMOVD, C_FREG, C_NONE, C_SOREG, 28, 4, REGZERO }, 181 182 { AMOVW, C_FREG, C_NONE, C_LEXT, 28, 16, REGSB }, 183 { AMOVF, C_FREG, C_NONE, C_LEXT, 28, 16, REGSB }, 184 { AMOVD, C_FREG, C_NONE, C_LEXT, 28, 16, REGSB }, 185 { AMOVW, C_FREG, C_NONE, C_LAUTO, 28, 16, REGSP }, 186 { AMOVF, C_FREG, C_NONE, C_LAUTO, 28, 16, REGSP }, 187 { AMOVD, C_FREG, C_NONE, C_LAUTO, 28, 16, REGSP }, 188 { AMOVW, C_FREG, C_NONE, C_LOREG, 28, 16, REGZERO }, 189 { AMOVF, C_FREG, C_NONE, C_LOREG, 28, 16, REGZERO }, 190 { AMOVD, C_FREG, C_NONE, C_LOREG, 28, 16, REGZERO }, 191 192 { AMOVW, C_REG, C_NONE, C_FREG, 30, 4, 0 }, 193 { AMOVW, C_FREG, C_NONE, C_REG, 31, 4, 0 }, 194 { AMOVV, C_REG, C_NONE, C_FREG, 47, 4, 0 }, 195 { AMOVV, C_FREG, C_NONE, C_REG, 48, 4, 0 }, 196 197 { AMOVW, C_ADDCON,C_NONE,C_FREG, 34, 8, 0 }, 198 { AMOVW, C_ANDCON,C_NONE,C_FREG, 34, 8, 0 }, 199 { AMOVW, C_UCON, C_NONE, C_FREG, 35, 8, 0 }, 200 { AMOVW, C_LCON, C_NONE, C_FREG, 36, 12, 0 }, 201 202 { AMOVW, C_REG, C_NONE, C_MREG, 37, 4, 0 }, 203 { AMOVV, C_REG, C_NONE, C_MREG, 37, 4, 0 }, 204 { AMOVW, C_MREG, C_NONE, C_REG, 38, 4, 0 }, 205 { AMOVV, C_MREG, C_NONE, C_REG, 38, 4, 0 }, 206 207 { ARFE, C_NONE, C_NONE, C_ZOREG, 39, 8, 0 }, 208 { AWORD, C_NONE, C_NONE, C_LCON, 40, 4, 0 }, 209 210 { AMOVW, C_REG, C_NONE, C_FCREG, 41, 8, 0 }, 211 { AMOVV, C_REG, C_NONE, C_FCREG, 41, 8, 0 }, 212 { AMOVW, C_FCREG,C_NONE, C_REG, 42, 4, 0 }, 213 { AMOVV, C_FCREG,C_NONE, C_REG, 42, 4, 0 }, 214 215 { ABREAK, C_REG, C_NONE, C_SEXT, 7, 4, REGSB }, /* really CACHE instruction */ 216 { ABREAK, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP }, 217 { ABREAK, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO }, 218 { ABREAK, C_NONE, C_NONE, C_NONE, 5, 4, 0 }, 219 220 { AXXX, C_NONE, C_NONE, C_NONE, 0, 4, 0 }, 221 }; 222