1 typedef struct Conf Conf; 2 typedef struct FPU FPU; 3 typedef struct FPenv FPenv; 4 typedef struct IMM IMM; 5 typedef struct Irqctl Irqctl; 6 typedef struct ISAConf ISAConf; 7 typedef struct Label Label; 8 typedef struct Lock Lock; 9 typedef struct Mach Mach; 10 typedef struct Map Map; 11 typedef struct Power Power; 12 typedef struct RMap RMap; 13 typedef struct Ureg Ureg; 14 15 typedef ulong Instr; 16 17 #define MACHP(n) (n==0? &mach0 : *(Mach**)0) 18 19 struct Lock 20 { 21 ulong key; 22 ulong pc; 23 ulong sr; 24 int pri; 25 }; 26 27 struct Label 28 { 29 ulong sp; 30 ulong pc; 31 }; 32 33 /* 34 * Proc.fpstate 35 */ 36 enum 37 { 38 FPINIT, 39 FPACTIVE, 40 FPINACTIVE, 41 }; 42 43 /* 44 * This structure must agree with FPsave and FPrestore asm routines 45 */ 46 struct FPenv 47 { 48 union { 49 double fpscrd; 50 struct { 51 ulong pad; 52 ulong fpscr; 53 }; 54 }; 55 int fpistate; /* emulated fp */ 56 ulong emreg[32][3]; /* emulated fp */ 57 }; 58 /* 59 * This structure must agree with fpsave and fprestore asm routines 60 */ 61 struct FPU 62 { 63 double fpreg[32]; 64 FPenv env; 65 }; 66 67 struct Conf 68 { 69 ulong nmach; /* processors */ 70 ulong nproc; /* processes */ 71 ulong npage0; /* total physical pages of memory */ 72 ulong npage1; /* total physical pages of memory */ 73 ulong npage; /* total physical pages of memory */ 74 ulong base0; /* base of bank 0 */ 75 ulong base1; /* base of bank 1 */ 76 ulong ialloc; /* max interrupt time allocation in bytes */ 77 78 int nscc; /* number of SCCs implemented */ 79 ulong smcuarts; /* bits for SMCs to define as eiaN */ 80 ulong sccuarts; /* bits for SCCs to define as eiaN */ 81 int nocts2; /* CTS2 and CD2 aren't connected */ 82 uchar* nvrambase; /* virtual address of nvram */ 83 ulong nvramsize; /* size in bytes */ 84 }; 85 86 #include "../port/portdat.h" 87 88 /* 89 * machine dependent definitions not used by ../port/dat.h 90 */ 91 92 struct Mach 93 { 94 /* OFFSETS OF THE FOLLOWING KNOWN BY l.s */ 95 int machno; /* physical id of processor (unused) */ 96 ulong splpc; /* pc of last caller to splhi (unused) */ 97 int mmask; /* 1<<m->machno (unused) */ 98 99 /* ordering from here on irrelevant */ 100 ulong ticks; /* of the clock since boot time */ 101 Proc *proc; /* current process on this processor */ 102 Label sched; /* scheduler wakeup */ 103 Lock alarmlock; /* access to alarm list */ 104 void *alarm; /* alarms bound to this clock */ 105 int nrdy; 106 int speed; /* general system clock in MHz */ 107 long oscclk; /* oscillator frequency (MHz) */ 108 long cpuhz; /* general system clock (cycles) */ 109 long clockgen; /* clock generator frequency (cycles) */ 110 int cputype; 111 ulong delayloop; 112 ulong* bcsr; 113 IMM* iomem; /* MPC8xx internal i/o control memory */ 114 115 /* MUST BE LAST */ 116 int stack[1]; 117 }; 118 extern Mach mach0; 119 120 121 /* 122 * a parsed .ini line 123 */ 124 #define NISAOPT 8 125 126 struct ISAConf { 127 char* type; 128 ulong port; 129 ulong irq; 130 ulong mem; 131 int dma; 132 ulong size; 133 ulong freq; 134 uchar bus; 135 136 int nopt; 137 char* opt[NISAOPT]; 138 }; 139 140 struct Map { 141 int size; 142 ulong addr; 143 }; 144 145 struct RMap { 146 char* name; 147 Map* map; 148 Map* mapend; 149 150 Lock; 151 }; 152 153 struct Power { 154 Dev* dev; 155 int (*powerdown)(Power*); 156 int (*powerup)(Power*); 157 int state; 158 void* arg; 159 }; 160 161 extern register Mach *m; 162 extern register Proc *up; 163