1 /* 2 * Memory and machine-specific definitions. Used in C and assembler. 3 */ 4 5 /* 6 * Sizes 7 */ 8 9 #define BI2BY 8 /* bits per byte */ 10 #define BI2WD 32 /* bits per word */ 11 #define BY2WD 4 /* bytes per word */ 12 #define BY2V 8 /* bytes per double word */ 13 #define BY2PG 4096 /* bytes per page */ 14 #define WD2PG (BY2PG/BY2WD) /* words per page */ 15 #define PGSHIFT 12 /* log(BY2PG) */ 16 #define ROUND(s, sz) (((s)+(sz-1))&~(sz-1)) 17 #define PGROUND(s) ROUND(s, BY2PG) 18 #define CACHELINELOG 4 19 #define CACHELINESZ (1<<CACHELINELOG) 20 21 #define MAXMACH 1 /* max # cpus system can run */ 22 #define MACHSIZE BY2PG 23 24 /* 25 * Time 26 */ 27 #define HZ 100 /* clock frequency */ 28 #define MS2HZ (1000/HZ) /* millisec per clock tick */ 29 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */ 30 #define MS2TK(t) ((t)/MS2HZ) /* milliseconds to ticks */ 31 #define MHz 1000000 32 33 /* 34 * MSR bits 35 */ 36 37 #define POW 0x40000 /* enable power mgmt */ 38 #define TGPR 0x20000 /* GPR0-3 remapped; 603/603e specific */ 39 #define ILE 0x10000 /* interrupts little endian */ 40 #define EE 0x08000 /* enable external/decrementer interrupts */ 41 #define PR 0x04000 /* =1, user mode */ 42 #define FPE 0x02000 /* enable floating point */ 43 #define ME 0x01000 /* enable machine check exceptions */ 44 #define FE0 0x00800 45 #define SE 0x00400 /* single-step trace */ 46 #define BE 0x00200 /* branch trace */ 47 #define FE1 0x00100 48 #define MSR_IP 0x00040 /* =0, vector to nnnnn; =1, vector to FFFnnnnn */ 49 #define IR 0x00020 /* enable instruction address translation */ 50 #define DR 0x00010 /* enable data address translation */ 51 #define RI 0x00002 /* exception is recoverable */ 52 #define LE 0x00001 /* little endian mode */ 53 54 #define KMSR (ME|FE0|FE1|FPE) 55 #define UMSR (KMSR|PR|EE|IR|DR) 56 57 /* 58 * Magic registers 59 */ 60 61 #define MACH 30 /* R30 is m-> */ 62 #define USER 29 /* R29 is up-> */ 63 #define IOMEMR 28 /* R28 will be iomem-> */ 64 65 /* 66 * Fundamental addresses 67 */ 68 69 #define UREGSIZE ((8+32)*4) 70 71 /* 72 * MMU 73 */ 74 75 /* L1 table entry and Mx_TWC flags */ 76 #define PTEVALID (1<<0) 77 #define PTEWT (1<<1) /* write through */ 78 #define PTE4K (0<<2) 79 #define PTE512K (1<<2) 80 #define PTE8MB (3<<2) 81 #define PTEG (1<<4) /* guarded */ 82 83 /* L2 table entry and Mx_RPN flags (also PTEVALID) */ 84 #define PTECI (1<<1) /* cache inhibit */ 85 #define PTESH (1<<2) /* page is shared; ASID ignored */ 86 #define PTELPS (1<<3) /* large page size */ 87 #define PTEWRITE 0x9F0 88 89 /* TLB and MxEPN flag */ 90 #define TLBVALID (1<<9) 91 92 /* 93 * Address spaces 94 */ 95 96 #define KUSEG 0x00000000 97 #define KSEG0 0x20000000 98 #define KSEGM 0xE0000000 /* mask to check which seg */ 99 100 #define KZERO KSEG0 /* base of kernel address space */ 101 #define KTZERO (KZERO+0x3000) /* first address in kernel text */ 102 #define KSTACK 8192 /* Size of kernel stack */ 103 104 #define CONFADDR (KZERO|0x200000) /* where qboot leaves configuration info */ 105 106 /* 107 * Exception codes (trap vectors) 108 */ 109 #define CRESET 0x01 110 #define CMCHECK 0x02 111 #define CDSI 0x03 112 #define CISI 0x04 113 #define CEI 0x05 114 #define CALIGN 0x06 115 #define CPROG 0x07 116 #define CFPU 0x08 117 #define CDEC 0x09 118 #define CSYSCALL 0x0C 119 #define CTRACE 0x0D 120 #define CFPA 0x0E 121 /* rest are power-implementation dependent (8xx) */ 122 #define CEMU 0x10 123 #define CIMISS 0x11 124 #define CDMISS 0x12 125 #define CITLBE 0x13 126 #define CDTLBE 0x14 127 #define CDBREAK 0x1C 128 #define CIBREAK 0x1D 129 #define CPBREAK 0x1E 130 #define CDPORT 0x1F 131 132 /* 133 * MPC8xx physical addresses 134 */ 135 136 /* those encouraged by mpc8bug */ 137 #define PHYSDRAM 0x00000000 138 #define PHYSBCSR 0x02100000 139 #define PHYSIMM 0x02200000 140 #define PHYSFLASH 0x02800000 141 142 /* remaining ones are our choice */ 143 #define PHYSSDRAM 0x03000000 144 #define PHYSPCMCIA 0x04000000 145 #define PCMCIALEN (8*MB) /* chosen to allow mapping by single TLB entry */ 146 #define ISAIO (KZERO|PHYSPCMCIA) /* for inb.s */ 147 148 /* 149 * MPC8xx dual-ported CPM memory physical addresses 150 */ 151 #define PHYSDPRAM (PHYSIMM+0x2000) 152 #define DPLEN1 0x200 153 #define DPLEN2 0x400 154 #define DPLEN3 0x800 155 #define DPBASE (PHYSDPRAM+DPLEN1) 156 157 #define KEEP_ALIVE_KEY 0x55ccaa33 /* clock and rtc register key */ 158