xref: /inferno-os/os/boot/rpcg/l.s (revision 74a4d8c26dd3c1e9febcb717cfd6cb6512991a7a) 
1#include "mem.h"
2
3/* special instruction definitions */
4#define	BDNE	BC	0,2,
5#define	BDNZ	BC	16,0,
6#define	NOOP	OR	R0,R0,R0
7
8/*
9 * common ppc special purpose registers
10 */
11#define DSISR	18
12#define DAR	19	/* Data Address Register */
13#define DEC	22	/* Decrementer */
14#define SRR0	26	/* Saved Registers (exception) */
15#define SRR1	27
16#define SPRG0	272	/* Supervisor Private Registers */
17#define SPRG1	273
18#define SPRG2	274
19#define SPRG3	275
20#define TBRU	269	/* Time base Upper/Lower (Reading) */
21#define TBRL	268
22#define TBWU	285	/* Time base Upper/Lower (Writing) */
23#define TBWL	284
24#define PVR	287	/* Processor Version */
25
26/*
27 * mpc82x-specific special purpose registers of interest here
28 */
29#define EIE	80
30#define EID	81
31#define NRI	82
32#define IMMR	638
33#define IC_CST	560
34#define IC_ADR	561
35#define IC_DAT	562
36#define DC_CST	568
37#define DC_ADR	569
38#define DC_DAT	570
39#define MI_CTR	784
40#define MI_AP	786
41#define MI_EPN	787
42#define MI_TWC	789
43#define MI_RPN	790
44#define MI_DBCAM	816
45#define MI_DBRAM0	817
46#define MI_DBRAM1	818
47#define MD_CTR	792
48#define M_CASID	793
49#define MD_AP	794
50#define MD_EPN	795
51#define M_TWB	796
52#define MD_TWC	797
53#define MD_RPN	798
54#define	M_TW	799
55#define	MD_DBCAM	824
56#define	MD_DBRAM0	825
57#define	MD_DBRAM1	826
58
59/* as on 603e, apparently mtmsr needs help in some chip revisions */
60#define	WAITMSR	SYNC; ISYNC
61
62/* use of SPRG registers in save/restore */
63#define	SAVER0	SPRG0
64#define	SAVER1	SPRG1
65#define	SAVELR	SPRG2
66#define	SAVECR	SPRG3
67
68#define	UREGSIZE	((8+32)*4)
69#define	UREGSPACE	(UREGSIZE+8)	/* allow for arg to trap, and align */
70
71/*
72 * This code is loaded by the ROM loader at location 0x3000,
73 * or lives in flash memory at FLASHMEM+0x100
74 * Move it to high memory so that it can load the kernel at 0x0000.
75 */
76
77#define LOADCODEBASE	0x3000	/* when downloaded in S records */
78#define FLASHCODEBASE	(FLASHMEM+0x20000+0x100)	/* when in flash */
79
80	TEXT	start(SB), $-4
81	MOVW	MSR, R3
82	MOVW	$(EE|IP|RI), R4
83	ANDN	R4, R3
84	OR	$ME, R3
85	SYNC
86	MOVW	R3, MSR	/* turn off interrupts but enable traps */
87	WAITMSR
88
89/*
90 * reset the caches and disable them for now
91 */
92	MOVW	SPR(IC_CST), R4	/* read and clear */
93	MOVW	$(5<<25), R4
94	MOVW	R4, SPR(IC_CST)	/* unlock all */
95	ISYNC
96	MOVW	$(6<<25), R4
97	MOVW	R4, SPR(IC_CST)	/* invalidate all */
98	ISYNC
99	MOVW	$(2<<25), R4
100	MOVW	R4, SPR(IC_CST)	/* disable i-cache */
101	ISYNC
102
103	SYNC
104	MOVW	SPR(DC_CST), R4	/* read and clear */
105	MOVW	$(10<<24), R4
106	MOVW	R4, SPR(DC_CST)	/* unlock all */
107	ISYNC
108	MOVW	$(12<<24), R4
109	MOVW	R4, SPR(DC_CST)	/* invalidate all */
110	ISYNC
111	MOVW	$(4<<24), R4
112	MOVW	R4, SPR(DC_CST)	/* disable i-cache */
113	ISYNC
114
115	MOVW	$7, R4
116	MOVW	R4, SPR(158)		/* cancel `show cycle' for normal instruction execution */
117
118/*
119 * set other system configuration values
120 */
121	MOVW	SPR(IMMR), R5		/* save initial space pointer */
122	MOVW	$INTMEM, R4
123	MOVW	R4, SPR(IMMR)		/* set internal memory base */
124	MOVW	$0xFFFFFF88, R3
125	MOVW	R3, 4(R4)	/* disable watchdog in sypcr */
126	MOVW	$0x01012440, R3
127	MOVW	R3, 0(R4)	/* siumcr */
128
129/*
130 * system initialisation (init and map DRAM)
131 */
132	MOVW	$0, R0
133	MOVW	$setSB(SB), R2
134#ifndef confrpcg
135	MOVW	$(0xF000<<16), R3
136/*MOVW R0, R3*/
137	ANDCC	R5, R3	/* initial space is high? */
138	BEQ	notrom
139	MOVW	$FLASHCODEBASE, R5	/* where $start(SB) actually is now */
140	MOVW	$start(SB), R4	/* logical start address */
141	SUB	R4, R5, R6	/* text relocation value */
142	MOVW	$etext(SB), R7
143	SUB	R4, R7
144	ADD	R5, R7	/* data address in ROM */
145	MOVW	$bdata(SB), R8
146	SUB	R8, R2
147	ADD	R7, R2	/* relocate SB: SB' = romdata+(SB-bdata) */
148	MOVW	$sysinit0(SB), R4
149	ADD	R6, R4	/* relocate sysinit0's address */
150	MOVW	R4, CTR
151	MOVW	$inmem(SB), R4
152	ADD	R6, R4
153	MOVW	R4, LR	/* and the return address */
154	BR	(CTR)	/* call sysinit0 */
155	TEXT	inmem(SB), $-4
156	MOVW	$FLASHCODEBASE, R3
157	BR	cpu0
158notrom:
159	MOVW	$start(SB), R6
160	SUB	R6, R2
161	ADD	$LOADCODEBASE, R2
162	BL	sysinit0(SB)
163	MOVW	$LOADCODEBASE, R3
164#endif
165
166/*
167 * cpu 0
168 *	relocate bootstrap to our link addresses for text and data
169 *	set new PC
170 */
171cpu0:
172	MOVW	$setSB(SB), R2	/* set correct static base register */
173#ifndef confrpcg
174	MOVW	$start(SB), R4
175	MOVW	$etext(SB), R5
176	SUB	R4, R5
177	CMP	R4, R3	/* already there? */
178	BNE	copytext
179	ADD	R5, R3	/* start of data image */
180#else
181	MOVW	$etext(SB), R3
182#endif
183	BR	copydata
184
185copytext:
186	ADD	$3, R5
187	SRAW	$2, R5
188	MOVW	R5, CTR
189	SUB	$4, R4
190	SUB	$4, R3
191copyt:			/* copy text */
192	MOVWU	4(R3), R5
193	MOVWU	R5, 4(R4)
194	BDNZ	copyt
195	ADD	$4, R3
196
197copydata:
198	/* copy data */
199	MOVW	$bdata(SB), R4
200	CMP	R4, R3	/* already there? */
201	BEQ	loadkpc
202	MOVW	$edata(SB), R5
203	SUB	R4, R5
204	ADD	$3, R5
205	SRAW	$2, R5
206	MOVW	R5, CTR
207	SUB	$4, R4
208	SUB	$4, R3
209copyd:
210	MOVWU	4(R3), R5
211	MOVWU	R5, 4(R4)
212	BDNZ	copyd
213#endif
214
215	/* load correct PC */
216loadkpc:
217	MOVW	$start1(SB), R3
218	MOVW	R3, LR
219	BR	(LR)
220TEXT start1(SB), $-4
221	MOVW	$edata(SB), R3
222	MOVW	$end(SB), R4
223	SUBCC	R3, R4
224	BLE	skipz
225	SRAW	$2, R4
226	MOVW	R4, CTR
227	SUB	$4, R3
228	MOVW	$0, R0
229zero:
230	MOVWU	R0, 4(R3)
231	BDNZ	zero
232skipz:
233	MOVW	$mach0(SB), R1
234	MOVW	R1, m(SB)
235	ADD	$(MACHSIZE-8), R1
236	MOVW	$0, R0
237
238	BL	sysinit0(SB)
239
240	BL	main(SB)
241	BR	0(PC)
242
243TEXT ledx(SB), $0
244
245	MOVW	$BCSRMEM, R8
246	MOVW	0(R8), R3
247	MOVW	$(0x0800<<16), R5
248	ANDN	R5, R3, R3
249	MOVW	R3, 0(R8)
250	BR	0(PC)
251
252TEXT	getmsr(SB), $0
253	MOVW	MSR, R3
254	RETURN
255
256TEXT	putmsr(SB), $0
257	SYNC
258	MOVW	R3, MSR
259	WAITMSR
260	RETURN
261
262TEXT	eieio(SB), $0
263	EIEIO
264	RETURN
265
266TEXT	idle(SB), $0
267	RETURN
268
269TEXT	spllo(SB), $0
270	MOVW	MSR, R3
271	OR	$EE, R3, R4
272	SYNC
273	MOVW	R4, MSR
274	WAITMSR
275	RETURN
276
277TEXT	splhi(SB), $0
278	MOVW	MSR, R3
279	RLWNM	$0, R3, $~EE, R4
280	SYNC
281	MOVW	R4, MSR
282	WAITMSR
283	RETURN
284
285TEXT	splx(SB), $0
286	MOVW	MSR, R4
287	RLWMI	$0, R3, $EE, R4
288	SYNC
289	MOVW	R4, MSR
290	WAITMSR
291	RETURN
292
293TEXT	gettbl(SB), $0
294/*	MOVW	SPR(TBRL), R3	*/
295	WORD	$0x7c6c42e6	/* mftbl on 8xx series */
296	RETURN
297
298TEXT	getpvr(SB), $0
299	MOVW	SPR(PVR), R3
300	RETURN
301
302TEXT	getimmr(SB), $0
303	MOVW	SPR(IMMR), R3
304	RETURN
305
306TEXT	getdec(SB), $0
307	MOVW	SPR(DEC), R3
308	RETURN
309
310TEXT	putdec(SB), $0
311	MOVW	R3, SPR(DEC)
312	RETURN
313
314/*
315 * save state in Ureg on kernel stack.
316 * enter with R0 giving the PC from the call to `exception' from the vector.
317 * on return, SB (R2) has been set, and R3 has the Ureg*
318 */
319TEXT saveureg(SB), $-4
320	SUB	$UREGSPACE, R1
321	MOVMW	R2, 48(R1)	/* r2:r31 */
322	MOVW	$setSB(SB), R2
323	MOVW	SPR(SAVER1), R4
324	MOVW	R4, 44(R1)
325	MOVW	SPR(SAVER0), R5
326	MOVW	R5, 40(R1)
327	MOVW	CTR, R6
328	MOVW	R6, 36(R1)
329	MOVW	XER, R4
330	MOVW	R4, 32(R1)
331	MOVW	SPR(SAVECR), R5	/* CR */
332	MOVW	R5, 28(R1)
333	MOVW	SPR(SAVELR), R6	/* LR */
334	MOVW	R6, 24(R1)
335	/* pad at 20(R1) */
336	MOVW	SPR(SRR0), R4
337	MOVW	R4, 16(R1)	/* old PC */
338	MOVW	SPR(SRR1), R5
339	MOVW	R5, 12(R1)
340	MOVW	R0, 8(R1)	/* cause/vector, encoded in LR from vector */
341	ADD	$8, R1, R3	/* Ureg* */
342	STWCCC	R3, (R1)	/* break any pending reservations */
343	MOVW	$0, R0	/* R0ISZERO */
344	BR	(LR)
345
346/*
347 * restore state from Ureg
348 * SB (R2) is unusable on return
349 */
350TEXT restoreureg(SB), $-4
351	MOVMW	48(R1), R2	/* r2:r31 */
352	/* defer R1 */
353	MOVW	40(R1), R0
354	MOVW	R0, SPR(SAVER0)
355	MOVW	36(R1), R0
356	MOVW	R0, CTR
357	MOVW	32(R1), R0
358	MOVW	R0, XER
359	MOVW	28(R1), R0
360	MOVW	R0, CR	/* CR */
361	MOVW	24(R1), R0
362	MOVW	R0, SPR(SAVELR)	/* LR */
363	/* pad, skip */
364	MOVW	16(R1), R0
365	MOVW	R0, SPR(SRR0)	/* old PC */
366	MOVW	12(R1), R0
367	MOVW	R0, SPR(SRR1)	/* old MSR */
368	/* cause, skip */
369	MOVW	44(R1), R1	/* old SP */
370	BR	(LR)
371
372TEXT	exception(SB), $-4
373	MOVW	R1, SPR(SAVER1)
374	MOVW	CR, R0
375	MOVW	R0, SPR(SAVECR)
376	MOVW	LR, R0
377	BL	saveureg(SB)
378	MOVW	$0, R0
379	BL	trap(SB)
380	BL	restoreureg(SB)
381	MOVW	SPR(SAVELR), R0
382	MOVW	R0, LR
383	MOVW	SPR(SAVER0), R0
384	ISYNC
385	RFI
386
387GLOBL	mach0+0(SB), $MACHSIZE
388GLOBL	m(SB), $4
389