1 /*
2 * Called from l.s in EPROM to set up a minimal working environment.
3 * Since there is no DRAM yet, and therefore no stack, no function
4 * calls may be made from sysinit0, and values can't be stored,
5 * except to INTMEM. Global values are accessed by offset from SB,
6 * which has been set by l.s to point into EPROM.
7 *
8 * This is PowerPAQ-specific:
9 * - assumes 8mbytes
10 * - powerpaq CS assignment
11 */
12
13 #include "u.h"
14 #include "lib.h"
15 #include "mem.h"
16 #include "dat.h"
17 #include "fns.h"
18 #include "io.h"
19
20 #include "archpaq.h"
21
22 #define MB (1024*1024)
23
24 enum {
25 DRAMSIZE = 8*MB,
26 FLASHSIZE = 8*MB,
27
28 UPMSIZE = 64, /* memory controller instruction RAM */
29 SPEED = 50, /* maximum memory clock in MHz */
30
31 /* mcr */
32 WriteRAM = 0<<30,
33 ReadRAM = 1<<30,
34 ExecRAM = 2<<30,
35
36 SelUPMA = 0<<23,
37 SelUPMB = 1<<23,
38
39 Once = 1<<8,
40 };
41
42 /*
43 * mpc8bug uses the following for 60ns EDO DRAMs 32-50MHz
44 */
45 static ulong upmb50[UPMSIZE] = {
46 0x8FFFEC24, 0xFFFEC04, 0xCFFEC04, 0xFFEC04,
47 0xFFEC00, 0x37FFEC47, 0xFFFFFFFF, 0xFFFFFFFF,
48 0x8FFFEC24, 0xFFFEC04, 0x8FFEC04, 0xFFEC0C,
49 0x3FFEC00, 0xFFEC44, 0xFFCC08, 0xCFFCC44,
50 0xFFEC0C, 0x3FFEC00, 0xFFEC44, 0xFFCC00,
51 0x3FFFC847, 0x3FFFEC47, 0xFFFFFFFF, 0xFFFFFFFF,
52 0x8FAFCC24, 0xFAFCC04, 0xCAFCC00, 0x11BFCC47,
53 0xC0FFCC84, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
54 0x8FAFCC24, 0xFAFCC04, 0xCAFCC00, 0x3AFCC4C,
55 0xCAFCC00, 0x3AFCC4C, 0xCAFCC00, 0x3AFCC4C,
56 0xCAFCC00, 0x33BFCC4F, 0xFFFFFFFF, 0xFFFFFFFF,
57 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
58 0xC0FFCC84, 0xFFCC04, 0x7FFCC04, 0x3FFFCC06,
59 0xFFFFCC85, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFFFFF,
60 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
61 0x33FFCC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
62 };
63
64 void
sysinit0(int inrom)65 sysinit0(int inrom)
66 {
67 ulong *upm;
68 IMM *io;
69 int i;
70
71 io = (IMM*)INTMEM; /* running before maps, no KADDR */
72
73 /* system interface unit initialisation, FADS manual table 3-2, except as noted */
74 io->siumcr = 0x01012440;
75 io->sypcr = 0xFFFFFF88;
76 io->tbscrk = KEEP_ALIVE_KEY;
77 io->tbscr = 0xC3; /* time base enabled */
78 io->rtcsck = KEEP_ALIVE_KEY;
79 io->rtcsc = 0xC1; /* don't FRZ, real-time clock enabled */
80 io->rtcsck = ~KEEP_ALIVE_KEY;
81 io->piscrk = KEEP_ALIVE_KEY;
82 io->piscr = 0x82;
83
84 io->memc[BOOTCS].base = FLASHMEM | 1;
85 io->memc[BOOTCS].option = ~(FLASHSIZE-1)|(1<<8)|(2<<4); /* mask, BIH, 2 wait states */
86
87 if(!inrom)
88 return; /* can't initialise DRAM controller from DRAM */
89
90 /* could check DRAM speed here; assume 60ns */
91 /* could probe DRAM for size here; assume DRAMSIZE */
92 io->mptpr = 0x400; /* powerpaq flash has 0x1000 */
93 io->mbmr = (0xC0<<24) | 0xA21114; /* 50MHz BRGCLK */
94 upm = upmb50;
95 for(i=0; i<UPMSIZE; i++){
96 io->mdr = upm[i];
97 io->mcr = WriteRAM | SelUPMB | i;
98 }
99 io->memc[DRAM1].option = ~(DRAMSIZE-1)|0x0800; /* address mask, SAM=1 */
100 io->memc[DRAM1].base = 0 | 0xC1; /* base at 0, 32-bit port size, no parity, UPMB */
101 }
102