1 /* 2 * values for RPXLite AW 3 */ 4 enum { 5 /* CS assignment */ 6 BOOTCS = 0, 7 DRAM1 = 1, 8 /* CS2 is routed to expansion header */ 9 BCSRCS = 3, 10 NVRAMCS = 4, 11 /* CS5 is routed to expansion header */ 12 PCMCIA0CS = 6, /* select even bytes */ 13 PCMCIA1CS = 7, /* select odd bytes */ 14 }; 15 16 /* 17 * BCSR bits (there are 4 8-bit registers that we access as ulong) 18 */ 19 enum { 20 EnableEnet = IBIT(0), 21 EnableXcrLB= IBIT(1), 22 DisableColTest= IBIT(2), 23 DisableFullDplx=IBIT(3), 24 LedOff= IBIT(4), 25 DisableUSB= IBIT(5), 26 HighSpdUSB= IBIT(6), 27 EnableUSBPwr= IBIT(7), 28 /* 8,9,10 unused */ 29 PCCVCCMask= IBIT(12)|IBIT(13), 30 PCCVPPMask= IBIT(14)|IBIT(15), 31 PCCVCC0V= 0, 32 PCCVCC5V= IBIT(13), 33 PCCVCC3V= IBIT(12), 34 PCCVPP0V= 0, 35 PCCVPP5V= IBIT(14), 36 PCCVPP12V= IBIT(15), 37 PCCVPPHiZ= IBIT(14)|IBIT(15), 38 /* 16-23 NYI */ 39 DipSwitchMask= IBIT(24)|IBIT(25)|IBIT(26)|IBIT(27), 40 DipSwitch0= IBIT(24), 41 DipSwitch1= IBIT(25), 42 DipSwitch2= IBIT(26), 43 DipSwitch3= IBIT(27), 44 /* bit 28 RESERVED */ 45 FlashComplete= IBIT(29), 46 NVRAMBattGood= IBIT(30), 47 RTCBattGood= IBIT(31), 48 }; 49