1 /* 2 * Teralogic TL750 - Puma Evaluation Board 3 */ 4 5 /* 6 * Puma addresses 7 */ 8 #define EPROM_BASE 0x80000000 /* EPROM */ 9 #define FLASH_BASE 0xa0000000 /* Flash */ 10 #define TL750_BASE 0xc0000000 /* TL750 registers */ 11 #define ISAMEM_BASE 0xe0000000 /* ISA memory space */ 12 #define ISAIO_BASE 0xf0000000 /* ISA I/O space */ 13 14 #define ISAIO_SHIFT 2 15 #define IOBADDR(io_port) (ISAIO_BASE + (io_port << ISAIO_SHIFT)) 16 17 /* Hardware address register for interrupts (HARI) */ 18 #define HARI1 0xE2000000 /* Interrupt status on read, User interrupt on write */ 19 #define HARI2 0xE3000000 /* More interrupt status on read, LEDs on write */ 20 #define HARI1_FIQ_MASK 0x92 /* FIQ indicator bits in HARI1, others are IRQ */ 21 #define HARI2_INIT 0x20 /* No timer2 aborts, Ethernet on IRQ */ 22 23 24 25 /* 26 * Interrupt Vectors 27 * corresponding to the HARIx_xxx_IRQ/FIQ bits above. 28 * 29 * HARI1 interrupts 30 */ 31 #define V_LPT 0 /* Parallel port interrupt */ 32 #define V_NM0 1 /* MPEG Decode Interrupt */ 33 #define V_NM1 2 /* MPEG Decode Interrupt */ 34 #define V_COM2 3 /* Serial Port 2 Interrupt */ 35 #define V_COM1 4 /* Serial Port 1 Interrupt */ 36 #define V_MOUSE 5 /* Mouse Interrupt */ 37 #define V_KEYBOARD 6 /* Keyboard Interrupt */ 38 #define V_ETHERNET 7 /* Ethernet Interrupt */ 39 /* 40 * HARI2 interrupts 41 */ 42 #define V_TIMER0 8 /* 82C54 Timer 0 Interrupt */ 43 #define V_TIMER1 9 /* 82C54 Timer 1 Interrupt */ 44 #define V_TIMER2 10 /* 82C54 Timer 2 Interrupt */ 45 #define V_SOFTWARE 11 /* Software Interrupt */ 46 #define V_IDE 12 /* IDE Hard Drive Interrupt */ 47 #define V_SMARTCARD 13 /* Smart Card Interrupt */ 48 #define V_TL750 14 /* TL750 Interrupt */ 49 /* Nothing in vector 15 for now */ 50 #define V_MAXNUM 15 51 52 /* 53 * Definitions for National Semiconductor PC87306 SuperIO configuration 54 */ 55 #define SIO_CONFIG_INDEX 0x398 /* SuperIO configuration index register */ 56 #define SIO_CONFIG_DATA 0x399 /* SuperIO configuration data register */ 57 58 #define SIO_CONFIG_RESET_VAL 0x88 /* Value read from first read of sio_config_index reg after reset */ 59 /* 60 * PC87306 Configuration Registers (The value listed is the configuration space 61 * index.) 62 */ 63 #define SIO_CONFIG_FER 0x00 /* Function Enable Register */ 64 65 #define FER_LPT_ENABLE 0x01 /* Enable Parallel Port */ 66 #define FER_UART1_ENABLE 0x02 /* Enable Serial Port 1 */ 67 #define FER_UART2_ENABLE 0x04 /* Enable Serial Port 2 */ 68 #define FER_FDC_ENABLE 0x08 /* Enable Floppy Controller */ 69 #define FER_FDC_4DRIVE_ENCODING 0x10 /* Select Floppy 4 Drive Encoding */ 70 #define FER_FDC_ADDR_ENABLE 0x20 /* Select Floppy Secondary Address */ 71 /* 0: [0x3F0..0x3F7] */ 72 /* 1: [0x370..0x377] */ 73 #define FER_IDE_ENABLE 0x40 /* Enable IDE Controller */ 74 #define FER_IDE_ADDR_SELECT 0x80 /* Select IDE Secondary Address */ 75 /* 0: [0x1F0..0x1F7,0x3F6,0x3F7] */ 76 /* 1: [0x170..0x177,0x376,0x377] */ 77 78 #define SIO_CONFIG_FAR 0x01 /* Function Address Register */ 79 80 #define FAR_LPT_ADDR_MASK 0x03 /* Select LPT Address */ 81 /* If (PNP0[4] == 0) then: */ 82 /* 0: LPTB [0x378..0x37F] IRQ5/7 */ 83 /* 1: LPTA [0x3BC..0x3BE] IRQ7 */ 84 /* 2: LPTC [0x278..0x27F] IRQ5 */ 85 /* 3: Reserved */ 86 /* Else ignored. */ 87 #define FAR_LPT_LPTB 0 /* 0: LPTB 0x378 irq5/7 */ 88 #define FAR_LPT_LPTA 1 /* 1: LPTA 0x3BC irq 7 */ 89 #define FAR_LPT_LPTC 2 /* 2: LPTC 0x278 irq5 */ 90 91 #define FAR_UART1_ADDR_MASK 0x0C /* Select Serial Port 1 Address */ 92 /* 0: COM1 [0x3F8..0x3FF] */ 93 /* 1: COM2 [0x2F8..0x2FF] */ 94 /* 2: COM3 (See FAR[7:6]) */ 95 /* 3: COM4 (See FAR[7:6]) */ 96 #define FAR_UART1_COM1 0x00 97 #define FAR_UART2_ADDR_MASK 0x30 /* Select Serial Port 2 Address */ 98 /* 0: COM1 [0x3F8..0x3FF] */ 99 /* 1: COM2 [0x2F8..0x2FF] */ 100 /* 2: COM3 (See FAR[7:6]) */ 101 /* 3: COM4 (See FAR[7:6]) */ 102 #define FAR_UART2_COM2 0x10 103 #define FAR_EXTENDED_UART_ADDR_SELECT 0xC0 /* Extended Address Selects */ 104 /* COM3@IRQ4, COM4@IRQ3 */ 105 /* 0: COM3@0x3E8, COM4@0x2E8 */ 106 /* 1: COM3@0x338, COM4@0x238 */ 107 /* 2: COM3@0x2E8, COM4@0x2E0 */ 108 /* 3: COM3@0x220, COM4@0x228 */ 109 110 #define SIO_CONFIG_PTR 0x02 /* Power & Test Register */ 111 112 #define PTR_POWER_DOWN 0x01 /* Power down all enabled functions */ 113 #define PTR_LPT_IRQ_SELECT 0x08 /* Select LPT IRQ if (FAR[1:0] == 0) */ 114 /* 0: IRQ5 */ 115 /* 1: IRQ7 */ 116 #define PTR_UART1_TEST_MODE 0x10 /* Set serial port 1 test mode */ 117 #define PTR_UART2_TEST_MODE 0x20 /* Set serial port 2 test mode */ 118 #define PTR_LOCK_CONFIGURATION 0x40 /* Prevent all further config writes */ 119 /* Only a RESET will reenable writes */ 120 #define PTR_LPT_EXTENDED_MODE_SELECT 0x80 /* Select Mode if not EPP/ECP */ 121 /* 0: Compatible Mode */ 122 /* 1: Extended Mode */ 123 124 #define SIO_CONFIG_FCR 0x03 /* Function Control Register */ 125 /* WARNING: The FCR register must be written */ 126 /* using read-modify-write! */ 127 #define FCR_TDR_MODE_SELECT 0x01 /* ? (floppy/tape) */ 128 #define FCR_IDE_DMA_ENABLE 0x02 /* Enable IDE DMA mode */ 129 #define FCR_EPP_ZERO_WAIT_STATE 0x40 /* Enable EPP zero wait state */ 130 131 #define SIO_CONFIG_PCR 0x04 /* Printer Control Register */ 132 133 #define PCR_EPP_ENABLE 0x01 /* Enable parallel port EPP mode */ 134 #define PCR_EPP_VERSION_SELECT 0x02 /* Select version of EPP mode */ 135 /* 0: Version 1.7 */ 136 /* 1: Version 1.9 (IEEE 1284) */ 137 #define PCR_ECP_ENABLE 0x04 /* Enable parallel port ECP mode */ 138 #define PCR_ECP_POWER_DOWN_CLOCK_ENABLE 0x08 /* Enable clock in power-down state */ 139 /* 0: Freeze ECP clock */ 140 /* 1: Run ECP clock */ 141 #define PCR_ECP_INT_POLARITY_CONTROL 0x20 /* Interrupt polarity control */ 142 /* 0: Level high or negative pulse */ 143 /* 1: Level low or positive pulse */ 144 #define PCR_ECP_INT_IO_CONTROL 0x40 /* Interrupt I/O control */ 145 /* WARNING: Slightly safer to choose */ 146 /* open drain if you don't know the */ 147 /* exact requirements of the circuit */ 148 /* 0: Totem-pole output */ 149 /* 1: Open drain output */ 150 #define PCR_RTC_RAM_WRITE_DISABLE 0x80 /* Disable writes to RTC RAM */ 151 /* 0: Enable writes */ 152 /* 1: Disable writes */ 153 154 #define SIO_CONFIG_KRR 0x05 /* Keyboard & RTC Control Register */ 155 /* WARNING: The KRR register must be written */ 156 /* with a 1 in bit 2, else the KBC will not */ 157 /* work! */ 158 #define KRR_KBC_ENABLE 0x01 /* Enable keyboard controller */ 159 #define KRR_KBC_SPEED_CONTROL 0x02 /* Select clock divisor if !KRR[7] */ 160 /* 0: Divide by 3 */ 161 /* 1: Divide by 2 */ 162 #define KRR_KBC_MUST_BE_1 0x04 /* Reserved: This bit must be 1! */ 163 #define KRR_RTC_ENABLE 0x08 /* Enable real time clock */ 164 #define KRR_RTC_RAMSEL 0x20 /* Select RTC RAM bank */ 165 #define KRR_KBC_CLOCK_SOURCE_SELECT 0x80 /* Select clock source */ 166 /* 0: Use X1 clock source */ 167 /* 1: Use SYSCLK clock source */ 168 169 #define SIO_CONFIG_PMC 0x06 /* Power Management Control Register */ 170 171 #define PMC_IDE_TRISTATE_CONTROL 0x01 /* ? (power management) */ 172 #define PMC_FDC_TRISTATE_CONTROL 0x02 /* ? (power management) */ 173 #define PMC_UART1_TRISTATE_CONTROL 0x04 /* ? (power management) */ 174 #define PMC_SELECTIVE_LOCK 0x20 /* ? (power management) */ 175 #define PMC_LPT_TRISTATE_CONTROL 0x40 /* ? (power management) */ 176 177 #define SIO_CONFIG_TUP 0x07 /* Tape, UARTS & Parallel Port Register */ 178 179 #define TUP_EPP_TIMEOUT_INT_ENABLE 0x04 /* Enable EPP timeout interrupts */ 180 181 #define SIO_CONFIG_SID 0x08 /* Super I/O Identification Register */ 182 183 #define SID_ID_MASK 0xF8 /* Super I/O ID field */ 184 #define SID_ID_PC87306 0x70 /* PC87306 ID value */ 185 186 #define SIO_CONFIG_ASC 0x09 /* Advanced Super I/O Config Register */ 187 /* WARNING: The ASC register must be written */ 188 /* with a 0 in bit 3! */ 189 /* WARNING: The ASC register resets to 1 in */ 190 /* bit 7 (PC/AT mode)! */ 191 #define ASC_VLD_MASK 0x03 /* ? (floppy/tape) */ 192 #define ASC_ENHANCED_TDR_SUPPORT 0x04 /* ? (floppy/tape) */ 193 #define ASC_MUST_BE_0 0x08 /* Reserved: Must be 0 */ 194 #define ASC_ECP_CNFGA 0x20 /* ? */ 195 #define ASC_DENSEL_POLARITY_BIT 0x40 /* ? (floppy/tape) */ 196 #define ASC_SYSTEM_OPERATION_MODE 0x80 /* Select system operation mode */ 197 /* 0: PS/2 mode */ 198 /* 1: PC/AT mode */ 199 200 #define SIO_CONFIG_CS0LA 0x0A /* Chip Select 0 Low Address Register */ 201 202 #define SIO_CONFIG_CS0CF 0x0B /* Chip Select 0 Configuration Register */ 203 /* WARNING: The CS0CF register must be */ 204 /* written with a 1 in bit 7! */ 205 #define CS0CF_CS0_DECODE 0x08 /* Select CS0 decode sensitivity */ 206 /* 0: Decode full 16-bit address */ 207 /* 1: Decode only bits 15 thru 12 */ 208 #define CS0CF_CS0_WRITE_ENABLE 0x10 /* Enable CS0 on write cycles */ 209 #define CS0CF_CS0_READ_ENABLE 0x20 /* Enable CS0 on read cycles */ 210 #define CS0CF_CS0_MUST_BE_1 0x80 /* Reserved: Must be 1 */ 211 212 #define SIO_CONFIG_CS1LA 0x0C /* Chip Select 1 Low Address Register */ 213 214 #define SIO_CONFIG_CS1CF 0x0D /* Chip Select 1 Configuration Register */ 215 216 #define CS1CF_CS1_DECODE 0x08 /* Select CS1 decode sensitivity */ 217 /* 0: Decode full 16-bit address */ 218 /* 1: Decode only bits 15 thru 12 */ 219 #define CS1CF_CS1_WRITE_ENABLE 0x10 /* Enable CS1 on write cycles */ 220 #define CS1CF_CS1_READ_ENABLE 0x20 /* Enable CS1 on read cycles */ 221 222 #define SIO_CONFIG_IRC 0x0E /* Infrared Configuration Register */ 223 224 #define IRC_UART2_INTERFACE_MODE 0x01 /* Select UART2 interface mode */ 225 /* 0: Normal (modem) mode */ 226 /* 1: IR mode */ 227 #define IRC_IR_FULL_DUPLEX 0x02 /* Select IR duplex mode */ 228 /* 0: Full duplex mode */ 229 /* 1: Half duplex mode */ 230 #define IRC_ENCODED_IR_TRANSMITTER_DRIVE 0x10 /* IR transmitter drive control */ 231 /* 0: IRTX active for 1.6usec */ 232 /* 1: IRTX active for 3/16 baud */ 233 #define IRC_ENCODED_IR_MODE 0x20 /* IR encode mode */ 234 /* 0: Encoded mode */ 235 /* 1: Non-encoded mode */ 236 237 #define SIO_CONFIG_GPBA 0x0F /* GP I/O Port Base Address Config Register */ 238 239 #define SIO_CONFIG_CS0HA 0x10 /* Chip Select 0 High Address Register */ 240 241 #define SIO_CONFIG_CS1HA 0x11 /* Chip Select 1 High Address Register */ 242 243 #define SIO_CONFIG_SCF0 0x12 /* Super I/O Configuration Register 0 */ 244 245 #define SCF0_RTC_RAM_LOCK 0x01 /* Lock (1) will prevent all further */ 246 /* accesses to RTC RAM. Only RESET */ 247 /* return this bit to a 0. */ 248 #define SCF0_IRQ1_12_LATCH_ENABLE 0x02 /* Enable IRQ1/IRQ12 latching */ 249 #define SCF0_IRQ12_TRISTATE 0x04 /* IRQ12 tri-state control */ 250 /* 0: Use quasi-bidirectional buffer */ 251 /* 1: Tri-state IRQ12 */ 252 #define SCF0_UART2_TRISTATE 0x08 /* Force UART2/IR outputs to */ 253 /* tri-state when disabled */ 254 #define SCF0_GPIO_PORT1_ENABLE 0x10 /* Enable GPIO port 1 */ 255 #define SCF0_GPIO_PORT2_ENABLE 0x20 /* Enable GPIO port 2 */ 256 257 #define SIO_CONFIG_SCF1 0x18 /* Super I/O Configuration Register 1 */ 258 259 #define SCF1_REPORTED_ECP_DMA 0x06 /* Reported ECP DMA number */ 260 /* 0: Jumpered 8-bit DMA */ 261 /* 1: DMA channel 1 */ 262 /* 2: DMA channel 2 */ 263 /* 3: DMA channel 3 */ 264 #define SCF1_SELECTED_ECP_DMA 0x08 /* Selected ECP DMA pins */ 265 /* 0: PDRQ0 & PDACK0 */ 266 /* 1: PDRQ1 & PDACK1 */ 267 #define SCF1_SCRATCH_BITS 0xC0 /* ? */ 268 269 #define SIO_CONFIG_LPTBA 0x19 /* LPT Base Address */ 270 271 #define SIO_CONFIG_PNP0 0x1B /* Plug & Play Configuration Register 0 */ 272 273 #define PNP0_LPT_INT_SELECT_CONTROL 0x10 /* LPT IRQ select control */ 274 /* 0: IRQ selected by FAR[1:0] */ 275 /* 1: IRQ selected by PNP0[5] */ 276 #define PNP0_LPT_INT_MAPPING 0x20 /* LPT IRQ mapping */ 277 /* 0: IRQ5 */ 278 /* 1: IRQ7 */ 279 #define PNP0_LPTA_BASE_ADDR_SELECT 0x40 /* LPTA base address */ 280 /* 0: Always 0x3BC */ 281 /* 1: Selected by LPTBA[7:0] */ 282 283 #define SIO_CONFIG_PNP1 0x1C /* Plug & Play Configuration Register 1 */ 284 285 #define PNP1_UARTS_INT_SELECT_CONTROL 0x01 /* UART interrupt select control */ 286 /* 0: Use FAR[3:2] & FAR[5:4] */ 287 /* 1: Use PNP1[2] & PNP1[6] */ 288 #define PNP1_UART1_INT_MAPPING 0x04 /* UART1 interrupt mapping */ 289 /* 0: IRQ3 */ 290 /* 1: IRQ4 */ 291 #define PNP1_UART2_INT_MAPPING 0x40 /* UART2 interrupt mapping */ 292 /* 0: IRQ3 */ 293 /* 1: IRQ4 */ 294 /*---------------------------------------------------------------------------*/ 295 296 /* 297 * Definitions for the SuperIO UART. 298 */ 299 #define COM1_PORT 0x3f8 300 #define COM2_PORT 0x2f8 301 302 /* 303 * Register offsets. 304 */ 305 #define UART_RX 0 /* Receive port, read only */ 306 #define UART_TX 0 /* transmit port, write only */ 307 #define UART_IER 1 /* Interrupt enable, read/write */ 308 #define UART_IIR 2 /* Interrupt id, read only */ 309 #define UART_FIFO_CONTROL 2 /* FIFO control, write only */ 310 #define UART_LCR 3 /* Line control register */ 311 #define UART_MCR 4 /* Modem control register */ 312 #define UART_LSR 5 /* Line Status register */ 313 #define UART_MSR 6 /* Modem Status register */ 314 315 /* with the DLAB bit set, the first two registers contain the baud rate */ 316 #define UART_DLLSB 0 317 #define UART_DLMSB 1 318 319 /* 320 * Line control register 321 */ 322 #define LCR_DB 3 /* Data bits in transmission (0 = 5, 1 = 6, 2 = 7, 3 = 8) */ 323 #define LCR_SB 4 /* Stop bit */ 324 #define LCR_PE 8 /* Parity enable */ 325 #define LCR_EP 16 /* Even parity */ 326 #define LCR_SP 32 /* Stick parity */ 327 #define LCR_BC 64 /* break control */ 328 #define LCR_DLAB 128 /* Divisor latch access bit */ 329 330 331 /* 332 * Modem Control register 333 */ 334 #define MCR_DTR 1 /* Data Terminal Ready */ 335 #define MCR_RTS 2 /* Request To Send */ 336 #define MCR_OUT1 4 /* Out1 (not used) */ 337 #define MCR_IRQ_ENABLE 8 /* Enable IRQ */ 338 #define MCR_LOOP 16 /* Loopback mode */ 339 340 /* 341 * Line status bits. 342 */ 343 #define LSR_DR 0x01 /* Data ready */ 344 #define LSR_OE 0x02 /* Overrun error */ 345 #define LSR_PE 0x04 /* Parity error */ 346 #define LSR_FE 0x08 /* Framing error */ 347 #define LSR_BI 0x10 /* Break interrupt */ 348 #define LSR_THRE 0x20 /* Transmitter holding register empty */ 349 #define LSR_TEMT 0x40 /* Transmitter empty */ 350 #define LSR_FFE 0x80 /* Receiver FIFO error */ 351 352 #define LSR_ERROR (LSR_OE | LSR_PE | LSR_FE) 353 354 /* 355 * Interrupt Identification register (IIR) 356 */ 357 #define IIR_IP 1 /* No Interrupt pending */ 358 #define IIR_RECEIVE_LINE_STATUS 6 /* Overrun, Parity, Framing erros, Break */ 359 #define IIR_RDA 4 /* Receive data available */ 360 #define IIR_FIFO_FLAG 8 /* FIFO flag */ 361 #define IIR_FIFO_TIMEOUT (IIR_RDA+IIR_FIFO_FLAG) /* Got data some time ago, but FIFO time out */ 362 #define IIR_THRE 2 /* Transmitter holding register empty. */ 363 #define IIR_MS 0 /* CTS, DSR, RING, DCD changed */ 364 #define IIR_HPIP 6 /* Highest priority interrupt pending */ 365 366 /* 367 * Interrupt enable register (IER) 368 */ 369 #define IER_RDA 1 /* Received data available */ 370 #define IER_THRE 2 /* Transmitter holding register empty */ 371 #define IER_RLS 4 /* Receiver line status */ 372 #define IER_MS 8 /* Modem status */ 373 374 /* 375 * PC87306 Parallel I/O Port 376 */ 377 #define LPT1_PORT 0x03BC 378 379 /* 380 * PC87306 General Purpose I/O Ports 381 */ 382 #define GPIO1_PORT 0x0078 383 #define GPIO2_PORT 0x0079 384 385 /* 386 * PC87306 IDE Port 387 */ 388 #define IDE_PORT_1 0x01F0 389 #define IDE_PORT_2 0x03F6 390 #define IDE_PORT_3 0x03F7 391 392 /* 393 * PC87306 Floppy Port 394 */ 395 #define FDC_PORT 0x03F0 396 397 /* 398 * PC87306 Real Time Clock/battery backed up RAM port 399 */ 400 #define RTC_INDEX_PORT 0x0070 401 #define RTC_DATA_PORT 0x0071 402 403 /* 404 * Offsets in RTC memory (RAMSEL = 0) 405 */ 406 #define RTC_SECONDS 0 407 #define RTC_SECONDS_ALARM 1 408 #define RTC_MINUTES 2 409 #define RTC_MINUTES_ALARM 3 410 #define RTC_HOURS 4 411 #define RTC_HOURS_ALARM 5 412 #define RTC_DAY_OF_WEEK 6 413 #define RTC_DAY_OF_MONTH 7 414 #define RTC_MONTH 8 415 #define RTC_YEAR 9 416 #define RTC_CONTROL_A 0xA 417 #define RTC_CONTROL_B 0xB 418 #define RTC_CONTROL_C 0xC 419 #define RTC_CONTROL_D 0xD 420 421 #define RTC_NVRAM0_START 0xE 422 #define RTC_NVRAM0_SIZE 114 423 #define RTC_NVRAM1_START 0 424 #define RTC_NVRAM1_SIZE 128 425 #define RTC_NVRAM_SIZE (RTC_NVRAM0_SIZE+RTC_NVRAM1_SIZE) 426 427 #define RTC_PWNVRAM_START 0x38 /* Start of protected NVRAM */ 428 #define RTC_PWNVRAM_SIZE 8 /* Size of protected NVRAM */ 429 430 431 /* 432 * PC87306 Keyboard controller ports 433 */ 434 #define KEYBD_DATA_PORT 0x0060 435 #define KEYBD_CTRL_PORT 0x0064 436