1 /* 2 * PSR 3 */ 4 #define PsrMusr 0x10 /* mode */ 5 #define PsrMfiq 0x11 6 #define PsrMirq 0x12 7 #define PsrMsvc 0x13 8 #define PsrMabt 0x17 9 #define PsrMund 0x1B 10 #define PsrMsys 0x1F 11 #define PsrMask 0x1F 12 13 #define PsrDfiq 0x00000040 /* disable FIQ interrupts */ 14 #define PsrDirq 0x00000080 /* disable IRQ interrupts */ 15 16 #define PsrV 0x10000000 /* overflow */ 17 #define PsrC 0x20000000 /* carry/borrow/extend */ 18 #define PsrZ 0x40000000 /* zero */ 19 #define PsrN 0x80000000 /* negative/less than */ 20 21 /* 22 * Internal MMU coprocessor registers 23 */ 24 #define CpCPUID 0 /* R: */ 25 #define CpControl 1 /* R: */ 26 #define CpTTB 2 /* W: translation table base */ 27 #define CpDAC 3 /* W: domain access control */ 28 #define CpFSR 5 /* R: fault status */ 29 #define CpTLBflush 5 /* W: */ 30 #define CpFAR 6 /* R: fault address */ 31 #define CpTLBpurge 6 /* W: */ 32 #define CpCacheCtl 7 /* W: */ 33 34 #define CpDebug 14 /* R/W: debug registers */ 35 /* 36 * Coprocessors 37 */ 38 #define CpMMU 15 39 40 /* 41 * Internal MMU coprocessor registers 42 */ 43 #define CpCmmu 0x00000001 /* M: MMU enable */ 44 #define CpCalign 0x00000002 /* A: alignment fault enable */ 45 #define CpCDcache 0x00000004 /* C: instruction/data cache on */ 46 #define CpCwb 0x00000008 /* W: write buffer turned on */ 47 #define CpCi32 0x00000010 /* P: 32-bit programme space */ 48 #define CpCd32 0x00000020 /* D: 32-bit data space */ 49 #define CpCbe 0x00000080 /* B: big-endian operation */ 50 #define CpCsystem 0x00000100 /* S: system permission */ 51 #define CpCrom 0x00000200 /* R: ROM permission */ 52 #define CpCIcache 0x00001000 /* C: Instruction Cache on */ 53 54 /* 55 * Debug support internal registers 56 */ 57 #define CpDBAR 0 58 #define CpDBVR 1 59 #define CpDBMR 2 60 #define CpDBCR 3 61 #define CpIBCR 8 62 /* 63 * MMU 64 */ 65 /* 66 * Small pages: 67 * L1: 12-bit index -> 4096 descriptors -> 16Kb 68 * L2: 8-bit index -> 256 descriptors -> 1Kb 69 * Each L2 descriptor has access permissions for 4 1Kb sub-pages. 70 * 71 * TTB + L1Tx gives address of L1 descriptor 72 * L1 descriptor gives PTBA 73 * PTBA + L2Tx gives address of L2 descriptor 74 * L2 descriptor gives PBA 75 */ 76 #define MmuTTB(pa) ((pa) & ~0x3FFF) /* translation table base */ 77 #define MmuL1x(pa) (((pa)>>20) & 0xFFF) /* L1 table index */ 78 #define MmuPTBA(pa) ((pa) & ~0x3FF) /* page table base address */ 79 #define MmuL2x(pa) (((pa)>>12) & 0xFF) /* L2 table index */ 80 #define MmuPBA(pa) ((pa) & ~0xFFF) /* page base address */ 81 #define MmuSBA(pa) ((pa) & ~0xFFFFF) /* section base address */ 82 83 #define MmuL1page 0x011 /* descriptor is for L2 pages */ 84 #define MmuL1section 0x012 /* descriptor is for section */ 85 86 #define MmuL2invalid 0x000 87 #define MmuL2large 0x001 /* large */ 88 #define MmuL2small 0x002 /* small */ 89 #define MmuWB 0x004 /* data goes through write buffer */ 90 #define MmuIDC 0x008 /* data placed in cache */ 91 92 #define MmuDAC(d) (((d) & 0xF)<<5) /* L1 domain */ 93 #define MmuAP(i, v) ((v)<<(((i)*2)+4)) /* access permissions */ 94 #define MmuL1AP(v) MmuAP(3, (v)) 95 #define MmuL2AP(v) MmuAP(3, (v))|MmuAP(2, (v))|MmuAP(1, (v))|MmuAP(0, (v)) 96 #define MmuAPsro 0 /* supervisor rw */ 97 #define MmuAPsrw 1 /* supervisor rw */ 98 #define MmuAPuro 2 /* supervisor rw + user ro */ 99 #define MmuAPurw 3 /* supervisor rw + user rw */ 100