1 #include "u.h"
2 #include "lib.h"
3 #include "mem.h"
4 #include "dat.h"
5 #include "fns.h"
6 #include "io.h"
7 #include "ureg.h"
8
9 void intr0(void), intr1(void), intr2(void), intr3(void);
10 void intr4(void), intr5(void), intr6(void), intr7(void);
11 void intr8(void), intr9(void), intr10(void), intr11(void);
12 void intr12(void), intr13(void), intr14(void), intr15(void);
13 void intr16(void);
14 void intr24(void), intr25(void), intr26(void), intr27(void);
15 void intr28(void), intr29(void), intr30(void), intr31(void);
16 void intr32(void), intr33(void), intr34(void), intr35(void);
17 void intr36(void), intr37(void), intr38(void), intr39(void);
18 void intr64(void);
19 void intrbad(void);
20
21 /*
22 * 8259 interrupt controllers
23 */
24 enum
25 {
26 Int0ctl= 0x20, /* control port (ICW1, OCW2, OCW3) */
27 Int0aux= 0x21, /* everything else (ICW2, ICW3, ICW4, OCW1) */
28 Int1ctl= 0xA0, /* control port */
29 Int1aux= 0xA1, /* everything else (ICW2, ICW3, ICW4, OCW1) */
30
31 Icw1= 0x10, /* select bit in ctl register */
32 Ocw2= 0x00,
33 Ocw3= 0x08,
34
35 EOI= 0x20, /* non-specific end of interrupt */
36
37 Elcr1= 0x4D0, /* Edge/Level Triggered Register */
38 Elcr2= 0x4D1,
39 };
40
41 int int0mask = 0xff; /* interrupts enabled for first 8259 */
42 int int1mask = 0xff; /* interrupts enabled for second 8259 */
43 int i8259elcr; /* mask of level-triggered interrupts */
44
45 /*
46 * trap/interrupt gates
47 */
48 Segdesc ilt[256];
49
50 enum
51 {
52 Maxhandler= 32, /* max number of interrupt handlers */
53 };
54
55 typedef struct Handler Handler;
56 struct Handler
57 {
58 void (*r)(Ureg*, void*);
59 void *arg;
60 Handler *next;
61 };
62
63 struct
64 {
65 Handler *ivec[256];
66 Handler h[Maxhandler];
67 int nextfree;
68 } halloc;
69
70 void
sethvec(int v,void (* r)(void),int type,int pri)71 sethvec(int v, void (*r)(void), int type, int pri)
72 {
73 ilt[v].d0 = ((ulong)r)&0xFFFF|(KESEL<<16);
74 ilt[v].d1 = ((ulong)r)&0xFFFF0000|SEGP|SEGPL(pri)|type;
75 }
76
77 void
setvec(int v,void (* r)(Ureg *,void *),void * arg)78 setvec(int v, void (*r)(Ureg*, void*), void *arg)
79 {
80 Handler *h;
81
82 if(halloc.nextfree >= Maxhandler)
83 panic("out of interrupt handlers");
84 h = &halloc.h[halloc.nextfree++];
85 h->next = halloc.ivec[v];
86 h->r = r;
87 h->arg = arg;
88 halloc.ivec[v] = h;
89
90 /*
91 * enable corresponding interrupt in 8259
92 */
93 if((v&~0x7) == VectorPIC){
94 int0mask &= ~(1<<(v&7));
95 outb(Int0aux, int0mask);
96 } else if((v&~0x7) == VectorPIC+8){
97 int1mask &= ~(1<<(v&7));
98 outb(Int1aux, int1mask);
99 }
100 }
101
102 void
trapdisable(void)103 trapdisable(void)
104 {
105 outb(Int0aux, 0xFF);
106 outb(Int1aux, 0xFF);
107 }
108
109 void
trapenable(void)110 trapenable(void)
111 {
112 outb(Int0aux, int0mask);
113 outb(Int1aux, int1mask);
114 }
115
116
117 /*
118 * set up the interrupt/trap gates
119 */
120 void
trapinit(void)121 trapinit(void)
122 {
123 int i, x;
124
125 /*
126 * set all interrupts to panics
127 */
128 for(i = 0; i < 256; i++)
129 sethvec(i, intrbad, SEGTG, 0);
130
131 /*
132 * 80386 processor (and coprocessor) traps
133 */
134 sethvec(0, intr0, SEGTG, 0);
135 sethvec(1, intr1, SEGTG, 0);
136 sethvec(2, intr2, SEGTG, 0);
137 sethvec(3, intr3, SEGTG, 0);
138 sethvec(4, intr4, SEGTG, 0);
139 sethvec(5, intr5, SEGTG, 0);
140 sethvec(6, intr6, SEGTG, 0);
141 sethvec(7, intr7, SEGTG, 0);
142 sethvec(8, intr8, SEGTG, 0);
143 sethvec(9, intr9, SEGTG, 0);
144 sethvec(10, intr10, SEGTG, 0);
145 sethvec(11, intr11, SEGTG, 0);
146 sethvec(12, intr12, SEGTG, 0);
147 sethvec(13, intr13, SEGTG, 0);
148 sethvec(14, intr14, SEGTG, 0);
149 sethvec(15, intr15, SEGTG, 0);
150 sethvec(16, intr16, SEGTG, 0);
151
152 /*
153 * device interrupts
154 */
155 sethvec(24, intr24, SEGIG, 0);
156 sethvec(25, intr25, SEGIG, 0);
157 sethvec(26, intr26, SEGIG, 0);
158 sethvec(27, intr27, SEGIG, 0);
159 sethvec(28, intr28, SEGIG, 0);
160 sethvec(29, intr29, SEGIG, 0);
161 sethvec(30, intr30, SEGIG, 0);
162 sethvec(31, intr31, SEGIG, 0);
163 sethvec(32, intr32, SEGIG, 0);
164 sethvec(33, intr33, SEGIG, 0);
165 sethvec(34, intr34, SEGIG, 0);
166 sethvec(35, intr35, SEGIG, 0);
167 sethvec(36, intr36, SEGIG, 0);
168 sethvec(37, intr37, SEGIG, 0);
169 sethvec(38, intr38, SEGIG, 0);
170 sethvec(39, intr39, SEGIG, 0);
171
172 /*
173 * tell the hardware where the table is (and how long)
174 */
175 putidt(ilt, sizeof(ilt)-1);
176
177 /*
178 * Set up the first 8259 interrupt processor.
179 * Make 8259 interrupts start at CPU vector VectorPIC.
180 * Set the 8259 as master with edge triggered
181 * input with fully nested interrupts.
182 */
183 outb(Int0ctl, Icw1|0x01); /* ICW1 - edge triggered, master,
184 ICW4 will be sent */
185 outb(Int0aux, VectorPIC); /* ICW2 - interrupt vector offset */
186 outb(Int0aux, 0x04); /* ICW3 - have slave on level 2 */
187 outb(Int0aux, 0x01); /* ICW4 - 8086 mode, not buffered */
188
189 /*
190 * Set up the second 8259 interrupt processor.
191 * Make 8259 interrupts start at CPU vector VectorPIC+8.
192 * Set the 8259 as master with edge triggered
193 * input with fully nested interrupts.
194 */
195 outb(Int1ctl, Icw1|0x01); /* ICW1 - edge triggered, master,
196 ICW4 will be sent */
197 outb(Int1aux, VectorPIC+8); /* ICW2 - interrupt vector offset */
198 outb(Int1aux, 0x02); /* ICW3 - I am a slave on level 2 */
199 outb(Int1aux, 0x01); /* ICW4 - 8086 mode, not buffered */
200 outb(Int1aux, int1mask);
201
202 /*
203 * pass #2 8259 interrupts to #1
204 */
205 int0mask &= ~0x04;
206 outb(Int0aux, int0mask);
207
208 /*
209 * Set Ocw3 to return the ISR when ctl read.
210 */
211 outb(Int0ctl, Ocw3|0x03);
212 outb(Int1ctl, Ocw3|0x03);
213
214 /*
215 * Check for Edge/Level register.
216 * This check may not work for all chipsets.
217 * First try a non-intrusive test - the bits for
218 * IRQs 13, 8, 2, 1 and 0 must be edge (0). If
219 * that's OK try a R/W test.
220 */
221 x = (inb(Elcr2)<<8)|inb(Elcr1);
222 if(!(x & 0x2107)){
223 outb(Elcr1, 0);
224 if(inb(Elcr1) == 0){
225 outb(Elcr1, 0x20);
226 if(inb(Elcr1) == 0x20)
227 i8259elcr = x;
228 outb(Elcr1, x & 0xFF);
229 print("ELCR: %4.4uX\n", i8259elcr);
230 }
231 }
232 }
233
234 /*
235 * dump registers
236 */
237 static void
dumpregs(Ureg * ur)238 dumpregs(Ureg *ur)
239 {
240 print("FLAGS=%lux TRAP=%lux ECODE=%lux PC=%lux\n",
241 ur->flags, ur->trap, ur->ecode, ur->pc);
242 print(" AX %8.8lux BX %8.8lux CX %8.8lux DX %8.8lux\n",
243 ur->ax, ur->bx, ur->cx, ur->dx);
244 print(" SI %8.8lux DI %8.8lux BP %8.8lux\n",
245 ur->si, ur->di, ur->bp);
246 print(" CS %4.4lux DS %4.4lux ES %4.4lux FS %4.4lux GS %4.4lux\n",
247 ur->cs & 0xFF, ur->ds & 0xFFFF, ur->es & 0xFFFF, ur->fs & 0xFFFF, ur->gs & 0xFFFF);
248 print(" CR0 %8.8lux CR2 %8.8lux CR3 %8.8lux\n",
249 getcr0(), getcr2(), getcr3());
250 }
251
252 /*
253 * All traps
254 */
255 void
trap(Ureg * ur)256 trap(Ureg *ur)
257 {
258 int v;
259 int c;
260 Handler *h;
261 ushort isr;
262
263 v = ur->trap;
264 /*
265 * tell the 8259 that we're done with the
266 * highest level interrupt (interrupts are still
267 * off at this point)
268 */
269 c = v&~0x7;
270 isr = 0;
271 if(c==VectorPIC || c==VectorPIC+8){
272 isr = inb(Int0ctl);
273 outb(Int0ctl, EOI);
274 if(c == VectorPIC+8){
275 isr |= inb(Int1ctl)<<8;
276 outb(Int1ctl, EOI);
277 }
278 }
279
280 if(v>=256 || (h = halloc.ivec[v]) == 0){
281 if(v >= VectorPIC && v < VectorPIC+16){
282 v -= VectorPIC;
283 /*
284 * Check for a default IRQ7. This can happen when
285 * the IRQ input goes away before the acknowledge.
286 * In this case, a 'default IRQ7' is generated, but
287 * the corresponding bit in the ISR isn't set.
288 * In fact, just ignore all such interrupts.
289 */
290 if(isr & (1<<v))
291 print("unknown interrupt %d pc=0x%lux\n", v, ur->pc);
292 return;
293 }
294
295 switch(v){
296
297 case 0x02: /* NMI */
298 print("NMI: nmisc=0x%2.2ux, nmiertc=0x%2.2ux, nmiesc=0x%2.2ux\n",
299 inb(0x61), inb(0x70), inb(0x461));
300 return;
301
302 default:
303 dumpregs(ur);
304 panic("exception/interrupt %d", v);
305 return;
306 }
307 }
308
309 /*
310 * call the trap routines
311 */
312 do {
313 (*h->r)(ur, h->arg);
314 h = h->next;
315 } while(h);
316 }
317
318 extern void realmode0(void); /* in l.s */
319
320 extern int realmodeintr;
321 extern Ureg realmoderegs;
322
323 void
realmode(int intr,Ureg * ureg)324 realmode(int intr, Ureg *ureg)
325 {
326 realmoderegs = *ureg;
327 realmodeintr = intr;
328 trapdisable();
329 realmode0();
330 trapenable();
331 *ureg = realmoderegs;
332 }
333