xref: /inferno-os/os/boot/mpc/l.s (revision 74a4d8c26dd3c1e9febcb717cfd6cb6512991a7a) 
1#include "mem.h"
2
3/* special instruction definitions */
4#define	BDNE	BC	0,2,
5#define	BDNZ	BC	16,0,
6#define	NOOP	OR	R0,R0,R0
7
8/*
9 * common ppc special purpose registers
10 */
11#define DSISR	18
12#define DAR	19	/* Data Address Register */
13#define DEC	22	/* Decrementer */
14#define SRR0	26	/* Saved Registers (exception) */
15#define SRR1	27
16#define SPRG0	272	/* Supervisor Private Registers */
17#define SPRG1	273
18#define SPRG2	274
19#define SPRG3	275
20#define TBRU	269	/* Time base Upper/Lower (Reading) */
21#define TBRL	268
22#define TBWU	285	/* Time base Upper/Lower (Writing) */
23#define TBWL	284
24#define PVR	287	/* Processor Version */
25
26/*
27 * mpc82x-specific special purpose registers of interest here
28 */
29#define EIE	80
30#define EID	81
31#define NRI	82
32#define IMMR	638
33#define IC_CST	560
34#define IC_ADR	561
35#define IC_DAT	562
36#define DC_CST	568
37#define DC_ADR	569
38#define DC_DAT	570
39#define MI_CTR	784
40#define MI_AP	786
41#define MI_EPN	787
42#define MI_TWC	789
43#define MI_RPN	790
44#define MI_DBCAM	816
45#define MI_DBRAM0	817
46#define MI_DBRAM1	818
47#define MD_CTR	792
48#define M_CASID	793
49#define MD_AP	794
50#define MD_EPN	795
51#define M_TWB	796
52#define MD_TWC	797
53#define MD_RPN	798
54#define	M_TW	799
55#define	MD_DBCAM	824
56#define	MD_DBRAM0	825
57#define	MD_DBRAM1	826
58
59/* as on 603e, apparently mtmsr needs help in some chip revisions */
60#define	WAITMSR	SYNC; ISYNC
61
62/* use of SPRG registers in save/restore */
63#define	SAVER0	SPRG0
64#define	SAVER1	SPRG1
65#define	SAVELR	SPRG2
66#define	SAVECR	SPRG3
67
68#define	UREGSIZE	((8+32)*4)
69#define	UREGSPACE	(UREGSIZE+8)	/* allow for arg to trap, and align */
70
71/*
72 * This code is loaded by the ROM loader at location 0x3000,
73 * or lives in flash memory at 0x2800100.
74 * Move it to high memory so that it can load the kernel at 0x0000.
75 */
76
77#define LOADCODEBASE	0x3000	/* when downloaded in S records */
78#define FLASHCODEBASE	(FLASHMEM+0x100)	/* when in flash */
79
80	TEXT	start(SB), $-4
81	MOVW	MSR, R3
82	MOVW	$(EE|IP|RI), R4
83	ANDN	R4, R3
84	OR	$ME, R3
85	SYNC
86	MOVW	R3, MSR	/* turn off interrupts but enable traps */
87	WAITMSR
88
89/*
90 * reset the caches and disable them for now
91 */
92	MOVW	SPR(IC_CST), R4	/* read and clear */
93	MOVW	$(5<<25), R4
94	MOVW	R4, SPR(IC_CST)	/* unlock all */
95	ISYNC
96	MOVW	$(6<<25), R4
97	MOVW	R4, SPR(IC_CST)	/* invalidate all */
98	ISYNC
99	MOVW	$(2<<25), R4
100	MOVW	R4, SPR(IC_CST)	/* disable i-cache */
101	ISYNC
102
103	SYNC
104	MOVW	SPR(DC_CST), R4	/* read and clear */
105	MOVW	$(10<<24), R4
106	MOVW	R4, SPR(DC_CST)	/* unlock all */
107	ISYNC
108	MOVW	$(12<<24), R4
109	MOVW	R4, SPR(DC_CST)	/* invalidate all */
110	ISYNC
111	MOVW	$(4<<24), R4
112	MOVW	R4, SPR(DC_CST)	/* disable i-cache */
113	ISYNC
114
115	MOVW	$7, R4
116ANDN R4, R4, R4
117	MOVW	R4, SPR(158)		/* cancel `show cycle' for normal instruction execution */
118
119/*
120 * set other system configuration values
121 */
122	MOVW	SPR(IMMR), R5		/* save initial space pointer */
123	MOVW	$INTMEM, R4
124	MOVW	R4, SPR(IMMR)		/* set internal memory base */
125	MOVW	$0xFFFFFF88, R3
126	MOVW	R3, 4(R4)	/* disable watchdog in sypcr */
127	MOVW	$0x01012440, R3
128	MOVW	R3, 0(R4)	/* siumcr */
129
130/*
131 * system initialisation (init and map DRAM)
132 */
133	MOVW	$0, R0
134	MOVW	$setSB(SB), R2
135	MOVW	$(0xF000<<16), R3
136/*MOVW R0, R3*/
137	ANDCC	R5, R3	/* initial space is high? */
138	BEQ	notrom
139	MOVW	$FLASHCODEBASE, R5	/* where $start(SB) actually is now */
140	MOVW	$start(SB), R4	/* logical start address */
141	SUB	R4, R5, R6	/* text relocation value */
142	MOVW	$etext(SB), R7
143	SUB	R4, R7
144	ADD	R5, R7	/* data address in ROM */
145	MOVW	$bdata(SB), R8
146	SUB	R8, R2
147	ADD	R7, R2	/* relocate SB: SB' = romdata+(SB-bdata) */
148	MOVW	$sysinit0(SB), R4
149	ADD	R6, R4	/* relocate sysinit0's address */
150	MOVW	R4, CTR
151	MOVW	$inmem(SB), R4
152	ADD	R6, R4
153	MOVW	R4, LR	/* and the return address */
154	BR	(CTR)	/* call sysinit0 */
155	TEXT	inmem(SB), $-4
156	MOVW	$FLASHCODEBASE, R3
157	BR	cpu0
158notrom:
159	MOVW	$start(SB), R6
160	SUB	R6, R2
161	ADD	$LOADCODEBASE, R2
162	BL	sysinit0(SB)
163	MOVW	$LOADCODEBASE, R3
164
165/*
166 * cpu 0
167 *	relocate bootstrap to our link addresses for text and data
168 *	set new PC
169 */
170cpu0:
171	MOVW	$setSB(SB), R2	/* set correct static base register */
172	MOVW	$start(SB), R4
173	MOVW	$etext(SB), R5
174	SUB	R4, R5
175	CMP	R4, R3	/* already there? */
176	BNE	copytext
177	ADD	R5, R3	/* start of data image */
178	BR	copydata
179
180copytext:
181	ADD	$3, R5
182	SRAW	$2, R5
183	MOVW	R5, CTR
184	SUB	$4, R4
185	SUB	$4, R3
186copyt:			/* copy text */
187	MOVWU	4(R3), R5
188	MOVWU	R5, 4(R4)
189	BDNZ	copyt
190	ADD	$4, R3
191
192copydata:
193	/* copy data */
194	MOVW	$bdata(SB), R4
195	CMP	R4, R3	/* already there? */
196	BEQ	loadkpc
197	MOVW	$edata(SB), R5
198	SUB	R4, R5
199	ADD	$3, R5
200	SRAW	$2, R5
201	MOVW	R5, CTR
202	SUB	$4, R4
203	SUB	$4, R3
204copyd:
205	MOVWU	4(R3), R5
206	MOVWU	R5, 4(R4)
207	BDNZ	copyd
208
209	/* load correct PC */
210loadkpc:
211	MOVW	$start1(SB), R3
212	MOVW	R3, LR
213	BR	(LR)
214TEXT start1(SB), $-4
215	MOVW	$edata(SB), R3
216	MOVW	$end(SB), R4
217	SUBCC	R3, R4
218	BLE	skipz
219	SRAW	$2, R4
220	MOVW	R4, CTR
221	SUB	$4, R3
222	MOVW	$0, R0
223zero:
224	MOVWU	R0, 4(R3)
225	BDNZ	zero
226skipz:
227	MOVW	$mach0(SB), R1
228	MOVW	R1, m(SB)
229	ADD	$(MACHSIZE-8), R1
230	MOVW	$0, R0
231	BL	main(SB)
232	BR	0(PC)
233
234TEXT	getmsr(SB), $0
235	MOVW	MSR, R3
236	RETURN
237
238TEXT	putmsr(SB), $0
239	SYNC
240	MOVW	R3, MSR
241	WAITMSR
242	RETURN
243
244TEXT	eieio(SB), $0
245	EIEIO
246	RETURN
247
248TEXT	idle(SB), $0
249	RETURN
250
251TEXT	spllo(SB), $0
252	MOVW	MSR, R3
253	OR	$EE, R3, R4
254	SYNC
255	MOVW	R4, MSR
256	WAITMSR
257	RETURN
258
259TEXT	splhi(SB), $0
260	MOVW	MSR, R3
261	RLWNM	$0, R3, $~EE, R4
262	SYNC
263	MOVW	R4, MSR
264	WAITMSR
265	RETURN
266
267TEXT	splx(SB), $0
268	MOVW	MSR, R4
269	RLWMI	$0, R3, $EE, R4
270	SYNC
271	MOVW	R4, MSR
272	WAITMSR
273	RETURN
274
275TEXT	gettbl(SB), $0
276/*	MOVW	SPR(TBRL), R3	*/
277	WORD	$0x7c6c42e6	/* mftbl on 8xx series */
278	RETURN
279
280TEXT	getpvr(SB), $0
281	MOVW	SPR(PVR), R3
282	RETURN
283
284TEXT	getimmr(SB), $0
285	MOVW	SPR(IMMR), R3
286	RETURN
287
288TEXT	getdec(SB), $0
289	MOVW	SPR(DEC), R3
290	RETURN
291
292TEXT	putdec(SB), $0
293	MOVW	R3, SPR(DEC)
294	RETURN
295
296/*
297 * save state in Ureg on kernel stack.
298 * enter with R0 giving the PC from the call to `exception' from the vector.
299 * on return, SB (R2) has been set, and R3 has the Ureg*
300 */
301TEXT saveureg(SB), $-4
302	SUB	$UREGSPACE, R1
303	MOVMW	R2, 48(R1)	/* r2:r31 */
304	MOVW	$setSB(SB), R2
305	MOVW	SPR(SAVER1), R4
306	MOVW	R4, 44(R1)
307	MOVW	SPR(SAVER0), R5
308	MOVW	R5, 40(R1)
309	MOVW	CTR, R6
310	MOVW	R6, 36(R1)
311	MOVW	XER, R4
312	MOVW	R4, 32(R1)
313	MOVW	SPR(SAVECR), R5	/* CR */
314	MOVW	R5, 28(R1)
315	MOVW	SPR(SAVELR), R6	/* LR */
316	MOVW	R6, 24(R1)
317	/* pad at 20(R1) */
318	MOVW	SPR(SRR0), R4
319	MOVW	R4, 16(R1)	/* old PC */
320	MOVW	SPR(SRR1), R5
321	MOVW	R5, 12(R1)
322	MOVW	R0, 8(R1)	/* cause/vector, encoded in LR from vector */
323	ADD	$8, R1, R3	/* Ureg* */
324	STWCCC	R3, (R1)	/* break any pending reservations */
325	MOVW	$0, R0	/* R0ISZERO */
326	BR	(LR)
327
328/*
329 * restore state from Ureg
330 * SB (R2) is unusable on return
331 */
332TEXT restoreureg(SB), $-4
333	MOVMW	48(R1), R2	/* r2:r31 */
334	/* defer R1 */
335	MOVW	40(R1), R0
336	MOVW	R0, SPR(SAVER0)
337	MOVW	36(R1), R0
338	MOVW	R0, CTR
339	MOVW	32(R1), R0
340	MOVW	R0, XER
341	MOVW	28(R1), R0
342	MOVW	R0, CR	/* CR */
343	MOVW	24(R1), R0
344	MOVW	R0, SPR(SAVELR)	/* LR */
345	/* pad, skip */
346	MOVW	16(R1), R0
347	MOVW	R0, SPR(SRR0)	/* old PC */
348	MOVW	12(R1), R0
349	MOVW	R0, SPR(SRR1)	/* old MSR */
350	/* cause, skip */
351	MOVW	44(R1), R1	/* old SP */
352	BR	(LR)
353
354TEXT	exception(SB), $-4
355	MOVW	R1, SPR(SAVER1)
356	MOVW	CR, R0
357	MOVW	R0, SPR(SAVECR)
358	MOVW	LR, R0
359	BL	saveureg(SB)
360	MOVW	$0, R0
361	BL	trap(SB)
362	BL	restoreureg(SB)
363	MOVW	SPR(SAVELR), R0
364	MOVW	R0, LR
365	MOVW	SPR(SAVER0), R0
366	ISYNC
367	RFI
368
369GLOBL	mach0+0(SB), $MACHSIZE
370GLOBL	m(SB), $4
371