1 enum 2 { 3 /* software interrupt vectors (SIU and CPM) */ 4 VectorPIC= 0, /* level 0 to level 7, assigned by software */ 5 CPIClevel= 4, 6 VectorIRQ= VectorPIC+8, /* IRQ0 to IRQ7 */ 7 VectorCPIC= VectorIRQ+8, /* 32 CPM interrupts: 0 (error) to 0x1F (PC15) */ 8 }; 9 10 enum 11 { 12 BUSUNKNOWN = 0, 13 }; 14 15 /* 16 * Buffer Descriptors and IO Rings 17 */ 18 19 typedef struct BD BD; 20 struct BD { 21 ushort status; 22 ushort length; 23 ulong addr; 24 }; 25 26 BD* bdalloc(int); 27 void bdfree(BD*, int); 28 29 enum { 30 /* Rx BDs, bits common to all protocols */ 31 BDEmpty= 1<<15, 32 BDWrap= 1<<13, 33 BDInt= 1<<12, 34 BDLast= 1<<11, 35 BDFirst= 1<<10, 36 37 /* Tx BDs */ 38 BDReady= 1<<15, 39 /* BDWrap, BDInt, BDLast */ 40 }; 41 42 typedef struct Ring Ring; 43 struct Ring { 44 BD* rdr; /* receive descriptor ring */ 45 void* rrb; /* receive ring buffers */ 46 int rdrx; /* index into rdr */ 47 int nrdre; /* length of rdr */ 48 49 BD* tdr; /* transmit descriptor ring */ 50 Block** txb; /* corresponding transmit ring buffers */ 51 int tdrh; /* host index into tdr */ 52 int tdri; /* interface index into tdr */ 53 int ntdre; /* length of tdr */ 54 int ntq; /* pending transmit requests */ 55 }; 56 57 #define NEXT(x, l) (((x)+1)%(l)) 58 #define PREV(x, l) (((x) == 0) ? (l)-1: (x)-1) 59 #define HOWMANY(x, y) (((x)+((y)-1))/(y)) 60 #define ROUNDUP(x, y) (HOWMANY((x), (y))*(y)) 61 62 int ioringinit(Ring*, int, int, int); 63 64 /* 65 * CPM 66 */ 67 enum { 68 /* commands */ 69 InitRxTx = 0, 70 InitRx = 1, 71 InitTx = 2, 72 EnterHunt= 3, 73 StopTx= 4, 74 GracefulStopTx = 5, 75 InitIDMA = 5, 76 RestartTx = 6, 77 CloseRxBD = 7, 78 SetGroupAddr = 8, 79 SetTimer = 8, 80 GCITimeout = 9, 81 GCIAbort = 10, 82 StopIDMA = 11, 83 StartDSP = 12, 84 ArmIDMA = 13, 85 InitDSP = 13, 86 USBCmd = 15, 87 88 /* channel IDs */ 89 SCC1ID= 0, 90 USBID= 0, 91 I2CID= 1, 92 IDMA1ID= 1, 93 SCC2ID= 4, 94 SPIID= 5, 95 IDMA2ID= 5, 96 TIMERID= 5, 97 SCC3ID= 8, 98 SMC1ID= 9, 99 DSP1ID=9, 100 SCC4ID= 12, 101 SMC2ID= 13, 102 DSP2ID= 13, 103 104 BaudEnable = 1<<16, 105 106 /* sicr */ 107 CLK1 = 4, /* SCC1,2 */ 108 CLK2 = 5, 109 CLK3 = 6, 110 CLK4 = 7, 111 CLK5 = CLK1, /* SCC3,4 */ 112 CLK6 = CLK2, 113 CLK7 = CLK3, 114 CLK8 = CLK4, 115 }; 116 117 void cpmop(int, int, int); 118 #define ioplock() (m->iomem) 119 #define iopunlock() 120 121 /* 122 * the structures below follow hardware/firmware layouts in the 8xx manuals: 123 * mind the data types, offsets and alignment 124 */ 125 126 /* 127 * basic IO controller parameters (SMC and SCC) 128 */ 129 typedef struct IOCparam IOCparam; 130 struct IOCparam { 131 ushort rbase; 132 ushort tbase; 133 uchar rfcr; 134 uchar tfcr; 135 ushort mrblr; 136 ulong rstate; 137 ulong rptr; 138 ushort rbptr; 139 ushort rcnt; 140 ulong rtmp; 141 ulong tstate; 142 ulong tptr; 143 ushort tbptr; 144 ushort tcnt; 145 ulong ttmp; 146 }; 147 148 typedef struct SCCparam SCCparam; 149 struct SCCparam { 150 IOCparam; 151 ulong rcrc; 152 ulong tcrc; 153 }; 154 155 typedef struct SCC SCC; 156 struct SCC { 157 ulong gsmrl; 158 ulong gsmrh; 159 ushort psmr; 160 uchar rsvscc0[2]; 161 ushort todr; 162 ushort dsr; 163 ushort scce; 164 uchar rsvscc1[2]; 165 ushort sccm; 166 uchar rsvscc3; 167 uchar sccs; 168 ushort irmode; 169 ushort irsip; 170 }; 171 172 typedef struct SMC SMC; 173 struct SMC { 174 uchar pad1[2]; 175 ushort smcmr; 176 uchar pad2[2]; 177 uchar smce; 178 uchar pad3[3]; 179 uchar smcm; 180 uchar pad4[5]; 181 }; 182 183 typedef struct SPI SPI; 184 struct SPI { 185 ushort spmode; 186 uchar res1[4]; 187 uchar spie; 188 uchar res2[3]; 189 uchar spim; 190 uchar res3[2]; 191 uchar spcom; 192 uchar res4[10]; 193 }; 194 195 typedef struct USB USB; 196 struct USB { /* 823 only */ 197 uchar usmod; 198 uchar usadr; 199 uchar uscom; 200 uchar rsvu1; 201 ushort usep[4]; 202 uchar rsvu2[4]; 203 ushort usber; 204 uchar rsvu3[2]; 205 ushort usbmr; 206 uchar rsvu4; 207 uchar usbs; 208 uchar rsvu5[8]; 209 }; 210 211 typedef struct IMM IMM; 212 struct IMM { 213 struct { /* general SIU */ 214 ulong siumcr; 215 ulong sypcr; 216 uchar rsv0[0xE-0x8]; 217 ushort swsr; 218 ulong sipend; 219 ulong simask; 220 ulong siel; 221 uchar sivec; 222 uchar padv[3]; 223 ulong tesr; 224 uchar rsv1[0x30-0x24]; 225 ulong sdcr; 226 uchar rsv2[0x80-0x34]; 227 }; 228 struct { /* PCMCIA */ 229 struct { 230 ulong base; 231 ulong option; 232 } pcmr[8]; 233 uchar rsv3[0xe0-0xc0]; 234 ulong pgcra; 235 ulong pgcrb; 236 ulong pscr; 237 uchar rsv4[0xf0-0xec]; 238 ulong pipr; 239 uchar rsv5[4]; 240 ulong per; 241 uchar rsv6[4]; 242 }; 243 struct { /* MEMC */ 244 struct { 245 ulong base; 246 ulong option; 247 } memc[8]; 248 uchar rsv7a[0x24]; 249 ulong mar; 250 ulong mcr; 251 uchar rsv7b[4]; 252 ulong mamr; 253 ulong mbmr; 254 ushort mstat; 255 ushort mptpr; 256 ulong mdr; 257 uchar rsv7c[0x80]; 258 }; 259 struct { /* system integration timers */ 260 ushort tbscr; 261 uchar rsv8a[2]; 262 ulong tbrefu; 263 ulong tbrefl; 264 uchar rsv8b[0x14]; 265 ushort rtcsc; 266 uchar rsv8c[2]; 267 ulong rtc; 268 ulong rtsec; 269 ulong rtcal; 270 uchar rsv8d[0x10]; 271 ushort piscr; 272 ushort rsv8e; 273 ulong pitc; 274 ulong pitr; 275 uchar rsv8f[0x34]; 276 }; 277 struct { /* 280: clocks and resets */ 278 ulong sccr; 279 ulong plprcr; 280 ulong rsr; 281 uchar rsv9[0x300-0x28c]; 282 }; 283 struct { /* 300: system integration timers keys */ 284 ulong tbscrk; 285 ulong tbrefuk; 286 ulong tbreflk; 287 ulong tbk; 288 uchar rsv10a[0x10]; 289 ulong rtcsck; 290 ulong rtck; 291 ulong rtseck; 292 ulong rtcalk; 293 uchar rsv10b[0x10]; 294 ulong piscrk; 295 ulong pitck; 296 uchar rsv10c[0x38]; 297 }; 298 struct { /* 380: clocks and resets keys */ 299 ulong sccrk; 300 ulong plprcrk; 301 ulong rsrk; 302 uchar rsv11[0x800-0x38C]; 303 }; 304 struct { /* 800: video controller */ 305 ushort vccr; 306 ushort pad11a; 307 uchar vsr; 308 uchar pad11b; 309 uchar vcmr; 310 uchar pad11c; 311 ulong vbcb; 312 ulong pad11d; 313 ulong vfcr0; 314 ulong vfaa0; 315 ulong vfba0; 316 ulong vfcr1; 317 ulong vfaa1; 318 ulong vfba1; 319 uchar rsv11a[0x840-0x828]; 320 }; 321 struct { /* 840: LCD */ 322 ulong lccr; 323 ulong lchcr; 324 ulong lcvcr; 325 ulong rsv11b; 326 ulong lcfaa; 327 ulong lcfba; 328 uchar lcsr; 329 uchar rsv11c[0x860-0x859]; 330 }; 331 struct { /* 860: I2C */ 332 uchar i2mod; 333 uchar rsv12a[3]; 334 uchar i2add; 335 uchar rsv12b[3]; 336 uchar i2brg; 337 uchar rsv12c[3]; 338 uchar i2com; 339 uchar rsv12d[3]; 340 uchar i2cer; 341 uchar rsv12e[3]; 342 uchar i2cmr; 343 uchar rsv12[0x900-0x875]; 344 }; 345 struct { /* 900: DMA */ 346 uchar rsv13[4]; 347 ulong sdar; 348 uchar sdsr; 349 uchar pad1[3]; 350 uchar sdmr; 351 uchar pad2[3]; 352 uchar idsr1; 353 uchar pad3[3]; 354 uchar idmr1; 355 uchar pad4[3]; 356 uchar idsr2; 357 uchar pad5[3]; 358 uchar idmr2; 359 uchar pad6[0x930-0x91D]; 360 }; 361 struct { /* CPM interrupt control */ 362 ushort civr; 363 uchar pad7[0x940-0x932]; 364 ulong cicr; 365 ulong cipr; 366 ulong cimr; 367 ulong cisr; 368 }; 369 struct { /* input/output port */ 370 ushort padir; 371 ushort papar; 372 ushort paodr; 373 ushort padat; 374 uchar pad8[8]; 375 ushort pcdir; 376 ushort pcpar; 377 ushort pcso; 378 ushort pcdat; 379 ushort pcint; 380 uchar pad9[6]; 381 ushort pddir; 382 ushort pdpar; 383 ushort rsv14a; 384 ushort pddat; 385 uchar rsv14[0x980-0x978]; 386 }; 387 struct { /* CPM timers */ 388 ushort tgcr; 389 uchar rsv15a[0x990-0x982]; 390 ushort tmr1; 391 ushort tmr2; 392 ushort trr1; 393 ushort trr2; 394 ushort tcr1; 395 ushort tcr2; 396 ushort tcn1; 397 ushort tcn2; 398 ushort tmr3; 399 ushort tmr4; 400 ushort trr3; 401 ushort trr4; 402 ushort tcr3; 403 ushort tcr4; 404 ushort tcn3; 405 ushort tcn4; 406 ushort ter1; 407 ushort ter2; 408 ushort ter3; 409 ushort ter4; 410 uchar rsv15[0x9C0-0x9B8]; 411 }; 412 struct { /* CPM */ 413 ushort cpcr; 414 uchar res0[2]; 415 ushort rccr; 416 uchar res1; 417 uchar rmds; 418 uchar res2a[4]; 419 ushort rctr1; 420 ushort rctr2; 421 ushort rctr3; 422 ushort rctr4; 423 uchar res2[2]; 424 ushort rter; 425 uchar res3[2]; 426 ushort rtmr; 427 uchar rsv16[0x9F0-0x9DC]; 428 }; 429 union { /* BRG */ 430 struct { 431 ulong brgc1; 432 ulong brgc2; 433 ulong brgc3; 434 ulong brgc4; 435 }; 436 ulong brgc[4]; 437 }; 438 uchar skip0[0xAB2-0xA00]; /* USB, SCC, SMC, SPI: address using cpmdev(CP...)->regs */ 439 struct { /* PIP */ 440 ushort pipc; /* not 823 */ 441 ushort ptpr; /* not 823 */ 442 ulong pbdir; 443 ulong pbpar; 444 uchar pad10[2]; 445 ushort pbodr; 446 ulong pbdat; 447 uchar pad11[0xAE0-0xAC8]; 448 }; 449 struct { /* SI */ 450 ulong simode; 451 uchar sigmr; 452 uchar pad12; 453 uchar sistr; 454 uchar sicmr; 455 uchar pad13[4]; 456 ulong sicr; 457 ulong sirp; 458 uchar pad14[0xB00-0xAF4]; 459 }; 460 ulong vcram[64]; 461 ushort siram[256]; 462 ushort lcdmap[256]; 463 }; 464