1 /* 2 * Memory and machine-specific definitions. Used in C and assembler. 3 */ 4 5 /* 6 * Sizes 7 */ 8 #define BI2BY 8 /* bits per byte */ 9 #define BI2WD 32 /* bits per word */ 10 #define BY2WD 4 /* bytes per word */ 11 #define BY2V 8 /* bytes per double word */ 12 #define BY2PG 4096 /* bytes per page */ 13 #define WD2PG (BY2PG/BY2WD) /* words per page */ 14 #define PGSHIFT 12 /* log(BY2PG) */ 15 #define ROUND(s, sz) (((s)+(sz-1))&~(sz-1)) 16 #define PGROUND(s) ROUND(s, BY2PG) 17 #define BLOCKALIGN 8 18 19 #define MAXMACH 1 /* max # cpus system can run */ 20 21 /* 22 * Time 23 */ 24 #define HZ (20) /* clock frequency */ 25 #define MS2HZ (1000/HZ) /* millisec per clock tick */ 26 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */ 27 #define TK2MS(t) ((((ulong)(t))*1000)/HZ) /* ticks to milliseconds */ 28 #define MS2TK(t) ((((ulong)(t))*HZ)/1000) /* milliseconds to ticks */ 29 30 /* 31 * Virtual addresses: 32 * 33 * We direct map all discovered DRAM and the area twixt 0xe0000000 and 34 * 0xe8000000 used to provide zeros for cache flushing. 35 * 36 * Flash is mapped to 0xb0000000 and special registers are mapped 37 * on demand to areas starting at 0xa0000000. 38 * 39 * The direct mapping is convenient but not necessary. It means 40 * that we don't have to turn on the MMU till well into the 41 * kernel. This can be changed by providing a mapping in l.s 42 * before calling main. 43 */ 44 #define UZERO 0 /* base of user address space */ 45 #define UTZERO (UZERO+BY2PG) /* first address in user text */ 46 #define KZERO 0xC0000000 /* base of kernel address space */ 47 #define KTZERO 0xC0008000 /* first address in kernel text */ 48 #define EMEMZERO 0x90000000 /* 256 meg for add on memory */ 49 #define EMEMTOP 0xA0000000 /* ... */ 50 #define REGZERO 0xA0000000 /* 128 meg for mapspecial regs */ 51 #define REGTOP 0xA8000000 /* ... */ 52 #define FLASHZERO 0xB0000000 /* 128 meg for flash */ 53 #define FLASHTOP 0xB8000000 /* ... */ 54 #define DRAMZERO 0xC0000000 /* 128 meg for dram */ 55 #define DRAMTOP 0xC8000000 /* ... */ 56 #define UCDRAMZERO 0xC8000000 /* 128 meg for dram (uncached/unbuffered) */ 57 #define UCDRAMTOP 0xD0000000 /* ... */ 58 #define NULLZERO 0xE0000000 /* 128 meg for cache flush zeroes */ 59 #define NULLTOP 0xE8000000 /* ... */ 60 #define USTKTOP 0x2000000 /* byte just beyond user stack */ 61 #define USTKSIZE (8*1024*1024) /* size of user stack */ 62 #define TSTKTOP (USTKTOP-USTKSIZE) /* end of new stack in sysexec */ 63 #define TSTKSIZ 100 64 #define MACHADDR (KZERO+0x00001000) 65 #define EVECTORS 0xFFFF0000 /* virt base of exception vectors */ 66 67 #define KSTACK (16*1024) /* Size of kernel stack */ 68 69 #define FLATESIZE (700*1024) /* maximum size of compressed image */ 70 71 /* 72 * Offsets into flash 73 */ 74 #define Flash_bootldr (FLASHZERO+0x0) /* boot loader */ 75 #define Flash_kernel (FLASHZERO+0x10000) /* boot kernel */ 76 #define Flash_tar (FLASHZERO+0x100000) /* tar file containing fs.sac */ 77 78 /* 79 * virtual MMU 80 */ 81 #define PTEMAPMEM (1024*1024) 82 #define PTEPERTAB (PTEMAPMEM/BY2PG) 83 #define SEGMAPSIZE 1984 84 #define SSEGMAPSIZE 16 85 #define PPN(x) ((x)&~(BY2PG-1)) 86 87 /* 88 * SA1110 definitions 89 */ 90 91 /* 92 * memory physical addresses 93 */ 94 #define PHYSFLASH0 0x00000000 95 #define PHYSDRAM0 0xC0000000 96 #define PHYSNULL0 0xE0000000 97 98 /* 99 * peripheral control module physical addresses 100 */ 101 #define USBREGS 0x80000000 /* serial port 0 - USB */ 102 #define UART1REGS 0x80010000 /* serial port 1 - UART */ 103 #define GPCLKREGS 0x80020060 /* serial port 1 - general purpose clock */ 104 #define UART2REGS 0x80030000 /* serial port 2 - low speed IR */ 105 #define HSSPREGS 0x80040060 /* serial port 2 - high speed IR */ 106 #define UART3REGS 0x80050000 /* serial port 3 - RS232 UART */ 107 #define MCPREGS 0x80060000 /* serial port 4 - multimedia comm port */ 108 #define SSPREGS 0x80070060 /* serial port 4 - synchronous serial port */ 109 #define OSTIMERREGS 0x90000000 /* operating system timer registers */ 110 #define POWERREGS 0x90020000 /* power management */ 111 #define GPIOREGS 0x90040000 /* 28 general purpose IO pins */ 112 #define INTRREGS 0x90050000 /* interrupt registers */ 113 #define PPCREGS 0x90060000 /* peripheral pin controller */ 114 #define MEMCONFREGS 0xA0000000 /* memory configuration */ 115 #define LCDREGS 0xB0100000 /* display */ 116 117 /* 118 * PCMCIA addresses 119 */ 120 #define PHYSPCM0REGS 0x20000000 121 #define PYHSPCM0ATTR 0x28000000 122 #define PYHSPCM0MEM 0x2C000000 123 #define PHYSPCM1REGS 0x30000000 124 #define PYHSPCM1ATTR 0x38000000 125 #define PYHSPCM1MEM 0x3C000000 126 127 /* 128 * Program Status Registers 129 */ 130 #define PsrMusr 0x00000010 /* mode */ 131 #define PsrMfiq 0x00000011 132 #define PsrMirq 0x00000012 133 #define PsrMsvc 0x00000013 134 #define PsrMabt 0x00000017 135 #define PsrMund 0x0000001B 136 #define PsrMask 0x0000001F 137 138 #define PsrDfiq 0x00000040 /* disable FIQ interrupts */ 139 #define PsrDirq 0x00000080 /* disable IRQ interrupts */ 140 141 #define PsrV 0x10000000 /* overflow */ 142 #define PsrC 0x20000000 /* carry/borrow/extend */ 143 #define PsrZ 0x40000000 /* zero */ 144 #define PsrN 0x80000000 /* negative/less than */ 145 146 /* 147 * Coprocessors 148 */ 149 #define CpMMU 15 150 #define CpPWR 15 151 152 /* 153 * Internal MMU coprocessor registers 154 */ 155 #define CpCPUID 0 /* R: */ 156 #define CpControl 1 /* R: */ 157 #define CpTTB 2 /* RW: translation table base */ 158 #define CpDAC 3 /* RW: domain access control */ 159 #define CpFSR 5 /* RW: fault status */ 160 #define CpFAR 6 /* RW: fault address */ 161 #define CpCacheFlush 7 /* W: cache flushing, wb draining*/ 162 #define CpTLBFlush 8 /* W: TLB flushing */ 163 #define CpRBFlush 9 /* W: Read Buffer ops */ 164 #define CpPID 13 /* RW: PID for virtual mapping */ 165 #define CpBpt 14 /* W: Breakpoint register */ 166 #define CpTest 15 /* W: Test, Clock and Idle Control */ 167 168 /* 169 * CpControl 170 */ 171 #define CpCmmuena 0x00000001 /* M: MMU enable */ 172 #define CpCalign 0x00000002 /* A: alignment fault enable */ 173 #define CpCdcache 0x00000004 /* C: data cache on */ 174 #define CpCwb 0x00000008 /* W: write buffer turned on */ 175 #define CpCi32 0x00000010 /* P: 32-bit program space */ 176 #define CpCd32 0x00000020 /* D: 32-bit data space */ 177 #define CpCbe 0x00000080 /* B: big-endian operation */ 178 #define CpCsystem 0x00000100 /* S: system permission */ 179 #define CpCrom 0x00000200 /* R: ROM permission */ 180 #define CpCicache 0x00001000 /* I: instruction cache on */ 181 #define CpCvivec 0x00002000 /* X: virtual interrupt vector adjust */ 182 183 /* 184 * fault codes 185 */ 186 #define FCterm 0x2 /* terminal */ 187 #define FCvec 0x0 /* vector */ 188 #define FCalignf 0x1 /* unaligned full word data access */ 189 #define FCalignh 0x3 /* unaligned half word data access */ 190 #define FCl1abort 0xc /* level 1 external abort on translation */ 191 #define FCl2abort 0xe /* level 2 external abort on translation */ 192 #define FCtransSec 0x5 /* section translation */ 193 #define FCtransPage 0x7 /* page translation */ 194 #define FCdomainSec 0x9 /* section domain */ 195 #define FCdomainPage 0x11 /* page domain */ 196 #define FCpermSec 0x9 /* section permissions */ 197 #define FCpermPage 0x11 /* page permissions */ 198 #define FCabortLFSec 0x4 /* external abort on linefetch for section */ 199 #define FCabortLFPage 0x6 /* external abort on linefetch for page */ 200 #define FCabortNLFSec 0x8 /* external abort on non-linefetch for section */ 201 #define FCabortNLFPage 0xa /* external abort on non-linefetch for page */ 202 203 /* 204 * PTE bits used by fault.h. mmu.c translates them to real values. 205 */ 206 #define PTEVALID (1<<0) 207 #define PTERONLY 0 /* this is implied by the absence of PTEWRITE */ 208 #define PTEWRITE (1<<1) 209 #define PTEUNCACHED (1<<2) 210 #define PTEKERNEL (1<<3) /* no user access */ 211 212 /* 213 * H3650 specific definitions 214 */ 215 #define EGPIOREGS 0x49000000 /* Additional GPIO register */ 216