1// Power PC support 2 3defn acidinit() // Called after all the init modules are loaded 4{ 5 bpl = {}; 6 bpid = -1; 7 bpfmt = 'X'; 8 nopstop = 0; 9 bplist = {}; 10 11 srcpath = { 12 "./", 13 "/sys/src/libc/port/", 14 "/sys/src/libc/9sys/", 15 "/sys/src/libc/power/" 16 }; 17 18 srcfiles = {}; // list of loaded files 19 srctext = {}; // the text of the files 20} 21 22// defn stk() // trace 23// { 24// _stk(*PC, *SP, linkreg(0), 0); 25// } 26 27// defn lstk() // trace with locals 28// { 29// _stk(*PC, *SP, linkreg(0), 1); 30// } 31 32defn ustk(ur) 33{ 34 complex Ureg ur; 35 _stk(ur.pc, ur.sp, 0, 0); 36} 37 38defn lustk(ur) 39{ 40 complex Ureg ur; 41 _stk(ur.pc, ur.sp, 0, 1); 42} 43 44defn stk() 45{ 46 ustk(0); 47} 48 49defn lstk() 50{ 51 lustk(0); 52} 53 54defn kstk() 55{ 56 local lab; 57 complex Proc proc; 58 lab = proc.sched; 59 complex Label lab; 60 _stk(lab.pc\X, lab.sp\X, 0, 0); 61} 62 63defn lkstk() 64{ 65 local lab; 66 complex Proc proc; 67 lab = proc.sched; 68 complex Label lab; 69 _stk(lab.pc\X, lab.sp\X, 0, 1); 70} 71 72defn gpr() // print general purpose registers 73{ 74 print("SP\t", *SP, " R2\t", *R2, " R3\t", *R3, "\n"); 75 print("R4\t", *R4, " R5\t", *R5, " R6\t", *R6, "\n"); 76 print("R7\t", *R7, " R8\t", *R8, " R9\t", *R9, "\n"); 77 print("R10\t", *R10, " R11\t", *R11, " R12\t", *R12, "\n"); 78 print("R13\t", *R13, " R14\t", *R14, " R15\t", *R15, "\n"); 79 print("R16\t", *R16, " R17\t", *R17, " R18\t", *R18, "\n"); 80 print("R19\t", *R19, " R20\t", *R20, " R21\t", *R21, "\n"); 81 print("R22\t", *R22, " R23\t", *R23, " R24\t", *R24, "\n"); 82 print("R25\t", *R25, " R26\t", *R26, " R27\t", *R27, "\n"); 83 print("R28\t", *R28, " R29\t", *R29, " R30\t", *R30, "\n"); 84 print("R31\t", *R31, "\n"); 85} 86 87defn Fpr() 88{ 89 fpr(); 90} 91 92defn fpr() 93{ 94 print("F0\t", *fmt(F0, 'G'), "\tF1\t", *fmt(F1, 'G'), "\n"); 95 print("F2\t", *fmt(F2, 'G'), "\tF3\t", *fmt(F3, 'G'), "\n"); 96 print("F4\t", *fmt(F4, 'G'), "\tF5\t", *fmt(F5, 'G'), "\n"); 97 print("F6\t", *fmt(F6, 'G'), "\tF7\t", *fmt(F7, 'G'), "\n"); 98 print("F8\t", *fmt(F8, 'G'), "\tF9\t", *fmt(F9, 'G'), "\n"); 99 print("F10\t", *fmt(F10, 'G'), "\tF11\t", *fmt(F11, 'G'), "\n"); 100 print("F12\t", *fmt(F12, 'G'), "\tF13\t", *fmt(F13, 'G'), "\n"); 101 print("F14\t", *fmt(F14, 'G'), "\tF15\t", *fmt(F15, 'G'), "\n"); 102 print("F16\t", *fmt(F16, 'G'), "\tF17\t", *fmt(F17, 'G'), "\n"); 103 print("F18\t", *fmt(F18, 'G'), "\tF19\t", *fmt(F19, 'G'), "\n"); 104 print("F20\t", *fmt(F20, 'G'), "\tF21\t", *fmt(F21, 'G'), "\n"); 105 print("F22\t", *fmt(F22, 'G'), "\tF23\t", *fmt(F23, 'G'), "\n"); 106 print("F24\t", *fmt(F24, 'G'), "\tF25\t", *fmt(F25, 'G'), "\n"); 107 print("F26\t", *fmt(F26, 'G'), "\tF27\t", *fmt(F27, 'G'), "\n"); 108 print("F28\t", *fmt(F28, 'G'), "\tF29\t", *fmt(F29, 'G'), "\n"); 109 print("F30\t", *fmt(F30, 'G'), "\tF31\t", *fmt(F31, 'G'), "\n"); 110} 111 112defn spr() // print special processor registers 113{ 114 local pc, link, cause; 115 116 pc = *PC; 117 print("PC\t", pc, " ", fmt(pc, 'a'), " "); 118 pfl(pc); 119 120 link = *R31; 121 print("SP\t", *SP, "\tLINK\t", link, " ", fmt(link, 'a'), " "); 122 pfl(link); 123 124 cause = *CAUSE; 125 print("SRR1\t", *SRR1, "\tCAUSE\t", cause, " ", reason(cause), "\n"); 126 print("LR\t", *LR, "\tCR\t", *CR, "\n"); 127 128 print("XER\t", *XER, "\tCTR\t", *CTR, "\n"); 129} 130 131defn regs() // print all registers 132{ 133 spr(); 134 gpr(); 135} 136 137 138defn linkreg(addr) 139{ 140 return *LR; 141} 142 143sizeofUreg = 160; 144aggr Ureg 145{ 146 'U' 0 cause; 147 'U' 4 status; 148 'U' 8 pc; 149 'U' 12 pad; 150 'U' 16 lr; 151 'U' 20 cr; 152 'U' 24 xer; 153 'U' 28 ctr; 154 'U' 32 r0; 155 'U' 36 sp; 156 'U' 40 r2; 157 'U' 44 r3; 158 'U' 48 r4; 159 'U' 52 r5; 160 'U' 56 r6; 161 'U' 60 r7; 162 'U' 64 r8; 163 'U' 68 r9; 164 'U' 72 r10; 165 'U' 76 r11; 166 'U' 80 r12; 167 'U' 84 r13; 168 'U' 88 r14; 169 'U' 92 r15; 170 'U' 96 r16; 171 'U' 100 r17; 172 'U' 104 r18; 173 'U' 108 r19; 174 'U' 112 r20; 175 'U' 116 r21; 176 'U' 120 r22; 177 'U' 124 r23; 178 'U' 128 r24; 179 'U' 132 r25; 180 'U' 136 r26; 181 'U' 140 r27; 182 'U' 144 r28; 183 'U' 148 r29; 184 'U' 152 r30; 185 'U' 156 r31; 186}; 187 188defn 189Ureg(addr) { 190 complex Ureg addr; 191 print(" cause ", addr.cause, "\n"); 192 print(" status ", addr.status, "\n"); 193 print(" pc ", addr.pc, "\n"); 194 print(" pad ", addr.pad, "\n"); 195 print(" lr ", addr.lr, "\n"); 196 print(" cr ", addr.cr, "\n"); 197 print(" xer ", addr.xer, "\n"); 198 print(" ctr ", addr.ctr, "\n"); 199 print(" r0 ", addr.r0, "\n"); 200 print(" sp ", addr.sp, "\n"); 201 print(" r2 ", addr.r2, "\n"); 202 print(" r3 ", addr.r3, "\n"); 203 print(" r4 ", addr.r4, "\n"); 204 print(" r5 ", addr.r5, "\n"); 205 print(" r6 ", addr.r6, "\n"); 206 print(" r7 ", addr.r7, "\n"); 207 print(" r8 ", addr.r8, "\n"); 208 print(" r9 ", addr.r9, "\n"); 209 print(" r10 ", addr.r10, "\n"); 210 print(" r11 ", addr.r11, "\n"); 211 print(" r12 ", addr.r12, "\n"); 212 print(" r13 ", addr.r13, "\n"); 213 print(" r14 ", addr.r14, "\n"); 214 print(" r15 ", addr.r15, "\n"); 215 print(" r16 ", addr.r16, "\n"); 216 print(" r17 ", addr.r17, "\n"); 217 print(" r18 ", addr.r18, "\n"); 218 print(" r19 ", addr.r19, "\n"); 219 print(" r20 ", addr.r20, "\n"); 220 print(" r21 ", addr.r21, "\n"); 221 print(" r22 ", addr.r22, "\n"); 222 print(" r23 ", addr.r23, "\n"); 223 print(" r24 ", addr.r24, "\n"); 224 print(" r25 ", addr.r25, "\n"); 225 print(" r26 ", addr.r26, "\n"); 226 print(" r27 ", addr.r27, "\n"); 227 print(" r28 ", addr.r28, "\n"); 228 print(" r29 ", addr.r29, "\n"); 229 print(" r30 ", addr.r30, "\n"); 230 print(" r31 ", addr.r31, "\n"); 231}; 232 233print("/sys/lib/acid/power"); 234